Mercurial > hg > graal-jvmci-8
annotate src/cpu/sparc/vm/sparc.ad @ 3854:1af104d6cf99
7079329: Adjust allocation prefetching for T4
Summary: on T4 2 BIS instructions should be issued to prefetch 64 bytes
Reviewed-by: iveresov, phh, twisti
| author | kvn |
|---|---|
| date | Tue, 16 Aug 2011 16:59:46 -0700 |
| parents | 95134e034042 |
| children | bd87c0dcaba5 |
| rev | line source |
|---|---|
| 0 | 1 // |
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2 // Copyright (c) 1998, 2011, Oracle and/or its affiliates. All rights reserved. |
| 0 | 3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 4 // | |
| 5 // This code is free software; you can redistribute it and/or modify it | |
| 6 // under the terms of the GNU General Public License version 2 only, as | |
| 7 // published by the Free Software Foundation. | |
| 8 // | |
| 9 // This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 // version 2 for more details (a copy is included in the LICENSE file that | |
| 13 // accompanied this code). | |
| 14 // | |
| 15 // You should have received a copy of the GNU General Public License version | |
| 16 // 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 // | |
|
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19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 // or visit www.oracle.com if you need additional information or have any |
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21 // questions. |
| 0 | 22 // |
| 23 // | |
| 24 | |
| 25 // SPARC Architecture Description File | |
| 26 | |
| 27 //----------REGISTER DEFINITION BLOCK------------------------------------------ | |
| 28 // This information is used by the matcher and the register allocator to | |
| 29 // describe individual registers and classes of registers within the target | |
| 30 // archtecture. | |
| 31 register %{ | |
| 32 //----------Architecture Description Register Definitions---------------------- | |
| 33 // General Registers | |
| 34 // "reg_def" name ( register save type, C convention save type, | |
| 35 // ideal register type, encoding, vm name ); | |
| 36 // Register Save Types: | |
| 37 // | |
| 38 // NS = No-Save: The register allocator assumes that these registers | |
| 39 // can be used without saving upon entry to the method, & | |
| 40 // that they do not need to be saved at call sites. | |
| 41 // | |
| 42 // SOC = Save-On-Call: The register allocator assumes that these registers | |
| 43 // can be used without saving upon entry to the method, | |
| 44 // but that they must be saved at call sites. | |
| 45 // | |
| 46 // SOE = Save-On-Entry: The register allocator assumes that these registers | |
| 47 // must be saved before using them upon entry to the | |
| 48 // method, but they do not need to be saved at call | |
| 49 // sites. | |
| 50 // | |
| 51 // AS = Always-Save: The register allocator assumes that these registers | |
| 52 // must be saved before using them upon entry to the | |
| 53 // method, & that they must be saved at call sites. | |
| 54 // | |
| 55 // Ideal Register Type is used to determine how to save & restore a | |
| 56 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get | |
| 57 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI. | |
| 58 // | |
| 59 // The encoding number is the actual bit-pattern placed into the opcodes. | |
| 60 | |
| 61 | |
| 62 // ---------------------------- | |
| 63 // Integer/Long Registers | |
| 64 // ---------------------------- | |
| 65 | |
| 66 // Need to expose the hi/lo aspect of 64-bit registers | |
| 67 // This register set is used for both the 64-bit build and | |
| 68 // the 32-bit build with 1-register longs. | |
| 69 | |
| 70 // Global Registers 0-7 | |
| 71 reg_def R_G0H( NS, NS, Op_RegI,128, G0->as_VMReg()->next()); | |
| 72 reg_def R_G0 ( NS, NS, Op_RegI, 0, G0->as_VMReg()); | |
| 73 reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next()); | |
| 74 reg_def R_G1 (SOC, SOC, Op_RegI, 1, G1->as_VMReg()); | |
| 75 reg_def R_G2H( NS, NS, Op_RegI,130, G2->as_VMReg()->next()); | |
| 76 reg_def R_G2 ( NS, NS, Op_RegI, 2, G2->as_VMReg()); | |
| 77 reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next()); | |
| 78 reg_def R_G3 (SOC, SOC, Op_RegI, 3, G3->as_VMReg()); | |
| 79 reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next()); | |
| 80 reg_def R_G4 (SOC, SOC, Op_RegI, 4, G4->as_VMReg()); | |
| 81 reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next()); | |
| 82 reg_def R_G5 (SOC, SOC, Op_RegI, 5, G5->as_VMReg()); | |
| 83 reg_def R_G6H( NS, NS, Op_RegI,134, G6->as_VMReg()->next()); | |
| 84 reg_def R_G6 ( NS, NS, Op_RegI, 6, G6->as_VMReg()); | |
| 85 reg_def R_G7H( NS, NS, Op_RegI,135, G7->as_VMReg()->next()); | |
| 86 reg_def R_G7 ( NS, NS, Op_RegI, 7, G7->as_VMReg()); | |
| 87 | |
| 88 // Output Registers 0-7 | |
| 89 reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next()); | |
| 90 reg_def R_O0 (SOC, SOC, Op_RegI, 8, O0->as_VMReg()); | |
| 91 reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next()); | |
| 92 reg_def R_O1 (SOC, SOC, Op_RegI, 9, O1->as_VMReg()); | |
| 93 reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next()); | |
| 94 reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg()); | |
| 95 reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next()); | |
| 96 reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg()); | |
| 97 reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next()); | |
| 98 reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg()); | |
| 99 reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next()); | |
| 100 reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg()); | |
| 101 reg_def R_SPH( NS, NS, Op_RegI,142, SP->as_VMReg()->next()); | |
| 102 reg_def R_SP ( NS, NS, Op_RegI, 14, SP->as_VMReg()); | |
| 103 reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next()); | |
| 104 reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg()); | |
| 105 | |
| 106 // Local Registers 0-7 | |
| 107 reg_def R_L0H( NS, NS, Op_RegI,144, L0->as_VMReg()->next()); | |
| 108 reg_def R_L0 ( NS, NS, Op_RegI, 16, L0->as_VMReg()); | |
| 109 reg_def R_L1H( NS, NS, Op_RegI,145, L1->as_VMReg()->next()); | |
| 110 reg_def R_L1 ( NS, NS, Op_RegI, 17, L1->as_VMReg()); | |
| 111 reg_def R_L2H( NS, NS, Op_RegI,146, L2->as_VMReg()->next()); | |
| 112 reg_def R_L2 ( NS, NS, Op_RegI, 18, L2->as_VMReg()); | |
| 113 reg_def R_L3H( NS, NS, Op_RegI,147, L3->as_VMReg()->next()); | |
| 114 reg_def R_L3 ( NS, NS, Op_RegI, 19, L3->as_VMReg()); | |
| 115 reg_def R_L4H( NS, NS, Op_RegI,148, L4->as_VMReg()->next()); | |
| 116 reg_def R_L4 ( NS, NS, Op_RegI, 20, L4->as_VMReg()); | |
| 117 reg_def R_L5H( NS, NS, Op_RegI,149, L5->as_VMReg()->next()); | |
| 118 reg_def R_L5 ( NS, NS, Op_RegI, 21, L5->as_VMReg()); | |
| 119 reg_def R_L6H( NS, NS, Op_RegI,150, L6->as_VMReg()->next()); | |
| 120 reg_def R_L6 ( NS, NS, Op_RegI, 22, L6->as_VMReg()); | |
| 121 reg_def R_L7H( NS, NS, Op_RegI,151, L7->as_VMReg()->next()); | |
| 122 reg_def R_L7 ( NS, NS, Op_RegI, 23, L7->as_VMReg()); | |
| 123 | |
| 124 // Input Registers 0-7 | |
| 125 reg_def R_I0H( NS, NS, Op_RegI,152, I0->as_VMReg()->next()); | |
| 126 reg_def R_I0 ( NS, NS, Op_RegI, 24, I0->as_VMReg()); | |
| 127 reg_def R_I1H( NS, NS, Op_RegI,153, I1->as_VMReg()->next()); | |
| 128 reg_def R_I1 ( NS, NS, Op_RegI, 25, I1->as_VMReg()); | |
| 129 reg_def R_I2H( NS, NS, Op_RegI,154, I2->as_VMReg()->next()); | |
| 130 reg_def R_I2 ( NS, NS, Op_RegI, 26, I2->as_VMReg()); | |
| 131 reg_def R_I3H( NS, NS, Op_RegI,155, I3->as_VMReg()->next()); | |
| 132 reg_def R_I3 ( NS, NS, Op_RegI, 27, I3->as_VMReg()); | |
| 133 reg_def R_I4H( NS, NS, Op_RegI,156, I4->as_VMReg()->next()); | |
| 134 reg_def R_I4 ( NS, NS, Op_RegI, 28, I4->as_VMReg()); | |
| 135 reg_def R_I5H( NS, NS, Op_RegI,157, I5->as_VMReg()->next()); | |
| 136 reg_def R_I5 ( NS, NS, Op_RegI, 29, I5->as_VMReg()); | |
| 137 reg_def R_FPH( NS, NS, Op_RegI,158, FP->as_VMReg()->next()); | |
| 138 reg_def R_FP ( NS, NS, Op_RegI, 30, FP->as_VMReg()); | |
| 139 reg_def R_I7H( NS, NS, Op_RegI,159, I7->as_VMReg()->next()); | |
| 140 reg_def R_I7 ( NS, NS, Op_RegI, 31, I7->as_VMReg()); | |
| 141 | |
| 142 // ---------------------------- | |
| 143 // Float/Double Registers | |
| 144 // ---------------------------- | |
| 145 | |
| 146 // Float Registers | |
| 147 reg_def R_F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg()); | |
| 148 reg_def R_F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg()); | |
| 149 reg_def R_F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg()); | |
| 150 reg_def R_F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg()); | |
| 151 reg_def R_F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg()); | |
| 152 reg_def R_F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg()); | |
| 153 reg_def R_F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg()); | |
| 154 reg_def R_F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg()); | |
| 155 reg_def R_F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg()); | |
| 156 reg_def R_F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg()); | |
| 157 reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg()); | |
| 158 reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg()); | |
| 159 reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg()); | |
| 160 reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg()); | |
| 161 reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg()); | |
| 162 reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg()); | |
| 163 reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg()); | |
| 164 reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg()); | |
| 165 reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg()); | |
| 166 reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg()); | |
| 167 reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg()); | |
| 168 reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg()); | |
| 169 reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg()); | |
| 170 reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg()); | |
| 171 reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg()); | |
| 172 reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg()); | |
| 173 reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg()); | |
| 174 reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg()); | |
| 175 reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg()); | |
| 176 reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg()); | |
| 177 reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg()); | |
| 178 reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg()); | |
| 179 | |
| 180 // Double Registers | |
| 181 // The rules of ADL require that double registers be defined in pairs. | |
| 182 // Each pair must be two 32-bit values, but not necessarily a pair of | |
| 183 // single float registers. In each pair, ADLC-assigned register numbers | |
| 184 // must be adjacent, with the lower number even. Finally, when the | |
| 185 // CPU stores such a register pair to memory, the word associated with | |
| 186 // the lower ADLC-assigned number must be stored to the lower address. | |
| 187 | |
| 188 // These definitions specify the actual bit encodings of the sparc | |
| 189 // double fp register numbers. FloatRegisterImpl in register_sparc.hpp | |
| 190 // wants 0-63, so we have to convert every time we want to use fp regs | |
| 191 // with the macroassembler, using reg_to_DoubleFloatRegister_object(). | |
| 605 | 192 // 255 is a flag meaning "don't go here". |
| 0 | 193 // I believe we can't handle callee-save doubles D32 and up until |
| 194 // the place in the sparc stack crawler that asserts on the 255 is | |
| 195 // fixed up. | |
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196 reg_def R_D32 (SOC, SOC, Op_RegD, 1, F32->as_VMReg()); |
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197 reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg()->next()); |
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198 reg_def R_D34 (SOC, SOC, Op_RegD, 3, F34->as_VMReg()); |
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199 reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg()->next()); |
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200 reg_def R_D36 (SOC, SOC, Op_RegD, 5, F36->as_VMReg()); |
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201 reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg()->next()); |
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202 reg_def R_D38 (SOC, SOC, Op_RegD, 7, F38->as_VMReg()); |
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203 reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg()->next()); |
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204 reg_def R_D40 (SOC, SOC, Op_RegD, 9, F40->as_VMReg()); |
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205 reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg()->next()); |
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206 reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg()); |
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207 reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg()->next()); |
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208 reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg()); |
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209 reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg()->next()); |
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210 reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg()); |
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211 reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg()->next()); |
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212 reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg()); |
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213 reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg()->next()); |
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214 reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg()); |
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215 reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg()->next()); |
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216 reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg()); |
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217 reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg()->next()); |
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218 reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg()); |
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219 reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg()->next()); |
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220 reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg()); |
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221 reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg()->next()); |
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222 reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg()); |
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223 reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg()->next()); |
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224 reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg()); |
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225 reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg()->next()); |
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226 reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg()); |
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227 reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg()->next()); |
| 0 | 228 |
| 229 | |
| 230 // ---------------------------- | |
| 231 // Special Registers | |
| 232 // Condition Codes Flag Registers | |
| 233 // I tried to break out ICC and XCC but it's not very pretty. | |
| 234 // Every Sparc instruction which defs/kills one also kills the other. | |
| 235 // Hence every compare instruction which defs one kind of flags ends | |
| 236 // up needing a kill of the other. | |
| 237 reg_def CCR (SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad()); | |
| 238 | |
| 239 reg_def FCC0(SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad()); | |
| 240 reg_def FCC1(SOC, SOC, Op_RegFlags, 1, VMRegImpl::Bad()); | |
| 241 reg_def FCC2(SOC, SOC, Op_RegFlags, 2, VMRegImpl::Bad()); | |
| 242 reg_def FCC3(SOC, SOC, Op_RegFlags, 3, VMRegImpl::Bad()); | |
| 243 | |
| 244 // ---------------------------- | |
| 245 // Specify the enum values for the registers. These enums are only used by the | |
| 246 // OptoReg "class". We can convert these enum values at will to VMReg when needed | |
| 247 // for visibility to the rest of the vm. The order of this enum influences the | |
| 248 // register allocator so having the freedom to set this order and not be stuck | |
| 249 // with the order that is natural for the rest of the vm is worth it. | |
| 250 alloc_class chunk0( | |
| 251 R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H, | |
| 252 R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H, | |
| 253 R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H, | |
| 254 R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H); | |
| 255 | |
| 256 // Note that a register is not allocatable unless it is also mentioned | |
| 257 // in a widely-used reg_class below. Thus, R_G7 and R_G0 are outside i_reg. | |
| 258 | |
| 259 alloc_class chunk1( | |
| 260 // The first registers listed here are those most likely to be used | |
| 261 // as temporaries. We move F0..F7 away from the front of the list, | |
| 262 // to reduce the likelihood of interferences with parameters and | |
| 263 // return values. Likewise, we avoid using F0/F1 for parameters, | |
| 264 // since they are used for return values. | |
| 265 // This FPU fine-tuning is worth about 1% on the SPEC geomean. | |
| 266 R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, | |
| 267 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23, | |
| 268 R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31, | |
| 269 R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values | |
| 270 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x, | |
| 271 R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x, | |
| 272 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x, | |
| 273 R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x); | |
| 274 | |
| 275 alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3); | |
| 276 | |
| 277 //----------Architecture Description Register Classes-------------------------- | |
| 278 // Several register classes are automatically defined based upon information in | |
| 279 // this architecture description. | |
| 280 // 1) reg_class inline_cache_reg ( as defined in frame section ) | |
| 281 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section ) | |
| 282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ ) | |
| 283 // | |
| 284 | |
| 285 // G0 is not included in integer class since it has special meaning. | |
| 286 reg_class g0_reg(R_G0); | |
| 287 | |
| 288 // ---------------------------- | |
| 289 // Integer Register Classes | |
| 290 // ---------------------------- | |
| 291 // Exclusions from i_reg: | |
| 292 // R_G0: hardwired zero | |
| 293 // R_G2: reserved by HotSpot to the TLS register (invariant within Java) | |
| 294 // R_G6: reserved by Solaris ABI to tools | |
| 295 // R_G7: reserved by Solaris ABI to libthread | |
| 296 // R_O7: Used as a temp in many encodings | |
| 297 reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); | |
| 298 | |
| 299 // Class for all integer registers, except the G registers. This is used for | |
| 300 // encodings which use G registers as temps. The regular inputs to such | |
| 301 // instructions use a "notemp_" prefix, as a hack to ensure that the allocator | |
| 302 // will not put an input into a temp register. | |
| 303 reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); | |
| 304 | |
| 305 reg_class g1_regI(R_G1); | |
| 306 reg_class g3_regI(R_G3); | |
| 307 reg_class g4_regI(R_G4); | |
| 308 reg_class o0_regI(R_O0); | |
| 309 reg_class o7_regI(R_O7); | |
| 310 | |
| 311 // ---------------------------- | |
| 312 // Pointer Register Classes | |
| 313 // ---------------------------- | |
| 314 #ifdef _LP64 | |
| 315 // 64-bit build means 64-bit pointers means hi/lo pairs | |
| 316 reg_class ptr_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5, | |
| 317 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, | |
| 318 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, | |
| 319 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 ); | |
| 320 // Lock encodings use G3 and G4 internally | |
| 321 reg_class lock_ptr_reg( R_G1H,R_G1, R_G5H,R_G5, | |
| 322 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, | |
| 323 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, | |
| 324 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 ); | |
| 325 // Special class for storeP instructions, which can store SP or RPC to TLS. | |
| 326 // It is also used for memory addressing, allowing direct TLS addressing. | |
| 327 reg_class sp_ptr_reg( R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5, | |
| 328 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP, | |
| 329 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, | |
| 330 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP ); | |
| 331 // R_L7 is the lowest-priority callee-save (i.e., NS) register | |
| 332 // We use it to save R_G2 across calls out of Java. | |
| 333 reg_class l7_regP(R_L7H,R_L7); | |
| 334 | |
| 335 // Other special pointer regs | |
| 336 reg_class g1_regP(R_G1H,R_G1); | |
| 337 reg_class g2_regP(R_G2H,R_G2); | |
| 338 reg_class g3_regP(R_G3H,R_G3); | |
| 339 reg_class g4_regP(R_G4H,R_G4); | |
| 340 reg_class g5_regP(R_G5H,R_G5); | |
| 341 reg_class i0_regP(R_I0H,R_I0); | |
| 342 reg_class o0_regP(R_O0H,R_O0); | |
| 343 reg_class o1_regP(R_O1H,R_O1); | |
| 344 reg_class o2_regP(R_O2H,R_O2); | |
| 345 reg_class o7_regP(R_O7H,R_O7); | |
| 346 | |
| 347 #else // _LP64 | |
| 348 // 32-bit build means 32-bit pointers means 1 register. | |
| 349 reg_class ptr_reg( R_G1, R_G3,R_G4,R_G5, | |
| 350 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5, | |
| 351 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, | |
| 352 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); | |
| 353 // Lock encodings use G3 and G4 internally | |
| 354 reg_class lock_ptr_reg(R_G1, R_G5, | |
| 355 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5, | |
| 356 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, | |
| 357 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); | |
| 358 // Special class for storeP instructions, which can store SP or RPC to TLS. | |
| 359 // It is also used for memory addressing, allowing direct TLS addressing. | |
| 360 reg_class sp_ptr_reg( R_G1,R_G2,R_G3,R_G4,R_G5, | |
| 361 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_SP, | |
| 362 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, | |
| 363 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5,R_FP); | |
| 364 // R_L7 is the lowest-priority callee-save (i.e., NS) register | |
| 365 // We use it to save R_G2 across calls out of Java. | |
| 366 reg_class l7_regP(R_L7); | |
| 367 | |
| 368 // Other special pointer regs | |
| 369 reg_class g1_regP(R_G1); | |
| 370 reg_class g2_regP(R_G2); | |
| 371 reg_class g3_regP(R_G3); | |
| 372 reg_class g4_regP(R_G4); | |
| 373 reg_class g5_regP(R_G5); | |
| 374 reg_class i0_regP(R_I0); | |
| 375 reg_class o0_regP(R_O0); | |
| 376 reg_class o1_regP(R_O1); | |
| 377 reg_class o2_regP(R_O2); | |
| 378 reg_class o7_regP(R_O7); | |
| 379 #endif // _LP64 | |
| 380 | |
| 381 | |
| 382 // ---------------------------- | |
| 383 // Long Register Classes | |
| 384 // ---------------------------- | |
| 385 // Longs in 1 register. Aligned adjacent hi/lo pairs. | |
| 386 // Note: O7 is never in this class; it is sometimes used as an encoding temp. | |
| 387 reg_class long_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5 | |
| 388 ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5 | |
| 389 #ifdef _LP64 | |
| 390 // 64-bit, longs in 1 register: use all 64-bit integer registers | |
| 391 // 32-bit, longs in 1 register: cannot use I's and L's. Restrict to O's and G's. | |
| 392 ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7 | |
| 393 ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 | |
| 394 #endif // _LP64 | |
| 395 ); | |
| 396 | |
| 397 reg_class g1_regL(R_G1H,R_G1); | |
|
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398 reg_class g3_regL(R_G3H,R_G3); |
| 0 | 399 reg_class o2_regL(R_O2H,R_O2); |
| 400 reg_class o7_regL(R_O7H,R_O7); | |
| 401 | |
| 402 // ---------------------------- | |
| 403 // Special Class for Condition Code Flags Register | |
| 404 reg_class int_flags(CCR); | |
| 405 reg_class float_flags(FCC0,FCC1,FCC2,FCC3); | |
| 406 reg_class float_flag0(FCC0); | |
| 407 | |
| 408 | |
| 409 // ---------------------------- | |
| 410 // Float Point Register Classes | |
| 411 // ---------------------------- | |
| 412 // Skip F30/F31, they are reserved for mem-mem copies | |
| 413 reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29); | |
| 414 | |
| 415 // Paired floating point registers--they show up in the same order as the floats, | |
| 416 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs. | |
| 417 reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, | |
| 418 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29, | |
| 419 /* Use extra V9 double registers; this AD file does not support V8 */ | |
| 420 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x, | |
| 421 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x | |
| 422 ); | |
| 423 | |
| 424 // Paired floating point registers--they show up in the same order as the floats, | |
| 425 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs. | |
| 426 // This class is usable for mis-aligned loads as happen in I2C adapters. | |
| 427 reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, | |
| 3804 | 428 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29); |
| 0 | 429 %} |
| 430 | |
| 431 //----------DEFINITION BLOCK--------------------------------------------------- | |
| 432 // Define name --> value mappings to inform the ADLC of an integer valued name | |
| 433 // Current support includes integer values in the range [0, 0x7FFFFFFF] | |
| 434 // Format: | |
| 435 // int_def <name> ( <int_value>, <expression>); | |
| 436 // Generated Code in ad_<arch>.hpp | |
| 437 // #define <name> (<expression>) | |
| 438 // // value == <int_value> | |
| 439 // Generated code in ad_<arch>.cpp adlc_verification() | |
| 440 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>"); | |
| 441 // | |
| 442 definitions %{ | |
| 443 // The default cost (of an ALU instruction). | |
| 444 int_def DEFAULT_COST ( 100, 100); | |
| 445 int_def HUGE_COST (1000000, 1000000); | |
| 446 | |
| 447 // Memory refs are twice as expensive as run-of-the-mill. | |
| 448 int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2); | |
| 449 | |
| 450 // Branches are even more expensive. | |
| 451 int_def BRANCH_COST ( 300, DEFAULT_COST * 3); | |
| 452 int_def CALL_COST ( 300, DEFAULT_COST * 3); | |
| 453 %} | |
| 454 | |
| 455 | |
| 456 //----------SOURCE BLOCK------------------------------------------------------- | |
| 457 // This is a block of C++ code which provides values, functions, and | |
| 458 // definitions necessary in the rest of the architecture description | |
| 459 source_hpp %{ | |
| 460 // Must be visible to the DFA in dfa_sparc.cpp | |
| 461 extern bool can_branch_register( Node *bol, Node *cmp ); | |
| 462 | |
| 463 // Macros to extract hi & lo halves from a long pair. | |
| 464 // G0 is not part of any long pair, so assert on that. | |
| 605 | 465 // Prevents accidentally using G1 instead of G0. |
| 0 | 466 #define LONG_HI_REG(x) (x) |
| 467 #define LONG_LO_REG(x) (x) | |
| 468 | |
| 469 %} | |
| 470 | |
| 471 source %{ | |
| 472 #define __ _masm. | |
| 473 | |
| 474 // tertiary op of a LoadP or StoreP encoding | |
| 475 #define REGP_OP true | |
| 476 | |
| 477 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding); | |
| 478 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding); | |
| 479 static Register reg_to_register_object(int register_encoding); | |
| 480 | |
| 481 // Used by the DFA in dfa_sparc.cpp. | |
| 482 // Check for being able to use a V9 branch-on-register. Requires a | |
| 483 // compare-vs-zero, equal/not-equal, of a value which was zero- or sign- | |
| 484 // extended. Doesn't work following an integer ADD, for example, because of | |
| 485 // overflow (-1 incremented yields 0 plus a carry in the high-order word). On | |
| 486 // 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and | |
| 487 // replace them with zero, which could become sign-extension in a different OS | |
| 488 // release. There's no obvious reason why an interrupt will ever fill these | |
| 489 // bits with non-zero junk (the registers are reloaded with standard LD | |
| 490 // instructions which either zero-fill or sign-fill). | |
| 491 bool can_branch_register( Node *bol, Node *cmp ) { | |
| 492 if( !BranchOnRegister ) return false; | |
| 493 #ifdef _LP64 | |
| 494 if( cmp->Opcode() == Op_CmpP ) | |
| 495 return true; // No problems with pointer compares | |
| 496 #endif | |
| 497 if( cmp->Opcode() == Op_CmpL ) | |
| 498 return true; // No problems with long compares | |
| 499 | |
| 500 if( !SparcV9RegsHiBitsZero ) return false; | |
| 501 if( bol->as_Bool()->_test._test != BoolTest::ne && | |
| 502 bol->as_Bool()->_test._test != BoolTest::eq ) | |
| 503 return false; | |
| 504 | |
| 505 // Check for comparing against a 'safe' value. Any operation which | |
| 506 // clears out the high word is safe. Thus, loads and certain shifts | |
| 507 // are safe, as are non-negative constants. Any operation which | |
| 508 // preserves zero bits in the high word is safe as long as each of its | |
| 509 // inputs are safe. Thus, phis and bitwise booleans are safe if their | |
| 510 // inputs are safe. At present, the only important case to recognize | |
| 511 // seems to be loads. Constants should fold away, and shifts & | |
| 512 // logicals can use the 'cc' forms. | |
| 513 Node *x = cmp->in(1); | |
| 514 if( x->is_Load() ) return true; | |
| 515 if( x->is_Phi() ) { | |
| 516 for( uint i = 1; i < x->req(); i++ ) | |
| 517 if( !x->in(i)->is_Load() ) | |
| 518 return false; | |
| 519 return true; | |
| 520 } | |
| 521 return false; | |
| 522 } | |
| 523 | |
| 524 // **************************************************************************** | |
| 525 | |
| 526 // REQUIRED FUNCTIONALITY | |
| 527 | |
| 528 // !!!!! Special hack to get all type of calls to specify the byte offset | |
| 529 // from the start of the call to the point where the return address | |
| 530 // will point. | |
| 531 // The "return address" is the address of the call instruction, plus 8. | |
| 532 | |
| 533 int MachCallStaticJavaNode::ret_addr_offset() { | |
| 1567 | 534 int offset = NativeCall::instruction_size; // call; delay slot |
| 535 if (_method_handle_invoke) | |
| 536 offset += 4; // restore SP | |
| 537 return offset; | |
| 0 | 538 } |
| 539 | |
| 540 int MachCallDynamicJavaNode::ret_addr_offset() { | |
| 541 int vtable_index = this->_vtable_index; | |
| 542 if (vtable_index < 0) { | |
| 543 // must be invalid_vtable_index, not nonvirtual_vtable_index | |
| 544 assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value"); | |
| 545 return (NativeMovConstReg::instruction_size + | |
| 546 NativeCall::instruction_size); // sethi; setlo; call; delay slot | |
| 547 } else { | |
| 548 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); | |
| 549 int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size(); | |
| 550 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes(); | |
|
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551 int klass_load_size; |
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552 if (UseCompressedOops) { |
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553 assert(Universe::heap() != NULL, "java heap should be initialized"); |
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554 if (Universe::narrow_oop_base() == NULL) |
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555 klass_load_size = 2*BytesPerInstWord; // see MacroAssembler::load_klass() |
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556 else |
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557 klass_load_size = 3*BytesPerInstWord; |
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558 } else { |
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559 klass_load_size = 1*BytesPerInstWord; |
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560 } |
| 0 | 561 if( Assembler::is_simm13(v_off) ) { |
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562 return klass_load_size + |
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563 (2*BytesPerInstWord + // ld_ptr, ld_ptr |
| 0 | 564 NativeCall::instruction_size); // call; delay slot |
| 565 } else { | |
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566 return klass_load_size + |
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567 (4*BytesPerInstWord + // set_hi, set, ld_ptr, ld_ptr |
| 0 | 568 NativeCall::instruction_size); // call; delay slot |
| 569 } | |
| 570 } | |
| 571 } | |
| 572 | |
| 573 int MachCallRuntimeNode::ret_addr_offset() { | |
| 574 #ifdef _LP64 | |
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575 if (MacroAssembler::is_far_target(entry_point())) { |
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576 return NativeFarCall::instruction_size; |
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577 } else { |
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578 return NativeCall::instruction_size; |
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579 } |
| 0 | 580 #else |
| 581 return NativeCall::instruction_size; // call; delay slot | |
| 582 #endif | |
| 583 } | |
| 584 | |
| 585 // Indicate if the safepoint node needs the polling page as an input. | |
| 586 // Since Sparc does not have absolute addressing, it does. | |
| 587 bool SafePointNode::needs_polling_address_input() { | |
| 588 return true; | |
| 589 } | |
| 590 | |
| 591 // emit an interrupt that is caught by the debugger (for debugging compiler) | |
| 592 void emit_break(CodeBuffer &cbuf) { | |
| 593 MacroAssembler _masm(&cbuf); | |
| 594 __ breakpoint_trap(); | |
| 595 } | |
| 596 | |
| 597 #ifndef PRODUCT | |
| 598 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const { | |
| 599 st->print("TA"); | |
| 600 } | |
| 601 #endif | |
| 602 | |
| 603 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 604 emit_break(cbuf); | |
| 605 } | |
| 606 | |
| 607 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const { | |
| 608 return MachNode::size(ra_); | |
| 609 } | |
| 610 | |
| 611 // Traceable jump | |
| 612 void emit_jmpl(CodeBuffer &cbuf, int jump_target) { | |
| 613 MacroAssembler _masm(&cbuf); | |
| 614 Register rdest = reg_to_register_object(jump_target); | |
| 615 __ JMP(rdest, 0); | |
| 616 __ delayed()->nop(); | |
| 617 } | |
| 618 | |
| 619 // Traceable jump and set exception pc | |
| 620 void emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) { | |
| 621 MacroAssembler _masm(&cbuf); | |
| 622 Register rdest = reg_to_register_object(jump_target); | |
| 623 __ JMP(rdest, 0); | |
| 624 __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc ); | |
| 625 } | |
| 626 | |
| 627 void emit_nop(CodeBuffer &cbuf) { | |
| 628 MacroAssembler _masm(&cbuf); | |
| 629 __ nop(); | |
| 630 } | |
| 631 | |
| 632 void emit_illtrap(CodeBuffer &cbuf) { | |
| 633 MacroAssembler _masm(&cbuf); | |
| 634 __ illtrap(0); | |
| 635 } | |
| 636 | |
| 637 | |
| 638 intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) { | |
| 639 assert(n->rule() != loadUB_rule, ""); | |
| 640 | |
| 641 intptr_t offset = 0; | |
| 642 const TypePtr *adr_type = TYPE_PTR_SENTINAL; // Check for base==RegI, disp==immP | |
| 643 const Node* addr = n->get_base_and_disp(offset, adr_type); | |
| 644 assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP"); | |
| 645 assert(addr != NULL && addr != (Node*)-1, "invalid addr"); | |
| 646 assert(addr->bottom_type()->isa_oopptr() == atype, ""); | |
| 647 atype = atype->add_offset(offset); | |
| 648 assert(disp32 == offset, "wrong disp32"); | |
| 649 return atype->_offset; | |
| 650 } | |
| 651 | |
| 652 | |
| 653 intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) { | |
| 654 assert(n->rule() != loadUB_rule, ""); | |
| 655 | |
| 656 intptr_t offset = 0; | |
| 657 Node* addr = n->in(2); | |
| 658 assert(addr->bottom_type()->isa_oopptr() == atype, ""); | |
| 659 if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) { | |
| 660 Node* a = addr->in(2/*AddPNode::Address*/); | |
| 661 Node* o = addr->in(3/*AddPNode::Offset*/); | |
| 662 offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot; | |
| 663 atype = a->bottom_type()->is_ptr()->add_offset(offset); | |
| 664 assert(atype->isa_oop_ptr(), "still an oop"); | |
| 665 } | |
| 666 offset = atype->is_ptr()->_offset; | |
| 667 if (offset != Type::OffsetBot) offset += disp32; | |
| 668 return offset; | |
| 669 } | |
| 670 | |
| 2008 | 671 static inline jdouble replicate_immI(int con, int count, int width) { |
| 672 // Load a constant replicated "count" times with width "width" | |
| 673 int bit_width = width * 8; | |
| 674 jlong elt_val = con; | |
| 675 elt_val &= (((jlong) 1) << bit_width) - 1; // mask off sign bits | |
| 676 jlong val = elt_val; | |
| 677 for (int i = 0; i < count - 1; i++) { | |
| 678 val <<= bit_width; | |
| 679 val |= elt_val; | |
| 680 } | |
| 681 jdouble dval = *((jdouble*) &val); // coerce to double type | |
| 682 return dval; | |
| 683 } | |
| 684 | |
| 0 | 685 // Standard Sparc opcode form2 field breakdown |
| 686 static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) { | |
| 687 f0 &= (1<<19)-1; // Mask displacement to 19 bits | |
| 688 int op = (f30 << 30) | | |
| 689 (f29 << 29) | | |
| 690 (f25 << 25) | | |
| 691 (f22 << 22) | | |
| 692 (f20 << 20) | | |
| 693 (f19 << 19) | | |
| 694 (f0 << 0); | |
| 1748 | 695 cbuf.insts()->emit_int32(op); |
| 0 | 696 } |
| 697 | |
| 698 // Standard Sparc opcode form2 field breakdown | |
| 699 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) { | |
| 700 f0 >>= 10; // Drop 10 bits | |
| 701 f0 &= (1<<22)-1; // Mask displacement to 22 bits | |
| 702 int op = (f30 << 30) | | |
| 703 (f25 << 25) | | |
| 704 (f22 << 22) | | |
| 705 (f0 << 0); | |
| 1748 | 706 cbuf.insts()->emit_int32(op); |
| 0 | 707 } |
| 708 | |
| 709 // Standard Sparc opcode form3 field breakdown | |
| 710 static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) { | |
| 711 int op = (f30 << 30) | | |
| 712 (f25 << 25) | | |
| 713 (f19 << 19) | | |
| 714 (f14 << 14) | | |
| 715 (f5 << 5) | | |
| 716 (f0 << 0); | |
| 1748 | 717 cbuf.insts()->emit_int32(op); |
| 0 | 718 } |
| 719 | |
| 720 // Standard Sparc opcode form3 field breakdown | |
| 721 static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) { | |
| 722 simm13 &= (1<<13)-1; // Mask to 13 bits | |
| 723 int op = (f30 << 30) | | |
| 724 (f25 << 25) | | |
| 725 (f19 << 19) | | |
| 726 (f14 << 14) | | |
| 727 (1 << 13) | // bit to indicate immediate-mode | |
| 728 (simm13<<0); | |
| 1748 | 729 cbuf.insts()->emit_int32(op); |
| 0 | 730 } |
| 731 | |
| 732 static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) { | |
| 733 simm10 &= (1<<10)-1; // Mask to 10 bits | |
| 734 emit3_simm13(cbuf,f30,f25,f19,f14,simm10); | |
| 735 } | |
| 736 | |
| 737 #ifdef ASSERT | |
| 738 // Helper function for VerifyOops in emit_form3_mem_reg | |
| 739 void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) { | |
| 740 warning("VerifyOops encountered unexpected instruction:"); | |
| 741 n->dump(2); | |
| 742 warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]); | |
| 743 } | |
| 744 #endif | |
| 745 | |
| 746 | |
| 747 void emit_form3_mem_reg(CodeBuffer &cbuf, const MachNode* n, int primary, int tertiary, | |
| 748 int src1_enc, int disp32, int src2_enc, int dst_enc) { | |
| 749 | |
| 750 #ifdef ASSERT | |
| 751 // The following code implements the +VerifyOops feature. | |
| 752 // It verifies oop values which are loaded into or stored out of | |
| 753 // the current method activation. +VerifyOops complements techniques | |
| 754 // like ScavengeALot, because it eagerly inspects oops in transit, | |
| 755 // as they enter or leave the stack, as opposed to ScavengeALot, | |
| 756 // which inspects oops "at rest", in the stack or heap, at safepoints. | |
| 757 // For this reason, +VerifyOops can sometimes detect bugs very close | |
| 758 // to their point of creation. It can also serve as a cross-check | |
| 759 // on the validity of oop maps, when used toegether with ScavengeALot. | |
| 760 | |
| 761 // It would be good to verify oops at other points, especially | |
| 762 // when an oop is used as a base pointer for a load or store. | |
| 763 // This is presently difficult, because it is hard to know when | |
| 764 // a base address is biased or not. (If we had such information, | |
| 765 // it would be easy and useful to make a two-argument version of | |
| 766 // verify_oop which unbiases the base, and performs verification.) | |
| 767 | |
| 768 assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary"); | |
| 769 bool is_verified_oop_base = false; | |
| 770 bool is_verified_oop_load = false; | |
| 771 bool is_verified_oop_store = false; | |
| 772 int tmp_enc = -1; | |
| 773 if (VerifyOops && src1_enc != R_SP_enc) { | |
| 774 // classify the op, mainly for an assert check | |
| 775 int st_op = 0, ld_op = 0; | |
| 776 switch (primary) { | |
| 777 case Assembler::stb_op3: st_op = Op_StoreB; break; | |
| 778 case Assembler::sth_op3: st_op = Op_StoreC; break; | |
| 779 case Assembler::stx_op3: // may become StoreP or stay StoreI or StoreD0 | |
| 780 case Assembler::stw_op3: st_op = Op_StoreI; break; | |
| 781 case Assembler::std_op3: st_op = Op_StoreL; break; | |
| 782 case Assembler::stf_op3: st_op = Op_StoreF; break; | |
| 783 case Assembler::stdf_op3: st_op = Op_StoreD; break; | |
| 784 | |
| 785 case Assembler::ldsb_op3: ld_op = Op_LoadB; break; | |
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786 case Assembler::lduh_op3: ld_op = Op_LoadUS; break; |
| 0 | 787 case Assembler::ldsh_op3: ld_op = Op_LoadS; break; |
| 788 case Assembler::ldx_op3: // may become LoadP or stay LoadI | |
| 789 case Assembler::ldsw_op3: // may become LoadP or stay LoadI | |
| 790 case Assembler::lduw_op3: ld_op = Op_LoadI; break; | |
| 791 case Assembler::ldd_op3: ld_op = Op_LoadL; break; | |
| 792 case Assembler::ldf_op3: ld_op = Op_LoadF; break; | |
| 793 case Assembler::lddf_op3: ld_op = Op_LoadD; break; | |
| 794 case Assembler::ldub_op3: ld_op = Op_LoadB; break; | |
| 795 case Assembler::prefetch_op3: ld_op = Op_LoadI; break; | |
| 796 | |
| 797 default: ShouldNotReachHere(); | |
| 798 } | |
| 799 if (tertiary == REGP_OP) { | |
| 800 if (st_op == Op_StoreI) st_op = Op_StoreP; | |
| 801 else if (ld_op == Op_LoadI) ld_op = Op_LoadP; | |
| 802 else ShouldNotReachHere(); | |
| 803 if (st_op) { | |
| 804 // a store | |
| 805 // inputs are (0:control, 1:memory, 2:address, 3:value) | |
| 806 Node* n2 = n->in(3); | |
| 807 if (n2 != NULL) { | |
| 808 const Type* t = n2->bottom_type(); | |
| 809 is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false; | |
| 810 } | |
| 811 } else { | |
| 812 // a load | |
| 813 const Type* t = n->bottom_type(); | |
| 814 is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false; | |
| 815 } | |
| 816 } | |
| 817 | |
| 818 if (ld_op) { | |
| 819 // a Load | |
| 820 // inputs are (0:control, 1:memory, 2:address) | |
| 821 if (!(n->ideal_Opcode()==ld_op) && // Following are special cases | |
| 822 !(n->ideal_Opcode()==Op_LoadLLocked && ld_op==Op_LoadI) && | |
| 823 !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) && | |
| 824 !(n->ideal_Opcode()==Op_LoadI && ld_op==Op_LoadF) && | |
| 825 !(n->ideal_Opcode()==Op_LoadF && ld_op==Op_LoadI) && | |
| 826 !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) && | |
| 827 !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) && | |
| 828 !(n->ideal_Opcode()==Op_LoadL && ld_op==Op_LoadI) && | |
| 829 !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) && | |
| 830 !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) && | |
| 831 !(n->ideal_Opcode()==Op_ConvI2F && ld_op==Op_LoadF) && | |
| 832 !(n->ideal_Opcode()==Op_ConvI2D && ld_op==Op_LoadF) && | |
| 833 !(n->ideal_Opcode()==Op_PrefetchRead && ld_op==Op_LoadI) && | |
| 834 !(n->ideal_Opcode()==Op_PrefetchWrite && ld_op==Op_LoadI) && | |
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835 !(n->ideal_Opcode()==Op_Load2I && ld_op==Op_LoadD) && |
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836 !(n->ideal_Opcode()==Op_Load4C && ld_op==Op_LoadD) && |
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837 !(n->ideal_Opcode()==Op_Load4S && ld_op==Op_LoadD) && |
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838 !(n->ideal_Opcode()==Op_Load8B && ld_op==Op_LoadD) && |
| 0 | 839 !(n->rule() == loadUB_rule)) { |
| 840 verify_oops_warning(n, n->ideal_Opcode(), ld_op); | |
| 841 } | |
| 842 } else if (st_op) { | |
| 843 // a Store | |
| 844 // inputs are (0:control, 1:memory, 2:address, 3:value) | |
| 845 if (!(n->ideal_Opcode()==st_op) && // Following are special cases | |
| 846 !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) && | |
| 847 !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) && | |
| 848 !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) && | |
| 849 !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) && | |
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850 !(n->ideal_Opcode()==Op_Store2I && st_op==Op_StoreD) && |
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851 !(n->ideal_Opcode()==Op_Store4C && st_op==Op_StoreD) && |
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852 !(n->ideal_Opcode()==Op_Store8B && st_op==Op_StoreD) && |
| 0 | 853 !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) { |
| 854 verify_oops_warning(n, n->ideal_Opcode(), st_op); | |
| 855 } | |
| 856 } | |
| 857 | |
| 858 if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) { | |
| 859 Node* addr = n->in(2); | |
| 860 if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) { | |
| 861 const TypeOopPtr* atype = addr->bottom_type()->isa_instptr(); // %%% oopptr? | |
| 862 if (atype != NULL) { | |
| 863 intptr_t offset = get_offset_from_base(n, atype, disp32); | |
| 864 intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32); | |
| 865 if (offset != offset_2) { | |
| 866 get_offset_from_base(n, atype, disp32); | |
| 867 get_offset_from_base_2(n, atype, disp32); | |
| 868 } | |
| 869 assert(offset == offset_2, "different offsets"); | |
| 870 if (offset == disp32) { | |
| 871 // we now know that src1 is a true oop pointer | |
| 872 is_verified_oop_base = true; | |
| 873 if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) { | |
| 874 if( primary == Assembler::ldd_op3 ) { | |
| 875 is_verified_oop_base = false; // Cannot 'ldd' into O7 | |
| 876 } else { | |
| 877 tmp_enc = dst_enc; | |
| 878 dst_enc = R_O7_enc; // Load into O7; preserve source oop | |
| 879 assert(src1_enc != dst_enc, ""); | |
| 880 } | |
| 881 } | |
| 882 } | |
| 883 if (st_op && (( offset == oopDesc::klass_offset_in_bytes()) | |
| 884 || offset == oopDesc::mark_offset_in_bytes())) { | |
| 885 // loading the mark should not be allowed either, but | |
| 886 // we don't check this since it conflicts with InlineObjectHash | |
| 887 // usage of LoadINode to get the mark. We could keep the | |
| 888 // check if we create a new LoadMarkNode | |
| 889 // but do not verify the object before its header is initialized | |
| 890 ShouldNotReachHere(); | |
| 891 } | |
| 892 } | |
| 893 } | |
| 894 } | |
| 895 } | |
| 896 #endif | |
| 897 | |
| 898 uint instr; | |
| 899 instr = (Assembler::ldst_op << 30) | |
| 900 | (dst_enc << 25) | |
| 901 | (primary << 19) | |
| 902 | (src1_enc << 14); | |
| 903 | |
| 904 uint index = src2_enc; | |
| 905 int disp = disp32; | |
| 906 | |
| 907 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc) | |
| 908 disp += STACK_BIAS; | |
| 909 | |
| 910 // We should have a compiler bailout here rather than a guarantee. | |
| 911 // Better yet would be some mechanism to handle variable-size matches correctly. | |
| 912 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" ); | |
| 913 | |
| 914 if( disp == 0 ) { | |
| 915 // use reg-reg form | |
| 916 // bit 13 is already zero | |
| 917 instr |= index; | |
| 918 } else { | |
| 919 // use reg-imm form | |
| 920 instr |= 0x00002000; // set bit 13 to one | |
| 921 instr |= disp & 0x1FFF; | |
| 922 } | |
| 923 | |
| 1748 | 924 cbuf.insts()->emit_int32(instr); |
| 0 | 925 |
| 926 #ifdef ASSERT | |
| 927 { | |
| 928 MacroAssembler _masm(&cbuf); | |
| 929 if (is_verified_oop_base) { | |
| 930 __ verify_oop(reg_to_register_object(src1_enc)); | |
| 931 } | |
| 932 if (is_verified_oop_store) { | |
| 933 __ verify_oop(reg_to_register_object(dst_enc)); | |
| 934 } | |
| 935 if (tmp_enc != -1) { | |
| 936 __ mov(O7, reg_to_register_object(tmp_enc)); | |
| 937 } | |
| 938 if (is_verified_oop_load) { | |
| 939 __ verify_oop(reg_to_register_object(dst_enc)); | |
| 940 } | |
| 941 } | |
| 942 #endif | |
| 943 } | |
| 944 | |
|
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945 void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, relocInfo::relocType rtype, bool preserve_g2 = false) { |
| 0 | 946 // The method which records debug information at every safepoint |
| 947 // expects the call to be the first instruction in the snippet as | |
| 948 // it creates a PcDesc structure which tracks the offset of a call | |
| 949 // from the start of the codeBlob. This offset is computed as | |
| 950 // code_end() - code_begin() of the code which has been emitted | |
| 951 // so far. | |
| 952 // In this particular case we have skirted around the problem by | |
| 953 // putting the "mov" instruction in the delay slot but the problem | |
| 954 // may bite us again at some other point and a cleaner/generic | |
| 955 // solution using relocations would be needed. | |
| 956 MacroAssembler _masm(&cbuf); | |
| 957 __ set_inst_mark(); | |
| 958 | |
| 959 // We flush the current window just so that there is a valid stack copy | |
| 960 // the fact that the current window becomes active again instantly is | |
| 961 // not a problem there is nothing live in it. | |
| 962 | |
| 963 #ifdef ASSERT | |
| 964 int startpos = __ offset(); | |
| 965 #endif /* ASSERT */ | |
| 966 | |
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967 __ call((address)entry_point, rtype); |
| 0 | 968 |
| 969 if (preserve_g2) __ delayed()->mov(G2, L7); | |
| 970 else __ delayed()->nop(); | |
| 971 | |
| 972 if (preserve_g2) __ mov(L7, G2); | |
| 973 | |
| 974 #ifdef ASSERT | |
| 975 if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) { | |
| 976 #ifdef _LP64 | |
| 977 // Trash argument dump slots. | |
| 978 __ set(0xb0b8ac0db0b8ac0d, G1); | |
| 979 __ mov(G1, G5); | |
| 980 __ stx(G1, SP, STACK_BIAS + 0x80); | |
| 981 __ stx(G1, SP, STACK_BIAS + 0x88); | |
| 982 __ stx(G1, SP, STACK_BIAS + 0x90); | |
| 983 __ stx(G1, SP, STACK_BIAS + 0x98); | |
| 984 __ stx(G1, SP, STACK_BIAS + 0xA0); | |
| 985 __ stx(G1, SP, STACK_BIAS + 0xA8); | |
| 986 #else // _LP64 | |
| 987 // this is also a native call, so smash the first 7 stack locations, | |
| 988 // and the various registers | |
| 989 | |
| 990 // Note: [SP+0x40] is sp[callee_aggregate_return_pointer_sp_offset], | |
| 991 // while [SP+0x44..0x58] are the argument dump slots. | |
| 992 __ set((intptr_t)0xbaadf00d, G1); | |
| 993 __ mov(G1, G5); | |
| 994 __ sllx(G1, 32, G1); | |
| 995 __ or3(G1, G5, G1); | |
| 996 __ mov(G1, G5); | |
| 997 __ stx(G1, SP, 0x40); | |
| 998 __ stx(G1, SP, 0x48); | |
| 999 __ stx(G1, SP, 0x50); | |
| 1000 __ stw(G1, SP, 0x58); // Do not trash [SP+0x5C] which is a usable spill slot | |
| 1001 #endif // _LP64 | |
| 1002 } | |
| 1003 #endif /*ASSERT*/ | |
| 1004 } | |
| 1005 | |
| 1006 //============================================================================= | |
| 1007 // REQUIRED FUNCTIONALITY for encoding | |
| 1008 void emit_lo(CodeBuffer &cbuf, int val) { } | |
| 1009 void emit_hi(CodeBuffer &cbuf, int val) { } | |
| 1010 | |
| 1011 | |
| 1012 //============================================================================= | |
| 2008 | 1013 const bool Matcher::constant_table_absolute_addressing = false; |
| 1014 const RegMask& MachConstantBaseNode::_out_RegMask = PTR_REG_mask; | |
| 1015 | |
| 1016 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const { | |
| 1017 Compile* C = ra_->C; | |
| 1018 Compile::ConstantTable& constant_table = C->constant_table(); | |
| 1019 MacroAssembler _masm(&cbuf); | |
| 1020 | |
| 1021 Register r = as_Register(ra_->get_encode(this)); | |
| 1022 CodeSection* cs = __ code()->consts(); | |
| 1023 int consts_size = cs->align_at_start(cs->size()); | |
| 1024 | |
| 1025 if (UseRDPCForConstantTableBase) { | |
| 1026 // For the following RDPC logic to work correctly the consts | |
| 1027 // section must be allocated right before the insts section. This | |
| 1028 // assert checks for that. The layout and the SECT_* constants | |
| 1029 // are defined in src/share/vm/asm/codeBuffer.hpp. | |
| 1030 assert(CodeBuffer::SECT_CONSTS + 1 == CodeBuffer::SECT_INSTS, "must be"); | |
| 1031 int offset = __ offset(); | |
| 1032 int disp; | |
| 1033 | |
| 1034 // If the displacement from the current PC to the constant table | |
| 1035 // base fits into simm13 we set the constant table base to the | |
| 1036 // current PC. | |
| 1037 if (__ is_simm13(-(consts_size + offset))) { | |
| 1038 constant_table.set_table_base_offset(-(consts_size + offset)); | |
| 1039 disp = 0; | |
| 1040 } else { | |
| 1041 // If the offset of the top constant (last entry in the table) | |
| 1042 // fits into simm13 we set the constant table base to the actual | |
| 1043 // table base. | |
| 1044 if (__ is_simm13(constant_table.top_offset())) { | |
| 1045 constant_table.set_table_base_offset(0); | |
| 1046 disp = consts_size + offset; | |
| 1047 } else { | |
| 1048 // Otherwise we set the constant table base in the middle of the | |
| 1049 // constant table. | |
| 1050 int half_consts_size = consts_size / 2; | |
| 1051 assert(half_consts_size * 2 == consts_size, "sanity"); | |
| 1052 constant_table.set_table_base_offset(-half_consts_size); // table base offset gets added to the load displacement. | |
| 1053 disp = half_consts_size + offset; | |
| 1054 } | |
| 1055 } | |
| 1056 | |
| 1057 __ rdpc(r); | |
| 1058 | |
| 1059 if (disp != 0) { | |
| 1060 assert(r != O7, "need temporary"); | |
| 1061 __ sub(r, __ ensure_simm13_or_reg(disp, O7), r); | |
| 1062 } | |
| 1063 } | |
| 1064 else { | |
| 1065 // Materialize the constant table base. | |
| 1066 assert(constant_table.size() == consts_size, err_msg("must be: %d == %d", constant_table.size(), consts_size)); | |
| 1067 address baseaddr = cs->start() + -(constant_table.table_base_offset()); | |
| 1068 RelocationHolder rspec = internal_word_Relocation::spec(baseaddr); | |
| 1069 AddressLiteral base(baseaddr, rspec); | |
| 1070 __ set(base, r); | |
| 1071 } | |
| 1072 } | |
| 1073 | |
| 1074 uint MachConstantBaseNode::size(PhaseRegAlloc*) const { | |
| 1075 if (UseRDPCForConstantTableBase) { | |
| 1076 // This is really the worst case but generally it's only 1 instruction. | |
|
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1077 return (1 /*rdpc*/ + 1 /*sub*/ + MacroAssembler::worst_case_insts_for_set()) * BytesPerInstWord; |
| 2008 | 1078 } else { |
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1079 return MacroAssembler::worst_case_insts_for_set() * BytesPerInstWord; |
| 2008 | 1080 } |
| 1081 } | |
| 1082 | |
| 1083 #ifndef PRODUCT | |
| 1084 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const { | |
| 1085 char reg[128]; | |
| 1086 ra_->dump_register(this, reg); | |
| 1087 if (UseRDPCForConstantTableBase) { | |
| 1088 st->print("RDPC %s\t! constant table base", reg); | |
| 1089 } else { | |
| 1090 st->print("SET &constanttable,%s\t! constant table base", reg); | |
| 1091 } | |
| 1092 } | |
| 1093 #endif | |
| 1094 | |
| 1095 | |
| 1096 //============================================================================= | |
| 0 | 1097 |
| 1098 #ifndef PRODUCT | |
| 1099 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
| 1100 Compile* C = ra_->C; | |
| 1101 | |
| 1102 for (int i = 0; i < OptoPrologueNops; i++) { | |
| 1103 st->print_cr("NOP"); st->print("\t"); | |
| 1104 } | |
| 1105 | |
| 1106 if( VerifyThread ) { | |
| 1107 st->print_cr("Verify_Thread"); st->print("\t"); | |
| 1108 } | |
| 1109 | |
| 1110 size_t framesize = C->frame_slots() << LogBytesPerInt; | |
| 1111 | |
| 1112 // Calls to C2R adapters often do not accept exceptional returns. | |
| 1113 // We require that their callers must bang for them. But be careful, because | |
| 1114 // some VM calls (such as call site linkage) can use several kilobytes of | |
| 1115 // stack. But the stack safety zone should account for that. | |
| 1116 // See bugs 4446381, 4468289, 4497237. | |
| 1117 if (C->need_stack_bang(framesize)) { | |
| 1118 st->print_cr("! stack bang"); st->print("\t"); | |
| 1119 } | |
| 1120 | |
| 1121 if (Assembler::is_simm13(-framesize)) { | |
| 1122 st->print ("SAVE R_SP,-%d,R_SP",framesize); | |
| 1123 } else { | |
| 1124 st->print_cr("SETHI R_SP,hi%%(-%d),R_G3",framesize); st->print("\t"); | |
| 1125 st->print_cr("ADD R_G3,lo%%(-%d),R_G3",framesize); st->print("\t"); | |
| 1126 st->print ("SAVE R_SP,R_G3,R_SP"); | |
| 1127 } | |
| 1128 | |
| 1129 } | |
| 1130 #endif | |
| 1131 | |
| 1132 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1133 Compile* C = ra_->C; | |
| 1134 MacroAssembler _masm(&cbuf); | |
| 1135 | |
| 1136 for (int i = 0; i < OptoPrologueNops; i++) { | |
| 1137 __ nop(); | |
| 1138 } | |
| 1139 | |
| 1140 __ verify_thread(); | |
| 1141 | |
| 1142 size_t framesize = C->frame_slots() << LogBytesPerInt; | |
| 1143 assert(framesize >= 16*wordSize, "must have room for reg. save area"); | |
| 1144 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment"); | |
| 1145 | |
| 1146 // Calls to C2R adapters often do not accept exceptional returns. | |
| 1147 // We require that their callers must bang for them. But be careful, because | |
| 1148 // some VM calls (such as call site linkage) can use several kilobytes of | |
| 1149 // stack. But the stack safety zone should account for that. | |
| 1150 // See bugs 4446381, 4468289, 4497237. | |
| 1151 if (C->need_stack_bang(framesize)) { | |
| 1152 __ generate_stack_overflow_check(framesize); | |
| 1153 } | |
| 1154 | |
| 1155 if (Assembler::is_simm13(-framesize)) { | |
| 1156 __ save(SP, -framesize, SP); | |
| 1157 } else { | |
| 1158 __ sethi(-framesize & ~0x3ff, G3); | |
| 1159 __ add(G3, -framesize & 0x3ff, G3); | |
| 1160 __ save(SP, G3, SP); | |
| 1161 } | |
| 1162 C->set_frame_complete( __ offset() ); | |
| 1163 } | |
| 1164 | |
| 1165 uint MachPrologNode::size(PhaseRegAlloc *ra_) const { | |
| 1166 return MachNode::size(ra_); | |
| 1167 } | |
| 1168 | |
| 1169 int MachPrologNode::reloc() const { | |
| 1170 return 10; // a large enough number | |
| 1171 } | |
| 1172 | |
| 1173 //============================================================================= | |
| 1174 #ifndef PRODUCT | |
| 1175 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
| 1176 Compile* C = ra_->C; | |
| 1177 | |
| 1178 if( do_polling() && ra_->C->is_method_compilation() ) { | |
| 1179 st->print("SETHI #PollAddr,L0\t! Load Polling address\n\t"); | |
| 1180 #ifdef _LP64 | |
| 1181 st->print("LDX [L0],G0\t!Poll for Safepointing\n\t"); | |
| 1182 #else | |
| 1183 st->print("LDUW [L0],G0\t!Poll for Safepointing\n\t"); | |
| 1184 #endif | |
| 1185 } | |
| 1186 | |
| 1187 if( do_polling() ) | |
| 1188 st->print("RET\n\t"); | |
| 1189 | |
| 1190 st->print("RESTORE"); | |
| 1191 } | |
| 1192 #endif | |
| 1193 | |
| 1194 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1195 MacroAssembler _masm(&cbuf); | |
| 1196 Compile* C = ra_->C; | |
| 1197 | |
| 1198 __ verify_thread(); | |
| 1199 | |
| 1200 // If this does safepoint polling, then do it here | |
| 1201 if( do_polling() && ra_->C->is_method_compilation() ) { | |
| 727 | 1202 AddressLiteral polling_page(os::get_polling_page()); |
| 1203 __ sethi(polling_page, L0); | |
| 0 | 1204 __ relocate(relocInfo::poll_return_type); |
| 1205 __ ld_ptr( L0, 0, G0 ); | |
| 1206 } | |
| 1207 | |
| 1208 // If this is a return, then stuff the restore in the delay slot | |
| 1209 if( do_polling() ) { | |
| 1210 __ ret(); | |
| 1211 __ delayed()->restore(); | |
| 1212 } else { | |
| 1213 __ restore(); | |
| 1214 } | |
| 1215 } | |
| 1216 | |
| 1217 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const { | |
| 1218 return MachNode::size(ra_); | |
| 1219 } | |
| 1220 | |
| 1221 int MachEpilogNode::reloc() const { | |
| 1222 return 16; // a large enough number | |
| 1223 } | |
| 1224 | |
| 1225 const Pipeline * MachEpilogNode::pipeline() const { | |
| 1226 return MachNode::pipeline_class(); | |
| 1227 } | |
| 1228 | |
| 1229 int MachEpilogNode::safepoint_offset() const { | |
| 1230 assert( do_polling(), "no return for this epilog node"); | |
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1231 return MacroAssembler::insts_for_sethi(os::get_polling_page()) * BytesPerInstWord; |
| 0 | 1232 } |
| 1233 | |
| 1234 //============================================================================= | |
| 1235 | |
| 1236 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack | |
| 1237 enum RC { rc_bad, rc_int, rc_float, rc_stack }; | |
| 1238 static enum RC rc_class( OptoReg::Name reg ) { | |
| 1239 if( !OptoReg::is_valid(reg) ) return rc_bad; | |
| 1240 if (OptoReg::is_stack(reg)) return rc_stack; | |
| 1241 VMReg r = OptoReg::as_VMReg(reg); | |
| 1242 if (r->is_Register()) return rc_int; | |
| 1243 assert(r->is_FloatRegister(), "must be"); | |
| 1244 return rc_float; | |
| 1245 } | |
| 1246 | |
| 1247 static int impl_helper( const MachNode *mach, CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size, outputStream* st ) { | |
| 1248 if( cbuf ) { | |
| 1249 // Better yet would be some mechanism to handle variable-size matches correctly | |
| 1250 if (!Assembler::is_simm13(offset + STACK_BIAS)) { | |
| 1251 ra_->C->record_method_not_compilable("unable to handle large constant offsets"); | |
| 1252 } else { | |
| 1253 emit_form3_mem_reg(*cbuf, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]); | |
| 1254 } | |
| 1255 } | |
| 1256 #ifndef PRODUCT | |
| 1257 else if( !do_size ) { | |
| 1258 if( size != 0 ) st->print("\n\t"); | |
| 1259 if( is_load ) st->print("%s [R_SP + #%d],R_%s\t! spill",op_str,offset,OptoReg::regname(reg)); | |
| 1260 else st->print("%s R_%s,[R_SP + #%d]\t! spill",op_str,OptoReg::regname(reg),offset); | |
| 1261 } | |
| 1262 #endif | |
| 1263 return size+4; | |
| 1264 } | |
| 1265 | |
| 1266 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int op1, int op2, const char *op_str, int size, outputStream* st ) { | |
| 1267 if( cbuf ) emit3( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src] ); | |
| 1268 #ifndef PRODUCT | |
| 1269 else if( !do_size ) { | |
| 1270 if( size != 0 ) st->print("\n\t"); | |
| 1271 st->print("%s R_%s,R_%s\t! spill",op_str,OptoReg::regname(src),OptoReg::regname(dst)); | |
| 1272 } | |
| 1273 #endif | |
| 1274 return size+4; | |
| 1275 } | |
| 1276 | |
| 1277 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, | |
| 1278 PhaseRegAlloc *ra_, | |
| 1279 bool do_size, | |
| 1280 outputStream* st ) const { | |
| 1281 // Get registers to move | |
| 1282 OptoReg::Name src_second = ra_->get_reg_second(in(1)); | |
| 1283 OptoReg::Name src_first = ra_->get_reg_first(in(1)); | |
| 1284 OptoReg::Name dst_second = ra_->get_reg_second(this ); | |
| 1285 OptoReg::Name dst_first = ra_->get_reg_first(this ); | |
| 1286 | |
| 1287 enum RC src_second_rc = rc_class(src_second); | |
| 1288 enum RC src_first_rc = rc_class(src_first); | |
| 1289 enum RC dst_second_rc = rc_class(dst_second); | |
| 1290 enum RC dst_first_rc = rc_class(dst_first); | |
| 1291 | |
| 1292 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" ); | |
| 1293 | |
| 1294 // Generate spill code! | |
| 1295 int size = 0; | |
| 1296 | |
| 1297 if( src_first == dst_first && src_second == dst_second ) | |
| 1298 return size; // Self copy, no move | |
| 1299 | |
| 1300 // -------------------------------------- | |
| 1301 // Check for mem-mem move. Load into unused float registers and fall into | |
| 1302 // the float-store case. | |
| 1303 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) { | |
| 1304 int offset = ra_->reg2offset(src_first); | |
| 1305 // Further check for aligned-adjacent pair, so we can use a double load | |
| 1306 if( (src_first&1)==0 && src_first+1 == src_second ) { | |
| 1307 src_second = OptoReg::Name(R_F31_num); | |
| 1308 src_second_rc = rc_float; | |
| 1309 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::lddf_op3,"LDDF",size, st); | |
| 1310 } else { | |
| 1311 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::ldf_op3 ,"LDF ",size, st); | |
| 1312 } | |
| 1313 src_first = OptoReg::Name(R_F30_num); | |
| 1314 src_first_rc = rc_float; | |
| 1315 } | |
| 1316 | |
| 1317 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { | |
| 1318 int offset = ra_->reg2offset(src_second); | |
| 1319 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F31_num,Assembler::ldf_op3,"LDF ",size, st); | |
| 1320 src_second = OptoReg::Name(R_F31_num); | |
| 1321 src_second_rc = rc_float; | |
| 1322 } | |
| 1323 | |
| 1324 // -------------------------------------- | |
| 1325 // Check for float->int copy; requires a trip through memory | |
| 3804 | 1326 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS < 3) { |
| 0 | 1327 int offset = frame::register_save_words*wordSize; |
| 3804 | 1328 if (cbuf) { |
| 0 | 1329 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16 ); |
| 1330 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); | |
| 1331 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); | |
| 1332 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16 ); | |
| 1333 } | |
| 1334 #ifndef PRODUCT | |
| 3804 | 1335 else if (!do_size) { |
| 1336 if (size != 0) st->print("\n\t"); | |
| 0 | 1337 st->print( "SUB R_SP,16,R_SP\n"); |
| 1338 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); | |
| 1339 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); | |
| 1340 st->print("\tADD R_SP,16,R_SP\n"); | |
| 1341 } | |
| 1342 #endif | |
| 1343 size += 16; | |
| 1344 } | |
| 1345 | |
| 3804 | 1346 // Check for float->int copy on T4 |
| 1347 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS >= 3) { | |
| 1348 // Further check for aligned-adjacent pair, so we can use a double move | |
| 1349 if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second) | |
| 1350 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mdtox_opf,"MOVDTOX",size, st); | |
| 1351 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mstouw_opf,"MOVSTOUW",size, st); | |
| 1352 } | |
| 1353 // Check for int->float copy on T4 | |
| 1354 if (src_first_rc == rc_int && dst_first_rc == rc_float && UseVIS >= 3) { | |
| 1355 // Further check for aligned-adjacent pair, so we can use a double move | |
| 1356 if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second) | |
| 1357 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mxtod_opf,"MOVXTOD",size, st); | |
| 1358 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mwtos_opf,"MOVWTOS",size, st); | |
| 1359 } | |
| 1360 | |
| 0 | 1361 // -------------------------------------- |
| 1362 // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations. | |
| 1363 // In such cases, I have to do the big-endian swap. For aligned targets, the | |
| 1364 // hardware does the flop for me. Doubles are always aligned, so no problem | |
| 1365 // there. Misaligned sources only come from native-long-returns (handled | |
| 1366 // special below). | |
| 1367 #ifndef _LP64 | |
| 1368 if( src_first_rc == rc_int && // source is already big-endian | |
| 1369 src_second_rc != rc_bad && // 64-bit move | |
| 1370 ((dst_first&1)!=0 || dst_second != dst_first+1) ) { // misaligned dst | |
| 1371 assert( (src_first&1)==0 && src_second == src_first+1, "source must be aligned" ); | |
| 1372 // Do the big-endian flop. | |
| 1373 OptoReg::Name tmp = dst_first ; dst_first = dst_second ; dst_second = tmp ; | |
| 1374 enum RC tmp_rc = dst_first_rc; dst_first_rc = dst_second_rc; dst_second_rc = tmp_rc; | |
| 1375 } | |
| 1376 #endif | |
| 1377 | |
| 1378 // -------------------------------------- | |
| 1379 // Check for integer reg-reg copy | |
| 1380 if( src_first_rc == rc_int && dst_first_rc == rc_int ) { | |
| 1381 #ifndef _LP64 | |
| 1382 if( src_first == R_O0_num && src_second == R_O1_num ) { // Check for the evil O0/O1 native long-return case | |
| 1383 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value | |
| 1384 // as stored in memory. On a big-endian machine like SPARC, this means that the _second | |
| 1385 // operand contains the least significant word of the 64-bit value and vice versa. | |
| 1386 OptoReg::Name tmp = OptoReg::Name(R_O7_num); | |
| 1387 assert( (dst_first&1)==0 && dst_second == dst_first+1, "return a native O0/O1 long to an aligned-adjacent 64-bit reg" ); | |
| 1388 // Shift O0 left in-place, zero-extend O1, then OR them into the dst | |
| 1389 if( cbuf ) { | |
| 1390 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tmp], Assembler::sllx_op3, Matcher::_regEncode[src_first], 0x1020 ); | |
| 1391 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[src_second], Assembler::srl_op3, Matcher::_regEncode[src_second], 0x0000 ); | |
| 1392 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler:: or_op3, Matcher::_regEncode[tmp], 0, Matcher::_regEncode[src_second] ); | |
| 1393 #ifndef PRODUCT | |
| 1394 } else if( !do_size ) { | |
| 1395 if( size != 0 ) st->print("\n\t"); | |
| 1396 st->print("SLLX R_%s,32,R_%s\t! Move O0-first to O7-high\n\t", OptoReg::regname(src_first), OptoReg::regname(tmp)); | |
| 1397 st->print("SRL R_%s, 0,R_%s\t! Zero-extend O1\n\t", OptoReg::regname(src_second), OptoReg::regname(src_second)); | |
| 1398 st->print("OR R_%s,R_%s,R_%s\t! spill",OptoReg::regname(tmp), OptoReg::regname(src_second), OptoReg::regname(dst_first)); | |
| 1399 #endif | |
| 1400 } | |
| 1401 return size+12; | |
| 1402 } | |
| 1403 else if( dst_first == R_I0_num && dst_second == R_I1_num ) { | |
| 1404 // returning a long value in I0/I1 | |
| 1405 // a SpillCopy must be able to target a return instruction's reg_class | |
| 1406 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value | |
| 1407 // as stored in memory. On a big-endian machine like SPARC, this means that the _second | |
| 1408 // operand contains the least significant word of the 64-bit value and vice versa. | |
| 1409 OptoReg::Name tdest = dst_first; | |
| 1410 | |
| 1411 if (src_first == dst_first) { | |
| 1412 tdest = OptoReg::Name(R_O7_num); | |
| 1413 size += 4; | |
| 1414 } | |
| 1415 | |
| 1416 if( cbuf ) { | |
| 1417 assert( (src_first&1) == 0 && (src_first+1) == src_second, "return value was in an aligned-adjacent 64-bit reg"); | |
| 1418 // Shift value in upper 32-bits of src to lower 32-bits of I0; move lower 32-bits to I1 | |
| 1419 // ShrL_reg_imm6 | |
| 1420 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tdest], Assembler::srlx_op3, Matcher::_regEncode[src_second], 32 | 0x1000 ); | |
| 1421 // ShrR_reg_imm6 src, 0, dst | |
| 1422 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srl_op3, Matcher::_regEncode[src_first], 0x0000 ); | |
| 1423 if (tdest != dst_first) { | |
| 1424 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler::or_op3, 0/*G0*/, 0/*op2*/, Matcher::_regEncode[tdest] ); | |
| 1425 } | |
| 1426 } | |
| 1427 #ifndef PRODUCT | |
| 1428 else if( !do_size ) { | |
| 1429 if( size != 0 ) st->print("\n\t"); // %%%%% !!!!! | |
| 1430 st->print("SRLX R_%s,32,R_%s\t! Extract MSW\n\t",OptoReg::regname(src_second),OptoReg::regname(tdest)); | |
| 1431 st->print("SRL R_%s, 0,R_%s\t! Extract LSW\n\t",OptoReg::regname(src_first),OptoReg::regname(dst_second)); | |
| 1432 if (tdest != dst_first) { | |
| 1433 st->print("MOV R_%s,R_%s\t! spill\n\t", OptoReg::regname(tdest), OptoReg::regname(dst_first)); | |
| 1434 } | |
| 1435 } | |
| 1436 #endif // PRODUCT | |
| 1437 return size+8; | |
| 1438 } | |
| 1439 #endif // !_LP64 | |
| 1440 // Else normal reg-reg copy | |
| 1441 assert( src_second != dst_first, "smashed second before evacuating it" ); | |
| 1442 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::or_op3,0,"MOV ",size, st); | |
| 1443 assert( (src_first&1) == 0 && (dst_first&1) == 0, "never move second-halves of int registers" ); | |
| 1444 // This moves an aligned adjacent pair. | |
| 1445 // See if we are done. | |
| 1446 if( src_first+1 == src_second && dst_first+1 == dst_second ) | |
| 1447 return size; | |
| 1448 } | |
| 1449 | |
| 1450 // Check for integer store | |
| 1451 if( src_first_rc == rc_int && dst_first_rc == rc_stack ) { | |
| 1452 int offset = ra_->reg2offset(dst_first); | |
| 1453 // Further check for aligned-adjacent pair, so we can use a double store | |
| 1454 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
| 1455 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stx_op3,"STX ",size, st); | |
| 1456 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stw_op3,"STW ",size, st); | |
| 1457 } | |
| 1458 | |
| 1459 // Check for integer load | |
| 1460 if( dst_first_rc == rc_int && src_first_rc == rc_stack ) { | |
| 1461 int offset = ra_->reg2offset(src_first); | |
| 1462 // Further check for aligned-adjacent pair, so we can use a double load | |
| 1463 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
| 1464 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldx_op3 ,"LDX ",size, st); | |
| 1465 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); | |
| 1466 } | |
| 1467 | |
| 1468 // Check for float reg-reg copy | |
| 1469 if( src_first_rc == rc_float && dst_first_rc == rc_float ) { | |
| 1470 // Further check for aligned-adjacent pair, so we can use a double move | |
| 1471 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
| 1472 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovd_opf,"FMOVD",size, st); | |
| 1473 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovs_opf,"FMOVS",size, st); | |
| 1474 } | |
| 1475 | |
| 1476 // Check for float store | |
| 1477 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) { | |
| 1478 int offset = ra_->reg2offset(dst_first); | |
| 1479 // Further check for aligned-adjacent pair, so we can use a double store | |
| 1480 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
| 1481 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stdf_op3,"STDF",size, st); | |
| 1482 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); | |
| 1483 } | |
| 1484 | |
| 1485 // Check for float load | |
| 1486 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) { | |
| 1487 int offset = ra_->reg2offset(src_first); | |
| 1488 // Further check for aligned-adjacent pair, so we can use a double load | |
| 1489 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
| 1490 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lddf_op3,"LDDF",size, st); | |
| 1491 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldf_op3 ,"LDF ",size, st); | |
| 1492 } | |
| 1493 | |
| 1494 // -------------------------------------------------------------------- | |
| 1495 // Check for hi bits still needing moving. Only happens for misaligned | |
| 1496 // arguments to native calls. | |
| 1497 if( src_second == dst_second ) | |
| 1498 return size; // Self copy; no move | |
| 1499 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" ); | |
| 1500 | |
| 1501 #ifndef _LP64 | |
| 1502 // In the LP64 build, all registers can be moved as aligned/adjacent | |
| 605 | 1503 // pairs, so there's never any need to move the high bits separately. |
| 0 | 1504 // The 32-bit builds have to deal with the 32-bit ABI which can force |
| 1505 // all sorts of silly alignment problems. | |
| 1506 | |
| 1507 // Check for integer reg-reg copy. Hi bits are stuck up in the top | |
| 1508 // 32-bits of a 64-bit register, but are needed in low bits of another | |
| 1509 // register (else it's a hi-bits-to-hi-bits copy which should have | |
| 1510 // happened already as part of a 64-bit move) | |
| 1511 if( src_second_rc == rc_int && dst_second_rc == rc_int ) { | |
| 1512 assert( (src_second&1)==1, "its the evil O0/O1 native return case" ); | |
| 1513 assert( (dst_second&1)==0, "should have moved with 1 64-bit move" ); | |
| 1514 // Shift src_second down to dst_second's low bits. | |
| 1515 if( cbuf ) { | |
| 1516 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 ); | |
| 1517 #ifndef PRODUCT | |
| 1518 } else if( !do_size ) { | |
| 1519 if( size != 0 ) st->print("\n\t"); | |
| 1520 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(dst_second)); | |
| 1521 #endif | |
| 1522 } | |
| 1523 return size+4; | |
| 1524 } | |
| 1525 | |
| 1526 // Check for high word integer store. Must down-shift the hi bits | |
| 1527 // into a temp register, then fall into the case of storing int bits. | |
| 1528 if( src_second_rc == rc_int && dst_second_rc == rc_stack && (src_second&1)==1 ) { | |
| 1529 // Shift src_second down to dst_second's low bits. | |
| 1530 if( cbuf ) { | |
| 1531 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[R_O7_num], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 ); | |
| 1532 #ifndef PRODUCT | |
| 1533 } else if( !do_size ) { | |
| 1534 if( size != 0 ) st->print("\n\t"); | |
| 1535 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(R_O7_num)); | |
| 1536 #endif | |
| 1537 } | |
| 1538 size+=4; | |
| 1539 src_second = OptoReg::Name(R_O7_num); // Not R_O7H_num! | |
| 1540 } | |
| 1541 | |
| 1542 // Check for high word integer load | |
| 1543 if( dst_second_rc == rc_int && src_second_rc == rc_stack ) | |
| 1544 return impl_helper(this,cbuf,ra_,do_size,true ,ra_->reg2offset(src_second),dst_second,Assembler::lduw_op3,"LDUW",size, st); | |
| 1545 | |
| 1546 // Check for high word integer store | |
| 1547 if( src_second_rc == rc_int && dst_second_rc == rc_stack ) | |
| 1548 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stw_op3 ,"STW ",size, st); | |
| 1549 | |
| 1550 // Check for high word float store | |
| 1551 if( src_second_rc == rc_float && dst_second_rc == rc_stack ) | |
| 1552 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stf_op3 ,"STF ",size, st); | |
| 1553 | |
| 1554 #endif // !_LP64 | |
| 1555 | |
| 1556 Unimplemented(); | |
| 1557 } | |
| 1558 | |
| 1559 #ifndef PRODUCT | |
| 1560 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
| 1561 implementation( NULL, ra_, false, st ); | |
| 1562 } | |
| 1563 #endif | |
| 1564 | |
| 1565 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1566 implementation( &cbuf, ra_, false, NULL ); | |
| 1567 } | |
| 1568 | |
| 1569 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const { | |
| 1570 return implementation( NULL, ra_, true, NULL ); | |
| 1571 } | |
| 1572 | |
| 1573 //============================================================================= | |
| 1574 #ifndef PRODUCT | |
| 1575 void MachNopNode::format( PhaseRegAlloc *, outputStream *st ) const { | |
| 1576 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count); | |
| 1577 } | |
| 1578 #endif | |
| 1579 | |
| 1580 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const { | |
| 1581 MacroAssembler _masm(&cbuf); | |
| 1582 for(int i = 0; i < _count; i += 1) { | |
| 1583 __ nop(); | |
| 1584 } | |
| 1585 } | |
| 1586 | |
| 1587 uint MachNopNode::size(PhaseRegAlloc *ra_) const { | |
| 1588 return 4 * _count; | |
| 1589 } | |
| 1590 | |
| 1591 | |
| 1592 //============================================================================= | |
| 1593 #ifndef PRODUCT | |
| 1594 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
| 1595 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
| 1596 int reg = ra_->get_reg_first(this); | |
| 1597 st->print("LEA [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]); | |
| 1598 } | |
| 1599 #endif | |
| 1600 | |
| 1601 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1602 MacroAssembler _masm(&cbuf); | |
| 1603 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS; | |
| 1604 int reg = ra_->get_encode(this); | |
| 1605 | |
| 1606 if (Assembler::is_simm13(offset)) { | |
| 1607 __ add(SP, offset, reg_to_register_object(reg)); | |
| 1608 } else { | |
| 1609 __ set(offset, O7); | |
| 1610 __ add(SP, O7, reg_to_register_object(reg)); | |
| 1611 } | |
| 1612 } | |
| 1613 | |
| 1614 uint BoxLockNode::size(PhaseRegAlloc *ra_) const { | |
| 1615 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_) | |
| 1616 assert(ra_ == ra_->C->regalloc(), "sanity"); | |
| 1617 return ra_->C->scratch_emit_size(this); | |
| 1618 } | |
| 1619 | |
| 1620 //============================================================================= | |
| 1621 | |
| 1622 // emit call stub, compiled java to interpretor | |
| 1623 void emit_java_to_interp(CodeBuffer &cbuf ) { | |
| 1624 | |
| 1625 // Stub is fixed up when the corresponding call is converted from calling | |
| 1626 // compiled code to calling interpreted code. | |
| 1627 // set (empty), G5 | |
| 1628 // jmp -1 | |
| 1629 | |
| 1748 | 1630 address mark = cbuf.insts_mark(); // get mark within main instrs section |
| 0 | 1631 |
| 1632 MacroAssembler _masm(&cbuf); | |
| 1633 | |
| 1634 address base = | |
| 1635 __ start_a_stub(Compile::MAX_stubs_size); | |
| 1636 if (base == NULL) return; // CodeBuffer::expand failed | |
| 1637 | |
| 1638 // static stub relocation stores the instruction address of the call | |
| 1639 __ relocate(static_stub_Relocation::spec(mark)); | |
| 1640 | |
| 1641 __ set_oop(NULL, reg_to_register_object(Matcher::inline_cache_reg_encode())); | |
| 1642 | |
| 1643 __ set_inst_mark(); | |
| 727 | 1644 AddressLiteral addrlit(-1); |
| 1645 __ JUMP(addrlit, G3, 0); | |
| 0 | 1646 |
| 1647 __ delayed()->nop(); | |
| 1648 | |
| 1649 // Update current stubs pointer and restore code_end. | |
| 1650 __ end_a_stub(); | |
| 1651 } | |
| 1652 | |
| 1653 // size of call stub, compiled java to interpretor | |
| 1654 uint size_java_to_interp() { | |
| 1655 // This doesn't need to be accurate but it must be larger or equal to | |
| 1656 // the real size of the stub. | |
| 1657 return (NativeMovConstReg::instruction_size + // sethi/setlo; | |
| 1658 NativeJump::instruction_size + // sethi; jmp; nop | |
| 1659 (TraceJumps ? 20 * BytesPerInstWord : 0) ); | |
| 1660 } | |
| 1661 // relocation entries for call stub, compiled java to interpretor | |
| 1662 uint reloc_java_to_interp() { | |
| 1663 return 10; // 4 in emit_java_to_interp + 1 in Java_Static_Call | |
| 1664 } | |
| 1665 | |
| 1666 | |
| 1667 //============================================================================= | |
| 1668 #ifndef PRODUCT | |
| 1669 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
| 1670 st->print_cr("\nUEP:"); | |
| 1671 #ifdef _LP64 | |
|
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1672 if (UseCompressedOops) { |
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1673 assert(Universe::heap() != NULL, "java heap should be initialized"); |
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1674 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass"); |
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1675 st->print_cr("\tSLL R_G5,3,R_G5"); |
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1676 if (Universe::narrow_oop_base() != NULL) |
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1677 st->print_cr("\tADD R_G5,R_G6_heap_base,R_G5"); |
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1678 } else { |
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1679 st->print_cr("\tLDX [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check"); |
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1680 } |
| 0 | 1681 st->print_cr("\tCMP R_G5,R_G3" ); |
| 1682 st->print ("\tTne xcc,R_G0+ST_RESERVED_FOR_USER_0+2"); | |
| 1683 #else // _LP64 | |
| 1684 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check"); | |
| 1685 st->print_cr("\tCMP R_G5,R_G3" ); | |
| 1686 st->print ("\tTne icc,R_G0+ST_RESERVED_FOR_USER_0+2"); | |
| 1687 #endif // _LP64 | |
| 1688 } | |
| 1689 #endif | |
| 1690 | |
| 1691 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1692 MacroAssembler _masm(&cbuf); | |
| 1693 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); | |
| 1694 Register temp_reg = G3; | |
| 1695 assert( G5_ic_reg != temp_reg, "conflicting registers" ); | |
| 1696 | |
| 605 | 1697 // Load klass from receiver |
|
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1698 __ load_klass(O0, temp_reg); |
| 0 | 1699 // Compare against expected klass |
| 1700 __ cmp(temp_reg, G5_ic_reg); | |
| 1701 // Branch to miss code, checks xcc or icc depending | |
| 1702 __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2); | |
| 1703 } | |
| 1704 | |
| 1705 uint MachUEPNode::size(PhaseRegAlloc *ra_) const { | |
| 1706 return MachNode::size(ra_); | |
| 1707 } | |
| 1708 | |
| 1709 | |
| 1710 //============================================================================= | |
| 1711 | |
| 1712 uint size_exception_handler() { | |
| 1713 if (TraceJumps) { | |
| 1714 return (400); // just a guess | |
| 1715 } | |
| 1716 return ( NativeJump::instruction_size ); // sethi;jmp;nop | |
| 1717 } | |
| 1718 | |
| 1719 uint size_deopt_handler() { | |
| 1720 if (TraceJumps) { | |
| 1721 return (400); // just a guess | |
| 1722 } | |
| 1723 return ( 4+ NativeJump::instruction_size ); // save;sethi;jmp;restore | |
| 1724 } | |
| 1725 | |
| 1726 // Emit exception handler code. | |
| 1727 int emit_exception_handler(CodeBuffer& cbuf) { | |
| 1728 Register temp_reg = G3; | |
| 1748 | 1729 AddressLiteral exception_blob(OptoRuntime::exception_blob()->entry_point()); |
| 0 | 1730 MacroAssembler _masm(&cbuf); |
| 1731 | |
| 1732 address base = | |
| 1733 __ start_a_stub(size_exception_handler()); | |
| 1734 if (base == NULL) return 0; // CodeBuffer::expand failed | |
| 1735 | |
| 1736 int offset = __ offset(); | |
| 1737 | |
| 727 | 1738 __ JUMP(exception_blob, temp_reg, 0); // sethi;jmp |
| 0 | 1739 __ delayed()->nop(); |
| 1740 | |
| 1741 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow"); | |
| 1742 | |
| 1743 __ end_a_stub(); | |
| 1744 | |
| 1745 return offset; | |
| 1746 } | |
| 1747 | |
| 1748 int emit_deopt_handler(CodeBuffer& cbuf) { | |
| 1749 // Can't use any of the current frame's registers as we may have deopted | |
| 1750 // at a poll and everything (including G3) can be live. | |
| 1751 Register temp_reg = L0; | |
| 727 | 1752 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack()); |
| 0 | 1753 MacroAssembler _masm(&cbuf); |
| 1754 | |
| 1755 address base = | |
| 1756 __ start_a_stub(size_deopt_handler()); | |
| 1757 if (base == NULL) return 0; // CodeBuffer::expand failed | |
| 1758 | |
| 1759 int offset = __ offset(); | |
| 1760 __ save_frame(0); | |
| 727 | 1761 __ JUMP(deopt_blob, temp_reg, 0); // sethi;jmp |
| 0 | 1762 __ delayed()->restore(); |
| 1763 | |
| 1764 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow"); | |
| 1765 | |
| 1766 __ end_a_stub(); | |
| 1767 return offset; | |
| 1768 | |
| 1769 } | |
| 1770 | |
| 1771 // Given a register encoding, produce a Integer Register object | |
| 1772 static Register reg_to_register_object(int register_encoding) { | |
| 1773 assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding"); | |
| 1774 return as_Register(register_encoding); | |
| 1775 } | |
| 1776 | |
| 1777 // Given a register encoding, produce a single-precision Float Register object | |
| 1778 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) { | |
| 1779 assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding"); | |
| 1780 return as_SingleFloatRegister(register_encoding); | |
| 1781 } | |
| 1782 | |
| 1783 // Given a register encoding, produce a double-precision Float Register object | |
| 1784 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) { | |
| 1785 assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding"); | |
| 1786 assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding"); | |
| 1787 return as_DoubleFloatRegister(register_encoding); | |
| 1788 } | |
| 1789 | |
|
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1790 const bool Matcher::match_rule_supported(int opcode) { |
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1791 if (!has_match_rule(opcode)) |
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1792 return false; |
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1793 |
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1794 switch (opcode) { |
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1795 case Op_CountLeadingZerosI: |
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1796 case Op_CountLeadingZerosL: |
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1797 case Op_CountTrailingZerosI: |
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1798 case Op_CountTrailingZerosL: |
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1799 if (!UsePopCountInstruction) |
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1800 return false; |
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1801 break; |
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1802 } |
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1803 |
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1804 return true; // Per default match rules are supported. |
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1805 } |
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1806 |
| 0 | 1807 int Matcher::regnum_to_fpu_offset(int regnum) { |
| 1808 return regnum - 32; // The FP registers are in the second chunk | |
| 1809 } | |
| 1810 | |
| 1811 #ifdef ASSERT | |
| 1812 address last_rethrow = NULL; // debugging aid for Rethrow encoding | |
| 1813 #endif | |
| 1814 | |
| 1815 // Vector width in bytes | |
| 1816 const uint Matcher::vector_width_in_bytes(void) { | |
| 1817 return 8; | |
| 1818 } | |
| 1819 | |
| 1820 // Vector ideal reg | |
| 1821 const uint Matcher::vector_ideal_reg(void) { | |
| 1822 return Op_RegD; | |
| 1823 } | |
| 1824 | |
| 1825 // USII supports fxtof through the whole range of number, USIII doesn't | |
| 1826 const bool Matcher::convL2FSupported(void) { | |
| 1827 return VM_Version::has_fast_fxtof(); | |
| 1828 } | |
| 1829 | |
| 1830 // Is this branch offset short enough that a short branch can be used? | |
| 1831 // | |
| 1832 // NOTE: If the platform does not provide any short branch variants, then | |
| 1833 // this method should return false for offset 0. | |
| 3851 | 1834 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) { |
| 1835 // The passed offset is relative to address of the branch. | |
| 1836 // Don't need to adjust the offset. | |
| 1837 return UseCBCond && Assembler::is_simm(offset, 12); | |
| 0 | 1838 } |
| 1839 | |
| 1840 const bool Matcher::isSimpleConstant64(jlong value) { | |
| 1841 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?. | |
| 1842 // Depends on optimizations in MacroAssembler::setx. | |
| 1843 int hi = (int)(value >> 32); | |
| 1844 int lo = (int)(value & ~0); | |
| 1845 return (hi == 0) || (hi == -1) || (lo == 0); | |
| 1846 } | |
| 1847 | |
| 1848 // No scaling for the parameter the ClearArray node. | |
| 1849 const bool Matcher::init_array_count_is_in_bytes = true; | |
| 1850 | |
| 1851 // Threshold size for cleararray. | |
| 1852 const int Matcher::init_array_short_size = 8 * BytesPerLong; | |
| 1853 | |
| 1854 // Should the Matcher clone shifts on addressing modes, expecting them to | |
| 1855 // be subsumed into complex addressing expressions or compute them into | |
| 1856 // registers? True for Intel but false for most RISCs | |
| 1857 const bool Matcher::clone_shift_expressions = false; | |
| 1858 | |
|
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1859 // Do we need to mask the count passed to shift instructions or does |
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1860 // the cpu only look at the lower 5/6 bits anyway? |
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1861 const bool Matcher::need_masked_shift_count = false; |
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1862 |
|
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1863 bool Matcher::narrow_oop_use_complex_address() { |
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1864 NOT_LP64(ShouldNotCallThis()); |
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1865 assert(UseCompressedOops, "only for compressed oops code"); |
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1866 return false; |
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1867 } |
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1868 |
| 0 | 1869 // Is it better to copy float constants, or load them directly from memory? |
| 1870 // Intel can load a float constant from a direct address, requiring no | |
| 1871 // extra registers. Most RISCs will have to materialize an address into a | |
| 1872 // register first, so they would do better to copy the constant from stack. | |
| 1873 const bool Matcher::rematerialize_float_constants = false; | |
| 1874 | |
| 1875 // If CPU can load and store mis-aligned doubles directly then no fixup is | |
| 1876 // needed. Else we split the double into 2 integer pieces and move it | |
| 1877 // piece-by-piece. Only happens when passing doubles into C code as the | |
| 1878 // Java calling convention forces doubles to be aligned. | |
| 1879 #ifdef _LP64 | |
| 1880 const bool Matcher::misaligned_doubles_ok = true; | |
| 1881 #else | |
| 1882 const bool Matcher::misaligned_doubles_ok = false; | |
| 1883 #endif | |
| 1884 | |
| 1885 // No-op on SPARC. | |
| 1886 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) { | |
| 1887 } | |
| 1888 | |
| 1889 // Advertise here if the CPU requires explicit rounding operations | |
| 1890 // to implement the UseStrictFP mode. | |
| 1891 const bool Matcher::strict_fp_requires_explicit_rounding = false; | |
| 1892 | |
|
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1893 // Are floats conerted to double when stored to stack during deoptimization? |
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1894 // Sparc does not handle callee-save floats. |
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1895 bool Matcher::float_in_double() { return false; } |
| 0 | 1896 |
| 1897 // Do ints take an entire long register or just half? | |
| 1898 // Note that we if-def off of _LP64. | |
| 1899 // The relevant question is how the int is callee-saved. In _LP64 | |
| 1900 // the whole long is written but de-opt'ing will have to extract | |
| 1901 // the relevant 32 bits, in not-_LP64 only the low 32 bits is written. | |
| 1902 #ifdef _LP64 | |
| 1903 const bool Matcher::int_in_long = true; | |
| 1904 #else | |
| 1905 const bool Matcher::int_in_long = false; | |
| 1906 #endif | |
| 1907 | |
| 1908 // Return whether or not this register is ever used as an argument. This | |
| 1909 // function is used on startup to build the trampoline stubs in generateOptoStub. | |
| 1910 // Registers not mentioned will be killed by the VM call in the trampoline, and | |
| 1911 // arguments in those registers not be available to the callee. | |
| 1912 bool Matcher::can_be_java_arg( int reg ) { | |
| 1913 // Standard sparc 6 args in registers | |
| 1914 if( reg == R_I0_num || | |
| 1915 reg == R_I1_num || | |
| 1916 reg == R_I2_num || | |
| 1917 reg == R_I3_num || | |
| 1918 reg == R_I4_num || | |
| 1919 reg == R_I5_num ) return true; | |
| 1920 #ifdef _LP64 | |
| 1921 // 64-bit builds can pass 64-bit pointers and longs in | |
| 1922 // the high I registers | |
| 1923 if( reg == R_I0H_num || | |
| 1924 reg == R_I1H_num || | |
| 1925 reg == R_I2H_num || | |
| 1926 reg == R_I3H_num || | |
| 1927 reg == R_I4H_num || | |
| 1928 reg == R_I5H_num ) return true; | |
|
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1929 |
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1930 if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) { |
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1931 return true; |
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1932 } |
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1933 |
| 0 | 1934 #else |
| 1935 // 32-bit builds with longs-in-one-entry pass longs in G1 & G4. | |
| 1936 // Longs cannot be passed in O regs, because O regs become I regs | |
| 1937 // after a 'save' and I regs get their high bits chopped off on | |
| 1938 // interrupt. | |
| 1939 if( reg == R_G1H_num || reg == R_G1_num ) return true; | |
| 1940 if( reg == R_G4H_num || reg == R_G4_num ) return true; | |
| 1941 #endif | |
| 1942 // A few float args in registers | |
| 1943 if( reg >= R_F0_num && reg <= R_F7_num ) return true; | |
| 1944 | |
| 1945 return false; | |
| 1946 } | |
| 1947 | |
| 1948 bool Matcher::is_spillable_arg( int reg ) { | |
| 1949 return can_be_java_arg(reg); | |
| 1950 } | |
| 1951 | |
|
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1952 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) { |
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1953 // Use hardware SDIVX instruction when it is |
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1954 // faster than a code which use multiply. |
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1955 return VM_Version::has_fast_idiv(); |
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1956 } |
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1957 |
| 0 | 1958 // Register for DIVI projection of divmodI |
| 1959 RegMask Matcher::divI_proj_mask() { | |
| 1960 ShouldNotReachHere(); | |
| 1961 return RegMask(); | |
| 1962 } | |
| 1963 | |
| 1964 // Register for MODI projection of divmodI | |
| 1965 RegMask Matcher::modI_proj_mask() { | |
| 1966 ShouldNotReachHere(); | |
| 1967 return RegMask(); | |
| 1968 } | |
| 1969 | |
| 1970 // Register for DIVL projection of divmodL | |
| 1971 RegMask Matcher::divL_proj_mask() { | |
| 1972 ShouldNotReachHere(); | |
| 1973 return RegMask(); | |
| 1974 } | |
| 1975 | |
| 1976 // Register for MODL projection of divmodL | |
| 1977 RegMask Matcher::modL_proj_mask() { | |
| 1978 ShouldNotReachHere(); | |
| 1979 return RegMask(); | |
| 1980 } | |
| 1981 | |
|
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1982 const RegMask Matcher::method_handle_invoke_SP_save_mask() { |
| 1567 | 1983 return L7_REGP_mask; |
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1984 } |
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1985 |
| 0 | 1986 %} |
| 1987 | |
| 1988 | |
| 1989 // The intptr_t operand types, defined by textual substitution. | |
| 1990 // (Cf. opto/type.hpp. This lets us avoid many, many other ifdefs.) | |
| 1991 #ifdef _LP64 | |
| 824 | 1992 #define immX immL |
| 1993 #define immX13 immL13 | |
| 1994 #define immX13m7 immL13m7 | |
| 1995 #define iRegX iRegL | |
| 1996 #define g1RegX g1RegL | |
| 0 | 1997 #else |
| 824 | 1998 #define immX immI |
| 1999 #define immX13 immI13 | |
| 2000 #define immX13m7 immI13m7 | |
| 2001 #define iRegX iRegI | |
| 2002 #define g1RegX g1RegI | |
| 0 | 2003 #endif |
| 2004 | |
| 2005 //----------ENCODING BLOCK----------------------------------------------------- | |
| 2006 // This block specifies the encoding classes used by the compiler to output | |
| 2007 // byte streams. Encoding classes are parameterized macros used by | |
| 2008 // Machine Instruction Nodes in order to generate the bit encoding of the | |
| 2009 // instruction. Operands specify their base encoding interface with the | |
| 2010 // interface keyword. There are currently supported four interfaces, | |
| 2011 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an | |
| 2012 // operand to generate a function which returns its register number when | |
| 2013 // queried. CONST_INTER causes an operand to generate a function which | |
| 2014 // returns the value of the constant when queried. MEMORY_INTER causes an | |
| 2015 // operand to generate four functions which return the Base Register, the | |
| 2016 // Index Register, the Scale Value, and the Offset Value of the operand when | |
| 2017 // queried. COND_INTER causes an operand to generate six functions which | |
| 2018 // return the encoding code (ie - encoding bits for the instruction) | |
| 2019 // associated with each basic boolean condition for a conditional instruction. | |
| 2020 // | |
| 2021 // Instructions specify two basic values for encoding. Again, a function | |
| 2022 // is available to check if the constant displacement is an oop. They use the | |
| 2023 // ins_encode keyword to specify their encoding classes (which must be | |
| 2024 // a sequence of enc_class names, and their parameters, specified in | |
| 2025 // the encoding block), and they use the | |
| 2026 // opcode keyword to specify, in order, their primary, secondary, and | |
| 2027 // tertiary opcode. Only the opcode sections which a particular instruction | |
| 2028 // needs for encoding need to be specified. | |
| 2029 encode %{ | |
| 2030 enc_class enc_untested %{ | |
| 2031 #ifdef ASSERT | |
| 2032 MacroAssembler _masm(&cbuf); | |
| 2033 __ untested("encoding"); | |
| 2034 #endif | |
| 2035 %} | |
| 2036 | |
| 2037 enc_class form3_mem_reg( memory mem, iRegI dst ) %{ | |
| 2038 emit_form3_mem_reg(cbuf, this, $primary, $tertiary, | |
| 2039 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg); | |
| 2040 %} | |
| 2041 | |
|
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2042 enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{ |
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2043 emit_form3_mem_reg(cbuf, this, $primary, -1, |
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2044 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg); |
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2045 %} |
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2046 |
| 0 | 2047 enc_class form3_mem_prefetch_read( memory mem ) %{ |
|
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2048 emit_form3_mem_reg(cbuf, this, $primary, -1, |
| 0 | 2049 $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/); |
| 2050 %} | |
| 2051 | |
| 2052 enc_class form3_mem_prefetch_write( memory mem ) %{ | |
|
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2053 emit_form3_mem_reg(cbuf, this, $primary, -1, |
| 0 | 2054 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/); |
| 2055 %} | |
| 2056 | |
| 2057 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{ | |
| 2058 assert( Assembler::is_simm13($mem$$disp ), "need disp and disp+4" ); | |
| 2059 assert( Assembler::is_simm13($mem$$disp+4), "need disp and disp+4" ); | |
| 2060 guarantee($mem$$index == R_G0_enc, "double index?"); | |
|
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2061 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc ); |
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2062 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg ); |
| 0 | 2063 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 ); |
| 2064 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc ); | |
| 2065 %} | |
| 2066 | |
| 2067 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{ | |
| 2068 assert( Assembler::is_simm13($mem$$disp ), "need disp and disp+4" ); | |
| 2069 assert( Assembler::is_simm13($mem$$disp+4), "need disp and disp+4" ); | |
| 2070 guarantee($mem$$index == R_G0_enc, "double index?"); | |
| 2071 // Load long with 2 instructions | |
|
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2072 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 ); |
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2073 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 ); |
| 0 | 2074 %} |
| 2075 | |
| 2076 //%%% form3_mem_plus_4_reg is a hack--get rid of it | |
| 2077 enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{ | |
| 2078 guarantee($mem$$disp, "cannot offset a reg-reg operand by 4"); | |
|
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2079 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg); |
| 0 | 2080 %} |
| 2081 | |
| 2082 enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{ | |
| 2083 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
| 2084 if( $rs2$$reg != $rd$$reg ) | |
| 2085 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg ); | |
| 2086 %} | |
| 2087 | |
| 2088 // Target lo half of long | |
| 2089 enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{ | |
| 2090 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
| 2091 if( $rs2$$reg != LONG_LO_REG($rd$$reg) ) | |
| 2092 emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg ); | |
| 2093 %} | |
| 2094 | |
| 2095 // Source lo half of long | |
| 2096 enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{ | |
| 2097 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
| 2098 if( LONG_LO_REG($rs2$$reg) != $rd$$reg ) | |
| 2099 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) ); | |
| 2100 %} | |
| 2101 | |
| 2102 // Target hi half of long | |
| 2103 enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{ | |
| 2104 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 ); | |
| 2105 %} | |
| 2106 | |
| 2107 // Source lo half of long, and leave it sign extended. | |
| 2108 enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{ | |
| 2109 // Sign extend low half | |
| 2110 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 ); | |
| 2111 %} | |
| 2112 | |
| 2113 // Source hi half of long, and leave it sign extended. | |
| 2114 enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{ | |
| 2115 // Shift high half to low half | |
| 2116 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 ); | |
| 2117 %} | |
| 2118 | |
| 2119 // Source hi half of long | |
| 2120 enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{ | |
| 2121 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
| 2122 if( LONG_HI_REG($rs2$$reg) != $rd$$reg ) | |
| 2123 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) ); | |
| 2124 %} | |
| 2125 | |
| 2126 enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{ | |
| 2127 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg ); | |
| 2128 %} | |
| 2129 | |
| 2130 enc_class enc_to_bool( iRegI src, iRegI dst ) %{ | |
| 2131 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, 0, 0, $src$$reg ); | |
| 2132 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 ); | |
| 2133 %} | |
| 2134 | |
| 2135 enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{ | |
| 2136 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg ); | |
| 2137 // clear if nothing else is happening | |
| 2138 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 0 ); | |
| 2139 // blt,a,pn done | |
| 2140 emit2_19 ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 ); | |
| 2141 // mov dst,-1 in delay slot | |
| 2142 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 ); | |
| 2143 %} | |
| 2144 | |
| 2145 enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{ | |
| 2146 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F ); | |
| 2147 %} | |
| 2148 | |
| 2149 enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{ | |
| 2150 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 ); | |
| 2151 %} | |
| 2152 | |
| 2153 enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{ | |
| 2154 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg ); | |
| 2155 %} | |
| 2156 | |
| 2157 enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{ | |
| 2158 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant ); | |
| 2159 %} | |
| 2160 | |
| 2161 enc_class move_return_pc_to_o1() %{ | |
| 2162 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset ); | |
| 2163 %} | |
| 2164 | |
| 2165 #ifdef _LP64 | |
| 2166 /* %%% merge with enc_to_bool */ | |
| 2167 enc_class enc_convP2B( iRegI dst, iRegP src ) %{ | |
| 2168 MacroAssembler _masm(&cbuf); | |
| 2169 | |
| 2170 Register src_reg = reg_to_register_object($src$$reg); | |
| 2171 Register dst_reg = reg_to_register_object($dst$$reg); | |
| 2172 __ movr(Assembler::rc_nz, src_reg, 1, dst_reg); | |
| 2173 %} | |
| 2174 #endif | |
| 2175 | |
| 2176 enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{ | |
| 2177 // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))) | |
| 2178 MacroAssembler _masm(&cbuf); | |
| 2179 | |
| 2180 Register p_reg = reg_to_register_object($p$$reg); | |
| 2181 Register q_reg = reg_to_register_object($q$$reg); | |
| 2182 Register y_reg = reg_to_register_object($y$$reg); | |
| 2183 Register tmp_reg = reg_to_register_object($tmp$$reg); | |
| 2184 | |
| 2185 __ subcc( p_reg, q_reg, p_reg ); | |
| 2186 __ add ( p_reg, y_reg, tmp_reg ); | |
| 2187 __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg ); | |
| 2188 %} | |
| 2189 | |
| 2190 enc_class form_d2i_helper(regD src, regF dst) %{ | |
| 2191 // fcmp %fcc0,$src,$src | |
| 2192 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg ); | |
| 2193 // branch %fcc0 not-nan, predict taken | |
| 2194 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); | |
| 2195 // fdtoi $src,$dst | |
| 2196 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtoi_opf, $src$$reg ); | |
| 2197 // fitos $dst,$dst (if nan) | |
| 2198 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg ); | |
| 2199 // clear $dst (if nan) | |
| 2200 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg ); | |
| 2201 // carry on here... | |
| 2202 %} | |
| 2203 | |
| 2204 enc_class form_d2l_helper(regD src, regD dst) %{ | |
| 2205 // fcmp %fcc0,$src,$src check for NAN | |
| 2206 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg ); | |
| 2207 // branch %fcc0 not-nan, predict taken | |
| 2208 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); | |
| 2209 // fdtox $src,$dst convert in delay slot | |
| 2210 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtox_opf, $src$$reg ); | |
| 2211 // fxtod $dst,$dst (if nan) | |
| 2212 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg ); | |
| 2213 // clear $dst (if nan) | |
| 2214 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg ); | |
| 2215 // carry on here... | |
| 2216 %} | |
| 2217 | |
| 2218 enc_class form_f2i_helper(regF src, regF dst) %{ | |
| 2219 // fcmps %fcc0,$src,$src | |
| 2220 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg ); | |
| 2221 // branch %fcc0 not-nan, predict taken | |
| 2222 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); | |
| 2223 // fstoi $src,$dst | |
| 2224 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstoi_opf, $src$$reg ); | |
| 2225 // fitos $dst,$dst (if nan) | |
| 2226 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg ); | |
| 2227 // clear $dst (if nan) | |
| 2228 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg ); | |
| 2229 // carry on here... | |
| 2230 %} | |
| 2231 | |
| 2232 enc_class form_f2l_helper(regF src, regD dst) %{ | |
| 2233 // fcmps %fcc0,$src,$src | |
| 2234 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg ); | |
| 2235 // branch %fcc0 not-nan, predict taken | |
| 2236 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); | |
| 2237 // fstox $src,$dst | |
| 2238 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstox_opf, $src$$reg ); | |
| 2239 // fxtod $dst,$dst (if nan) | |
| 2240 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg ); | |
| 2241 // clear $dst (if nan) | |
| 2242 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg ); | |
| 2243 // carry on here... | |
| 2244 %} | |
| 2245 | |
| 2246 enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
| 2247 enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
| 2248 enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
| 2249 enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
| 2250 | |
| 2251 enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %} | |
| 2252 | |
| 2253 enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
| 2254 enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %} | |
| 2255 | |
| 2256 enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{ | |
| 2257 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); | |
| 2258 %} | |
| 2259 | |
| 2260 enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{ | |
| 2261 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); | |
| 2262 %} | |
| 2263 | |
| 2264 enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{ | |
| 2265 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); | |
| 2266 %} | |
| 2267 | |
| 2268 enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{ | |
| 2269 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); | |
| 2270 %} | |
| 2271 | |
| 2272 enc_class form3_convI2F(regF rs2, regF rd) %{ | |
| 2273 emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg); | |
| 2274 %} | |
| 2275 | |
| 2276 // Encloding class for traceable jumps | |
| 2277 enc_class form_jmpl(g3RegP dest) %{ | |
| 2278 emit_jmpl(cbuf, $dest$$reg); | |
| 2279 %} | |
| 2280 | |
| 2281 enc_class form_jmpl_set_exception_pc(g1RegP dest) %{ | |
| 2282 emit_jmpl_set_exception_pc(cbuf, $dest$$reg); | |
| 2283 %} | |
| 2284 | |
| 2285 enc_class form2_nop() %{ | |
| 2286 emit_nop(cbuf); | |
| 2287 %} | |
| 2288 | |
| 2289 enc_class form2_illtrap() %{ | |
| 2290 emit_illtrap(cbuf); | |
| 2291 %} | |
| 2292 | |
| 2293 | |
| 2294 // Compare longs and convert into -1, 0, 1. | |
| 2295 enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{ | |
| 2296 // CMP $src1,$src2 | |
| 2297 emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg ); | |
| 2298 // blt,a,pn done | |
| 2299 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 ); | |
| 2300 // mov dst,-1 in delay slot | |
| 2301 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 ); | |
| 2302 // bgt,a,pn done | |
| 2303 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 ); | |
| 2304 // mov dst,1 in delay slot | |
| 2305 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 1 ); | |
| 2306 // CLR $dst | |
| 2307 emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 ); | |
| 2308 %} | |
| 2309 | |
| 2310 enc_class enc_PartialSubtypeCheck() %{ | |
| 2311 MacroAssembler _masm(&cbuf); | |
| 2312 __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type); | |
| 2313 __ delayed()->nop(); | |
| 2314 %} | |
| 2315 | |
| 3839 | 2316 enc_class enc_bp( label labl, cmpOp cmp, flagsReg cc ) %{ |
| 0 | 2317 MacroAssembler _masm(&cbuf); |
| 3839 | 2318 Label* L = $labl$$label; |
| 0 | 2319 Assembler::Predict predict_taken = |
| 3839 | 2320 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; |
| 2321 | |
| 2322 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); | |
| 0 | 2323 __ delayed()->nop(); |
| 2324 %} | |
| 2325 | |
| 3839 | 2326 enc_class enc_bpr( label labl, cmpOp_reg cmp, iRegI op1 ) %{ |
| 0 | 2327 MacroAssembler _masm(&cbuf); |
| 3839 | 2328 Label* L = $labl$$label; |
| 0 | 2329 Assembler::Predict predict_taken = |
| 3839 | 2330 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; |
| 2331 | |
| 2332 __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), *L); | |
| 0 | 2333 __ delayed()->nop(); |
| 2334 %} | |
| 2335 | |
| 2336 enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{ | |
| 2337 int op = (Assembler::arith_op << 30) | | |
| 2338 ($dst$$reg << 25) | | |
| 2339 (Assembler::movcc_op3 << 19) | | |
| 2340 (1 << 18) | // cc2 bit for 'icc' | |
| 2341 ($cmp$$cmpcode << 14) | | |
| 2342 (0 << 13) | // select register move | |
| 2343 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' or 'xcc' | |
| 2344 ($src$$reg << 0); | |
| 1748 | 2345 cbuf.insts()->emit_int32(op); |
| 0 | 2346 %} |
| 2347 | |
| 2348 enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{ | |
| 2349 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits | |
| 2350 int op = (Assembler::arith_op << 30) | | |
| 2351 ($dst$$reg << 25) | | |
| 2352 (Assembler::movcc_op3 << 19) | | |
| 2353 (1 << 18) | // cc2 bit for 'icc' | |
| 2354 ($cmp$$cmpcode << 14) | | |
| 2355 (1 << 13) | // select immediate move | |
| 2356 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' | |
| 2357 (simm11 << 0); | |
| 1748 | 2358 cbuf.insts()->emit_int32(op); |
| 0 | 2359 %} |
| 2360 | |
| 2361 enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{ | |
| 2362 int op = (Assembler::arith_op << 30) | | |
| 2363 ($dst$$reg << 25) | | |
| 2364 (Assembler::movcc_op3 << 19) | | |
| 2365 (0 << 18) | // cc2 bit for 'fccX' | |
| 2366 ($cmp$$cmpcode << 14) | | |
| 2367 (0 << 13) | // select register move | |
| 2368 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3 | |
| 2369 ($src$$reg << 0); | |
| 1748 | 2370 cbuf.insts()->emit_int32(op); |
| 0 | 2371 %} |
| 2372 | |
| 2373 enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{ | |
| 2374 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits | |
| 2375 int op = (Assembler::arith_op << 30) | | |
| 2376 ($dst$$reg << 25) | | |
| 2377 (Assembler::movcc_op3 << 19) | | |
| 2378 (0 << 18) | // cc2 bit for 'fccX' | |
| 2379 ($cmp$$cmpcode << 14) | | |
| 2380 (1 << 13) | // select immediate move | |
| 2381 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3 | |
| 2382 (simm11 << 0); | |
| 1748 | 2383 cbuf.insts()->emit_int32(op); |
| 0 | 2384 %} |
| 2385 | |
| 2386 enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{ | |
| 2387 int op = (Assembler::arith_op << 30) | | |
| 2388 ($dst$$reg << 25) | | |
| 2389 (Assembler::fpop2_op3 << 19) | | |
| 2390 (0 << 18) | | |
| 2391 ($cmp$$cmpcode << 14) | | |
| 2392 (1 << 13) | // select register move | |
| 2393 ($pcc$$constant << 11) | // cc1-cc0 bits for 'icc' or 'xcc' | |
| 2394 ($primary << 5) | // select single, double or quad | |
| 2395 ($src$$reg << 0); | |
| 1748 | 2396 cbuf.insts()->emit_int32(op); |
| 0 | 2397 %} |
| 2398 | |
| 2399 enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{ | |
| 2400 int op = (Assembler::arith_op << 30) | | |
| 2401 ($dst$$reg << 25) | | |
| 2402 (Assembler::fpop2_op3 << 19) | | |
| 2403 (0 << 18) | | |
| 2404 ($cmp$$cmpcode << 14) | | |
| 2405 ($fcc$$reg << 11) | // cc2-cc0 bits for 'fccX' | |
| 2406 ($primary << 5) | // select single, double or quad | |
| 2407 ($src$$reg << 0); | |
| 1748 | 2408 cbuf.insts()->emit_int32(op); |
| 0 | 2409 %} |
| 2410 | |
| 2411 // Used by the MIN/MAX encodings. Same as a CMOV, but | |
| 2412 // the condition comes from opcode-field instead of an argument. | |
| 2413 enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{ | |
| 2414 int op = (Assembler::arith_op << 30) | | |
| 2415 ($dst$$reg << 25) | | |
| 2416 (Assembler::movcc_op3 << 19) | | |
| 2417 (1 << 18) | // cc2 bit for 'icc' | |
| 2418 ($primary << 14) | | |
| 2419 (0 << 13) | // select register move | |
| 2420 (0 << 11) | // cc1, cc0 bits for 'icc' | |
| 2421 ($src$$reg << 0); | |
| 1748 | 2422 cbuf.insts()->emit_int32(op); |
| 0 | 2423 %} |
| 2424 | |
| 2425 enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{ | |
| 2426 int op = (Assembler::arith_op << 30) | | |
| 2427 ($dst$$reg << 25) | | |
| 2428 (Assembler::movcc_op3 << 19) | | |
| 2429 (6 << 16) | // cc2 bit for 'xcc' | |
| 2430 ($primary << 14) | | |
| 2431 (0 << 13) | // select register move | |
| 2432 (0 << 11) | // cc1, cc0 bits for 'icc' | |
| 2433 ($src$$reg << 0); | |
| 1748 | 2434 cbuf.insts()->emit_int32(op); |
| 0 | 2435 %} |
| 2436 | |
| 2437 enc_class Set13( immI13 src, iRegI rd ) %{ | |
| 2438 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant ); | |
| 2439 %} | |
| 2440 | |
| 2441 enc_class SetHi22( immI src, iRegI rd ) %{ | |
| 2442 emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant ); | |
| 2443 %} | |
| 2444 | |
| 2445 enc_class Set32( immI src, iRegI rd ) %{ | |
| 2446 MacroAssembler _masm(&cbuf); | |
| 2447 __ set($src$$constant, reg_to_register_object($rd$$reg)); | |
| 2448 %} | |
| 2449 | |
| 2450 enc_class call_epilog %{ | |
| 2451 if( VerifyStackAtCalls ) { | |
| 2452 MacroAssembler _masm(&cbuf); | |
| 2453 int framesize = ra_->C->frame_slots() << LogBytesPerInt; | |
| 2454 Register temp_reg = G3; | |
| 2455 __ add(SP, framesize, temp_reg); | |
| 2456 __ cmp(temp_reg, FP); | |
| 2457 __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc); | |
| 2458 } | |
| 2459 %} | |
| 2460 | |
| 2461 // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value | |
| 2462 // to G1 so the register allocator will not have to deal with the misaligned register | |
| 2463 // pair. | |
| 2464 enc_class adjust_long_from_native_call %{ | |
| 2465 #ifndef _LP64 | |
| 2466 if (returns_long()) { | |
| 2467 // sllx O0,32,O0 | |
| 2468 emit3_simm13( cbuf, Assembler::arith_op, R_O0_enc, Assembler::sllx_op3, R_O0_enc, 0x1020 ); | |
| 2469 // srl O1,0,O1 | |
| 2470 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::srl_op3, R_O1_enc, 0x0000 ); | |
| 2471 // or O0,O1,G1 | |
| 2472 emit3 ( cbuf, Assembler::arith_op, R_G1_enc, Assembler:: or_op3, R_O0_enc, 0, R_O1_enc ); | |
| 2473 } | |
| 2474 #endif | |
| 2475 %} | |
| 2476 | |
| 2477 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime | |
| 2478 // CALL directly to the runtime | |
| 2479 // The user of this is responsible for ensuring that R_L7 is empty (killed). | |
| 2480 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type, | |
|
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2481 /*preserve_g2=*/true); |
| 0 | 2482 %} |
| 2483 | |
| 1567 | 2484 enc_class preserve_SP %{ |
| 2485 MacroAssembler _masm(&cbuf); | |
| 2486 __ mov(SP, L7_mh_SP_save); | |
| 2487 %} | |
| 2488 | |
| 2489 enc_class restore_SP %{ | |
| 2490 MacroAssembler _masm(&cbuf); | |
| 2491 __ mov(L7_mh_SP_save, SP); | |
| 2492 %} | |
| 2493 | |
| 0 | 2494 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL |
| 2495 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine | |
| 2496 // who we intended to call. | |
| 2497 if ( !_method ) { | |
| 2498 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type); | |
| 2499 } else if (_optimized_virtual) { | |
| 2500 emit_call_reloc(cbuf, $meth$$method, relocInfo::opt_virtual_call_type); | |
| 2501 } else { | |
| 2502 emit_call_reloc(cbuf, $meth$$method, relocInfo::static_call_type); | |
| 2503 } | |
| 2504 if( _method ) { // Emit stub for static call | |
| 2505 emit_java_to_interp(cbuf); | |
| 2506 } | |
| 2507 %} | |
| 2508 | |
| 2509 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL | |
| 2510 MacroAssembler _masm(&cbuf); | |
| 2511 __ set_inst_mark(); | |
| 2512 int vtable_index = this->_vtable_index; | |
| 2513 // MachCallDynamicJavaNode::ret_addr_offset uses this same test | |
| 2514 if (vtable_index < 0) { | |
| 2515 // must be invalid_vtable_index, not nonvirtual_vtable_index | |
| 2516 assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value"); | |
| 2517 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); | |
| 2518 assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()"); | |
| 2519 assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub"); | |
| 2520 // !!!!! | |
| 2521 // Generate "set 0x01, R_G5", placeholder instruction to load oop-info | |
| 2522 // emit_call_dynamic_prologue( cbuf ); | |
| 2523 __ set_oop((jobject)Universe::non_oop_word(), G5_ic_reg); | |
| 2524 | |
| 2525 address virtual_call_oop_addr = __ inst_mark(); | |
| 2526 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine | |
| 2527 // who we intended to call. | |
| 2528 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr)); | |
| 2529 emit_call_reloc(cbuf, $meth$$method, relocInfo::none); | |
| 2530 } else { | |
| 2531 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); | |
| 2532 // Just go thru the vtable | |
| 2533 // get receiver klass (receiver already checked for non-null) | |
| 2534 // If we end up going thru a c2i adapter interpreter expects method in G5 | |
| 2535 int off = __ offset(); | |
|
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2536 __ load_klass(O0, G3_scratch); |
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2537 int klass_load_size; |
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2538 if (UseCompressedOops) { |
|
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2539 assert(Universe::heap() != NULL, "java heap should be initialized"); |
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2540 if (Universe::narrow_oop_base() == NULL) |
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2541 klass_load_size = 2*BytesPerInstWord; |
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2542 else |
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2543 klass_load_size = 3*BytesPerInstWord; |
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2544 } else { |
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2545 klass_load_size = 1*BytesPerInstWord; |
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2546 } |
| 0 | 2547 int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size(); |
| 2548 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes(); | |
| 2549 if( __ is_simm13(v_off) ) { | |
| 2550 __ ld_ptr(G3, v_off, G5_method); | |
| 2551 } else { | |
| 2552 // Generate 2 instructions | |
| 2553 __ Assembler::sethi(v_off & ~0x3ff, G5_method); | |
| 2554 __ or3(G5_method, v_off & 0x3ff, G5_method); | |
| 2555 // ld_ptr, set_hi, set | |
|
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2556 assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord, |
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2557 "Unexpected instruction size(s)"); |
| 0 | 2558 __ ld_ptr(G3, G5_method, G5_method); |
| 2559 } | |
| 2560 // NOTE: for vtable dispatches, the vtable entry will never be null. | |
| 2561 // However it may very well end up in handle_wrong_method if the | |
| 2562 // method is abstract for the particular class. | |
| 2563 __ ld_ptr(G5_method, in_bytes(methodOopDesc::from_compiled_offset()), G3_scratch); | |
| 2564 // jump to target (either compiled code or c2iadapter) | |
| 2565 __ jmpl(G3_scratch, G0, O7); | |
| 2566 __ delayed()->nop(); | |
| 2567 } | |
| 2568 %} | |
| 2569 | |
| 2570 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL | |
| 2571 MacroAssembler _masm(&cbuf); | |
| 2572 | |
| 2573 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); | |
| 2574 Register temp_reg = G3; // caller must kill G3! We cannot reuse G5_ic_reg here because | |
| 2575 // we might be calling a C2I adapter which needs it. | |
| 2576 | |
| 2577 assert(temp_reg != G5_ic_reg, "conflicting registers"); | |
| 2578 // Load nmethod | |
| 2579 __ ld_ptr(G5_ic_reg, in_bytes(methodOopDesc::from_compiled_offset()), temp_reg); | |
| 2580 | |
| 2581 // CALL to compiled java, indirect the contents of G3 | |
| 2582 __ set_inst_mark(); | |
| 2583 __ callr(temp_reg, G0); | |
| 2584 __ delayed()->nop(); | |
| 2585 %} | |
| 2586 | |
| 2587 enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{ | |
| 2588 MacroAssembler _masm(&cbuf); | |
| 2589 Register Rdividend = reg_to_register_object($src1$$reg); | |
| 2590 Register Rdivisor = reg_to_register_object($src2$$reg); | |
| 2591 Register Rresult = reg_to_register_object($dst$$reg); | |
| 2592 | |
| 2593 __ sra(Rdivisor, 0, Rdivisor); | |
| 2594 __ sra(Rdividend, 0, Rdividend); | |
| 2595 __ sdivx(Rdividend, Rdivisor, Rresult); | |
| 2596 %} | |
| 2597 | |
| 2598 enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{ | |
| 2599 MacroAssembler _masm(&cbuf); | |
| 2600 | |
| 2601 Register Rdividend = reg_to_register_object($src1$$reg); | |
| 2602 int divisor = $imm$$constant; | |
| 2603 Register Rresult = reg_to_register_object($dst$$reg); | |
| 2604 | |
| 2605 __ sra(Rdividend, 0, Rdividend); | |
| 2606 __ sdivx(Rdividend, divisor, Rresult); | |
| 2607 %} | |
| 2608 | |
| 2609 enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{ | |
| 2610 MacroAssembler _masm(&cbuf); | |
| 2611 Register Rsrc1 = reg_to_register_object($src1$$reg); | |
| 2612 Register Rsrc2 = reg_to_register_object($src2$$reg); | |
| 2613 Register Rdst = reg_to_register_object($dst$$reg); | |
| 2614 | |
| 2615 __ sra( Rsrc1, 0, Rsrc1 ); | |
| 2616 __ sra( Rsrc2, 0, Rsrc2 ); | |
| 2617 __ mulx( Rsrc1, Rsrc2, Rdst ); | |
| 2618 __ srlx( Rdst, 32, Rdst ); | |
| 2619 %} | |
| 2620 | |
| 2621 enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{ | |
| 2622 MacroAssembler _masm(&cbuf); | |
| 2623 Register Rdividend = reg_to_register_object($src1$$reg); | |
| 2624 Register Rdivisor = reg_to_register_object($src2$$reg); | |
| 2625 Register Rresult = reg_to_register_object($dst$$reg); | |
| 2626 Register Rscratch = reg_to_register_object($scratch$$reg); | |
| 2627 | |
| 2628 assert(Rdividend != Rscratch, ""); | |
| 2629 assert(Rdivisor != Rscratch, ""); | |
| 2630 | |
| 2631 __ sra(Rdividend, 0, Rdividend); | |
| 2632 __ sra(Rdivisor, 0, Rdivisor); | |
| 2633 __ sdivx(Rdividend, Rdivisor, Rscratch); | |
| 2634 __ mulx(Rscratch, Rdivisor, Rscratch); | |
| 2635 __ sub(Rdividend, Rscratch, Rresult); | |
| 2636 %} | |
| 2637 | |
| 2638 enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{ | |
| 2639 MacroAssembler _masm(&cbuf); | |
| 2640 | |
| 2641 Register Rdividend = reg_to_register_object($src1$$reg); | |
| 2642 int divisor = $imm$$constant; | |
| 2643 Register Rresult = reg_to_register_object($dst$$reg); | |
| 2644 Register Rscratch = reg_to_register_object($scratch$$reg); | |
| 2645 | |
| 2646 assert(Rdividend != Rscratch, ""); | |
| 2647 | |
| 2648 __ sra(Rdividend, 0, Rdividend); | |
| 2649 __ sdivx(Rdividend, divisor, Rscratch); | |
| 2650 __ mulx(Rscratch, divisor, Rscratch); | |
| 2651 __ sub(Rdividend, Rscratch, Rresult); | |
| 2652 %} | |
| 2653 | |
| 2654 enc_class fabss (sflt_reg dst, sflt_reg src) %{ | |
| 2655 MacroAssembler _masm(&cbuf); | |
| 2656 | |
| 2657 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); | |
| 2658 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); | |
| 2659 | |
| 2660 __ fabs(FloatRegisterImpl::S, Fsrc, Fdst); | |
| 2661 %} | |
| 2662 | |
| 2663 enc_class fabsd (dflt_reg dst, dflt_reg src) %{ | |
| 2664 MacroAssembler _masm(&cbuf); | |
| 2665 | |
| 2666 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); | |
| 2667 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); | |
| 2668 | |
| 2669 __ fabs(FloatRegisterImpl::D, Fsrc, Fdst); | |
| 2670 %} | |
| 2671 | |
| 2672 enc_class fnegd (dflt_reg dst, dflt_reg src) %{ | |
| 2673 MacroAssembler _masm(&cbuf); | |
| 2674 | |
| 2675 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); | |
| 2676 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); | |
| 2677 | |
| 2678 __ fneg(FloatRegisterImpl::D, Fsrc, Fdst); | |
| 2679 %} | |
| 2680 | |
| 2681 enc_class fsqrts (sflt_reg dst, sflt_reg src) %{ | |
| 2682 MacroAssembler _masm(&cbuf); | |
| 2683 | |
| 2684 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); | |
| 2685 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); | |
| 2686 | |
| 2687 __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst); | |
| 2688 %} | |
| 2689 | |
| 2690 enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{ | |
| 2691 MacroAssembler _masm(&cbuf); | |
| 2692 | |
| 2693 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); | |
| 2694 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); | |
| 2695 | |
| 2696 __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst); | |
| 2697 %} | |
| 2698 | |
| 2699 enc_class fmovs (dflt_reg dst, dflt_reg src) %{ | |
| 2700 MacroAssembler _masm(&cbuf); | |
| 2701 | |
| 2702 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); | |
| 2703 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); | |
| 2704 | |
| 2705 __ fmov(FloatRegisterImpl::S, Fsrc, Fdst); | |
| 2706 %} | |
| 2707 | |
| 2708 enc_class fmovd (dflt_reg dst, dflt_reg src) %{ | |
| 2709 MacroAssembler _masm(&cbuf); | |
| 2710 | |
| 2711 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); | |
| 2712 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); | |
| 2713 | |
| 2714 __ fmov(FloatRegisterImpl::D, Fsrc, Fdst); | |
| 2715 %} | |
| 2716 | |
| 2717 enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{ | |
| 2718 MacroAssembler _masm(&cbuf); | |
| 2719 | |
| 2720 Register Roop = reg_to_register_object($oop$$reg); | |
| 2721 Register Rbox = reg_to_register_object($box$$reg); | |
| 2722 Register Rscratch = reg_to_register_object($scratch$$reg); | |
| 2723 Register Rmark = reg_to_register_object($scratch2$$reg); | |
| 2724 | |
| 2725 assert(Roop != Rscratch, ""); | |
| 2726 assert(Roop != Rmark, ""); | |
| 2727 assert(Rbox != Rscratch, ""); | |
| 2728 assert(Rbox != Rmark, ""); | |
| 2729 | |
|
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2730 __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters, UseBiasedLocking && !UseOptoBiasInlining); |
| 0 | 2731 %} |
| 2732 | |
| 2733 enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{ | |
| 2734 MacroAssembler _masm(&cbuf); | |
| 2735 | |
| 2736 Register Roop = reg_to_register_object($oop$$reg); | |
| 2737 Register Rbox = reg_to_register_object($box$$reg); | |
| 2738 Register Rscratch = reg_to_register_object($scratch$$reg); | |
| 2739 Register Rmark = reg_to_register_object($scratch2$$reg); | |
| 2740 | |
| 2741 assert(Roop != Rscratch, ""); | |
| 2742 assert(Roop != Rmark, ""); | |
| 2743 assert(Rbox != Rscratch, ""); | |
| 2744 assert(Rbox != Rmark, ""); | |
| 2745 | |
|
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2746 __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch, UseBiasedLocking && !UseOptoBiasInlining); |
| 0 | 2747 %} |
| 2748 | |
| 2749 enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{ | |
| 2750 MacroAssembler _masm(&cbuf); | |
| 2751 Register Rmem = reg_to_register_object($mem$$reg); | |
| 2752 Register Rold = reg_to_register_object($old$$reg); | |
| 2753 Register Rnew = reg_to_register_object($new$$reg); | |
| 2754 | |
| 2755 // casx_under_lock picks 1 of 3 encodings: | |
| 2756 // For 32-bit pointers you get a 32-bit CAS | |
| 2757 // For 64-bit pointers you get a 64-bit CASX | |
|
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2758 __ casn(Rmem, Rold, Rnew); // Swap(*Rmem,Rnew) if *Rmem == Rold |
| 0 | 2759 __ cmp( Rold, Rnew ); |
| 2760 %} | |
| 2761 | |
| 2762 enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{ | |
| 2763 Register Rmem = reg_to_register_object($mem$$reg); | |
| 2764 Register Rold = reg_to_register_object($old$$reg); | |
| 2765 Register Rnew = reg_to_register_object($new$$reg); | |
| 2766 | |
| 2767 MacroAssembler _masm(&cbuf); | |
| 2768 __ mov(Rnew, O7); | |
| 2769 __ casx(Rmem, Rold, O7); | |
| 2770 __ cmp( Rold, O7 ); | |
| 2771 %} | |
| 2772 | |
| 2773 // raw int cas, used for compareAndSwap | |
| 2774 enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{ | |
| 2775 Register Rmem = reg_to_register_object($mem$$reg); | |
| 2776 Register Rold = reg_to_register_object($old$$reg); | |
| 2777 Register Rnew = reg_to_register_object($new$$reg); | |
| 2778 | |
| 2779 MacroAssembler _masm(&cbuf); | |
| 2780 __ mov(Rnew, O7); | |
| 2781 __ cas(Rmem, Rold, O7); | |
| 2782 __ cmp( Rold, O7 ); | |
| 2783 %} | |
| 2784 | |
| 2785 enc_class enc_lflags_ne_to_boolean( iRegI res ) %{ | |
| 2786 Register Rres = reg_to_register_object($res$$reg); | |
| 2787 | |
| 2788 MacroAssembler _masm(&cbuf); | |
| 2789 __ mov(1, Rres); | |
| 2790 __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres ); | |
| 2791 %} | |
| 2792 | |
| 2793 enc_class enc_iflags_ne_to_boolean( iRegI res ) %{ | |
| 2794 Register Rres = reg_to_register_object($res$$reg); | |
| 2795 | |
| 2796 MacroAssembler _masm(&cbuf); | |
| 2797 __ mov(1, Rres); | |
| 2798 __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres ); | |
| 2799 %} | |
| 2800 | |
| 2801 enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{ | |
| 2802 MacroAssembler _masm(&cbuf); | |
| 2803 Register Rdst = reg_to_register_object($dst$$reg); | |
| 2804 FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg) | |
| 2805 : reg_to_DoubleFloatRegister_object($src1$$reg); | |
| 2806 FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg) | |
| 2807 : reg_to_DoubleFloatRegister_object($src2$$reg); | |
| 2808 | |
| 2809 // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1) | |
| 2810 __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst); | |
| 2811 %} | |
| 2812 | |
| 2813 // Compiler ensures base is doubleword aligned and cnt is count of doublewords | |
| 2814 enc_class enc_Clear_Array(iRegX cnt, iRegP base, iRegX temp) %{ | |
| 2815 MacroAssembler _masm(&cbuf); | |
| 2816 Register nof_bytes_arg = reg_to_register_object($cnt$$reg); | |
| 2817 Register nof_bytes_tmp = reg_to_register_object($temp$$reg); | |
| 2818 Register base_pointer_arg = reg_to_register_object($base$$reg); | |
| 3854 | 2819 |
| 0 | 2820 Label loop; |
| 2821 __ mov(nof_bytes_arg, nof_bytes_tmp); | |
| 3854 | 2822 |
| 0 | 2823 // Loop and clear, walking backwards through the array. |
| 2824 // nof_bytes_tmp (if >0) is always the number of bytes to zero | |
| 2825 __ bind(loop); | |
| 2826 __ deccc(nof_bytes_tmp, 8); | |
| 2827 __ br(Assembler::greaterEqual, true, Assembler::pt, loop); | |
| 2828 __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp); | |
| 2829 // %%%% this mini-loop must not cross a cache boundary! | |
| 2830 %} | |
| 2831 | |
| 2832 | |
|
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2833 enc_class enc_String_Compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result) %{ |
| 0 | 2834 Label Ldone, Lloop; |
| 2835 MacroAssembler _masm(&cbuf); | |
| 2836 | |
| 2837 Register str1_reg = reg_to_register_object($str1$$reg); | |
| 2838 Register str2_reg = reg_to_register_object($str2$$reg); | |
|
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2839 Register cnt1_reg = reg_to_register_object($cnt1$$reg); |
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2840 Register cnt2_reg = reg_to_register_object($cnt2$$reg); |
| 0 | 2841 Register result_reg = reg_to_register_object($result$$reg); |
| 2842 | |
|
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2843 assert(result_reg != str1_reg && |
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2844 result_reg != str2_reg && |
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2845 result_reg != cnt1_reg && |
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2846 result_reg != cnt2_reg , |
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2847 "need different registers"); |
| 0 | 2848 |
| 2849 // Compute the minimum of the string lengths(str1_reg) and the | |
| 2850 // difference of the string lengths (stack) | |
| 2851 | |
| 2852 // See if the lengths are different, and calculate min in str1_reg. | |
| 2853 // Stash diff in O7 in case we need it for a tie-breaker. | |
| 2854 Label Lskip; | |
|
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2855 __ subcc(cnt1_reg, cnt2_reg, O7); |
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2856 __ sll(cnt1_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit |
| 0 | 2857 __ br(Assembler::greater, true, Assembler::pt, Lskip); |
|
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2858 // cnt2 is shorter, so use its count: |
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2859 __ delayed()->sll(cnt2_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit |
| 0 | 2860 __ bind(Lskip); |
| 2861 | |
|
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2862 // reallocate cnt1_reg, cnt2_reg, result_reg |
| 0 | 2863 // Note: limit_reg holds the string length pre-scaled by 2 |
|
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2864 Register limit_reg = cnt1_reg; |
|
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2865 Register chr2_reg = cnt2_reg; |
| 0 | 2866 Register chr1_reg = result_reg; |
|
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2867 // str{12} are the base pointers |
| 0 | 2868 |
| 2869 // Is the minimum length zero? | |
| 2870 __ cmp(limit_reg, (int)(0 * sizeof(jchar))); // use cast to resolve overloading ambiguity | |
| 2871 __ br(Assembler::equal, true, Assembler::pn, Ldone); | |
| 2872 __ delayed()->mov(O7, result_reg); // result is difference in lengths | |
| 2873 | |
| 2874 // Load first characters | |
|
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2875 __ lduh(str1_reg, 0, chr1_reg); |
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2876 __ lduh(str2_reg, 0, chr2_reg); |
| 0 | 2877 |
| 2878 // Compare first characters | |
| 2879 __ subcc(chr1_reg, chr2_reg, chr1_reg); | |
| 2880 __ br(Assembler::notZero, false, Assembler::pt, Ldone); | |
| 2881 assert(chr1_reg == result_reg, "result must be pre-placed"); | |
| 2882 __ delayed()->nop(); | |
| 2883 | |
| 2884 { | |
| 2885 // Check after comparing first character to see if strings are equivalent | |
| 2886 Label LSkip2; | |
| 2887 // Check if the strings start at same location | |
|
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2888 __ cmp(str1_reg, str2_reg); |
| 0 | 2889 __ brx(Assembler::notEqual, true, Assembler::pt, LSkip2); |
| 2890 __ delayed()->nop(); | |
| 2891 | |
| 2892 // Check if the length difference is zero (in O7) | |
| 2893 __ cmp(G0, O7); | |
| 2894 __ br(Assembler::equal, true, Assembler::pn, Ldone); | |
| 2895 __ delayed()->mov(G0, result_reg); // result is zero | |
| 2896 | |
| 2897 // Strings might not be equal | |
| 2898 __ bind(LSkip2); | |
| 2899 } | |
| 2900 | |
| 2901 __ subcc(limit_reg, 1 * sizeof(jchar), chr1_reg); | |
| 2902 __ br(Assembler::equal, true, Assembler::pn, Ldone); | |
| 2903 __ delayed()->mov(O7, result_reg); // result is difference in lengths | |
| 2904 | |
|
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2905 // Shift str1_reg and str2_reg to the end of the arrays, negate limit |
|
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2906 __ add(str1_reg, limit_reg, str1_reg); |
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2907 __ add(str2_reg, limit_reg, str2_reg); |
| 0 | 2908 __ neg(chr1_reg, limit_reg); // limit = -(limit-2) |
| 2909 | |
| 2910 // Compare the rest of the characters | |
|
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2911 __ lduh(str1_reg, limit_reg, chr1_reg); |
| 0 | 2912 __ bind(Lloop); |
|
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2913 // __ lduh(str1_reg, limit_reg, chr1_reg); // hoisted |
|
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2914 __ lduh(str2_reg, limit_reg, chr2_reg); |
| 0 | 2915 __ subcc(chr1_reg, chr2_reg, chr1_reg); |
| 2916 __ br(Assembler::notZero, false, Assembler::pt, Ldone); | |
| 2917 assert(chr1_reg == result_reg, "result must be pre-placed"); | |
| 2918 __ delayed()->inccc(limit_reg, sizeof(jchar)); | |
| 2919 // annul LDUH if branch is not taken to prevent access past end of string | |
| 2920 __ br(Assembler::notZero, true, Assembler::pt, Lloop); | |
|
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2921 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted |
| 0 | 2922 |
| 2923 // If strings are equal up to min length, return the length difference. | |
| 2924 __ mov(O7, result_reg); | |
| 2925 | |
| 2926 // Otherwise, return the difference between the first mismatched chars. | |
| 2927 __ bind(Ldone); | |
| 2928 %} | |
| 2929 | |
|
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2930 enc_class enc_String_Equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result) %{ |
|
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2931 Label Lword_loop, Lpost_word, Lchar, Lchar_loop, Ldone; |
| 681 | 2932 MacroAssembler _masm(&cbuf); |
| 2933 | |
| 2934 Register str1_reg = reg_to_register_object($str1$$reg); | |
| 2935 Register str2_reg = reg_to_register_object($str2$$reg); | |
|
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2936 Register cnt_reg = reg_to_register_object($cnt$$reg); |
|
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2937 Register tmp1_reg = O7; |
| 681 | 2938 Register result_reg = reg_to_register_object($result$$reg); |
| 2939 | |
|
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2940 assert(result_reg != str1_reg && |
|
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2941 result_reg != str2_reg && |
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2942 result_reg != cnt_reg && |
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2943 result_reg != tmp1_reg , |
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2944 "need different registers"); |
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|
2945 |
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|
2946 __ cmp(str1_reg, str2_reg); //same char[] ? |
| 681 | 2947 __ brx(Assembler::equal, true, Assembler::pn, Ldone); |
| 2948 __ delayed()->add(G0, 1, result_reg); | |
| 2949 | |
| 3839 | 2950 __ cmp_zero_and_br(Assembler::zero, cnt_reg, Ldone, true, Assembler::pn); |
|
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2951 __ delayed()->add(G0, 1, result_reg); // count == 0 |
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2952 |
| 681 | 2953 //rename registers |
|
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2954 Register limit_reg = cnt_reg; |
| 681 | 2955 Register chr1_reg = result_reg; |
|
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2956 Register chr2_reg = tmp1_reg; |
| 681 | 2957 |
| 2958 //check for alignment and position the pointers to the ends | |
|
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2959 __ or3(str1_reg, str2_reg, chr1_reg); |
|
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2960 __ andcc(chr1_reg, 0x3, chr1_reg); |
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2961 // notZero means at least one not 4-byte aligned. |
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|
2962 // We could optimize the case when both arrays are not aligned |
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2963 // but it is not frequent case and it requires additional checks. |
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2964 __ br(Assembler::notZero, false, Assembler::pn, Lchar); // char by char compare |
|
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2965 __ delayed()->sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg); // set byte count |
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2966 |
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2967 // Compare char[] arrays aligned to 4 bytes. |
|
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2968 __ char_arrays_equals(str1_reg, str2_reg, limit_reg, result_reg, |
|
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2969 chr1_reg, chr2_reg, Ldone); |
| 3839 | 2970 __ ba(Ldone); |
| 681 | 2971 __ delayed()->add(G0, 1, result_reg); |
| 2972 | |
|
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2973 // char by char compare |
| 681 | 2974 __ bind(Lchar); |
|
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2975 __ add(str1_reg, limit_reg, str1_reg); |
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2976 __ add(str2_reg, limit_reg, str2_reg); |
| 681 | 2977 __ neg(limit_reg); //negate count |
| 2978 | |
|
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|
2979 __ lduh(str1_reg, limit_reg, chr1_reg); |
|
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2980 // Lchar_loop |
| 681 | 2981 __ bind(Lchar_loop); |
|
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2982 __ lduh(str2_reg, limit_reg, chr2_reg); |
| 681 | 2983 __ cmp(chr1_reg, chr2_reg); |
| 2984 __ br(Assembler::notEqual, true, Assembler::pt, Ldone); | |
| 2985 __ delayed()->mov(G0, result_reg); //not equal | |
| 2986 __ inccc(limit_reg, sizeof(jchar)); | |
| 2987 // annul LDUH if branch is not taken to prevent access past end of string | |
|
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2988 __ br(Assembler::notZero, true, Assembler::pt, Lchar_loop); |
|
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|
2989 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted |
| 681 | 2990 |
| 2991 __ add(G0, 1, result_reg); //equal | |
| 2992 | |
| 2993 __ bind(Ldone); | |
| 2994 %} | |
| 2995 | |
|
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|
2996 enc_class enc_Array_Equals(o0RegP ary1, o1RegP ary2, g3RegP tmp1, notemp_iRegI result) %{ |
| 681 | 2997 Label Lvector, Ldone, Lloop; |
| 2998 MacroAssembler _masm(&cbuf); | |
| 2999 | |
| 3000 Register ary1_reg = reg_to_register_object($ary1$$reg); | |
| 3001 Register ary2_reg = reg_to_register_object($ary2$$reg); | |
| 3002 Register tmp1_reg = reg_to_register_object($tmp1$$reg); | |
|
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3003 Register tmp2_reg = O7; |
| 681 | 3004 Register result_reg = reg_to_register_object($result$$reg); |
| 3005 | |
| 3006 int length_offset = arrayOopDesc::length_offset_in_bytes(); | |
| 3007 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR); | |
| 3008 | |
| 3009 // return true if the same array | |
| 3010 __ cmp(ary1_reg, ary2_reg); | |
| 1016 | 3011 __ brx(Assembler::equal, true, Assembler::pn, Ldone); |
| 681 | 3012 __ delayed()->add(G0, 1, result_reg); // equal |
| 3013 | |
| 3014 __ br_null(ary1_reg, true, Assembler::pn, Ldone); | |
| 3015 __ delayed()->mov(G0, result_reg); // not equal | |
| 3016 | |
| 3017 __ br_null(ary2_reg, true, Assembler::pn, Ldone); | |
| 3018 __ delayed()->mov(G0, result_reg); // not equal | |
| 3019 | |
| 3020 //load the lengths of arrays | |
| 727 | 3021 __ ld(Address(ary1_reg, length_offset), tmp1_reg); |
| 3022 __ ld(Address(ary2_reg, length_offset), tmp2_reg); | |
| 681 | 3023 |
| 3024 // return false if the two arrays are not equal length | |
| 3025 __ cmp(tmp1_reg, tmp2_reg); | |
| 3026 __ br(Assembler::notEqual, true, Assembler::pn, Ldone); | |
| 3027 __ delayed()->mov(G0, result_reg); // not equal | |
| 3028 | |
| 3839 | 3029 __ cmp_zero_and_br(Assembler::zero, tmp1_reg, Ldone, true, Assembler::pn); |
| 681 | 3030 __ delayed()->add(G0, 1, result_reg); // zero-length arrays are equal |
| 3031 | |
| 3032 // load array addresses | |
| 3033 __ add(ary1_reg, base_offset, ary1_reg); | |
| 3034 __ add(ary2_reg, base_offset, ary2_reg); | |
| 3035 | |
| 3036 // renaming registers | |
|
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3037 Register chr1_reg = result_reg; // for characters in ary1 |
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3038 Register chr2_reg = tmp2_reg; // for characters in ary2 |
| 681 | 3039 Register limit_reg = tmp1_reg; // length |
| 3040 | |
| 3041 // set byte count | |
| 3042 __ sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg); | |
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3043 |
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3044 // Compare char[] arrays aligned to 4 bytes. |
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3045 __ char_arrays_equals(ary1_reg, ary2_reg, limit_reg, result_reg, |
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3046 chr1_reg, chr2_reg, Ldone); |
| 681 | 3047 __ add(G0, 1, result_reg); // equals |
| 3048 | |
| 3049 __ bind(Ldone); | |
| 3050 %} | |
| 3051 | |
| 0 | 3052 enc_class enc_rethrow() %{ |
| 1748 | 3053 cbuf.set_insts_mark(); |
| 0 | 3054 Register temp_reg = G3; |
| 727 | 3055 AddressLiteral rethrow_stub(OptoRuntime::rethrow_stub()); |
| 0 | 3056 assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg"); |
| 3057 MacroAssembler _masm(&cbuf); | |
| 3058 #ifdef ASSERT | |
| 3059 __ save_frame(0); | |
| 727 | 3060 AddressLiteral last_rethrow_addrlit(&last_rethrow); |
| 3061 __ sethi(last_rethrow_addrlit, L1); | |
| 3062 Address addr(L1, last_rethrow_addrlit.low10()); | |
| 0 | 3063 __ get_pc(L2); |
| 3064 __ inc(L2, 3 * BytesPerInstWord); // skip this & 2 more insns to point at jump_to | |
| 727 | 3065 __ st_ptr(L2, addr); |
| 0 | 3066 __ restore(); |
| 3067 #endif | |
| 727 | 3068 __ JUMP(rethrow_stub, temp_reg, 0); // sethi;jmp |
| 0 | 3069 __ delayed()->nop(); |
| 3070 %} | |
| 3071 | |
| 3072 enc_class emit_mem_nop() %{ | |
| 3073 // Generates the instruction LDUXA [o6,g0],#0x82,g0 | |
| 1748 | 3074 cbuf.insts()->emit_int32((unsigned int) 0xc0839040); |
| 0 | 3075 %} |
| 3076 | |
| 3077 enc_class emit_fadd_nop() %{ | |
| 3078 // Generates the instruction FMOVS f31,f31 | |
| 1748 | 3079 cbuf.insts()->emit_int32((unsigned int) 0xbfa0003f); |
| 0 | 3080 %} |
| 3081 | |
| 3082 enc_class emit_br_nop() %{ | |
| 3083 // Generates the instruction BPN,PN . | |
| 1748 | 3084 cbuf.insts()->emit_int32((unsigned int) 0x00400000); |
| 0 | 3085 %} |
| 3086 | |
| 3087 enc_class enc_membar_acquire %{ | |
| 3088 MacroAssembler _masm(&cbuf); | |
| 3089 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) ); | |
| 3090 %} | |
| 3091 | |
| 3092 enc_class enc_membar_release %{ | |
| 3093 MacroAssembler _masm(&cbuf); | |
| 3094 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) ); | |
| 3095 %} | |
| 3096 | |
| 3097 enc_class enc_membar_volatile %{ | |
| 3098 MacroAssembler _masm(&cbuf); | |
| 3099 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) ); | |
| 3100 %} | |
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3101 |
| 0 | 3102 enc_class enc_repl8b( iRegI src, iRegL dst ) %{ |
| 3103 MacroAssembler _masm(&cbuf); | |
| 3104 Register src_reg = reg_to_register_object($src$$reg); | |
| 3105 Register dst_reg = reg_to_register_object($dst$$reg); | |
| 3106 __ sllx(src_reg, 56, dst_reg); | |
| 3107 __ srlx(dst_reg, 8, O7); | |
| 3108 __ or3 (dst_reg, O7, dst_reg); | |
| 3109 __ srlx(dst_reg, 16, O7); | |
| 3110 __ or3 (dst_reg, O7, dst_reg); | |
| 3111 __ srlx(dst_reg, 32, O7); | |
| 3112 __ or3 (dst_reg, O7, dst_reg); | |
| 3113 %} | |
| 3114 | |
| 3115 enc_class enc_repl4b( iRegI src, iRegL dst ) %{ | |
| 3116 MacroAssembler _masm(&cbuf); | |
| 3117 Register src_reg = reg_to_register_object($src$$reg); | |
| 3118 Register dst_reg = reg_to_register_object($dst$$reg); | |
| 3119 __ sll(src_reg, 24, dst_reg); | |
| 3120 __ srl(dst_reg, 8, O7); | |
| 3121 __ or3(dst_reg, O7, dst_reg); | |
| 3122 __ srl(dst_reg, 16, O7); | |
| 3123 __ or3(dst_reg, O7, dst_reg); | |
| 3124 %} | |
| 3125 | |
| 3126 enc_class enc_repl4s( iRegI src, iRegL dst ) %{ | |
| 3127 MacroAssembler _masm(&cbuf); | |
| 3128 Register src_reg = reg_to_register_object($src$$reg); | |
| 3129 Register dst_reg = reg_to_register_object($dst$$reg); | |
| 3130 __ sllx(src_reg, 48, dst_reg); | |
| 3131 __ srlx(dst_reg, 16, O7); | |
| 3132 __ or3 (dst_reg, O7, dst_reg); | |
| 3133 __ srlx(dst_reg, 32, O7); | |
| 3134 __ or3 (dst_reg, O7, dst_reg); | |
| 3135 %} | |
| 3136 | |
| 3137 enc_class enc_repl2i( iRegI src, iRegL dst ) %{ | |
| 3138 MacroAssembler _masm(&cbuf); | |
| 3139 Register src_reg = reg_to_register_object($src$$reg); | |
| 3140 Register dst_reg = reg_to_register_object($dst$$reg); | |
| 3141 __ sllx(src_reg, 32, dst_reg); | |
| 3142 __ srlx(dst_reg, 32, O7); | |
| 3143 __ or3 (dst_reg, O7, dst_reg); | |
| 3144 %} | |
| 3145 | |
| 3146 %} | |
| 3147 | |
| 3148 //----------FRAME-------------------------------------------------------------- | |
| 3149 // Definition of frame structure and management information. | |
| 3150 // | |
| 3151 // S T A C K L A Y O U T Allocators stack-slot number | |
| 3152 // | (to get allocators register number | |
| 3153 // G Owned by | | v add VMRegImpl::stack0) | |
| 3154 // r CALLER | | | |
| 3155 // o | +--------+ pad to even-align allocators stack-slot | |
| 3156 // w V | pad0 | numbers; owned by CALLER | |
| 3157 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned | |
| 3158 // h ^ | in | 5 | |
| 3159 // | | args | 4 Holes in incoming args owned by SELF | |
| 3160 // | | | | 3 | |
| 3161 // | | +--------+ | |
| 3162 // V | | old out| Empty on Intel, window on Sparc | |
| 3163 // | old |preserve| Must be even aligned. | |
| 3164 // | SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned | |
| 3165 // | | in | 3 area for Intel ret address | |
| 3166 // Owned by |preserve| Empty on Sparc. | |
| 3167 // SELF +--------+ | |
| 3168 // | | pad2 | 2 pad to align old SP | |
| 3169 // | +--------+ 1 | |
| 3170 // | | locks | 0 | |
| 3171 // | +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned | |
| 3172 // | | pad1 | 11 pad to align new SP | |
| 3173 // | +--------+ | |
| 3174 // | | | 10 | |
| 3175 // | | spills | 9 spills | |
| 3176 // V | | 8 (pad0 slot for callee) | |
| 3177 // -----------+--------+----> Matcher::_out_arg_limit, unaligned | |
| 3178 // ^ | out | 7 | |
| 3179 // | | args | 6 Holes in outgoing args owned by CALLEE | |
| 3180 // Owned by +--------+ | |
| 3181 // CALLEE | new out| 6 Empty on Intel, window on Sparc | |
| 3182 // | new |preserve| Must be even-aligned. | |
| 3183 // | SP-+--------+----> Matcher::_new_SP, even aligned | |
| 3184 // | | | | |
| 3185 // | |
| 3186 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is | |
| 3187 // known from SELF's arguments and the Java calling convention. | |
| 3188 // Region 6-7 is determined per call site. | |
| 3189 // Note 2: If the calling convention leaves holes in the incoming argument | |
| 3190 // area, those holes are owned by SELF. Holes in the outgoing area | |
| 3191 // are owned by the CALLEE. Holes should not be nessecary in the | |
| 3192 // incoming area, as the Java calling convention is completely under | |
| 3193 // the control of the AD file. Doubles can be sorted and packed to | |
| 3194 // avoid holes. Holes in the outgoing arguments may be nessecary for | |
| 3195 // varargs C calling conventions. | |
| 3196 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is | |
| 3197 // even aligned with pad0 as needed. | |
| 3198 // Region 6 is even aligned. Region 6-7 is NOT even aligned; | |
| 3199 // region 6-11 is even aligned; it may be padded out more so that | |
| 3200 // the region from SP to FP meets the minimum stack alignment. | |
| 3201 | |
| 3202 frame %{ | |
| 3203 // What direction does stack grow in (assumed to be same for native & Java) | |
| 3204 stack_direction(TOWARDS_LOW); | |
| 3205 | |
| 3206 // These two registers define part of the calling convention | |
| 3207 // between compiled code and the interpreter. | |
| 3208 inline_cache_reg(R_G5); // Inline Cache Register or methodOop for I2C | |
| 3209 interpreter_method_oop_reg(R_G5); // Method Oop Register when calling interpreter | |
| 3210 | |
| 3211 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset] | |
| 3212 cisc_spilling_operand_name(indOffset); | |
| 3213 | |
| 3214 // Number of stack slots consumed by a Monitor enter | |
| 3215 #ifdef _LP64 | |
| 3216 sync_stack_slots(2); | |
| 3217 #else | |
| 3218 sync_stack_slots(1); | |
| 3219 #endif | |
| 3220 | |
| 3221 // Compiled code's Frame Pointer | |
| 3222 frame_pointer(R_SP); | |
| 3223 | |
| 3224 // Stack alignment requirement | |
| 3225 stack_alignment(StackAlignmentInBytes); | |
| 3226 // LP64: Alignment size in bytes (128-bit -> 16 bytes) | |
| 3227 // !LP64: Alignment size in bytes (64-bit -> 8 bytes) | |
| 3228 | |
| 3229 // Number of stack slots between incoming argument block and the start of | |
| 3230 // a new frame. The PROLOG must add this many slots to the stack. The | |
| 3231 // EPILOG must remove this many slots. | |
| 3232 in_preserve_stack_slots(0); | |
| 3233 | |
| 3234 // Number of outgoing stack slots killed above the out_preserve_stack_slots | |
| 3235 // for calls to C. Supports the var-args backing area for register parms. | |
| 3236 // ADLC doesn't support parsing expressions, so I folded the math by hand. | |
| 3237 #ifdef _LP64 | |
| 3238 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word | |
| 3239 varargs_C_out_slots_killed(12); | |
| 3240 #else | |
| 3241 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (1)) * 1-stack-slots-per-word | |
| 3242 varargs_C_out_slots_killed( 7); | |
| 3243 #endif | |
| 3244 | |
| 3245 // The after-PROLOG location of the return address. Location of | |
| 3246 // return address specifies a type (REG or STACK) and a number | |
| 3247 // representing the register number (i.e. - use a register name) or | |
| 3248 // stack slot. | |
| 3249 return_addr(REG R_I7); // Ret Addr is in register I7 | |
| 3250 | |
| 3251 // Body of function which returns an OptoRegs array locating | |
| 3252 // arguments either in registers or in stack slots for calling | |
| 3253 // java | |
| 3254 calling_convention %{ | |
| 3255 (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing); | |
| 3256 | |
| 3257 %} | |
| 3258 | |
| 3259 // Body of function which returns an OptoRegs array locating | |
| 3260 // arguments either in registers or in stack slots for callin | |
| 3261 // C. | |
| 3262 c_calling_convention %{ | |
| 3263 // This is obviously always outgoing | |
| 3264 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length); | |
| 3265 %} | |
| 3266 | |
| 3267 // Location of native (C/C++) and interpreter return values. This is specified to | |
| 3268 // be the same as Java. In the 32-bit VM, long values are actually returned from | |
| 3269 // native calls in O0:O1 and returned to the interpreter in I0:I1. The copying | |
| 3270 // to and from the register pairs is done by the appropriate call and epilog | |
| 3271 // opcodes. This simplifies the register allocator. | |
| 3272 c_return_value %{ | |
| 3273 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); | |
| 3274 #ifdef _LP64 | |
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3275 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num }; |
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3276 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num}; |
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3277 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num }; |
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3278 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num}; |
| 0 | 3279 #else // !_LP64 |
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3280 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num }; |
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3281 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num }; |
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3282 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num }; |
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3283 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num }; |
| 0 | 3284 #endif |
| 3285 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg], | |
| 3286 (is_outgoing?lo_out:lo_in)[ideal_reg] ); | |
| 3287 %} | |
| 3288 | |
| 3289 // Location of compiled Java return values. Same as C | |
| 3290 return_value %{ | |
| 3291 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); | |
| 3292 #ifdef _LP64 | |
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3293 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num }; |
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3294 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num}; |
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3295 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num }; |
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3296 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num}; |
| 0 | 3297 #else // !_LP64 |
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3298 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num }; |
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3299 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num}; |
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3300 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num }; |
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3301 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num}; |
| 0 | 3302 #endif |
| 3303 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg], | |
| 3304 (is_outgoing?lo_out:lo_in)[ideal_reg] ); | |
| 3305 %} | |
| 3306 | |
| 3307 %} | |
| 3308 | |
| 3309 | |
| 3310 //----------ATTRIBUTES--------------------------------------------------------- | |
| 3311 //----------Operand Attributes------------------------------------------------- | |
| 3312 op_attrib op_cost(1); // Required cost attribute | |
| 3313 | |
| 3314 //----------Instruction Attributes--------------------------------------------- | |
| 3315 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute | |
| 3842 | 3316 ins_attrib ins_size(32); // Required size attribute (in bits) |
| 3851 | 3317 ins_attrib ins_avoid_back_to_back(0); // instruction should not be generated back to back |
| 3842 | 3318 ins_attrib ins_short_branch(0); // Required flag: is this instruction a |
| 3319 // non-matching short branch variant of some | |
| 0 | 3320 // long branch? |
| 3321 | |
| 3322 //----------OPERANDS----------------------------------------------------------- | |
| 3323 // Operand definitions must precede instruction definitions for correct parsing | |
| 3324 // in the ADLC because operands constitute user defined types which are used in | |
| 3325 // instruction definitions. | |
| 3326 | |
| 3327 //----------Simple Operands---------------------------------------------------- | |
| 3328 // Immediate Operands | |
| 3329 // Integer Immediate: 32-bit | |
| 3330 operand immI() %{ | |
| 3331 match(ConI); | |
| 3332 | |
| 3333 op_cost(0); | |
| 3334 // formats are generated automatically for constants and base registers | |
| 3335 format %{ %} | |
| 3336 interface(CONST_INTER); | |
| 3337 %} | |
| 3338 | |
| 824 | 3339 // Integer Immediate: 8-bit |
| 3340 operand immI8() %{ | |
| 3341 predicate(Assembler::is_simm(n->get_int(), 8)); | |
| 3342 match(ConI); | |
| 3343 op_cost(0); | |
| 3344 format %{ %} | |
| 3345 interface(CONST_INTER); | |
| 3346 %} | |
| 3347 | |
| 0 | 3348 // Integer Immediate: 13-bit |
| 3349 operand immI13() %{ | |
| 3350 predicate(Assembler::is_simm13(n->get_int())); | |
| 3351 match(ConI); | |
| 3352 op_cost(0); | |
| 3353 | |
| 3354 format %{ %} | |
| 3355 interface(CONST_INTER); | |
| 3356 %} | |
| 3357 | |
| 785 | 3358 // Integer Immediate: 13-bit minus 7 |
| 3359 operand immI13m7() %{ | |
| 3360 predicate((-4096 < n->get_int()) && ((n->get_int() + 7) <= 4095)); | |
| 3361 match(ConI); | |
| 3362 op_cost(0); | |
| 3363 | |
| 3364 format %{ %} | |
| 3365 interface(CONST_INTER); | |
| 3366 %} | |
| 3367 | |
| 824 | 3368 // Integer Immediate: 16-bit |
| 3369 operand immI16() %{ | |
| 3370 predicate(Assembler::is_simm(n->get_int(), 16)); | |
| 3371 match(ConI); | |
| 3372 op_cost(0); | |
| 3373 format %{ %} | |
| 3374 interface(CONST_INTER); | |
| 3375 %} | |
| 3376 | |
| 0 | 3377 // Unsigned (positive) Integer Immediate: 13-bit |
| 3378 operand immU13() %{ | |
| 3379 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int())); | |
| 3380 match(ConI); | |
| 3381 op_cost(0); | |
| 3382 | |
| 3383 format %{ %} | |
| 3384 interface(CONST_INTER); | |
| 3385 %} | |
| 3386 | |
| 3387 // Integer Immediate: 6-bit | |
| 3388 operand immU6() %{ | |
| 3389 predicate(n->get_int() >= 0 && n->get_int() <= 63); | |
| 3390 match(ConI); | |
| 3391 op_cost(0); | |
| 3392 format %{ %} | |
| 3393 interface(CONST_INTER); | |
| 3394 %} | |
| 3395 | |
| 3396 // Integer Immediate: 11-bit | |
| 3397 operand immI11() %{ | |
| 3398 predicate(Assembler::is_simm(n->get_int(),11)); | |
| 3399 match(ConI); | |
| 3400 op_cost(0); | |
| 3401 format %{ %} | |
| 3402 interface(CONST_INTER); | |
| 3403 %} | |
| 3404 | |
| 3851 | 3405 // Integer Immediate: 5-bit |
| 3406 operand immI5() %{ | |
| 3407 predicate(Assembler::is_simm(n->get_int(), 5)); | |
| 3408 match(ConI); | |
| 3409 op_cost(0); | |
| 3410 format %{ %} | |
| 3411 interface(CONST_INTER); | |
| 3412 %} | |
| 3413 | |
| 0 | 3414 // Integer Immediate: 0-bit |
| 3415 operand immI0() %{ | |
| 3416 predicate(n->get_int() == 0); | |
| 3417 match(ConI); | |
| 3418 op_cost(0); | |
| 3419 | |
| 3420 format %{ %} | |
| 3421 interface(CONST_INTER); | |
| 3422 %} | |
| 3423 | |
| 3424 // Integer Immediate: the value 10 | |
| 3425 operand immI10() %{ | |
| 3426 predicate(n->get_int() == 10); | |
| 3427 match(ConI); | |
| 3428 op_cost(0); | |
| 3429 | |
| 3430 format %{ %} | |
| 3431 interface(CONST_INTER); | |
| 3432 %} | |
| 3433 | |
| 3434 // Integer Immediate: the values 0-31 | |
| 3435 operand immU5() %{ | |
| 3436 predicate(n->get_int() >= 0 && n->get_int() <= 31); | |
| 3437 match(ConI); | |
| 3438 op_cost(0); | |
| 3439 | |
| 3440 format %{ %} | |
| 3441 interface(CONST_INTER); | |
| 3442 %} | |
| 3443 | |
| 3444 // Integer Immediate: the values 1-31 | |
| 3445 operand immI_1_31() %{ | |
| 3446 predicate(n->get_int() >= 1 && n->get_int() <= 31); | |
| 3447 match(ConI); | |
| 3448 op_cost(0); | |
| 3449 | |
| 3450 format %{ %} | |
| 3451 interface(CONST_INTER); | |
| 3452 %} | |
| 3453 | |
| 3454 // Integer Immediate: the values 32-63 | |
| 3455 operand immI_32_63() %{ | |
| 3456 predicate(n->get_int() >= 32 && n->get_int() <= 63); | |
| 3457 match(ConI); | |
| 3458 op_cost(0); | |
| 3459 | |
| 3460 format %{ %} | |
| 3461 interface(CONST_INTER); | |
| 3462 %} | |
| 3463 | |
| 785 | 3464 // Immediates for special shifts (sign extend) |
| 3465 | |
| 3466 // Integer Immediate: the value 16 | |
| 3467 operand immI_16() %{ | |
| 3468 predicate(n->get_int() == 16); | |
| 3469 match(ConI); | |
| 3470 op_cost(0); | |
| 3471 | |
| 3472 format %{ %} | |
| 3473 interface(CONST_INTER); | |
| 3474 %} | |
| 3475 | |
| 3476 // Integer Immediate: the value 24 | |
| 3477 operand immI_24() %{ | |
| 3478 predicate(n->get_int() == 24); | |
| 3479 match(ConI); | |
| 3480 op_cost(0); | |
| 3481 | |
| 3482 format %{ %} | |
| 3483 interface(CONST_INTER); | |
| 3484 %} | |
| 3485 | |
| 0 | 3486 // Integer Immediate: the value 255 |
| 3487 operand immI_255() %{ | |
| 3488 predicate( n->get_int() == 255 ); | |
| 3489 match(ConI); | |
| 3490 op_cost(0); | |
| 3491 | |
| 3492 format %{ %} | |
| 3493 interface(CONST_INTER); | |
| 3494 %} | |
| 3495 | |
| 785 | 3496 // Integer Immediate: the value 65535 |
| 3497 operand immI_65535() %{ | |
| 3498 predicate(n->get_int() == 65535); | |
| 3499 match(ConI); | |
| 3500 op_cost(0); | |
| 3501 | |
| 3502 format %{ %} | |
| 3503 interface(CONST_INTER); | |
| 3504 %} | |
| 3505 | |
| 0 | 3506 // Long Immediate: the value FF |
| 3507 operand immL_FF() %{ | |
| 3508 predicate( n->get_long() == 0xFFL ); | |
| 3509 match(ConL); | |
| 3510 op_cost(0); | |
| 3511 | |
| 3512 format %{ %} | |
| 3513 interface(CONST_INTER); | |
| 3514 %} | |
| 3515 | |
| 3516 // Long Immediate: the value FFFF | |
| 3517 operand immL_FFFF() %{ | |
| 3518 predicate( n->get_long() == 0xFFFFL ); | |
| 3519 match(ConL); | |
| 3520 op_cost(0); | |
| 3521 | |
| 3522 format %{ %} | |
| 3523 interface(CONST_INTER); | |
| 3524 %} | |
| 3525 | |
| 3526 // Pointer Immediate: 32 or 64-bit | |
| 3527 operand immP() %{ | |
| 3528 match(ConP); | |
| 3529 | |
| 3530 op_cost(5); | |
| 3531 // formats are generated automatically for constants and base registers | |
| 3532 format %{ %} | |
| 3533 interface(CONST_INTER); | |
| 3534 %} | |
| 3535 | |
|
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3536 #ifdef _LP64 |
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3537 // Pointer Immediate: 64-bit |
| 2008 | 3538 operand immP_set() %{ |
| 2080 | 3539 predicate(!VM_Version::is_niagara_plus()); |
| 2008 | 3540 match(ConP); |
| 3541 | |
| 3542 op_cost(5); | |
| 3543 // formats are generated automatically for constants and base registers | |
| 3544 format %{ %} | |
| 3545 interface(CONST_INTER); | |
| 3546 %} | |
| 3547 | |
|
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3548 // Pointer Immediate: 64-bit |
| 2008 | 3549 // From Niagara2 processors on a load should be better than materializing. |
| 3550 operand immP_load() %{ | |
| 2080 | 3551 predicate(VM_Version::is_niagara_plus() && (n->bottom_type()->isa_oop_ptr() || (MacroAssembler::insts_for_set(n->get_ptr()) > 3))); |
| 2008 | 3552 match(ConP); |
| 3553 | |
| 3554 op_cost(5); | |
| 3555 // formats are generated automatically for constants and base registers | |
| 3556 format %{ %} | |
| 3557 interface(CONST_INTER); | |
| 3558 %} | |
| 3559 | |
|
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3560 // Pointer Immediate: 64-bit |
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3561 operand immP_no_oop_cheap() %{ |
| 2080 | 3562 predicate(VM_Version::is_niagara_plus() && !n->bottom_type()->isa_oop_ptr() && (MacroAssembler::insts_for_set(n->get_ptr()) <= 3)); |
|
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3563 match(ConP); |
|
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3564 |
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3565 op_cost(5); |
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3566 // formats are generated automatically for constants and base registers |
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3567 format %{ %} |
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3568 interface(CONST_INTER); |
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3569 %} |
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3570 #endif |
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3571 |
| 0 | 3572 operand immP13() %{ |
| 3573 predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095)); | |
| 3574 match(ConP); | |
| 3575 op_cost(0); | |
| 3576 | |
| 3577 format %{ %} | |
| 3578 interface(CONST_INTER); | |
| 3579 %} | |
| 3580 | |
| 3581 operand immP0() %{ | |
| 3582 predicate(n->get_ptr() == 0); | |
| 3583 match(ConP); | |
| 3584 op_cost(0); | |
| 3585 | |
| 3586 format %{ %} | |
| 3587 interface(CONST_INTER); | |
| 3588 %} | |
| 3589 | |
| 3590 operand immP_poll() %{ | |
| 3591 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page()); | |
| 3592 match(ConP); | |
| 3593 | |
| 3594 // formats are generated automatically for constants and base registers | |
| 3595 format %{ %} | |
| 3596 interface(CONST_INTER); | |
| 3597 %} | |
| 3598 | |
|
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3599 // Pointer Immediate |
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3600 operand immN() |
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3601 %{ |
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3602 match(ConN); |
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3603 |
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3604 op_cost(10); |
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3605 format %{ %} |
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3606 interface(CONST_INTER); |
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3607 %} |
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3608 |
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3609 // NULL Pointer Immediate |
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3610 operand immN0() |
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3611 %{ |
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3612 predicate(n->get_narrowcon() == 0); |
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3613 match(ConN); |
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3614 |
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3615 op_cost(0); |
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3616 format %{ %} |
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3617 interface(CONST_INTER); |
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3618 %} |
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3619 |
| 0 | 3620 operand immL() %{ |
| 3621 match(ConL); | |
| 3622 op_cost(40); | |
| 3623 // formats are generated automatically for constants and base registers | |
| 3624 format %{ %} | |
| 3625 interface(CONST_INTER); | |
| 3626 %} | |
| 3627 | |
| 3628 operand immL0() %{ | |
| 3629 predicate(n->get_long() == 0L); | |
| 3630 match(ConL); | |
| 3631 op_cost(0); | |
| 3632 // formats are generated automatically for constants and base registers | |
| 3633 format %{ %} | |
| 3634 interface(CONST_INTER); | |
| 3635 %} | |
| 3636 | |
| 3851 | 3637 // Integer Immediate: 5-bit |
| 3638 operand immL5() %{ | |
| 3639 predicate(n->get_long() == (int)n->get_long() && Assembler::is_simm((int)n->get_long(), 5)); | |
| 3640 match(ConL); | |
| 3641 op_cost(0); | |
| 3642 format %{ %} | |
| 3643 interface(CONST_INTER); | |
| 3644 %} | |
| 3645 | |
| 0 | 3646 // Long Immediate: 13-bit |
| 3647 operand immL13() %{ | |
| 3648 predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L)); | |
| 3649 match(ConL); | |
| 3650 op_cost(0); | |
| 3651 | |
| 3652 format %{ %} | |
| 3653 interface(CONST_INTER); | |
| 3654 %} | |
| 3655 | |
| 785 | 3656 // Long Immediate: 13-bit minus 7 |
| 3657 operand immL13m7() %{ | |
| 3658 predicate((-4096L < n->get_long()) && ((n->get_long() + 7L) <= 4095L)); | |
| 3659 match(ConL); | |
| 3660 op_cost(0); | |
| 3661 | |
| 3662 format %{ %} | |
| 3663 interface(CONST_INTER); | |
| 3664 %} | |
| 3665 | |
| 0 | 3666 // Long Immediate: low 32-bit mask |
| 3667 operand immL_32bits() %{ | |
| 3668 predicate(n->get_long() == 0xFFFFFFFFL); | |
| 3669 match(ConL); | |
| 3670 op_cost(0); | |
| 3671 | |
| 3672 format %{ %} | |
| 3673 interface(CONST_INTER); | |
| 3674 %} | |
| 3675 | |
| 2008 | 3676 // Long Immediate: cheap (materialize in <= 3 instructions) |
| 3677 operand immL_cheap() %{ | |
| 2080 | 3678 predicate(!VM_Version::is_niagara_plus() || MacroAssembler::insts_for_set64(n->get_long()) <= 3); |
| 2008 | 3679 match(ConL); |
| 3680 op_cost(0); | |
| 3681 | |
| 3682 format %{ %} | |
| 3683 interface(CONST_INTER); | |
| 3684 %} | |
| 3685 | |
| 3686 // Long Immediate: expensive (materialize in > 3 instructions) | |
| 3687 operand immL_expensive() %{ | |
| 2080 | 3688 predicate(VM_Version::is_niagara_plus() && MacroAssembler::insts_for_set64(n->get_long()) > 3); |
| 2008 | 3689 match(ConL); |
| 3690 op_cost(0); | |
| 3691 | |
| 3692 format %{ %} | |
| 3693 interface(CONST_INTER); | |
| 3694 %} | |
| 3695 | |
| 0 | 3696 // Double Immediate |
| 3697 operand immD() %{ | |
| 3698 match(ConD); | |
| 3699 | |
| 3700 op_cost(40); | |
| 3701 format %{ %} | |
| 3702 interface(CONST_INTER); | |
| 3703 %} | |
| 3704 | |
| 3705 operand immD0() %{ | |
| 3706 #ifdef _LP64 | |
| 3707 // on 64-bit architectures this comparision is faster | |
| 3708 predicate(jlong_cast(n->getd()) == 0); | |
| 3709 #else | |
| 3710 predicate((n->getd() == 0) && (fpclass(n->getd()) == FP_PZERO)); | |
| 3711 #endif | |
| 3712 match(ConD); | |
| 3713 | |
| 3714 op_cost(0); | |
| 3715 format %{ %} | |
| 3716 interface(CONST_INTER); | |
| 3717 %} | |
| 3718 | |
| 3719 // Float Immediate | |
| 3720 operand immF() %{ | |
| 3721 match(ConF); | |
| 3722 | |
| 3723 op_cost(20); | |
| 3724 format %{ %} | |
| 3725 interface(CONST_INTER); | |
| 3726 %} | |
| 3727 | |
| 3728 // Float Immediate: 0 | |
| 3729 operand immF0() %{ | |
| 3730 predicate((n->getf() == 0) && (fpclass(n->getf()) == FP_PZERO)); | |
| 3731 match(ConF); | |
| 3732 | |
| 3733 op_cost(0); | |
| 3734 format %{ %} | |
| 3735 interface(CONST_INTER); | |
| 3736 %} | |
| 3737 | |
| 3738 // Integer Register Operands | |
| 3739 // Integer Register | |
| 3740 operand iRegI() %{ | |
| 3741 constraint(ALLOC_IN_RC(int_reg)); | |
| 3742 match(RegI); | |
| 3743 | |
| 3744 match(notemp_iRegI); | |
| 3745 match(g1RegI); | |
| 3746 match(o0RegI); | |
| 3747 match(iRegIsafe); | |
| 3748 | |
| 3749 format %{ %} | |
| 3750 interface(REG_INTER); | |
| 3751 %} | |
| 3752 | |
| 3753 operand notemp_iRegI() %{ | |
| 3754 constraint(ALLOC_IN_RC(notemp_int_reg)); | |
| 3755 match(RegI); | |
| 3756 | |
| 3757 match(o0RegI); | |
| 3758 | |
| 3759 format %{ %} | |
| 3760 interface(REG_INTER); | |
| 3761 %} | |
| 3762 | |
| 3763 operand o0RegI() %{ | |
| 3764 constraint(ALLOC_IN_RC(o0_regI)); | |
| 3765 match(iRegI); | |
| 3766 | |
| 3767 format %{ %} | |
| 3768 interface(REG_INTER); | |
| 3769 %} | |
| 3770 | |
| 3771 // Pointer Register | |
| 3772 operand iRegP() %{ | |
| 3773 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 3774 match(RegP); | |
| 3775 | |
| 3776 match(lock_ptr_RegP); | |
| 3777 match(g1RegP); | |
| 3778 match(g2RegP); | |
| 3779 match(g3RegP); | |
| 3780 match(g4RegP); | |
| 3781 match(i0RegP); | |
| 3782 match(o0RegP); | |
| 3783 match(o1RegP); | |
| 3784 match(l7RegP); | |
| 3785 | |
| 3786 format %{ %} | |
| 3787 interface(REG_INTER); | |
| 3788 %} | |
| 3789 | |
| 3790 operand sp_ptr_RegP() %{ | |
| 3791 constraint(ALLOC_IN_RC(sp_ptr_reg)); | |
| 3792 match(RegP); | |
| 3793 match(iRegP); | |
| 3794 | |
| 3795 format %{ %} | |
| 3796 interface(REG_INTER); | |
| 3797 %} | |
| 3798 | |
| 3799 operand lock_ptr_RegP() %{ | |
| 3800 constraint(ALLOC_IN_RC(lock_ptr_reg)); | |
| 3801 match(RegP); | |
| 3802 match(i0RegP); | |
| 3803 match(o0RegP); | |
| 3804 match(o1RegP); | |
| 3805 match(l7RegP); | |
| 3806 | |
| 3807 format %{ %} | |
| 3808 interface(REG_INTER); | |
| 3809 %} | |
| 3810 | |
| 3811 operand g1RegP() %{ | |
| 3812 constraint(ALLOC_IN_RC(g1_regP)); | |
| 3813 match(iRegP); | |
| 3814 | |
| 3815 format %{ %} | |
| 3816 interface(REG_INTER); | |
| 3817 %} | |
| 3818 | |
| 3819 operand g2RegP() %{ | |
| 3820 constraint(ALLOC_IN_RC(g2_regP)); | |
| 3821 match(iRegP); | |
| 3822 | |
| 3823 format %{ %} | |
| 3824 interface(REG_INTER); | |
| 3825 %} | |
| 3826 | |
| 3827 operand g3RegP() %{ | |
| 3828 constraint(ALLOC_IN_RC(g3_regP)); | |
| 3829 match(iRegP); | |
| 3830 | |
| 3831 format %{ %} | |
| 3832 interface(REG_INTER); | |
| 3833 %} | |
| 3834 | |
| 3835 operand g1RegI() %{ | |
| 3836 constraint(ALLOC_IN_RC(g1_regI)); | |
| 3837 match(iRegI); | |
| 3838 | |
| 3839 format %{ %} | |
| 3840 interface(REG_INTER); | |
| 3841 %} | |
| 3842 | |
| 3843 operand g3RegI() %{ | |
| 3844 constraint(ALLOC_IN_RC(g3_regI)); | |
| 3845 match(iRegI); | |
| 3846 | |
| 3847 format %{ %} | |
| 3848 interface(REG_INTER); | |
| 3849 %} | |
| 3850 | |
| 3851 operand g4RegI() %{ | |
| 3852 constraint(ALLOC_IN_RC(g4_regI)); | |
| 3853 match(iRegI); | |
| 3854 | |
| 3855 format %{ %} | |
| 3856 interface(REG_INTER); | |
| 3857 %} | |
| 3858 | |
| 3859 operand g4RegP() %{ | |
| 3860 constraint(ALLOC_IN_RC(g4_regP)); | |
| 3861 match(iRegP); | |
| 3862 | |
| 3863 format %{ %} | |
| 3864 interface(REG_INTER); | |
| 3865 %} | |
| 3866 | |
| 3867 operand i0RegP() %{ | |
| 3868 constraint(ALLOC_IN_RC(i0_regP)); | |
| 3869 match(iRegP); | |
| 3870 | |
| 3871 format %{ %} | |
| 3872 interface(REG_INTER); | |
| 3873 %} | |
| 3874 | |
| 3875 operand o0RegP() %{ | |
| 3876 constraint(ALLOC_IN_RC(o0_regP)); | |
| 3877 match(iRegP); | |
| 3878 | |
| 3879 format %{ %} | |
| 3880 interface(REG_INTER); | |
| 3881 %} | |
| 3882 | |
| 3883 operand o1RegP() %{ | |
| 3884 constraint(ALLOC_IN_RC(o1_regP)); | |
| 3885 match(iRegP); | |
| 3886 | |
| 3887 format %{ %} | |
| 3888 interface(REG_INTER); | |
| 3889 %} | |
| 3890 | |
| 3891 operand o2RegP() %{ | |
| 3892 constraint(ALLOC_IN_RC(o2_regP)); | |
| 3893 match(iRegP); | |
| 3894 | |
| 3895 format %{ %} | |
| 3896 interface(REG_INTER); | |
| 3897 %} | |
| 3898 | |
| 3899 operand o7RegP() %{ | |
| 3900 constraint(ALLOC_IN_RC(o7_regP)); | |
| 3901 match(iRegP); | |
| 3902 | |
| 3903 format %{ %} | |
| 3904 interface(REG_INTER); | |
| 3905 %} | |
| 3906 | |
| 3907 operand l7RegP() %{ | |
| 3908 constraint(ALLOC_IN_RC(l7_regP)); | |
| 3909 match(iRegP); | |
| 3910 | |
| 3911 format %{ %} | |
| 3912 interface(REG_INTER); | |
| 3913 %} | |
| 3914 | |
| 3915 operand o7RegI() %{ | |
| 3916 constraint(ALLOC_IN_RC(o7_regI)); | |
| 3917 match(iRegI); | |
| 3918 | |
| 3919 format %{ %} | |
| 3920 interface(REG_INTER); | |
| 3921 %} | |
| 3922 | |
|
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3923 operand iRegN() %{ |
|
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3924 constraint(ALLOC_IN_RC(int_reg)); |
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3925 match(RegN); |
|
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3926 |
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3927 format %{ %} |
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3928 interface(REG_INTER); |
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3929 %} |
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|
3930 |
| 0 | 3931 // Long Register |
| 3932 operand iRegL() %{ | |
| 3933 constraint(ALLOC_IN_RC(long_reg)); | |
| 3934 match(RegL); | |
| 3935 | |
| 3936 format %{ %} | |
| 3937 interface(REG_INTER); | |
| 3938 %} | |
| 3939 | |
| 3940 operand o2RegL() %{ | |
| 3941 constraint(ALLOC_IN_RC(o2_regL)); | |
| 3942 match(iRegL); | |
| 3943 | |
| 3944 format %{ %} | |
| 3945 interface(REG_INTER); | |
| 3946 %} | |
| 3947 | |
| 3948 operand o7RegL() %{ | |
| 3949 constraint(ALLOC_IN_RC(o7_regL)); | |
| 3950 match(iRegL); | |
| 3951 | |
| 3952 format %{ %} | |
| 3953 interface(REG_INTER); | |
| 3954 %} | |
| 3955 | |
| 3956 operand g1RegL() %{ | |
| 3957 constraint(ALLOC_IN_RC(g1_regL)); | |
| 3958 match(iRegL); | |
| 3959 | |
| 3960 format %{ %} | |
| 3961 interface(REG_INTER); | |
| 3962 %} | |
| 3963 | |
|
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3964 operand g3RegL() %{ |
|
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3965 constraint(ALLOC_IN_RC(g3_regL)); |
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3966 match(iRegL); |
|
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|
3967 |
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3968 format %{ %} |
|
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3969 interface(REG_INTER); |
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3970 %} |
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|
3971 |
| 0 | 3972 // Int Register safe |
| 3973 // This is 64bit safe | |
| 3974 operand iRegIsafe() %{ | |
| 3975 constraint(ALLOC_IN_RC(long_reg)); | |
| 3976 | |
| 3977 match(iRegI); | |
| 3978 | |
| 3979 format %{ %} | |
| 3980 interface(REG_INTER); | |
| 3981 %} | |
| 3982 | |
| 3983 // Condition Code Flag Register | |
| 3984 operand flagsReg() %{ | |
| 3985 constraint(ALLOC_IN_RC(int_flags)); | |
| 3986 match(RegFlags); | |
| 3987 | |
| 3988 format %{ "ccr" %} // both ICC and XCC | |
| 3989 interface(REG_INTER); | |
| 3990 %} | |
| 3991 | |
| 3992 // Condition Code Register, unsigned comparisons. | |
| 3993 operand flagsRegU() %{ | |
| 3994 constraint(ALLOC_IN_RC(int_flags)); | |
| 3995 match(RegFlags); | |
| 3996 | |
| 3997 format %{ "icc_U" %} | |
| 3998 interface(REG_INTER); | |
| 3999 %} | |
| 4000 | |
| 4001 // Condition Code Register, pointer comparisons. | |
| 4002 operand flagsRegP() %{ | |
| 4003 constraint(ALLOC_IN_RC(int_flags)); | |
| 4004 match(RegFlags); | |
| 4005 | |
| 4006 #ifdef _LP64 | |
| 4007 format %{ "xcc_P" %} | |
| 4008 #else | |
| 4009 format %{ "icc_P" %} | |
| 4010 #endif | |
| 4011 interface(REG_INTER); | |
| 4012 %} | |
| 4013 | |
| 4014 // Condition Code Register, long comparisons. | |
| 4015 operand flagsRegL() %{ | |
| 4016 constraint(ALLOC_IN_RC(int_flags)); | |
| 4017 match(RegFlags); | |
| 4018 | |
| 4019 format %{ "xcc_L" %} | |
| 4020 interface(REG_INTER); | |
| 4021 %} | |
| 4022 | |
| 4023 // Condition Code Register, floating comparisons, unordered same as "less". | |
| 4024 operand flagsRegF() %{ | |
| 4025 constraint(ALLOC_IN_RC(float_flags)); | |
| 4026 match(RegFlags); | |
| 4027 match(flagsRegF0); | |
| 4028 | |
| 4029 format %{ %} | |
| 4030 interface(REG_INTER); | |
| 4031 %} | |
| 4032 | |
| 4033 operand flagsRegF0() %{ | |
| 4034 constraint(ALLOC_IN_RC(float_flag0)); | |
| 4035 match(RegFlags); | |
| 4036 | |
| 4037 format %{ %} | |
| 4038 interface(REG_INTER); | |
| 4039 %} | |
| 4040 | |
| 4041 | |
| 4042 // Condition Code Flag Register used by long compare | |
| 4043 operand flagsReg_long_LTGE() %{ | |
| 4044 constraint(ALLOC_IN_RC(int_flags)); | |
| 4045 match(RegFlags); | |
| 4046 format %{ "icc_LTGE" %} | |
| 4047 interface(REG_INTER); | |
| 4048 %} | |
| 4049 operand flagsReg_long_EQNE() %{ | |
| 4050 constraint(ALLOC_IN_RC(int_flags)); | |
| 4051 match(RegFlags); | |
| 4052 format %{ "icc_EQNE" %} | |
| 4053 interface(REG_INTER); | |
| 4054 %} | |
| 4055 operand flagsReg_long_LEGT() %{ | |
| 4056 constraint(ALLOC_IN_RC(int_flags)); | |
| 4057 match(RegFlags); | |
| 4058 format %{ "icc_LEGT" %} | |
| 4059 interface(REG_INTER); | |
| 4060 %} | |
| 4061 | |
| 4062 | |
| 4063 operand regD() %{ | |
| 4064 constraint(ALLOC_IN_RC(dflt_reg)); | |
| 4065 match(RegD); | |
| 4066 | |
| 551 | 4067 match(regD_low); |
| 4068 | |
| 0 | 4069 format %{ %} |
| 4070 interface(REG_INTER); | |
| 4071 %} | |
| 4072 | |
| 4073 operand regF() %{ | |
| 4074 constraint(ALLOC_IN_RC(sflt_reg)); | |
| 4075 match(RegF); | |
| 4076 | |
| 4077 format %{ %} | |
| 4078 interface(REG_INTER); | |
| 4079 %} | |
| 4080 | |
| 4081 operand regD_low() %{ | |
| 4082 constraint(ALLOC_IN_RC(dflt_low_reg)); | |
| 551 | 4083 match(regD); |
| 0 | 4084 |
| 4085 format %{ %} | |
| 4086 interface(REG_INTER); | |
| 4087 %} | |
| 4088 | |
| 4089 // Special Registers | |
| 4090 | |
| 4091 // Method Register | |
| 4092 operand inline_cache_regP(iRegP reg) %{ | |
| 4093 constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1 | |
| 4094 match(reg); | |
| 4095 format %{ %} | |
| 4096 interface(REG_INTER); | |
| 4097 %} | |
| 4098 | |
| 4099 operand interpreter_method_oop_regP(iRegP reg) %{ | |
| 4100 constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1 | |
| 4101 match(reg); | |
| 4102 format %{ %} | |
| 4103 interface(REG_INTER); | |
| 4104 %} | |
| 4105 | |
| 4106 | |
| 4107 //----------Complex Operands--------------------------------------------------- | |
| 4108 // Indirect Memory Reference | |
| 4109 operand indirect(sp_ptr_RegP reg) %{ | |
| 4110 constraint(ALLOC_IN_RC(sp_ptr_reg)); | |
| 4111 match(reg); | |
| 4112 | |
| 4113 op_cost(100); | |
| 4114 format %{ "[$reg]" %} | |
| 4115 interface(MEMORY_INTER) %{ | |
| 4116 base($reg); | |
| 4117 index(0x0); | |
| 4118 scale(0x0); | |
| 4119 disp(0x0); | |
| 4120 %} | |
| 4121 %} | |
| 4122 | |
| 785 | 4123 // Indirect with simm13 Offset |
| 0 | 4124 operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{ |
| 4125 constraint(ALLOC_IN_RC(sp_ptr_reg)); | |
| 4126 match(AddP reg offset); | |
| 4127 | |
| 4128 op_cost(100); | |
| 4129 format %{ "[$reg + $offset]" %} | |
| 4130 interface(MEMORY_INTER) %{ | |
| 4131 base($reg); | |
| 4132 index(0x0); | |
| 4133 scale(0x0); | |
| 4134 disp($offset); | |
| 4135 %} | |
| 4136 %} | |
| 4137 | |
| 785 | 4138 // Indirect with simm13 Offset minus 7 |
| 4139 operand indOffset13m7(sp_ptr_RegP reg, immX13m7 offset) %{ | |
| 4140 constraint(ALLOC_IN_RC(sp_ptr_reg)); | |
| 4141 match(AddP reg offset); | |
| 4142 | |
| 4143 op_cost(100); | |
| 4144 format %{ "[$reg + $offset]" %} | |
| 4145 interface(MEMORY_INTER) %{ | |
| 4146 base($reg); | |
| 4147 index(0x0); | |
| 4148 scale(0x0); | |
| 4149 disp($offset); | |
| 4150 %} | |
| 4151 %} | |
| 4152 | |
| 0 | 4153 // Note: Intel has a swapped version also, like this: |
| 4154 //operand indOffsetX(iRegI reg, immP offset) %{ | |
| 4155 // constraint(ALLOC_IN_RC(int_reg)); | |
| 4156 // match(AddP offset reg); | |
| 4157 // | |
| 4158 // op_cost(100); | |
| 4159 // format %{ "[$reg + $offset]" %} | |
| 4160 // interface(MEMORY_INTER) %{ | |
| 4161 // base($reg); | |
| 4162 // index(0x0); | |
| 4163 // scale(0x0); | |
| 4164 // disp($offset); | |
| 4165 // %} | |
| 4166 //%} | |
| 4167 //// However, it doesn't make sense for SPARC, since | |
| 4168 // we have no particularly good way to embed oops in | |
| 4169 // single instructions. | |
| 4170 | |
| 4171 // Indirect with Register Index | |
| 4172 operand indIndex(iRegP addr, iRegX index) %{ | |
| 4173 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 4174 match(AddP addr index); | |
| 4175 | |
| 4176 op_cost(100); | |
| 4177 format %{ "[$addr + $index]" %} | |
| 4178 interface(MEMORY_INTER) %{ | |
| 4179 base($addr); | |
| 4180 index($index); | |
| 4181 scale(0x0); | |
| 4182 disp(0x0); | |
| 4183 %} | |
| 4184 %} | |
| 4185 | |
| 4186 //----------Special Memory Operands-------------------------------------------- | |
| 4187 // Stack Slot Operand - This operand is used for loading and storing temporary | |
| 4188 // values on the stack where a match requires a value to | |
| 4189 // flow through memory. | |
| 4190 operand stackSlotI(sRegI reg) %{ | |
| 4191 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4192 op_cost(100); | |
| 4193 //match(RegI); | |
| 4194 format %{ "[$reg]" %} | |
| 4195 interface(MEMORY_INTER) %{ | |
| 4196 base(0xE); // R_SP | |
| 4197 index(0x0); | |
| 4198 scale(0x0); | |
| 4199 disp($reg); // Stack Offset | |
| 4200 %} | |
| 4201 %} | |
| 4202 | |
| 4203 operand stackSlotP(sRegP reg) %{ | |
| 4204 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4205 op_cost(100); | |
| 4206 //match(RegP); | |
| 4207 format %{ "[$reg]" %} | |
| 4208 interface(MEMORY_INTER) %{ | |
| 4209 base(0xE); // R_SP | |
| 4210 index(0x0); | |
| 4211 scale(0x0); | |
| 4212 disp($reg); // Stack Offset | |
| 4213 %} | |
| 4214 %} | |
| 4215 | |
| 4216 operand stackSlotF(sRegF reg) %{ | |
| 4217 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4218 op_cost(100); | |
| 4219 //match(RegF); | |
| 4220 format %{ "[$reg]" %} | |
| 4221 interface(MEMORY_INTER) %{ | |
| 4222 base(0xE); // R_SP | |
| 4223 index(0x0); | |
| 4224 scale(0x0); | |
| 4225 disp($reg); // Stack Offset | |
| 4226 %} | |
| 4227 %} | |
| 4228 operand stackSlotD(sRegD reg) %{ | |
| 4229 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4230 op_cost(100); | |
| 4231 //match(RegD); | |
| 4232 format %{ "[$reg]" %} | |
| 4233 interface(MEMORY_INTER) %{ | |
| 4234 base(0xE); // R_SP | |
| 4235 index(0x0); | |
| 4236 scale(0x0); | |
| 4237 disp($reg); // Stack Offset | |
| 4238 %} | |
| 4239 %} | |
| 4240 operand stackSlotL(sRegL reg) %{ | |
| 4241 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4242 op_cost(100); | |
| 4243 //match(RegL); | |
| 4244 format %{ "[$reg]" %} | |
| 4245 interface(MEMORY_INTER) %{ | |
| 4246 base(0xE); // R_SP | |
| 4247 index(0x0); | |
| 4248 scale(0x0); | |
| 4249 disp($reg); // Stack Offset | |
| 4250 %} | |
| 4251 %} | |
| 4252 | |
| 4253 // Operands for expressing Control Flow | |
| 4254 // NOTE: Label is a predefined operand which should not be redefined in | |
| 4255 // the AD file. It is generically handled within the ADLC. | |
| 4256 | |
| 4257 //----------Conditional Branch Operands---------------------------------------- | |
| 4258 // Comparison Op - This is the operation of the comparison, and is limited to | |
| 4259 // the following set of codes: | |
| 4260 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=) | |
| 4261 // | |
| 4262 // Other attributes of the comparison, such as unsignedness, are specified | |
| 4263 // by the comparison instruction that sets a condition code flags register. | |
| 4264 // That result is represented by a flags operand whose subtype is appropriate | |
| 4265 // to the unsignedness (etc.) of the comparison. | |
| 4266 // | |
| 4267 // Later, the instruction which matches both the Comparison Op (a Bool) and | |
| 4268 // the flags (produced by the Cmp) specifies the coding of the comparison op | |
| 4269 // by matching a specific subtype of Bool operand below, such as cmpOpU. | |
| 4270 | |
| 4271 operand cmpOp() %{ | |
| 4272 match(Bool); | |
| 4273 | |
| 4274 format %{ "" %} | |
| 4275 interface(COND_INTER) %{ | |
| 4276 equal(0x1); | |
| 4277 not_equal(0x9); | |
| 4278 less(0x3); | |
| 4279 greater_equal(0xB); | |
| 4280 less_equal(0x2); | |
| 4281 greater(0xA); | |
| 4282 %} | |
| 4283 %} | |
| 4284 | |
| 4285 // Comparison Op, unsigned | |
| 4286 operand cmpOpU() %{ | |
| 4287 match(Bool); | |
| 4288 | |
| 4289 format %{ "u" %} | |
| 4290 interface(COND_INTER) %{ | |
| 4291 equal(0x1); | |
| 4292 not_equal(0x9); | |
| 4293 less(0x5); | |
| 4294 greater_equal(0xD); | |
| 4295 less_equal(0x4); | |
| 4296 greater(0xC); | |
| 4297 %} | |
| 4298 %} | |
| 4299 | |
| 4300 // Comparison Op, pointer (same as unsigned) | |
| 4301 operand cmpOpP() %{ | |
| 4302 match(Bool); | |
| 4303 | |
| 4304 format %{ "p" %} | |
| 4305 interface(COND_INTER) %{ | |
| 4306 equal(0x1); | |
| 4307 not_equal(0x9); | |
| 4308 less(0x5); | |
| 4309 greater_equal(0xD); | |
| 4310 less_equal(0x4); | |
| 4311 greater(0xC); | |
| 4312 %} | |
| 4313 %} | |
| 4314 | |
| 4315 // Comparison Op, branch-register encoding | |
| 4316 operand cmpOp_reg() %{ | |
| 4317 match(Bool); | |
| 4318 | |
| 4319 format %{ "" %} | |
| 4320 interface(COND_INTER) %{ | |
| 4321 equal (0x1); | |
| 4322 not_equal (0x5); | |
| 4323 less (0x3); | |
| 4324 greater_equal(0x7); | |
| 4325 less_equal (0x2); | |
| 4326 greater (0x6); | |
| 4327 %} | |
| 4328 %} | |
| 4329 | |
| 4330 // Comparison Code, floating, unordered same as less | |
| 4331 operand cmpOpF() %{ | |
| 4332 match(Bool); | |
| 4333 | |
| 4334 format %{ "fl" %} | |
| 4335 interface(COND_INTER) %{ | |
| 4336 equal(0x9); | |
| 4337 not_equal(0x1); | |
| 4338 less(0x3); | |
| 4339 greater_equal(0xB); | |
| 4340 less_equal(0xE); | |
| 4341 greater(0x6); | |
| 4342 %} | |
| 4343 %} | |
| 4344 | |
| 4345 // Used by long compare | |
| 4346 operand cmpOp_commute() %{ | |
| 4347 match(Bool); | |
| 4348 | |
| 4349 format %{ "" %} | |
| 4350 interface(COND_INTER) %{ | |
| 4351 equal(0x1); | |
| 4352 not_equal(0x9); | |
| 4353 less(0xA); | |
| 4354 greater_equal(0x2); | |
| 4355 less_equal(0xB); | |
| 4356 greater(0x3); | |
| 4357 %} | |
| 4358 %} | |
| 4359 | |
| 4360 //----------OPERAND CLASSES---------------------------------------------------- | |
| 4361 // Operand Classes are groups of operands that are used to simplify | |
| 605 | 4362 // instruction definitions by not requiring the AD writer to specify separate |
| 0 | 4363 // instructions for every form of operand when the instruction accepts |
| 4364 // multiple operand types with the same basic encoding and format. The classic | |
| 4365 // case of this is memory operands. | |
| 4366 opclass memory( indirect, indOffset13, indIndex ); | |
|
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4367 opclass indIndexMemory( indIndex ); |
| 0 | 4368 |
| 4369 //----------PIPELINE----------------------------------------------------------- | |
| 4370 pipeline %{ | |
| 4371 | |
| 4372 //----------ATTRIBUTES--------------------------------------------------------- | |
| 4373 attributes %{ | |
| 4374 fixed_size_instructions; // Fixed size instructions | |
| 4375 branch_has_delay_slot; // Branch has delay slot following | |
| 4376 max_instructions_per_bundle = 4; // Up to 4 instructions per bundle | |
| 4377 instruction_unit_size = 4; // An instruction is 4 bytes long | |
| 4378 instruction_fetch_unit_size = 16; // The processor fetches one line | |
| 4379 instruction_fetch_units = 1; // of 16 bytes | |
| 4380 | |
| 4381 // List of nop instructions | |
| 4382 nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR ); | |
| 4383 %} | |
| 4384 | |
| 4385 //----------RESOURCES---------------------------------------------------------- | |
| 4386 // Resources are the functional units available to the machine | |
| 4387 resources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1); | |
| 4388 | |
| 4389 //----------PIPELINE DESCRIPTION----------------------------------------------- | |
| 4390 // Pipeline Description specifies the stages in the machine's pipeline | |
| 4391 | |
| 4392 pipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D); | |
| 4393 | |
| 4394 //----------PIPELINE CLASSES--------------------------------------------------- | |
| 4395 // Pipeline Classes describe the stages in which input and output are | |
| 4396 // referenced by the hardware pipeline. | |
| 4397 | |
| 4398 // Integer ALU reg-reg operation | |
| 4399 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 4400 single_instruction; | |
| 4401 dst : E(write); | |
| 4402 src1 : R(read); | |
| 4403 src2 : R(read); | |
| 4404 IALU : R; | |
| 4405 %} | |
| 4406 | |
| 4407 // Integer ALU reg-reg long operation | |
| 4408 pipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 4409 instruction_count(2); | |
| 4410 dst : E(write); | |
| 4411 src1 : R(read); | |
| 4412 src2 : R(read); | |
| 4413 IALU : R; | |
| 4414 IALU : R; | |
| 4415 %} | |
| 4416 | |
| 4417 // Integer ALU reg-reg long dependent operation | |
| 4418 pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{ | |
| 4419 instruction_count(1); multiple_bundles; | |
| 4420 dst : E(write); | |
| 4421 src1 : R(read); | |
| 4422 src2 : R(read); | |
| 4423 cr : E(write); | |
| 4424 IALU : R(2); | |
| 4425 %} | |
| 4426 | |
| 4427 // Integer ALU reg-imm operaion | |
| 4428 pipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{ | |
| 4429 single_instruction; | |
| 4430 dst : E(write); | |
| 4431 src1 : R(read); | |
| 4432 IALU : R; | |
| 4433 %} | |
| 4434 | |
| 4435 // Integer ALU reg-reg operation with condition code | |
| 4436 pipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{ | |
| 4437 single_instruction; | |
| 4438 dst : E(write); | |
| 4439 cr : E(write); | |
| 4440 src1 : R(read); | |
| 4441 src2 : R(read); | |
| 4442 IALU : R; | |
| 4443 %} | |
| 4444 | |
| 4445 // Integer ALU reg-imm operation with condition code | |
| 4446 pipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{ | |
| 4447 single_instruction; | |
| 4448 dst : E(write); | |
| 4449 cr : E(write); | |
| 4450 src1 : R(read); | |
| 4451 IALU : R; | |
| 4452 %} | |
| 4453 | |
| 4454 // Integer ALU zero-reg operation | |
| 4455 pipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{ | |
| 4456 single_instruction; | |
| 4457 dst : E(write); | |
| 4458 src2 : R(read); | |
| 4459 IALU : R; | |
| 4460 %} | |
| 4461 | |
| 4462 // Integer ALU zero-reg operation with condition code only | |
| 4463 pipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{ | |
| 4464 single_instruction; | |
| 4465 cr : E(write); | |
| 4466 src : R(read); | |
| 4467 IALU : R; | |
| 4468 %} | |
| 4469 | |
| 4470 // Integer ALU reg-reg operation with condition code only | |
| 4471 pipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{ | |
| 4472 single_instruction; | |
| 4473 cr : E(write); | |
| 4474 src1 : R(read); | |
| 4475 src2 : R(read); | |
| 4476 IALU : R; | |
| 4477 %} | |
| 4478 | |
| 4479 // Integer ALU reg-imm operation with condition code only | |
| 4480 pipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{ | |
| 4481 single_instruction; | |
| 4482 cr : E(write); | |
| 4483 src1 : R(read); | |
| 4484 IALU : R; | |
| 4485 %} | |
| 4486 | |
| 4487 // Integer ALU reg-reg-zero operation with condition code only | |
| 4488 pipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{ | |
| 4489 single_instruction; | |
| 4490 cr : E(write); | |
| 4491 src1 : R(read); | |
| 4492 src2 : R(read); | |
| 4493 IALU : R; | |
| 4494 %} | |
| 4495 | |
| 4496 // Integer ALU reg-imm-zero operation with condition code only | |
| 4497 pipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{ | |
| 4498 single_instruction; | |
| 4499 cr : E(write); | |
| 4500 src1 : R(read); | |
| 4501 IALU : R; | |
| 4502 %} | |
| 4503 | |
| 4504 // Integer ALU reg-reg operation with condition code, src1 modified | |
| 4505 pipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{ | |
| 4506 single_instruction; | |
| 4507 cr : E(write); | |
| 4508 src1 : E(write); | |
| 4509 src1 : R(read); | |
| 4510 src2 : R(read); | |
| 4511 IALU : R; | |
| 4512 %} | |
| 4513 | |
| 4514 // Integer ALU reg-imm operation with condition code, src1 modified | |
| 4515 pipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{ | |
| 4516 single_instruction; | |
| 4517 cr : E(write); | |
| 4518 src1 : E(write); | |
| 4519 src1 : R(read); | |
| 4520 IALU : R; | |
| 4521 %} | |
| 4522 | |
| 4523 pipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{ | |
| 4524 multiple_bundles; | |
| 4525 dst : E(write)+4; | |
| 4526 cr : E(write); | |
| 4527 src1 : R(read); | |
| 4528 src2 : R(read); | |
| 4529 IALU : R(3); | |
| 4530 BR : R(2); | |
| 4531 %} | |
| 4532 | |
| 4533 // Integer ALU operation | |
| 4534 pipe_class ialu_none(iRegI dst) %{ | |
| 4535 single_instruction; | |
| 4536 dst : E(write); | |
| 4537 IALU : R; | |
| 4538 %} | |
| 4539 | |
| 4540 // Integer ALU reg operation | |
| 4541 pipe_class ialu_reg(iRegI dst, iRegI src) %{ | |
| 4542 single_instruction; may_have_no_code; | |
| 4543 dst : E(write); | |
| 4544 src : R(read); | |
| 4545 IALU : R; | |
| 4546 %} | |
| 4547 | |
| 4548 // Integer ALU reg conditional operation | |
| 4549 // This instruction has a 1 cycle stall, and cannot execute | |
| 4550 // in the same cycle as the instruction setting the condition | |
| 4551 // code. We kludge this by pretending to read the condition code | |
| 4552 // 1 cycle earlier, and by marking the functional units as busy | |
| 4553 // for 2 cycles with the result available 1 cycle later than | |
| 4554 // is really the case. | |
| 4555 pipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{ | |
| 4556 single_instruction; | |
| 4557 op2_out : C(write); | |
| 4558 op1 : R(read); | |
| 4559 cr : R(read); // This is really E, with a 1 cycle stall | |
| 4560 BR : R(2); | |
| 4561 MS : R(2); | |
| 4562 %} | |
| 4563 | |
| 4564 #ifdef _LP64 | |
| 4565 pipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{ | |
| 4566 instruction_count(1); multiple_bundles; | |
| 4567 dst : C(write)+1; | |
| 4568 src : R(read)+1; | |
| 4569 IALU : R(1); | |
| 4570 BR : E(2); | |
| 4571 MS : E(2); | |
| 4572 %} | |
| 4573 #endif | |
| 4574 | |
| 4575 // Integer ALU reg operation | |
| 4576 pipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{ | |
| 4577 single_instruction; may_have_no_code; | |
| 4578 dst : E(write); | |
| 4579 src : R(read); | |
| 4580 IALU : R; | |
| 4581 %} | |
| 4582 pipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{ | |
| 4583 single_instruction; may_have_no_code; | |
| 4584 dst : E(write); | |
| 4585 src : R(read); | |
| 4586 IALU : R; | |
| 4587 %} | |
| 4588 | |
| 4589 // Two integer ALU reg operations | |
| 4590 pipe_class ialu_reg_2(iRegL dst, iRegL src) %{ | |
| 4591 instruction_count(2); | |
| 4592 dst : E(write); | |
| 4593 src : R(read); | |
| 4594 A0 : R; | |
| 4595 A1 : R; | |
| 4596 %} | |
| 4597 | |
| 4598 // Two integer ALU reg operations | |
| 4599 pipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{ | |
| 4600 instruction_count(2); may_have_no_code; | |
| 4601 dst : E(write); | |
| 4602 src : R(read); | |
| 4603 A0 : R; | |
| 4604 A1 : R; | |
| 4605 %} | |
| 4606 | |
| 4607 // Integer ALU imm operation | |
| 4608 pipe_class ialu_imm(iRegI dst, immI13 src) %{ | |
| 4609 single_instruction; | |
| 4610 dst : E(write); | |
| 4611 IALU : R; | |
| 4612 %} | |
| 4613 | |
| 4614 // Integer ALU reg-reg with carry operation | |
| 4615 pipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{ | |
| 4616 single_instruction; | |
| 4617 dst : E(write); | |
| 4618 src1 : R(read); | |
| 4619 src2 : R(read); | |
| 4620 IALU : R; | |
| 4621 %} | |
| 4622 | |
| 4623 // Integer ALU cc operation | |
| 4624 pipe_class ialu_cc(iRegI dst, flagsReg cc) %{ | |
| 4625 single_instruction; | |
| 4626 dst : E(write); | |
| 4627 cc : R(read); | |
| 4628 IALU : R; | |
| 4629 %} | |
| 4630 | |
| 4631 // Integer ALU cc / second IALU operation | |
| 4632 pipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{ | |
| 4633 instruction_count(1); multiple_bundles; | |
| 4634 dst : E(write)+1; | |
| 4635 src : R(read); | |
| 4636 IALU : R; | |
| 4637 %} | |
| 4638 | |
| 4639 // Integer ALU cc / second IALU operation | |
| 4640 pipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{ | |
| 4641 instruction_count(1); multiple_bundles; | |
| 4642 dst : E(write)+1; | |
| 4643 p : R(read); | |
| 4644 q : R(read); | |
| 4645 IALU : R; | |
| 4646 %} | |
| 4647 | |
| 4648 // Integer ALU hi-lo-reg operation | |
| 4649 pipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{ | |
| 4650 instruction_count(1); multiple_bundles; | |
| 4651 dst : E(write)+1; | |
| 4652 IALU : R(2); | |
| 4653 %} | |
| 4654 | |
| 4655 // Float ALU hi-lo-reg operation (with temp) | |
| 4656 pipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{ | |
| 4657 instruction_count(1); multiple_bundles; | |
| 4658 dst : E(write)+1; | |
| 4659 IALU : R(2); | |
| 4660 %} | |
| 4661 | |
| 4662 // Long Constant | |
| 4663 pipe_class loadConL( iRegL dst, immL src ) %{ | |
| 4664 instruction_count(2); multiple_bundles; | |
| 4665 dst : E(write)+1; | |
| 4666 IALU : R(2); | |
| 4667 IALU : R(2); | |
| 4668 %} | |
| 4669 | |
| 4670 // Pointer Constant | |
| 4671 pipe_class loadConP( iRegP dst, immP src ) %{ | |
| 4672 instruction_count(0); multiple_bundles; | |
| 4673 fixed_latency(6); | |
| 4674 %} | |
| 4675 | |
| 4676 // Polling Address | |
| 4677 pipe_class loadConP_poll( iRegP dst, immP_poll src ) %{ | |
| 4678 #ifdef _LP64 | |
| 4679 instruction_count(0); multiple_bundles; | |
| 4680 fixed_latency(6); | |
| 4681 #else | |
| 4682 dst : E(write); | |
| 4683 IALU : R; | |
| 4684 #endif | |
| 4685 %} | |
| 4686 | |
| 4687 // Long Constant small | |
| 4688 pipe_class loadConLlo( iRegL dst, immL src ) %{ | |
| 4689 instruction_count(2); | |
| 4690 dst : E(write); | |
| 4691 IALU : R; | |
| 4692 IALU : R; | |
| 4693 %} | |
| 4694 | |
| 4695 // [PHH] This is wrong for 64-bit. See LdImmF/D. | |
| 4696 pipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{ | |
| 4697 instruction_count(1); multiple_bundles; | |
| 4698 src : R(read); | |
| 4699 dst : M(write)+1; | |
| 4700 IALU : R; | |
| 4701 MS : E; | |
| 4702 %} | |
| 4703 | |
| 4704 // Integer ALU nop operation | |
| 4705 pipe_class ialu_nop() %{ | |
| 4706 single_instruction; | |
| 4707 IALU : R; | |
| 4708 %} | |
| 4709 | |
| 4710 // Integer ALU nop operation | |
| 4711 pipe_class ialu_nop_A0() %{ | |
| 4712 single_instruction; | |
| 4713 A0 : R; | |
| 4714 %} | |
| 4715 | |
| 4716 // Integer ALU nop operation | |
| 4717 pipe_class ialu_nop_A1() %{ | |
| 4718 single_instruction; | |
| 4719 A1 : R; | |
| 4720 %} | |
| 4721 | |
| 4722 // Integer Multiply reg-reg operation | |
| 4723 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 4724 single_instruction; | |
| 4725 dst : E(write); | |
| 4726 src1 : R(read); | |
| 4727 src2 : R(read); | |
| 4728 MS : R(5); | |
| 4729 %} | |
| 4730 | |
| 4731 // Integer Multiply reg-imm operation | |
| 4732 pipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{ | |
| 4733 single_instruction; | |
| 4734 dst : E(write); | |
| 4735 src1 : R(read); | |
| 4736 MS : R(5); | |
| 4737 %} | |
| 4738 | |
| 4739 pipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 4740 single_instruction; | |
| 4741 dst : E(write)+4; | |
| 4742 src1 : R(read); | |
| 4743 src2 : R(read); | |
| 4744 MS : R(6); | |
| 4745 %} | |
| 4746 | |
| 4747 pipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{ | |
| 4748 single_instruction; | |
| 4749 dst : E(write)+4; | |
| 4750 src1 : R(read); | |
| 4751 MS : R(6); | |
| 4752 %} | |
| 4753 | |
| 4754 // Integer Divide reg-reg | |
| 4755 pipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{ | |
| 4756 instruction_count(1); multiple_bundles; | |
| 4757 dst : E(write); | |
| 4758 temp : E(write); | |
| 4759 src1 : R(read); | |
| 4760 src2 : R(read); | |
| 4761 temp : R(read); | |
| 4762 MS : R(38); | |
| 4763 %} | |
| 4764 | |
| 4765 // Integer Divide reg-imm | |
| 4766 pipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{ | |
| 4767 instruction_count(1); multiple_bundles; | |
| 4768 dst : E(write); | |
| 4769 temp : E(write); | |
| 4770 src1 : R(read); | |
| 4771 temp : R(read); | |
| 4772 MS : R(38); | |
| 4773 %} | |
| 4774 | |
| 4775 // Long Divide | |
| 4776 pipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 4777 dst : E(write)+71; | |
| 4778 src1 : R(read); | |
| 4779 src2 : R(read)+1; | |
| 4780 MS : R(70); | |
| 4781 %} | |
| 4782 | |
| 4783 pipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{ | |
| 4784 dst : E(write)+71; | |
| 4785 src1 : R(read); | |
| 4786 MS : R(70); | |
| 4787 %} | |
| 4788 | |
| 4789 // Floating Point Add Float | |
| 4790 pipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{ | |
| 4791 single_instruction; | |
| 4792 dst : X(write); | |
| 4793 src1 : E(read); | |
| 4794 src2 : E(read); | |
| 4795 FA : R; | |
| 4796 %} | |
| 4797 | |
| 4798 // Floating Point Add Double | |
| 4799 pipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{ | |
| 4800 single_instruction; | |
| 4801 dst : X(write); | |
| 4802 src1 : E(read); | |
| 4803 src2 : E(read); | |
| 4804 FA : R; | |
| 4805 %} | |
| 4806 | |
| 4807 // Floating Point Conditional Move based on integer flags | |
| 4808 pipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{ | |
| 4809 single_instruction; | |
| 4810 dst : X(write); | |
| 4811 src : E(read); | |
| 4812 cr : R(read); | |
| 4813 FA : R(2); | |
| 4814 BR : R(2); | |
| 4815 %} | |
| 4816 | |
| 4817 // Floating Point Conditional Move based on integer flags | |
| 4818 pipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{ | |
| 4819 single_instruction; | |
| 4820 dst : X(write); | |
| 4821 src : E(read); | |
| 4822 cr : R(read); | |
| 4823 FA : R(2); | |
| 4824 BR : R(2); | |
| 4825 %} | |
| 4826 | |
| 4827 // Floating Point Multiply Float | |
| 4828 pipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{ | |
| 4829 single_instruction; | |
| 4830 dst : X(write); | |
| 4831 src1 : E(read); | |
| 4832 src2 : E(read); | |
| 4833 FM : R; | |
| 4834 %} | |
| 4835 | |
| 4836 // Floating Point Multiply Double | |
| 4837 pipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{ | |
| 4838 single_instruction; | |
| 4839 dst : X(write); | |
| 4840 src1 : E(read); | |
| 4841 src2 : E(read); | |
| 4842 FM : R; | |
| 4843 %} | |
| 4844 | |
| 4845 // Floating Point Divide Float | |
| 4846 pipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{ | |
| 4847 single_instruction; | |
| 4848 dst : X(write); | |
| 4849 src1 : E(read); | |
| 4850 src2 : E(read); | |
| 4851 FM : R; | |
| 4852 FDIV : C(14); | |
| 4853 %} | |
| 4854 | |
| 4855 // Floating Point Divide Double | |
| 4856 pipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{ | |
| 4857 single_instruction; | |
| 4858 dst : X(write); | |
| 4859 src1 : E(read); | |
| 4860 src2 : E(read); | |
| 4861 FM : R; | |
| 4862 FDIV : C(17); | |
| 4863 %} | |
| 4864 | |
| 4865 // Floating Point Move/Negate/Abs Float | |
| 4866 pipe_class faddF_reg(regF dst, regF src) %{ | |
| 4867 single_instruction; | |
| 4868 dst : W(write); | |
| 4869 src : E(read); | |
| 4870 FA : R(1); | |
| 4871 %} | |
| 4872 | |
| 4873 // Floating Point Move/Negate/Abs Double | |
| 4874 pipe_class faddD_reg(regD dst, regD src) %{ | |
| 4875 single_instruction; | |
| 4876 dst : W(write); | |
| 4877 src : E(read); | |
| 4878 FA : R; | |
| 4879 %} | |
| 4880 | |
| 4881 // Floating Point Convert F->D | |
| 4882 pipe_class fcvtF2D(regD dst, regF src) %{ | |
| 4883 single_instruction; | |
| 4884 dst : X(write); | |
| 4885 src : E(read); | |
| 4886 FA : R; | |
| 4887 %} | |
| 4888 | |
| 4889 // Floating Point Convert I->D | |
| 4890 pipe_class fcvtI2D(regD dst, regF src) %{ | |
| 4891 single_instruction; | |
| 4892 dst : X(write); | |
| 4893 src : E(read); | |
| 4894 FA : R; | |
| 4895 %} | |
| 4896 | |
| 4897 // Floating Point Convert LHi->D | |
| 4898 pipe_class fcvtLHi2D(regD dst, regD src) %{ | |
| 4899 single_instruction; | |
| 4900 dst : X(write); | |
| 4901 src : E(read); | |
| 4902 FA : R; | |
| 4903 %} | |
| 4904 | |
| 4905 // Floating Point Convert L->D | |
| 4906 pipe_class fcvtL2D(regD dst, regF src) %{ | |
| 4907 single_instruction; | |
| 4908 dst : X(write); | |
| 4909 src : E(read); | |
| 4910 FA : R; | |
| 4911 %} | |
| 4912 | |
| 4913 // Floating Point Convert L->F | |
| 4914 pipe_class fcvtL2F(regD dst, regF src) %{ | |
| 4915 single_instruction; | |
| 4916 dst : X(write); | |
| 4917 src : E(read); | |
| 4918 FA : R; | |
| 4919 %} | |
| 4920 | |
| 4921 // Floating Point Convert D->F | |
| 4922 pipe_class fcvtD2F(regD dst, regF src) %{ | |
| 4923 single_instruction; | |
| 4924 dst : X(write); | |
| 4925 src : E(read); | |
| 4926 FA : R; | |
| 4927 %} | |
| 4928 | |
| 4929 // Floating Point Convert I->L | |
| 4930 pipe_class fcvtI2L(regD dst, regF src) %{ | |
| 4931 single_instruction; | |
| 4932 dst : X(write); | |
| 4933 src : E(read); | |
| 4934 FA : R; | |
| 4935 %} | |
| 4936 | |
| 4937 // Floating Point Convert D->F | |
| 4938 pipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{ | |
| 4939 instruction_count(1); multiple_bundles; | |
| 4940 dst : X(write)+6; | |
| 4941 src : E(read); | |
| 4942 FA : R; | |
| 4943 %} | |
| 4944 | |
| 4945 // Floating Point Convert D->L | |
| 4946 pipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{ | |
| 4947 instruction_count(1); multiple_bundles; | |
| 4948 dst : X(write)+6; | |
| 4949 src : E(read); | |
| 4950 FA : R; | |
| 4951 %} | |
| 4952 | |
| 4953 // Floating Point Convert F->I | |
| 4954 pipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{ | |
| 4955 instruction_count(1); multiple_bundles; | |
| 4956 dst : X(write)+6; | |
| 4957 src : E(read); | |
| 4958 FA : R; | |
| 4959 %} | |
| 4960 | |
| 4961 // Floating Point Convert F->L | |
| 4962 pipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{ | |
| 4963 instruction_count(1); multiple_bundles; | |
| 4964 dst : X(write)+6; | |
| 4965 src : E(read); | |
| 4966 FA : R; | |
| 4967 %} | |
| 4968 | |
| 4969 // Floating Point Convert I->F | |
| 4970 pipe_class fcvtI2F(regF dst, regF src) %{ | |
| 4971 single_instruction; | |
| 4972 dst : X(write); | |
| 4973 src : E(read); | |
| 4974 FA : R; | |
| 4975 %} | |
| 4976 | |
| 4977 // Floating Point Compare | |
| 4978 pipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{ | |
| 4979 single_instruction; | |
| 4980 cr : X(write); | |
| 4981 src1 : E(read); | |
| 4982 src2 : E(read); | |
| 4983 FA : R; | |
| 4984 %} | |
| 4985 | |
| 4986 // Floating Point Compare | |
| 4987 pipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{ | |
| 4988 single_instruction; | |
| 4989 cr : X(write); | |
| 4990 src1 : E(read); | |
| 4991 src2 : E(read); | |
| 4992 FA : R; | |
| 4993 %} | |
| 4994 | |
| 4995 // Floating Add Nop | |
| 4996 pipe_class fadd_nop() %{ | |
| 4997 single_instruction; | |
| 4998 FA : R; | |
| 4999 %} | |
| 5000 | |
| 5001 // Integer Store to Memory | |
| 5002 pipe_class istore_mem_reg(memory mem, iRegI src) %{ | |
| 5003 single_instruction; | |
| 5004 mem : R(read); | |
| 5005 src : C(read); | |
| 5006 MS : R; | |
| 5007 %} | |
| 5008 | |
| 5009 // Integer Store to Memory | |
| 5010 pipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{ | |
| 5011 single_instruction; | |
| 5012 mem : R(read); | |
| 5013 src : C(read); | |
| 5014 MS : R; | |
| 5015 %} | |
| 5016 | |
| 5017 // Integer Store Zero to Memory | |
| 5018 pipe_class istore_mem_zero(memory mem, immI0 src) %{ | |
| 5019 single_instruction; | |
| 5020 mem : R(read); | |
| 5021 MS : R; | |
| 5022 %} | |
| 5023 | |
| 5024 // Special Stack Slot Store | |
| 5025 pipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{ | |
| 5026 single_instruction; | |
| 5027 stkSlot : R(read); | |
| 5028 src : C(read); | |
| 5029 MS : R; | |
| 5030 %} | |
| 5031 | |
| 5032 // Special Stack Slot Store | |
| 5033 pipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{ | |
| 5034 instruction_count(2); multiple_bundles; | |
| 5035 stkSlot : R(read); | |
| 5036 src : C(read); | |
| 5037 MS : R(2); | |
| 5038 %} | |
| 5039 | |
| 5040 // Float Store | |
| 5041 pipe_class fstoreF_mem_reg(memory mem, RegF src) %{ | |
| 5042 single_instruction; | |
| 5043 mem : R(read); | |
| 5044 src : C(read); | |
| 5045 MS : R; | |
| 5046 %} | |
| 5047 | |
| 5048 // Float Store | |
| 5049 pipe_class fstoreF_mem_zero(memory mem, immF0 src) %{ | |
| 5050 single_instruction; | |
| 5051 mem : R(read); | |
| 5052 MS : R; | |
| 5053 %} | |
| 5054 | |
| 5055 // Double Store | |
| 5056 pipe_class fstoreD_mem_reg(memory mem, RegD src) %{ | |
| 5057 instruction_count(1); | |
| 5058 mem : R(read); | |
| 5059 src : C(read); | |
| 5060 MS : R; | |
| 5061 %} | |
| 5062 | |
| 5063 // Double Store | |
| 5064 pipe_class fstoreD_mem_zero(memory mem, immD0 src) %{ | |
| 5065 single_instruction; | |
| 5066 mem : R(read); | |
| 5067 MS : R; | |
| 5068 %} | |
| 5069 | |
| 5070 // Special Stack Slot Float Store | |
| 5071 pipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{ | |
| 5072 single_instruction; | |
| 5073 stkSlot : R(read); | |
| 5074 src : C(read); | |
| 5075 MS : R; | |
| 5076 %} | |
| 5077 | |
| 5078 // Special Stack Slot Double Store | |
| 5079 pipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{ | |
| 5080 single_instruction; | |
| 5081 stkSlot : R(read); | |
| 5082 src : C(read); | |
| 5083 MS : R; | |
| 5084 %} | |
| 5085 | |
| 5086 // Integer Load (when sign bit propagation not needed) | |
| 5087 pipe_class iload_mem(iRegI dst, memory mem) %{ | |
| 5088 single_instruction; | |
| 5089 mem : R(read); | |
| 5090 dst : C(write); | |
| 5091 MS : R; | |
| 5092 %} | |
| 5093 | |
| 5094 // Integer Load from stack operand | |
| 5095 pipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{ | |
| 5096 single_instruction; | |
| 5097 mem : R(read); | |
| 5098 dst : C(write); | |
| 5099 MS : R; | |
| 5100 %} | |
| 5101 | |
| 5102 // Integer Load (when sign bit propagation or masking is needed) | |
| 5103 pipe_class iload_mask_mem(iRegI dst, memory mem) %{ | |
| 5104 single_instruction; | |
| 5105 mem : R(read); | |
| 5106 dst : M(write); | |
| 5107 MS : R; | |
| 5108 %} | |
| 5109 | |
| 5110 // Float Load | |
| 5111 pipe_class floadF_mem(regF dst, memory mem) %{ | |
| 5112 single_instruction; | |
| 5113 mem : R(read); | |
| 5114 dst : M(write); | |
| 5115 MS : R; | |
| 5116 %} | |
| 5117 | |
| 5118 // Float Load | |
| 5119 pipe_class floadD_mem(regD dst, memory mem) %{ | |
| 5120 instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case | |
| 5121 mem : R(read); | |
| 5122 dst : M(write); | |
| 5123 MS : R; | |
| 5124 %} | |
| 5125 | |
| 5126 // Float Load | |
| 5127 pipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{ | |
| 5128 single_instruction; | |
| 5129 stkSlot : R(read); | |
| 5130 dst : M(write); | |
| 5131 MS : R; | |
| 5132 %} | |
| 5133 | |
| 5134 // Float Load | |
| 5135 pipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{ | |
| 5136 single_instruction; | |
| 5137 stkSlot : R(read); | |
| 5138 dst : M(write); | |
| 5139 MS : R; | |
| 5140 %} | |
| 5141 | |
| 5142 // Memory Nop | |
| 5143 pipe_class mem_nop() %{ | |
| 5144 single_instruction; | |
| 5145 MS : R; | |
| 5146 %} | |
| 5147 | |
| 5148 pipe_class sethi(iRegP dst, immI src) %{ | |
| 5149 single_instruction; | |
| 5150 dst : E(write); | |
| 5151 IALU : R; | |
| 5152 %} | |
| 5153 | |
| 5154 pipe_class loadPollP(iRegP poll) %{ | |
| 5155 single_instruction; | |
| 5156 poll : R(read); | |
| 5157 MS : R; | |
| 5158 %} | |
| 5159 | |
| 5160 pipe_class br(Universe br, label labl) %{ | |
| 5161 single_instruction_with_delay_slot; | |
| 5162 BR : R; | |
| 5163 %} | |
| 5164 | |
| 5165 pipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{ | |
| 5166 single_instruction_with_delay_slot; | |
| 5167 cr : E(read); | |
| 5168 BR : R; | |
| 5169 %} | |
| 5170 | |
| 5171 pipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{ | |
| 5172 single_instruction_with_delay_slot; | |
| 5173 op1 : E(read); | |
| 5174 BR : R; | |
| 5175 MS : R; | |
| 5176 %} | |
| 5177 | |
| 3851 | 5178 // Compare and branch |
| 5179 pipe_class cmp_br_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl, flagsReg cr) %{ | |
| 5180 instruction_count(2); has_delay_slot; | |
| 5181 cr : E(write); | |
| 5182 src1 : R(read); | |
| 5183 src2 : R(read); | |
| 5184 IALU : R; | |
| 5185 BR : R; | |
| 5186 %} | |
| 5187 | |
| 5188 // Compare and branch | |
| 5189 pipe_class cmp_br_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI13 src2, label labl, flagsReg cr) %{ | |
| 5190 instruction_count(2); has_delay_slot; | |
| 5191 cr : E(write); | |
| 5192 src1 : R(read); | |
| 5193 IALU : R; | |
| 5194 BR : R; | |
| 5195 %} | |
| 5196 | |
| 5197 // Compare and branch using cbcond | |
| 5198 pipe_class cbcond_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl) %{ | |
| 5199 single_instruction; | |
| 5200 src1 : E(read); | |
| 5201 src2 : E(read); | |
| 5202 IALU : R; | |
| 5203 BR : R; | |
| 5204 %} | |
| 5205 | |
| 5206 // Compare and branch using cbcond | |
| 5207 pipe_class cbcond_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI5 src2, label labl) %{ | |
| 5208 single_instruction; | |
| 5209 src1 : E(read); | |
| 5210 IALU : R; | |
| 5211 BR : R; | |
| 5212 %} | |
| 5213 | |
| 0 | 5214 pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{ |
| 5215 single_instruction_with_delay_slot; | |
| 5216 cr : E(read); | |
| 5217 BR : R; | |
| 5218 %} | |
| 5219 | |
| 5220 pipe_class br_nop() %{ | |
| 5221 single_instruction; | |
| 5222 BR : R; | |
| 5223 %} | |
| 5224 | |
| 5225 pipe_class simple_call(method meth) %{ | |
| 5226 instruction_count(2); multiple_bundles; force_serialization; | |
| 5227 fixed_latency(100); | |
| 5228 BR : R(1); | |
| 5229 MS : R(1); | |
| 5230 A0 : R(1); | |
| 5231 %} | |
| 5232 | |
| 5233 pipe_class compiled_call(method meth) %{ | |
| 5234 instruction_count(1); multiple_bundles; force_serialization; | |
| 5235 fixed_latency(100); | |
| 5236 MS : R(1); | |
| 5237 %} | |
| 5238 | |
| 5239 pipe_class call(method meth) %{ | |
| 5240 instruction_count(0); multiple_bundles; force_serialization; | |
| 5241 fixed_latency(100); | |
| 5242 %} | |
| 5243 | |
| 5244 pipe_class tail_call(Universe ignore, label labl) %{ | |
| 5245 single_instruction; has_delay_slot; | |
| 5246 fixed_latency(100); | |
| 5247 BR : R(1); | |
| 5248 MS : R(1); | |
| 5249 %} | |
| 5250 | |
| 5251 pipe_class ret(Universe ignore) %{ | |
| 5252 single_instruction; has_delay_slot; | |
| 5253 BR : R(1); | |
| 5254 MS : R(1); | |
| 5255 %} | |
| 5256 | |
| 5257 pipe_class ret_poll(g3RegP poll) %{ | |
| 5258 instruction_count(3); has_delay_slot; | |
| 5259 poll : E(read); | |
| 5260 MS : R; | |
| 5261 %} | |
| 5262 | |
| 5263 // The real do-nothing guy | |
| 5264 pipe_class empty( ) %{ | |
| 5265 instruction_count(0); | |
| 5266 %} | |
| 5267 | |
| 5268 pipe_class long_memory_op() %{ | |
| 5269 instruction_count(0); multiple_bundles; force_serialization; | |
| 5270 fixed_latency(25); | |
| 5271 MS : R(1); | |
| 5272 %} | |
| 5273 | |
| 5274 // Check-cast | |
| 5275 pipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{ | |
| 5276 array : R(read); | |
| 5277 match : R(read); | |
| 5278 IALU : R(2); | |
| 5279 BR : R(2); | |
| 5280 MS : R; | |
| 5281 %} | |
| 5282 | |
| 5283 // Convert FPU flags into +1,0,-1 | |
| 5284 pipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{ | |
| 5285 src1 : E(read); | |
| 5286 src2 : E(read); | |
| 5287 dst : E(write); | |
| 5288 FA : R; | |
| 5289 MS : R(2); | |
| 5290 BR : R(2); | |
| 5291 %} | |
| 5292 | |
| 5293 // Compare for p < q, and conditionally add y | |
| 5294 pipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{ | |
| 5295 p : E(read); | |
| 5296 q : E(read); | |
| 5297 y : E(read); | |
| 5298 IALU : R(3) | |
| 5299 %} | |
| 5300 | |
| 5301 // Perform a compare, then move conditionally in a branch delay slot. | |
| 5302 pipe_class min_max( iRegI src2, iRegI srcdst ) %{ | |
| 5303 src2 : E(read); | |
| 5304 srcdst : E(read); | |
| 5305 IALU : R; | |
| 5306 BR : R; | |
| 5307 %} | |
| 5308 | |
| 5309 // Define the class for the Nop node | |
| 5310 define %{ | |
| 5311 MachNop = ialu_nop; | |
| 5312 %} | |
| 5313 | |
| 5314 %} | |
| 5315 | |
| 5316 //----------INSTRUCTIONS------------------------------------------------------- | |
| 5317 | |
| 5318 //------------Special Stack Slot instructions - no match rules----------------- | |
| 5319 instruct stkI_to_regF(regF dst, stackSlotI src) %{ | |
| 5320 // No match rule to avoid chain rule match. | |
| 5321 effect(DEF dst, USE src); | |
| 5322 ins_cost(MEMORY_REF_COST); | |
| 5323 size(4); | |
| 5324 format %{ "LDF $src,$dst\t! stkI to regF" %} | |
| 5325 opcode(Assembler::ldf_op3); | |
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5326 ins_encode(simple_form3_mem_reg(src, dst)); |
| 0 | 5327 ins_pipe(floadF_stk); |
| 5328 %} | |
| 5329 | |
| 5330 instruct stkL_to_regD(regD dst, stackSlotL src) %{ | |
| 5331 // No match rule to avoid chain rule match. | |
| 5332 effect(DEF dst, USE src); | |
| 5333 ins_cost(MEMORY_REF_COST); | |
| 5334 size(4); | |
| 5335 format %{ "LDDF $src,$dst\t! stkL to regD" %} | |
| 5336 opcode(Assembler::lddf_op3); | |
|
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5337 ins_encode(simple_form3_mem_reg(src, dst)); |
| 0 | 5338 ins_pipe(floadD_stk); |
| 5339 %} | |
| 5340 | |
| 5341 instruct regF_to_stkI(stackSlotI dst, regF src) %{ | |
| 5342 // No match rule to avoid chain rule match. | |
| 5343 effect(DEF dst, USE src); | |
| 5344 ins_cost(MEMORY_REF_COST); | |
| 5345 size(4); | |
| 5346 format %{ "STF $src,$dst\t! regF to stkI" %} | |
| 5347 opcode(Assembler::stf_op3); | |
|
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5348 ins_encode(simple_form3_mem_reg(dst, src)); |
| 0 | 5349 ins_pipe(fstoreF_stk_reg); |
| 5350 %} | |
| 5351 | |
| 5352 instruct regD_to_stkL(stackSlotL dst, regD src) %{ | |
| 5353 // No match rule to avoid chain rule match. | |
| 5354 effect(DEF dst, USE src); | |
| 5355 ins_cost(MEMORY_REF_COST); | |
| 5356 size(4); | |
| 5357 format %{ "STDF $src,$dst\t! regD to stkL" %} | |
| 5358 opcode(Assembler::stdf_op3); | |
|
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5359 ins_encode(simple_form3_mem_reg(dst, src)); |
| 0 | 5360 ins_pipe(fstoreD_stk_reg); |
| 5361 %} | |
| 5362 | |
| 5363 instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{ | |
| 5364 effect(DEF dst, USE src); | |
| 5365 ins_cost(MEMORY_REF_COST*2); | |
| 5366 size(8); | |
| 5367 format %{ "STW $src,$dst.hi\t! long\n\t" | |
| 5368 "STW R_G0,$dst.lo" %} | |
| 5369 opcode(Assembler::stw_op3); | |
|
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5370 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0)); |
| 0 | 5371 ins_pipe(lstoreI_stk_reg); |
| 5372 %} | |
| 5373 | |
| 5374 instruct regL_to_stkD(stackSlotD dst, iRegL src) %{ | |
| 5375 // No match rule to avoid chain rule match. | |
| 5376 effect(DEF dst, USE src); | |
| 5377 ins_cost(MEMORY_REF_COST); | |
| 5378 size(4); | |
| 5379 format %{ "STX $src,$dst\t! regL to stkD" %} | |
| 5380 opcode(Assembler::stx_op3); | |
|
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5381 ins_encode(simple_form3_mem_reg( dst, src ) ); |
| 0 | 5382 ins_pipe(istore_stk_reg); |
| 5383 %} | |
| 5384 | |
| 5385 //---------- Chain stack slots between similar types -------- | |
| 5386 | |
| 5387 // Load integer from stack slot | |
| 5388 instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{ | |
| 5389 match(Set dst src); | |
| 5390 ins_cost(MEMORY_REF_COST); | |
| 5391 | |
| 5392 size(4); | |
| 5393 format %{ "LDUW $src,$dst\t!stk" %} | |
| 5394 opcode(Assembler::lduw_op3); | |
|
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5395 ins_encode(simple_form3_mem_reg( src, dst ) ); |
| 0 | 5396 ins_pipe(iload_mem); |
| 5397 %} | |
| 5398 | |
| 5399 // Store integer to stack slot | |
| 5400 instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{ | |
| 5401 match(Set dst src); | |
| 5402 ins_cost(MEMORY_REF_COST); | |
| 5403 | |
| 5404 size(4); | |
| 5405 format %{ "STW $src,$dst\t!stk" %} | |
| 5406 opcode(Assembler::stw_op3); | |
|
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5407 ins_encode(simple_form3_mem_reg( dst, src ) ); |
| 0 | 5408 ins_pipe(istore_mem_reg); |
| 5409 %} | |
| 5410 | |
| 5411 // Load long from stack slot | |
| 5412 instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{ | |
| 5413 match(Set dst src); | |
| 5414 | |
| 5415 ins_cost(MEMORY_REF_COST); | |
| 5416 size(4); | |
| 5417 format %{ "LDX $src,$dst\t! long" %} | |
| 5418 opcode(Assembler::ldx_op3); | |
|
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5419 ins_encode(simple_form3_mem_reg( src, dst ) ); |
| 0 | 5420 ins_pipe(iload_mem); |
| 5421 %} | |
| 5422 | |
| 5423 // Store long to stack slot | |
| 5424 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{ | |
| 5425 match(Set dst src); | |
| 5426 | |
| 5427 ins_cost(MEMORY_REF_COST); | |
| 5428 size(4); | |
| 5429 format %{ "STX $src,$dst\t! long" %} | |
| 5430 opcode(Assembler::stx_op3); | |
|
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5431 ins_encode(simple_form3_mem_reg( dst, src ) ); |
| 0 | 5432 ins_pipe(istore_mem_reg); |
| 5433 %} | |
| 5434 | |
| 5435 #ifdef _LP64 | |
| 5436 // Load pointer from stack slot, 64-bit encoding | |
| 5437 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{ | |
| 5438 match(Set dst src); | |
| 5439 ins_cost(MEMORY_REF_COST); | |
| 5440 size(4); | |
| 5441 format %{ "LDX $src,$dst\t!ptr" %} | |
| 5442 opcode(Assembler::ldx_op3); | |
|
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5443 ins_encode(simple_form3_mem_reg( src, dst ) ); |
| 0 | 5444 ins_pipe(iload_mem); |
| 5445 %} | |
| 5446 | |
| 5447 // Store pointer to stack slot | |
| 5448 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{ | |
| 5449 match(Set dst src); | |
| 5450 ins_cost(MEMORY_REF_COST); | |
| 5451 size(4); | |
| 5452 format %{ "STX $src,$dst\t!ptr" %} | |
| 5453 opcode(Assembler::stx_op3); | |
|
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5454 ins_encode(simple_form3_mem_reg( dst, src ) ); |
| 0 | 5455 ins_pipe(istore_mem_reg); |
| 5456 %} | |
| 5457 #else // _LP64 | |
| 5458 // Load pointer from stack slot, 32-bit encoding | |
| 5459 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{ | |
| 5460 match(Set dst src); | |
| 5461 ins_cost(MEMORY_REF_COST); | |
| 5462 format %{ "LDUW $src,$dst\t!ptr" %} | |
| 5463 opcode(Assembler::lduw_op3, Assembler::ldst_op); | |
|
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5464 ins_encode(simple_form3_mem_reg( src, dst ) ); |
| 0 | 5465 ins_pipe(iload_mem); |
| 5466 %} | |
| 5467 | |
| 5468 // Store pointer to stack slot | |
| 5469 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{ | |
| 5470 match(Set dst src); | |
| 5471 ins_cost(MEMORY_REF_COST); | |
| 5472 format %{ "STW $src,$dst\t!ptr" %} | |
| 5473 opcode(Assembler::stw_op3, Assembler::ldst_op); | |
|
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|
5474 ins_encode(simple_form3_mem_reg( dst, src ) ); |
| 0 | 5475 ins_pipe(istore_mem_reg); |
| 5476 %} | |
| 5477 #endif // _LP64 | |
| 5478 | |
| 5479 //------------Special Nop instructions for bundling - no match rules----------- | |
| 5480 // Nop using the A0 functional unit | |
| 5481 instruct Nop_A0() %{ | |
| 5482 ins_cost(0); | |
| 5483 | |
| 5484 format %{ "NOP ! Alu Pipeline" %} | |
| 5485 opcode(Assembler::or_op3, Assembler::arith_op); | |
| 5486 ins_encode( form2_nop() ); | |
| 5487 ins_pipe(ialu_nop_A0); | |
| 5488 %} | |
| 5489 | |
| 5490 // Nop using the A1 functional unit | |
| 5491 instruct Nop_A1( ) %{ | |
| 5492 ins_cost(0); | |
| 5493 | |
| 5494 format %{ "NOP ! Alu Pipeline" %} | |
| 5495 opcode(Assembler::or_op3, Assembler::arith_op); | |
| 5496 ins_encode( form2_nop() ); | |
| 5497 ins_pipe(ialu_nop_A1); | |
| 5498 %} | |
| 5499 | |
| 5500 // Nop using the memory functional unit | |
| 5501 instruct Nop_MS( ) %{ | |
| 5502 ins_cost(0); | |
| 5503 | |
| 5504 format %{ "NOP ! Memory Pipeline" %} | |
| 5505 ins_encode( emit_mem_nop ); | |
| 5506 ins_pipe(mem_nop); | |
| 5507 %} | |
| 5508 | |
| 5509 // Nop using the floating add functional unit | |
| 5510 instruct Nop_FA( ) %{ | |
| 5511 ins_cost(0); | |
| 5512 | |
| 5513 format %{ "NOP ! Floating Add Pipeline" %} | |
| 5514 ins_encode( emit_fadd_nop ); | |
| 5515 ins_pipe(fadd_nop); | |
| 5516 %} | |
| 5517 | |
| 5518 // Nop using the branch functional unit | |
| 5519 instruct Nop_BR( ) %{ | |
| 5520 ins_cost(0); | |
| 5521 | |
| 5522 format %{ "NOP ! Branch Pipeline" %} | |
| 5523 ins_encode( emit_br_nop ); | |
| 5524 ins_pipe(br_nop); | |
| 5525 %} | |
| 5526 | |
| 5527 //----------Load/Store/Move Instructions--------------------------------------- | |
| 5528 //----------Load Instructions-------------------------------------------------- | |
| 5529 // Load Byte (8bit signed) | |
| 5530 instruct loadB(iRegI dst, memory mem) %{ | |
| 5531 match(Set dst (LoadB mem)); | |
| 5532 ins_cost(MEMORY_REF_COST); | |
| 5533 | |
| 5534 size(4); | |
| 624 | 5535 format %{ "LDSB $mem,$dst\t! byte" %} |
| 727 | 5536 ins_encode %{ |
| 5537 __ ldsb($mem$$Address, $dst$$Register); | |
| 5538 %} | |
| 624 | 5539 ins_pipe(iload_mask_mem); |
| 5540 %} | |
| 5541 | |
| 5542 // Load Byte (8bit signed) into a Long Register | |
| 5543 instruct loadB2L(iRegL dst, memory mem) %{ | |
| 5544 match(Set dst (ConvI2L (LoadB mem))); | |
| 5545 ins_cost(MEMORY_REF_COST); | |
| 5546 | |
| 5547 size(4); | |
| 5548 format %{ "LDSB $mem,$dst\t! byte -> long" %} | |
| 727 | 5549 ins_encode %{ |
| 5550 __ ldsb($mem$$Address, $dst$$Register); | |
| 5551 %} | |
| 0 | 5552 ins_pipe(iload_mask_mem); |
| 5553 %} | |
| 5554 | |
| 624 | 5555 // Load Unsigned Byte (8bit UNsigned) into an int reg |
| 5556 instruct loadUB(iRegI dst, memory mem) %{ | |
| 5557 match(Set dst (LoadUB mem)); | |
| 0 | 5558 ins_cost(MEMORY_REF_COST); |
| 5559 | |
| 5560 size(4); | |
| 624 | 5561 format %{ "LDUB $mem,$dst\t! ubyte" %} |
| 727 | 5562 ins_encode %{ |
| 5563 __ ldub($mem$$Address, $dst$$Register); | |
| 5564 %} | |
| 824 | 5565 ins_pipe(iload_mem); |
| 624 | 5566 %} |
| 5567 | |
| 5568 // Load Unsigned Byte (8bit UNsigned) into a Long Register | |
| 5569 instruct loadUB2L(iRegL dst, memory mem) %{ | |
| 5570 match(Set dst (ConvI2L (LoadUB mem))); | |
| 5571 ins_cost(MEMORY_REF_COST); | |
| 5572 | |
| 5573 size(4); | |
| 5574 format %{ "LDUB $mem,$dst\t! ubyte -> long" %} | |
| 727 | 5575 ins_encode %{ |
| 5576 __ ldub($mem$$Address, $dst$$Register); | |
| 5577 %} | |
| 824 | 5578 ins_pipe(iload_mem); |
| 5579 %} | |
| 5580 | |
| 5581 // Load Unsigned Byte (8 bit UNsigned) with 8-bit mask into Long Register | |
| 5582 instruct loadUB2L_immI8(iRegL dst, memory mem, immI8 mask) %{ | |
| 5583 match(Set dst (ConvI2L (AndI (LoadUB mem) mask))); | |
| 5584 ins_cost(MEMORY_REF_COST + DEFAULT_COST); | |
| 5585 | |
| 5586 size(2*4); | |
| 5587 format %{ "LDUB $mem,$dst\t# ubyte & 8-bit mask -> long\n\t" | |
| 5588 "AND $dst,$mask,$dst" %} | |
| 5589 ins_encode %{ | |
| 5590 __ ldub($mem$$Address, $dst$$Register); | |
| 5591 __ and3($dst$$Register, $mask$$constant, $dst$$Register); | |
| 5592 %} | |
| 5593 ins_pipe(iload_mem); | |
| 0 | 5594 %} |
| 5595 | |
| 624 | 5596 // Load Short (16bit signed) |
| 5597 instruct loadS(iRegI dst, memory mem) %{ | |
| 5598 match(Set dst (LoadS mem)); | |
| 5599 ins_cost(MEMORY_REF_COST); | |
| 5600 | |
| 5601 size(4); | |
| 5602 format %{ "LDSH $mem,$dst\t! short" %} | |
| 727 | 5603 ins_encode %{ |
| 5604 __ ldsh($mem$$Address, $dst$$Register); | |
| 5605 %} | |
| 624 | 5606 ins_pipe(iload_mask_mem); |
| 5607 %} | |
| 5608 | |
| 785 | 5609 // Load Short (16 bit signed) to Byte (8 bit signed) |
| 5610 instruct loadS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ | |
| 5611 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour)); | |
| 5612 ins_cost(MEMORY_REF_COST); | |
| 5613 | |
| 5614 size(4); | |
| 5615 | |
| 5616 format %{ "LDSB $mem+1,$dst\t! short -> byte" %} | |
| 5617 ins_encode %{ | |
| 5618 __ ldsb($mem$$Address, $dst$$Register, 1); | |
| 5619 %} | |
| 5620 ins_pipe(iload_mask_mem); | |
| 5621 %} | |
| 5622 | |
| 624 | 5623 // Load Short (16bit signed) into a Long Register |
| 5624 instruct loadS2L(iRegL dst, memory mem) %{ | |
| 5625 match(Set dst (ConvI2L (LoadS mem))); | |
| 0 | 5626 ins_cost(MEMORY_REF_COST); |
| 5627 | |
| 5628 size(4); | |
| 624 | 5629 format %{ "LDSH $mem,$dst\t! short -> long" %} |
| 727 | 5630 ins_encode %{ |
| 5631 __ ldsh($mem$$Address, $dst$$Register); | |
| 5632 %} | |
| 624 | 5633 ins_pipe(iload_mask_mem); |
| 5634 %} | |
| 5635 | |
| 5636 // Load Unsigned Short/Char (16bit UNsigned) | |
| 5637 instruct loadUS(iRegI dst, memory mem) %{ | |
| 5638 match(Set dst (LoadUS mem)); | |
| 5639 ins_cost(MEMORY_REF_COST); | |
| 5640 | |
| 5641 size(4); | |
| 5642 format %{ "LDUH $mem,$dst\t! ushort/char" %} | |
| 727 | 5643 ins_encode %{ |
| 5644 __ lduh($mem$$Address, $dst$$Register); | |
| 5645 %} | |
| 824 | 5646 ins_pipe(iload_mem); |
| 0 | 5647 %} |
| 5648 | |
| 785 | 5649 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed) |
| 5650 instruct loadUS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ | |
| 5651 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour)); | |
| 5652 ins_cost(MEMORY_REF_COST); | |
| 5653 | |
| 5654 size(4); | |
| 5655 format %{ "LDSB $mem+1,$dst\t! ushort -> byte" %} | |
| 5656 ins_encode %{ | |
| 5657 __ ldsb($mem$$Address, $dst$$Register, 1); | |
| 5658 %} | |
| 5659 ins_pipe(iload_mask_mem); | |
| 5660 %} | |
| 5661 | |
|
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|
5662 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register |
| 624 | 5663 instruct loadUS2L(iRegL dst, memory mem) %{ |
| 5664 match(Set dst (ConvI2L (LoadUS mem))); | |
| 0 | 5665 ins_cost(MEMORY_REF_COST); |
| 5666 | |
| 5667 size(4); | |
| 624 | 5668 format %{ "LDUH $mem,$dst\t! ushort/char -> long" %} |
| 727 | 5669 ins_encode %{ |
| 5670 __ lduh($mem$$Address, $dst$$Register); | |
| 5671 %} | |
| 824 | 5672 ins_pipe(iload_mem); |
| 5673 %} | |
| 5674 | |
| 5675 // Load Unsigned Short/Char (16bit UNsigned) with mask 0xFF into a Long Register | |
| 5676 instruct loadUS2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{ | |
| 5677 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
| 5678 ins_cost(MEMORY_REF_COST); | |
| 5679 | |
| 5680 size(4); | |
| 5681 format %{ "LDUB $mem+1,$dst\t! ushort/char & 0xFF -> long" %} | |
| 5682 ins_encode %{ | |
| 5683 __ ldub($mem$$Address, $dst$$Register, 1); // LSB is index+1 on BE | |
| 5684 %} | |
| 5685 ins_pipe(iload_mem); | |
| 5686 %} | |
| 5687 | |
| 5688 // Load Unsigned Short/Char (16bit UNsigned) with a 13-bit mask into a Long Register | |
| 5689 instruct loadUS2L_immI13(iRegL dst, memory mem, immI13 mask) %{ | |
| 5690 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
| 5691 ins_cost(MEMORY_REF_COST + DEFAULT_COST); | |
| 5692 | |
| 5693 size(2*4); | |
| 5694 format %{ "LDUH $mem,$dst\t! ushort/char & 13-bit mask -> long\n\t" | |
| 5695 "AND $dst,$mask,$dst" %} | |
| 5696 ins_encode %{ | |
| 5697 Register Rdst = $dst$$Register; | |
| 5698 __ lduh($mem$$Address, Rdst); | |
| 5699 __ and3(Rdst, $mask$$constant, Rdst); | |
| 5700 %} | |
| 5701 ins_pipe(iload_mem); | |
| 5702 %} | |
| 5703 | |
| 5704 // Load Unsigned Short/Char (16bit UNsigned) with a 16-bit mask into a Long Register | |
| 5705 instruct loadUS2L_immI16(iRegL dst, memory mem, immI16 mask, iRegL tmp) %{ | |
| 5706 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
| 5707 effect(TEMP dst, TEMP tmp); | |
| 5708 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST); | |
| 5709 | |
|
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824
diff
changeset
|
5710 size((3+1)*4); // set may use two instructions. |
| 824 | 5711 format %{ "LDUH $mem,$dst\t! ushort/char & 16-bit mask -> long\n\t" |
| 5712 "SET $mask,$tmp\n\t" | |
| 5713 "AND $dst,$tmp,$dst" %} | |
| 5714 ins_encode %{ | |
| 5715 Register Rdst = $dst$$Register; | |
| 5716 Register Rtmp = $tmp$$Register; | |
| 5717 __ lduh($mem$$Address, Rdst); | |
| 5718 __ set($mask$$constant, Rtmp); | |
| 5719 __ and3(Rdst, Rtmp, Rdst); | |
| 5720 %} | |
| 5721 ins_pipe(iload_mem); | |
| 0 | 5722 %} |
| 5723 | |
| 5724 // Load Integer | |
| 5725 instruct loadI(iRegI dst, memory mem) %{ | |
| 5726 match(Set dst (LoadI mem)); | |
| 5727 ins_cost(MEMORY_REF_COST); | |
| 624 | 5728 |
| 5729 size(4); | |
| 5730 format %{ "LDUW $mem,$dst\t! int" %} | |
| 727 | 5731 ins_encode %{ |
| 5732 __ lduw($mem$$Address, $dst$$Register); | |
| 5733 %} | |
| 624 | 5734 ins_pipe(iload_mem); |
| 5735 %} | |
| 5736 | |
| 785 | 5737 // Load Integer to Byte (8 bit signed) |
| 5738 instruct loadI2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ | |
| 5739 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour)); | |
| 5740 ins_cost(MEMORY_REF_COST); | |
| 5741 | |
| 5742 size(4); | |
| 5743 | |
| 5744 format %{ "LDSB $mem+3,$dst\t! int -> byte" %} | |
| 5745 ins_encode %{ | |
| 5746 __ ldsb($mem$$Address, $dst$$Register, 3); | |
| 5747 %} | |
| 5748 ins_pipe(iload_mask_mem); | |
| 5749 %} | |
| 5750 | |
| 5751 // Load Integer to Unsigned Byte (8 bit UNsigned) | |
| 5752 instruct loadI2UB(iRegI dst, indOffset13m7 mem, immI_255 mask) %{ | |
| 5753 match(Set dst (AndI (LoadI mem) mask)); | |
| 5754 ins_cost(MEMORY_REF_COST); | |
| 5755 | |
| 5756 size(4); | |
| 5757 | |
| 5758 format %{ "LDUB $mem+3,$dst\t! int -> ubyte" %} | |
| 5759 ins_encode %{ | |
| 5760 __ ldub($mem$$Address, $dst$$Register, 3); | |
| 5761 %} | |
| 5762 ins_pipe(iload_mask_mem); | |
| 5763 %} | |
| 5764 | |
| 5765 // Load Integer to Short (16 bit signed) | |
| 5766 instruct loadI2S(iRegI dst, indOffset13m7 mem, immI_16 sixteen) %{ | |
| 5767 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen)); | |
| 5768 ins_cost(MEMORY_REF_COST); | |
| 5769 | |
| 5770 size(4); | |
| 5771 | |
| 5772 format %{ "LDSH $mem+2,$dst\t! int -> short" %} | |
| 5773 ins_encode %{ | |
| 5774 __ ldsh($mem$$Address, $dst$$Register, 2); | |
| 5775 %} | |
| 5776 ins_pipe(iload_mask_mem); | |
| 5777 %} | |
| 5778 | |
| 5779 // Load Integer to Unsigned Short (16 bit UNsigned) | |
| 5780 instruct loadI2US(iRegI dst, indOffset13m7 mem, immI_65535 mask) %{ | |
| 5781 match(Set dst (AndI (LoadI mem) mask)); | |
| 5782 ins_cost(MEMORY_REF_COST); | |
| 5783 | |
| 5784 size(4); | |
| 5785 | |
| 5786 format %{ "LDUH $mem+2,$dst\t! int -> ushort/char" %} | |
| 5787 ins_encode %{ | |
| 5788 __ lduh($mem$$Address, $dst$$Register, 2); | |
| 5789 %} | |
| 5790 ins_pipe(iload_mask_mem); | |
| 5791 %} | |
| 5792 | |
| 624 | 5793 // Load Integer into a Long Register |
| 5794 instruct loadI2L(iRegL dst, memory mem) %{ | |
| 5795 match(Set dst (ConvI2L (LoadI mem))); | |
| 5796 ins_cost(MEMORY_REF_COST); | |
| 5797 | |
| 5798 size(4); | |
| 5799 format %{ "LDSW $mem,$dst\t! int -> long" %} | |
| 727 | 5800 ins_encode %{ |
| 5801 __ ldsw($mem$$Address, $dst$$Register); | |
| 5802 %} | |
| 824 | 5803 ins_pipe(iload_mask_mem); |
| 5804 %} | |
| 5805 | |
| 5806 // Load Integer with mask 0xFF into a Long Register | |
| 5807 instruct loadI2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{ | |
| 5808 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
| 5809 ins_cost(MEMORY_REF_COST); | |
| 5810 | |
| 5811 size(4); | |
| 5812 format %{ "LDUB $mem+3,$dst\t! int & 0xFF -> long" %} | |
| 5813 ins_encode %{ | |
| 5814 __ ldub($mem$$Address, $dst$$Register, 3); // LSB is index+3 on BE | |
| 5815 %} | |
| 5816 ins_pipe(iload_mem); | |
| 5817 %} | |
| 5818 | |
| 5819 // Load Integer with mask 0xFFFF into a Long Register | |
| 5820 instruct loadI2L_immI_65535(iRegL dst, indOffset13m7 mem, immI_65535 mask) %{ | |
| 5821 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
| 5822 ins_cost(MEMORY_REF_COST); | |
| 5823 | |
| 5824 size(4); | |
| 5825 format %{ "LDUH $mem+2,$dst\t! int & 0xFFFF -> long" %} | |
| 5826 ins_encode %{ | |
| 5827 __ lduh($mem$$Address, $dst$$Register, 2); // LSW is index+2 on BE | |
| 5828 %} | |
| 5829 ins_pipe(iload_mem); | |
| 5830 %} | |
| 5831 | |
| 5832 // Load Integer with a 13-bit mask into a Long Register | |
| 5833 instruct loadI2L_immI13(iRegL dst, memory mem, immI13 mask) %{ | |
| 5834 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
| 5835 ins_cost(MEMORY_REF_COST + DEFAULT_COST); | |
| 5836 | |
| 5837 size(2*4); | |
| 5838 format %{ "LDUW $mem,$dst\t! int & 13-bit mask -> long\n\t" | |
| 5839 "AND $dst,$mask,$dst" %} | |
| 5840 ins_encode %{ | |
| 5841 Register Rdst = $dst$$Register; | |
| 5842 __ lduw($mem$$Address, Rdst); | |
| 5843 __ and3(Rdst, $mask$$constant, Rdst); | |
| 5844 %} | |
| 5845 ins_pipe(iload_mem); | |
| 5846 %} | |
| 5847 | |
| 5848 // Load Integer with a 32-bit mask into a Long Register | |
| 5849 instruct loadI2L_immI(iRegL dst, memory mem, immI mask, iRegL tmp) %{ | |
| 5850 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
| 5851 effect(TEMP dst, TEMP tmp); | |
| 5852 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST); | |
| 5853 | |
|
951
1fbd5d696bf4
6875967: CTW fails with./generated/adfiles/ad_sparc.cpp:6711
twisti
parents:
824
diff
changeset
|
5854 size((3+1)*4); // set may use two instructions. |
| 824 | 5855 format %{ "LDUW $mem,$dst\t! int & 32-bit mask -> long\n\t" |
| 5856 "SET $mask,$tmp\n\t" | |
| 5857 "AND $dst,$tmp,$dst" %} | |
| 5858 ins_encode %{ | |
| 5859 Register Rdst = $dst$$Register; | |
| 5860 Register Rtmp = $tmp$$Register; | |
| 5861 __ lduw($mem$$Address, Rdst); | |
| 5862 __ set($mask$$constant, Rtmp); | |
| 5863 __ and3(Rdst, Rtmp, Rdst); | |
| 5864 %} | |
| 624 | 5865 ins_pipe(iload_mem); |
| 5866 %} | |
| 5867 | |
| 5868 // Load Unsigned Integer into a Long Register | |
| 5869 instruct loadUI2L(iRegL dst, memory mem) %{ | |
| 5870 match(Set dst (LoadUI2L mem)); | |
| 5871 ins_cost(MEMORY_REF_COST); | |
| 5872 | |
| 5873 size(4); | |
| 5874 format %{ "LDUW $mem,$dst\t! uint -> long" %} | |
| 727 | 5875 ins_encode %{ |
| 5876 __ lduw($mem$$Address, $dst$$Register); | |
| 5877 %} | |
| 0 | 5878 ins_pipe(iload_mem); |
| 5879 %} | |
| 5880 | |
| 5881 // Load Long - aligned | |
| 5882 instruct loadL(iRegL dst, memory mem ) %{ | |
| 5883 match(Set dst (LoadL mem)); | |
| 5884 ins_cost(MEMORY_REF_COST); | |
| 624 | 5885 |
| 0 | 5886 size(4); |
| 5887 format %{ "LDX $mem,$dst\t! long" %} | |
| 727 | 5888 ins_encode %{ |
| 5889 __ ldx($mem$$Address, $dst$$Register); | |
| 5890 %} | |
| 0 | 5891 ins_pipe(iload_mem); |
| 5892 %} | |
| 5893 | |
| 5894 // Load Long - UNaligned | |
| 5895 instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{ | |
| 5896 match(Set dst (LoadL_unaligned mem)); | |
| 5897 effect(KILL tmp); | |
| 5898 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST); | |
| 5899 size(16); | |
| 5900 format %{ "LDUW $mem+4,R_O7\t! misaligned long\n" | |
| 5901 "\tLDUW $mem ,$dst\n" | |
| 5902 "\tSLLX #32, $dst, $dst\n" | |
| 5903 "\tOR $dst, R_O7, $dst" %} | |
| 5904 opcode(Assembler::lduw_op3); | |
|
415
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6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
235
diff
changeset
|
5905 ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst )); |
| 0 | 5906 ins_pipe(iload_mem); |
| 5907 %} | |
| 5908 | |
| 5909 // Load Aligned Packed Byte into a Double Register | |
| 5910 instruct loadA8B(regD dst, memory mem) %{ | |
| 5911 match(Set dst (Load8B mem)); | |
| 5912 ins_cost(MEMORY_REF_COST); | |
| 5913 size(4); | |
| 5914 format %{ "LDDF $mem,$dst\t! packed8B" %} | |
| 5915 opcode(Assembler::lddf_op3); | |
|
415
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never
parents:
235
diff
changeset
|
5916 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
| 0 | 5917 ins_pipe(floadD_mem); |
| 5918 %} | |
| 5919 | |
| 5920 // Load Aligned Packed Char into a Double Register | |
| 5921 instruct loadA4C(regD dst, memory mem) %{ | |
| 5922 match(Set dst (Load4C mem)); | |
| 5923 ins_cost(MEMORY_REF_COST); | |
| 5924 size(4); | |
| 5925 format %{ "LDDF $mem,$dst\t! packed4C" %} | |
| 5926 opcode(Assembler::lddf_op3); | |
|
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4d9884b01ba6
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never
parents:
235
diff
changeset
|
5927 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
| 0 | 5928 ins_pipe(floadD_mem); |
| 5929 %} | |
| 5930 | |
| 5931 // Load Aligned Packed Short into a Double Register | |
| 5932 instruct loadA4S(regD dst, memory mem) %{ | |
| 5933 match(Set dst (Load4S mem)); | |
| 5934 ins_cost(MEMORY_REF_COST); | |
| 5935 size(4); | |
| 5936 format %{ "LDDF $mem,$dst\t! packed4S" %} | |
| 5937 opcode(Assembler::lddf_op3); | |
|
415
4d9884b01ba6
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never
parents:
235
diff
changeset
|
5938 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
| 0 | 5939 ins_pipe(floadD_mem); |
| 5940 %} | |
| 5941 | |
| 5942 // Load Aligned Packed Int into a Double Register | |
| 5943 instruct loadA2I(regD dst, memory mem) %{ | |
| 5944 match(Set dst (Load2I mem)); | |
| 5945 ins_cost(MEMORY_REF_COST); | |
| 5946 size(4); | |
| 5947 format %{ "LDDF $mem,$dst\t! packed2I" %} | |
| 5948 opcode(Assembler::lddf_op3); | |
|
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5949 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
| 0 | 5950 ins_pipe(floadD_mem); |
| 5951 %} | |
| 5952 | |
| 5953 // Load Range | |
| 5954 instruct loadRange(iRegI dst, memory mem) %{ | |
| 5955 match(Set dst (LoadRange mem)); | |
| 5956 ins_cost(MEMORY_REF_COST); | |
| 5957 | |
| 5958 size(4); | |
| 5959 format %{ "LDUW $mem,$dst\t! range" %} | |
| 5960 opcode(Assembler::lduw_op3); | |
|
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5961 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
| 0 | 5962 ins_pipe(iload_mem); |
| 5963 %} | |
| 5964 | |
| 5965 // Load Integer into %f register (for fitos/fitod) | |
| 5966 instruct loadI_freg(regF dst, memory mem) %{ | |
| 5967 match(Set dst (LoadI mem)); | |
| 5968 ins_cost(MEMORY_REF_COST); | |
| 5969 size(4); | |
| 5970 | |
| 5971 format %{ "LDF $mem,$dst\t! for fitos/fitod" %} | |
| 5972 opcode(Assembler::ldf_op3); | |
|
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5973 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
| 0 | 5974 ins_pipe(floadF_mem); |
| 5975 %} | |
| 5976 | |
| 5977 // Load Pointer | |
| 5978 instruct loadP(iRegP dst, memory mem) %{ | |
| 5979 match(Set dst (LoadP mem)); | |
| 5980 ins_cost(MEMORY_REF_COST); | |
| 5981 size(4); | |
| 5982 | |
| 5983 #ifndef _LP64 | |
| 5984 format %{ "LDUW $mem,$dst\t! ptr" %} | |
| 727 | 5985 ins_encode %{ |
| 5986 __ lduw($mem$$Address, $dst$$Register); | |
| 5987 %} | |
| 0 | 5988 #else |
| 5989 format %{ "LDX $mem,$dst\t! ptr" %} | |
| 727 | 5990 ins_encode %{ |
| 5991 __ ldx($mem$$Address, $dst$$Register); | |
| 5992 %} | |
| 0 | 5993 #endif |
| 5994 ins_pipe(iload_mem); | |
| 5995 %} | |
| 5996 | |
|
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5997 // Load Compressed Pointer |
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5998 instruct loadN(iRegN dst, memory mem) %{ |
| 727 | 5999 match(Set dst (LoadN mem)); |
| 6000 ins_cost(MEMORY_REF_COST); | |
| 6001 size(4); | |
| 6002 | |
| 6003 format %{ "LDUW $mem,$dst\t! compressed ptr" %} | |
| 6004 ins_encode %{ | |
| 6005 __ lduw($mem$$Address, $dst$$Register); | |
| 6006 %} | |
| 6007 ins_pipe(iload_mem); | |
|
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6008 %} |
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6009 |
| 0 | 6010 // Load Klass Pointer |
| 6011 instruct loadKlass(iRegP dst, memory mem) %{ | |
| 6012 match(Set dst (LoadKlass mem)); | |
| 6013 ins_cost(MEMORY_REF_COST); | |
| 6014 size(4); | |
| 6015 | |
| 6016 #ifndef _LP64 | |
| 6017 format %{ "LDUW $mem,$dst\t! klass ptr" %} | |
| 727 | 6018 ins_encode %{ |
| 6019 __ lduw($mem$$Address, $dst$$Register); | |
| 6020 %} | |
| 0 | 6021 #else |
| 6022 format %{ "LDX $mem,$dst\t! klass ptr" %} | |
| 727 | 6023 ins_encode %{ |
| 6024 __ ldx($mem$$Address, $dst$$Register); | |
| 6025 %} | |
| 0 | 6026 #endif |
| 6027 ins_pipe(iload_mem); | |
| 6028 %} | |
| 6029 | |
|
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6030 // Load narrow Klass Pointer |
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6031 instruct loadNKlass(iRegN dst, memory mem) %{ |
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6032 match(Set dst (LoadNKlass mem)); |
|
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6033 ins_cost(MEMORY_REF_COST); |
|
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6034 size(4); |
|
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6035 |
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6036 format %{ "LDUW $mem,$dst\t! compressed klass ptr" %} |
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6037 ins_encode %{ |
| 727 | 6038 __ lduw($mem$$Address, $dst$$Register); |
|
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6039 %} |
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6040 ins_pipe(iload_mem); |
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6041 %} |
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6042 |
| 0 | 6043 // Load Double |
| 6044 instruct loadD(regD dst, memory mem) %{ | |
| 6045 match(Set dst (LoadD mem)); | |
| 6046 ins_cost(MEMORY_REF_COST); | |
| 6047 | |
| 6048 size(4); | |
| 6049 format %{ "LDDF $mem,$dst" %} | |
| 6050 opcode(Assembler::lddf_op3); | |
|
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6051 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
| 0 | 6052 ins_pipe(floadD_mem); |
| 6053 %} | |
| 6054 | |
| 6055 // Load Double - UNaligned | |
| 6056 instruct loadD_unaligned(regD_low dst, memory mem ) %{ | |
| 6057 match(Set dst (LoadD_unaligned mem)); | |
| 6058 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST); | |
| 6059 size(8); | |
| 6060 format %{ "LDF $mem ,$dst.hi\t! misaligned double\n" | |
| 6061 "\tLDF $mem+4,$dst.lo\t!" %} | |
| 6062 opcode(Assembler::ldf_op3); | |
| 6063 ins_encode( form3_mem_reg_double_unaligned( mem, dst )); | |
| 6064 ins_pipe(iload_mem); | |
| 6065 %} | |
| 6066 | |
| 6067 // Load Float | |
| 6068 instruct loadF(regF dst, memory mem) %{ | |
| 6069 match(Set dst (LoadF mem)); | |
| 6070 ins_cost(MEMORY_REF_COST); | |
| 6071 | |
| 6072 size(4); | |
| 6073 format %{ "LDF $mem,$dst" %} | |
| 6074 opcode(Assembler::ldf_op3); | |
|
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6075 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
| 0 | 6076 ins_pipe(floadF_mem); |
| 6077 %} | |
| 6078 | |
| 6079 // Load Constant | |
| 6080 instruct loadConI( iRegI dst, immI src ) %{ | |
| 6081 match(Set dst src); | |
| 6082 ins_cost(DEFAULT_COST * 3/2); | |
| 6083 format %{ "SET $src,$dst" %} | |
| 6084 ins_encode( Set32(src, dst) ); | |
| 6085 ins_pipe(ialu_hi_lo_reg); | |
| 6086 %} | |
| 6087 | |
| 6088 instruct loadConI13( iRegI dst, immI13 src ) %{ | |
| 6089 match(Set dst src); | |
| 6090 | |
| 6091 size(4); | |
| 6092 format %{ "MOV $src,$dst" %} | |
| 6093 ins_encode( Set13( src, dst ) ); | |
| 6094 ins_pipe(ialu_imm); | |
| 6095 %} | |
| 6096 | |
| 2008 | 6097 #ifndef _LP64 |
| 6098 instruct loadConP(iRegP dst, immP con) %{ | |
| 6099 match(Set dst con); | |
| 6100 ins_cost(DEFAULT_COST * 3/2); | |
| 6101 format %{ "SET $con,$dst\t!ptr" %} | |
| 6102 ins_encode %{ | |
| 6103 // [RGV] This next line should be generated from ADLC | |
| 6104 if (_opnds[1]->constant_is_oop()) { | |
| 6105 intptr_t val = $con$$constant; | |
| 6106 __ set_oop_constant((jobject) val, $dst$$Register); | |
| 6107 } else { // non-oop pointers, e.g. card mark base, heap top | |
| 6108 __ set($con$$constant, $dst$$Register); | |
| 6109 } | |
| 6110 %} | |
| 6111 ins_pipe(loadConP); | |
| 6112 %} | |
| 6113 #else | |
| 6114 instruct loadConP_set(iRegP dst, immP_set con) %{ | |
| 6115 match(Set dst con); | |
| 0 | 6116 ins_cost(DEFAULT_COST * 3/2); |
| 2008 | 6117 format %{ "SET $con,$dst\t! ptr" %} |
| 6118 ins_encode %{ | |
| 6119 // [RGV] This next line should be generated from ADLC | |
| 6120 if (_opnds[1]->constant_is_oop()) { | |
| 6121 intptr_t val = $con$$constant; | |
| 6122 __ set_oop_constant((jobject) val, $dst$$Register); | |
| 6123 } else { // non-oop pointers, e.g. card mark base, heap top | |
| 6124 __ set($con$$constant, $dst$$Register); | |
| 6125 } | |
| 6126 %} | |
| 0 | 6127 ins_pipe(loadConP); |
| 2008 | 6128 %} |
| 6129 | |
| 6130 instruct loadConP_load(iRegP dst, immP_load con) %{ | |
| 6131 match(Set dst con); | |
| 6132 ins_cost(MEMORY_REF_COST); | |
| 6133 format %{ "LD [$constanttablebase + $constantoffset],$dst\t! load from constant table: ptr=$con" %} | |
| 6134 ins_encode %{ | |
|
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6135 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register); |
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6136 __ ld_ptr($constanttablebase, con_offset, $dst$$Register); |
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6137 %} |
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6138 ins_pipe(loadConP); |
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6139 %} |
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|
6140 |
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6141 instruct loadConP_no_oop_cheap(iRegP dst, immP_no_oop_cheap con) %{ |
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6142 match(Set dst con); |
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6143 ins_cost(DEFAULT_COST * 3/2); |
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6144 format %{ "SET $con,$dst\t! non-oop ptr" %} |
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6145 ins_encode %{ |
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6146 __ set($con$$constant, $dst$$Register); |
| 2008 | 6147 %} |
| 6148 ins_pipe(loadConP); | |
| 6149 %} | |
| 6150 #endif // _LP64 | |
| 0 | 6151 |
| 6152 instruct loadConP0(iRegP dst, immP0 src) %{ | |
| 6153 match(Set dst src); | |
| 6154 | |
| 6155 size(4); | |
| 6156 format %{ "CLR $dst\t!ptr" %} | |
| 2008 | 6157 ins_encode %{ |
| 6158 __ clr($dst$$Register); | |
| 6159 %} | |
| 0 | 6160 ins_pipe(ialu_imm); |
| 6161 %} | |
| 6162 | |
| 6163 instruct loadConP_poll(iRegP dst, immP_poll src) %{ | |
| 6164 match(Set dst src); | |
| 6165 ins_cost(DEFAULT_COST); | |
| 6166 format %{ "SET $src,$dst\t!ptr" %} | |
| 6167 ins_encode %{ | |
| 727 | 6168 AddressLiteral polling_page(os::get_polling_page()); |
| 6169 __ sethi(polling_page, reg_to_register_object($dst$$reg)); | |
| 0 | 6170 %} |
| 6171 ins_pipe(loadConP_poll); | |
| 6172 %} | |
| 6173 | |
|
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6174 instruct loadConN0(iRegN dst, immN0 src) %{ |
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6175 match(Set dst src); |
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6176 |
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6177 size(4); |
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6178 format %{ "CLR $dst\t! compressed NULL ptr" %} |
| 2008 | 6179 ins_encode %{ |
| 6180 __ clr($dst$$Register); | |
| 6181 %} | |
|
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6182 ins_pipe(ialu_imm); |
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6183 %} |
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6184 |
|
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6185 instruct loadConN(iRegN dst, immN src) %{ |
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6186 match(Set dst src); |
|
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6187 ins_cost(DEFAULT_COST * 3/2); |
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6188 format %{ "SET $src,$dst\t! compressed ptr" %} |
|
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6189 ins_encode %{ |
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6190 Register dst = $dst$$Register; |
|
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6191 __ set_narrow_oop((jobject)$src$$constant, dst); |
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6192 %} |
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6193 ins_pipe(ialu_hi_lo_reg); |
|
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6194 %} |
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6195 |
| 2008 | 6196 // Materialize long value (predicated by immL_cheap). |
| 6197 instruct loadConL_set64(iRegL dst, immL_cheap con, o7RegL tmp) %{ | |
| 6198 match(Set dst con); | |
| 0 | 6199 effect(KILL tmp); |
| 2008 | 6200 ins_cost(DEFAULT_COST * 3); |
| 6201 format %{ "SET64 $con,$dst KILL $tmp\t! cheap long" %} | |
| 6202 ins_encode %{ | |
| 6203 __ set64($con$$constant, $dst$$Register, $tmp$$Register); | |
| 6204 %} | |
| 6205 ins_pipe(loadConL); | |
| 6206 %} | |
| 6207 | |
| 6208 // Load long value from constant table (predicated by immL_expensive). | |
| 6209 instruct loadConL_ldx(iRegL dst, immL_expensive con) %{ | |
| 6210 match(Set dst con); | |
| 6211 ins_cost(MEMORY_REF_COST); | |
| 6212 format %{ "LDX [$constanttablebase + $constantoffset],$dst\t! load from constant table: long=$con" %} | |
| 6213 ins_encode %{ | |
|
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6214 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register); |
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6215 __ ldx($constanttablebase, con_offset, $dst$$Register); |
| 2008 | 6216 %} |
| 0 | 6217 ins_pipe(loadConL); |
| 6218 %} | |
| 6219 | |
| 6220 instruct loadConL0( iRegL dst, immL0 src ) %{ | |
| 6221 match(Set dst src); | |
| 6222 ins_cost(DEFAULT_COST); | |
| 6223 size(4); | |
| 6224 format %{ "CLR $dst\t! long" %} | |
| 6225 ins_encode( Set13( src, dst ) ); | |
| 6226 ins_pipe(ialu_imm); | |
| 6227 %} | |
| 6228 | |
| 6229 instruct loadConL13( iRegL dst, immL13 src ) %{ | |
| 6230 match(Set dst src); | |
| 6231 ins_cost(DEFAULT_COST * 2); | |
| 6232 | |
| 6233 size(4); | |
| 6234 format %{ "MOV $src,$dst\t! long" %} | |
| 6235 ins_encode( Set13( src, dst ) ); | |
| 6236 ins_pipe(ialu_imm); | |
| 6237 %} | |
| 6238 | |
|
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|
6239 instruct loadConF(regF dst, immF con, o7RegI tmp) %{ |
| 2008 | 6240 match(Set dst con); |
|
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|
6241 effect(KILL tmp); |
| 2008 | 6242 format %{ "LDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: float=$con" %} |
| 727 | 6243 ins_encode %{ |
|
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|
6244 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register); |
|
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diff
changeset
|
6245 __ ldf(FloatRegisterImpl::S, $constanttablebase, con_offset, $dst$$FloatRegister); |
| 727 | 6246 %} |
| 0 | 6247 ins_pipe(loadConFD); |
| 6248 %} | |
| 6249 | |
|
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diff
changeset
|
6250 instruct loadConD(regD dst, immD con, o7RegI tmp) %{ |
| 2008 | 6251 match(Set dst con); |
|
2012
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diff
changeset
|
6252 effect(KILL tmp); |
| 2008 | 6253 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: double=$con" %} |
| 727 | 6254 ins_encode %{ |
|
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|
6255 // XXX This is a quick fix for 6833573. |
| 2008 | 6256 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset($con), $dst$$FloatRegister); |
|
2012
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|
6257 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register); |
|
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diff
changeset
|
6258 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); |
| 727 | 6259 %} |
| 0 | 6260 ins_pipe(loadConFD); |
| 6261 %} | |
| 6262 | |
| 6263 // Prefetch instructions. | |
| 6264 // Must be safe to execute with invalid address (cannot fault). | |
| 6265 | |
| 6266 instruct prefetchr( memory mem ) %{ | |
| 6267 match( PrefetchRead mem ); | |
| 6268 ins_cost(MEMORY_REF_COST); | |
| 3854 | 6269 size(4); |
| 0 | 6270 |
| 6271 format %{ "PREFETCH $mem,0\t! Prefetch read-many" %} | |
| 6272 opcode(Assembler::prefetch_op3); | |
| 6273 ins_encode( form3_mem_prefetch_read( mem ) ); | |
| 6274 ins_pipe(iload_mem); | |
| 6275 %} | |
| 6276 | |
| 6277 instruct prefetchw( memory mem ) %{ | |
| 6278 match( PrefetchWrite mem ); | |
| 6279 ins_cost(MEMORY_REF_COST); | |
| 3854 | 6280 size(4); |
| 0 | 6281 |
| 6282 format %{ "PREFETCH $mem,2\t! Prefetch write-many (and read)" %} | |
| 6283 opcode(Assembler::prefetch_op3); | |
| 6284 ins_encode( form3_mem_prefetch_write( mem ) ); | |
| 6285 ins_pipe(iload_mem); | |
| 6286 %} | |
| 6287 | |
| 3854 | 6288 // Prefetch instructions for allocation. |
| 6289 | |
| 6290 instruct prefetchAlloc( memory mem ) %{ | |
| 6291 predicate(AllocatePrefetchInstr == 0); | |
| 6292 match( PrefetchAllocation mem ); | |
| 6293 ins_cost(MEMORY_REF_COST); | |
| 6294 size(4); | |
| 6295 | |
| 6296 format %{ "PREFETCH $mem,2\t! Prefetch allocation" %} | |
| 6297 opcode(Assembler::prefetch_op3); | |
| 6298 ins_encode( form3_mem_prefetch_write( mem ) ); | |
| 6299 ins_pipe(iload_mem); | |
| 6300 %} | |
| 6301 | |
| 6302 // Use BIS instruction to prefetch for allocation. | |
| 6303 // Could fault, need space at the end of TLAB. | |
| 6304 instruct prefetchAlloc_bis( iRegP dst ) %{ | |
| 6305 predicate(AllocatePrefetchInstr == 1); | |
| 6306 match( PrefetchAllocation dst ); | |
| 6307 ins_cost(MEMORY_REF_COST); | |
| 6308 size(4); | |
| 6309 | |
| 6310 format %{ "STXA [$dst]\t! // Prefetch allocation using BIS" %} | |
| 6311 ins_encode %{ | |
| 6312 __ stxa(G0, $dst$$Register, G0, Assembler::ASI_ST_BLKINIT_PRIMARY); | |
|
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|
6313 %} |
|
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|
6314 ins_pipe(istore_mem_reg); |
|
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|
6315 %} |
| 0 | 6316 |
| 3854 | 6317 // Next code is used for finding next cache line address to prefetch. |
| 6318 #ifndef _LP64 | |
| 6319 instruct cacheLineAdr( iRegP dst, iRegP src, immI13 mask ) %{ | |
| 6320 match(Set dst (CastX2P (AndI (CastP2X src) mask))); | |
| 6321 ins_cost(DEFAULT_COST); | |
| 6322 size(4); | |
| 6323 | |
| 6324 format %{ "AND $src,$mask,$dst\t! next cache line address" %} | |
| 6325 ins_encode %{ | |
| 6326 __ and3($src$$Register, $mask$$constant, $dst$$Register); | |
| 6327 %} | |
| 6328 ins_pipe(ialu_reg_imm); | |
| 6329 %} | |
| 6330 #else | |
| 6331 instruct cacheLineAdr( iRegP dst, iRegP src, immL13 mask ) %{ | |
| 6332 match(Set dst (CastX2P (AndL (CastP2X src) mask))); | |
| 6333 ins_cost(DEFAULT_COST); | |
| 6334 size(4); | |
| 6335 | |
| 6336 format %{ "AND $src,$mask,$dst\t! next cache line address" %} | |
| 6337 ins_encode %{ | |
| 6338 __ and3($src$$Register, $mask$$constant, $dst$$Register); | |
| 6339 %} | |
| 6340 ins_pipe(ialu_reg_imm); | |
| 6341 %} | |
| 6342 #endif | |
| 6343 | |
| 0 | 6344 //----------Store Instructions------------------------------------------------- |
| 6345 // Store Byte | |
| 6346 instruct storeB(memory mem, iRegI src) %{ | |
| 6347 match(Set mem (StoreB mem src)); | |
| 6348 ins_cost(MEMORY_REF_COST); | |
| 6349 | |
| 6350 size(4); | |
| 6351 format %{ "STB $src,$mem\t! byte" %} | |
| 6352 opcode(Assembler::stb_op3); | |
|
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|
6353 ins_encode(simple_form3_mem_reg( mem, src ) ); |
| 0 | 6354 ins_pipe(istore_mem_reg); |
| 6355 %} | |
| 6356 | |
| 6357 instruct storeB0(memory mem, immI0 src) %{ | |
| 6358 match(Set mem (StoreB mem src)); | |
| 6359 ins_cost(MEMORY_REF_COST); | |
| 6360 | |
| 6361 size(4); | |
| 6362 format %{ "STB $src,$mem\t! byte" %} | |
| 6363 opcode(Assembler::stb_op3); | |
|
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|
6364 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
| 0 | 6365 ins_pipe(istore_mem_zero); |
| 6366 %} | |
| 6367 | |
| 6368 instruct storeCM0(memory mem, immI0 src) %{ | |
| 6369 match(Set mem (StoreCM mem src)); | |
| 6370 ins_cost(MEMORY_REF_COST); | |
| 6371 | |
| 6372 size(4); | |
| 6373 format %{ "STB $src,$mem\t! CMS card-mark byte 0" %} | |
| 6374 opcode(Assembler::stb_op3); | |
|
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|
6375 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
| 0 | 6376 ins_pipe(istore_mem_zero); |
| 6377 %} | |
| 6378 | |
| 6379 // Store Char/Short | |
| 6380 instruct storeC(memory mem, iRegI src) %{ | |
| 6381 match(Set mem (StoreC mem src)); | |
| 6382 ins_cost(MEMORY_REF_COST); | |
| 6383 | |
| 6384 size(4); | |
| 6385 format %{ "STH $src,$mem\t! short" %} | |
| 6386 opcode(Assembler::sth_op3); | |
|
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|
6387 ins_encode(simple_form3_mem_reg( mem, src ) ); |
| 0 | 6388 ins_pipe(istore_mem_reg); |
| 6389 %} | |
| 6390 | |
| 6391 instruct storeC0(memory mem, immI0 src) %{ | |
| 6392 match(Set mem (StoreC mem src)); | |
| 6393 ins_cost(MEMORY_REF_COST); | |
| 6394 | |
| 6395 size(4); | |
| 6396 format %{ "STH $src,$mem\t! short" %} | |
| 6397 opcode(Assembler::sth_op3); | |
|
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|
6398 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
| 0 | 6399 ins_pipe(istore_mem_zero); |
| 6400 %} | |
| 6401 | |
| 6402 // Store Integer | |
| 6403 instruct storeI(memory mem, iRegI src) %{ | |
| 6404 match(Set mem (StoreI mem src)); | |
| 6405 ins_cost(MEMORY_REF_COST); | |
| 6406 | |
| 6407 size(4); | |
| 6408 format %{ "STW $src,$mem" %} | |
| 6409 opcode(Assembler::stw_op3); | |
|
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|
6410 ins_encode(simple_form3_mem_reg( mem, src ) ); |
| 0 | 6411 ins_pipe(istore_mem_reg); |
| 6412 %} | |
| 6413 | |
| 6414 // Store Long | |
| 6415 instruct storeL(memory mem, iRegL src) %{ | |
| 6416 match(Set mem (StoreL mem src)); | |
| 6417 ins_cost(MEMORY_REF_COST); | |
| 6418 size(4); | |
| 6419 format %{ "STX $src,$mem\t! long" %} | |
| 6420 opcode(Assembler::stx_op3); | |
|
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|
6421 ins_encode(simple_form3_mem_reg( mem, src ) ); |
| 0 | 6422 ins_pipe(istore_mem_reg); |
| 6423 %} | |
| 6424 | |
| 6425 instruct storeI0(memory mem, immI0 src) %{ | |
| 6426 match(Set mem (StoreI mem src)); | |
| 6427 ins_cost(MEMORY_REF_COST); | |
| 6428 | |
| 6429 size(4); | |
| 6430 format %{ "STW $src,$mem" %} | |
| 6431 opcode(Assembler::stw_op3); | |
|
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|
6432 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
| 0 | 6433 ins_pipe(istore_mem_zero); |
| 6434 %} | |
| 6435 | |
| 6436 instruct storeL0(memory mem, immL0 src) %{ | |
| 6437 match(Set mem (StoreL mem src)); | |
| 6438 ins_cost(MEMORY_REF_COST); | |
| 6439 | |
| 6440 size(4); | |
| 6441 format %{ "STX $src,$mem" %} | |
| 6442 opcode(Assembler::stx_op3); | |
|
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|
6443 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
| 0 | 6444 ins_pipe(istore_mem_zero); |
| 6445 %} | |
| 6446 | |
| 6447 // Store Integer from float register (used after fstoi) | |
| 6448 instruct storeI_Freg(memory mem, regF src) %{ | |
| 6449 match(Set mem (StoreI mem src)); | |
| 6450 ins_cost(MEMORY_REF_COST); | |
| 6451 | |
| 6452 size(4); | |
| 6453 format %{ "STF $src,$mem\t! after fstoi/fdtoi" %} | |
| 6454 opcode(Assembler::stf_op3); | |
|
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|
6455 ins_encode(simple_form3_mem_reg( mem, src ) ); |
| 0 | 6456 ins_pipe(fstoreF_mem_reg); |
| 6457 %} | |
| 6458 | |
| 6459 // Store Pointer | |
| 6460 instruct storeP(memory dst, sp_ptr_RegP src) %{ | |
| 6461 match(Set dst (StoreP dst src)); | |
| 6462 ins_cost(MEMORY_REF_COST); | |
| 6463 size(4); | |
| 6464 | |
| 6465 #ifndef _LP64 | |
| 6466 format %{ "STW $src,$dst\t! ptr" %} | |
| 6467 opcode(Assembler::stw_op3, 0, REGP_OP); | |
| 6468 #else | |
| 6469 format %{ "STX $src,$dst\t! ptr" %} | |
| 6470 opcode(Assembler::stx_op3, 0, REGP_OP); | |
| 6471 #endif | |
| 6472 ins_encode( form3_mem_reg( dst, src ) ); | |
| 6473 ins_pipe(istore_mem_spORreg); | |
| 6474 %} | |
| 6475 | |
| 6476 instruct storeP0(memory dst, immP0 src) %{ | |
| 6477 match(Set dst (StoreP dst src)); | |
| 6478 ins_cost(MEMORY_REF_COST); | |
| 6479 size(4); | |
| 6480 | |
| 6481 #ifndef _LP64 | |
| 6482 format %{ "STW $src,$dst\t! ptr" %} | |
| 6483 opcode(Assembler::stw_op3, 0, REGP_OP); | |
| 6484 #else | |
| 6485 format %{ "STX $src,$dst\t! ptr" %} | |
| 6486 opcode(Assembler::stx_op3, 0, REGP_OP); | |
| 6487 #endif | |
| 6488 ins_encode( form3_mem_reg( dst, R_G0 ) ); | |
| 6489 ins_pipe(istore_mem_zero); | |
| 6490 %} | |
| 6491 | |
|
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|
6492 // Store Compressed Pointer |
|
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6493 instruct storeN(memory dst, iRegN src) %{ |
|
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|
6494 match(Set dst (StoreN dst src)); |
|
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|
6495 ins_cost(MEMORY_REF_COST); |
|
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|
6496 size(4); |
|
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|
6497 |
|
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|
6498 format %{ "STW $src,$dst\t! compressed ptr" %} |
|
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|
6499 ins_encode %{ |
|
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|
6500 Register base = as_Register($dst$$base); |
|
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|
6501 Register index = as_Register($dst$$index); |
|
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|
6502 Register src = $src$$Register; |
|
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|
6503 if (index != G0) { |
|
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|
6504 __ stw(src, base, index); |
|
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6505 } else { |
|
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|
6506 __ stw(src, base, $dst$$disp); |
|
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6507 } |
|
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|
6508 %} |
|
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|
6509 ins_pipe(istore_mem_spORreg); |
|
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|
6510 %} |
|
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|
6511 |
|
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|
6512 instruct storeN0(memory dst, immN0 src) %{ |
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6513 match(Set dst (StoreN dst src)); |
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6514 ins_cost(MEMORY_REF_COST); |
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6515 size(4); |
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6516 |
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|
6517 format %{ "STW $src,$dst\t! compressed ptr" %} |
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6518 ins_encode %{ |
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6519 Register base = as_Register($dst$$base); |
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6520 Register index = as_Register($dst$$index); |
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6521 if (index != G0) { |
|
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6522 __ stw(0, base, index); |
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6523 } else { |
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6524 __ stw(0, base, $dst$$disp); |
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6525 } |
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6526 %} |
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6527 ins_pipe(istore_mem_zero); |
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6528 %} |
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6529 |
| 0 | 6530 // Store Double |
| 6531 instruct storeD( memory mem, regD src) %{ | |
| 6532 match(Set mem (StoreD mem src)); | |
| 6533 ins_cost(MEMORY_REF_COST); | |
| 6534 | |
| 6535 size(4); | |
| 6536 format %{ "STDF $src,$mem" %} | |
| 6537 opcode(Assembler::stdf_op3); | |
|
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6538 ins_encode(simple_form3_mem_reg( mem, src ) ); |
| 0 | 6539 ins_pipe(fstoreD_mem_reg); |
| 6540 %} | |
| 6541 | |
| 6542 instruct storeD0( memory mem, immD0 src) %{ | |
| 6543 match(Set mem (StoreD mem src)); | |
| 6544 ins_cost(MEMORY_REF_COST); | |
| 6545 | |
| 6546 size(4); | |
| 6547 format %{ "STX $src,$mem" %} | |
| 6548 opcode(Assembler::stx_op3); | |
|
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6549 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
| 0 | 6550 ins_pipe(fstoreD_mem_zero); |
| 6551 %} | |
| 6552 | |
| 6553 // Store Float | |
| 6554 instruct storeF( memory mem, regF src) %{ | |
| 6555 match(Set mem (StoreF mem src)); | |
| 6556 ins_cost(MEMORY_REF_COST); | |
| 6557 | |
| 6558 size(4); | |
| 6559 format %{ "STF $src,$mem" %} | |
| 6560 opcode(Assembler::stf_op3); | |
|
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|
6561 ins_encode(simple_form3_mem_reg( mem, src ) ); |
| 0 | 6562 ins_pipe(fstoreF_mem_reg); |
| 6563 %} | |
| 6564 | |
| 6565 instruct storeF0( memory mem, immF0 src) %{ | |
| 6566 match(Set mem (StoreF mem src)); | |
| 6567 ins_cost(MEMORY_REF_COST); | |
| 6568 | |
| 6569 size(4); | |
| 6570 format %{ "STW $src,$mem\t! storeF0" %} | |
| 6571 opcode(Assembler::stw_op3); | |
|
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|
6572 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
| 0 | 6573 ins_pipe(fstoreF_mem_zero); |
| 6574 %} | |
| 6575 | |
| 6576 // Store Aligned Packed Bytes in Double register to memory | |
| 6577 instruct storeA8B(memory mem, regD src) %{ | |
| 6578 match(Set mem (Store8B mem src)); | |
| 6579 ins_cost(MEMORY_REF_COST); | |
| 6580 size(4); | |
| 6581 format %{ "STDF $src,$mem\t! packed8B" %} | |
| 6582 opcode(Assembler::stdf_op3); | |
|
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|
6583 ins_encode(simple_form3_mem_reg( mem, src ) ); |
| 0 | 6584 ins_pipe(fstoreD_mem_reg); |
| 6585 %} | |
| 6586 | |
|
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6587 // Convert oop pointer into compressed form |
|
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6588 instruct encodeHeapOop(iRegN dst, iRegP src) %{ |
|
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|
6589 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull); |
|
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6590 match(Set dst (EncodeP src)); |
|
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6591 format %{ "encode_heap_oop $src, $dst" %} |
|
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6592 ins_encode %{ |
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6593 __ encode_heap_oop($src$$Register, $dst$$Register); |
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6594 %} |
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|
6595 ins_pipe(ialu_reg); |
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|
6596 %} |
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|
6597 |
|
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|
6598 instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{ |
|
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6599 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull); |
|
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6600 match(Set dst (EncodeP src)); |
|
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|
6601 format %{ "encode_heap_oop_not_null $src, $dst" %} |
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|
6602 ins_encode %{ |
|
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|
6603 __ encode_heap_oop_not_null($src$$Register, $dst$$Register); |
|
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|
6604 %} |
|
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|
6605 ins_pipe(ialu_reg); |
|
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|
6606 %} |
|
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|
6607 |
|
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6608 instruct decodeHeapOop(iRegP dst, iRegN src) %{ |
|
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6609 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull && |
|
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6610 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant); |
|
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6611 match(Set dst (DecodeN src)); |
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6612 format %{ "decode_heap_oop $src, $dst" %} |
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6613 ins_encode %{ |
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6614 __ decode_heap_oop($src$$Register, $dst$$Register); |
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6615 %} |
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|
6616 ins_pipe(ialu_reg); |
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6617 %} |
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|
6618 |
|
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6619 instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{ |
|
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6620 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull || |
|
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|
6621 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant); |
|
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6622 match(Set dst (DecodeN src)); |
|
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|
6623 format %{ "decode_heap_oop_not_null $src, $dst" %} |
|
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|
6624 ins_encode %{ |
|
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|
6625 __ decode_heap_oop_not_null($src$$Register, $dst$$Register); |
|
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|
6626 %} |
|
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|
6627 ins_pipe(ialu_reg); |
|
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|
6628 %} |
|
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|
6629 |
|
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6630 |
| 0 | 6631 // Store Zero into Aligned Packed Bytes |
| 6632 instruct storeA8B0(memory mem, immI0 zero) %{ | |
| 6633 match(Set mem (Store8B mem zero)); | |
| 6634 ins_cost(MEMORY_REF_COST); | |
| 6635 size(4); | |
| 6636 format %{ "STX $zero,$mem\t! packed8B" %} | |
| 6637 opcode(Assembler::stx_op3); | |
|
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|
6638 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
| 0 | 6639 ins_pipe(fstoreD_mem_zero); |
| 6640 %} | |
| 6641 | |
| 6642 // Store Aligned Packed Chars/Shorts in Double register to memory | |
| 6643 instruct storeA4C(memory mem, regD src) %{ | |
| 6644 match(Set mem (Store4C mem src)); | |
| 6645 ins_cost(MEMORY_REF_COST); | |
| 6646 size(4); | |
| 6647 format %{ "STDF $src,$mem\t! packed4C" %} | |
| 6648 opcode(Assembler::stdf_op3); | |
|
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|
6649 ins_encode(simple_form3_mem_reg( mem, src ) ); |
| 0 | 6650 ins_pipe(fstoreD_mem_reg); |
| 6651 %} | |
| 6652 | |
| 6653 // Store Zero into Aligned Packed Chars/Shorts | |
| 6654 instruct storeA4C0(memory mem, immI0 zero) %{ | |
| 6655 match(Set mem (Store4C mem (Replicate4C zero))); | |
| 6656 ins_cost(MEMORY_REF_COST); | |
| 6657 size(4); | |
| 6658 format %{ "STX $zero,$mem\t! packed4C" %} | |
| 6659 opcode(Assembler::stx_op3); | |
|
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|
6660 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
| 0 | 6661 ins_pipe(fstoreD_mem_zero); |
| 6662 %} | |
| 6663 | |
| 6664 // Store Aligned Packed Ints in Double register to memory | |
| 6665 instruct storeA2I(memory mem, regD src) %{ | |
| 6666 match(Set mem (Store2I mem src)); | |
| 6667 ins_cost(MEMORY_REF_COST); | |
| 6668 size(4); | |
| 6669 format %{ "STDF $src,$mem\t! packed2I" %} | |
| 6670 opcode(Assembler::stdf_op3); | |
|
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6671 ins_encode(simple_form3_mem_reg( mem, src ) ); |
| 0 | 6672 ins_pipe(fstoreD_mem_reg); |
| 6673 %} | |
| 6674 | |
| 6675 // Store Zero into Aligned Packed Ints | |
| 6676 instruct storeA2I0(memory mem, immI0 zero) %{ | |
| 6677 match(Set mem (Store2I mem zero)); | |
| 6678 ins_cost(MEMORY_REF_COST); | |
| 6679 size(4); | |
| 6680 format %{ "STX $zero,$mem\t! packed2I" %} | |
| 6681 opcode(Assembler::stx_op3); | |
|
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6682 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
| 0 | 6683 ins_pipe(fstoreD_mem_zero); |
| 6684 %} | |
| 6685 | |
| 6686 | |
| 6687 //----------MemBar Instructions----------------------------------------------- | |
| 6688 // Memory barrier flavors | |
| 6689 | |
| 6690 instruct membar_acquire() %{ | |
| 6691 match(MemBarAcquire); | |
| 6692 ins_cost(4*MEMORY_REF_COST); | |
| 6693 | |
| 6694 size(0); | |
| 6695 format %{ "MEMBAR-acquire" %} | |
| 6696 ins_encode( enc_membar_acquire ); | |
| 6697 ins_pipe(long_memory_op); | |
| 6698 %} | |
| 6699 | |
| 6700 instruct membar_acquire_lock() %{ | |
|
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|
6701 match(MemBarAcquireLock); |
| 0 | 6702 ins_cost(0); |
| 6703 | |
| 6704 size(0); | |
| 6705 format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %} | |
| 6706 ins_encode( ); | |
| 6707 ins_pipe(empty); | |
| 6708 %} | |
| 6709 | |
| 6710 instruct membar_release() %{ | |
| 6711 match(MemBarRelease); | |
| 6712 ins_cost(4*MEMORY_REF_COST); | |
| 6713 | |
| 6714 size(0); | |
| 6715 format %{ "MEMBAR-release" %} | |
| 6716 ins_encode( enc_membar_release ); | |
| 6717 ins_pipe(long_memory_op); | |
| 6718 %} | |
| 6719 | |
| 6720 instruct membar_release_lock() %{ | |
|
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|
6721 match(MemBarReleaseLock); |
| 0 | 6722 ins_cost(0); |
| 6723 | |
| 6724 size(0); | |
| 6725 format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %} | |
| 6726 ins_encode( ); | |
| 6727 ins_pipe(empty); | |
| 6728 %} | |
| 6729 | |
| 6730 instruct membar_volatile() %{ | |
| 6731 match(MemBarVolatile); | |
| 6732 ins_cost(4*MEMORY_REF_COST); | |
| 6733 | |
| 6734 size(4); | |
| 6735 format %{ "MEMBAR-volatile" %} | |
| 6736 ins_encode( enc_membar_volatile ); | |
| 6737 ins_pipe(long_memory_op); | |
| 6738 %} | |
| 6739 | |
| 6740 instruct unnecessary_membar_volatile() %{ | |
| 6741 match(MemBarVolatile); | |
| 6742 predicate(Matcher::post_store_load_barrier(n)); | |
| 6743 ins_cost(0); | |
| 6744 | |
| 6745 size(0); | |
| 6746 format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %} | |
| 6747 ins_encode( ); | |
| 6748 ins_pipe(empty); | |
| 6749 %} | |
| 6750 | |
| 6751 //----------Register Move Instructions----------------------------------------- | |
| 6752 instruct roundDouble_nop(regD dst) %{ | |
| 6753 match(Set dst (RoundDouble dst)); | |
| 6754 ins_cost(0); | |
| 6755 // SPARC results are already "rounded" (i.e., normal-format IEEE) | |
| 6756 ins_encode( ); | |
| 6757 ins_pipe(empty); | |
| 6758 %} | |
| 6759 | |
| 6760 | |
| 6761 instruct roundFloat_nop(regF dst) %{ | |
| 6762 match(Set dst (RoundFloat dst)); | |
| 6763 ins_cost(0); | |
| 6764 // SPARC results are already "rounded" (i.e., normal-format IEEE) | |
| 6765 ins_encode( ); | |
| 6766 ins_pipe(empty); | |
| 6767 %} | |
| 6768 | |
| 6769 | |
| 6770 // Cast Index to Pointer for unsafe natives | |
| 6771 instruct castX2P(iRegX src, iRegP dst) %{ | |
| 6772 match(Set dst (CastX2P src)); | |
| 6773 | |
| 6774 format %{ "MOV $src,$dst\t! IntX->Ptr" %} | |
| 6775 ins_encode( form3_g0_rs2_rd_move( src, dst ) ); | |
| 6776 ins_pipe(ialu_reg); | |
| 6777 %} | |
| 6778 | |
| 6779 // Cast Pointer to Index for unsafe natives | |
| 6780 instruct castP2X(iRegP src, iRegX dst) %{ | |
| 6781 match(Set dst (CastP2X src)); | |
| 6782 | |
| 6783 format %{ "MOV $src,$dst\t! Ptr->IntX" %} | |
| 6784 ins_encode( form3_g0_rs2_rd_move( src, dst ) ); | |
| 6785 ins_pipe(ialu_reg); | |
| 6786 %} | |
| 6787 | |
| 6788 instruct stfSSD(stackSlotD stkSlot, regD src) %{ | |
| 6789 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! | |
| 6790 match(Set stkSlot src); // chain rule | |
| 6791 ins_cost(MEMORY_REF_COST); | |
| 6792 format %{ "STDF $src,$stkSlot\t!stk" %} | |
| 6793 opcode(Assembler::stdf_op3); | |
|
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|
6794 ins_encode(simple_form3_mem_reg(stkSlot, src)); |
| 0 | 6795 ins_pipe(fstoreD_stk_reg); |
| 6796 %} | |
| 6797 | |
| 6798 instruct ldfSSD(regD dst, stackSlotD stkSlot) %{ | |
| 6799 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! | |
| 6800 match(Set dst stkSlot); // chain rule | |
| 6801 ins_cost(MEMORY_REF_COST); | |
| 6802 format %{ "LDDF $stkSlot,$dst\t!stk" %} | |
| 6803 opcode(Assembler::lddf_op3); | |
|
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|
6804 ins_encode(simple_form3_mem_reg(stkSlot, dst)); |
| 0 | 6805 ins_pipe(floadD_stk); |
| 6806 %} | |
| 6807 | |
| 6808 instruct stfSSF(stackSlotF stkSlot, regF src) %{ | |
| 6809 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! | |
| 6810 match(Set stkSlot src); // chain rule | |
| 6811 ins_cost(MEMORY_REF_COST); | |
| 6812 format %{ "STF $src,$stkSlot\t!stk" %} | |
| 6813 opcode(Assembler::stf_op3); | |
|
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|
6814 ins_encode(simple_form3_mem_reg(stkSlot, src)); |
| 0 | 6815 ins_pipe(fstoreF_stk_reg); |
| 6816 %} | |
| 6817 | |
| 6818 //----------Conditional Move--------------------------------------------------- | |
| 6819 // Conditional move | |
| 6820 instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{ | |
| 6821 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src))); | |
| 6822 ins_cost(150); | |
| 6823 format %{ "MOV$cmp $pcc,$src,$dst" %} | |
| 6824 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
| 6825 ins_pipe(ialu_reg); | |
| 6826 %} | |
| 6827 | |
| 6828 instruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{ | |
| 6829 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src))); | |
| 6830 ins_cost(140); | |
| 6831 format %{ "MOV$cmp $pcc,$src,$dst" %} | |
| 6832 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); | |
| 6833 ins_pipe(ialu_imm); | |
| 6834 %} | |
| 6835 | |
| 6836 instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{ | |
| 6837 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); | |
| 6838 ins_cost(150); | |
| 6839 size(4); | |
| 6840 format %{ "MOV$cmp $icc,$src,$dst" %} | |
| 6841 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); | |
| 6842 ins_pipe(ialu_reg); | |
| 6843 %} | |
| 6844 | |
| 6845 instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{ | |
| 6846 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); | |
| 6847 ins_cost(140); | |
| 6848 size(4); | |
| 6849 format %{ "MOV$cmp $icc,$src,$dst" %} | |
| 6850 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); | |
| 6851 ins_pipe(ialu_imm); | |
| 6852 %} | |
| 6853 | |
|
1160
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changeset
|
6854 instruct cmovIIu_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{ |
| 0 | 6855 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); |
| 6856 ins_cost(150); | |
| 6857 size(4); | |
| 6858 format %{ "MOV$cmp $icc,$src,$dst" %} | |
| 6859 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); | |
| 6860 ins_pipe(ialu_reg); | |
| 6861 %} | |
| 6862 | |
|
1160
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changeset
|
6863 instruct cmovIIu_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{ |
| 0 | 6864 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); |
| 6865 ins_cost(140); | |
| 6866 size(4); | |
| 6867 format %{ "MOV$cmp $icc,$src,$dst" %} | |
| 6868 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); | |
| 6869 ins_pipe(ialu_imm); | |
| 6870 %} | |
| 6871 | |
| 6872 instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{ | |
| 6873 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src))); | |
| 6874 ins_cost(150); | |
| 6875 size(4); | |
| 6876 format %{ "MOV$cmp $fcc,$src,$dst" %} | |
| 6877 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); | |
| 6878 ins_pipe(ialu_reg); | |
| 6879 %} | |
| 6880 | |
| 6881 instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{ | |
| 6882 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src))); | |
| 6883 ins_cost(140); | |
| 6884 size(4); | |
| 6885 format %{ "MOV$cmp $fcc,$src,$dst" %} | |
| 6886 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) ); | |
| 6887 ins_pipe(ialu_imm); | |
| 6888 %} | |
| 6889 | |
|
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|
6890 // Conditional move for RegN. Only cmov(reg,reg). |
|
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|
6891 instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{ |
|
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|
6892 match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src))); |
|
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|
6893 ins_cost(150); |
|
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|
6894 format %{ "MOV$cmp $pcc,$src,$dst" %} |
|
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|
6895 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); |
|
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changeset
|
6896 ins_pipe(ialu_reg); |
|
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|
6897 %} |
|
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|
6898 |
|
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changeset
|
6899 // This instruction also works with CmpN so we don't need cmovNN_reg. |
|
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|
6900 instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{ |
|
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163
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changeset
|
6901 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src))); |
|
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|
6902 ins_cost(150); |
|
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parents:
163
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changeset
|
6903 size(4); |
|
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parents:
163
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changeset
|
6904 format %{ "MOV$cmp $icc,$src,$dst" %} |
|
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163
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changeset
|
6905 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); |
|
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changeset
|
6906 ins_pipe(ialu_reg); |
|
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163
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|
6907 %} |
|
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163
diff
changeset
|
6908 |
|
1160
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changeset
|
6909 // This instruction also works with CmpN so we don't need cmovNN_reg. |
|
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changeset
|
6910 instruct cmovNIu_reg(cmpOpU cmp, flagsRegU icc, iRegN dst, iRegN src) %{ |
|
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changeset
|
6911 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src))); |
|
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diff
changeset
|
6912 ins_cost(150); |
|
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6909839: missing unsigned compare cases for some cmoves in sparc.ad
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diff
changeset
|
6913 size(4); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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diff
changeset
|
6914 format %{ "MOV$cmp $icc,$src,$dst" %} |
|
f24201449cac
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changeset
|
6915 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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diff
changeset
|
6916 ins_pipe(ialu_reg); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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changeset
|
6917 %} |
|
f24201449cac
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diff
changeset
|
6918 |
|
164
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changeset
|
6919 instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{ |
|
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163
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changeset
|
6920 match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src))); |
|
c436414a719e
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163
diff
changeset
|
6921 ins_cost(150); |
|
c436414a719e
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163
diff
changeset
|
6922 size(4); |
|
c436414a719e
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163
diff
changeset
|
6923 format %{ "MOV$cmp $fcc,$src,$dst" %} |
|
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163
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changeset
|
6924 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); |
|
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163
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changeset
|
6925 ins_pipe(ialu_reg); |
|
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163
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changeset
|
6926 %} |
|
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changeset
|
6927 |
| 0 | 6928 // Conditional move |
| 6929 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{ | |
| 6930 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src))); | |
| 6931 ins_cost(150); | |
| 6932 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %} | |
| 6933 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
| 6934 ins_pipe(ialu_reg); | |
| 6935 %} | |
| 6936 | |
| 6937 instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{ | |
| 6938 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src))); | |
| 6939 ins_cost(140); | |
| 6940 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %} | |
| 6941 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); | |
| 6942 ins_pipe(ialu_imm); | |
| 6943 %} | |
| 6944 | |
|
164
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163
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changeset
|
6945 // This instruction also works with CmpN so we don't need cmovPN_reg. |
| 0 | 6946 instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{ |
| 6947 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); | |
| 6948 ins_cost(150); | |
| 6949 | |
| 6950 size(4); | |
| 6951 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} | |
| 6952 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); | |
| 6953 ins_pipe(ialu_reg); | |
| 6954 %} | |
| 6955 | |
|
1160
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diff
changeset
|
6956 instruct cmovPIu_reg(cmpOpU cmp, flagsRegU icc, iRegP dst, iRegP src) %{ |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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diff
changeset
|
6957 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6958 ins_cost(150); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6959 |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6960 size(4); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6961 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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parents:
1137
diff
changeset
|
6962 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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1137
diff
changeset
|
6963 ins_pipe(ialu_reg); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
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1137
diff
changeset
|
6964 %} |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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1137
diff
changeset
|
6965 |
| 0 | 6966 instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{ |
| 6967 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); | |
| 6968 ins_cost(140); | |
| 6969 | |
| 6970 size(4); | |
| 6971 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} | |
| 6972 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); | |
| 6973 ins_pipe(ialu_imm); | |
| 6974 %} | |
| 6975 | |
|
1160
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6909839: missing unsigned compare cases for some cmoves in sparc.ad
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changeset
|
6976 instruct cmovPIu_imm(cmpOpU cmp, flagsRegU icc, iRegP dst, immP0 src) %{ |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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changeset
|
6977 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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parents:
1137
diff
changeset
|
6978 ins_cost(140); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6979 |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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1137
diff
changeset
|
6980 size(4); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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1137
diff
changeset
|
6981 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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1137
diff
changeset
|
6982 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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1137
diff
changeset
|
6983 ins_pipe(ialu_imm); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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diff
changeset
|
6984 %} |
|
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diff
changeset
|
6985 |
| 0 | 6986 instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{ |
| 6987 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src))); | |
| 6988 ins_cost(150); | |
| 6989 size(4); | |
| 6990 format %{ "MOV$cmp $fcc,$src,$dst" %} | |
| 6991 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); | |
| 6992 ins_pipe(ialu_imm); | |
| 6993 %} | |
| 6994 | |
| 6995 instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{ | |
| 6996 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src))); | |
| 6997 ins_cost(140); | |
| 6998 size(4); | |
| 6999 format %{ "MOV$cmp $fcc,$src,$dst" %} | |
| 7000 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) ); | |
| 7001 ins_pipe(ialu_imm); | |
| 7002 %} | |
| 7003 | |
| 7004 // Conditional move | |
| 7005 instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{ | |
| 7006 match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src))); | |
| 7007 ins_cost(150); | |
| 7008 opcode(0x101); | |
| 7009 format %{ "FMOVD$cmp $pcc,$src,$dst" %} | |
| 7010 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
| 7011 ins_pipe(int_conditional_float_move); | |
| 7012 %} | |
| 7013 | |
| 7014 instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{ | |
| 7015 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src))); | |
| 7016 ins_cost(150); | |
| 7017 | |
| 7018 size(4); | |
| 7019 format %{ "FMOVS$cmp $icc,$src,$dst" %} | |
| 7020 opcode(0x101); | |
| 7021 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); | |
| 7022 ins_pipe(int_conditional_float_move); | |
| 7023 %} | |
| 7024 | |
|
1160
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changeset
|
7025 instruct cmovFIu_reg(cmpOpU cmp, flagsRegU icc, regF dst, regF src) %{ |
|
f24201449cac
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changeset
|
7026 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src))); |
|
f24201449cac
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1137
diff
changeset
|
7027 ins_cost(150); |
|
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changeset
|
7028 |
|
f24201449cac
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diff
changeset
|
7029 size(4); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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1137
diff
changeset
|
7030 format %{ "FMOVS$cmp $icc,$src,$dst" %} |
|
f24201449cac
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diff
changeset
|
7031 opcode(0x101); |
|
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1137
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changeset
|
7032 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); |
|
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changeset
|
7033 ins_pipe(int_conditional_float_move); |
|
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diff
changeset
|
7034 %} |
|
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diff
changeset
|
7035 |
| 0 | 7036 // Conditional move, |
| 7037 instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{ | |
| 7038 match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src))); | |
| 7039 ins_cost(150); | |
| 7040 size(4); | |
| 7041 format %{ "FMOVF$cmp $fcc,$src,$dst" %} | |
| 7042 opcode(0x1); | |
| 7043 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) ); | |
| 7044 ins_pipe(int_conditional_double_move); | |
| 7045 %} | |
| 7046 | |
| 7047 // Conditional move | |
| 7048 instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{ | |
| 7049 match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src))); | |
| 7050 ins_cost(150); | |
| 7051 size(4); | |
| 7052 opcode(0x102); | |
| 7053 format %{ "FMOVD$cmp $pcc,$src,$dst" %} | |
| 7054 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
| 7055 ins_pipe(int_conditional_double_move); | |
| 7056 %} | |
| 7057 | |
| 7058 instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{ | |
| 7059 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src))); | |
| 7060 ins_cost(150); | |
| 7061 | |
| 7062 size(4); | |
| 7063 format %{ "FMOVD$cmp $icc,$src,$dst" %} | |
| 7064 opcode(0x102); | |
| 7065 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); | |
| 7066 ins_pipe(int_conditional_double_move); | |
| 7067 %} | |
| 7068 | |
|
1160
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diff
changeset
|
7069 instruct cmovDIu_reg(cmpOpU cmp, flagsRegU icc, regD dst, regD src) %{ |
|
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|
7070 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src))); |
|
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|
7071 ins_cost(150); |
|
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|
7072 |
|
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changeset
|
7073 size(4); |
|
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|
7074 format %{ "FMOVD$cmp $icc,$src,$dst" %} |
|
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|
7075 opcode(0x102); |
|
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|
7076 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); |
|
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|
7077 ins_pipe(int_conditional_double_move); |
|
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|
7078 %} |
|
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|
7079 |
| 0 | 7080 // Conditional move, |
| 7081 instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{ | |
| 7082 match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src))); | |
| 7083 ins_cost(150); | |
| 7084 size(4); | |
| 7085 format %{ "FMOVD$cmp $fcc,$src,$dst" %} | |
| 7086 opcode(0x2); | |
| 7087 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) ); | |
| 7088 ins_pipe(int_conditional_double_move); | |
| 7089 %} | |
| 7090 | |
| 7091 // Conditional move | |
| 7092 instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{ | |
| 7093 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src))); | |
| 7094 ins_cost(150); | |
| 7095 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %} | |
| 7096 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
| 7097 ins_pipe(ialu_reg); | |
| 7098 %} | |
| 7099 | |
| 7100 instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{ | |
| 7101 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src))); | |
| 7102 ins_cost(140); | |
| 7103 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %} | |
| 7104 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); | |
| 7105 ins_pipe(ialu_imm); | |
| 7106 %} | |
| 7107 | |
| 7108 instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{ | |
| 7109 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src))); | |
| 7110 ins_cost(150); | |
| 7111 | |
| 7112 size(4); | |
| 7113 format %{ "MOV$cmp $icc,$src,$dst\t! long" %} | |
| 7114 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); | |
| 7115 ins_pipe(ialu_reg); | |
| 7116 %} | |
| 7117 | |
| 7118 | |
|
1160
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|
7119 instruct cmovLIu_reg(cmpOpU cmp, flagsRegU icc, iRegL dst, iRegL src) %{ |
|
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|
7120 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src))); |
|
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|
7121 ins_cost(150); |
|
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changeset
|
7122 |
|
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changeset
|
7123 size(4); |
|
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|
7124 format %{ "MOV$cmp $icc,$src,$dst\t! long" %} |
|
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|
7125 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); |
|
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|
7126 ins_pipe(ialu_reg); |
|
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|
7127 %} |
|
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|
7128 |
|
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|
7129 |
| 0 | 7130 instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{ |
| 7131 match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src))); | |
| 7132 ins_cost(150); | |
| 7133 | |
| 7134 size(4); | |
| 7135 format %{ "MOV$cmp $fcc,$src,$dst\t! long" %} | |
| 7136 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); | |
| 7137 ins_pipe(ialu_reg); | |
| 7138 %} | |
| 7139 | |
| 7140 | |
| 7141 | |
| 7142 //----------OS and Locking Instructions---------------------------------------- | |
| 7143 | |
| 7144 // This name is KNOWN by the ADLC and cannot be changed. | |
| 7145 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type | |
| 7146 // for this guy. | |
| 7147 instruct tlsLoadP(g2RegP dst) %{ | |
| 7148 match(Set dst (ThreadLocal)); | |
| 7149 | |
| 7150 size(0); | |
| 7151 ins_cost(0); | |
| 7152 format %{ "# TLS is in G2" %} | |
| 7153 ins_encode( /*empty encoding*/ ); | |
| 7154 ins_pipe(ialu_none); | |
| 7155 %} | |
| 7156 | |
| 7157 instruct checkCastPP( iRegP dst ) %{ | |
| 7158 match(Set dst (CheckCastPP dst)); | |
| 7159 | |
| 7160 size(0); | |
| 7161 format %{ "# checkcastPP of $dst" %} | |
| 7162 ins_encode( /*empty encoding*/ ); | |
| 7163 ins_pipe(empty); | |
| 7164 %} | |
| 7165 | |
| 7166 | |
| 7167 instruct castPP( iRegP dst ) %{ | |
| 7168 match(Set dst (CastPP dst)); | |
| 7169 format %{ "# castPP of $dst" %} | |
| 7170 ins_encode( /*empty encoding*/ ); | |
| 7171 ins_pipe(empty); | |
| 7172 %} | |
| 7173 | |
| 7174 instruct castII( iRegI dst ) %{ | |
| 7175 match(Set dst (CastII dst)); | |
| 7176 format %{ "# castII of $dst" %} | |
| 7177 ins_encode( /*empty encoding*/ ); | |
| 7178 ins_cost(0); | |
| 7179 ins_pipe(empty); | |
| 7180 %} | |
| 7181 | |
| 7182 //----------Arithmetic Instructions-------------------------------------------- | |
| 7183 // Addition Instructions | |
| 7184 // Register Addition | |
| 7185 instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 7186 match(Set dst (AddI src1 src2)); | |
| 7187 | |
| 7188 size(4); | |
| 7189 format %{ "ADD $src1,$src2,$dst" %} | |
| 7190 ins_encode %{ | |
| 7191 __ add($src1$$Register, $src2$$Register, $dst$$Register); | |
| 7192 %} | |
| 7193 ins_pipe(ialu_reg_reg); | |
| 7194 %} | |
| 7195 | |
| 7196 // Immediate Addition | |
| 7197 instruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
| 7198 match(Set dst (AddI src1 src2)); | |
| 7199 | |
| 7200 size(4); | |
| 7201 format %{ "ADD $src1,$src2,$dst" %} | |
| 7202 opcode(Assembler::add_op3, Assembler::arith_op); | |
| 7203 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7204 ins_pipe(ialu_reg_imm); | |
| 7205 %} | |
| 7206 | |
| 7207 // Pointer Register Addition | |
| 7208 instruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{ | |
| 7209 match(Set dst (AddP src1 src2)); | |
| 7210 | |
| 7211 size(4); | |
| 7212 format %{ "ADD $src1,$src2,$dst" %} | |
| 7213 opcode(Assembler::add_op3, Assembler::arith_op); | |
| 7214 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7215 ins_pipe(ialu_reg_reg); | |
| 7216 %} | |
| 7217 | |
| 7218 // Pointer Immediate Addition | |
| 7219 instruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{ | |
| 7220 match(Set dst (AddP src1 src2)); | |
| 7221 | |
| 7222 size(4); | |
| 7223 format %{ "ADD $src1,$src2,$dst" %} | |
| 7224 opcode(Assembler::add_op3, Assembler::arith_op); | |
| 7225 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7226 ins_pipe(ialu_reg_imm); | |
| 7227 %} | |
| 7228 | |
| 7229 // Long Addition | |
| 7230 instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7231 match(Set dst (AddL src1 src2)); | |
| 7232 | |
| 7233 size(4); | |
| 7234 format %{ "ADD $src1,$src2,$dst\t! long" %} | |
| 7235 opcode(Assembler::add_op3, Assembler::arith_op); | |
| 7236 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7237 ins_pipe(ialu_reg_reg); | |
| 7238 %} | |
| 7239 | |
| 7240 instruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
| 7241 match(Set dst (AddL src1 con)); | |
| 7242 | |
| 7243 size(4); | |
| 7244 format %{ "ADD $src1,$con,$dst" %} | |
| 7245 opcode(Assembler::add_op3, Assembler::arith_op); | |
| 7246 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
| 7247 ins_pipe(ialu_reg_imm); | |
| 7248 %} | |
| 7249 | |
| 7250 //----------Conditional_store-------------------------------------------------- | |
| 7251 // Conditional-store of the updated heap-top. | |
| 7252 // Used during allocation of the shared heap. | |
| 7253 // Sets flags (EQ) on success. Implemented with a CASA on Sparc. | |
| 7254 | |
| 7255 // LoadP-locked. Same as a regular pointer load when used with a compare-swap | |
| 7256 instruct loadPLocked(iRegP dst, memory mem) %{ | |
| 7257 match(Set dst (LoadPLocked mem)); | |
| 7258 ins_cost(MEMORY_REF_COST); | |
| 7259 | |
| 7260 #ifndef _LP64 | |
| 7261 size(4); | |
| 7262 format %{ "LDUW $mem,$dst\t! ptr" %} | |
| 7263 opcode(Assembler::lduw_op3, 0, REGP_OP); | |
| 7264 #else | |
| 7265 format %{ "LDX $mem,$dst\t! ptr" %} | |
| 7266 opcode(Assembler::ldx_op3, 0, REGP_OP); | |
| 7267 #endif | |
| 7268 ins_encode( form3_mem_reg( mem, dst ) ); | |
| 7269 ins_pipe(iload_mem); | |
| 7270 %} | |
| 7271 | |
| 7272 // LoadL-locked. Same as a regular long load when used with a compare-swap | |
| 7273 instruct loadLLocked(iRegL dst, memory mem) %{ | |
| 7274 match(Set dst (LoadLLocked mem)); | |
| 7275 ins_cost(MEMORY_REF_COST); | |
| 7276 size(4); | |
| 7277 format %{ "LDX $mem,$dst\t! long" %} | |
| 7278 opcode(Assembler::ldx_op3); | |
|
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7279 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
| 0 | 7280 ins_pipe(iload_mem); |
| 7281 %} | |
| 7282 | |
| 7283 instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{ | |
| 7284 match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval))); | |
| 7285 effect( KILL newval ); | |
| 7286 format %{ "CASA [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t" | |
| 7287 "CMP R_G3,$oldval\t\t! See if we made progress" %} | |
| 7288 ins_encode( enc_cas(heap_top_ptr,oldval,newval) ); | |
| 7289 ins_pipe( long_memory_op ); | |
| 7290 %} | |
| 7291 | |
|
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|
7292 // Conditional-store of an int value. |
|
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|
7293 instruct storeIConditional( iRegP mem_ptr, iRegI oldval, g3RegI newval, flagsReg icc ) %{ |
|
a1980da045cc
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|
7294 match(Set icc (StoreIConditional mem_ptr (Binary oldval newval))); |
|
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|
7295 effect( KILL newval ); |
|
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|
7296 format %{ "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t" |
|
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|
7297 "CMP $oldval,$newval\t\t! See if we made progress" %} |
|
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|
7298 ins_encode( enc_cas(mem_ptr,oldval,newval) ); |
| 0 | 7299 ins_pipe( long_memory_op ); |
| 7300 %} | |
| 7301 | |
|
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|
7302 // Conditional-store of a long value. |
|
a1980da045cc
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|
7303 instruct storeLConditional( iRegP mem_ptr, iRegL oldval, g3RegL newval, flagsRegL xcc ) %{ |
|
a1980da045cc
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|
7304 match(Set xcc (StoreLConditional mem_ptr (Binary oldval newval))); |
|
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|
7305 effect( KILL newval ); |
|
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|
7306 format %{ "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t" |
|
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|
7307 "CMP $oldval,$newval\t\t! See if we made progress" %} |
|
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|
7308 ins_encode( enc_cas(mem_ptr,oldval,newval) ); |
| 0 | 7309 ins_pipe( long_memory_op ); |
| 7310 %} | |
| 7311 | |
| 7312 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them | |
| 7313 | |
| 7314 instruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ | |
| 7315 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval))); | |
| 7316 effect( USE mem_ptr, KILL ccr, KILL tmp1); | |
| 7317 format %{ | |
| 7318 "MOV $newval,O7\n\t" | |
| 7319 "CASXA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" | |
| 7320 "CMP $oldval,O7\t\t! See if we made progress\n\t" | |
| 7321 "MOV 1,$res\n\t" | |
| 7322 "MOVne xcc,R_G0,$res" | |
| 7323 %} | |
| 7324 ins_encode( enc_casx(mem_ptr, oldval, newval), | |
| 7325 enc_lflags_ne_to_boolean(res) ); | |
| 7326 ins_pipe( long_memory_op ); | |
| 7327 %} | |
| 7328 | |
| 7329 | |
| 7330 instruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ | |
| 7331 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval))); | |
| 7332 effect( USE mem_ptr, KILL ccr, KILL tmp1); | |
| 7333 format %{ | |
| 7334 "MOV $newval,O7\n\t" | |
| 7335 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" | |
| 7336 "CMP $oldval,O7\t\t! See if we made progress\n\t" | |
| 7337 "MOV 1,$res\n\t" | |
| 7338 "MOVne icc,R_G0,$res" | |
| 7339 %} | |
| 7340 ins_encode( enc_casi(mem_ptr, oldval, newval), | |
| 7341 enc_iflags_ne_to_boolean(res) ); | |
| 7342 ins_pipe( long_memory_op ); | |
| 7343 %} | |
| 7344 | |
| 7345 instruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ | |
| 7346 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval))); | |
| 7347 effect( USE mem_ptr, KILL ccr, KILL tmp1); | |
| 7348 format %{ | |
| 7349 "MOV $newval,O7\n\t" | |
|
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7350 "CASA_PTR [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" |
| 0 | 7351 "CMP $oldval,O7\t\t! See if we made progress\n\t" |
| 7352 "MOV 1,$res\n\t" | |
| 7353 "MOVne xcc,R_G0,$res" | |
| 7354 %} | |
|
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|
7355 #ifdef _LP64 |
| 0 | 7356 ins_encode( enc_casx(mem_ptr, oldval, newval), |
| 7357 enc_lflags_ne_to_boolean(res) ); | |
| 7358 #else | |
|
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7359 ins_encode( enc_casi(mem_ptr, oldval, newval), |
|
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|
7360 enc_iflags_ne_to_boolean(res) ); |
|
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|
7361 #endif |
|
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|
7362 ins_pipe( long_memory_op ); |
|
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|
7363 %} |
|
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|
7364 |
|
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7365 instruct compareAndSwapN_bool(iRegP mem_ptr, iRegN oldval, iRegN newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ |
|
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7366 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval))); |
|
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|
7367 effect( USE mem_ptr, KILL ccr, KILL tmp1); |
| 0 | 7368 format %{ |
| 7369 "MOV $newval,O7\n\t" | |
| 7370 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" | |
| 7371 "CMP $oldval,O7\t\t! See if we made progress\n\t" | |
| 7372 "MOV 1,$res\n\t" | |
| 7373 "MOVne icc,R_G0,$res" | |
| 7374 %} | |
|
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changeset
|
7375 ins_encode( enc_casi(mem_ptr, oldval, newval), |
|
823298b11afc
6709165: Tests hang or misbahve with HS 13.0-b01 on solaris-sparcv9
never
parents:
165
diff
changeset
|
7376 enc_iflags_ne_to_boolean(res) ); |
| 0 | 7377 ins_pipe( long_memory_op ); |
| 7378 %} | |
| 7379 | |
| 7380 //--------------------- | |
| 7381 // Subtraction Instructions | |
| 7382 // Register Subtraction | |
| 7383 instruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 7384 match(Set dst (SubI src1 src2)); | |
| 7385 | |
| 7386 size(4); | |
| 7387 format %{ "SUB $src1,$src2,$dst" %} | |
| 7388 opcode(Assembler::sub_op3, Assembler::arith_op); | |
| 7389 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7390 ins_pipe(ialu_reg_reg); | |
| 7391 %} | |
| 7392 | |
| 7393 // Immediate Subtraction | |
| 7394 instruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
| 7395 match(Set dst (SubI src1 src2)); | |
| 7396 | |
| 7397 size(4); | |
| 7398 format %{ "SUB $src1,$src2,$dst" %} | |
| 7399 opcode(Assembler::sub_op3, Assembler::arith_op); | |
| 7400 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7401 ins_pipe(ialu_reg_imm); | |
| 7402 %} | |
| 7403 | |
| 7404 instruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{ | |
| 7405 match(Set dst (SubI zero src2)); | |
| 7406 | |
| 7407 size(4); | |
| 7408 format %{ "NEG $src2,$dst" %} | |
| 7409 opcode(Assembler::sub_op3, Assembler::arith_op); | |
| 7410 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) ); | |
| 7411 ins_pipe(ialu_zero_reg); | |
| 7412 %} | |
| 7413 | |
| 7414 // Long subtraction | |
| 7415 instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7416 match(Set dst (SubL src1 src2)); | |
| 7417 | |
| 7418 size(4); | |
| 7419 format %{ "SUB $src1,$src2,$dst\t! long" %} | |
| 7420 opcode(Assembler::sub_op3, Assembler::arith_op); | |
| 7421 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7422 ins_pipe(ialu_reg_reg); | |
| 7423 %} | |
| 7424 | |
| 7425 // Immediate Subtraction | |
| 7426 instruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
| 7427 match(Set dst (SubL src1 con)); | |
| 7428 | |
| 7429 size(4); | |
| 7430 format %{ "SUB $src1,$con,$dst\t! long" %} | |
| 7431 opcode(Assembler::sub_op3, Assembler::arith_op); | |
| 7432 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
| 7433 ins_pipe(ialu_reg_imm); | |
| 7434 %} | |
| 7435 | |
| 7436 // Long negation | |
| 7437 instruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{ | |
| 7438 match(Set dst (SubL zero src2)); | |
| 7439 | |
| 7440 size(4); | |
| 7441 format %{ "NEG $src2,$dst\t! long" %} | |
| 7442 opcode(Assembler::sub_op3, Assembler::arith_op); | |
| 7443 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) ); | |
| 7444 ins_pipe(ialu_zero_reg); | |
| 7445 %} | |
| 7446 | |
| 7447 // Multiplication Instructions | |
| 7448 // Integer Multiplication | |
| 7449 // Register Multiplication | |
| 7450 instruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 7451 match(Set dst (MulI src1 src2)); | |
| 7452 | |
| 7453 size(4); | |
| 7454 format %{ "MULX $src1,$src2,$dst" %} | |
| 7455 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
| 7456 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7457 ins_pipe(imul_reg_reg); | |
| 7458 %} | |
| 7459 | |
| 7460 // Immediate Multiplication | |
| 7461 instruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
| 7462 match(Set dst (MulI src1 src2)); | |
| 7463 | |
| 7464 size(4); | |
| 7465 format %{ "MULX $src1,$src2,$dst" %} | |
| 7466 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
| 7467 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7468 ins_pipe(imul_reg_imm); | |
| 7469 %} | |
| 7470 | |
| 7471 instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7472 match(Set dst (MulL src1 src2)); | |
| 7473 ins_cost(DEFAULT_COST * 5); | |
| 7474 size(4); | |
| 7475 format %{ "MULX $src1,$src2,$dst\t! long" %} | |
| 7476 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
| 7477 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7478 ins_pipe(mulL_reg_reg); | |
| 7479 %} | |
| 7480 | |
| 7481 // Immediate Multiplication | |
| 7482 instruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ | |
| 7483 match(Set dst (MulL src1 src2)); | |
| 7484 ins_cost(DEFAULT_COST * 5); | |
| 7485 size(4); | |
| 7486 format %{ "MULX $src1,$src2,$dst" %} | |
| 7487 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
| 7488 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7489 ins_pipe(mulL_reg_imm); | |
| 7490 %} | |
| 7491 | |
| 7492 // Integer Division | |
| 7493 // Register Division | |
| 7494 instruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{ | |
| 7495 match(Set dst (DivI src1 src2)); | |
| 7496 ins_cost((2+71)*DEFAULT_COST); | |
| 7497 | |
| 7498 format %{ "SRA $src2,0,$src2\n\t" | |
| 7499 "SRA $src1,0,$src1\n\t" | |
| 7500 "SDIVX $src1,$src2,$dst" %} | |
| 7501 ins_encode( idiv_reg( src1, src2, dst ) ); | |
| 7502 ins_pipe(sdiv_reg_reg); | |
| 7503 %} | |
| 7504 | |
| 7505 // Immediate Division | |
| 7506 instruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{ | |
| 7507 match(Set dst (DivI src1 src2)); | |
| 7508 ins_cost((2+71)*DEFAULT_COST); | |
| 7509 | |
| 7510 format %{ "SRA $src1,0,$src1\n\t" | |
| 7511 "SDIVX $src1,$src2,$dst" %} | |
| 7512 ins_encode( idiv_imm( src1, src2, dst ) ); | |
| 7513 ins_pipe(sdiv_reg_imm); | |
| 7514 %} | |
| 7515 | |
| 7516 //----------Div-By-10-Expansion------------------------------------------------ | |
| 7517 // Extract hi bits of a 32x32->64 bit multiply. | |
| 7518 // Expand rule only, not matched | |
| 7519 instruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{ | |
| 7520 effect( DEF dst, USE src1, USE src2 ); | |
| 7521 format %{ "MULX $src1,$src2,$dst\t! Used in div-by-10\n\t" | |
| 7522 "SRLX $dst,#32,$dst\t\t! Extract only hi word of result" %} | |
| 7523 ins_encode( enc_mul_hi(dst,src1,src2)); | |
| 7524 ins_pipe(sdiv_reg_reg); | |
| 7525 %} | |
| 7526 | |
| 605 | 7527 // Magic constant, reciprocal of 10 |
| 0 | 7528 instruct loadConI_x66666667(iRegIsafe dst) %{ |
| 7529 effect( DEF dst ); | |
| 7530 | |
| 7531 size(8); | |
| 7532 format %{ "SET 0x66666667,$dst\t! Used in div-by-10" %} | |
| 7533 ins_encode( Set32(0x66666667, dst) ); | |
| 7534 ins_pipe(ialu_hi_lo_reg); | |
| 7535 %} | |
| 7536 | |
| 605 | 7537 // Register Shift Right Arithmetic Long by 32-63 |
| 0 | 7538 instruct sra_31( iRegI dst, iRegI src ) %{ |
| 7539 effect( DEF dst, USE src ); | |
| 7540 format %{ "SRA $src,31,$dst\t! Used in div-by-10" %} | |
| 7541 ins_encode( form3_rs1_rd_copysign_hi(src,dst) ); | |
| 7542 ins_pipe(ialu_reg_reg); | |
| 7543 %} | |
| 7544 | |
| 7545 // Arithmetic Shift Right by 8-bit immediate | |
| 7546 instruct sra_reg_2( iRegI dst, iRegI src ) %{ | |
| 7547 effect( DEF dst, USE src ); | |
| 7548 format %{ "SRA $src,2,$dst\t! Used in div-by-10" %} | |
| 7549 opcode(Assembler::sra_op3, Assembler::arith_op); | |
| 7550 ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) ); | |
| 7551 ins_pipe(ialu_reg_imm); | |
| 7552 %} | |
| 7553 | |
| 7554 // Integer DIV with 10 | |
| 7555 instruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{ | |
| 7556 match(Set dst (DivI src div)); | |
| 7557 ins_cost((6+6)*DEFAULT_COST); | |
| 7558 expand %{ | |
| 7559 iRegIsafe tmp1; // Killed temps; | |
| 7560 iRegIsafe tmp2; // Killed temps; | |
| 7561 iRegI tmp3; // Killed temps; | |
| 7562 iRegI tmp4; // Killed temps; | |
| 7563 loadConI_x66666667( tmp1 ); // SET 0x66666667 -> tmp1 | |
| 7564 mul_hi( tmp2, src, tmp1 ); // MUL hibits(src * tmp1) -> tmp2 | |
| 7565 sra_31( tmp3, src ); // SRA src,31 -> tmp3 | |
| 7566 sra_reg_2( tmp4, tmp2 ); // SRA tmp2,2 -> tmp4 | |
| 7567 subI_reg_reg( dst,tmp4,tmp3); // SUB tmp4 - tmp3 -> dst | |
| 7568 %} | |
| 7569 %} | |
| 7570 | |
| 7571 // Register Long Division | |
| 7572 instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7573 match(Set dst (DivL src1 src2)); | |
| 7574 ins_cost(DEFAULT_COST*71); | |
| 7575 size(4); | |
| 7576 format %{ "SDIVX $src1,$src2,$dst\t! long" %} | |
| 7577 opcode(Assembler::sdivx_op3, Assembler::arith_op); | |
| 7578 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7579 ins_pipe(divL_reg_reg); | |
| 7580 %} | |
| 7581 | |
| 7582 // Register Long Division | |
| 7583 instruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ | |
| 7584 match(Set dst (DivL src1 src2)); | |
| 7585 ins_cost(DEFAULT_COST*71); | |
| 7586 size(4); | |
| 7587 format %{ "SDIVX $src1,$src2,$dst\t! long" %} | |
| 7588 opcode(Assembler::sdivx_op3, Assembler::arith_op); | |
| 7589 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7590 ins_pipe(divL_reg_imm); | |
| 7591 %} | |
| 7592 | |
| 7593 // Integer Remainder | |
| 7594 // Register Remainder | |
| 7595 instruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{ | |
| 7596 match(Set dst (ModI src1 src2)); | |
| 7597 effect( KILL ccr, KILL temp); | |
| 7598 | |
| 7599 format %{ "SREM $src1,$src2,$dst" %} | |
| 7600 ins_encode( irem_reg(src1, src2, dst, temp) ); | |
| 7601 ins_pipe(sdiv_reg_reg); | |
| 7602 %} | |
| 7603 | |
| 7604 // Immediate Remainder | |
| 7605 instruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{ | |
| 7606 match(Set dst (ModI src1 src2)); | |
| 7607 effect( KILL ccr, KILL temp); | |
| 7608 | |
| 7609 format %{ "SREM $src1,$src2,$dst" %} | |
| 7610 ins_encode( irem_imm(src1, src2, dst, temp) ); | |
| 7611 ins_pipe(sdiv_reg_imm); | |
| 7612 %} | |
| 7613 | |
| 7614 // Register Long Remainder | |
| 7615 instruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7616 effect(DEF dst, USE src1, USE src2); | |
| 7617 size(4); | |
| 7618 format %{ "SDIVX $src1,$src2,$dst\t! long" %} | |
| 7619 opcode(Assembler::sdivx_op3, Assembler::arith_op); | |
| 7620 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7621 ins_pipe(divL_reg_reg); | |
| 7622 %} | |
| 7623 | |
| 7624 // Register Long Division | |
| 7625 instruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{ | |
| 7626 effect(DEF dst, USE src1, USE src2); | |
| 7627 size(4); | |
| 7628 format %{ "SDIVX $src1,$src2,$dst\t! long" %} | |
| 7629 opcode(Assembler::sdivx_op3, Assembler::arith_op); | |
| 7630 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7631 ins_pipe(divL_reg_imm); | |
| 7632 %} | |
| 7633 | |
| 7634 instruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7635 effect(DEF dst, USE src1, USE src2); | |
| 7636 size(4); | |
| 7637 format %{ "MULX $src1,$src2,$dst\t! long" %} | |
| 7638 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
| 7639 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7640 ins_pipe(mulL_reg_reg); | |
| 7641 %} | |
| 7642 | |
| 7643 // Immediate Multiplication | |
| 7644 instruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{ | |
| 7645 effect(DEF dst, USE src1, USE src2); | |
| 7646 size(4); | |
| 7647 format %{ "MULX $src1,$src2,$dst" %} | |
| 7648 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
| 7649 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7650 ins_pipe(mulL_reg_imm); | |
| 7651 %} | |
| 7652 | |
| 7653 instruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7654 effect(DEF dst, USE src1, USE src2); | |
| 7655 size(4); | |
| 7656 format %{ "SUB $src1,$src2,$dst\t! long" %} | |
| 7657 opcode(Assembler::sub_op3, Assembler::arith_op); | |
| 7658 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7659 ins_pipe(ialu_reg_reg); | |
| 7660 %} | |
| 7661 | |
| 7662 instruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7663 effect(DEF dst, USE src1, USE src2); | |
| 7664 size(4); | |
| 7665 format %{ "SUB $src1,$src2,$dst\t! long" %} | |
| 7666 opcode(Assembler::sub_op3, Assembler::arith_op); | |
| 7667 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7668 ins_pipe(ialu_reg_reg); | |
| 7669 %} | |
| 7670 | |
| 7671 // Register Long Remainder | |
| 7672 instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7673 match(Set dst (ModL src1 src2)); | |
| 7674 ins_cost(DEFAULT_COST*(71 + 6 + 1)); | |
| 7675 expand %{ | |
| 7676 iRegL tmp1; | |
| 7677 iRegL tmp2; | |
| 7678 divL_reg_reg_1(tmp1, src1, src2); | |
| 7679 mulL_reg_reg_1(tmp2, tmp1, src2); | |
| 7680 subL_reg_reg_1(dst, src1, tmp2); | |
| 7681 %} | |
| 7682 %} | |
| 7683 | |
| 7684 // Register Long Remainder | |
| 7685 instruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ | |
| 7686 match(Set dst (ModL src1 src2)); | |
| 7687 ins_cost(DEFAULT_COST*(71 + 6 + 1)); | |
| 7688 expand %{ | |
| 7689 iRegL tmp1; | |
| 7690 iRegL tmp2; | |
| 7691 divL_reg_imm13_1(tmp1, src1, src2); | |
| 7692 mulL_reg_imm13_1(tmp2, tmp1, src2); | |
| 7693 subL_reg_reg_2 (dst, src1, tmp2); | |
| 7694 %} | |
| 7695 %} | |
| 7696 | |
| 7697 // Integer Shift Instructions | |
| 7698 // Register Shift Left | |
| 7699 instruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 7700 match(Set dst (LShiftI src1 src2)); | |
| 7701 | |
| 7702 size(4); | |
| 7703 format %{ "SLL $src1,$src2,$dst" %} | |
| 7704 opcode(Assembler::sll_op3, Assembler::arith_op); | |
| 7705 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7706 ins_pipe(ialu_reg_reg); | |
| 7707 %} | |
| 7708 | |
| 7709 // Register Shift Left Immediate | |
| 7710 instruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ | |
| 7711 match(Set dst (LShiftI src1 src2)); | |
| 7712 | |
| 7713 size(4); | |
| 7714 format %{ "SLL $src1,$src2,$dst" %} | |
| 7715 opcode(Assembler::sll_op3, Assembler::arith_op); | |
| 7716 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); | |
| 7717 ins_pipe(ialu_reg_imm); | |
| 7718 %} | |
| 7719 | |
| 7720 // Register Shift Left | |
| 7721 instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ | |
| 7722 match(Set dst (LShiftL src1 src2)); | |
| 7723 | |
| 7724 size(4); | |
| 7725 format %{ "SLLX $src1,$src2,$dst" %} | |
| 7726 opcode(Assembler::sllx_op3, Assembler::arith_op); | |
| 7727 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7728 ins_pipe(ialu_reg_reg); | |
| 7729 %} | |
| 7730 | |
| 7731 // Register Shift Left Immediate | |
| 7732 instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ | |
| 7733 match(Set dst (LShiftL src1 src2)); | |
| 7734 | |
| 7735 size(4); | |
| 7736 format %{ "SLLX $src1,$src2,$dst" %} | |
| 7737 opcode(Assembler::sllx_op3, Assembler::arith_op); | |
| 7738 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); | |
| 7739 ins_pipe(ialu_reg_imm); | |
| 7740 %} | |
| 7741 | |
| 7742 // Register Arithmetic Shift Right | |
| 7743 instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 7744 match(Set dst (RShiftI src1 src2)); | |
| 7745 size(4); | |
| 7746 format %{ "SRA $src1,$src2,$dst" %} | |
| 7747 opcode(Assembler::sra_op3, Assembler::arith_op); | |
| 7748 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7749 ins_pipe(ialu_reg_reg); | |
| 7750 %} | |
| 7751 | |
| 7752 // Register Arithmetic Shift Right Immediate | |
| 7753 instruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ | |
| 7754 match(Set dst (RShiftI src1 src2)); | |
| 7755 | |
| 7756 size(4); | |
| 7757 format %{ "SRA $src1,$src2,$dst" %} | |
| 7758 opcode(Assembler::sra_op3, Assembler::arith_op); | |
| 7759 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); | |
| 7760 ins_pipe(ialu_reg_imm); | |
| 7761 %} | |
| 7762 | |
| 7763 // Register Shift Right Arithmatic Long | |
| 7764 instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ | |
| 7765 match(Set dst (RShiftL src1 src2)); | |
| 7766 | |
| 7767 size(4); | |
| 7768 format %{ "SRAX $src1,$src2,$dst" %} | |
| 7769 opcode(Assembler::srax_op3, Assembler::arith_op); | |
| 7770 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7771 ins_pipe(ialu_reg_reg); | |
| 7772 %} | |
| 7773 | |
| 7774 // Register Shift Left Immediate | |
| 7775 instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ | |
| 7776 match(Set dst (RShiftL src1 src2)); | |
| 7777 | |
| 7778 size(4); | |
| 7779 format %{ "SRAX $src1,$src2,$dst" %} | |
| 7780 opcode(Assembler::srax_op3, Assembler::arith_op); | |
| 7781 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); | |
| 7782 ins_pipe(ialu_reg_imm); | |
| 7783 %} | |
| 7784 | |
| 7785 // Register Shift Right | |
| 7786 instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 7787 match(Set dst (URShiftI src1 src2)); | |
| 7788 | |
| 7789 size(4); | |
| 7790 format %{ "SRL $src1,$src2,$dst" %} | |
| 7791 opcode(Assembler::srl_op3, Assembler::arith_op); | |
| 7792 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7793 ins_pipe(ialu_reg_reg); | |
| 7794 %} | |
| 7795 | |
| 7796 // Register Shift Right Immediate | |
| 7797 instruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ | |
| 7798 match(Set dst (URShiftI src1 src2)); | |
| 7799 | |
| 7800 size(4); | |
| 7801 format %{ "SRL $src1,$src2,$dst" %} | |
| 7802 opcode(Assembler::srl_op3, Assembler::arith_op); | |
| 7803 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); | |
| 7804 ins_pipe(ialu_reg_imm); | |
| 7805 %} | |
| 7806 | |
| 7807 // Register Shift Right | |
| 7808 instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ | |
| 7809 match(Set dst (URShiftL src1 src2)); | |
| 7810 | |
| 7811 size(4); | |
| 7812 format %{ "SRLX $src1,$src2,$dst" %} | |
| 7813 opcode(Assembler::srlx_op3, Assembler::arith_op); | |
| 7814 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7815 ins_pipe(ialu_reg_reg); | |
| 7816 %} | |
| 7817 | |
| 7818 // Register Shift Right Immediate | |
| 7819 instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ | |
| 7820 match(Set dst (URShiftL src1 src2)); | |
| 7821 | |
| 7822 size(4); | |
| 7823 format %{ "SRLX $src1,$src2,$dst" %} | |
| 7824 opcode(Assembler::srlx_op3, Assembler::arith_op); | |
| 7825 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); | |
| 7826 ins_pipe(ialu_reg_imm); | |
| 7827 %} | |
| 7828 | |
| 7829 // Register Shift Right Immediate with a CastP2X | |
| 7830 #ifdef _LP64 | |
| 7831 instruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{ | |
| 7832 match(Set dst (URShiftL (CastP2X src1) src2)); | |
| 7833 size(4); | |
| 7834 format %{ "SRLX $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %} | |
| 7835 opcode(Assembler::srlx_op3, Assembler::arith_op); | |
| 7836 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); | |
| 7837 ins_pipe(ialu_reg_imm); | |
| 7838 %} | |
| 7839 #else | |
| 7840 instruct shrP_reg_imm5(iRegI dst, iRegP src1, immU5 src2) %{ | |
| 7841 match(Set dst (URShiftI (CastP2X src1) src2)); | |
| 7842 size(4); | |
| 7843 format %{ "SRL $src1,$src2,$dst\t! Cast ptr $src1 to int and shift" %} | |
| 7844 opcode(Assembler::srl_op3, Assembler::arith_op); | |
| 7845 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); | |
| 7846 ins_pipe(ialu_reg_imm); | |
| 7847 %} | |
| 7848 #endif | |
| 7849 | |
| 7850 | |
| 7851 //----------Floating Point Arithmetic Instructions----------------------------- | |
| 7852 | |
| 7853 // Add float single precision | |
| 7854 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{ | |
| 7855 match(Set dst (AddF src1 src2)); | |
| 7856 | |
| 7857 size(4); | |
| 7858 format %{ "FADDS $src1,$src2,$dst" %} | |
| 7859 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf); | |
| 7860 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); | |
| 7861 ins_pipe(faddF_reg_reg); | |
| 7862 %} | |
| 7863 | |
| 7864 // Add float double precision | |
| 7865 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{ | |
| 7866 match(Set dst (AddD src1 src2)); | |
| 7867 | |
| 7868 size(4); | |
| 7869 format %{ "FADDD $src1,$src2,$dst" %} | |
| 7870 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf); | |
| 7871 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
| 7872 ins_pipe(faddD_reg_reg); | |
| 7873 %} | |
| 7874 | |
| 7875 // Sub float single precision | |
| 7876 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{ | |
| 7877 match(Set dst (SubF src1 src2)); | |
| 7878 | |
| 7879 size(4); | |
| 7880 format %{ "FSUBS $src1,$src2,$dst" %} | |
| 7881 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf); | |
| 7882 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); | |
| 7883 ins_pipe(faddF_reg_reg); | |
| 7884 %} | |
| 7885 | |
| 7886 // Sub float double precision | |
| 7887 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{ | |
| 7888 match(Set dst (SubD src1 src2)); | |
| 7889 | |
| 7890 size(4); | |
| 7891 format %{ "FSUBD $src1,$src2,$dst" %} | |
| 7892 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf); | |
| 7893 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
| 7894 ins_pipe(faddD_reg_reg); | |
| 7895 %} | |
| 7896 | |
| 7897 // Mul float single precision | |
| 7898 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{ | |
| 7899 match(Set dst (MulF src1 src2)); | |
| 7900 | |
| 7901 size(4); | |
| 7902 format %{ "FMULS $src1,$src2,$dst" %} | |
| 7903 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf); | |
| 7904 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); | |
| 7905 ins_pipe(fmulF_reg_reg); | |
| 7906 %} | |
| 7907 | |
| 7908 // Mul float double precision | |
| 7909 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{ | |
| 7910 match(Set dst (MulD src1 src2)); | |
| 7911 | |
| 7912 size(4); | |
| 7913 format %{ "FMULD $src1,$src2,$dst" %} | |
| 7914 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf); | |
| 7915 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
| 7916 ins_pipe(fmulD_reg_reg); | |
| 7917 %} | |
| 7918 | |
| 7919 // Div float single precision | |
| 7920 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{ | |
| 7921 match(Set dst (DivF src1 src2)); | |
| 7922 | |
| 7923 size(4); | |
| 7924 format %{ "FDIVS $src1,$src2,$dst" %} | |
| 7925 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf); | |
| 7926 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); | |
| 7927 ins_pipe(fdivF_reg_reg); | |
| 7928 %} | |
| 7929 | |
| 7930 // Div float double precision | |
| 7931 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{ | |
| 7932 match(Set dst (DivD src1 src2)); | |
| 7933 | |
| 7934 size(4); | |
| 7935 format %{ "FDIVD $src1,$src2,$dst" %} | |
| 7936 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf); | |
| 7937 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
| 7938 ins_pipe(fdivD_reg_reg); | |
| 7939 %} | |
| 7940 | |
| 7941 // Absolute float double precision | |
| 7942 instruct absD_reg(regD dst, regD src) %{ | |
| 7943 match(Set dst (AbsD src)); | |
| 7944 | |
| 7945 format %{ "FABSd $src,$dst" %} | |
| 7946 ins_encode(fabsd(dst, src)); | |
| 7947 ins_pipe(faddD_reg); | |
| 7948 %} | |
| 7949 | |
| 7950 // Absolute float single precision | |
| 7951 instruct absF_reg(regF dst, regF src) %{ | |
| 7952 match(Set dst (AbsF src)); | |
| 7953 | |
| 7954 format %{ "FABSs $src,$dst" %} | |
| 7955 ins_encode(fabss(dst, src)); | |
| 7956 ins_pipe(faddF_reg); | |
| 7957 %} | |
| 7958 | |
| 7959 instruct negF_reg(regF dst, regF src) %{ | |
| 7960 match(Set dst (NegF src)); | |
| 7961 | |
| 7962 size(4); | |
| 7963 format %{ "FNEGs $src,$dst" %} | |
| 7964 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf); | |
| 7965 ins_encode(form3_opf_rs2F_rdF(src, dst)); | |
| 7966 ins_pipe(faddF_reg); | |
| 7967 %} | |
| 7968 | |
| 7969 instruct negD_reg(regD dst, regD src) %{ | |
| 7970 match(Set dst (NegD src)); | |
| 7971 | |
| 7972 format %{ "FNEGd $src,$dst" %} | |
| 7973 ins_encode(fnegd(dst, src)); | |
| 7974 ins_pipe(faddD_reg); | |
| 7975 %} | |
| 7976 | |
| 7977 // Sqrt float double precision | |
| 7978 instruct sqrtF_reg_reg(regF dst, regF src) %{ | |
| 7979 match(Set dst (ConvD2F (SqrtD (ConvF2D src)))); | |
| 7980 | |
| 7981 size(4); | |
| 7982 format %{ "FSQRTS $src,$dst" %} | |
| 7983 ins_encode(fsqrts(dst, src)); | |
| 7984 ins_pipe(fdivF_reg_reg); | |
| 7985 %} | |
| 7986 | |
| 7987 // Sqrt float double precision | |
| 7988 instruct sqrtD_reg_reg(regD dst, regD src) %{ | |
| 7989 match(Set dst (SqrtD src)); | |
| 7990 | |
| 7991 size(4); | |
| 7992 format %{ "FSQRTD $src,$dst" %} | |
| 7993 ins_encode(fsqrtd(dst, src)); | |
| 7994 ins_pipe(fdivD_reg_reg); | |
| 7995 %} | |
| 7996 | |
| 7997 //----------Logical Instructions----------------------------------------------- | |
| 7998 // And Instructions | |
| 7999 // Register And | |
| 8000 instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 8001 match(Set dst (AndI src1 src2)); | |
| 8002 | |
| 8003 size(4); | |
| 8004 format %{ "AND $src1,$src2,$dst" %} | |
| 8005 opcode(Assembler::and_op3, Assembler::arith_op); | |
| 8006 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 8007 ins_pipe(ialu_reg_reg); | |
| 8008 %} | |
| 8009 | |
| 8010 // Immediate And | |
| 8011 instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
| 8012 match(Set dst (AndI src1 src2)); | |
| 8013 | |
| 8014 size(4); | |
| 8015 format %{ "AND $src1,$src2,$dst" %} | |
| 8016 opcode(Assembler::and_op3, Assembler::arith_op); | |
| 8017 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 8018 ins_pipe(ialu_reg_imm); | |
| 8019 %} | |
| 8020 | |
| 8021 // Register And Long | |
| 8022 instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 8023 match(Set dst (AndL src1 src2)); | |
| 8024 | |
| 8025 ins_cost(DEFAULT_COST); | |
| 8026 size(4); | |
| 8027 format %{ "AND $src1,$src2,$dst\t! long" %} | |
| 8028 opcode(Assembler::and_op3, Assembler::arith_op); | |
| 8029 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 8030 ins_pipe(ialu_reg_reg); | |
| 8031 %} | |
| 8032 | |
| 8033 instruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
| 8034 match(Set dst (AndL src1 con)); | |
| 8035 | |
| 8036 ins_cost(DEFAULT_COST); | |
| 8037 size(4); | |
| 8038 format %{ "AND $src1,$con,$dst\t! long" %} | |
| 8039 opcode(Assembler::and_op3, Assembler::arith_op); | |
| 8040 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
| 8041 ins_pipe(ialu_reg_imm); | |
| 8042 %} | |
| 8043 | |
| 8044 // Or Instructions | |
| 8045 // Register Or | |
| 8046 instruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 8047 match(Set dst (OrI src1 src2)); | |
| 8048 | |
| 8049 size(4); | |
| 8050 format %{ "OR $src1,$src2,$dst" %} | |
| 8051 opcode(Assembler::or_op3, Assembler::arith_op); | |
| 8052 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 8053 ins_pipe(ialu_reg_reg); | |
| 8054 %} | |
| 8055 | |
| 8056 // Immediate Or | |
| 8057 instruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
| 8058 match(Set dst (OrI src1 src2)); | |
| 8059 | |
| 8060 size(4); | |
| 8061 format %{ "OR $src1,$src2,$dst" %} | |
| 8062 opcode(Assembler::or_op3, Assembler::arith_op); | |
| 8063 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 8064 ins_pipe(ialu_reg_imm); | |
| 8065 %} | |
| 8066 | |
| 8067 // Register Or Long | |
| 8068 instruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 8069 match(Set dst (OrL src1 src2)); | |
| 8070 | |
| 8071 ins_cost(DEFAULT_COST); | |
| 8072 size(4); | |
| 8073 format %{ "OR $src1,$src2,$dst\t! long" %} | |
| 8074 opcode(Assembler::or_op3, Assembler::arith_op); | |
| 8075 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 8076 ins_pipe(ialu_reg_reg); | |
| 8077 %} | |
| 8078 | |
| 8079 instruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
| 8080 match(Set dst (OrL src1 con)); | |
| 8081 ins_cost(DEFAULT_COST*2); | |
| 8082 | |
| 8083 ins_cost(DEFAULT_COST); | |
| 8084 size(4); | |
| 8085 format %{ "OR $src1,$con,$dst\t! long" %} | |
| 8086 opcode(Assembler::or_op3, Assembler::arith_op); | |
| 8087 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
| 8088 ins_pipe(ialu_reg_imm); | |
| 8089 %} | |
| 8090 | |
|
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8091 #ifndef _LP64 |
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8092 |
|
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8093 // Use sp_ptr_RegP to match G2 (TLS register) without spilling. |
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8094 instruct orI_reg_castP2X(iRegI dst, iRegI src1, sp_ptr_RegP src2) %{ |
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8095 match(Set dst (OrI src1 (CastP2X src2))); |
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8096 |
|
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8097 size(4); |
|
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8098 format %{ "OR $src1,$src2,$dst" %} |
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8099 opcode(Assembler::or_op3, Assembler::arith_op); |
|
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8100 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); |
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8101 ins_pipe(ialu_reg_reg); |
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8102 %} |
|
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8103 |
|
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8104 #else |
|
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8105 |
|
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8106 instruct orL_reg_castP2X(iRegL dst, iRegL src1, sp_ptr_RegP src2) %{ |
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8107 match(Set dst (OrL src1 (CastP2X src2))); |
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8108 |
|
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8109 ins_cost(DEFAULT_COST); |
|
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8110 size(4); |
|
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8111 format %{ "OR $src1,$src2,$dst\t! long" %} |
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8112 opcode(Assembler::or_op3, Assembler::arith_op); |
|
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8113 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); |
|
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8114 ins_pipe(ialu_reg_reg); |
|
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8115 %} |
|
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8116 |
|
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8117 #endif |
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8118 |
| 0 | 8119 // Xor Instructions |
| 8120 // Register Xor | |
| 8121 instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 8122 match(Set dst (XorI src1 src2)); | |
| 8123 | |
| 8124 size(4); | |
| 8125 format %{ "XOR $src1,$src2,$dst" %} | |
| 8126 opcode(Assembler::xor_op3, Assembler::arith_op); | |
| 8127 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 8128 ins_pipe(ialu_reg_reg); | |
| 8129 %} | |
| 8130 | |
| 8131 // Immediate Xor | |
| 8132 instruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
| 8133 match(Set dst (XorI src1 src2)); | |
| 8134 | |
| 8135 size(4); | |
| 8136 format %{ "XOR $src1,$src2,$dst" %} | |
| 8137 opcode(Assembler::xor_op3, Assembler::arith_op); | |
| 8138 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 8139 ins_pipe(ialu_reg_imm); | |
| 8140 %} | |
| 8141 | |
| 8142 // Register Xor Long | |
| 8143 instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 8144 match(Set dst (XorL src1 src2)); | |
| 8145 | |
| 8146 ins_cost(DEFAULT_COST); | |
| 8147 size(4); | |
| 8148 format %{ "XOR $src1,$src2,$dst\t! long" %} | |
| 8149 opcode(Assembler::xor_op3, Assembler::arith_op); | |
| 8150 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 8151 ins_pipe(ialu_reg_reg); | |
| 8152 %} | |
| 8153 | |
| 8154 instruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
| 8155 match(Set dst (XorL src1 con)); | |
| 8156 | |
| 8157 ins_cost(DEFAULT_COST); | |
| 8158 size(4); | |
| 8159 format %{ "XOR $src1,$con,$dst\t! long" %} | |
| 8160 opcode(Assembler::xor_op3, Assembler::arith_op); | |
| 8161 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
| 8162 ins_pipe(ialu_reg_imm); | |
| 8163 %} | |
| 8164 | |
| 8165 //----------Convert to Boolean------------------------------------------------- | |
| 8166 // Nice hack for 32-bit tests but doesn't work for | |
| 8167 // 64-bit pointers. | |
| 8168 instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{ | |
| 8169 match(Set dst (Conv2B src)); | |
| 8170 effect( KILL ccr ); | |
| 8171 ins_cost(DEFAULT_COST*2); | |
| 8172 format %{ "CMP R_G0,$src\n\t" | |
| 8173 "ADDX R_G0,0,$dst" %} | |
| 8174 ins_encode( enc_to_bool( src, dst ) ); | |
| 8175 ins_pipe(ialu_reg_ialu); | |
| 8176 %} | |
| 8177 | |
| 8178 #ifndef _LP64 | |
| 8179 instruct convP2B( iRegI dst, iRegP src, flagsReg ccr ) %{ | |
| 8180 match(Set dst (Conv2B src)); | |
| 8181 effect( KILL ccr ); | |
| 8182 ins_cost(DEFAULT_COST*2); | |
| 8183 format %{ "CMP R_G0,$src\n\t" | |
| 8184 "ADDX R_G0,0,$dst" %} | |
| 8185 ins_encode( enc_to_bool( src, dst ) ); | |
| 8186 ins_pipe(ialu_reg_ialu); | |
| 8187 %} | |
| 8188 #else | |
| 8189 instruct convP2B( iRegI dst, iRegP src ) %{ | |
| 8190 match(Set dst (Conv2B src)); | |
| 8191 ins_cost(DEFAULT_COST*2); | |
| 8192 format %{ "MOV $src,$dst\n\t" | |
| 8193 "MOVRNZ $src,1,$dst" %} | |
| 8194 ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) ); | |
| 8195 ins_pipe(ialu_clr_and_mover); | |
| 8196 %} | |
| 8197 #endif | |
| 8198 | |
|
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7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
kvn
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2121
diff
changeset
|
8199 instruct cmpLTMask0( iRegI dst, iRegI src, immI0 zero, flagsReg ccr ) %{ |
|
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2121
diff
changeset
|
8200 match(Set dst (CmpLTMask src zero)); |
|
ab42c7e1cf83
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
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2121
diff
changeset
|
8201 effect(KILL ccr); |
|
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7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
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diff
changeset
|
8202 size(4); |
|
ab42c7e1cf83
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
kvn
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2121
diff
changeset
|
8203 format %{ "SRA $src,#31,$dst\t# cmpLTMask0" %} |
|
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7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
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2121
diff
changeset
|
8204 ins_encode %{ |
|
ab42c7e1cf83
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2121
diff
changeset
|
8205 __ sra($src$$Register, 31, $dst$$Register); |
|
ab42c7e1cf83
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|
8206 %} |
|
ab42c7e1cf83
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
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2121
diff
changeset
|
8207 ins_pipe(ialu_reg_imm); |
|
ab42c7e1cf83
7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
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2121
diff
changeset
|
8208 %} |
|
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diff
changeset
|
8209 |
| 0 | 8210 instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{ |
| 8211 match(Set dst (CmpLTMask p q)); | |
| 8212 effect( KILL ccr ); | |
| 8213 ins_cost(DEFAULT_COST*4); | |
| 8214 format %{ "CMP $p,$q\n\t" | |
| 8215 "MOV #0,$dst\n\t" | |
| 8216 "BLT,a .+8\n\t" | |
| 8217 "MOV #-1,$dst" %} | |
| 8218 ins_encode( enc_ltmask(p,q,dst) ); | |
| 8219 ins_pipe(ialu_reg_reg_ialu); | |
| 8220 %} | |
| 8221 | |
| 8222 instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{ | |
| 8223 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))); | |
| 8224 effect(KILL ccr, TEMP tmp); | |
| 8225 ins_cost(DEFAULT_COST*3); | |
| 8226 | |
| 8227 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t" | |
| 8228 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t" | |
|
2254
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7017746: Regression : C2 compiler crash due to SIGSEGV in PhaseCFG::schedule_early()
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2121
diff
changeset
|
8229 "MOVlt $tmp,$p\t! p' < 0 ? p'+y : p'" %} |
| 0 | 8230 ins_encode( enc_cadd_cmpLTMask(p, q, y, tmp) ); |
| 8231 ins_pipe( cadd_cmpltmask ); | |
| 8232 %} | |
| 8233 | |
| 3804 | 8234 |
| 8235 //----------------------------------------------------------------- | |
| 8236 // Direct raw moves between float and general registers using VIS3. | |
| 8237 | |
| 8238 // ins_pipe(faddF_reg); | |
| 8239 instruct MoveF2I_reg_reg(iRegI dst, regF src) %{ | |
| 8240 predicate(UseVIS >= 3); | |
| 8241 match(Set dst (MoveF2I src)); | |
| 8242 | |
| 8243 format %{ "MOVSTOUW $src,$dst\t! MoveF2I" %} | |
| 8244 ins_encode %{ | |
| 8245 __ movstouw($src$$FloatRegister, $dst$$Register); | |
| 8246 %} | |
| 8247 ins_pipe(ialu_reg_reg); | |
| 8248 %} | |
| 8249 | |
| 8250 instruct MoveI2F_reg_reg(regF dst, iRegI src) %{ | |
| 8251 predicate(UseVIS >= 3); | |
| 8252 match(Set dst (MoveI2F src)); | |
| 8253 | |
| 8254 format %{ "MOVWTOS $src,$dst\t! MoveI2F" %} | |
| 8255 ins_encode %{ | |
| 8256 __ movwtos($src$$Register, $dst$$FloatRegister); | |
| 8257 %} | |
| 0 | 8258 ins_pipe(ialu_reg_reg); |
| 8259 %} | |
| 8260 | |
| 3804 | 8261 instruct MoveD2L_reg_reg(iRegL dst, regD src) %{ |
| 8262 predicate(UseVIS >= 3); | |
| 8263 match(Set dst (MoveD2L src)); | |
| 8264 | |
| 8265 format %{ "MOVDTOX $src,$dst\t! MoveD2L" %} | |
| 8266 ins_encode %{ | |
| 8267 __ movdtox(as_DoubleFloatRegister($src$$reg), $dst$$Register); | |
| 8268 %} | |
| 0 | 8269 ins_pipe(ialu_reg_reg); |
| 8270 %} | |
| 8271 | |
| 3804 | 8272 instruct MoveL2D_reg_reg(regD dst, iRegL src) %{ |
| 8273 predicate(UseVIS >= 3); | |
| 8274 match(Set dst (MoveL2D src)); | |
| 8275 | |
| 8276 format %{ "MOVXTOD $src,$dst\t! MoveL2D" %} | |
| 8277 ins_encode %{ | |
| 8278 __ movxtod($src$$Register, as_DoubleFloatRegister($dst$$reg)); | |
| 8279 %} | |
| 0 | 8280 ins_pipe(ialu_reg_reg); |
| 8281 %} | |
| 8282 | |
| 3804 | 8283 |
| 8284 // Raw moves between float and general registers using stack. | |
| 8285 | |
| 0 | 8286 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{ |
| 8287 match(Set dst (MoveF2I src)); | |
| 8288 effect(DEF dst, USE src); | |
| 8289 ins_cost(MEMORY_REF_COST); | |
| 8290 | |
| 8291 size(4); | |
| 8292 format %{ "LDUW $src,$dst\t! MoveF2I" %} | |
| 8293 opcode(Assembler::lduw_op3); | |
|
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|
8294 ins_encode(simple_form3_mem_reg( src, dst ) ); |
| 0 | 8295 ins_pipe(iload_mem); |
| 8296 %} | |
| 8297 | |
| 8298 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{ | |
| 8299 match(Set dst (MoveI2F src)); | |
| 8300 effect(DEF dst, USE src); | |
| 8301 ins_cost(MEMORY_REF_COST); | |
| 8302 | |
| 8303 size(4); | |
| 8304 format %{ "LDF $src,$dst\t! MoveI2F" %} | |
| 8305 opcode(Assembler::ldf_op3); | |
|
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235
diff
changeset
|
8306 ins_encode(simple_form3_mem_reg(src, dst)); |
| 0 | 8307 ins_pipe(floadF_stk); |
| 8308 %} | |
| 8309 | |
| 8310 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{ | |
| 8311 match(Set dst (MoveD2L src)); | |
| 8312 effect(DEF dst, USE src); | |
| 8313 ins_cost(MEMORY_REF_COST); | |
| 8314 | |
| 8315 size(4); | |
| 8316 format %{ "LDX $src,$dst\t! MoveD2L" %} | |
| 8317 opcode(Assembler::ldx_op3); | |
|
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|
8318 ins_encode(simple_form3_mem_reg( src, dst ) ); |
| 0 | 8319 ins_pipe(iload_mem); |
| 8320 %} | |
| 8321 | |
| 8322 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{ | |
| 8323 match(Set dst (MoveL2D src)); | |
| 8324 effect(DEF dst, USE src); | |
| 8325 ins_cost(MEMORY_REF_COST); | |
| 8326 | |
| 8327 size(4); | |
| 8328 format %{ "LDDF $src,$dst\t! MoveL2D" %} | |
| 8329 opcode(Assembler::lddf_op3); | |
|
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|
8330 ins_encode(simple_form3_mem_reg(src, dst)); |
| 0 | 8331 ins_pipe(floadD_stk); |
| 8332 %} | |
| 8333 | |
| 8334 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{ | |
| 8335 match(Set dst (MoveF2I src)); | |
| 8336 effect(DEF dst, USE src); | |
| 8337 ins_cost(MEMORY_REF_COST); | |
| 8338 | |
| 8339 size(4); | |
| 3804 | 8340 format %{ "STF $src,$dst\t! MoveF2I" %} |
| 0 | 8341 opcode(Assembler::stf_op3); |
|
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|
8342 ins_encode(simple_form3_mem_reg(dst, src)); |
| 0 | 8343 ins_pipe(fstoreF_stk_reg); |
| 8344 %} | |
| 8345 | |
| 8346 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{ | |
| 8347 match(Set dst (MoveI2F src)); | |
| 8348 effect(DEF dst, USE src); | |
| 8349 ins_cost(MEMORY_REF_COST); | |
| 8350 | |
| 8351 size(4); | |
| 3804 | 8352 format %{ "STW $src,$dst\t! MoveI2F" %} |
| 0 | 8353 opcode(Assembler::stw_op3); |
|
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|
8354 ins_encode(simple_form3_mem_reg( dst, src ) ); |
| 0 | 8355 ins_pipe(istore_mem_reg); |
| 8356 %} | |
| 8357 | |
| 8358 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{ | |
| 8359 match(Set dst (MoveD2L src)); | |
| 8360 effect(DEF dst, USE src); | |
| 8361 ins_cost(MEMORY_REF_COST); | |
| 8362 | |
| 8363 size(4); | |
| 3804 | 8364 format %{ "STDF $src,$dst\t! MoveD2L" %} |
| 0 | 8365 opcode(Assembler::stdf_op3); |
|
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235
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|
8366 ins_encode(simple_form3_mem_reg(dst, src)); |
| 0 | 8367 ins_pipe(fstoreD_stk_reg); |
| 8368 %} | |
| 8369 | |
| 8370 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{ | |
| 8371 match(Set dst (MoveL2D src)); | |
| 8372 effect(DEF dst, USE src); | |
| 8373 ins_cost(MEMORY_REF_COST); | |
| 8374 | |
| 8375 size(4); | |
| 3804 | 8376 format %{ "STX $src,$dst\t! MoveL2D" %} |
| 0 | 8377 opcode(Assembler::stx_op3); |
|
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|
8378 ins_encode(simple_form3_mem_reg( dst, src ) ); |
| 0 | 8379 ins_pipe(istore_mem_reg); |
| 8380 %} | |
| 8381 | |
| 8382 | |
| 3804 | 8383 //----------Arithmetic Conversion Instructions--------------------------------- |
| 8384 // The conversions operations are all Alpha sorted. Please keep it that way! | |
| 8385 | |
| 8386 instruct convD2F_reg(regF dst, regD src) %{ | |
| 8387 match(Set dst (ConvD2F src)); | |
| 8388 size(4); | |
| 8389 format %{ "FDTOS $src,$dst" %} | |
| 8390 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf); | |
| 8391 ins_encode(form3_opf_rs2D_rdF(src, dst)); | |
| 8392 ins_pipe(fcvtD2F); | |
| 8393 %} | |
| 8394 | |
| 8395 | |
| 8396 // Convert a double to an int in a float register. | |
| 8397 // If the double is a NAN, stuff a zero in instead. | |
| 8398 instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{ | |
| 8399 effect(DEF dst, USE src, KILL fcc0); | |
| 8400 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t" | |
| 8401 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" | |
| 8402 "FDTOI $src,$dst\t! convert in delay slot\n\t" | |
| 8403 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t" | |
| 8404 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n" | |
| 8405 "skip:" %} | |
| 8406 ins_encode(form_d2i_helper(src,dst)); | |
| 8407 ins_pipe(fcvtD2I); | |
| 8408 %} | |
| 8409 | |
| 8410 instruct convD2I_stk(stackSlotI dst, regD src) %{ | |
| 8411 match(Set dst (ConvD2I src)); | |
| 8412 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); | |
| 8413 expand %{ | |
| 8414 regF tmp; | |
| 8415 convD2I_helper(tmp, src); | |
| 8416 regF_to_stkI(dst, tmp); | |
| 8417 %} | |
| 8418 %} | |
| 8419 | |
| 8420 instruct convD2I_reg(iRegI dst, regD src) %{ | |
| 8421 predicate(UseVIS >= 3); | |
| 8422 match(Set dst (ConvD2I src)); | |
| 8423 ins_cost(DEFAULT_COST*2 + BRANCH_COST); | |
| 8424 expand %{ | |
| 8425 regF tmp; | |
| 8426 convD2I_helper(tmp, src); | |
| 8427 MoveF2I_reg_reg(dst, tmp); | |
| 8428 %} | |
| 8429 %} | |
| 8430 | |
| 8431 | |
| 8432 // Convert a double to a long in a double register. | |
| 8433 // If the double is a NAN, stuff a zero in instead. | |
| 8434 instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{ | |
| 8435 effect(DEF dst, USE src, KILL fcc0); | |
| 8436 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t" | |
| 8437 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" | |
| 8438 "FDTOX $src,$dst\t! convert in delay slot\n\t" | |
| 8439 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t" | |
| 8440 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n" | |
| 8441 "skip:" %} | |
| 8442 ins_encode(form_d2l_helper(src,dst)); | |
| 8443 ins_pipe(fcvtD2L); | |
| 8444 %} | |
| 8445 | |
| 8446 instruct convD2L_stk(stackSlotL dst, regD src) %{ | |
| 8447 match(Set dst (ConvD2L src)); | |
| 8448 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); | |
| 8449 expand %{ | |
| 8450 regD tmp; | |
| 8451 convD2L_helper(tmp, src); | |
| 8452 regD_to_stkL(dst, tmp); | |
| 8453 %} | |
| 8454 %} | |
| 8455 | |
| 8456 instruct convD2L_reg(iRegL dst, regD src) %{ | |
| 8457 predicate(UseVIS >= 3); | |
| 8458 match(Set dst (ConvD2L src)); | |
| 8459 ins_cost(DEFAULT_COST*2 + BRANCH_COST); | |
| 8460 expand %{ | |
| 8461 regD tmp; | |
| 8462 convD2L_helper(tmp, src); | |
| 8463 MoveD2L_reg_reg(dst, tmp); | |
| 8464 %} | |
| 8465 %} | |
| 8466 | |
| 8467 | |
| 8468 instruct convF2D_reg(regD dst, regF src) %{ | |
| 8469 match(Set dst (ConvF2D src)); | |
| 8470 format %{ "FSTOD $src,$dst" %} | |
| 8471 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf); | |
| 8472 ins_encode(form3_opf_rs2F_rdD(src, dst)); | |
| 8473 ins_pipe(fcvtF2D); | |
| 8474 %} | |
| 8475 | |
| 8476 | |
| 8477 // Convert a float to an int in a float register. | |
| 8478 // If the float is a NAN, stuff a zero in instead. | |
| 8479 instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{ | |
| 8480 effect(DEF dst, USE src, KILL fcc0); | |
| 8481 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t" | |
| 8482 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" | |
| 8483 "FSTOI $src,$dst\t! convert in delay slot\n\t" | |
| 8484 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t" | |
| 8485 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n" | |
| 8486 "skip:" %} | |
| 8487 ins_encode(form_f2i_helper(src,dst)); | |
| 8488 ins_pipe(fcvtF2I); | |
| 8489 %} | |
| 8490 | |
| 8491 instruct convF2I_stk(stackSlotI dst, regF src) %{ | |
| 8492 match(Set dst (ConvF2I src)); | |
| 8493 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); | |
| 8494 expand %{ | |
| 8495 regF tmp; | |
| 8496 convF2I_helper(tmp, src); | |
| 8497 regF_to_stkI(dst, tmp); | |
| 8498 %} | |
| 8499 %} | |
| 8500 | |
| 8501 instruct convF2I_reg(iRegI dst, regF src) %{ | |
| 8502 predicate(UseVIS >= 3); | |
| 8503 match(Set dst (ConvF2I src)); | |
| 8504 ins_cost(DEFAULT_COST*2 + BRANCH_COST); | |
| 8505 expand %{ | |
| 8506 regF tmp; | |
| 8507 convF2I_helper(tmp, src); | |
| 8508 MoveF2I_reg_reg(dst, tmp); | |
| 8509 %} | |
| 8510 %} | |
| 8511 | |
| 8512 | |
| 8513 // Convert a float to a long in a float register. | |
| 8514 // If the float is a NAN, stuff a zero in instead. | |
| 8515 instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{ | |
| 8516 effect(DEF dst, USE src, KILL fcc0); | |
| 8517 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t" | |
| 8518 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" | |
| 8519 "FSTOX $src,$dst\t! convert in delay slot\n\t" | |
| 8520 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t" | |
| 8521 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n" | |
| 8522 "skip:" %} | |
| 8523 ins_encode(form_f2l_helper(src,dst)); | |
| 8524 ins_pipe(fcvtF2L); | |
| 8525 %} | |
| 8526 | |
| 8527 instruct convF2L_stk(stackSlotL dst, regF src) %{ | |
| 8528 match(Set dst (ConvF2L src)); | |
| 8529 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); | |
| 8530 expand %{ | |
| 8531 regD tmp; | |
| 8532 convF2L_helper(tmp, src); | |
| 8533 regD_to_stkL(dst, tmp); | |
| 8534 %} | |
| 8535 %} | |
| 8536 | |
| 8537 instruct convF2L_reg(iRegL dst, regF src) %{ | |
| 8538 predicate(UseVIS >= 3); | |
| 8539 match(Set dst (ConvF2L src)); | |
| 8540 ins_cost(DEFAULT_COST*2 + BRANCH_COST); | |
| 8541 expand %{ | |
| 8542 regD tmp; | |
| 8543 convF2L_helper(tmp, src); | |
| 8544 MoveD2L_reg_reg(dst, tmp); | |
| 8545 %} | |
| 8546 %} | |
| 8547 | |
| 8548 | |
| 8549 instruct convI2D_helper(regD dst, regF tmp) %{ | |
| 8550 effect(USE tmp, DEF dst); | |
| 8551 format %{ "FITOD $tmp,$dst" %} | |
| 8552 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf); | |
| 8553 ins_encode(form3_opf_rs2F_rdD(tmp, dst)); | |
| 8554 ins_pipe(fcvtI2D); | |
| 8555 %} | |
| 8556 | |
| 8557 instruct convI2D_stk(stackSlotI src, regD dst) %{ | |
| 8558 match(Set dst (ConvI2D src)); | |
| 8559 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
| 8560 expand %{ | |
| 8561 regF tmp; | |
| 8562 stkI_to_regF(tmp, src); | |
| 8563 convI2D_helper(dst, tmp); | |
| 8564 %} | |
| 8565 %} | |
| 8566 | |
| 8567 instruct convI2D_reg(regD_low dst, iRegI src) %{ | |
| 8568 predicate(UseVIS >= 3); | |
| 8569 match(Set dst (ConvI2D src)); | |
| 8570 expand %{ | |
| 8571 regF tmp; | |
| 8572 MoveI2F_reg_reg(tmp, src); | |
| 8573 convI2D_helper(dst, tmp); | |
| 8574 %} | |
| 8575 %} | |
| 8576 | |
| 8577 instruct convI2D_mem(regD_low dst, memory mem) %{ | |
| 8578 match(Set dst (ConvI2D (LoadI mem))); | |
| 8579 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
| 8580 size(8); | |
| 8581 format %{ "LDF $mem,$dst\n\t" | |
| 8582 "FITOD $dst,$dst" %} | |
| 8583 opcode(Assembler::ldf_op3, Assembler::fitod_opf); | |
| 8584 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst)); | |
| 8585 ins_pipe(floadF_mem); | |
| 8586 %} | |
| 8587 | |
| 8588 | |
| 8589 instruct convI2F_helper(regF dst, regF tmp) %{ | |
| 8590 effect(DEF dst, USE tmp); | |
| 8591 format %{ "FITOS $tmp,$dst" %} | |
| 8592 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf); | |
| 8593 ins_encode(form3_opf_rs2F_rdF(tmp, dst)); | |
| 8594 ins_pipe(fcvtI2F); | |
| 8595 %} | |
| 8596 | |
| 8597 instruct convI2F_stk(regF dst, stackSlotI src) %{ | |
| 8598 match(Set dst (ConvI2F src)); | |
| 8599 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
| 8600 expand %{ | |
| 8601 regF tmp; | |
| 8602 stkI_to_regF(tmp,src); | |
| 8603 convI2F_helper(dst, tmp); | |
| 8604 %} | |
| 8605 %} | |
| 8606 | |
| 8607 instruct convI2F_reg(regF dst, iRegI src) %{ | |
| 8608 predicate(UseVIS >= 3); | |
| 8609 match(Set dst (ConvI2F src)); | |
| 8610 ins_cost(DEFAULT_COST); | |
| 8611 expand %{ | |
| 8612 regF tmp; | |
| 8613 MoveI2F_reg_reg(tmp, src); | |
| 8614 convI2F_helper(dst, tmp); | |
| 8615 %} | |
| 8616 %} | |
| 8617 | |
| 8618 instruct convI2F_mem( regF dst, memory mem ) %{ | |
| 8619 match(Set dst (ConvI2F (LoadI mem))); | |
| 8620 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
| 8621 size(8); | |
| 8622 format %{ "LDF $mem,$dst\n\t" | |
| 8623 "FITOS $dst,$dst" %} | |
| 8624 opcode(Assembler::ldf_op3, Assembler::fitos_opf); | |
| 8625 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst)); | |
| 8626 ins_pipe(floadF_mem); | |
| 8627 %} | |
| 8628 | |
| 8629 | |
| 8630 instruct convI2L_reg(iRegL dst, iRegI src) %{ | |
| 8631 match(Set dst (ConvI2L src)); | |
| 8632 size(4); | |
| 8633 format %{ "SRA $src,0,$dst\t! int->long" %} | |
| 8634 opcode(Assembler::sra_op3, Assembler::arith_op); | |
| 8635 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); | |
| 8636 ins_pipe(ialu_reg_reg); | |
| 8637 %} | |
| 8638 | |
| 8639 // Zero-extend convert int to long | |
| 8640 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{ | |
| 8641 match(Set dst (AndL (ConvI2L src) mask) ); | |
| 8642 size(4); | |
| 8643 format %{ "SRL $src,0,$dst\t! zero-extend int to long" %} | |
| 8644 opcode(Assembler::srl_op3, Assembler::arith_op); | |
| 8645 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); | |
| 8646 ins_pipe(ialu_reg_reg); | |
| 8647 %} | |
| 8648 | |
| 8649 // Zero-extend long | |
| 8650 instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{ | |
| 8651 match(Set dst (AndL src mask) ); | |
| 8652 size(4); | |
| 8653 format %{ "SRL $src,0,$dst\t! zero-extend long" %} | |
| 8654 opcode(Assembler::srl_op3, Assembler::arith_op); | |
| 8655 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); | |
| 8656 ins_pipe(ialu_reg_reg); | |
| 8657 %} | |
| 8658 | |
| 8659 | |
| 0 | 8660 //----------- |
| 8661 // Long to Double conversion using V8 opcodes. | |
| 8662 // Still useful because cheetah traps and becomes | |
| 8663 // amazingly slow for some common numbers. | |
| 8664 | |
| 8665 // Magic constant, 0x43300000 | |
| 8666 instruct loadConI_x43300000(iRegI dst) %{ | |
| 8667 effect(DEF dst); | |
| 8668 size(4); | |
| 8669 format %{ "SETHI HI(0x43300000),$dst\t! 2^52" %} | |
| 8670 ins_encode(SetHi22(0x43300000, dst)); | |
| 8671 ins_pipe(ialu_none); | |
| 8672 %} | |
| 8673 | |
| 8674 // Magic constant, 0x41f00000 | |
| 8675 instruct loadConI_x41f00000(iRegI dst) %{ | |
| 8676 effect(DEF dst); | |
| 8677 size(4); | |
| 8678 format %{ "SETHI HI(0x41f00000),$dst\t! 2^32" %} | |
| 8679 ins_encode(SetHi22(0x41f00000, dst)); | |
| 8680 ins_pipe(ialu_none); | |
| 8681 %} | |
| 8682 | |
| 8683 // Construct a double from two float halves | |
| 8684 instruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{ | |
| 8685 effect(DEF dst, USE src1, USE src2); | |
| 8686 size(8); | |
| 8687 format %{ "FMOVS $src1.hi,$dst.hi\n\t" | |
| 8688 "FMOVS $src2.lo,$dst.lo" %} | |
| 8689 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf); | |
| 8690 ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst)); | |
| 8691 ins_pipe(faddD_reg_reg); | |
| 8692 %} | |
| 8693 | |
| 8694 // Convert integer in high half of a double register (in the lower half of | |
| 8695 // the double register file) to double | |
| 8696 instruct convI2D_regDHi_regD(regD dst, regD_low src) %{ | |
| 8697 effect(DEF dst, USE src); | |
| 8698 size(4); | |
| 8699 format %{ "FITOD $src,$dst" %} | |
| 8700 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf); | |
| 8701 ins_encode(form3_opf_rs2D_rdD(src, dst)); | |
| 8702 ins_pipe(fcvtLHi2D); | |
| 8703 %} | |
| 8704 | |
| 8705 // Add float double precision | |
| 8706 instruct addD_regD_regD(regD dst, regD src1, regD src2) %{ | |
| 8707 effect(DEF dst, USE src1, USE src2); | |
| 8708 size(4); | |
| 8709 format %{ "FADDD $src1,$src2,$dst" %} | |
| 8710 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf); | |
| 8711 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
| 8712 ins_pipe(faddD_reg_reg); | |
| 8713 %} | |
| 8714 | |
| 8715 // Sub float double precision | |
| 8716 instruct subD_regD_regD(regD dst, regD src1, regD src2) %{ | |
| 8717 effect(DEF dst, USE src1, USE src2); | |
| 8718 size(4); | |
| 8719 format %{ "FSUBD $src1,$src2,$dst" %} | |
| 8720 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf); | |
| 8721 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
| 8722 ins_pipe(faddD_reg_reg); | |
| 8723 %} | |
| 8724 | |
| 8725 // Mul float double precision | |
| 8726 instruct mulD_regD_regD(regD dst, regD src1, regD src2) %{ | |
| 8727 effect(DEF dst, USE src1, USE src2); | |
| 8728 size(4); | |
| 8729 format %{ "FMULD $src1,$src2,$dst" %} | |
| 8730 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf); | |
| 8731 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
| 8732 ins_pipe(fmulD_reg_reg); | |
| 8733 %} | |
| 8734 | |
| 8735 instruct convL2D_reg_slow_fxtof(regD dst, stackSlotL src) %{ | |
| 8736 match(Set dst (ConvL2D src)); | |
| 8737 ins_cost(DEFAULT_COST*8 + MEMORY_REF_COST*6); | |
| 8738 | |
| 8739 expand %{ | |
| 8740 regD_low tmpsrc; | |
| 8741 iRegI ix43300000; | |
| 8742 iRegI ix41f00000; | |
| 8743 stackSlotL lx43300000; | |
| 8744 stackSlotL lx41f00000; | |
| 8745 regD_low dx43300000; | |
| 8746 regD dx41f00000; | |
| 8747 regD tmp1; | |
| 8748 regD_low tmp2; | |
| 8749 regD tmp3; | |
| 8750 regD tmp4; | |
| 8751 | |
| 8752 stkL_to_regD(tmpsrc, src); | |
| 8753 | |
| 8754 loadConI_x43300000(ix43300000); | |
| 8755 loadConI_x41f00000(ix41f00000); | |
| 8756 regI_to_stkLHi(lx43300000, ix43300000); | |
| 8757 regI_to_stkLHi(lx41f00000, ix41f00000); | |
| 8758 stkL_to_regD(dx43300000, lx43300000); | |
| 8759 stkL_to_regD(dx41f00000, lx41f00000); | |
| 8760 | |
| 8761 convI2D_regDHi_regD(tmp1, tmpsrc); | |
| 8762 regDHi_regDLo_to_regD(tmp2, dx43300000, tmpsrc); | |
| 8763 subD_regD_regD(tmp3, tmp2, dx43300000); | |
| 8764 mulD_regD_regD(tmp4, tmp1, dx41f00000); | |
| 8765 addD_regD_regD(dst, tmp3, tmp4); | |
| 8766 %} | |
| 8767 %} | |
| 8768 | |
| 8769 // Long to Double conversion using fast fxtof | |
| 8770 instruct convL2D_helper(regD dst, regD tmp) %{ | |
| 8771 effect(DEF dst, USE tmp); | |
| 8772 size(4); | |
| 8773 format %{ "FXTOD $tmp,$dst" %} | |
| 8774 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf); | |
| 8775 ins_encode(form3_opf_rs2D_rdD(tmp, dst)); | |
| 8776 ins_pipe(fcvtL2D); | |
| 8777 %} | |
| 8778 | |
| 3804 | 8779 instruct convL2D_stk_fast_fxtof(regD dst, stackSlotL src) %{ |
| 0 | 8780 predicate(VM_Version::has_fast_fxtof()); |
| 8781 match(Set dst (ConvL2D src)); | |
| 8782 ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST); | |
| 8783 expand %{ | |
| 8784 regD tmp; | |
| 8785 stkL_to_regD(tmp, src); | |
| 8786 convL2D_helper(dst, tmp); | |
| 8787 %} | |
| 8788 %} | |
| 8789 | |
| 3804 | 8790 instruct convL2D_reg(regD dst, iRegL src) %{ |
| 8791 predicate(UseVIS >= 3); | |
| 8792 match(Set dst (ConvL2D src)); | |
| 8793 expand %{ | |
| 8794 regD tmp; | |
| 8795 MoveL2D_reg_reg(tmp, src); | |
| 8796 convL2D_helper(dst, tmp); | |
| 8797 %} | |
| 8798 %} | |
| 0 | 8799 |
| 8800 // Long to Float conversion using fast fxtof | |
| 8801 instruct convL2F_helper(regF dst, regD tmp) %{ | |
| 8802 effect(DEF dst, USE tmp); | |
| 8803 size(4); | |
| 8804 format %{ "FXTOS $tmp,$dst" %} | |
| 8805 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf); | |
| 8806 ins_encode(form3_opf_rs2D_rdF(tmp, dst)); | |
| 8807 ins_pipe(fcvtL2F); | |
| 8808 %} | |
| 8809 | |
| 3804 | 8810 instruct convL2F_stk_fast_fxtof(regF dst, stackSlotL src) %{ |
| 0 | 8811 match(Set dst (ConvL2F src)); |
| 8812 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
| 8813 expand %{ | |
| 8814 regD tmp; | |
| 8815 stkL_to_regD(tmp, src); | |
| 8816 convL2F_helper(dst, tmp); | |
| 8817 %} | |
| 8818 %} | |
| 3804 | 8819 |
| 8820 instruct convL2F_reg(regF dst, iRegL src) %{ | |
| 8821 predicate(UseVIS >= 3); | |
| 8822 match(Set dst (ConvL2F src)); | |
| 8823 ins_cost(DEFAULT_COST); | |
| 8824 expand %{ | |
| 8825 regD tmp; | |
| 8826 MoveL2D_reg_reg(tmp, src); | |
| 8827 convL2F_helper(dst, tmp); | |
| 8828 %} | |
| 8829 %} | |
| 8830 | |
| 0 | 8831 //----------- |
| 8832 | |
| 8833 instruct convL2I_reg(iRegI dst, iRegL src) %{ | |
| 8834 match(Set dst (ConvL2I src)); | |
| 8835 #ifndef _LP64 | |
| 8836 format %{ "MOV $src.lo,$dst\t! long->int" %} | |
| 8837 ins_encode( form3_g0_rs2_rd_move_lo2( src, dst ) ); | |
| 8838 ins_pipe(ialu_move_reg_I_to_L); | |
| 8839 #else | |
| 8840 size(4); | |
| 8841 format %{ "SRA $src,R_G0,$dst\t! long->int" %} | |
| 8842 ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) ); | |
| 8843 ins_pipe(ialu_reg); | |
| 8844 #endif | |
| 8845 %} | |
| 8846 | |
| 8847 // Register Shift Right Immediate | |
| 8848 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{ | |
| 8849 match(Set dst (ConvL2I (RShiftL src cnt))); | |
| 8850 | |
| 8851 size(4); | |
| 8852 format %{ "SRAX $src,$cnt,$dst" %} | |
| 8853 opcode(Assembler::srax_op3, Assembler::arith_op); | |
| 8854 ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) ); | |
| 8855 ins_pipe(ialu_reg_imm); | |
| 8856 %} | |
| 8857 | |
| 8858 // Replicate scalar to packed byte values in Double register | |
| 8859 instruct Repl8B_reg_helper(iRegL dst, iRegI src) %{ | |
| 8860 effect(DEF dst, USE src); | |
| 8861 format %{ "SLLX $src,56,$dst\n\t" | |
| 8862 "SRLX $dst, 8,O7\n\t" | |
| 8863 "OR $dst,O7,$dst\n\t" | |
| 8864 "SRLX $dst,16,O7\n\t" | |
| 8865 "OR $dst,O7,$dst\n\t" | |
| 8866 "SRLX $dst,32,O7\n\t" | |
| 8867 "OR $dst,O7,$dst\t! replicate8B" %} | |
| 8868 ins_encode( enc_repl8b(src, dst)); | |
| 8869 ins_pipe(ialu_reg); | |
| 8870 %} | |
| 8871 | |
| 8872 // Replicate scalar to packed byte values in Double register | |
| 8873 instruct Repl8B_reg(stackSlotD dst, iRegI src) %{ | |
| 8874 match(Set dst (Replicate8B src)); | |
| 8875 expand %{ | |
| 8876 iRegL tmp; | |
| 8877 Repl8B_reg_helper(tmp, src); | |
| 8878 regL_to_stkD(dst, tmp); | |
| 8879 %} | |
| 8880 %} | |
| 8881 | |
| 8882 // Replicate scalar constant to packed byte values in Double register | |
|
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
8883 instruct Repl8B_immI(regD dst, immI13 con, o7RegI tmp) %{ |
| 2008 | 8884 match(Set dst (Replicate8B con)); |
|
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
8885 effect(KILL tmp); |
| 2008 | 8886 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl8B($con)" %} |
| 8887 ins_encode %{ | |
| 8888 // XXX This is a quick fix for 6833573. | |
| 8889 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 8, 1)), $dst$$FloatRegister); | |
|
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
8890 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 8, 1)), $tmp$$Register); |
|
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
8891 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); |
| 2008 | 8892 %} |
| 0 | 8893 ins_pipe(loadConFD); |
| 8894 %} | |
| 8895 | |
| 8896 // Replicate scalar to packed char values into stack slot | |
| 8897 instruct Repl4C_reg_helper(iRegL dst, iRegI src) %{ | |
| 8898 effect(DEF dst, USE src); | |
| 8899 format %{ "SLLX $src,48,$dst\n\t" | |
| 8900 "SRLX $dst,16,O7\n\t" | |
| 8901 "OR $dst,O7,$dst\n\t" | |
| 8902 "SRLX $dst,32,O7\n\t" | |
| 8903 "OR $dst,O7,$dst\t! replicate4C" %} | |
| 8904 ins_encode( enc_repl4s(src, dst) ); | |
| 8905 ins_pipe(ialu_reg); | |
| 8906 %} | |
| 8907 | |
| 8908 // Replicate scalar to packed char values into stack slot | |
| 8909 instruct Repl4C_reg(stackSlotD dst, iRegI src) %{ | |
| 8910 match(Set dst (Replicate4C src)); | |
| 8911 expand %{ | |
| 8912 iRegL tmp; | |
| 8913 Repl4C_reg_helper(tmp, src); | |
| 8914 regL_to_stkD(dst, tmp); | |
| 8915 %} | |
| 8916 %} | |
| 8917 | |
| 8918 // Replicate scalar constant to packed char values in Double register | |
|
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
8919 instruct Repl4C_immI(regD dst, immI con, o7RegI tmp) %{ |
| 2008 | 8920 match(Set dst (Replicate4C con)); |
|
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
8921 effect(KILL tmp); |
| 2008 | 8922 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4C($con)" %} |
| 8923 ins_encode %{ | |
| 8924 // XXX This is a quick fix for 6833573. | |
| 8925 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister); | |
|
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
8926 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 4, 2)), $tmp$$Register); |
|
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
8927 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); |
| 2008 | 8928 %} |
| 0 | 8929 ins_pipe(loadConFD); |
| 8930 %} | |
| 8931 | |
| 8932 // Replicate scalar to packed short values into stack slot | |
| 8933 instruct Repl4S_reg_helper(iRegL dst, iRegI src) %{ | |
| 8934 effect(DEF dst, USE src); | |
| 8935 format %{ "SLLX $src,48,$dst\n\t" | |
| 8936 "SRLX $dst,16,O7\n\t" | |
| 8937 "OR $dst,O7,$dst\n\t" | |
| 8938 "SRLX $dst,32,O7\n\t" | |
| 8939 "OR $dst,O7,$dst\t! replicate4S" %} | |
| 8940 ins_encode( enc_repl4s(src, dst) ); | |
| 8941 ins_pipe(ialu_reg); | |
| 8942 %} | |
| 8943 | |
| 8944 // Replicate scalar to packed short values into stack slot | |
| 8945 instruct Repl4S_reg(stackSlotD dst, iRegI src) %{ | |
| 8946 match(Set dst (Replicate4S src)); | |
| 8947 expand %{ | |
| 8948 iRegL tmp; | |
| 8949 Repl4S_reg_helper(tmp, src); | |
| 8950 regL_to_stkD(dst, tmp); | |
| 8951 %} | |
| 8952 %} | |
| 8953 | |
| 8954 // Replicate scalar constant to packed short values in Double register | |
|
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
8955 instruct Repl4S_immI(regD dst, immI con, o7RegI tmp) %{ |
| 2008 | 8956 match(Set dst (Replicate4S con)); |
|
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
8957 effect(KILL tmp); |
| 2008 | 8958 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4S($con)" %} |
| 8959 ins_encode %{ | |
| 8960 // XXX This is a quick fix for 6833573. | |
| 8961 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister); | |
|
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
8962 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 4, 2)), $tmp$$Register); |
|
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
8963 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); |
| 2008 | 8964 %} |
| 0 | 8965 ins_pipe(loadConFD); |
| 8966 %} | |
| 8967 | |
| 8968 // Replicate scalar to packed int values in Double register | |
| 8969 instruct Repl2I_reg_helper(iRegL dst, iRegI src) %{ | |
| 8970 effect(DEF dst, USE src); | |
| 8971 format %{ "SLLX $src,32,$dst\n\t" | |
| 8972 "SRLX $dst,32,O7\n\t" | |
| 8973 "OR $dst,O7,$dst\t! replicate2I" %} | |
| 8974 ins_encode( enc_repl2i(src, dst)); | |
| 8975 ins_pipe(ialu_reg); | |
| 8976 %} | |
| 8977 | |
| 8978 // Replicate scalar to packed int values in Double register | |
| 8979 instruct Repl2I_reg(stackSlotD dst, iRegI src) %{ | |
| 8980 match(Set dst (Replicate2I src)); | |
| 8981 expand %{ | |
| 8982 iRegL tmp; | |
| 8983 Repl2I_reg_helper(tmp, src); | |
| 8984 regL_to_stkD(dst, tmp); | |
| 8985 %} | |
| 8986 %} | |
| 8987 | |
| 8988 // Replicate scalar zero constant to packed int values in Double register | |
|
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
8989 instruct Repl2I_immI(regD dst, immI con, o7RegI tmp) %{ |
| 2008 | 8990 match(Set dst (Replicate2I con)); |
|
2012
5fe0781a8560
7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
kvn
parents:
2008
diff
changeset
|
8991 effect(KILL tmp); |
| 2008 | 8992 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2I($con)" %} |
| 8993 ins_encode %{ | |
| 8994 // XXX This is a quick fix for 6833573. | |
| 8995 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 2, 4)), $dst$$FloatRegister); | |
|
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|
8996 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 2, 4)), $tmp$$Register); |
|
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8997 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); |
| 2008 | 8998 %} |
| 0 | 8999 ins_pipe(loadConFD); |
| 9000 %} | |
| 9001 | |
| 9002 //----------Control Flow Instructions------------------------------------------ | |
| 9003 // Compare Instructions | |
| 9004 // Compare Integers | |
| 9005 instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{ | |
| 9006 match(Set icc (CmpI op1 op2)); | |
| 9007 effect( DEF icc, USE op1, USE op2 ); | |
| 9008 | |
| 9009 size(4); | |
| 9010 format %{ "CMP $op1,$op2" %} | |
| 9011 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
| 9012 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
| 9013 ins_pipe(ialu_cconly_reg_reg); | |
| 9014 %} | |
| 9015 | |
| 9016 instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{ | |
| 9017 match(Set icc (CmpU op1 op2)); | |
| 9018 | |
| 9019 size(4); | |
| 9020 format %{ "CMP $op1,$op2\t! unsigned" %} | |
| 9021 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
| 9022 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
| 9023 ins_pipe(ialu_cconly_reg_reg); | |
| 9024 %} | |
| 9025 | |
| 9026 instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{ | |
| 9027 match(Set icc (CmpI op1 op2)); | |
| 9028 effect( DEF icc, USE op1 ); | |
| 9029 | |
| 9030 size(4); | |
| 9031 format %{ "CMP $op1,$op2" %} | |
| 9032 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
| 9033 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); | |
| 9034 ins_pipe(ialu_cconly_reg_imm); | |
| 9035 %} | |
| 9036 | |
| 9037 instruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{ | |
| 9038 match(Set icc (CmpI (AndI op1 op2) zero)); | |
| 9039 | |
| 9040 size(4); | |
| 9041 format %{ "BTST $op2,$op1" %} | |
| 9042 opcode(Assembler::andcc_op3, Assembler::arith_op); | |
| 9043 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
| 9044 ins_pipe(ialu_cconly_reg_reg_zero); | |
| 9045 %} | |
| 9046 | |
| 9047 instruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{ | |
| 9048 match(Set icc (CmpI (AndI op1 op2) zero)); | |
| 9049 | |
| 9050 size(4); | |
| 9051 format %{ "BTST $op2,$op1" %} | |
| 9052 opcode(Assembler::andcc_op3, Assembler::arith_op); | |
| 9053 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); | |
| 9054 ins_pipe(ialu_cconly_reg_imm_zero); | |
| 9055 %} | |
| 9056 | |
| 9057 instruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{ | |
| 9058 match(Set xcc (CmpL op1 op2)); | |
| 9059 effect( DEF xcc, USE op1, USE op2 ); | |
| 9060 | |
| 9061 size(4); | |
| 9062 format %{ "CMP $op1,$op2\t\t! long" %} | |
| 9063 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
| 9064 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
| 9065 ins_pipe(ialu_cconly_reg_reg); | |
| 9066 %} | |
| 9067 | |
| 9068 instruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{ | |
| 9069 match(Set xcc (CmpL op1 con)); | |
| 9070 effect( DEF xcc, USE op1, USE con ); | |
| 9071 | |
| 9072 size(4); | |
| 9073 format %{ "CMP $op1,$con\t\t! long" %} | |
| 9074 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
| 9075 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) ); | |
| 9076 ins_pipe(ialu_cconly_reg_reg); | |
| 9077 %} | |
| 9078 | |
| 9079 instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{ | |
| 9080 match(Set xcc (CmpL (AndL op1 op2) zero)); | |
| 9081 effect( DEF xcc, USE op1, USE op2 ); | |
| 9082 | |
| 9083 size(4); | |
| 9084 format %{ "BTST $op1,$op2\t\t! long" %} | |
| 9085 opcode(Assembler::andcc_op3, Assembler::arith_op); | |
| 9086 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
| 9087 ins_pipe(ialu_cconly_reg_reg); | |
| 9088 %} | |
| 9089 | |
| 9090 // useful for checking the alignment of a pointer: | |
| 9091 instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{ | |
| 9092 match(Set xcc (CmpL (AndL op1 con) zero)); | |
| 9093 effect( DEF xcc, USE op1, USE con ); | |
| 9094 | |
| 9095 size(4); | |
| 9096 format %{ "BTST $op1,$con\t\t! long" %} | |
| 9097 opcode(Assembler::andcc_op3, Assembler::arith_op); | |
| 9098 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) ); | |
| 9099 ins_pipe(ialu_cconly_reg_reg); | |
| 9100 %} | |
| 9101 | |
| 9102 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU13 op2 ) %{ | |
| 9103 match(Set icc (CmpU op1 op2)); | |
| 9104 | |
| 9105 size(4); | |
| 9106 format %{ "CMP $op1,$op2\t! unsigned" %} | |
| 9107 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
| 9108 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); | |
| 9109 ins_pipe(ialu_cconly_reg_imm); | |
| 9110 %} | |
| 9111 | |
| 9112 // Compare Pointers | |
| 9113 instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{ | |
| 9114 match(Set pcc (CmpP op1 op2)); | |
| 9115 | |
| 9116 size(4); | |
| 9117 format %{ "CMP $op1,$op2\t! ptr" %} | |
| 9118 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
| 9119 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
| 9120 ins_pipe(ialu_cconly_reg_reg); | |
| 9121 %} | |
| 9122 | |
| 9123 instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{ | |
| 9124 match(Set pcc (CmpP op1 op2)); | |
| 9125 | |
| 9126 size(4); | |
| 9127 format %{ "CMP $op1,$op2\t! ptr" %} | |
| 9128 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
| 9129 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); | |
| 9130 ins_pipe(ialu_cconly_reg_imm); | |
| 9131 %} | |
| 9132 | |
|
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9133 // Compare Narrow oops |
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9134 instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{ |
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9135 match(Set icc (CmpN op1 op2)); |
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9136 |
|
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9137 size(4); |
|
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9138 format %{ "CMP $op1,$op2\t! compressed ptr" %} |
|
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9139 opcode(Assembler::subcc_op3, Assembler::arith_op); |
|
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9140 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); |
|
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9141 ins_pipe(ialu_cconly_reg_reg); |
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9142 %} |
|
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9143 |
|
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9144 instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{ |
|
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9145 match(Set icc (CmpN op1 op2)); |
|
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9146 |
|
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9147 size(4); |
|
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9148 format %{ "CMP $op1,$op2\t! compressed ptr" %} |
|
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9149 opcode(Assembler::subcc_op3, Assembler::arith_op); |
|
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9150 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); |
|
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9151 ins_pipe(ialu_cconly_reg_imm); |
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9152 %} |
|
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9153 |
| 0 | 9154 //----------Max and Min-------------------------------------------------------- |
| 9155 // Min Instructions | |
| 9156 // Conditional move for min | |
| 9157 instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{ | |
| 9158 effect( USE_DEF op2, USE op1, USE icc ); | |
| 9159 | |
| 9160 size(4); | |
| 9161 format %{ "MOVlt icc,$op1,$op2\t! min" %} | |
| 9162 opcode(Assembler::less); | |
| 9163 ins_encode( enc_cmov_reg_minmax(op2,op1) ); | |
| 9164 ins_pipe(ialu_reg_flags); | |
| 9165 %} | |
| 9166 | |
| 9167 // Min Register with Register. | |
| 9168 instruct minI_eReg(iRegI op1, iRegI op2) %{ | |
| 9169 match(Set op2 (MinI op1 op2)); | |
| 9170 ins_cost(DEFAULT_COST*2); | |
| 9171 expand %{ | |
| 9172 flagsReg icc; | |
| 9173 compI_iReg(icc,op1,op2); | |
| 9174 cmovI_reg_lt(op2,op1,icc); | |
| 9175 %} | |
| 9176 %} | |
| 9177 | |
| 9178 // Max Instructions | |
| 9179 // Conditional move for max | |
| 9180 instruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{ | |
| 9181 effect( USE_DEF op2, USE op1, USE icc ); | |
| 9182 format %{ "MOVgt icc,$op1,$op2\t! max" %} | |
| 9183 opcode(Assembler::greater); | |
| 9184 ins_encode( enc_cmov_reg_minmax(op2,op1) ); | |
| 9185 ins_pipe(ialu_reg_flags); | |
| 9186 %} | |
| 9187 | |
| 9188 // Max Register with Register | |
| 9189 instruct maxI_eReg(iRegI op1, iRegI op2) %{ | |
| 9190 match(Set op2 (MaxI op1 op2)); | |
| 9191 ins_cost(DEFAULT_COST*2); | |
| 9192 expand %{ | |
| 9193 flagsReg icc; | |
| 9194 compI_iReg(icc,op1,op2); | |
| 9195 cmovI_reg_gt(op2,op1,icc); | |
| 9196 %} | |
| 9197 %} | |
| 9198 | |
| 9199 | |
| 9200 //----------Float Compares---------------------------------------------------- | |
| 9201 // Compare floating, generate condition code | |
| 9202 instruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{ | |
| 9203 match(Set fcc (CmpF src1 src2)); | |
| 9204 | |
| 9205 size(4); | |
| 9206 format %{ "FCMPs $fcc,$src1,$src2" %} | |
| 9207 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf); | |
| 9208 ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) ); | |
| 9209 ins_pipe(faddF_fcc_reg_reg_zero); | |
| 9210 %} | |
| 9211 | |
| 9212 instruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{ | |
| 9213 match(Set fcc (CmpD src1 src2)); | |
| 9214 | |
| 9215 size(4); | |
| 9216 format %{ "FCMPd $fcc,$src1,$src2" %} | |
| 9217 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf); | |
| 9218 ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) ); | |
| 9219 ins_pipe(faddD_fcc_reg_reg_zero); | |
| 9220 %} | |
| 9221 | |
| 9222 | |
| 9223 // Compare floating, generate -1,0,1 | |
| 9224 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{ | |
| 9225 match(Set dst (CmpF3 src1 src2)); | |
| 9226 effect(KILL fcc0); | |
| 9227 ins_cost(DEFAULT_COST*3+BRANCH_COST*3); | |
| 9228 format %{ "fcmpl $dst,$src1,$src2" %} | |
| 9229 // Primary = float | |
| 9230 opcode( true ); | |
| 9231 ins_encode( floating_cmp( dst, src1, src2 ) ); | |
| 9232 ins_pipe( floating_cmp ); | |
| 9233 %} | |
| 9234 | |
| 9235 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{ | |
| 9236 match(Set dst (CmpD3 src1 src2)); | |
| 9237 effect(KILL fcc0); | |
| 9238 ins_cost(DEFAULT_COST*3+BRANCH_COST*3); | |
| 9239 format %{ "dcmpl $dst,$src1,$src2" %} | |
| 9240 // Primary = double (not float) | |
| 9241 opcode( false ); | |
| 9242 ins_encode( floating_cmp( dst, src1, src2 ) ); | |
| 9243 ins_pipe( floating_cmp ); | |
| 9244 %} | |
| 9245 | |
| 9246 //----------Branches--------------------------------------------------------- | |
| 9247 // Jump | |
| 9248 // (compare 'operand indIndex' and 'instruct addP_reg_reg' above) | |
| 9249 instruct jumpXtnd(iRegX switch_val, o7RegI table) %{ | |
| 9250 match(Jump switch_val); | |
| 9251 | |
| 9252 ins_cost(350); | |
| 9253 | |
| 2008 | 9254 format %{ "ADD $constanttablebase, $constantoffset, O7\n\t" |
| 9255 "LD [O7 + $switch_val], O7\n\t" | |
| 0 | 9256 "JUMP O7" |
| 9257 %} | |
| 2008 | 9258 ins_encode %{ |
| 9259 // Calculate table address into a register. | |
| 9260 Register table_reg; | |
| 9261 Register label_reg = O7; | |
| 9262 if (constant_offset() == 0) { | |
| 9263 table_reg = $constanttablebase; | |
| 9264 } else { | |
| 9265 table_reg = O7; | |
|
2012
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7004925: CTW: assert(nbits == 32 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1)) failed: value out of range
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9266 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset, O7); |
|
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|
9267 __ add($constanttablebase, con_offset, table_reg); |
| 2008 | 9268 } |
| 9269 | |
| 9270 // Jump to base address + switch value | |
| 9271 __ ld_ptr(table_reg, $switch_val$$Register, label_reg); | |
| 9272 __ jmp(label_reg, G0); | |
| 9273 __ delayed()->nop(); | |
| 9274 %} | |
| 0 | 9275 ins_pipe(ialu_reg_reg); |
| 9276 %} | |
| 9277 | |
| 9278 // Direct Branch. Use V8 version with longer range. | |
| 9279 instruct branch(label labl) %{ | |
| 9280 match(Goto); | |
| 9281 effect(USE labl); | |
| 9282 | |
| 9283 size(8); | |
| 9284 ins_cost(BRANCH_COST); | |
| 9285 format %{ "BA $labl" %} | |
| 3839 | 9286 ins_encode %{ |
| 9287 Label* L = $labl$$label; | |
| 9288 __ ba(*L); | |
| 9289 __ delayed()->nop(); | |
| 9290 %} | |
| 0 | 9291 ins_pipe(br); |
| 9292 %} | |
| 9293 | |
| 3851 | 9294 // Direct Branch, short with no delay slot |
| 9295 instruct branch_short(label labl) %{ | |
| 9296 match(Goto); | |
| 9297 predicate(UseCBCond); | |
| 9298 effect(USE labl); | |
| 9299 | |
| 9300 size(4); | |
| 9301 ins_cost(BRANCH_COST); | |
| 9302 format %{ "BA $labl\t! short branch" %} | |
| 9303 ins_encode %{ | |
| 9304 Label* L = $labl$$label; | |
| 9305 assert(__ use_cbcond(*L), "back to back cbcond"); | |
| 9306 __ ba_short(*L); | |
| 9307 %} | |
| 9308 ins_short_branch(1); | |
| 9309 ins_avoid_back_to_back(1); | |
| 9310 ins_pipe(cbcond_reg_imm); | |
| 9311 %} | |
| 9312 | |
| 0 | 9313 // Conditional Direct Branch |
| 9314 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{ | |
| 9315 match(If cmp icc); | |
| 9316 effect(USE labl); | |
| 9317 | |
| 9318 size(8); | |
| 9319 ins_cost(BRANCH_COST); | |
| 9320 format %{ "BP$cmp $icc,$labl" %} | |
| 9321 // Prim = bits 24-22, Secnd = bits 31-30 | |
| 9322 ins_encode( enc_bp( labl, cmp, icc ) ); | |
| 9323 ins_pipe(br_cc); | |
| 9324 %} | |
| 9325 | |
| 9326 instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{ | |
| 9327 match(If cmp icc); | |
| 9328 effect(USE labl); | |
| 9329 | |
| 3851 | 9330 ins_cost(BRANCH_COST); |
| 0 | 9331 format %{ "BP$cmp $icc,$labl" %} |
| 9332 // Prim = bits 24-22, Secnd = bits 31-30 | |
| 9333 ins_encode( enc_bp( labl, cmp, icc ) ); | |
| 9334 ins_pipe(br_cc); | |
| 9335 %} | |
| 9336 | |
| 9337 instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{ | |
| 9338 match(If cmp pcc); | |
| 9339 effect(USE labl); | |
| 9340 | |
| 9341 size(8); | |
| 9342 ins_cost(BRANCH_COST); | |
| 9343 format %{ "BP$cmp $pcc,$labl" %} | |
| 3839 | 9344 ins_encode %{ |
| 9345 Label* L = $labl$$label; | |
| 9346 Assembler::Predict predict_taken = | |
| 9347 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
| 9348 | |
| 9349 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L); | |
| 9350 __ delayed()->nop(); | |
| 9351 %} | |
| 0 | 9352 ins_pipe(br_cc); |
| 9353 %} | |
| 9354 | |
| 9355 instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{ | |
| 9356 match(If cmp fcc); | |
| 9357 effect(USE labl); | |
| 9358 | |
| 9359 size(8); | |
| 9360 ins_cost(BRANCH_COST); | |
| 9361 format %{ "FBP$cmp $fcc,$labl" %} | |
| 3839 | 9362 ins_encode %{ |
| 9363 Label* L = $labl$$label; | |
| 9364 Assembler::Predict predict_taken = | |
| 9365 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
| 9366 | |
| 9367 __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($fcc$$reg), predict_taken, *L); | |
| 9368 __ delayed()->nop(); | |
| 9369 %} | |
| 0 | 9370 ins_pipe(br_fcc); |
| 9371 %} | |
| 9372 | |
| 9373 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{ | |
| 9374 match(CountedLoopEnd cmp icc); | |
| 9375 effect(USE labl); | |
| 9376 | |
| 9377 size(8); | |
| 9378 ins_cost(BRANCH_COST); | |
| 9379 format %{ "BP$cmp $icc,$labl\t! Loop end" %} | |
| 9380 // Prim = bits 24-22, Secnd = bits 31-30 | |
| 9381 ins_encode( enc_bp( labl, cmp, icc ) ); | |
| 9382 ins_pipe(br_cc); | |
| 9383 %} | |
| 9384 | |
| 9385 instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{ | |
| 9386 match(CountedLoopEnd cmp icc); | |
| 9387 effect(USE labl); | |
| 9388 | |
| 9389 size(8); | |
| 9390 ins_cost(BRANCH_COST); | |
| 9391 format %{ "BP$cmp $icc,$labl\t! Loop end" %} | |
| 9392 // Prim = bits 24-22, Secnd = bits 31-30 | |
| 9393 ins_encode( enc_bp( labl, cmp, icc ) ); | |
| 9394 ins_pipe(br_cc); | |
| 9395 %} | |
| 9396 | |
| 3851 | 9397 // Compare and branch instructions |
| 9398 instruct cmpI_reg_branch(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{ | |
| 9399 match(If cmp (CmpI op1 op2)); | |
| 9400 effect(USE labl, KILL icc); | |
| 9401 | |
| 9402 size(12); | |
| 9403 ins_cost(BRANCH_COST); | |
| 9404 format %{ "CMP $op1,$op2\t! int\n\t" | |
| 9405 "BP$cmp $labl" %} | |
| 9406 ins_encode %{ | |
| 9407 Label* L = $labl$$label; | |
| 9408 Assembler::Predict predict_taken = | |
| 9409 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
| 9410 __ cmp($op1$$Register, $op2$$Register); | |
| 9411 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); | |
| 9412 __ delayed()->nop(); | |
| 9413 %} | |
| 9414 ins_pipe(cmp_br_reg_reg); | |
| 9415 %} | |
| 9416 | |
| 9417 instruct cmpI_imm_branch(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{ | |
| 9418 match(If cmp (CmpI op1 op2)); | |
| 9419 effect(USE labl, KILL icc); | |
| 9420 | |
| 9421 size(12); | |
| 9422 ins_cost(BRANCH_COST); | |
| 9423 format %{ "CMP $op1,$op2\t! int\n\t" | |
| 9424 "BP$cmp $labl" %} | |
| 9425 ins_encode %{ | |
| 9426 Label* L = $labl$$label; | |
| 9427 Assembler::Predict predict_taken = | |
| 9428 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
| 9429 __ cmp($op1$$Register, $op2$$constant); | |
| 9430 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); | |
| 9431 __ delayed()->nop(); | |
| 9432 %} | |
| 9433 ins_pipe(cmp_br_reg_imm); | |
| 9434 %} | |
| 9435 | |
| 9436 instruct cmpU_reg_branch(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{ | |
| 9437 match(If cmp (CmpU op1 op2)); | |
| 9438 effect(USE labl, KILL icc); | |
| 9439 | |
| 9440 size(12); | |
| 9441 ins_cost(BRANCH_COST); | |
| 9442 format %{ "CMP $op1,$op2\t! unsigned\n\t" | |
| 9443 "BP$cmp $labl" %} | |
| 9444 ins_encode %{ | |
| 9445 Label* L = $labl$$label; | |
| 9446 Assembler::Predict predict_taken = | |
| 9447 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
| 9448 __ cmp($op1$$Register, $op2$$Register); | |
| 9449 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); | |
| 9450 __ delayed()->nop(); | |
| 9451 %} | |
| 9452 ins_pipe(cmp_br_reg_reg); | |
| 9453 %} | |
| 9454 | |
| 9455 instruct cmpU_imm_branch(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{ | |
| 9456 match(If cmp (CmpU op1 op2)); | |
| 9457 effect(USE labl, KILL icc); | |
| 9458 | |
| 9459 size(12); | |
| 9460 ins_cost(BRANCH_COST); | |
| 9461 format %{ "CMP $op1,$op2\t! unsigned\n\t" | |
| 9462 "BP$cmp $labl" %} | |
| 9463 ins_encode %{ | |
| 9464 Label* L = $labl$$label; | |
| 9465 Assembler::Predict predict_taken = | |
| 9466 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
| 9467 __ cmp($op1$$Register, $op2$$constant); | |
| 9468 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); | |
| 9469 __ delayed()->nop(); | |
| 9470 %} | |
| 9471 ins_pipe(cmp_br_reg_imm); | |
| 9472 %} | |
| 9473 | |
| 9474 instruct cmpL_reg_branch(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{ | |
| 9475 match(If cmp (CmpL op1 op2)); | |
| 9476 effect(USE labl, KILL xcc); | |
| 9477 | |
| 9478 size(12); | |
| 9479 ins_cost(BRANCH_COST); | |
| 9480 format %{ "CMP $op1,$op2\t! long\n\t" | |
| 9481 "BP$cmp $labl" %} | |
| 9482 ins_encode %{ | |
| 9483 Label* L = $labl$$label; | |
| 9484 Assembler::Predict predict_taken = | |
| 9485 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
| 9486 __ cmp($op1$$Register, $op2$$Register); | |
| 9487 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L); | |
| 9488 __ delayed()->nop(); | |
| 9489 %} | |
| 9490 ins_pipe(cmp_br_reg_reg); | |
| 9491 %} | |
| 9492 | |
| 9493 instruct cmpL_imm_branch(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{ | |
| 9494 match(If cmp (CmpL op1 op2)); | |
| 9495 effect(USE labl, KILL xcc); | |
| 9496 | |
| 9497 size(12); | |
| 9498 ins_cost(BRANCH_COST); | |
| 9499 format %{ "CMP $op1,$op2\t! long\n\t" | |
| 9500 "BP$cmp $labl" %} | |
| 9501 ins_encode %{ | |
| 9502 Label* L = $labl$$label; | |
| 9503 Assembler::Predict predict_taken = | |
| 9504 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
| 9505 __ cmp($op1$$Register, $op2$$constant); | |
| 9506 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L); | |
| 9507 __ delayed()->nop(); | |
| 9508 %} | |
| 9509 ins_pipe(cmp_br_reg_imm); | |
| 9510 %} | |
| 9511 | |
| 9512 // Compare Pointers and branch | |
| 9513 instruct cmpP_reg_branch(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{ | |
| 9514 match(If cmp (CmpP op1 op2)); | |
| 9515 effect(USE labl, KILL pcc); | |
| 9516 | |
| 9517 size(12); | |
| 9518 ins_cost(BRANCH_COST); | |
| 9519 format %{ "CMP $op1,$op2\t! ptr\n\t" | |
| 9520 "B$cmp $labl" %} | |
| 9521 ins_encode %{ | |
| 9522 Label* L = $labl$$label; | |
| 9523 Assembler::Predict predict_taken = | |
| 9524 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
| 9525 __ cmp($op1$$Register, $op2$$Register); | |
| 9526 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L); | |
| 9527 __ delayed()->nop(); | |
| 9528 %} | |
| 9529 ins_pipe(cmp_br_reg_reg); | |
| 9530 %} | |
| 9531 | |
| 9532 instruct cmpP_null_branch(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{ | |
| 9533 match(If cmp (CmpP op1 null)); | |
| 9534 effect(USE labl, KILL pcc); | |
| 9535 | |
| 9536 size(12); | |
| 9537 ins_cost(BRANCH_COST); | |
| 9538 format %{ "CMP $op1,0\t! ptr\n\t" | |
| 9539 "B$cmp $labl" %} | |
| 9540 ins_encode %{ | |
| 9541 Label* L = $labl$$label; | |
| 9542 Assembler::Predict predict_taken = | |
| 9543 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
| 9544 __ cmp($op1$$Register, G0); | |
| 9545 // bpr() is not used here since it has shorter distance. | |
| 9546 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L); | |
| 9547 __ delayed()->nop(); | |
| 9548 %} | |
| 9549 ins_pipe(cmp_br_reg_reg); | |
| 9550 %} | |
| 9551 | |
| 9552 instruct cmpN_reg_branch(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{ | |
| 9553 match(If cmp (CmpN op1 op2)); | |
| 9554 effect(USE labl, KILL icc); | |
| 9555 | |
| 9556 size(12); | |
| 9557 ins_cost(BRANCH_COST); | |
| 9558 format %{ "CMP $op1,$op2\t! compressed ptr\n\t" | |
| 9559 "BP$cmp $labl" %} | |
| 9560 ins_encode %{ | |
| 9561 Label* L = $labl$$label; | |
| 9562 Assembler::Predict predict_taken = | |
| 9563 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
| 9564 __ cmp($op1$$Register, $op2$$Register); | |
| 9565 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); | |
| 9566 __ delayed()->nop(); | |
| 9567 %} | |
| 9568 ins_pipe(cmp_br_reg_reg); | |
| 9569 %} | |
| 9570 | |
| 9571 instruct cmpN_null_branch(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{ | |
| 9572 match(If cmp (CmpN op1 null)); | |
| 9573 effect(USE labl, KILL icc); | |
| 9574 | |
| 9575 size(12); | |
| 9576 ins_cost(BRANCH_COST); | |
| 9577 format %{ "CMP $op1,0\t! compressed ptr\n\t" | |
| 9578 "BP$cmp $labl" %} | |
| 9579 ins_encode %{ | |
| 9580 Label* L = $labl$$label; | |
| 9581 Assembler::Predict predict_taken = | |
| 9582 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
| 9583 __ cmp($op1$$Register, G0); | |
| 9584 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); | |
| 9585 __ delayed()->nop(); | |
| 9586 %} | |
| 9587 ins_pipe(cmp_br_reg_reg); | |
| 9588 %} | |
| 9589 | |
| 9590 // Loop back branch | |
| 9591 instruct cmpI_reg_branchLoopEnd(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{ | |
| 9592 match(CountedLoopEnd cmp (CmpI op1 op2)); | |
| 9593 effect(USE labl, KILL icc); | |
| 9594 | |
| 9595 size(12); | |
| 9596 ins_cost(BRANCH_COST); | |
| 9597 format %{ "CMP $op1,$op2\t! int\n\t" | |
| 9598 "BP$cmp $labl\t! Loop end" %} | |
| 9599 ins_encode %{ | |
| 9600 Label* L = $labl$$label; | |
| 9601 Assembler::Predict predict_taken = | |
| 9602 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
| 9603 __ cmp($op1$$Register, $op2$$Register); | |
| 9604 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); | |
| 9605 __ delayed()->nop(); | |
| 9606 %} | |
| 9607 ins_pipe(cmp_br_reg_reg); | |
| 9608 %} | |
| 9609 | |
| 9610 instruct cmpI_imm_branchLoopEnd(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{ | |
| 9611 match(CountedLoopEnd cmp (CmpI op1 op2)); | |
| 9612 effect(USE labl, KILL icc); | |
| 9613 | |
| 9614 size(12); | |
| 9615 ins_cost(BRANCH_COST); | |
| 9616 format %{ "CMP $op1,$op2\t! int\n\t" | |
| 9617 "BP$cmp $labl\t! Loop end" %} | |
| 9618 ins_encode %{ | |
| 9619 Label* L = $labl$$label; | |
| 9620 Assembler::Predict predict_taken = | |
| 9621 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
| 9622 __ cmp($op1$$Register, $op2$$constant); | |
| 9623 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); | |
| 9624 __ delayed()->nop(); | |
| 9625 %} | |
| 9626 ins_pipe(cmp_br_reg_imm); | |
| 9627 %} | |
| 9628 | |
| 9629 // Short compare and branch instructions | |
| 9630 instruct cmpI_reg_branch_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{ | |
| 9631 match(If cmp (CmpI op1 op2)); | |
| 9632 predicate(UseCBCond); | |
| 9633 effect(USE labl, KILL icc); | |
| 9634 | |
| 9635 size(4); | |
| 9636 ins_cost(BRANCH_COST); | |
| 9637 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %} | |
| 9638 ins_encode %{ | |
| 9639 Label* L = $labl$$label; | |
| 9640 assert(__ use_cbcond(*L), "back to back cbcond"); | |
| 9641 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L); | |
| 9642 %} | |
| 9643 ins_short_branch(1); | |
| 9644 ins_avoid_back_to_back(1); | |
| 9645 ins_pipe(cbcond_reg_reg); | |
| 9646 %} | |
| 9647 | |
| 9648 instruct cmpI_imm_branch_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{ | |
| 9649 match(If cmp (CmpI op1 op2)); | |
| 9650 predicate(UseCBCond); | |
| 9651 effect(USE labl, KILL icc); | |
| 9652 | |
| 9653 size(4); | |
| 9654 ins_cost(BRANCH_COST); | |
| 9655 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %} | |
| 9656 ins_encode %{ | |
| 9657 Label* L = $labl$$label; | |
| 9658 assert(__ use_cbcond(*L), "back to back cbcond"); | |
| 9659 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L); | |
| 9660 %} | |
| 9661 ins_short_branch(1); | |
| 9662 ins_avoid_back_to_back(1); | |
| 9663 ins_pipe(cbcond_reg_imm); | |
| 9664 %} | |
| 9665 | |
| 9666 instruct cmpU_reg_branch_short(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{ | |
| 9667 match(If cmp (CmpU op1 op2)); | |
| 9668 predicate(UseCBCond); | |
| 9669 effect(USE labl, KILL icc); | |
| 9670 | |
| 9671 size(4); | |
| 9672 ins_cost(BRANCH_COST); | |
| 9673 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %} | |
| 9674 ins_encode %{ | |
| 9675 Label* L = $labl$$label; | |
| 9676 assert(__ use_cbcond(*L), "back to back cbcond"); | |
| 9677 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L); | |
| 9678 %} | |
| 9679 ins_short_branch(1); | |
| 9680 ins_avoid_back_to_back(1); | |
| 9681 ins_pipe(cbcond_reg_reg); | |
| 9682 %} | |
| 9683 | |
| 9684 instruct cmpU_imm_branch_short(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{ | |
| 9685 match(If cmp (CmpU op1 op2)); | |
| 9686 predicate(UseCBCond); | |
| 9687 effect(USE labl, KILL icc); | |
| 9688 | |
| 9689 size(4); | |
| 9690 ins_cost(BRANCH_COST); | |
| 9691 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %} | |
| 9692 ins_encode %{ | |
| 9693 Label* L = $labl$$label; | |
| 9694 assert(__ use_cbcond(*L), "back to back cbcond"); | |
| 9695 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L); | |
| 9696 %} | |
| 9697 ins_short_branch(1); | |
| 9698 ins_avoid_back_to_back(1); | |
| 9699 ins_pipe(cbcond_reg_imm); | |
| 9700 %} | |
| 9701 | |
| 9702 instruct cmpL_reg_branch_short(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{ | |
| 9703 match(If cmp (CmpL op1 op2)); | |
| 9704 predicate(UseCBCond); | |
| 9705 effect(USE labl, KILL xcc); | |
| 9706 | |
| 9707 size(4); | |
| 9708 ins_cost(BRANCH_COST); | |
| 9709 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %} | |
| 9710 ins_encode %{ | |
| 9711 Label* L = $labl$$label; | |
| 9712 assert(__ use_cbcond(*L), "back to back cbcond"); | |
| 9713 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$Register, *L); | |
| 9714 %} | |
| 9715 ins_short_branch(1); | |
| 9716 ins_avoid_back_to_back(1); | |
| 9717 ins_pipe(cbcond_reg_reg); | |
| 9718 %} | |
| 9719 | |
| 9720 instruct cmpL_imm_branch_short(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{ | |
| 9721 match(If cmp (CmpL op1 op2)); | |
| 9722 predicate(UseCBCond); | |
| 9723 effect(USE labl, KILL xcc); | |
| 9724 | |
| 9725 size(4); | |
| 9726 ins_cost(BRANCH_COST); | |
| 9727 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %} | |
| 9728 ins_encode %{ | |
| 9729 Label* L = $labl$$label; | |
| 9730 assert(__ use_cbcond(*L), "back to back cbcond"); | |
| 9731 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$constant, *L); | |
| 9732 %} | |
| 9733 ins_short_branch(1); | |
| 9734 ins_avoid_back_to_back(1); | |
| 9735 ins_pipe(cbcond_reg_imm); | |
| 9736 %} | |
| 9737 | |
| 9738 // Compare Pointers and branch | |
| 9739 instruct cmpP_reg_branch_short(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{ | |
| 9740 match(If cmp (CmpP op1 op2)); | |
| 9741 predicate(UseCBCond); | |
| 9742 effect(USE labl, KILL pcc); | |
| 9743 | |
| 9744 size(4); | |
| 9745 ins_cost(BRANCH_COST); | |
| 9746 #ifdef _LP64 | |
| 9747 format %{ "CXB$cmp $op1,$op2,$labl\t! ptr" %} | |
| 9748 #else | |
| 9749 format %{ "CWB$cmp $op1,$op2,$labl\t! ptr" %} | |
| 9750 #endif | |
| 9751 ins_encode %{ | |
| 9752 Label* L = $labl$$label; | |
| 9753 assert(__ use_cbcond(*L), "back to back cbcond"); | |
| 9754 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, $op2$$Register, *L); | |
| 9755 %} | |
| 9756 ins_short_branch(1); | |
| 9757 ins_avoid_back_to_back(1); | |
| 9758 ins_pipe(cbcond_reg_reg); | |
| 9759 %} | |
| 9760 | |
| 9761 instruct cmpP_null_branch_short(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{ | |
| 9762 match(If cmp (CmpP op1 null)); | |
| 9763 predicate(UseCBCond); | |
| 9764 effect(USE labl, KILL pcc); | |
| 9765 | |
| 9766 size(4); | |
| 9767 ins_cost(BRANCH_COST); | |
| 9768 #ifdef _LP64 | |
| 9769 format %{ "CXB$cmp $op1,0,$labl\t! ptr" %} | |
| 9770 #else | |
| 9771 format %{ "CWB$cmp $op1,0,$labl\t! ptr" %} | |
| 9772 #endif | |
| 9773 ins_encode %{ | |
| 9774 Label* L = $labl$$label; | |
| 9775 assert(__ use_cbcond(*L), "back to back cbcond"); | |
| 9776 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, G0, *L); | |
| 9777 %} | |
| 9778 ins_short_branch(1); | |
| 9779 ins_avoid_back_to_back(1); | |
| 9780 ins_pipe(cbcond_reg_reg); | |
| 9781 %} | |
| 9782 | |
| 9783 instruct cmpN_reg_branch_short(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{ | |
| 9784 match(If cmp (CmpN op1 op2)); | |
| 9785 predicate(UseCBCond); | |
| 9786 effect(USE labl, KILL icc); | |
| 9787 | |
| 9788 size(4); | |
| 9789 ins_cost(BRANCH_COST); | |
| 9790 format %{ "CWB$cmp $op1,op2,$labl\t! compressed ptr" %} | |
| 9791 ins_encode %{ | |
| 9792 Label* L = $labl$$label; | |
| 9793 assert(__ use_cbcond(*L), "back to back cbcond"); | |
| 9794 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L); | |
| 9795 %} | |
| 9796 ins_short_branch(1); | |
| 9797 ins_avoid_back_to_back(1); | |
| 9798 ins_pipe(cbcond_reg_reg); | |
| 9799 %} | |
| 9800 | |
| 9801 instruct cmpN_null_branch_short(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{ | |
| 9802 match(If cmp (CmpN op1 null)); | |
| 9803 predicate(UseCBCond); | |
| 9804 effect(USE labl, KILL icc); | |
| 9805 | |
| 9806 size(4); | |
| 9807 ins_cost(BRANCH_COST); | |
| 9808 format %{ "CWB$cmp $op1,0,$labl\t! compressed ptr" %} | |
| 9809 ins_encode %{ | |
| 9810 Label* L = $labl$$label; | |
| 9811 assert(__ use_cbcond(*L), "back to back cbcond"); | |
| 9812 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, G0, *L); | |
| 9813 %} | |
| 9814 ins_short_branch(1); | |
| 9815 ins_avoid_back_to_back(1); | |
| 9816 ins_pipe(cbcond_reg_reg); | |
| 9817 %} | |
| 9818 | |
| 9819 // Loop back branch | |
| 9820 instruct cmpI_reg_branchLoopEnd_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{ | |
| 9821 match(CountedLoopEnd cmp (CmpI op1 op2)); | |
| 9822 predicate(UseCBCond); | |
| 9823 effect(USE labl, KILL icc); | |
| 9824 | |
| 9825 size(4); | |
| 9826 ins_cost(BRANCH_COST); | |
| 9827 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %} | |
| 9828 ins_encode %{ | |
| 9829 Label* L = $labl$$label; | |
| 9830 assert(__ use_cbcond(*L), "back to back cbcond"); | |
| 9831 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L); | |
| 9832 %} | |
| 9833 ins_short_branch(1); | |
| 9834 ins_avoid_back_to_back(1); | |
| 9835 ins_pipe(cbcond_reg_reg); | |
| 9836 %} | |
| 9837 | |
| 9838 instruct cmpI_imm_branchLoopEnd_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{ | |
| 9839 match(CountedLoopEnd cmp (CmpI op1 op2)); | |
| 9840 predicate(UseCBCond); | |
| 9841 effect(USE labl, KILL icc); | |
| 9842 | |
| 9843 size(4); | |
| 9844 ins_cost(BRANCH_COST); | |
| 9845 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %} | |
| 9846 ins_encode %{ | |
| 9847 Label* L = $labl$$label; | |
| 9848 assert(__ use_cbcond(*L), "back to back cbcond"); | |
| 9849 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L); | |
| 9850 %} | |
| 9851 ins_short_branch(1); | |
| 9852 ins_avoid_back_to_back(1); | |
| 9853 ins_pipe(cbcond_reg_imm); | |
| 9854 %} | |
| 9855 | |
| 9856 // Branch-on-register tests all 64 bits. We assume that values | |
| 9857 // in 64-bit registers always remains zero or sign extended | |
| 9858 // unless our code munges the high bits. Interrupts can chop | |
| 9859 // the high order bits to zero or sign at any time. | |
| 9860 instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{ | |
| 9861 match(If cmp (CmpI op1 zero)); | |
| 9862 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); | |
| 9863 effect(USE labl); | |
| 9864 | |
| 9865 size(8); | |
| 9866 ins_cost(BRANCH_COST); | |
| 9867 format %{ "BR$cmp $op1,$labl" %} | |
| 9868 ins_encode( enc_bpr( labl, cmp, op1 ) ); | |
| 9869 ins_pipe(br_reg); | |
| 9870 %} | |
| 9871 | |
| 9872 instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{ | |
| 9873 match(If cmp (CmpP op1 null)); | |
| 9874 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); | |
| 9875 effect(USE labl); | |
| 9876 | |
| 9877 size(8); | |
| 9878 ins_cost(BRANCH_COST); | |
| 9879 format %{ "BR$cmp $op1,$labl" %} | |
| 9880 ins_encode( enc_bpr( labl, cmp, op1 ) ); | |
| 9881 ins_pipe(br_reg); | |
| 9882 %} | |
| 9883 | |
| 9884 instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{ | |
| 9885 match(If cmp (CmpL op1 zero)); | |
| 9886 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); | |
| 9887 effect(USE labl); | |
| 9888 | |
| 9889 size(8); | |
| 9890 ins_cost(BRANCH_COST); | |
| 9891 format %{ "BR$cmp $op1,$labl" %} | |
| 9892 ins_encode( enc_bpr( labl, cmp, op1 ) ); | |
| 9893 ins_pipe(br_reg); | |
| 9894 %} | |
| 9895 | |
| 9896 | |
| 0 | 9897 // ============================================================================ |
| 9898 // Long Compare | |
| 9899 // | |
| 9900 // Currently we hold longs in 2 registers. Comparing such values efficiently | |
| 9901 // is tricky. The flavor of compare used depends on whether we are testing | |
| 9902 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit. | |
| 9903 // The GE test is the negated LT test. The LE test can be had by commuting | |
| 9904 // the operands (yielding a GE test) and then negating; negate again for the | |
| 9905 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the | |
| 9906 // NE test is negated from that. | |
| 9907 | |
| 9908 // Due to a shortcoming in the ADLC, it mixes up expressions like: | |
| 9909 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the | |
| 9910 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections | |
| 9911 // are collapsed internally in the ADLC's dfa-gen code. The match for | |
| 9912 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the | |
| 9913 // foo match ends up with the wrong leaf. One fix is to not match both | |
| 9914 // reg-reg and reg-zero forms of long-compare. This is unfortunate because | |
| 9915 // both forms beat the trinary form of long-compare and both are very useful | |
| 9916 // on Intel which has so few registers. | |
| 9917 | |
| 9918 instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{ | |
| 9919 match(If cmp xcc); | |
| 9920 effect(USE labl); | |
| 9921 | |
| 9922 size(8); | |
| 9923 ins_cost(BRANCH_COST); | |
| 9924 format %{ "BP$cmp $xcc,$labl" %} | |
| 3839 | 9925 ins_encode %{ |
| 9926 Label* L = $labl$$label; | |
| 9927 Assembler::Predict predict_taken = | |
| 9928 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; | |
| 9929 | |
| 9930 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L); | |
| 9931 __ delayed()->nop(); | |
| 9932 %} | |
| 0 | 9933 ins_pipe(br_cc); |
| 9934 %} | |
| 9935 | |
| 9936 // Manifest a CmpL3 result in an integer register. Very painful. | |
| 9937 // This is the test to avoid. | |
| 9938 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{ | |
| 9939 match(Set dst (CmpL3 src1 src2) ); | |
| 9940 effect( KILL ccr ); | |
| 9941 ins_cost(6*DEFAULT_COST); | |
| 9942 size(24); | |
| 9943 format %{ "CMP $src1,$src2\t\t! long\n" | |
| 9944 "\tBLT,a,pn done\n" | |
| 9945 "\tMOV -1,$dst\t! delay slot\n" | |
| 9946 "\tBGT,a,pn done\n" | |
| 9947 "\tMOV 1,$dst\t! delay slot\n" | |
| 9948 "\tCLR $dst\n" | |
| 9949 "done:" %} | |
| 9950 ins_encode( cmpl_flag(src1,src2,dst) ); | |
| 9951 ins_pipe(cmpL_reg); | |
| 9952 %} | |
| 9953 | |
| 9954 // Conditional move | |
| 9955 instruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{ | |
| 9956 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src))); | |
| 9957 ins_cost(150); | |
| 9958 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %} | |
| 9959 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); | |
| 9960 ins_pipe(ialu_reg); | |
| 9961 %} | |
| 9962 | |
| 9963 instruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{ | |
| 9964 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src))); | |
| 9965 ins_cost(140); | |
| 9966 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %} | |
| 9967 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); | |
| 9968 ins_pipe(ialu_imm); | |
| 9969 %} | |
| 9970 | |
| 9971 instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{ | |
| 9972 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src))); | |
| 9973 ins_cost(150); | |
| 9974 format %{ "MOV$cmp $xcc,$src,$dst" %} | |
| 9975 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); | |
| 9976 ins_pipe(ialu_reg); | |
| 9977 %} | |
| 9978 | |
| 9979 instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{ | |
| 9980 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src))); | |
| 9981 ins_cost(140); | |
| 9982 format %{ "MOV$cmp $xcc,$src,$dst" %} | |
| 9983 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); | |
| 9984 ins_pipe(ialu_imm); | |
| 9985 %} | |
| 9986 | |
|
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9987 instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{ |
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9988 match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src))); |
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9989 ins_cost(150); |
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9990 format %{ "MOV$cmp $xcc,$src,$dst" %} |
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9991 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); |
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9992 ins_pipe(ialu_reg); |
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9993 %} |
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9994 |
| 0 | 9995 instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{ |
| 9996 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src))); | |
| 9997 ins_cost(150); | |
| 9998 format %{ "MOV$cmp $xcc,$src,$dst" %} | |
| 9999 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); | |
| 10000 ins_pipe(ialu_reg); | |
| 10001 %} | |
| 10002 | |
| 10003 instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{ | |
| 10004 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src))); | |
| 10005 ins_cost(140); | |
| 10006 format %{ "MOV$cmp $xcc,$src,$dst" %} | |
| 10007 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); | |
| 10008 ins_pipe(ialu_imm); | |
| 10009 %} | |
| 10010 | |
| 10011 instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{ | |
| 10012 match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src))); | |
| 10013 ins_cost(150); | |
| 10014 opcode(0x101); | |
| 10015 format %{ "FMOVS$cmp $xcc,$src,$dst" %} | |
| 10016 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) ); | |
| 10017 ins_pipe(int_conditional_float_move); | |
| 10018 %} | |
| 10019 | |
| 10020 instruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{ | |
| 10021 match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src))); | |
| 10022 ins_cost(150); | |
| 10023 opcode(0x102); | |
| 10024 format %{ "FMOVD$cmp $xcc,$src,$dst" %} | |
| 10025 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) ); | |
| 10026 ins_pipe(int_conditional_float_move); | |
| 10027 %} | |
| 10028 | |
| 10029 // ============================================================================ | |
| 10030 // Safepoint Instruction | |
| 10031 instruct safePoint_poll(iRegP poll) %{ | |
| 10032 match(SafePoint poll); | |
| 10033 effect(USE poll); | |
| 10034 | |
| 10035 size(4); | |
| 10036 #ifdef _LP64 | |
| 10037 format %{ "LDX [$poll],R_G0\t! Safepoint: poll for GC" %} | |
| 10038 #else | |
| 10039 format %{ "LDUW [$poll],R_G0\t! Safepoint: poll for GC" %} | |
| 10040 #endif | |
| 10041 ins_encode %{ | |
| 10042 __ relocate(relocInfo::poll_type); | |
| 10043 __ ld_ptr($poll$$Register, 0, G0); | |
| 10044 %} | |
| 10045 ins_pipe(loadPollP); | |
| 10046 %} | |
| 10047 | |
| 10048 // ============================================================================ | |
| 10049 // Call Instructions | |
| 10050 // Call Java Static Instruction | |
| 10051 instruct CallStaticJavaDirect( method meth ) %{ | |
| 10052 match(CallStaticJava); | |
| 1567 | 10053 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke()); |
| 0 | 10054 effect(USE meth); |
| 10055 | |
| 10056 size(8); | |
| 10057 ins_cost(CALL_COST); | |
| 10058 format %{ "CALL,static ; NOP ==> " %} | |
| 10059 ins_encode( Java_Static_Call( meth ), call_epilog ); | |
| 10060 ins_pipe(simple_call); | |
| 10061 %} | |
| 10062 | |
| 1567 | 10063 // Call Java Static Instruction (method handle version) |
| 10064 instruct CallStaticJavaHandle(method meth, l7RegP l7_mh_SP_save) %{ | |
| 10065 match(CallStaticJava); | |
| 10066 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke()); | |
| 10067 effect(USE meth, KILL l7_mh_SP_save); | |
| 10068 | |
| 10069 size(8); | |
| 10070 ins_cost(CALL_COST); | |
| 10071 format %{ "CALL,static/MethodHandle" %} | |
| 10072 ins_encode(preserve_SP, Java_Static_Call(meth), restore_SP, call_epilog); | |
| 10073 ins_pipe(simple_call); | |
| 10074 %} | |
| 10075 | |
| 0 | 10076 // Call Java Dynamic Instruction |
| 10077 instruct CallDynamicJavaDirect( method meth ) %{ | |
| 10078 match(CallDynamicJava); | |
| 10079 effect(USE meth); | |
| 10080 | |
| 10081 ins_cost(CALL_COST); | |
| 10082 format %{ "SET (empty),R_G5\n\t" | |
| 10083 "CALL,dynamic ; NOP ==> " %} | |
| 10084 ins_encode( Java_Dynamic_Call( meth ), call_epilog ); | |
| 10085 ins_pipe(call); | |
| 10086 %} | |
| 10087 | |
| 10088 // Call Runtime Instruction | |
| 10089 instruct CallRuntimeDirect(method meth, l7RegP l7) %{ | |
| 10090 match(CallRuntime); | |
| 10091 effect(USE meth, KILL l7); | |
| 10092 ins_cost(CALL_COST); | |
| 10093 format %{ "CALL,runtime" %} | |
| 10094 ins_encode( Java_To_Runtime( meth ), | |
| 10095 call_epilog, adjust_long_from_native_call ); | |
| 10096 ins_pipe(simple_call); | |
| 10097 %} | |
| 10098 | |
| 10099 // Call runtime without safepoint - same as CallRuntime | |
| 10100 instruct CallLeafDirect(method meth, l7RegP l7) %{ | |
| 10101 match(CallLeaf); | |
| 10102 effect(USE meth, KILL l7); | |
| 10103 ins_cost(CALL_COST); | |
| 10104 format %{ "CALL,runtime leaf" %} | |
| 10105 ins_encode( Java_To_Runtime( meth ), | |
| 10106 call_epilog, | |
| 10107 adjust_long_from_native_call ); | |
| 10108 ins_pipe(simple_call); | |
| 10109 %} | |
| 10110 | |
| 10111 // Call runtime without safepoint - same as CallLeaf | |
| 10112 instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{ | |
| 10113 match(CallLeafNoFP); | |
| 10114 effect(USE meth, KILL l7); | |
| 10115 ins_cost(CALL_COST); | |
| 10116 format %{ "CALL,runtime leaf nofp" %} | |
| 10117 ins_encode( Java_To_Runtime( meth ), | |
| 10118 call_epilog, | |
| 10119 adjust_long_from_native_call ); | |
| 10120 ins_pipe(simple_call); | |
| 10121 %} | |
| 10122 | |
| 10123 // Tail Call; Jump from runtime stub to Java code. | |
| 10124 // Also known as an 'interprocedural jump'. | |
| 10125 // Target of jump will eventually return to caller. | |
| 10126 // TailJump below removes the return address. | |
| 10127 instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{ | |
| 10128 match(TailCall jump_target method_oop ); | |
| 10129 | |
| 10130 ins_cost(CALL_COST); | |
| 10131 format %{ "Jmp $jump_target ; NOP \t! $method_oop holds method oop" %} | |
| 10132 ins_encode(form_jmpl(jump_target)); | |
| 10133 ins_pipe(tail_call); | |
| 10134 %} | |
| 10135 | |
| 10136 | |
| 10137 // Return Instruction | |
| 10138 instruct Ret() %{ | |
| 10139 match(Return); | |
| 10140 | |
| 10141 // The epilogue node did the ret already. | |
| 10142 size(0); | |
| 10143 format %{ "! return" %} | |
| 10144 ins_encode(); | |
| 10145 ins_pipe(empty); | |
| 10146 %} | |
| 10147 | |
| 10148 | |
| 10149 // Tail Jump; remove the return address; jump to target. | |
| 10150 // TailCall above leaves the return address around. | |
| 10151 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2). | |
| 10152 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a | |
| 10153 // "restore" before this instruction (in Epilogue), we need to materialize it | |
| 10154 // in %i0. | |
| 10155 instruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{ | |
| 10156 match( TailJump jump_target ex_oop ); | |
| 10157 ins_cost(CALL_COST); | |
| 10158 format %{ "! discard R_O7\n\t" | |
| 10159 "Jmp $jump_target ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %} | |
| 10160 ins_encode(form_jmpl_set_exception_pc(jump_target)); | |
| 10161 // opcode(Assembler::jmpl_op3, Assembler::arith_op); | |
| 10162 // The hack duplicates the exception oop into G3, so that CreateEx can use it there. | |
| 10163 // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() ); | |
| 10164 ins_pipe(tail_call); | |
| 10165 %} | |
| 10166 | |
| 10167 // Create exception oop: created by stack-crawling runtime code. | |
| 10168 // Created exception is now available to this handler, and is setup | |
| 10169 // just prior to jumping to this handler. No code emitted. | |
| 10170 instruct CreateException( o0RegP ex_oop ) | |
| 10171 %{ | |
| 10172 match(Set ex_oop (CreateEx)); | |
| 10173 ins_cost(0); | |
| 10174 | |
| 10175 size(0); | |
| 10176 // use the following format syntax | |
| 10177 format %{ "! exception oop is in R_O0; no code emitted" %} | |
| 10178 ins_encode(); | |
| 10179 ins_pipe(empty); | |
| 10180 %} | |
| 10181 | |
| 10182 | |
| 10183 // Rethrow exception: | |
| 10184 // The exception oop will come in the first argument position. | |
| 10185 // Then JUMP (not call) to the rethrow stub code. | |
| 10186 instruct RethrowException() | |
| 10187 %{ | |
| 10188 match(Rethrow); | |
| 10189 ins_cost(CALL_COST); | |
| 10190 | |
| 10191 // use the following format syntax | |
| 10192 format %{ "Jmp rethrow_stub" %} | |
| 10193 ins_encode(enc_rethrow); | |
| 10194 ins_pipe(tail_call); | |
| 10195 %} | |
| 10196 | |
| 10197 | |
| 10198 // Die now | |
| 10199 instruct ShouldNotReachHere( ) | |
| 10200 %{ | |
| 10201 match(Halt); | |
| 10202 ins_cost(CALL_COST); | |
| 10203 | |
| 10204 size(4); | |
| 10205 // Use the following format syntax | |
| 10206 format %{ "ILLTRAP ; ShouldNotReachHere" %} | |
| 10207 ins_encode( form2_illtrap() ); | |
| 10208 ins_pipe(tail_call); | |
| 10209 %} | |
| 10210 | |
| 10211 // ============================================================================ | |
| 10212 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass | |
| 10213 // array for an instance of the superklass. Set a hidden internal cache on a | |
| 10214 // hit (cache is checked with exposed code in gen_subtype_check()). Return | |
| 10215 // not zero for a miss or zero for a hit. The encoding ALSO sets flags. | |
| 10216 instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{ | |
| 10217 match(Set index (PartialSubtypeCheck sub super)); | |
| 10218 effect( KILL pcc, KILL o7 ); | |
| 10219 ins_cost(DEFAULT_COST*10); | |
| 10220 format %{ "CALL PartialSubtypeCheck\n\tNOP" %} | |
| 10221 ins_encode( enc_PartialSubtypeCheck() ); | |
| 10222 ins_pipe(partial_subtype_check_pipe); | |
| 10223 %} | |
| 10224 | |
| 10225 instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{ | |
| 10226 match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero)); | |
| 10227 effect( KILL idx, KILL o7 ); | |
| 10228 ins_cost(DEFAULT_COST*10); | |
| 10229 format %{ "CALL PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %} | |
| 10230 ins_encode( enc_PartialSubtypeCheck() ); | |
| 10231 ins_pipe(partial_subtype_check_pipe); | |
| 10232 %} | |
| 10233 | |
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10234 |
| 0 | 10235 // ============================================================================ |
| 10236 // inlined locking and unlocking | |
| 10237 | |
| 10238 instruct cmpFastLock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{ | |
| 10239 match(Set pcc (FastLock object box)); | |
| 10240 | |
| 10241 effect(KILL scratch, TEMP scratch2); | |
| 10242 ins_cost(100); | |
| 10243 | |
| 10244 format %{ "FASTLOCK $object, $box; KILL $scratch, $scratch2, $box" %} | |
| 10245 ins_encode( Fast_Lock(object, box, scratch, scratch2) ); | |
| 10246 ins_pipe(long_memory_op); | |
| 10247 %} | |
| 10248 | |
| 10249 | |
| 10250 instruct cmpFastUnlock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{ | |
| 10251 match(Set pcc (FastUnlock object box)); | |
| 10252 effect(KILL scratch, TEMP scratch2); | |
| 10253 ins_cost(100); | |
| 10254 | |
| 10255 format %{ "FASTUNLOCK $object, $box; KILL $scratch, $scratch2, $box" %} | |
| 10256 ins_encode( Fast_Unlock(object, box, scratch, scratch2) ); | |
| 10257 ins_pipe(long_memory_op); | |
| 10258 %} | |
| 10259 | |
| 10260 // Count and Base registers are fixed because the allocator cannot | |
| 10261 // kill unknown registers. The encodings are generic. | |
| 10262 instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{ | |
| 10263 match(Set dummy (ClearArray cnt base)); | |
| 10264 effect(TEMP temp, KILL ccr); | |
| 10265 ins_cost(300); | |
| 10266 format %{ "MOV $cnt,$temp\n" | |
| 10267 "loop: SUBcc $temp,8,$temp\t! Count down a dword of bytes\n" | |
| 10268 " BRge loop\t\t! Clearing loop\n" | |
| 10269 " STX G0,[$base+$temp]\t! delay slot" %} | |
| 10270 ins_encode( enc_Clear_Array(cnt, base, temp) ); | |
| 10271 ins_pipe(long_memory_op); | |
| 10272 %} | |
| 10273 | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
10274 instruct string_compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
10275 o7RegI tmp, flagsReg ccr) %{ |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
10276 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
10277 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp); |
| 0 | 10278 ins_cost(300); |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
10279 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp" %} |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
10280 ins_encode( enc_String_Compare(str1, str2, cnt1, cnt2, result) ); |
| 0 | 10281 ins_pipe(long_memory_op); |
| 10282 %} | |
| 10283 | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
10284 instruct string_equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
10285 o7RegI tmp, flagsReg ccr) %{ |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
10286 match(Set result (StrEquals (Binary str1 str2) cnt)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
10287 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr); |
| 681 | 10288 ins_cost(300); |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
10289 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp" %} |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
10290 ins_encode( enc_String_Equals(str1, str2, cnt, result) ); |
| 681 | 10291 ins_pipe(long_memory_op); |
| 10292 %} | |
| 10293 | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
10294 instruct array_equals(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
10295 o7RegI tmp2, flagsReg ccr) %{ |
| 681 | 10296 match(Set result (AryEq ary1 ary2)); |
| 10297 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr); | |
| 10298 ins_cost(300); | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
10299 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1,$tmp2" %} |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
951
diff
changeset
|
10300 ins_encode( enc_Array_Equals(ary1, ary2, tmp1, result)); |
| 681 | 10301 ins_pipe(long_memory_op); |
| 10302 %} | |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10303 |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10304 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10305 //---------- Zeros Count Instructions ------------------------------------------ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10306 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10307 instruct countLeadingZerosI(iRegI dst, iRegI src, iRegI tmp, flagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10308 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10309 match(Set dst (CountLeadingZerosI src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10310 effect(TEMP dst, TEMP tmp, KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10311 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10312 // x |= (x >> 1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10313 // x |= (x >> 2); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10314 // x |= (x >> 4); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10315 // x |= (x >> 8); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10316 // x |= (x >> 16); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10317 // return (WORDBITS - popc(x)); |
|
1041
f875b4f472f7
6893554: SPECjvm2008 mpegaudio fails with SecurityException
twisti
parents:
1016
diff
changeset
|
10318 format %{ "SRL $src,1,$tmp\t! count leading zeros (int)\n\t" |
|
f875b4f472f7
6893554: SPECjvm2008 mpegaudio fails with SecurityException
twisti
parents:
1016
diff
changeset
|
10319 "SRL $src,0,$dst\t! 32-bit zero extend\n\t" |
|
f875b4f472f7
6893554: SPECjvm2008 mpegaudio fails with SecurityException
twisti
parents:
1016
diff
changeset
|
10320 "OR $dst,$tmp,$dst\n\t" |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10321 "SRL $dst,2,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10322 "OR $dst,$tmp,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10323 "SRL $dst,4,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10324 "OR $dst,$tmp,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10325 "SRL $dst,8,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10326 "OR $dst,$tmp,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10327 "SRL $dst,16,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10328 "OR $dst,$tmp,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10329 "POPC $dst,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10330 "MOV 32,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10331 "SUB $tmp,$dst,$dst" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10332 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10333 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10334 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10335 Register Rtmp = $tmp$$Register; |
|
1915
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10336 __ srl(Rsrc, 1, Rtmp); |
|
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10337 __ srl(Rsrc, 0, Rdst); |
|
1041
f875b4f472f7
6893554: SPECjvm2008 mpegaudio fails with SecurityException
twisti
parents:
1016
diff
changeset
|
10338 __ or3(Rdst, Rtmp, Rdst); |
|
1915
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10339 __ srl(Rdst, 2, Rtmp); |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10340 __ or3(Rdst, Rtmp, Rdst); |
|
1915
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10341 __ srl(Rdst, 4, Rtmp); |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10342 __ or3(Rdst, Rtmp, Rdst); |
|
1915
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10343 __ srl(Rdst, 8, Rtmp); |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10344 __ or3(Rdst, Rtmp, Rdst); |
|
1915
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10345 __ srl(Rdst, 16, Rtmp); |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10346 __ or3(Rdst, Rtmp, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10347 __ popc(Rdst, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10348 __ mov(BitsPerInt, Rtmp); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10349 __ sub(Rtmp, Rdst, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10350 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10351 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10352 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10353 |
|
1915
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10354 instruct countLeadingZerosL(iRegIsafe dst, iRegL src, iRegL tmp, flagsReg cr) %{ |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10355 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10356 match(Set dst (CountLeadingZerosL src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10357 effect(TEMP dst, TEMP tmp, KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10358 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10359 // x |= (x >> 1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10360 // x |= (x >> 2); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10361 // x |= (x >> 4); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10362 // x |= (x >> 8); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10363 // x |= (x >> 16); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10364 // x |= (x >> 32); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10365 // return (WORDBITS - popc(x)); |
|
1041
f875b4f472f7
6893554: SPECjvm2008 mpegaudio fails with SecurityException
twisti
parents:
1016
diff
changeset
|
10366 format %{ "SRLX $src,1,$tmp\t! count leading zeros (long)\n\t" |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10367 "OR $src,$tmp,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10368 "SRLX $dst,2,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10369 "OR $dst,$tmp,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10370 "SRLX $dst,4,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10371 "OR $dst,$tmp,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10372 "SRLX $dst,8,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10373 "OR $dst,$tmp,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10374 "SRLX $dst,16,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10375 "OR $dst,$tmp,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10376 "SRLX $dst,32,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10377 "OR $dst,$tmp,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10378 "POPC $dst,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10379 "MOV 64,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10380 "SUB $tmp,$dst,$dst" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10381 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10382 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10383 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10384 Register Rtmp = $tmp$$Register; |
|
1915
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10385 __ srlx(Rsrc, 1, Rtmp); |
|
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10386 __ or3( Rsrc, Rtmp, Rdst); |
|
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10387 __ srlx(Rdst, 2, Rtmp); |
|
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10388 __ or3( Rdst, Rtmp, Rdst); |
|
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10389 __ srlx(Rdst, 4, Rtmp); |
|
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10390 __ or3( Rdst, Rtmp, Rdst); |
|
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10391 __ srlx(Rdst, 8, Rtmp); |
|
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10392 __ or3( Rdst, Rtmp, Rdst); |
|
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10393 __ srlx(Rdst, 16, Rtmp); |
|
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10394 __ or3( Rdst, Rtmp, Rdst); |
|
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10395 __ srlx(Rdst, 32, Rtmp); |
|
885e464e1a40
6996240: The BitSet.length method sometimes returns an index+1 value less than that of the highest bit set.
twisti
parents:
1914
diff
changeset
|
10396 __ or3( Rdst, Rtmp, Rdst); |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10397 __ popc(Rdst, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10398 __ mov(BitsPerLong, Rtmp); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10399 __ sub(Rtmp, Rdst, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10400 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10401 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10402 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10403 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10404 instruct countTrailingZerosI(iRegI dst, iRegI src, flagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10405 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10406 match(Set dst (CountTrailingZerosI src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10407 effect(TEMP dst, KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10408 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10409 // return popc(~x & (x - 1)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10410 format %{ "SUB $src,1,$dst\t! count trailing zeros (int)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10411 "ANDN $dst,$src,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10412 "SRL $dst,R_G0,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10413 "POPC $dst,$dst" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10414 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10415 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10416 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10417 __ sub(Rsrc, 1, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10418 __ andn(Rdst, Rsrc, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10419 __ srl(Rdst, G0, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10420 __ popc(Rdst, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10421 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10422 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10423 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10424 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10425 instruct countTrailingZerosL(iRegI dst, iRegL src, flagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10426 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10427 match(Set dst (CountTrailingZerosL src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10428 effect(TEMP dst, KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10429 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10430 // return popc(~x & (x - 1)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10431 format %{ "SUB $src,1,$dst\t! count trailing zeros (long)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10432 "ANDN $dst,$src,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10433 "POPC $dst,$dst" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10434 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10435 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10436 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10437 __ sub(Rsrc, 1, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10438 __ andn(Rdst, Rsrc, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10439 __ popc(Rdst, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10440 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10441 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10442 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10443 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
10444 |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10445 //---------- Population Count Instructions ------------------------------------- |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10446 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10447 instruct popCountI(iRegI dst, iRegI src) %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10448 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10449 match(Set dst (PopCountI src)); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10450 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10451 format %{ "POPC $src, $dst" %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10452 ins_encode %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10453 __ popc($src$$Register, $dst$$Register); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10454 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10455 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10456 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10457 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10458 // Note: Long.bitCount(long) returns an int. |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10459 instruct popCountL(iRegI dst, iRegL src) %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10460 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10461 match(Set dst (PopCountL src)); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10462 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10463 format %{ "POPC $src, $dst" %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10464 ins_encode %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10465 __ popc($src$$Register, $dst$$Register); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10466 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10467 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10468 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10469 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
10470 |
| 0 | 10471 // ============================================================================ |
| 10472 //------------Bytes reverse-------------------------------------------------- | |
| 10473 | |
| 10474 instruct bytes_reverse_int(iRegI dst, stackSlotI src) %{ | |
| 10475 match(Set dst (ReverseBytesI src)); | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10476 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10477 // Op cost is artificially doubled to make sure that load or store |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10478 // instructions are preferred over this one which requires a spill |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10479 // onto a stack slot. |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10480 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10481 format %{ "LDUWA $src, $dst\t!asi=primary_little" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10482 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10483 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10484 __ set($src$$disp + STACK_BIAS, O7); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10485 __ lduwa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10486 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10487 ins_pipe( iload_mem ); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10488 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10489 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10490 instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10491 match(Set dst (ReverseBytesL src)); |
| 0 | 10492 |
| 10493 // Op cost is artificially doubled to make sure that load or store | |
| 10494 // instructions are preferred over this one which requires a spill | |
| 10495 // onto a stack slot. | |
| 10496 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); | |
|
1396
d7f654633cfe
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never
parents:
1367
diff
changeset
|
10497 format %{ "LDXA $src, $dst\t!asi=primary_little" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10498 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10499 ins_encode %{ |
|
d7f654633cfe
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never
parents:
1367
diff
changeset
|
10500 __ set($src$$disp + STACK_BIAS, O7); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10501 __ ldxa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10502 %} |
| 0 | 10503 ins_pipe( iload_mem ); |
| 10504 %} | |
| 10505 | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10506 instruct bytes_reverse_unsigned_short(iRegI dst, stackSlotI src) %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10507 match(Set dst (ReverseBytesUS src)); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10508 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10509 // Op cost is artificially doubled to make sure that load or store |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10510 // instructions are preferred over this one which requires a spill |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10511 // onto a stack slot. |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10512 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10513 format %{ "LDUHA $src, $dst\t!asi=primary_little\n\t" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10514 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10515 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10516 // the value was spilled as an int so bias the load |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10517 __ set($src$$disp + STACK_BIAS + 2, O7); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10518 __ lduha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10519 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10520 ins_pipe( iload_mem ); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10521 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10522 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10523 instruct bytes_reverse_short(iRegI dst, stackSlotI src) %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10524 match(Set dst (ReverseBytesS src)); |
| 0 | 10525 |
| 10526 // Op cost is artificially doubled to make sure that load or store | |
| 10527 // instructions are preferred over this one which requires a spill | |
| 10528 // onto a stack slot. | |
| 10529 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10530 format %{ "LDSHA $src, $dst\t!asi=primary_little\n\t" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10531 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10532 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10533 // the value was spilled as an int so bias the load |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10534 __ set($src$$disp + STACK_BIAS + 2, O7); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10535 __ ldsha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10536 %} |
| 0 | 10537 ins_pipe( iload_mem ); |
| 10538 %} | |
| 10539 | |
| 10540 // Load Integer reversed byte order | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10541 instruct loadI_reversed(iRegI dst, indIndexMemory src) %{ |
| 0 | 10542 match(Set dst (ReverseBytesI (LoadI src))); |
| 10543 | |
| 10544 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10545 size(4); |
| 0 | 10546 format %{ "LDUWA $src, $dst\t!asi=primary_little" %} |
| 10547 | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10548 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10549 __ lduwa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10550 %} |
| 0 | 10551 ins_pipe(iload_mem); |
| 10552 %} | |
| 10553 | |
| 10554 // Load Long - aligned and reversed | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10555 instruct loadL_reversed(iRegL dst, indIndexMemory src) %{ |
| 0 | 10556 match(Set dst (ReverseBytesL (LoadL src))); |
| 10557 | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10558 ins_cost(MEMORY_REF_COST); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10559 size(4); |
| 0 | 10560 format %{ "LDXA $src, $dst\t!asi=primary_little" %} |
| 10561 | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10562 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10563 __ ldxa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10564 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10565 ins_pipe(iload_mem); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10566 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10567 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10568 // Load unsigned short / char reversed byte order |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10569 instruct loadUS_reversed(iRegI dst, indIndexMemory src) %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10570 match(Set dst (ReverseBytesUS (LoadUS src))); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10571 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10572 ins_cost(MEMORY_REF_COST); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10573 size(4); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10574 format %{ "LDUHA $src, $dst\t!asi=primary_little" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10575 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10576 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10577 __ lduha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10578 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10579 ins_pipe(iload_mem); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10580 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10581 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10582 // Load short reversed byte order |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10583 instruct loadS_reversed(iRegI dst, indIndexMemory src) %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10584 match(Set dst (ReverseBytesS (LoadS src))); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10585 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10586 ins_cost(MEMORY_REF_COST); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10587 size(4); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10588 format %{ "LDSHA $src, $dst\t!asi=primary_little" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10589 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10590 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10591 __ ldsha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10592 %} |
| 0 | 10593 ins_pipe(iload_mem); |
| 10594 %} | |
| 10595 | |
| 10596 // Store Integer reversed byte order | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10597 instruct storeI_reversed(indIndexMemory dst, iRegI src) %{ |
| 0 | 10598 match(Set dst (StoreI dst (ReverseBytesI src))); |
| 10599 | |
| 10600 ins_cost(MEMORY_REF_COST); | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10601 size(4); |
| 0 | 10602 format %{ "STWA $src, $dst\t!asi=primary_little" %} |
| 10603 | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10604 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10605 __ stwa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10606 %} |
| 0 | 10607 ins_pipe(istore_mem_reg); |
| 10608 %} | |
| 10609 | |
| 10610 // Store Long reversed byte order | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10611 instruct storeL_reversed(indIndexMemory dst, iRegL src) %{ |
| 0 | 10612 match(Set dst (StoreL dst (ReverseBytesL src))); |
| 10613 | |
| 10614 ins_cost(MEMORY_REF_COST); | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10615 size(4); |
| 0 | 10616 format %{ "STXA $src, $dst\t!asi=primary_little" %} |
| 10617 | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10618 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10619 __ stxa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10620 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10621 ins_pipe(istore_mem_reg); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10622 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10623 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10624 // Store unsighed short/char reversed byte order |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10625 instruct storeUS_reversed(indIndexMemory dst, iRegI src) %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10626 match(Set dst (StoreC dst (ReverseBytesUS src))); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10627 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10628 ins_cost(MEMORY_REF_COST); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10629 size(4); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10630 format %{ "STHA $src, $dst\t!asi=primary_little" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10631 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10632 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10633 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10634 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10635 ins_pipe(istore_mem_reg); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10636 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10637 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10638 // Store short reversed byte order |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10639 instruct storeS_reversed(indIndexMemory dst, iRegI src) %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10640 match(Set dst (StoreC dst (ReverseBytesS src))); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10641 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10642 ins_cost(MEMORY_REF_COST); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10643 size(4); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10644 format %{ "STHA $src, $dst\t!asi=primary_little" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10645 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10646 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10647 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
10648 %} |
| 0 | 10649 ins_pipe(istore_mem_reg); |
| 10650 %} | |
| 10651 | |
| 10652 //----------PEEPHOLE RULES----------------------------------------------------- | |
| 10653 // These must follow all instruction definitions as they use the names | |
| 10654 // defined in the instructions definitions. | |
| 10655 // | |
| 605 | 10656 // peepmatch ( root_instr_name [preceding_instruction]* ); |
| 0 | 10657 // |
| 10658 // peepconstraint %{ | |
| 10659 // (instruction_number.operand_name relational_op instruction_number.operand_name | |
| 10660 // [, ...] ); | |
| 10661 // // instruction numbers are zero-based using left to right order in peepmatch | |
| 10662 // | |
| 10663 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) ); | |
| 10664 // // provide an instruction_number.operand_name for each operand that appears | |
| 10665 // // in the replacement instruction's match rule | |
| 10666 // | |
| 10667 // ---------VM FLAGS--------------------------------------------------------- | |
| 10668 // | |
| 10669 // All peephole optimizations can be turned off using -XX:-OptoPeephole | |
| 10670 // | |
| 10671 // Each peephole rule is given an identifying number starting with zero and | |
| 10672 // increasing by one in the order seen by the parser. An individual peephole | |
| 10673 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=# | |
| 10674 // on the command-line. | |
| 10675 // | |
| 10676 // ---------CURRENT LIMITATIONS---------------------------------------------- | |
| 10677 // | |
| 10678 // Only match adjacent instructions in same basic block | |
| 10679 // Only equality constraints | |
| 10680 // Only constraints between operands, not (0.dest_reg == EAX_enc) | |
| 10681 // Only one replacement instruction | |
| 10682 // | |
| 10683 // ---------EXAMPLE---------------------------------------------------------- | |
| 10684 // | |
| 10685 // // pertinent parts of existing instructions in architecture description | |
| 10686 // instruct movI(eRegI dst, eRegI src) %{ | |
| 10687 // match(Set dst (CopyI src)); | |
| 10688 // %} | |
| 10689 // | |
| 10690 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{ | |
| 10691 // match(Set dst (AddI dst src)); | |
| 10692 // effect(KILL cr); | |
| 10693 // %} | |
| 10694 // | |
| 10695 // // Change (inc mov) to lea | |
| 10696 // peephole %{ | |
| 10697 // // increment preceeded by register-register move | |
| 10698 // peepmatch ( incI_eReg movI ); | |
| 10699 // // require that the destination register of the increment | |
| 10700 // // match the destination register of the move | |
| 10701 // peepconstraint ( 0.dst == 1.dst ); | |
| 10702 // // construct a replacement instruction that sets | |
| 10703 // // the destination to ( move's source register + one ) | |
| 10704 // peepreplace ( incI_eReg_immI1( 0.dst 1.src 0.src ) ); | |
| 10705 // %} | |
| 10706 // | |
| 10707 | |
| 10708 // // Change load of spilled value to only a spill | |
| 10709 // instruct storeI(memory mem, eRegI src) %{ | |
| 10710 // match(Set mem (StoreI mem src)); | |
| 10711 // %} | |
| 10712 // | |
| 10713 // instruct loadI(eRegI dst, memory mem) %{ | |
| 10714 // match(Set dst (LoadI mem)); | |
| 10715 // %} | |
| 10716 // | |
| 10717 // peephole %{ | |
| 10718 // peepmatch ( loadI storeI ); | |
| 10719 // peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem ); | |
| 10720 // peepreplace ( storeI( 1.mem 1.mem 1.src ) ); | |
| 10721 // %} | |
| 10722 | |
| 10723 //----------SMARTSPILL RULES--------------------------------------------------- | |
| 10724 // These must follow all instruction definitions as they use the names | |
| 10725 // defined in the instructions definitions. | |
| 10726 // | |
| 10727 // SPARC will probably not have any of these rules due to RISC instruction set. | |
| 10728 | |
| 10729 //----------PIPELINE----------------------------------------------------------- | |
| 10730 // Rules which define the behavior of the target architectures pipeline. |