Mercurial > hg > graal-jvmci-8
annotate src/share/vm/c1/c1_LIRAssembler.cpp @ 6616:7a302948f5a4
7192167: JSR 292: C1 has old broken code which needs to be removed
Reviewed-by: kvn, roland, jrose
author | twisti |
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date | Tue, 21 Aug 2012 10:48:50 -0700 |
parents | 6759698e3140 |
children | c38f13903fdf da91efe96a93 |
rev | line source |
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0 | 1 /* |
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2 * Copyright (c) 2000, 2011, Oracle and/or its affiliates. All rights reserved. |
0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
4 * | |
5 * This code is free software; you can redistribute it and/or modify it | |
6 * under the terms of the GNU General Public License version 2 only, as | |
7 * published by the Free Software Foundation. | |
8 * | |
9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 * version 2 for more details (a copy is included in the LICENSE file that | |
13 * accompanied this code). | |
14 * | |
15 * You should have received a copy of the GNU General Public License version | |
16 * 2 along with this work; if not, write to the Free Software Foundation, | |
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
18 * | |
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
0 | 22 * |
23 */ | |
24 | |
1972 | 25 #include "precompiled.hpp" |
26 #include "c1/c1_Compilation.hpp" | |
27 #include "c1/c1_Instruction.hpp" | |
28 #include "c1/c1_InstructionPrinter.hpp" | |
29 #include "c1/c1_LIRAssembler.hpp" | |
30 #include "c1/c1_MacroAssembler.hpp" | |
31 #include "c1/c1_ValueStack.hpp" | |
32 #include "ci/ciInstance.hpp" | |
33 #ifdef TARGET_ARCH_x86 | |
34 # include "nativeInst_x86.hpp" | |
35 # include "vmreg_x86.inline.hpp" | |
36 #endif | |
37 #ifdef TARGET_ARCH_sparc | |
38 # include "nativeInst_sparc.hpp" | |
39 # include "vmreg_sparc.inline.hpp" | |
40 #endif | |
41 #ifdef TARGET_ARCH_zero | |
42 # include "nativeInst_zero.hpp" | |
43 # include "vmreg_zero.inline.hpp" | |
44 #endif | |
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45 #ifdef TARGET_ARCH_arm |
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46 # include "nativeInst_arm.hpp" |
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47 # include "vmreg_arm.inline.hpp" |
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48 #endif |
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49 #ifdef TARGET_ARCH_ppc |
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50 # include "nativeInst_ppc.hpp" |
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51 # include "vmreg_ppc.inline.hpp" |
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52 #endif |
0 | 53 |
54 | |
55 void LIR_Assembler::patching_epilog(PatchingStub* patch, LIR_PatchCode patch_code, Register obj, CodeEmitInfo* info) { | |
56 // we must have enough patching space so that call can be inserted | |
57 while ((intx) _masm->pc() - (intx) patch->pc_start() < NativeCall::instruction_size) { | |
58 _masm->nop(); | |
59 } | |
60 patch->install(_masm, patch_code, obj, info); | |
61 append_patching_stub(patch); | |
62 | |
63 #ifdef ASSERT | |
1819 | 64 Bytecodes::Code code = info->scope()->method()->java_code_at_bci(info->stack()->bci()); |
0 | 65 if (patch->id() == PatchingStub::access_field_id) { |
66 switch (code) { | |
67 case Bytecodes::_putstatic: | |
68 case Bytecodes::_getstatic: | |
69 case Bytecodes::_putfield: | |
70 case Bytecodes::_getfield: | |
71 break; | |
72 default: | |
73 ShouldNotReachHere(); | |
74 } | |
75 } else if (patch->id() == PatchingStub::load_klass_id) { | |
76 switch (code) { | |
77 case Bytecodes::_putstatic: | |
78 case Bytecodes::_getstatic: | |
79 case Bytecodes::_new: | |
80 case Bytecodes::_anewarray: | |
81 case Bytecodes::_multianewarray: | |
82 case Bytecodes::_instanceof: | |
83 case Bytecodes::_checkcast: | |
84 case Bytecodes::_ldc: | |
85 case Bytecodes::_ldc_w: | |
86 break; | |
87 default: | |
88 ShouldNotReachHere(); | |
89 } | |
90 } else { | |
91 ShouldNotReachHere(); | |
92 } | |
93 #endif | |
94 } | |
95 | |
96 | |
97 //--------------------------------------------------------------- | |
98 | |
99 | |
100 LIR_Assembler::LIR_Assembler(Compilation* c): | |
101 _compilation(c) | |
102 , _masm(c->masm()) | |
342 | 103 , _bs(Universe::heap()->barrier_set()) |
0 | 104 , _frame_map(c->frame_map()) |
105 , _current_block(NULL) | |
106 , _pending_non_safepoint(NULL) | |
107 , _pending_non_safepoint_offset(0) | |
108 { | |
109 _slow_case_stubs = new CodeStubList(); | |
110 } | |
111 | |
112 | |
113 LIR_Assembler::~LIR_Assembler() { | |
114 } | |
115 | |
116 | |
117 void LIR_Assembler::append_patching_stub(PatchingStub* stub) { | |
118 _slow_case_stubs->append(stub); | |
119 } | |
120 | |
121 | |
122 void LIR_Assembler::check_codespace() { | |
123 CodeSection* cs = _masm->code_section(); | |
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124 if (cs->remaining() < (int)(NOT_LP64(1*K)LP64_ONLY(2*K))) { |
0 | 125 BAILOUT("CodeBuffer overflow"); |
126 } | |
127 } | |
128 | |
129 | |
130 void LIR_Assembler::emit_code_stub(CodeStub* stub) { | |
131 _slow_case_stubs->append(stub); | |
132 } | |
133 | |
134 void LIR_Assembler::emit_stubs(CodeStubList* stub_list) { | |
135 for (int m = 0; m < stub_list->length(); m++) { | |
136 CodeStub* s = (*stub_list)[m]; | |
137 | |
138 check_codespace(); | |
139 CHECK_BAILOUT(); | |
140 | |
141 #ifndef PRODUCT | |
142 if (CommentedAssembly) { | |
143 stringStream st; | |
144 s->print_name(&st); | |
145 st.print(" slow case"); | |
146 _masm->block_comment(st.as_string()); | |
147 } | |
148 #endif | |
149 s->emit_code(this); | |
150 #ifdef ASSERT | |
151 s->assert_no_unbound_labels(); | |
152 #endif | |
153 } | |
154 } | |
155 | |
156 | |
157 void LIR_Assembler::emit_slow_case_stubs() { | |
158 emit_stubs(_slow_case_stubs); | |
159 } | |
160 | |
161 | |
162 bool LIR_Assembler::needs_icache(ciMethod* method) const { | |
163 return !method->is_static(); | |
164 } | |
165 | |
166 | |
167 int LIR_Assembler::code_offset() const { | |
168 return _masm->offset(); | |
169 } | |
170 | |
171 | |
172 address LIR_Assembler::pc() const { | |
173 return _masm->pc(); | |
174 } | |
175 | |
176 | |
177 void LIR_Assembler::emit_exception_entries(ExceptionInfoList* info_list) { | |
178 for (int i = 0; i < info_list->length(); i++) { | |
179 XHandlers* handlers = info_list->at(i)->exception_handlers(); | |
180 | |
181 for (int j = 0; j < handlers->length(); j++) { | |
182 XHandler* handler = handlers->handler_at(j); | |
183 assert(handler->lir_op_id() != -1, "handler not processed by LinearScan"); | |
184 assert(handler->entry_code() == NULL || | |
185 handler->entry_code()->instructions_list()->last()->code() == lir_branch || | |
186 handler->entry_code()->instructions_list()->last()->code() == lir_delay_slot, "last operation must be branch"); | |
187 | |
188 if (handler->entry_pco() == -1) { | |
189 // entry code not emitted yet | |
190 if (handler->entry_code() != NULL && handler->entry_code()->instructions_list()->length() > 1) { | |
191 handler->set_entry_pco(code_offset()); | |
192 if (CommentedAssembly) { | |
193 _masm->block_comment("Exception adapter block"); | |
194 } | |
195 emit_lir_list(handler->entry_code()); | |
196 } else { | |
197 handler->set_entry_pco(handler->entry_block()->exception_handler_pco()); | |
198 } | |
199 | |
200 assert(handler->entry_pco() != -1, "must be set now"); | |
201 } | |
202 } | |
203 } | |
204 } | |
205 | |
206 | |
207 void LIR_Assembler::emit_code(BlockList* hir) { | |
208 if (PrintLIR) { | |
209 print_LIR(hir); | |
210 } | |
211 | |
212 int n = hir->length(); | |
213 for (int i = 0; i < n; i++) { | |
214 emit_block(hir->at(i)); | |
215 CHECK_BAILOUT(); | |
216 } | |
217 | |
218 flush_debug_info(code_offset()); | |
219 | |
220 DEBUG_ONLY(check_no_unbound_labels()); | |
221 } | |
222 | |
223 | |
224 void LIR_Assembler::emit_block(BlockBegin* block) { | |
225 if (block->is_set(BlockBegin::backward_branch_target_flag)) { | |
226 align_backward_branch_target(); | |
227 } | |
228 | |
229 // if this block is the start of an exception handler, record the | |
230 // PC offset of the first instruction for later construction of | |
231 // the ExceptionHandlerTable | |
232 if (block->is_set(BlockBegin::exception_entry_flag)) { | |
233 block->set_exception_handler_pco(code_offset()); | |
234 } | |
235 | |
236 #ifndef PRODUCT | |
237 if (PrintLIRWithAssembly) { | |
238 // don't print Phi's | |
239 InstructionPrinter ip(false); | |
240 block->print(ip); | |
241 } | |
242 #endif /* PRODUCT */ | |
243 | |
244 assert(block->lir() != NULL, "must have LIR"); | |
304 | 245 X86_ONLY(assert(_masm->rsp_offset() == 0, "frame size should be fixed")); |
0 | 246 |
247 #ifndef PRODUCT | |
248 if (CommentedAssembly) { | |
249 stringStream st; | |
1819 | 250 st.print_cr(" block B%d [%d, %d]", block->block_id(), block->bci(), block->end()->printable_bci()); |
0 | 251 _masm->block_comment(st.as_string()); |
252 } | |
253 #endif | |
254 | |
255 emit_lir_list(block->lir()); | |
256 | |
304 | 257 X86_ONLY(assert(_masm->rsp_offset() == 0, "frame size should be fixed")); |
0 | 258 } |
259 | |
260 | |
261 void LIR_Assembler::emit_lir_list(LIR_List* list) { | |
262 peephole(list); | |
263 | |
264 int n = list->length(); | |
265 for (int i = 0; i < n; i++) { | |
266 LIR_Op* op = list->at(i); | |
267 | |
268 check_codespace(); | |
269 CHECK_BAILOUT(); | |
270 | |
271 #ifndef PRODUCT | |
272 if (CommentedAssembly) { | |
273 // Don't record out every op since that's too verbose. Print | |
274 // branches since they include block and stub names. Also print | |
275 // patching moves since they generate funny looking code. | |
276 if (op->code() == lir_branch || | |
277 (op->code() == lir_move && op->as_Op1()->patch_code() != lir_patch_none)) { | |
278 stringStream st; | |
279 op->print_on(&st); | |
280 _masm->block_comment(st.as_string()); | |
281 } | |
282 } | |
283 if (PrintLIRWithAssembly) { | |
284 // print out the LIR operation followed by the resulting assembly | |
285 list->at(i)->print(); tty->cr(); | |
286 } | |
287 #endif /* PRODUCT */ | |
288 | |
289 op->emit_code(this); | |
290 | |
291 if (compilation()->debug_info_recorder()->recording_non_safepoints()) { | |
292 process_debug_info(op); | |
293 } | |
294 | |
295 #ifndef PRODUCT | |
296 if (PrintLIRWithAssembly) { | |
297 _masm->code()->decode(); | |
298 } | |
299 #endif /* PRODUCT */ | |
300 } | |
301 } | |
302 | |
303 #ifdef ASSERT | |
304 void LIR_Assembler::check_no_unbound_labels() { | |
305 CHECK_BAILOUT(); | |
306 | |
307 for (int i = 0; i < _branch_target_blocks.length() - 1; i++) { | |
308 if (!_branch_target_blocks.at(i)->label()->is_bound()) { | |
309 tty->print_cr("label of block B%d is not bound", _branch_target_blocks.at(i)->block_id()); | |
310 assert(false, "unbound label"); | |
311 } | |
312 } | |
313 } | |
314 #endif | |
315 | |
316 //----------------------------------debug info-------------------------------- | |
317 | |
318 | |
319 void LIR_Assembler::add_debug_info_for_branch(CodeEmitInfo* info) { | |
320 _masm->code_section()->relocate(pc(), relocInfo::poll_type); | |
321 int pc_offset = code_offset(); | |
322 flush_debug_info(pc_offset); | |
323 info->record_debug_info(compilation()->debug_info_recorder(), pc_offset); | |
324 if (info->exception_handlers() != NULL) { | |
325 compilation()->add_exception_handlers_for_pco(pc_offset, info->exception_handlers()); | |
326 } | |
327 } | |
328 | |
329 | |
1564 | 330 void LIR_Assembler::add_call_info(int pc_offset, CodeEmitInfo* cinfo) { |
0 | 331 flush_debug_info(pc_offset); |
1564 | 332 cinfo->record_debug_info(compilation()->debug_info_recorder(), pc_offset); |
0 | 333 if (cinfo->exception_handlers() != NULL) { |
334 compilation()->add_exception_handlers_for_pco(pc_offset, cinfo->exception_handlers()); | |
335 } | |
336 } | |
337 | |
338 static ValueStack* debug_info(Instruction* ins) { | |
339 StateSplit* ss = ins->as_StateSplit(); | |
340 if (ss != NULL) return ss->state(); | |
1819 | 341 return ins->state_before(); |
0 | 342 } |
343 | |
344 void LIR_Assembler::process_debug_info(LIR_Op* op) { | |
345 Instruction* src = op->source(); | |
346 if (src == NULL) return; | |
347 int pc_offset = code_offset(); | |
348 if (_pending_non_safepoint == src) { | |
349 _pending_non_safepoint_offset = pc_offset; | |
350 return; | |
351 } | |
352 ValueStack* vstack = debug_info(src); | |
353 if (vstack == NULL) return; | |
354 if (_pending_non_safepoint != NULL) { | |
355 // Got some old debug info. Get rid of it. | |
1819 | 356 if (debug_info(_pending_non_safepoint) == vstack) { |
0 | 357 _pending_non_safepoint_offset = pc_offset; |
358 return; | |
359 } | |
360 if (_pending_non_safepoint_offset < pc_offset) { | |
361 record_non_safepoint_debug_info(); | |
362 } | |
363 _pending_non_safepoint = NULL; | |
364 } | |
365 // Remember the debug info. | |
366 if (pc_offset > compilation()->debug_info_recorder()->last_pc_offset()) { | |
367 _pending_non_safepoint = src; | |
368 _pending_non_safepoint_offset = pc_offset; | |
369 } | |
370 } | |
371 | |
372 // Index caller states in s, where 0 is the oldest, 1 its callee, etc. | |
373 // Return NULL if n is too large. | |
374 // Returns the caller_bci for the next-younger state, also. | |
375 static ValueStack* nth_oldest(ValueStack* s, int n, int& bci_result) { | |
376 ValueStack* t = s; | |
377 for (int i = 0; i < n; i++) { | |
378 if (t == NULL) break; | |
379 t = t->caller_state(); | |
380 } | |
381 if (t == NULL) return NULL; | |
382 for (;;) { | |
383 ValueStack* tc = t->caller_state(); | |
384 if (tc == NULL) return s; | |
385 t = tc; | |
1819 | 386 bci_result = tc->bci(); |
0 | 387 s = s->caller_state(); |
388 } | |
389 } | |
390 | |
391 void LIR_Assembler::record_non_safepoint_debug_info() { | |
392 int pc_offset = _pending_non_safepoint_offset; | |
393 ValueStack* vstack = debug_info(_pending_non_safepoint); | |
1819 | 394 int bci = vstack->bci(); |
0 | 395 |
396 DebugInformationRecorder* debug_info = compilation()->debug_info_recorder(); | |
397 assert(debug_info->recording_non_safepoints(), "sanity"); | |
398 | |
399 debug_info->add_non_safepoint(pc_offset); | |
400 | |
401 // Visit scopes from oldest to youngest. | |
402 for (int n = 0; ; n++) { | |
403 int s_bci = bci; | |
404 ValueStack* s = nth_oldest(vstack, n, s_bci); | |
405 if (s == NULL) break; | |
406 IRScope* scope = s->scope(); | |
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407 //Always pass false for reexecute since these ScopeDescs are never used for deopt |
1819 | 408 debug_info->describe_scope(pc_offset, scope->method(), s->bci(), false/*reexecute*/); |
0 | 409 } |
410 | |
411 debug_info->end_non_safepoint(pc_offset); | |
412 } | |
413 | |
414 | |
415 void LIR_Assembler::add_debug_info_for_null_check_here(CodeEmitInfo* cinfo) { | |
416 add_debug_info_for_null_check(code_offset(), cinfo); | |
417 } | |
418 | |
419 void LIR_Assembler::add_debug_info_for_null_check(int pc_offset, CodeEmitInfo* cinfo) { | |
420 ImplicitNullCheckStub* stub = new ImplicitNullCheckStub(pc_offset, cinfo); | |
421 emit_code_stub(stub); | |
422 } | |
423 | |
424 void LIR_Assembler::add_debug_info_for_div0_here(CodeEmitInfo* info) { | |
425 add_debug_info_for_div0(code_offset(), info); | |
426 } | |
427 | |
428 void LIR_Assembler::add_debug_info_for_div0(int pc_offset, CodeEmitInfo* cinfo) { | |
429 DivByZeroStub* stub = new DivByZeroStub(pc_offset, cinfo); | |
430 emit_code_stub(stub); | |
431 } | |
432 | |
433 void LIR_Assembler::emit_rtcall(LIR_OpRTCall* op) { | |
434 rt_call(op->result_opr(), op->addr(), op->arguments(), op->tmp(), op->info()); | |
435 } | |
436 | |
437 | |
438 void LIR_Assembler::emit_call(LIR_OpJavaCall* op) { | |
439 verify_oop_map(op->info()); | |
440 | |
441 if (os::is_MP()) { | |
442 // must align calls sites, otherwise they can't be updated atomically on MP hardware | |
443 align_call(op->code()); | |
444 } | |
445 | |
446 // emit the static call stub stuff out of line | |
447 emit_static_call_stub(); | |
448 | |
449 switch (op->code()) { | |
450 case lir_static_call: | |
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451 case lir_dynamic_call: |
1295 | 452 call(op, relocInfo::static_call_type); |
0 | 453 break; |
454 case lir_optvirtual_call: | |
1295 | 455 call(op, relocInfo::opt_virtual_call_type); |
0 | 456 break; |
457 case lir_icvirtual_call: | |
1295 | 458 ic_call(op); |
0 | 459 break; |
460 case lir_virtual_call: | |
1295 | 461 vtable_call(op); |
0 | 462 break; |
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463 default: |
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464 fatal(err_msg_res("unexpected op code: %s", op->name())); |
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465 break; |
0 | 466 } |
1295 | 467 |
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468 // JSR 292 |
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469 // Record if this method has MethodHandle invokes. |
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470 if (op->is_method_handle_invoke()) { |
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471 compilation()->set_has_method_handle_invokes(true); |
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472 } |
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473 |
304 | 474 #if defined(X86) && defined(TIERED) |
0 | 475 // C2 leave fpu stack dirty clean it |
476 if (UseSSE < 2) { | |
477 int i; | |
478 for ( i = 1; i <= 7 ; i++ ) { | |
479 ffree(i); | |
480 } | |
481 if (!op->result_opr()->is_float_kind()) { | |
482 ffree(0); | |
483 } | |
484 } | |
304 | 485 #endif // X86 && TIERED |
0 | 486 } |
487 | |
488 | |
489 void LIR_Assembler::emit_opLabel(LIR_OpLabel* op) { | |
490 _masm->bind (*(op->label())); | |
491 } | |
492 | |
493 | |
494 void LIR_Assembler::emit_op1(LIR_Op1* op) { | |
495 switch (op->code()) { | |
496 case lir_move: | |
497 if (op->move_kind() == lir_move_volatile) { | |
498 assert(op->patch_code() == lir_patch_none, "can't patch volatiles"); | |
499 volatile_move_op(op->in_opr(), op->result_opr(), op->type(), op->info()); | |
500 } else { | |
501 move_op(op->in_opr(), op->result_opr(), op->type(), | |
2002 | 502 op->patch_code(), op->info(), op->pop_fpu_stack(), |
503 op->move_kind() == lir_move_unaligned, | |
504 op->move_kind() == lir_move_wide); | |
0 | 505 } |
506 break; | |
507 | |
508 case lir_prefetchr: | |
509 prefetchr(op->in_opr()); | |
510 break; | |
511 | |
512 case lir_prefetchw: | |
513 prefetchw(op->in_opr()); | |
514 break; | |
515 | |
516 case lir_roundfp: { | |
517 LIR_OpRoundFP* round_op = op->as_OpRoundFP(); | |
518 roundfp_op(round_op->in_opr(), round_op->tmp(), round_op->result_opr(), round_op->pop_fpu_stack()); | |
519 break; | |
520 } | |
521 | |
522 case lir_return: | |
523 return_op(op->in_opr()); | |
524 break; | |
525 | |
526 case lir_safepoint: | |
527 if (compilation()->debug_info_recorder()->last_pc_offset() == code_offset()) { | |
528 _masm->nop(); | |
529 } | |
530 safepoint_poll(op->in_opr(), op->info()); | |
531 break; | |
532 | |
533 case lir_fxch: | |
534 fxch(op->in_opr()->as_jint()); | |
535 break; | |
536 | |
537 case lir_fld: | |
538 fld(op->in_opr()->as_jint()); | |
539 break; | |
540 | |
541 case lir_ffree: | |
542 ffree(op->in_opr()->as_jint()); | |
543 break; | |
544 | |
545 case lir_branch: | |
546 break; | |
547 | |
548 case lir_push: | |
549 push(op->in_opr()); | |
550 break; | |
551 | |
552 case lir_pop: | |
553 pop(op->in_opr()); | |
554 break; | |
555 | |
556 case lir_neg: | |
557 negate(op->in_opr(), op->result_opr()); | |
558 break; | |
559 | |
560 case lir_leal: | |
561 leal(op->in_opr(), op->result_opr()); | |
562 break; | |
563 | |
564 case lir_null_check: | |
565 if (GenerateCompilerNullChecks) { | |
566 add_debug_info_for_null_check_here(op->info()); | |
567 | |
568 if (op->in_opr()->is_single_cpu()) { | |
569 _masm->null_check(op->in_opr()->as_register()); | |
570 } else { | |
571 Unimplemented(); | |
572 } | |
573 } | |
574 break; | |
575 | |
576 case lir_monaddr: | |
577 monitor_address(op->in_opr()->as_constant_ptr()->as_jint(), op->result_opr()); | |
578 break; | |
579 | |
1783 | 580 #ifdef SPARC |
581 case lir_pack64: | |
582 pack64(op->in_opr(), op->result_opr()); | |
583 break; | |
584 | |
585 case lir_unpack64: | |
586 unpack64(op->in_opr(), op->result_opr()); | |
587 break; | |
588 #endif | |
589 | |
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590 case lir_unwind: |
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591 unwind_op(op->in_opr()); |
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592 break; |
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593 |
0 | 594 default: |
595 Unimplemented(); | |
596 break; | |
597 } | |
598 } | |
599 | |
600 | |
601 void LIR_Assembler::emit_op0(LIR_Op0* op) { | |
602 switch (op->code()) { | |
603 case lir_word_align: { | |
604 while (code_offset() % BytesPerWord != 0) { | |
605 _masm->nop(); | |
606 } | |
607 break; | |
608 } | |
609 | |
610 case lir_nop: | |
611 assert(op->info() == NULL, "not supported"); | |
612 _masm->nop(); | |
613 break; | |
614 | |
615 case lir_label: | |
616 Unimplemented(); | |
617 break; | |
618 | |
619 case lir_build_frame: | |
620 build_frame(); | |
621 break; | |
622 | |
623 case lir_std_entry: | |
624 // init offsets | |
625 offsets()->set_value(CodeOffsets::OSR_Entry, _masm->offset()); | |
626 _masm->align(CodeEntryAlignment); | |
627 if (needs_icache(compilation()->method())) { | |
628 check_icache(); | |
629 } | |
630 offsets()->set_value(CodeOffsets::Verified_Entry, _masm->offset()); | |
631 _masm->verified_entry(); | |
632 build_frame(); | |
633 offsets()->set_value(CodeOffsets::Frame_Complete, _masm->offset()); | |
634 break; | |
635 | |
636 case lir_osr_entry: | |
637 offsets()->set_value(CodeOffsets::OSR_Entry, _masm->offset()); | |
638 osr_entry(); | |
639 break; | |
640 | |
641 case lir_24bit_FPU: | |
642 set_24bit_FPU(); | |
643 break; | |
644 | |
645 case lir_reset_FPU: | |
646 reset_FPU(); | |
647 break; | |
648 | |
649 case lir_breakpoint: | |
650 breakpoint(); | |
651 break; | |
652 | |
653 case lir_fpop_raw: | |
654 fpop(); | |
655 break; | |
656 | |
657 case lir_membar: | |
658 membar(); | |
659 break; | |
660 | |
661 case lir_membar_acquire: | |
662 membar_acquire(); | |
663 break; | |
664 | |
665 case lir_membar_release: | |
666 membar_release(); | |
667 break; | |
668 | |
4966
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669 case lir_membar_loadload: |
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670 membar_loadload(); |
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671 break; |
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672 |
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673 case lir_membar_storestore: |
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674 membar_storestore(); |
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675 break; |
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676 |
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677 case lir_membar_loadstore: |
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678 membar_loadstore(); |
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679 break; |
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680 |
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681 case lir_membar_storeload: |
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682 membar_storeload(); |
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683 break; |
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684 |
0 | 685 case lir_get_thread: |
686 get_thread(op->result_opr()); | |
687 break; | |
688 | |
689 default: | |
690 ShouldNotReachHere(); | |
691 break; | |
692 } | |
693 } | |
694 | |
695 | |
696 void LIR_Assembler::emit_op2(LIR_Op2* op) { | |
697 switch (op->code()) { | |
698 case lir_cmp: | |
699 if (op->info() != NULL) { | |
700 assert(op->in_opr1()->is_address() || op->in_opr2()->is_address(), | |
701 "shouldn't be codeemitinfo for non-address operands"); | |
702 add_debug_info_for_null_check_here(op->info()); // exception possible | |
703 } | |
704 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op); | |
705 break; | |
706 | |
707 case lir_cmp_l2i: | |
708 case lir_cmp_fd2i: | |
709 case lir_ucmp_fd2i: | |
710 comp_fl2i(op->code(), op->in_opr1(), op->in_opr2(), op->result_opr(), op); | |
711 break; | |
712 | |
713 case lir_cmove: | |
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714 cmove(op->condition(), op->in_opr1(), op->in_opr2(), op->result_opr(), op->type()); |
0 | 715 break; |
716 | |
717 case lir_shl: | |
718 case lir_shr: | |
719 case lir_ushr: | |
720 if (op->in_opr2()->is_constant()) { | |
721 shift_op(op->code(), op->in_opr1(), op->in_opr2()->as_constant_ptr()->as_jint(), op->result_opr()); | |
722 } else { | |
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723 shift_op(op->code(), op->in_opr1(), op->in_opr2(), op->result_opr(), op->tmp1_opr()); |
0 | 724 } |
725 break; | |
726 | |
727 case lir_add: | |
728 case lir_sub: | |
729 case lir_mul: | |
730 case lir_mul_strictfp: | |
731 case lir_div: | |
732 case lir_div_strictfp: | |
733 case lir_rem: | |
734 assert(op->fpu_pop_count() < 2, ""); | |
735 arith_op( | |
736 op->code(), | |
737 op->in_opr1(), | |
738 op->in_opr2(), | |
739 op->result_opr(), | |
740 op->info(), | |
741 op->fpu_pop_count() == 1); | |
742 break; | |
743 | |
744 case lir_abs: | |
745 case lir_sqrt: | |
746 case lir_sin: | |
747 case lir_tan: | |
748 case lir_cos: | |
749 case lir_log: | |
750 case lir_log10: | |
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751 case lir_exp: |
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752 case lir_pow: |
0 | 753 intrinsic_op(op->code(), op->in_opr1(), op->in_opr2(), op->result_opr(), op); |
754 break; | |
755 | |
756 case lir_logic_and: | |
757 case lir_logic_or: | |
758 case lir_logic_xor: | |
759 logic_op( | |
760 op->code(), | |
761 op->in_opr1(), | |
762 op->in_opr2(), | |
763 op->result_opr()); | |
764 break; | |
765 | |
766 case lir_throw: | |
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767 throw_op(op->in_opr1(), op->in_opr2(), op->info()); |
0 | 768 break; |
769 | |
770 default: | |
771 Unimplemented(); | |
772 break; | |
773 } | |
774 } | |
775 | |
776 | |
777 void LIR_Assembler::build_frame() { | |
778 _masm->build_frame(initial_frame_size_in_bytes()); | |
779 } | |
780 | |
781 | |
782 void LIR_Assembler::roundfp_op(LIR_Opr src, LIR_Opr tmp, LIR_Opr dest, bool pop_fpu_stack) { | |
783 assert((src->is_single_fpu() && dest->is_single_stack()) || | |
784 (src->is_double_fpu() && dest->is_double_stack()), | |
785 "round_fp: rounds register -> stack location"); | |
786 | |
787 reg2stack (src, dest, src->type(), pop_fpu_stack); | |
788 } | |
789 | |
790 | |
2002 | 791 void LIR_Assembler::move_op(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool unaligned, bool wide) { |
0 | 792 if (src->is_register()) { |
793 if (dest->is_register()) { | |
794 assert(patch_code == lir_patch_none && info == NULL, "no patching and info allowed here"); | |
795 reg2reg(src, dest); | |
796 } else if (dest->is_stack()) { | |
797 assert(patch_code == lir_patch_none && info == NULL, "no patching and info allowed here"); | |
798 reg2stack(src, dest, type, pop_fpu_stack); | |
799 } else if (dest->is_address()) { | |
2002 | 800 reg2mem(src, dest, type, patch_code, info, pop_fpu_stack, wide, unaligned); |
0 | 801 } else { |
802 ShouldNotReachHere(); | |
803 } | |
804 | |
805 } else if (src->is_stack()) { | |
806 assert(patch_code == lir_patch_none && info == NULL, "no patching and info allowed here"); | |
807 if (dest->is_register()) { | |
808 stack2reg(src, dest, type); | |
809 } else if (dest->is_stack()) { | |
810 stack2stack(src, dest, type); | |
811 } else { | |
812 ShouldNotReachHere(); | |
813 } | |
814 | |
815 } else if (src->is_constant()) { | |
816 if (dest->is_register()) { | |
817 const2reg(src, dest, patch_code, info); // patching is possible | |
818 } else if (dest->is_stack()) { | |
819 assert(patch_code == lir_patch_none && info == NULL, "no patching and info allowed here"); | |
820 const2stack(src, dest); | |
821 } else if (dest->is_address()) { | |
822 assert(patch_code == lir_patch_none, "no patching allowed here"); | |
2002 | 823 const2mem(src, dest, type, info, wide); |
0 | 824 } else { |
825 ShouldNotReachHere(); | |
826 } | |
827 | |
828 } else if (src->is_address()) { | |
2002 | 829 mem2reg(src, dest, type, patch_code, info, wide, unaligned); |
0 | 830 |
831 } else { | |
832 ShouldNotReachHere(); | |
833 } | |
834 } | |
835 | |
836 | |
837 void LIR_Assembler::verify_oop_map(CodeEmitInfo* info) { | |
838 #ifndef PRODUCT | |
839 if (VerifyOopMaps || VerifyOops) { | |
840 bool v = VerifyOops; | |
841 VerifyOops = true; | |
842 OopMapStream s(info->oop_map()); | |
843 while (!s.is_done()) { | |
844 OopMapValue v = s.current(); | |
845 if (v.is_oop()) { | |
846 VMReg r = v.reg(); | |
847 if (!r->is_stack()) { | |
848 stringStream st; | |
849 st.print("bad oop %s at %d", r->as_Register()->name(), _masm->offset()); | |
850 #ifdef SPARC | |
851 _masm->_verify_oop(r->as_Register(), strdup(st.as_string()), __FILE__, __LINE__); | |
852 #else | |
853 _masm->verify_oop(r->as_Register()); | |
854 #endif | |
855 } else { | |
856 _masm->verify_stack_oop(r->reg2stack() * VMRegImpl::stack_slot_size); | |
857 } | |
858 } | |
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859 check_codespace(); |
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860 CHECK_BAILOUT(); |
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861 |
0 | 862 s.next(); |
863 } | |
864 VerifyOops = v; | |
865 } | |
866 #endif | |
867 } |