Mercurial > hg > graal-jvmci-8
annotate graal/com.oracle.graal.asm.amd64/src/com/oracle/graal/asm/amd64/AMD64MacroAssembler.java @ 8167:7f57c30575c8
Make AMD64Address a low-level representation for use by the assembler only.
author | Roland Schatz <roland.schatz@oracle.com> |
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date | Thu, 07 Mar 2013 16:20:18 +0100 |
parents | 838293a77af7 |
children | 45e1ea931e9c |
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1 /* |
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2 * Copyright (c) 2009, 2013, Oracle and/or its affiliates. All rights reserved. |
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3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
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4 * |
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5 * This code is free software; you can redistribute it and/or modify it |
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6 * under the terms of the GNU General Public License version 2 only, as |
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7 * published by the Free Software Foundation. |
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8 * |
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9 * This code is distributed in the hope that it will be useful, but WITHOUT |
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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12 * version 2 for more details (a copy is included in the LICENSE file that |
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13 * accompanied this code). |
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14 * |
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15 * You should have received a copy of the GNU General Public License version |
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16 * 2 along with this work; if not, write to the Free Software Foundation, |
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17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
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18 * |
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
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22 */ |
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23 package com.oracle.graal.asm.amd64; |
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24 |
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25 import static com.oracle.graal.asm.amd64.AMD64AsmOptions.*; |
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26 |
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27 import com.oracle.graal.amd64.*; |
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28 import com.oracle.graal.api.code.*; |
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29 |
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30 /** |
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31 * This class implements commonly used X86 code patterns. |
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32 */ |
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33 public class AMD64MacroAssembler extends AMD64Assembler { |
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34 |
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35 public AMD64MacroAssembler(TargetDescription target, RegisterConfig registerConfig) { |
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36 super(target, registerConfig); |
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37 } |
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38 |
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39 public final void xorptr(Register dst, Register src) { |
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40 xorq(dst, src); |
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41 } |
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42 |
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43 public final void decrementq(Register reg, int value) { |
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44 if (value == Integer.MIN_VALUE) { |
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45 subq(reg, value); |
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46 return; |
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47 } |
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48 if (value < 0) { |
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49 incrementq(reg, -value); |
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50 return; |
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51 } |
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52 if (value == 0) { |
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53 return; |
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54 } |
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55 if (value == 1 && UseIncDec) { |
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56 decq(reg); |
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57 } else { |
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58 subq(reg, value); |
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59 } |
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60 } |
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61 |
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62 public void incrementq(Register reg, int value) { |
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63 if (value == Integer.MIN_VALUE) { |
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64 addq(reg, value); |
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65 return; |
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66 } |
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67 if (value < 0) { |
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68 decrementq(reg, -value); |
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69 return; |
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70 } |
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71 if (value == 0) { |
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72 return; |
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73 } |
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74 if (value == 1 && UseIncDec) { |
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75 incq(reg); |
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76 } else { |
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77 addq(reg, value); |
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78 } |
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79 } |
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80 |
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81 public final void movptr(AMD64Address dst, int src) { |
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82 movslq(dst, src); |
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83 } |
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84 |
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85 public final void cmpptr(Register src1, Register src2) { |
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86 cmpq(src1, src2); |
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87 } |
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88 |
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89 public final void cmpptr(Register src1, AMD64Address src2) { |
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90 cmpq(src1, src2); |
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91 } |
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92 |
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93 public final void decrementl(Register reg, int value) { |
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94 if (value == Integer.MIN_VALUE) { |
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95 subl(reg, value); |
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96 return; |
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97 } |
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98 if (value < 0) { |
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99 incrementl(reg, -value); |
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100 return; |
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101 } |
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102 if (value == 0) { |
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103 return; |
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104 } |
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105 if (value == 1 && UseIncDec) { |
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106 decl(reg); |
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107 } else { |
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108 subl(reg, value); |
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109 } |
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110 } |
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111 |
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112 public final void decrementl(AMD64Address dst, int value) { |
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113 if (value == Integer.MIN_VALUE) { |
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114 subl(dst, value); |
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115 return; |
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116 } |
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117 if (value < 0) { |
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118 incrementl(dst, -value); |
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119 return; |
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120 } |
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121 if (value == 0) { |
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122 return; |
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diff
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|
123 } |
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124 if (value == 1 && UseIncDec) { |
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diff
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125 decl(dst); |
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parents:
diff
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|
126 } else { |
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parents:
diff
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|
127 subl(dst, value); |
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parents:
diff
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|
128 } |
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parents:
diff
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|
129 } |
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|
130 |
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|
131 public final void incrementl(Register reg, int value) { |
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132 if (value == Integer.MIN_VALUE) { |
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|
133 addl(reg, value); |
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parents:
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|
134 return; |
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parents:
diff
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|
135 } |
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parents:
diff
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|
136 if (value < 0) { |
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parents:
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|
137 decrementl(reg, -value); |
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parents:
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|
138 return; |
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parents:
diff
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|
139 } |
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parents:
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|
140 if (value == 0) { |
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parents:
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|
141 return; |
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|
142 } |
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|
143 if (value == 1 && UseIncDec) { |
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144 incl(reg); |
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parents:
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|
145 } else { |
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parents:
diff
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|
146 addl(reg, value); |
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|
147 } |
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|
148 } |
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149 |
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150 public final void incrementl(AMD64Address dst, int value) { |
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|
151 if (value == Integer.MIN_VALUE) { |
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|
152 addl(dst, value); |
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|
153 return; |
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|
154 } |
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|
155 if (value < 0) { |
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|
156 decrementl(dst, -value); |
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|
157 return; |
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parents:
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|
158 } |
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|
159 if (value == 0) { |
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parents:
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|
160 return; |
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parents:
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|
161 } |
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|
162 if (value == 1 && UseIncDec) { |
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|
163 incl(dst); |
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|
164 } else { |
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|
165 addl(dst, value); |
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parents:
diff
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|
166 } |
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parents:
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|
167 } |
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|
168 |
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|
169 public final void signExtendByte(Register reg) { |
3733
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diff
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|
170 if (reg.isByte()) { |
7822
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|
171 movsxb(reg, reg); |
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|
172 } else { |
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|
173 shll(reg, 24); |
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|
174 sarl(reg, 24); |
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parents:
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|
175 } |
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|
176 } |
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|
177 |
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|
178 public final void signExtendShort(Register reg) { |
03eec5b7a546
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|
179 movsxw(reg, reg); |
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|
180 } |
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|
181 |
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|
182 public final void movflt(Register dst, Register src) { |
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|
183 assert dst.isFpu() && src.isFpu(); |
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|
184 if (UseXmmRegToRegMoveAll) { |
3733
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|
185 movaps(dst, src); |
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|
186 } else { |
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diff
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|
187 movss(dst, src); |
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parents:
diff
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|
188 } |
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parents:
diff
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|
189 } |
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parents:
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|
190 |
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7822
diff
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|
191 public final void movflt(Register dst, AMD64Address src) { |
3733
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diff
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|
192 assert dst.isFpu(); |
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diff
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|
193 movss(dst, src); |
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parents:
diff
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|
194 } |
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|
195 |
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7822
diff
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|
196 public final void movflt(AMD64Address dst, Register src) { |
3733
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|
197 assert src.isFpu(); |
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changeset
|
198 movss(dst, src); |
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parents:
diff
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|
199 } |
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|
200 |
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diff
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|
201 public final void movdbl(Register dst, Register src) { |
3733
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parents:
diff
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|
202 assert dst.isFpu() && src.isFpu(); |
6493
85c1b84f8fd9
moved ADM64-specific assembler code into separate project
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diff
changeset
|
203 if (UseXmmRegToRegMoveAll) { |
3733
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parents:
diff
changeset
|
204 movapd(dst, src); |
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parents:
diff
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|
205 } else { |
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Thomas Wuerthinger <thomas.wuerthinger@oracle.com>
parents:
diff
changeset
|
206 movsd(dst, src); |
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Thomas Wuerthinger <thomas.wuerthinger@oracle.com>
parents:
diff
changeset
|
207 } |
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Thomas Wuerthinger <thomas.wuerthinger@oracle.com>
parents:
diff
changeset
|
208 } |
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Thomas Wuerthinger <thomas.wuerthinger@oracle.com>
parents:
diff
changeset
|
209 |
7839
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7822
diff
changeset
|
210 public final void movdbl(Register dst, AMD64Address src) { |
3733
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diff
changeset
|
211 assert dst.isFpu(); |
6493
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moved ADM64-specific assembler code into separate project
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diff
changeset
|
212 if (UseXmmLoadAndClearUpper) { |
3733
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parents:
diff
changeset
|
213 movsd(dst, src); |
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parents:
diff
changeset
|
214 } else { |
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parents:
diff
changeset
|
215 movlpd(dst, src); |
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parents:
diff
changeset
|
216 } |
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parents:
diff
changeset
|
217 } |
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diff
changeset
|
218 |
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parents:
diff
changeset
|
219 /** |
7530
5e3d1a68664e
applied mx eclipseformat to all Java files
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6580
diff
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|
220 * Non-atomic write of a 64-bit constant to memory. Do not use if the address might be a |
5e3d1a68664e
applied mx eclipseformat to all Java files
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6580
diff
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|
221 * volatile field! |
3733
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parents:
diff
changeset
|
222 */ |
7839
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parents:
7822
diff
changeset
|
223 public final void movlong(AMD64Address dst, long src) { |
8167
7f57c30575c8
Make AMD64Address a low-level representation for use by the assembler only.
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diff
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|
224 AMD64Address high = new AMD64Address(dst.getBase(), dst.getIndex(), dst.getScale(), dst.getDisplacement() + 4); |
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|
225 movl(dst, (int) (src & 0xFFFFFFFF)); |
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parents:
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|
226 movl(high, (int) (src >> 32)); |
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|
227 } |
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parents:
diff
changeset
|
228 |
7822
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diff
changeset
|
229 public final void flog(Register dest, Register value, boolean base10) { |
7791
fe1187115167
remove incorrect use of spillSlotSize
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parents:
7530
diff
changeset
|
230 assert dest.isFpu() && value.isFpu(); |
3733
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diff
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|
231 |
8167
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Make AMD64Address a low-level representation for use by the assembler only.
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diff
changeset
|
232 AMD64Address tmp = new AMD64Address(AMD64.rsp); |
3733
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parents:
diff
changeset
|
233 if (base10) { |
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parents:
diff
changeset
|
234 fldlg2(); |
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parents:
diff
changeset
|
235 } else { |
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Thomas Wuerthinger <thomas.wuerthinger@oracle.com>
parents:
diff
changeset
|
236 fldln2(); |
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Thomas Wuerthinger <thomas.wuerthinger@oracle.com>
parents:
diff
changeset
|
237 } |
7791
fe1187115167
remove incorrect use of spillSlotSize
Roland Schatz <roland.schatz@oracle.com>
parents:
7530
diff
changeset
|
238 subq(AMD64.rsp, 8); |
3733
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parents:
diff
changeset
|
239 movsd(tmp, value); |
e233f5660da4
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parents:
diff
changeset
|
240 fld(tmp); |
e233f5660da4
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parents:
diff
changeset
|
241 fyl2x(); |
7822
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diff
changeset
|
242 trigEpilogue(dest, tmp); |
3733
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parents:
diff
changeset
|
243 } |
e233f5660da4
Added Java files from Maxine project.
Thomas Wuerthinger <thomas.wuerthinger@oracle.com>
parents:
diff
changeset
|
244 |
7822
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diff
changeset
|
245 public final void fsin(Register dest, Register value) { |
7839
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7822
diff
changeset
|
246 AMD64Address tmp = trigPrologue(value); |
7822
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Clean up of AMD64MacroAssembler.
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247 fsin(); |
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248 trigEpilogue(dest, tmp); |
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249 } |
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250 |
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251 public final void fcos(Register dest, Register value) { |
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252 AMD64Address tmp = trigPrologue(value); |
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253 fcos(); |
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254 trigEpilogue(dest, tmp); |
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255 } |
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256 |
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257 public final void ftan(Register dest, Register value) { |
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258 AMD64Address tmp = trigPrologue(value); |
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259 fptan(); |
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260 fstp(0); // ftan pushes 1.0 in addition to the actual result, pop |
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261 trigEpilogue(dest, tmp); |
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262 } |
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263 |
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264 private AMD64Address trigPrologue(Register value) { |
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265 assert value.isFpu(); |
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266 AMD64Address tmp = new AMD64Address(AMD64.rsp); |
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267 subq(AMD64.rsp, 8); |
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268 movsd(tmp, value); |
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269 fld(tmp); |
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270 return tmp; |
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271 } |
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272 |
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273 private void trigEpilogue(Register dest, AMD64Address tmp) { |
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274 assert dest.isFpu(); |
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275 fstp(tmp); |
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276 movsd(dest, tmp); |
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277 addq(AMD64.rsp, 8); |
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278 } |
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279 |
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280 /** |
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281 * Emit code to save a given set of callee save registers in the {@linkplain CalleeSaveLayout |
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282 * CSA} within the frame. |
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283 * |
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284 * @param csl the description of the CSA |
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285 * @param frameToCSA offset from the frame pointer to the CSA |
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286 */ |
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287 public final void save(CalleeSaveLayout csl, int frameToCSA) { |
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288 for (Register r : csl.registers) { |
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289 int offset = csl.offsetOf(r); |
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290 movq(new AMD64Address(frameRegister, frameToCSA + offset), r); |
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291 } |
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292 } |
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293 |
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294 public final void restore(CalleeSaveLayout csl, int frameToCSA) { |
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295 for (Register r : csl.registers) { |
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296 int offset = csl.offsetOf(r); |
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297 movq(r, new AMD64Address(frameRegister, frameToCSA + offset)); |
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298 } |
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299 } |
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300 } |