Mercurial > hg > graal-jvmci-8
annotate src/share/vm/opto/phase.cpp @ 22815:9df0d8f65fea
8068881: SIGBUS in C2 compiled method weblogic.wsee.jaxws.framework.jaxrpc.EnvironmentFactory$SimulatedWsdlDefinitions.<init>
Summary: Use MachMerge to hook together defs of the same multidef value in a block
Reviewed-by: kvn, vlivanov
author | iveresov |
---|---|
date | Tue, 20 Jan 2015 13:56:02 -0800 |
parents | a9becfeecd1b |
children | dd9cc155639c 70649f10b88c |
rev | line source |
---|---|
0 | 1 /* |
17467
55fb97c4c58d
8029233: Update copyright year to match last edit in jdk8 hotspot repository for 2013
mikael
parents:
10278
diff
changeset
|
2 * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. |
0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
4 * | |
5 * This code is free software; you can redistribute it and/or modify it | |
6 * under the terms of the GNU General Public License version 2 only, as | |
7 * published by the Free Software Foundation. | |
8 * | |
9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 * version 2 for more details (a copy is included in the LICENSE file that | |
13 * accompanied this code). | |
14 * | |
15 * You should have received a copy of the GNU General Public License version | |
16 * 2 along with this work; if not, write to the Free Software Foundation, | |
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
18 * | |
1552
c18cbe5936b8
6941466: Oracle rebranding changes for Hotspot repositories
trims
parents:
921
diff
changeset
|
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
c18cbe5936b8
6941466: Oracle rebranding changes for Hotspot repositories
trims
parents:
921
diff
changeset
|
20 * or visit www.oracle.com if you need additional information or have any |
c18cbe5936b8
6941466: Oracle rebranding changes for Hotspot repositories
trims
parents:
921
diff
changeset
|
21 * questions. |
0 | 22 * |
23 */ | |
24 | |
1972 | 25 #include "precompiled.hpp" |
26 #include "code/nmethod.hpp" | |
27 #include "compiler/compileBroker.hpp" | |
28 #include "opto/compile.hpp" | |
14428
044b28168e20
8003854: PPC64 (part 115): Introduce PostallocExpand that expands nodes after register allocation
goetz
parents:
10278
diff
changeset
|
29 #include "opto/matcher.hpp" |
1972 | 30 #include "opto/node.hpp" |
31 #include "opto/phase.hpp" | |
0 | 32 |
33 #ifndef PRODUCT | |
34 int Phase::_total_bytes_compiled = 0; | |
35 | |
36 elapsedTimer Phase::_t_totalCompilation; | |
37 elapsedTimer Phase::_t_methodCompilation; | |
38 elapsedTimer Phase::_t_stubCompilation; | |
39 #endif | |
40 | |
41 // The next timers used for LogCompilation | |
42 elapsedTimer Phase::_t_parser; | |
43 elapsedTimer Phase::_t_optimizer; | |
5948
ee138854b3a6
7147744: CTW: assert(false) failed: infinite EA connection graph build
kvn
parents:
2249
diff
changeset
|
44 elapsedTimer Phase::_t_escapeAnalysis; |
ee138854b3a6
7147744: CTW: assert(false) failed: infinite EA connection graph build
kvn
parents:
2249
diff
changeset
|
45 elapsedTimer Phase::_t_connectionGraph; |
0 | 46 elapsedTimer Phase::_t_idealLoop; |
47 elapsedTimer Phase::_t_ccp; | |
48 elapsedTimer Phase::_t_matcher; | |
49 elapsedTimer Phase::_t_registerAllocation; | |
50 elapsedTimer Phase::_t_output; | |
51 | |
52 #ifndef PRODUCT | |
53 elapsedTimer Phase::_t_graphReshaping; | |
54 elapsedTimer Phase::_t_scheduler; | |
418 | 55 elapsedTimer Phase::_t_blockOrdering; |
5948
ee138854b3a6
7147744: CTW: assert(false) failed: infinite EA connection graph build
kvn
parents:
2249
diff
changeset
|
56 elapsedTimer Phase::_t_macroEliminate; |
0 | 57 elapsedTimer Phase::_t_macroExpand; |
58 elapsedTimer Phase::_t_peephole; | |
14428
044b28168e20
8003854: PPC64 (part 115): Introduce PostallocExpand that expands nodes after register allocation
goetz
parents:
10278
diff
changeset
|
59 elapsedTimer Phase::_t_postalloc_expand; |
0 | 60 elapsedTimer Phase::_t_codeGeneration; |
61 elapsedTimer Phase::_t_registerMethod; | |
62 elapsedTimer Phase::_t_temporaryTimer1; | |
63 elapsedTimer Phase::_t_temporaryTimer2; | |
921
046932b72aa2
6862956: PhaseIdealLoop should have a CFG verification mode
never
parents:
605
diff
changeset
|
64 elapsedTimer Phase::_t_idealLoopVerify; |
0 | 65 |
66 // Subtimers for _t_optimizer | |
67 elapsedTimer Phase::_t_iterGVN; | |
68 elapsedTimer Phase::_t_iterGVN2; | |
10278 | 69 elapsedTimer Phase::_t_incrInline; |
0 | 70 |
71 // Subtimers for _t_registerAllocation | |
72 elapsedTimer Phase::_t_ctorChaitin; | |
73 elapsedTimer Phase::_t_buildIFGphysical; | |
74 elapsedTimer Phase::_t_computeLive; | |
75 elapsedTimer Phase::_t_regAllocSplit; | |
76 elapsedTimer Phase::_t_postAllocCopyRemoval; | |
22815
9df0d8f65fea
8068881: SIGBUS in C2 compiled method weblogic.wsee.jaxws.framework.jaxrpc.EnvironmentFactory$SimulatedWsdlDefinitions.<init>
iveresov
parents:
17795
diff
changeset
|
77 elapsedTimer Phase::_t_mergeMultidefs; |
0 | 78 elapsedTimer Phase::_t_fixupSpills; |
79 | |
80 // Subtimers for _t_output | |
81 elapsedTimer Phase::_t_instrSched; | |
82 elapsedTimer Phase::_t_buildOopMaps; | |
83 #endif | |
84 | |
85 //------------------------------Phase------------------------------------------ | |
86 Phase::Phase( PhaseNumber pnum ) : _pnum(pnum), C( pnum == Compiler ? NULL : Compile::current()) { | |
605 | 87 // Poll for requests from shutdown mechanism to quiesce compiler (4448539, 4448544). |
0 | 88 // This is an effective place to poll, since the compiler is full of phases. |
89 // In particular, every inlining site uses a recursively created Parse phase. | |
90 CompileBroker::maybe_block(); | |
91 } | |
92 | |
93 #ifndef PRODUCT | |
94 static const double minimum_reported_time = 0.0001; // seconds | |
95 static const double expected_method_compile_coverage = 0.97; // % | |
96 static const double minimum_meaningful_method_compile = 2.00; // seconds | |
97 | |
98 void Phase::print_timers() { | |
99 tty->print_cr ("Accumulated compiler times:"); | |
100 tty->print_cr ("---------------------------"); | |
101 tty->print_cr (" Total compilation: %3.3f sec.", Phase::_t_totalCompilation.seconds()); | |
921
046932b72aa2
6862956: PhaseIdealLoop should have a CFG verification mode
never
parents:
605
diff
changeset
|
102 tty->print (" method compilation : %3.3f sec", Phase::_t_methodCompilation.seconds()); |
0 | 103 tty->print ("/%d bytes",_total_bytes_compiled); |
104 tty->print_cr (" (%3.0f bytes per sec) ", Phase::_total_bytes_compiled / Phase::_t_methodCompilation.seconds()); | |
921
046932b72aa2
6862956: PhaseIdealLoop should have a CFG verification mode
never
parents:
605
diff
changeset
|
105 tty->print_cr (" stub compilation : %3.3f sec.", Phase::_t_stubCompilation.seconds()); |
0 | 106 tty->print_cr (" Phases:"); |
921
046932b72aa2
6862956: PhaseIdealLoop should have a CFG verification mode
never
parents:
605
diff
changeset
|
107 tty->print_cr (" parse : %3.3f sec", Phase::_t_parser.seconds()); |
046932b72aa2
6862956: PhaseIdealLoop should have a CFG verification mode
never
parents:
605
diff
changeset
|
108 tty->print_cr (" optimizer : %3.3f sec", Phase::_t_optimizer.seconds()); |
0 | 109 if( Verbose || WizardMode ) { |
2249 | 110 if (DoEscapeAnalysis) { |
111 // EA is part of Optimizer. | |
112 tty->print_cr (" escape analysis: %3.3f sec", Phase::_t_escapeAnalysis.seconds()); | |
5948
ee138854b3a6
7147744: CTW: assert(false) failed: infinite EA connection graph build
kvn
parents:
2249
diff
changeset
|
113 tty->print_cr (" connection graph: %3.3f sec", Phase::_t_connectionGraph.seconds()); |
ee138854b3a6
7147744: CTW: assert(false) failed: infinite EA connection graph build
kvn
parents:
2249
diff
changeset
|
114 tty->print_cr (" macroEliminate : %3.3f sec", Phase::_t_macroEliminate.seconds()); |
2249 | 115 } |
921
046932b72aa2
6862956: PhaseIdealLoop should have a CFG verification mode
never
parents:
605
diff
changeset
|
116 tty->print_cr (" iterGVN : %3.3f sec", Phase::_t_iterGVN.seconds()); |
10278 | 117 tty->print_cr (" incrInline : %3.3f sec", Phase::_t_incrInline.seconds()); |
921
046932b72aa2
6862956: PhaseIdealLoop should have a CFG verification mode
never
parents:
605
diff
changeset
|
118 tty->print_cr (" idealLoop : %3.3f sec", Phase::_t_idealLoop.seconds()); |
046932b72aa2
6862956: PhaseIdealLoop should have a CFG verification mode
never
parents:
605
diff
changeset
|
119 tty->print_cr (" idealLoopVerify: %3.3f sec", Phase::_t_idealLoopVerify.seconds()); |
046932b72aa2
6862956: PhaseIdealLoop should have a CFG verification mode
never
parents:
605
diff
changeset
|
120 tty->print_cr (" ccp : %3.3f sec", Phase::_t_ccp.seconds()); |
046932b72aa2
6862956: PhaseIdealLoop should have a CFG verification mode
never
parents:
605
diff
changeset
|
121 tty->print_cr (" iterGVN2 : %3.3f sec", Phase::_t_iterGVN2.seconds()); |
2249 | 122 tty->print_cr (" macroExpand : %3.3f sec", Phase::_t_macroExpand.seconds()); |
921
046932b72aa2
6862956: PhaseIdealLoop should have a CFG verification mode
never
parents:
605
diff
changeset
|
123 tty->print_cr (" graphReshape : %3.3f sec", Phase::_t_graphReshaping.seconds()); |
5948
ee138854b3a6
7147744: CTW: assert(false) failed: infinite EA connection graph build
kvn
parents:
2249
diff
changeset
|
124 double optimizer_subtotal = Phase::_t_iterGVN.seconds() + Phase::_t_iterGVN2.seconds() + |
ee138854b3a6
7147744: CTW: assert(false) failed: infinite EA connection graph build
kvn
parents:
2249
diff
changeset
|
125 Phase::_t_escapeAnalysis.seconds() + Phase::_t_macroEliminate.seconds() + |
0 | 126 Phase::_t_idealLoop.seconds() + Phase::_t_ccp.seconds() + |
5948
ee138854b3a6
7147744: CTW: assert(false) failed: infinite EA connection graph build
kvn
parents:
2249
diff
changeset
|
127 Phase::_t_macroExpand.seconds() + Phase::_t_graphReshaping.seconds(); |
0 | 128 double percent_of_optimizer = ((optimizer_subtotal == 0.0) ? 0.0 : (optimizer_subtotal / Phase::_t_optimizer.seconds() * 100.0)); |
921
046932b72aa2
6862956: PhaseIdealLoop should have a CFG verification mode
never
parents:
605
diff
changeset
|
129 tty->print_cr (" subtotal : %3.3f sec, %3.2f %%", optimizer_subtotal, percent_of_optimizer); |
0 | 130 } |
921
046932b72aa2
6862956: PhaseIdealLoop should have a CFG verification mode
never
parents:
605
diff
changeset
|
131 tty->print_cr (" matcher : %3.3f sec", Phase::_t_matcher.seconds()); |
046932b72aa2
6862956: PhaseIdealLoop should have a CFG verification mode
never
parents:
605
diff
changeset
|
132 tty->print_cr (" scheduler : %3.3f sec", Phase::_t_scheduler.seconds()); |
046932b72aa2
6862956: PhaseIdealLoop should have a CFG verification mode
never
parents:
605
diff
changeset
|
133 tty->print_cr (" regalloc : %3.3f sec", Phase::_t_registerAllocation.seconds()); |
0 | 134 if( Verbose || WizardMode ) { |
921
046932b72aa2
6862956: PhaseIdealLoop should have a CFG verification mode
never
parents:
605
diff
changeset
|
135 tty->print_cr (" ctorChaitin : %3.3f sec", Phase::_t_ctorChaitin.seconds()); |
046932b72aa2
6862956: PhaseIdealLoop should have a CFG verification mode
never
parents:
605
diff
changeset
|
136 tty->print_cr (" buildIFG : %3.3f sec", Phase::_t_buildIFGphysical.seconds()); |
046932b72aa2
6862956: PhaseIdealLoop should have a CFG verification mode
never
parents:
605
diff
changeset
|
137 tty->print_cr (" computeLive : %3.3f sec", Phase::_t_computeLive.seconds()); |
046932b72aa2
6862956: PhaseIdealLoop should have a CFG verification mode
never
parents:
605
diff
changeset
|
138 tty->print_cr (" regAllocSplit : %3.3f sec", Phase::_t_regAllocSplit.seconds()); |
0 | 139 tty->print_cr (" postAllocCopyRemoval: %3.3f sec", Phase::_t_postAllocCopyRemoval.seconds()); |
22815
9df0d8f65fea
8068881: SIGBUS in C2 compiled method weblogic.wsee.jaxws.framework.jaxrpc.EnvironmentFactory$SimulatedWsdlDefinitions.<init>
iveresov
parents:
17795
diff
changeset
|
140 tty->print_cr (" mergeMultidefs: %3.3f sec", Phase::_t_mergeMultidefs.seconds()); |
921
046932b72aa2
6862956: PhaseIdealLoop should have a CFG verification mode
never
parents:
605
diff
changeset
|
141 tty->print_cr (" fixupSpills : %3.3f sec", Phase::_t_fixupSpills.seconds()); |
0 | 142 double regalloc_subtotal = Phase::_t_ctorChaitin.seconds() + |
143 Phase::_t_buildIFGphysical.seconds() + Phase::_t_computeLive.seconds() + | |
144 Phase::_t_regAllocSplit.seconds() + Phase::_t_fixupSpills.seconds() + | |
22815
9df0d8f65fea
8068881: SIGBUS in C2 compiled method weblogic.wsee.jaxws.framework.jaxrpc.EnvironmentFactory$SimulatedWsdlDefinitions.<init>
iveresov
parents:
17795
diff
changeset
|
145 Phase::_t_postAllocCopyRemoval.seconds() + Phase::_t_mergeMultidefs.seconds(); |
0 | 146 double percent_of_regalloc = ((regalloc_subtotal == 0.0) ? 0.0 : (regalloc_subtotal / Phase::_t_registerAllocation.seconds() * 100.0)); |
921
046932b72aa2
6862956: PhaseIdealLoop should have a CFG verification mode
never
parents:
605
diff
changeset
|
147 tty->print_cr (" subtotal : %3.3f sec, %3.2f %%", regalloc_subtotal, percent_of_regalloc); |
0 | 148 } |
921
046932b72aa2
6862956: PhaseIdealLoop should have a CFG verification mode
never
parents:
605
diff
changeset
|
149 tty->print_cr (" blockOrdering : %3.3f sec", Phase::_t_blockOrdering.seconds()); |
046932b72aa2
6862956: PhaseIdealLoop should have a CFG verification mode
never
parents:
605
diff
changeset
|
150 tty->print_cr (" peephole : %3.3f sec", Phase::_t_peephole.seconds()); |
14428
044b28168e20
8003854: PPC64 (part 115): Introduce PostallocExpand that expands nodes after register allocation
goetz
parents:
10278
diff
changeset
|
151 if (Matcher::require_postalloc_expand) { |
044b28168e20
8003854: PPC64 (part 115): Introduce PostallocExpand that expands nodes after register allocation
goetz
parents:
10278
diff
changeset
|
152 tty->print_cr (" postalloc_expand: %3.3f sec", Phase::_t_postalloc_expand.seconds()); |
044b28168e20
8003854: PPC64 (part 115): Introduce PostallocExpand that expands nodes after register allocation
goetz
parents:
10278
diff
changeset
|
153 } |
921
046932b72aa2
6862956: PhaseIdealLoop should have a CFG verification mode
never
parents:
605
diff
changeset
|
154 tty->print_cr (" codeGen : %3.3f sec", Phase::_t_codeGeneration.seconds()); |
046932b72aa2
6862956: PhaseIdealLoop should have a CFG verification mode
never
parents:
605
diff
changeset
|
155 tty->print_cr (" install_code : %3.3f sec", Phase::_t_registerMethod.seconds()); |
046932b72aa2
6862956: PhaseIdealLoop should have a CFG verification mode
never
parents:
605
diff
changeset
|
156 tty->print_cr (" -------------- : ----------"); |
0 | 157 double phase_subtotal = Phase::_t_parser.seconds() + |
158 Phase::_t_optimizer.seconds() + Phase::_t_graphReshaping.seconds() + | |
159 Phase::_t_matcher.seconds() + Phase::_t_scheduler.seconds() + | |
418 | 160 Phase::_t_registerAllocation.seconds() + Phase::_t_blockOrdering.seconds() + |
0 | 161 Phase::_t_codeGeneration.seconds() + Phase::_t_registerMethod.seconds(); |
162 double percent_of_method_compile = ((phase_subtotal == 0.0) ? 0.0 : phase_subtotal / Phase::_t_methodCompilation.seconds()) * 100.0; | |
163 // counters inside Compile::CodeGen include time for adapters and stubs | |
164 // so phase-total can be greater than 100% | |
921
046932b72aa2
6862956: PhaseIdealLoop should have a CFG verification mode
never
parents:
605
diff
changeset
|
165 tty->print_cr (" total : %3.3f sec, %3.2f %%", phase_subtotal, percent_of_method_compile); |
0 | 166 |
167 assert( percent_of_method_compile > expected_method_compile_coverage || | |
168 phase_subtotal < minimum_meaningful_method_compile, | |
169 "Must account for method compilation"); | |
170 | |
171 if( Phase::_t_temporaryTimer1.seconds() > minimum_reported_time ) { | |
172 tty->cr(); | |
173 tty->print_cr (" temporaryTimer1: %3.3f sec", Phase::_t_temporaryTimer1.seconds()); | |
174 } | |
175 if( Phase::_t_temporaryTimer2.seconds() > minimum_reported_time ) { | |
176 tty->cr(); | |
177 tty->print_cr (" temporaryTimer2: %3.3f sec", Phase::_t_temporaryTimer2.seconds()); | |
178 } | |
921
046932b72aa2
6862956: PhaseIdealLoop should have a CFG verification mode
never
parents:
605
diff
changeset
|
179 tty->print_cr (" output : %3.3f sec", Phase::_t_output.seconds()); |
046932b72aa2
6862956: PhaseIdealLoop should have a CFG verification mode
never
parents:
605
diff
changeset
|
180 tty->print_cr (" isched : %3.3f sec", Phase::_t_instrSched.seconds()); |
046932b72aa2
6862956: PhaseIdealLoop should have a CFG verification mode
never
parents:
605
diff
changeset
|
181 tty->print_cr (" bldOopMaps : %3.3f sec", Phase::_t_buildOopMaps.seconds()); |
0 | 182 } |
183 #endif |