Mercurial > hg > graal-jvmci-8
annotate src/cpu/x86/vm/x86_32.ad @ 23660:b5f3a471e646
Merge.
| author | Doug Simon <doug.simon@oracle.com> |
|---|---|
| date | Wed, 01 Jun 2016 00:11:44 +0200 |
| parents | dd9cc155639c faef2a237329 |
| children | 9b69cec6d01b |
| rev | line source |
|---|---|
| 0 | 1 // |
| 9154 | 2 // Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. |
| 0 | 3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 4 // | |
| 5 // This code is free software; you can redistribute it and/or modify it | |
| 6 // under the terms of the GNU General Public License version 2 only, as | |
| 7 // published by the Free Software Foundation. | |
| 8 // | |
| 9 // This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 // version 2 for more details (a copy is included in the LICENSE file that | |
| 13 // accompanied this code). | |
| 14 // | |
| 15 // You should have received a copy of the GNU General Public License version | |
| 16 // 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 // | |
|
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19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 // or visit www.oracle.com if you need additional information or have any |
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21 // questions. |
| 0 | 22 // |
| 23 // | |
| 24 | |
| 25 // X86 Architecture Description File | |
| 26 | |
| 27 //----------REGISTER DEFINITION BLOCK------------------------------------------ | |
| 28 // This information is used by the matcher and the register allocator to | |
| 29 // describe individual registers and classes of registers within the target | |
| 30 // archtecture. | |
| 31 | |
| 32 register %{ | |
| 33 //----------Architecture Description Register Definitions---------------------- | |
| 34 // General Registers | |
| 35 // "reg_def" name ( register save type, C convention save type, | |
| 36 // ideal register type, encoding ); | |
| 37 // Register Save Types: | |
| 38 // | |
| 39 // NS = No-Save: The register allocator assumes that these registers | |
| 40 // can be used without saving upon entry to the method, & | |
| 41 // that they do not need to be saved at call sites. | |
| 42 // | |
| 43 // SOC = Save-On-Call: The register allocator assumes that these registers | |
| 44 // can be used without saving upon entry to the method, | |
| 45 // but that they must be saved at call sites. | |
| 46 // | |
| 47 // SOE = Save-On-Entry: The register allocator assumes that these registers | |
| 48 // must be saved before using them upon entry to the | |
| 49 // method, but they do not need to be saved at call | |
| 50 // sites. | |
| 51 // | |
| 52 // AS = Always-Save: The register allocator assumes that these registers | |
| 53 // must be saved before using them upon entry to the | |
| 54 // method, & that they must be saved at call sites. | |
| 55 // | |
| 56 // Ideal Register Type is used to determine how to save & restore a | |
| 57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get | |
| 58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI. | |
| 59 // | |
| 60 // The encoding number is the actual bit-pattern placed into the opcodes. | |
| 61 | |
| 62 // General Registers | |
| 63 // Previously set EBX, ESI, and EDI as save-on-entry for java code | |
| 64 // Turn off SOE in java-code due to frequent use of uncommon-traps. | |
| 65 // Now that allocator is better, turn on ESI and EDI as SOE registers. | |
| 66 | |
| 67 reg_def EBX(SOC, SOE, Op_RegI, 3, rbx->as_VMReg()); | |
| 68 reg_def ECX(SOC, SOC, Op_RegI, 1, rcx->as_VMReg()); | |
| 69 reg_def ESI(SOC, SOE, Op_RegI, 6, rsi->as_VMReg()); | |
| 70 reg_def EDI(SOC, SOE, Op_RegI, 7, rdi->as_VMReg()); | |
| 71 // now that adapter frames are gone EBP is always saved and restored by the prolog/epilog code | |
| 72 reg_def EBP(NS, SOE, Op_RegI, 5, rbp->as_VMReg()); | |
| 73 reg_def EDX(SOC, SOC, Op_RegI, 2, rdx->as_VMReg()); | |
| 74 reg_def EAX(SOC, SOC, Op_RegI, 0, rax->as_VMReg()); | |
| 75 reg_def ESP( NS, NS, Op_RegI, 4, rsp->as_VMReg()); | |
| 76 | |
| 77 // Float registers. We treat TOS/FPR0 special. It is invisible to the | |
| 78 // allocator, and only shows up in the encodings. | |
| 79 reg_def FPR0L( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad()); | |
| 80 reg_def FPR0H( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad()); | |
| 81 // Ok so here's the trick FPR1 is really st(0) except in the midst | |
| 82 // of emission of assembly for a machnode. During the emission the fpu stack | |
| 83 // is pushed making FPR1 == st(1) temporarily. However at any safepoint | |
| 84 // the stack will not have this element so FPR1 == st(0) from the | |
| 85 // oopMap viewpoint. This same weirdness with numbering causes | |
| 86 // instruction encoding to have to play games with the register | |
| 87 // encode to correct for this 0/1 issue. See MachSpillCopyNode::implementation | |
| 88 // where it does flt->flt moves to see an example | |
| 89 // | |
| 90 reg_def FPR1L( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg()); | |
| 91 reg_def FPR1H( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg()->next()); | |
| 92 reg_def FPR2L( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg()); | |
| 93 reg_def FPR2H( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg()->next()); | |
| 94 reg_def FPR3L( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg()); | |
| 95 reg_def FPR3H( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg()->next()); | |
| 96 reg_def FPR4L( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg()); | |
| 97 reg_def FPR4H( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg()->next()); | |
| 98 reg_def FPR5L( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg()); | |
| 99 reg_def FPR5H( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg()->next()); | |
| 100 reg_def FPR6L( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()); | |
| 101 reg_def FPR6H( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()->next()); | |
| 102 reg_def FPR7L( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()); | |
| 103 reg_def FPR7H( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()->next()); | |
| 104 | |
| 105 // Specify priority of register selection within phases of register | |
| 106 // allocation. Highest priority is first. A useful heuristic is to | |
| 107 // give registers a low priority when they are required by machine | |
| 108 // instructions, like EAX and EDX. Registers which are used as | |
| 605 | 109 // pairs must fall on an even boundary (witness the FPR#L's in this list). |
| 0 | 110 // For the Intel integer registers, the equivalent Long pairs are |
| 111 // EDX:EAX, EBX:ECX, and EDI:EBP. | |
| 112 alloc_class chunk0( ECX, EBX, EBP, EDI, EAX, EDX, ESI, ESP, | |
| 113 FPR0L, FPR0H, FPR1L, FPR1H, FPR2L, FPR2H, | |
| 114 FPR3L, FPR3H, FPR4L, FPR4H, FPR5L, FPR5H, | |
| 115 FPR6L, FPR6H, FPR7L, FPR7H ); | |
| 116 | |
| 117 | |
| 118 //----------Architecture Description Register Classes-------------------------- | |
| 119 // Several register classes are automatically defined based upon information in | |
| 120 // this architecture description. | |
| 121 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ ) | |
| 122 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ ) | |
| 123 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ ) | |
| 124 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ ) | |
| 125 // | |
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126 // Class for no registers (empty set). |
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127 reg_class no_reg(); |
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128 |
| 0 | 129 // Class for all registers |
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130 reg_class any_reg_with_ebp(EAX, EDX, EBP, EDI, ESI, ECX, EBX, ESP); |
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131 // Class for all registers (excluding EBP) |
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132 reg_class any_reg_no_ebp(EAX, EDX, EDI, ESI, ECX, EBX, ESP); |
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133 // Dynamic register class that selects at runtime between register classes |
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134 // any_reg and any_no_ebp_reg (depending on the value of the flag PreserveFramePointer). |
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135 // Equivalent to: return PreserveFramePointer ? any_no_ebp_reg : any_reg; |
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136 reg_class_dynamic any_reg(any_reg_no_ebp, any_reg_with_ebp, %{ PreserveFramePointer %}); |
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137 |
| 0 | 138 // Class for general registers |
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139 reg_class int_reg_with_ebp(EAX, EDX, EBP, EDI, ESI, ECX, EBX); |
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140 // Class for general registers (excluding EBP). |
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141 // This register class can be used for implicit null checks on win95. |
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142 // It is also safe for use by tailjumps (we don't want to allocate in ebp). |
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143 // Used also if the PreserveFramePointer flag is true. |
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144 reg_class int_reg_no_ebp(EAX, EDX, EDI, ESI, ECX, EBX); |
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145 // Dynamic register class that selects between int_reg and int_reg_no_ebp. |
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146 reg_class_dynamic int_reg(int_reg_no_ebp, int_reg_with_ebp, %{ PreserveFramePointer %}); |
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147 |
| 0 | 148 // Class of "X" registers |
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149 reg_class int_x_reg(EBX, ECX, EDX, EAX); |
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150 |
| 0 | 151 // Class of registers that can appear in an address with no offset. |
| 152 // EBP and ESP require an extra instruction byte for zero offset. | |
| 153 // Used in fast-unlock | |
| 154 reg_class p_reg(EDX, EDI, ESI, EBX); | |
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155 |
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156 // Class for general registers excluding ECX |
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157 reg_class ncx_reg_with_ebp(EAX, EDX, EBP, EDI, ESI, EBX); |
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158 // Class for general registers excluding ECX (and EBP) |
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159 reg_class ncx_reg_no_ebp(EAX, EDX, EDI, ESI, EBX); |
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160 // Dynamic register class that selects between ncx_reg and ncx_reg_no_ebp. |
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161 reg_class_dynamic ncx_reg(ncx_reg_no_ebp, ncx_reg_with_ebp, %{ PreserveFramePointer %}); |
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162 |
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163 // Class for general registers excluding EAX |
| 0 | 164 reg_class nax_reg(EDX, EDI, ESI, ECX, EBX); |
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165 |
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166 // Class for general registers excluding EAX and EBX. |
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167 reg_class nabx_reg_with_ebp(EDX, EDI, ESI, ECX, EBP); |
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168 // Class for general registers excluding EAX and EBX (and EBP) |
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169 reg_class nabx_reg_no_ebp(EDX, EDI, ESI, ECX); |
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170 // Dynamic register class that selects between nabx_reg and nabx_reg_no_ebp. |
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171 reg_class_dynamic nabx_reg(nabx_reg_no_ebp, nabx_reg_with_ebp, %{ PreserveFramePointer %}); |
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172 |
| 0 | 173 // Class of EAX (for multiply and divide operations) |
| 174 reg_class eax_reg(EAX); | |
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175 |
| 0 | 176 // Class of EBX (for atomic add) |
| 177 reg_class ebx_reg(EBX); | |
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178 |
| 0 | 179 // Class of ECX (for shift and JCXZ operations and cmpLTMask) |
| 180 reg_class ecx_reg(ECX); | |
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181 |
| 0 | 182 // Class of EDX (for multiply and divide operations) |
| 183 reg_class edx_reg(EDX); | |
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184 |
| 0 | 185 // Class of EDI (for synchronization) |
| 186 reg_class edi_reg(EDI); | |
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187 |
| 0 | 188 // Class of ESI (for synchronization) |
| 189 reg_class esi_reg(ESI); | |
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190 |
| 0 | 191 // Singleton class for stack pointer |
| 192 reg_class sp_reg(ESP); | |
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193 |
| 0 | 194 // Singleton class for instruction pointer |
| 195 // reg_class ip_reg(EIP); | |
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196 |
| 0 | 197 // Class of integer register pairs |
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198 reg_class long_reg_with_ebp( EAX,EDX, ECX,EBX, EBP,EDI ); |
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199 // Class of integer register pairs (excluding EBP and EDI); |
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200 reg_class long_reg_no_ebp( EAX,EDX, ECX,EBX ); |
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201 // Dynamic register class that selects between long_reg and long_reg_no_ebp. |
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202 reg_class_dynamic long_reg(long_reg_no_ebp, long_reg_with_ebp, %{ PreserveFramePointer %}); |
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203 |
| 0 | 204 // Class of integer register pairs that aligns with calling convention |
| 205 reg_class eadx_reg( EAX,EDX ); | |
| 206 reg_class ebcx_reg( ECX,EBX ); | |
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207 |
| 0 | 208 // Not AX or DX, used in divides |
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209 reg_class nadx_reg_with_ebp(EBX, ECX, ESI, EDI, EBP); |
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210 // Not AX or DX (and neither EBP), used in divides |
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211 reg_class nadx_reg_no_ebp(EBX, ECX, ESI, EDI); |
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212 // Dynamic register class that selects between nadx_reg and nadx_reg_no_ebp. |
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213 reg_class_dynamic nadx_reg(nadx_reg_no_ebp, nadx_reg_with_ebp, %{ PreserveFramePointer %}); |
| 0 | 214 |
| 215 // Floating point registers. Notice FPR0 is not a choice. | |
| 216 // FPR0 is not ever allocated; we use clever encodings to fake | |
| 217 // a 2-address instructions out of Intels FP stack. | |
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218 reg_class fp_flt_reg( FPR1L,FPR2L,FPR3L,FPR4L,FPR5L,FPR6L,FPR7L ); |
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219 |
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220 reg_class fp_dbl_reg( FPR1L,FPR1H, FPR2L,FPR2H, FPR3L,FPR3H, |
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221 FPR4L,FPR4H, FPR5L,FPR5H, FPR6L,FPR6H, |
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222 FPR7L,FPR7H ); |
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223 |
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224 reg_class fp_flt_reg0( FPR1L ); |
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225 reg_class fp_dbl_reg0( FPR1L,FPR1H ); |
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226 reg_class fp_dbl_reg1( FPR2L,FPR2H ); |
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227 reg_class fp_dbl_notreg0( FPR2L,FPR2H, FPR3L,FPR3H, FPR4L,FPR4H, |
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228 FPR5L,FPR5H, FPR6L,FPR6H, FPR7L,FPR7H ); |
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229 |
| 0 | 230 %} |
| 231 | |
| 232 | |
| 233 //----------SOURCE BLOCK------------------------------------------------------- | |
| 234 // This is a block of C++ code which provides values, functions, and | |
| 235 // definitions necessary in the rest of the architecture description | |
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236 source_hpp %{ |
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237 // Must be visible to the DFA in dfa_x86_32.cpp |
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238 extern bool is_operand_hi32_zero(Node* n); |
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239 %} |
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240 |
| 0 | 241 source %{ |
| 304 | 242 #define RELOC_IMM32 Assembler::imm_operand |
| 0 | 243 #define RELOC_DISP32 Assembler::disp32_operand |
| 244 | |
| 245 #define __ _masm. | |
| 246 | |
| 247 // How to find the high register of a Long pair, given the low register | |
| 248 #define HIGH_FROM_LOW(x) ((x)+2) | |
| 249 | |
| 250 // These masks are used to provide 128-bit aligned bitmasks to the XMM | |
| 251 // instructions, to allow sign-masking or sign-bit flipping. They allow | |
| 252 // fast versions of NegF/NegD and AbsF/AbsD. | |
| 253 | |
| 254 // Note: 'double' and 'long long' have 32-bits alignment on x86. | |
| 255 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) { | |
| 256 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address | |
| 257 // of 128-bits operands for SSE instructions. | |
| 258 jlong *operand = (jlong*)(((uintptr_t)adr)&((uintptr_t)(~0xF))); | |
| 259 // Store the value to a 128-bits operand. | |
| 260 operand[0] = lo; | |
| 261 operand[1] = hi; | |
| 262 return operand; | |
| 263 } | |
| 264 | |
| 265 // Buffer for 128-bits masks used by SSE instructions. | |
| 266 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment) | |
| 267 | |
| 268 // Static initialization during VM startup. | |
| 269 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF)); | |
| 270 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF)); | |
| 271 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000)); | |
| 272 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000)); | |
| 273 | |
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274 // Offset hacking within calls. |
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275 static int pre_call_resets_size() { |
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276 int size = 0; |
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277 Compile* C = Compile::current(); |
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278 if (C->in_24_bit_fp_mode()) { |
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279 size += 6; // fldcw |
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280 } |
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281 if (C->max_vector_size() > 16) { |
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282 size += 3; // vzeroupper |
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283 } |
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284 return size; |
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285 } |
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286 |
| 0 | 287 // !!!!! Special hack to get all type of calls to specify the byte offset |
| 288 // from the start of the call to the point where the return address | |
| 289 // will point. | |
| 290 int MachCallStaticJavaNode::ret_addr_offset() { | |
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291 return 5 + pre_call_resets_size(); // 5 bytes from start of call to where return address points |
| 0 | 292 } |
| 293 | |
| 294 int MachCallDynamicJavaNode::ret_addr_offset() { | |
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295 return 10 + pre_call_resets_size(); // 10 bytes from start of call to where return address points |
| 0 | 296 } |
| 297 | |
| 298 static int sizeof_FFree_Float_Stack_All = -1; | |
| 299 | |
| 300 int MachCallRuntimeNode::ret_addr_offset() { | |
| 301 assert(sizeof_FFree_Float_Stack_All != -1, "must have been emitted already"); | |
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302 return sizeof_FFree_Float_Stack_All + 5 + pre_call_resets_size(); |
| 0 | 303 } |
| 304 | |
| 305 // Indicate if the safepoint node needs the polling page as an input. | |
| 306 // Since x86 does have absolute addressing, it doesn't. | |
| 307 bool SafePointNode::needs_polling_address_input() { | |
| 308 return false; | |
| 309 } | |
| 310 | |
| 311 // | |
| 312 // Compute padding required for nodes which need alignment | |
| 313 // | |
| 314 | |
| 315 // The address of the call instruction needs to be 4-byte aligned to | |
| 316 // ensure that it does not span a cache line so that it can be patched. | |
| 317 int CallStaticJavaDirectNode::compute_padding(int current_offset) const { | |
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318 current_offset += pre_call_resets_size(); // skip fldcw, if any |
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319 current_offset += 1; // skip call opcode byte |
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320 return round_to(current_offset, alignment_required()) - current_offset; |
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321 } |
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322 |
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323 // The address of the call instruction needs to be 4-byte aligned to |
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324 // ensure that it does not span a cache line so that it can be patched. |
| 0 | 325 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const { |
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326 current_offset += pre_call_resets_size(); // skip fldcw, if any |
| 0 | 327 current_offset += 5; // skip MOV instruction |
| 328 current_offset += 1; // skip call opcode byte | |
| 329 return round_to(current_offset, alignment_required()) - current_offset; | |
| 330 } | |
| 331 | |
| 332 // EMIT_RM() | |
| 333 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) { | |
| 334 unsigned char c = (unsigned char)((f1 << 6) | (f2 << 3) | f3); | |
| 1748 | 335 cbuf.insts()->emit_int8(c); |
| 0 | 336 } |
| 337 | |
| 338 // EMIT_CC() | |
| 339 void emit_cc(CodeBuffer &cbuf, int f1, int f2) { | |
| 340 unsigned char c = (unsigned char)( f1 | f2 ); | |
| 1748 | 341 cbuf.insts()->emit_int8(c); |
| 0 | 342 } |
| 343 | |
| 344 // EMIT_OPCODE() | |
| 345 void emit_opcode(CodeBuffer &cbuf, int code) { | |
| 1748 | 346 cbuf.insts()->emit_int8((unsigned char) code); |
| 0 | 347 } |
| 348 | |
| 349 // EMIT_OPCODE() w/ relocation information | |
| 350 void emit_opcode(CodeBuffer &cbuf, int code, relocInfo::relocType reloc, int offset = 0) { | |
| 1748 | 351 cbuf.relocate(cbuf.insts_mark() + offset, reloc); |
| 0 | 352 emit_opcode(cbuf, code); |
| 353 } | |
| 354 | |
| 355 // EMIT_D8() | |
| 356 void emit_d8(CodeBuffer &cbuf, int d8) { | |
| 1748 | 357 cbuf.insts()->emit_int8((unsigned char) d8); |
| 0 | 358 } |
| 359 | |
| 360 // EMIT_D16() | |
| 361 void emit_d16(CodeBuffer &cbuf, int d16) { | |
| 1748 | 362 cbuf.insts()->emit_int16(d16); |
| 0 | 363 } |
| 364 | |
| 365 // EMIT_D32() | |
| 366 void emit_d32(CodeBuffer &cbuf, int d32) { | |
| 1748 | 367 cbuf.insts()->emit_int32(d32); |
| 0 | 368 } |
| 369 | |
| 370 // emit 32 bit value and construct relocation entry from relocInfo::relocType | |
| 371 void emit_d32_reloc(CodeBuffer &cbuf, int d32, relocInfo::relocType reloc, | |
| 372 int format) { | |
| 1748 | 373 cbuf.relocate(cbuf.insts_mark(), reloc, format); |
| 374 cbuf.insts()->emit_int32(d32); | |
| 0 | 375 } |
| 376 | |
| 377 // emit 32 bit value and construct relocation entry from RelocationHolder | |
| 378 void emit_d32_reloc(CodeBuffer &cbuf, int d32, RelocationHolder const& rspec, | |
| 379 int format) { | |
| 380 #ifdef ASSERT | |
| 381 if (rspec.reloc()->type() == relocInfo::oop_type && d32 != 0 && d32 != (int)Universe::non_oop_word()) { | |
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382 assert(cast_to_oop(d32)->is_oop() && (ScavengeRootsInCode || !cast_to_oop(d32)->is_scavengable()), "cannot embed scavengable oops in code"); |
| 0 | 383 } |
| 384 #endif | |
| 1748 | 385 cbuf.relocate(cbuf.insts_mark(), rspec, format); |
| 386 cbuf.insts()->emit_int32(d32); | |
| 0 | 387 } |
| 388 | |
| 389 // Access stack slot for load or store | |
| 390 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp) { | |
| 391 emit_opcode( cbuf, opcode ); // (e.g., FILD [ESP+src]) | |
| 392 if( -128 <= disp && disp <= 127 ) { | |
| 393 emit_rm( cbuf, 0x01, rm_field, ESP_enc ); // R/M byte | |
| 394 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte | |
| 395 emit_d8 (cbuf, disp); // Displacement // R/M byte | |
| 396 } else { | |
| 397 emit_rm( cbuf, 0x02, rm_field, ESP_enc ); // R/M byte | |
| 398 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte | |
| 399 emit_d32(cbuf, disp); // Displacement // R/M byte | |
| 400 } | |
| 401 } | |
| 402 | |
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403 // rRegI ereg, memory mem) %{ // emit_reg_mem |
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404 void encode_RegMem( CodeBuffer &cbuf, int reg_encoding, int base, int index, int scale, int displace, relocInfo::relocType disp_reloc ) { |
| 0 | 405 // There is no index & no scale, use form without SIB byte |
| 406 if ((index == 0x4) && | |
| 407 (scale == 0) && (base != ESP_enc)) { | |
| 408 // If no displacement, mode is 0x0; unless base is [EBP] | |
| 409 if ( (displace == 0) && (base != EBP_enc) ) { | |
| 410 emit_rm(cbuf, 0x0, reg_encoding, base); | |
| 411 } | |
| 412 else { // If 8-bit displacement, mode 0x1 | |
| 413 if ((displace >= -128) && (displace <= 127) | |
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414 && (disp_reloc == relocInfo::none) ) { |
| 0 | 415 emit_rm(cbuf, 0x1, reg_encoding, base); |
| 416 emit_d8(cbuf, displace); | |
| 417 } | |
| 418 else { // If 32-bit displacement | |
| 419 if (base == -1) { // Special flag for absolute address | |
| 420 emit_rm(cbuf, 0x0, reg_encoding, 0x5); | |
| 421 // (manual lies; no SIB needed here) | |
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422 if ( disp_reloc != relocInfo::none ) { |
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423 emit_d32_reloc(cbuf, displace, disp_reloc, 1); |
| 0 | 424 } else { |
| 425 emit_d32 (cbuf, displace); | |
| 426 } | |
| 427 } | |
| 428 else { // Normal base + offset | |
| 429 emit_rm(cbuf, 0x2, reg_encoding, base); | |
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430 if ( disp_reloc != relocInfo::none ) { |
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431 emit_d32_reloc(cbuf, displace, disp_reloc, 1); |
| 0 | 432 } else { |
| 433 emit_d32 (cbuf, displace); | |
| 434 } | |
| 435 } | |
| 436 } | |
| 437 } | |
| 438 } | |
| 439 else { // Else, encode with the SIB byte | |
| 440 // If no displacement, mode is 0x0; unless base is [EBP] | |
| 441 if (displace == 0 && (base != EBP_enc)) { // If no displacement | |
| 442 emit_rm(cbuf, 0x0, reg_encoding, 0x4); | |
| 443 emit_rm(cbuf, scale, index, base); | |
| 444 } | |
| 445 else { // If 8-bit displacement, mode 0x1 | |
| 446 if ((displace >= -128) && (displace <= 127) | |
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447 && (disp_reloc == relocInfo::none) ) { |
| 0 | 448 emit_rm(cbuf, 0x1, reg_encoding, 0x4); |
| 449 emit_rm(cbuf, scale, index, base); | |
| 450 emit_d8(cbuf, displace); | |
| 451 } | |
| 452 else { // If 32-bit displacement | |
| 453 if (base == 0x04 ) { | |
| 454 emit_rm(cbuf, 0x2, reg_encoding, 0x4); | |
| 455 emit_rm(cbuf, scale, index, 0x04); | |
| 456 } else { | |
| 457 emit_rm(cbuf, 0x2, reg_encoding, 0x4); | |
| 458 emit_rm(cbuf, scale, index, base); | |
| 459 } | |
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460 if ( disp_reloc != relocInfo::none ) { |
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461 emit_d32_reloc(cbuf, displace, disp_reloc, 1); |
| 0 | 462 } else { |
| 463 emit_d32 (cbuf, displace); | |
| 464 } | |
| 465 } | |
| 466 } | |
| 467 } | |
| 468 } | |
| 469 | |
| 470 | |
| 471 void encode_Copy( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) { | |
| 472 if( dst_encoding == src_encoding ) { | |
| 473 // reg-reg copy, use an empty encoding | |
| 474 } else { | |
| 475 emit_opcode( cbuf, 0x8B ); | |
| 476 emit_rm(cbuf, 0x3, dst_encoding, src_encoding ); | |
| 477 } | |
| 478 } | |
| 479 | |
| 4759 | 480 void emit_cmpfp_fixup(MacroAssembler& _masm) { |
| 481 Label exit; | |
| 482 __ jccb(Assembler::noParity, exit); | |
| 483 __ pushf(); | |
| 484 // | |
| 485 // comiss/ucomiss instructions set ZF,PF,CF flags and | |
| 486 // zero OF,AF,SF for NaN values. | |
| 487 // Fixup flags by zeroing ZF,PF so that compare of NaN | |
| 488 // values returns 'less than' result (CF is set). | |
| 489 // Leave the rest of flags unchanged. | |
| 490 // | |
| 491 // 7 6 5 4 3 2 1 0 | |
| 492 // |S|Z|r|A|r|P|r|C| (r - reserved bit) | |
| 493 // 0 0 1 0 1 0 1 1 (0x2B) | |
| 494 // | |
| 495 __ andl(Address(rsp, 0), 0xffffff2b); | |
| 496 __ popf(); | |
| 497 __ bind(exit); | |
| 498 } | |
| 499 | |
| 500 void emit_cmpfp3(MacroAssembler& _masm, Register dst) { | |
| 501 Label done; | |
| 502 __ movl(dst, -1); | |
| 503 __ jcc(Assembler::parity, done); | |
| 504 __ jcc(Assembler::below, done); | |
| 505 __ setb(Assembler::notEqual, dst); | |
| 506 __ movzbl(dst, dst); | |
| 507 __ bind(done); | |
| 0 | 508 } |
| 509 | |
| 510 | |
| 511 //============================================================================= | |
| 2008 | 512 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty; |
| 513 | |
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514 int Compile::ConstantTable::calculate_table_base_offset() const { |
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515 return 0; // absolute addressing, no offset |
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516 } |
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517 |
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518 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; } |
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519 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) { |
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520 ShouldNotReachHere(); |
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521 } |
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522 |
| 2008 | 523 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const { |
| 524 // Empty encoding | |
| 525 } | |
| 526 | |
| 527 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const { | |
| 528 return 0; | |
| 529 } | |
| 530 | |
| 531 #ifndef PRODUCT | |
| 532 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const { | |
| 533 st->print("# MachConstantBaseNode (empty encoding)"); | |
| 534 } | |
| 535 #endif | |
| 536 | |
| 537 | |
| 538 //============================================================================= | |
| 0 | 539 #ifndef PRODUCT |
|
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540 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const { |
| 0 | 541 Compile* C = ra_->C; |
| 542 | |
|
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543 int framesize = C->frame_size_in_bytes(); |
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544 int bangsize = C->bang_size_in_bytes(); |
| 0 | 545 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); |
|
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546 // Remove wordSize for return addr which is already pushed. |
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547 framesize -= wordSize; |
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548 |
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549 if (C->need_stack_bang(bangsize)) { |
| 0 | 550 framesize -= wordSize; |
|
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551 st->print("# stack bang (%d bytes)", bangsize); |
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552 st->print("\n\t"); |
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553 st->print("PUSH EBP\t# Save EBP"); |
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554 if (PreserveFramePointer) { |
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555 st->print("\n\t"); |
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556 st->print("MOV EBP, ESP\t# Save the caller's SP into EBP"); |
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557 } |
| 0 | 558 if (framesize) { |
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559 st->print("\n\t"); |
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560 st->print("SUB ESP, #%d\t# Create frame",framesize); |
| 0 | 561 } |
| 562 } else { | |
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563 st->print("SUB ESP, #%d\t# Create frame",framesize); |
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564 st->print("\n\t"); |
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565 framesize -= wordSize; |
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566 st->print("MOV [ESP + #%d], EBP\t# Save EBP",framesize); |
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567 if (PreserveFramePointer) { |
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568 st->print("\n\t"); |
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569 st->print("MOV EBP, ESP\t# Save the caller's SP into EBP"); |
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570 if (framesize > 0) { |
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571 st->print("\n\t"); |
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572 st->print("ADD EBP, #%d", framesize); |
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573 } |
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574 } |
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575 } |
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576 |
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577 if (VerifyStackAtCalls) { |
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578 st->print("\n\t"); |
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579 framesize -= wordSize; |
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580 st->print("MOV [ESP + #%d], 0xBADB100D\t# Majik cookie for stack depth check",framesize); |
| 0 | 581 } |
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582 |
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583 if( C->in_24_bit_fp_mode() ) { |
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584 st->print("\n\t"); |
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585 st->print("FLDCW \t# load 24 bit fpu control word"); |
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586 } |
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587 if (UseSSE >= 2 && VerifyFPU) { |
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588 st->print("\n\t"); |
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589 st->print("# verify FPU stack (must be clean on entry)"); |
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590 } |
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591 |
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592 #ifdef ASSERT |
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593 if (VerifyStackAtCalls) { |
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594 st->print("\n\t"); |
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595 st->print("# stack alignment check"); |
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596 } |
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597 #endif |
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598 st->cr(); |
| 0 | 599 } |
| 600 #endif | |
| 601 | |
| 602 | |
| 603 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 604 Compile* C = ra_->C; | |
|
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605 MacroAssembler _masm(&cbuf); |
| 0 | 606 |
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607 int framesize = C->frame_size_in_bytes(); |
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608 int bangsize = C->bang_size_in_bytes(); |
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609 |
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610 __ verified_entry(framesize, C->need_stack_bang(bangsize)?bangsize:0, C->in_24_bit_fp_mode()); |
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611 |
| 1748 | 612 C->set_frame_complete(cbuf.insts_size()); |
| 0 | 613 |
|
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614 if (C->has_mach_constant_base_node()) { |
|
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615 // NOTE: We set the table base offset here because users might be |
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616 // emitted before MachConstantBaseNode. |
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617 Compile::ConstantTable& constant_table = C->constant_table(); |
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618 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset()); |
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619 } |
| 0 | 620 } |
| 621 | |
| 622 uint MachPrologNode::size(PhaseRegAlloc *ra_) const { | |
| 623 return MachNode::size(ra_); // too many variables; just compute it the hard way | |
| 624 } | |
| 625 | |
| 626 int MachPrologNode::reloc() const { | |
| 627 return 0; // a large enough number | |
| 628 } | |
| 629 | |
| 630 //============================================================================= | |
| 631 #ifndef PRODUCT | |
| 632 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream* st ) const { | |
| 633 Compile *C = ra_->C; | |
|
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634 int framesize = C->frame_size_in_bytes(); |
| 0 | 635 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); |
| 636 // Remove two words for return addr and rbp, | |
| 637 framesize -= 2*wordSize; | |
| 638 | |
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639 if (C->max_vector_size() > 16) { |
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640 st->print("VZEROUPPER"); |
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641 st->cr(); st->print("\t"); |
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642 } |
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643 if (C->in_24_bit_fp_mode()) { |
| 0 | 644 st->print("FLDCW standard control word"); |
| 645 st->cr(); st->print("\t"); | |
| 646 } | |
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647 if (framesize) { |
| 0 | 648 st->print("ADD ESP,%d\t# Destroy frame",framesize); |
| 649 st->cr(); st->print("\t"); | |
| 650 } | |
| 651 st->print_cr("POPL EBP"); st->print("\t"); | |
|
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652 if (do_polling() && C->is_method_compilation()) { |
| 0 | 653 st->print("TEST PollPage,EAX\t! Poll Safepoint"); |
| 654 st->cr(); st->print("\t"); | |
| 655 } | |
| 656 } | |
| 657 #endif | |
| 658 | |
| 659 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 660 Compile *C = ra_->C; | |
| 661 | |
|
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662 if (C->max_vector_size() > 16) { |
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663 // Clear upper bits of YMM registers when current compiled code uses |
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664 // wide vectors to avoid AVX <-> SSE transition penalty during call. |
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665 MacroAssembler masm(&cbuf); |
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666 masm.vzeroupper(); |
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667 } |
| 0 | 668 // If method set FPU control word, restore to standard control word |
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669 if (C->in_24_bit_fp_mode()) { |
| 0 | 670 MacroAssembler masm(&cbuf); |
| 671 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); | |
| 672 } | |
| 673 | |
|
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674 int framesize = C->frame_size_in_bytes(); |
| 0 | 675 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); |
| 676 // Remove two words for return addr and rbp, | |
| 677 framesize -= 2*wordSize; | |
| 678 | |
| 679 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here | |
| 680 | |
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681 if (framesize >= 128) { |
| 0 | 682 emit_opcode(cbuf, 0x81); // add SP, #framesize |
| 683 emit_rm(cbuf, 0x3, 0x00, ESP_enc); | |
| 684 emit_d32(cbuf, framesize); | |
|
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685 } else if (framesize) { |
| 0 | 686 emit_opcode(cbuf, 0x83); // add SP, #framesize |
| 687 emit_rm(cbuf, 0x3, 0x00, ESP_enc); | |
| 688 emit_d8(cbuf, framesize); | |
| 689 } | |
| 690 | |
| 691 emit_opcode(cbuf, 0x58 | EBP_enc); | |
| 692 | |
|
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693 if (do_polling() && C->is_method_compilation()) { |
| 1748 | 694 cbuf.relocate(cbuf.insts_end(), relocInfo::poll_return_type, 0); |
| 0 | 695 emit_opcode(cbuf,0x85); |
| 696 emit_rm(cbuf, 0x0, EAX_enc, 0x5); // EAX | |
| 697 emit_d32(cbuf, (intptr_t)os::get_polling_page()); | |
| 698 } | |
| 699 } | |
| 700 | |
| 701 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const { | |
| 702 Compile *C = ra_->C; | |
| 703 // If method set FPU control word, restore to standard control word | |
| 704 int size = C->in_24_bit_fp_mode() ? 6 : 0; | |
|
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705 if (C->max_vector_size() > 16) size += 3; // vzeroupper |
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706 if (do_polling() && C->is_method_compilation()) size += 6; |
| 0 | 707 |
|
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708 int framesize = C->frame_size_in_bytes(); |
| 0 | 709 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); |
| 710 // Remove two words for return addr and rbp, | |
| 711 framesize -= 2*wordSize; | |
| 712 | |
| 713 size++; // popl rbp, | |
| 714 | |
|
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|
715 if (framesize >= 128) { |
| 0 | 716 size += 6; |
| 717 } else { | |
| 718 size += framesize ? 3 : 0; | |
| 719 } | |
| 720 return size; | |
| 721 } | |
| 722 | |
| 723 int MachEpilogNode::reloc() const { | |
| 724 return 0; // a large enough number | |
| 725 } | |
| 726 | |
| 727 const Pipeline * MachEpilogNode::pipeline() const { | |
| 728 return MachNode::pipeline_class(); | |
| 729 } | |
| 730 | |
| 731 int MachEpilogNode::safepoint_offset() const { return 0; } | |
| 732 | |
| 733 //============================================================================= | |
| 734 | |
| 735 enum RC { rc_bad, rc_int, rc_float, rc_xmm, rc_stack }; | |
| 736 static enum RC rc_class( OptoReg::Name reg ) { | |
| 737 | |
| 738 if( !OptoReg::is_valid(reg) ) return rc_bad; | |
| 739 if (OptoReg::is_stack(reg)) return rc_stack; | |
| 740 | |
| 741 VMReg r = OptoReg::as_VMReg(reg); | |
| 742 if (r->is_Register()) return rc_int; | |
| 743 if (r->is_FloatRegister()) { | |
| 744 assert(UseSSE < 2, "shouldn't be used in SSE2+ mode"); | |
| 745 return rc_float; | |
| 746 } | |
| 747 assert(r->is_XMMRegister(), "must be"); | |
| 748 return rc_xmm; | |
| 749 } | |
| 750 | |
|
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751 static int impl_helper( CodeBuffer *cbuf, bool do_size, bool is_load, int offset, int reg, |
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752 int opcode, const char *op_str, int size, outputStream* st ) { |
| 0 | 753 if( cbuf ) { |
| 754 emit_opcode (*cbuf, opcode ); | |
|
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755 encode_RegMem(*cbuf, Matcher::_regEncode[reg], ESP_enc, 0x4, 0, offset, relocInfo::none); |
| 0 | 756 #ifndef PRODUCT |
| 757 } else if( !do_size ) { | |
|
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758 if( size != 0 ) st->print("\n\t"); |
| 0 | 759 if( opcode == 0x8B || opcode == 0x89 ) { // MOV |
|
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760 if( is_load ) st->print("%s %s,[ESP + #%d]",op_str,Matcher::regName[reg],offset); |
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761 else st->print("%s [ESP + #%d],%s",op_str,offset,Matcher::regName[reg]); |
| 0 | 762 } else { // FLD, FST, PUSH, POP |
|
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763 st->print("%s [ESP + #%d]",op_str,offset); |
| 0 | 764 } |
| 765 #endif | |
| 766 } | |
| 767 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4); | |
| 768 return size+3+offset_size; | |
| 769 } | |
| 770 | |
| 771 // Helper for XMM registers. Extra opcode bits, limited syntax. | |
| 772 static int impl_x_helper( CodeBuffer *cbuf, bool do_size, bool is_load, | |
|
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773 int offset, int reg_lo, int reg_hi, int size, outputStream* st ) { |
| 4759 | 774 if (cbuf) { |
| 775 MacroAssembler _masm(cbuf); | |
| 776 if (reg_lo+1 == reg_hi) { // double move? | |
| 777 if (is_load) { | |
| 778 __ movdbl(as_XMMRegister(Matcher::_regEncode[reg_lo]), Address(rsp, offset)); | |
| 779 } else { | |
| 780 __ movdbl(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[reg_lo])); | |
| 781 } | |
| 0 | 782 } else { |
| 4759 | 783 if (is_load) { |
| 784 __ movflt(as_XMMRegister(Matcher::_regEncode[reg_lo]), Address(rsp, offset)); | |
| 785 } else { | |
| 786 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[reg_lo])); | |
| 787 } | |
| 0 | 788 } |
| 789 #ifndef PRODUCT | |
| 4759 | 790 } else if (!do_size) { |
| 791 if (size != 0) st->print("\n\t"); | |
| 792 if (reg_lo+1 == reg_hi) { // double move? | |
| 793 if (is_load) st->print("%s %s,[ESP + #%d]", | |
| 794 UseXmmLoadAndClearUpper ? "MOVSD " : "MOVLPD", | |
| 795 Matcher::regName[reg_lo], offset); | |
| 796 else st->print("MOVSD [ESP + #%d],%s", | |
| 797 offset, Matcher::regName[reg_lo]); | |
| 0 | 798 } else { |
| 4759 | 799 if (is_load) st->print("MOVSS %s,[ESP + #%d]", |
| 800 Matcher::regName[reg_lo], offset); | |
| 801 else st->print("MOVSS [ESP + #%d],%s", | |
| 802 offset, Matcher::regName[reg_lo]); | |
| 0 | 803 } |
| 804 #endif | |
| 805 } | |
| 806 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4); | |
|
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807 // VEX_2bytes prefix is used if UseAVX > 0, so it takes the same 2 bytes as SIMD prefix. |
| 0 | 808 return size+5+offset_size; |
| 809 } | |
| 810 | |
| 811 | |
| 812 static int impl_movx_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo, | |
|
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813 int src_hi, int dst_hi, int size, outputStream* st ) { |
| 4759 | 814 if (cbuf) { |
| 815 MacroAssembler _masm(cbuf); | |
| 816 if (src_lo+1 == src_hi && dst_lo+1 == dst_hi) { // double move? | |
| 817 __ movdbl(as_XMMRegister(Matcher::_regEncode[dst_lo]), | |
| 818 as_XMMRegister(Matcher::_regEncode[src_lo])); | |
| 819 } else { | |
| 820 __ movflt(as_XMMRegister(Matcher::_regEncode[dst_lo]), | |
| 821 as_XMMRegister(Matcher::_regEncode[src_lo])); | |
| 822 } | |
| 0 | 823 #ifndef PRODUCT |
| 4759 | 824 } else if (!do_size) { |
| 825 if (size != 0) st->print("\n\t"); | |
| 826 if (UseXmmRegToRegMoveAll) {//Use movaps,movapd to move between xmm registers | |
| 827 if (src_lo+1 == src_hi && dst_lo+1 == dst_hi) { // double move? | |
|
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828 st->print("MOVAPD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]); |
| 0 | 829 } else { |
|
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830 st->print("MOVAPS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]); |
| 0 | 831 } |
| 4759 | 832 } else { |
| 0 | 833 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move? |
|
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834 st->print("MOVSD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]); |
| 0 | 835 } else { |
|
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836 st->print("MOVSS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]); |
| 0 | 837 } |
| 4759 | 838 } |
| 0 | 839 #endif |
| 840 } | |
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841 // VEX_2bytes prefix is used if UseAVX > 0, and it takes the same 2 bytes as SIMD prefix. |
| 4759 | 842 // Only MOVAPS SSE prefix uses 1 byte. |
| 843 int sz = 4; | |
| 844 if (!(src_lo+1 == src_hi && dst_lo+1 == dst_hi) && | |
| 845 UseXmmRegToRegMoveAll && (UseAVX == 0)) sz = 3; | |
| 846 return size + sz; | |
| 0 | 847 } |
| 848 | |
|
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849 static int impl_movgpr2x_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo, |
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850 int src_hi, int dst_hi, int size, outputStream* st ) { |
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851 // 32-bit |
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852 if (cbuf) { |
| 4759 | 853 MacroAssembler _masm(cbuf); |
| 854 __ movdl(as_XMMRegister(Matcher::_regEncode[dst_lo]), | |
| 855 as_Register(Matcher::_regEncode[src_lo])); | |
|
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856 #ifndef PRODUCT |
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857 } else if (!do_size) { |
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858 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]); |
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859 #endif |
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860 } |
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861 return 4; |
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862 } |
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863 |
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864 |
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865 static int impl_movx2gpr_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo, |
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866 int src_hi, int dst_hi, int size, outputStream* st ) { |
|
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867 // 32-bit |
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868 if (cbuf) { |
| 4759 | 869 MacroAssembler _masm(cbuf); |
| 870 __ movdl(as_Register(Matcher::_regEncode[dst_lo]), | |
| 871 as_XMMRegister(Matcher::_regEncode[src_lo])); | |
|
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872 #ifndef PRODUCT |
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873 } else if (!do_size) { |
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874 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]); |
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875 #endif |
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876 } |
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877 return 4; |
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878 } |
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879 |
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880 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int size, outputStream* st ) { |
| 0 | 881 if( cbuf ) { |
| 882 emit_opcode(*cbuf, 0x8B ); | |
| 883 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst], Matcher::_regEncode[src] ); | |
| 884 #ifndef PRODUCT | |
| 885 } else if( !do_size ) { | |
|
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886 if( size != 0 ) st->print("\n\t"); |
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887 st->print("MOV %s,%s",Matcher::regName[dst],Matcher::regName[src]); |
| 0 | 888 #endif |
| 889 } | |
| 890 return size+2; | |
| 891 } | |
| 892 | |
|
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893 static int impl_fp_store_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int src_hi, int dst_lo, int dst_hi, |
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894 int offset, int size, outputStream* st ) { |
| 0 | 895 if( src_lo != FPR1L_num ) { // Move value to top of FP stack, if not already there |
| 896 if( cbuf ) { | |
| 897 emit_opcode( *cbuf, 0xD9 ); // FLD (i.e., push it) | |
| 898 emit_d8( *cbuf, 0xC0-1+Matcher::_regEncode[src_lo] ); | |
| 899 #ifndef PRODUCT | |
| 900 } else if( !do_size ) { | |
|
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901 if( size != 0 ) st->print("\n\t"); |
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902 st->print("FLD %s",Matcher::regName[src_lo]); |
| 0 | 903 #endif |
| 904 } | |
| 905 size += 2; | |
| 906 } | |
| 907 | |
| 908 int st_op = (src_lo != FPR1L_num) ? EBX_num /*store & pop*/ : EDX_num /*store no pop*/; | |
| 909 const char *op_str; | |
| 910 int op; | |
| 911 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double store? | |
| 912 op_str = (src_lo != FPR1L_num) ? "FSTP_D" : "FST_D "; | |
| 913 op = 0xDD; | |
| 914 } else { // 32-bit store | |
| 915 op_str = (src_lo != FPR1L_num) ? "FSTP_S" : "FST_S "; | |
| 916 op = 0xD9; | |
| 917 assert( !OptoReg::is_valid(src_hi) && !OptoReg::is_valid(dst_hi), "no non-adjacent float-stores" ); | |
| 918 } | |
| 919 | |
|
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920 return impl_helper(cbuf,do_size,false,offset,st_op,op,op_str,size, st); |
| 0 | 921 } |
| 922 | |
|
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923 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad. |
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924 static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo, |
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925 int src_hi, int dst_hi, uint ireg, outputStream* st); |
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926 |
|
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927 static int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load, |
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928 int stack_offset, int reg, uint ireg, outputStream* st); |
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929 |
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930 static int vec_stack_to_stack_helper(CodeBuffer *cbuf, bool do_size, int src_offset, |
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931 int dst_offset, uint ireg, outputStream* st) { |
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932 int calc_size = 0; |
|
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933 int src_offset_size = (src_offset == 0) ? 0 : ((src_offset < 0x80) ? 1 : 4); |
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934 int dst_offset_size = (dst_offset == 0) ? 0 : ((dst_offset < 0x80) ? 1 : 4); |
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935 switch (ireg) { |
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936 case Op_VecS: |
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937 calc_size = 3+src_offset_size + 3+dst_offset_size; |
|
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938 break; |
|
8c92982cbbc4
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939 case Op_VecD: |
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940 calc_size = 3+src_offset_size + 3+dst_offset_size; |
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941 src_offset += 4; |
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942 dst_offset += 4; |
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943 src_offset_size = (src_offset == 0) ? 0 : ((src_offset < 0x80) ? 1 : 4); |
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944 dst_offset_size = (dst_offset == 0) ? 0 : ((dst_offset < 0x80) ? 1 : 4); |
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945 calc_size += 3+src_offset_size + 3+dst_offset_size; |
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946 break; |
|
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947 case Op_VecX: |
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948 calc_size = 6 + 6 + 5+src_offset_size + 5+dst_offset_size; |
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|
949 break; |
|
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|
950 case Op_VecY: |
|
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|
951 calc_size = 6 + 6 + 5+src_offset_size + 5+dst_offset_size; |
|
8c92982cbbc4
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|
952 break; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
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parents:
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diff
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|
953 default: |
|
8c92982cbbc4
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|
954 ShouldNotReachHere(); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
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|
955 } |
|
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|
956 if (cbuf) { |
|
8c92982cbbc4
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|
957 MacroAssembler _masm(cbuf); |
|
8c92982cbbc4
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|
958 int offset = __ offset(); |
|
8c92982cbbc4
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|
959 switch (ireg) { |
|
8c92982cbbc4
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kvn
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|
960 case Op_VecS: |
|
8c92982cbbc4
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kvn
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|
961 __ pushl(Address(rsp, src_offset)); |
|
8c92982cbbc4
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|
962 __ popl (Address(rsp, dst_offset)); |
|
8c92982cbbc4
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kvn
parents:
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|
963 break; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
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parents:
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|
964 case Op_VecD: |
|
8c92982cbbc4
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kvn
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|
965 __ pushl(Address(rsp, src_offset)); |
|
8c92982cbbc4
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|
966 __ popl (Address(rsp, dst_offset)); |
|
8c92982cbbc4
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|
967 __ pushl(Address(rsp, src_offset+4)); |
|
8c92982cbbc4
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|
968 __ popl (Address(rsp, dst_offset+4)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
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|
969 break; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
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|
970 case Op_VecX: |
|
8c92982cbbc4
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|
971 __ movdqu(Address(rsp, -16), xmm0); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
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|
972 __ movdqu(xmm0, Address(rsp, src_offset)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
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|
973 __ movdqu(Address(rsp, dst_offset), xmm0); |
|
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|
974 __ movdqu(xmm0, Address(rsp, -16)); |
|
8c92982cbbc4
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kvn
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|
975 break; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
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|
976 case Op_VecY: |
|
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7119644: Increase superword's vector size up to 256 bits
kvn
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|
977 __ vmovdqu(Address(rsp, -32), xmm0); |
|
8c92982cbbc4
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|
978 __ vmovdqu(xmm0, Address(rsp, src_offset)); |
|
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|
979 __ vmovdqu(Address(rsp, dst_offset), xmm0); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
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|
980 __ vmovdqu(xmm0, Address(rsp, -32)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
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|
981 break; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
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diff
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|
982 default: |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
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|
983 ShouldNotReachHere(); |
|
8c92982cbbc4
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|
984 } |
|
8c92982cbbc4
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|
985 int size = __ offset() - offset; |
|
8c92982cbbc4
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|
986 assert(size == calc_size, "incorrect size calculattion"); |
|
8c92982cbbc4
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|
987 return size; |
|
8c92982cbbc4
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|
988 #ifndef PRODUCT |
|
8c92982cbbc4
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|
989 } else if (!do_size) { |
|
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|
990 switch (ireg) { |
|
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|
991 case Op_VecS: |
|
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|
992 st->print("pushl [rsp + #%d]\t# 32-bit mem-mem spill\n\t" |
|
8c92982cbbc4
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|
993 "popl [rsp + #%d]", |
|
8c92982cbbc4
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|
994 src_offset, dst_offset); |
|
8c92982cbbc4
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|
995 break; |
|
8c92982cbbc4
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|
996 case Op_VecD: |
|
8c92982cbbc4
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|
997 st->print("pushl [rsp + #%d]\t# 64-bit mem-mem spill\n\t" |
|
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|
998 "popq [rsp + #%d]\n\t" |
|
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|
999 "pushl [rsp + #%d]\n\t" |
|
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1000 "popq [rsp + #%d]", |
|
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1001 src_offset, dst_offset, src_offset+4, dst_offset+4); |
|
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|
1002 break; |
|
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|
1003 case Op_VecX: |
|
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|
1004 st->print("movdqu [rsp - #16], xmm0\t# 128-bit mem-mem spill\n\t" |
|
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1005 "movdqu xmm0, [rsp + #%d]\n\t" |
|
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1006 "movdqu [rsp + #%d], xmm0\n\t" |
|
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1007 "movdqu xmm0, [rsp - #16]", |
|
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|
1008 src_offset, dst_offset); |
|
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|
1009 break; |
|
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|
1010 case Op_VecY: |
|
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|
1011 st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t" |
|
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1012 "vmovdqu xmm0, [rsp + #%d]\n\t" |
|
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1013 "vmovdqu [rsp + #%d], xmm0\n\t" |
|
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1014 "vmovdqu xmm0, [rsp - #32]", |
|
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1015 src_offset, dst_offset); |
|
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|
1016 break; |
|
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|
1017 default: |
|
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|
1018 ShouldNotReachHere(); |
|
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|
1019 } |
|
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|
1020 #endif |
|
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|
1021 } |
|
8c92982cbbc4
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|
1022 return calc_size; |
|
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|
1023 } |
|
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|
1024 |
| 0 | 1025 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const { |
| 1026 // Get registers to move | |
| 1027 OptoReg::Name src_second = ra_->get_reg_second(in(1)); | |
| 1028 OptoReg::Name src_first = ra_->get_reg_first(in(1)); | |
| 1029 OptoReg::Name dst_second = ra_->get_reg_second(this ); | |
| 1030 OptoReg::Name dst_first = ra_->get_reg_first(this ); | |
| 1031 | |
| 1032 enum RC src_second_rc = rc_class(src_second); | |
| 1033 enum RC src_first_rc = rc_class(src_first); | |
| 1034 enum RC dst_second_rc = rc_class(dst_second); | |
| 1035 enum RC dst_first_rc = rc_class(dst_first); | |
| 1036 | |
| 1037 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" ); | |
| 1038 | |
| 1039 // Generate spill code! | |
| 1040 int size = 0; | |
| 1041 | |
| 1042 if( src_first == dst_first && src_second == dst_second ) | |
| 1043 return size; // Self copy, no move | |
| 1044 | |
|
6179
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1045 if (bottom_type()->isa_vect() != NULL) { |
|
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1046 uint ireg = ideal_reg(); |
|
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1047 assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity"); |
|
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1048 assert((src_first_rc != rc_float && dst_first_rc != rc_float), "sanity"); |
|
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1049 assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY), "sanity"); |
|
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1050 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) { |
|
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|
1051 // mem -> mem |
|
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|
1052 int src_offset = ra_->reg2offset(src_first); |
|
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1053 int dst_offset = ra_->reg2offset(dst_first); |
|
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1054 return vec_stack_to_stack_helper(cbuf, do_size, src_offset, dst_offset, ireg, st); |
|
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|
1055 } else if (src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) { |
|
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1056 return vec_mov_helper(cbuf, do_size, src_first, dst_first, src_second, dst_second, ireg, st); |
|
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1057 } else if (src_first_rc == rc_xmm && dst_first_rc == rc_stack ) { |
|
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1058 int stack_offset = ra_->reg2offset(dst_first); |
|
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1059 return vec_spill_helper(cbuf, do_size, false, stack_offset, src_first, ireg, st); |
|
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1060 } else if (src_first_rc == rc_stack && dst_first_rc == rc_xmm ) { |
|
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1061 int stack_offset = ra_->reg2offset(src_first); |
|
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1062 return vec_spill_helper(cbuf, do_size, true, stack_offset, dst_first, ireg, st); |
|
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1063 } else { |
|
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|
1064 ShouldNotReachHere(); |
|
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|
1065 } |
|
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|
1066 } |
|
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|
1067 |
| 0 | 1068 // -------------------------------------- |
| 1069 // Check for mem-mem move. push/pop to move. | |
| 1070 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) { | |
| 1071 if( src_second == dst_first ) { // overlapping stack copy ranges | |
| 1072 assert( src_second_rc == rc_stack && dst_second_rc == rc_stack, "we only expect a stk-stk copy here" ); | |
|
415
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|
1073 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st); |
|
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403
diff
changeset
|
1074 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st); |
| 0 | 1075 src_second_rc = dst_second_rc = rc_bad; // flag as already moved the second bits |
| 1076 } | |
| 1077 // move low bits | |
|
415
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|
1078 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),ESI_num,0xFF,"PUSH ",size, st); |
|
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diff
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|
1079 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),EAX_num,0x8F,"POP ",size, st); |
| 0 | 1080 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { // mov second bits |
|
415
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diff
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|
1081 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st); |
|
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diff
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|
1082 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st); |
| 0 | 1083 } |
| 1084 return size; | |
| 1085 } | |
| 1086 | |
| 1087 // -------------------------------------- | |
| 1088 // Check for integer reg-reg copy | |
| 1089 if( src_first_rc == rc_int && dst_first_rc == rc_int ) | |
|
415
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changeset
|
1090 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,size, st); |
| 0 | 1091 |
| 1092 // Check for integer store | |
| 1093 if( src_first_rc == rc_int && dst_first_rc == rc_stack ) | |
|
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1094 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first,0x89,"MOV ",size, st); |
| 0 | 1095 |
| 1096 // Check for integer load | |
| 1097 if( dst_first_rc == rc_int && src_first_rc == rc_stack ) | |
|
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1098 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first,0x8B,"MOV ",size, st); |
| 0 | 1099 |
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1100 // Check for integer reg-xmm reg copy |
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1101 if( src_first_rc == rc_int && dst_first_rc == rc_xmm ) { |
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1102 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad), |
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1103 "no 64 bit integer-float reg moves" ); |
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1104 return impl_movgpr2x_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st); |
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1105 } |
| 0 | 1106 // -------------------------------------- |
| 1107 // Check for float reg-reg copy | |
| 1108 if( src_first_rc == rc_float && dst_first_rc == rc_float ) { | |
| 1109 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) || | |
| 1110 (src_first+1 == src_second && dst_first+1 == dst_second), "no non-adjacent float-moves" ); | |
| 1111 if( cbuf ) { | |
| 1112 | |
| 1113 // Note the mucking with the register encode to compensate for the 0/1 | |
| 1114 // indexing issue mentioned in a comment in the reg_def sections | |
| 1115 // for FPR registers many lines above here. | |
| 1116 | |
| 1117 if( src_first != FPR1L_num ) { | |
| 1118 emit_opcode (*cbuf, 0xD9 ); // FLD ST(i) | |
| 1119 emit_d8 (*cbuf, 0xC0+Matcher::_regEncode[src_first]-1 ); | |
| 1120 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i) | |
| 1121 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] ); | |
| 1122 } else { | |
| 1123 emit_opcode (*cbuf, 0xDD ); // FST ST(i) | |
| 1124 emit_d8 (*cbuf, 0xD0+Matcher::_regEncode[dst_first]-1 ); | |
| 1125 } | |
| 1126 #ifndef PRODUCT | |
| 1127 } else if( !do_size ) { | |
| 1128 if( size != 0 ) st->print("\n\t"); | |
| 1129 if( src_first != FPR1L_num ) st->print("FLD %s\n\tFSTP %s",Matcher::regName[src_first],Matcher::regName[dst_first]); | |
| 1130 else st->print( "FST %s", Matcher::regName[dst_first]); | |
| 1131 #endif | |
| 1132 } | |
| 1133 return size + ((src_first != FPR1L_num) ? 2+2 : 2); | |
| 1134 } | |
| 1135 | |
| 1136 // Check for float store | |
| 1137 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) { | |
|
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1138 return impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,ra_->reg2offset(dst_first),size, st); |
| 0 | 1139 } |
| 1140 | |
| 1141 // Check for float load | |
| 1142 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) { | |
| 1143 int offset = ra_->reg2offset(src_first); | |
| 1144 const char *op_str; | |
| 1145 int op; | |
| 1146 if( src_first+1 == src_second && dst_first+1 == dst_second ) { // double load? | |
| 1147 op_str = "FLD_D"; | |
| 1148 op = 0xDD; | |
| 1149 } else { // 32-bit load | |
| 1150 op_str = "FLD_S"; | |
| 1151 op = 0xD9; | |
| 1152 assert( src_second_rc == rc_bad && dst_second_rc == rc_bad, "no non-adjacent float-loads" ); | |
| 1153 } | |
| 1154 if( cbuf ) { | |
| 1155 emit_opcode (*cbuf, op ); | |
|
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1156 encode_RegMem(*cbuf, 0x0, ESP_enc, 0x4, 0, offset, relocInfo::none); |
| 0 | 1157 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i) |
| 1158 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] ); | |
| 1159 #ifndef PRODUCT | |
| 1160 } else if( !do_size ) { | |
| 1161 if( size != 0 ) st->print("\n\t"); | |
| 1162 st->print("%s ST,[ESP + #%d]\n\tFSTP %s",op_str, offset,Matcher::regName[dst_first]); | |
| 1163 #endif | |
| 1164 } | |
| 1165 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4); | |
| 1166 return size + 3+offset_size+2; | |
| 1167 } | |
| 1168 | |
| 1169 // Check for xmm reg-reg copy | |
| 1170 if( src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) { | |
| 1171 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) || | |
| 1172 (src_first+1 == src_second && dst_first+1 == dst_second), | |
| 1173 "no non-adjacent float-moves" ); | |
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1174 return impl_movx_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st); |
| 0 | 1175 } |
| 1176 | |
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1177 // Check for xmm reg-integer reg copy |
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1178 if( src_first_rc == rc_xmm && dst_first_rc == rc_int ) { |
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1179 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad), |
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1180 "no 64 bit float-integer reg moves" ); |
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1181 return impl_movx2gpr_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st); |
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1182 } |
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1183 |
| 0 | 1184 // Check for xmm store |
| 1185 if( src_first_rc == rc_xmm && dst_first_rc == rc_stack ) { | |
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1186 return impl_x_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first, src_second, size, st); |
| 0 | 1187 } |
| 1188 | |
| 1189 // Check for float xmm load | |
| 1190 if( dst_first_rc == rc_xmm && src_first_rc == rc_stack ) { | |
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1191 return impl_x_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first, dst_second, size, st); |
| 0 | 1192 } |
| 1193 | |
| 1194 // Copy from float reg to xmm reg | |
| 1195 if( dst_first_rc == rc_xmm && src_first_rc == rc_float ) { | |
| 1196 // copy to the top of stack from floating point reg | |
| 1197 // and use LEA to preserve flags | |
| 1198 if( cbuf ) { | |
| 1199 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP-8] | |
| 1200 emit_rm(*cbuf, 0x1, ESP_enc, 0x04); | |
| 1201 emit_rm(*cbuf, 0x0, 0x04, ESP_enc); | |
| 1202 emit_d8(*cbuf,0xF8); | |
| 1203 #ifndef PRODUCT | |
| 1204 } else if( !do_size ) { | |
| 1205 if( size != 0 ) st->print("\n\t"); | |
| 1206 st->print("LEA ESP,[ESP-8]"); | |
| 1207 #endif | |
| 1208 } | |
| 1209 size += 4; | |
| 1210 | |
|
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1211 size = impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,0,size, st); |
| 0 | 1212 |
| 1213 // Copy from the temp memory to the xmm reg. | |
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1214 size = impl_x_helper(cbuf,do_size,true ,0,dst_first, dst_second, size, st); |
| 0 | 1215 |
| 1216 if( cbuf ) { | |
| 1217 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP+8] | |
| 1218 emit_rm(*cbuf, 0x1, ESP_enc, 0x04); | |
| 1219 emit_rm(*cbuf, 0x0, 0x04, ESP_enc); | |
| 1220 emit_d8(*cbuf,0x08); | |
| 1221 #ifndef PRODUCT | |
| 1222 } else if( !do_size ) { | |
| 1223 if( size != 0 ) st->print("\n\t"); | |
| 1224 st->print("LEA ESP,[ESP+8]"); | |
| 1225 #endif | |
| 1226 } | |
| 1227 size += 4; | |
| 1228 return size; | |
| 1229 } | |
| 1230 | |
| 1231 assert( size > 0, "missed a case" ); | |
| 1232 | |
| 1233 // -------------------------------------------------------------------- | |
| 1234 // Check for second bits still needing moving. | |
| 1235 if( src_second == dst_second ) | |
| 1236 return size; // Self copy; no move | |
| 1237 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" ); | |
| 1238 | |
| 1239 // Check for second word int-int move | |
| 1240 if( src_second_rc == rc_int && dst_second_rc == rc_int ) | |
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1241 return impl_mov_helper(cbuf,do_size,src_second,dst_second,size, st); |
| 0 | 1242 |
| 1243 // Check for second word integer store | |
| 1244 if( src_second_rc == rc_int && dst_second_rc == rc_stack ) | |
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1245 return impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),src_second,0x89,"MOV ",size, st); |
| 0 | 1246 |
| 1247 // Check for second word integer load | |
| 1248 if( dst_second_rc == rc_int && src_second_rc == rc_stack ) | |
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1249 return impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),dst_second,0x8B,"MOV ",size, st); |
| 0 | 1250 |
| 1251 | |
| 1252 Unimplemented(); | |
| 1253 } | |
| 1254 | |
| 1255 #ifndef PRODUCT | |
| 4950 | 1256 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const { |
| 0 | 1257 implementation( NULL, ra_, false, st ); |
| 1258 } | |
| 1259 #endif | |
| 1260 | |
| 1261 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1262 implementation( &cbuf, ra_, false, NULL ); | |
| 1263 } | |
| 1264 | |
| 1265 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const { | |
| 1266 return implementation( NULL, ra_, true, NULL ); | |
| 1267 } | |
| 1268 | |
| 1269 | |
| 1270 //============================================================================= | |
| 1271 #ifndef PRODUCT | |
| 1272 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream* st ) const { | |
| 1273 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
| 1274 int reg = ra_->get_reg_first(this); | |
| 1275 st->print("LEA %s,[ESP + #%d]",Matcher::regName[reg],offset); | |
| 1276 } | |
| 1277 #endif | |
| 1278 | |
| 1279 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1280 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
| 1281 int reg = ra_->get_encode(this); | |
| 1282 if( offset >= 128 ) { | |
| 1283 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset] | |
| 1284 emit_rm(cbuf, 0x2, reg, 0x04); | |
| 1285 emit_rm(cbuf, 0x0, 0x04, ESP_enc); | |
| 1286 emit_d32(cbuf, offset); | |
| 1287 } | |
| 1288 else { | |
| 1289 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset] | |
| 1290 emit_rm(cbuf, 0x1, reg, 0x04); | |
| 1291 emit_rm(cbuf, 0x0, 0x04, ESP_enc); | |
| 1292 emit_d8(cbuf, offset); | |
| 1293 } | |
| 1294 } | |
| 1295 | |
| 1296 uint BoxLockNode::size(PhaseRegAlloc *ra_) const { | |
| 1297 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
| 1298 if( offset >= 128 ) { | |
| 1299 return 7; | |
| 1300 } | |
| 1301 else { | |
| 1302 return 4; | |
| 1303 } | |
| 1304 } | |
| 1305 | |
| 1306 //============================================================================= | |
| 1307 #ifndef PRODUCT | |
| 1308 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream* st ) const { | |
| 1309 st->print_cr( "CMP EAX,[ECX+4]\t# Inline cache check"); | |
| 1310 st->print_cr("\tJNE SharedRuntime::handle_ic_miss_stub"); | |
| 1311 st->print_cr("\tNOP"); | |
| 1312 st->print_cr("\tNOP"); | |
| 1313 if( !OptoBreakpoint ) | |
| 1314 st->print_cr("\tNOP"); | |
| 1315 } | |
| 1316 #endif | |
| 1317 | |
| 1318 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1319 MacroAssembler masm(&cbuf); | |
| 1320 #ifdef ASSERT | |
| 1748 | 1321 uint insts_size = cbuf.insts_size(); |
| 0 | 1322 #endif |
| 304 | 1323 masm.cmpptr(rax, Address(rcx, oopDesc::klass_offset_in_bytes())); |
| 0 | 1324 masm.jump_cc(Assembler::notEqual, |
| 1325 RuntimeAddress(SharedRuntime::get_ic_miss_stub())); | |
| 1326 /* WARNING these NOPs are critical so that verified entry point is properly | |
| 1327 aligned for patching by NativeJump::patch_verified_entry() */ | |
| 1328 int nops_cnt = 2; | |
| 1329 if( !OptoBreakpoint ) // Leave space for int3 | |
| 1330 nops_cnt += 1; | |
| 1331 masm.nop(nops_cnt); | |
| 1332 | |
| 1748 | 1333 assert(cbuf.insts_size() - insts_size == size(ra_), "checking code size of inline cache node"); |
| 0 | 1334 } |
| 1335 | |
| 1336 uint MachUEPNode::size(PhaseRegAlloc *ra_) const { | |
| 1337 return OptoBreakpoint ? 11 : 12; | |
| 1338 } | |
| 1339 | |
| 1340 | |
| 1341 //============================================================================= | |
| 1342 | |
| 1343 int Matcher::regnum_to_fpu_offset(int regnum) { | |
| 1344 return regnum - 32; // The FP registers are in the second chunk | |
| 1345 } | |
| 1346 | |
| 1347 // This is UltraSparc specific, true just means we have fast l2f conversion | |
| 1348 const bool Matcher::convL2FSupported(void) { | |
| 1349 return true; | |
| 1350 } | |
| 1351 | |
| 1352 // Is this branch offset short enough that a short branch can be used? | |
| 1353 // | |
| 1354 // NOTE: If the platform does not provide any short branch variants, then | |
| 1355 // this method should return false for offset 0. | |
| 3851 | 1356 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) { |
| 1357 // The passed offset is relative to address of the branch. | |
| 1358 // On 86 a branch displacement is calculated relative to address | |
| 1359 // of a next instruction. | |
| 1360 offset -= br_size; | |
| 1361 | |
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1362 // the short version of jmpConUCF2 contains multiple branches, |
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1363 // making the reach slightly less |
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1364 if (rule == jmpConUCF2_rule) |
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1365 return (-126 <= offset && offset <= 125); |
| 0 | 1366 return (-128 <= offset && offset <= 127); |
| 1367 } | |
| 1368 | |
| 1369 const bool Matcher::isSimpleConstant64(jlong value) { | |
| 1370 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?. | |
| 1371 return false; | |
| 1372 } | |
| 1373 | |
| 1374 // The ecx parameter to rep stos for the ClearArray node is in dwords. | |
| 1375 const bool Matcher::init_array_count_is_in_bytes = false; | |
| 1376 | |
| 1377 // Threshold size for cleararray. | |
| 1378 const int Matcher::init_array_short_size = 8 * BytesPerLong; | |
| 1379 | |
| 4047 | 1380 // Needs 2 CMOV's for longs. |
| 1381 const int Matcher::long_cmove_cost() { return 1; } | |
| 1382 | |
| 1383 // No CMOVF/CMOVD with SSE/SSE2 | |
| 1384 const int Matcher::float_cmove_cost() { return (UseSSE>=1) ? ConditionalMoveLimit : 0; } | |
| 1385 | |
|
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1386 // Does the CPU require late expand (see block.cpp for description of late expand)? |
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1387 const bool Matcher::require_postalloc_expand = false; |
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1388 |
| 0 | 1389 // Should the Matcher clone shifts on addressing modes, expecting them to |
| 1390 // be subsumed into complex addressing expressions or compute them into | |
| 1391 // registers? True for Intel but false for most RISCs | |
| 1392 const bool Matcher::clone_shift_expressions = true; | |
| 1393 | |
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1394 // Do we need to mask the count passed to shift instructions or does |
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1395 // the cpu only look at the lower 5/6 bits anyway? |
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1396 const bool Matcher::need_masked_shift_count = false; |
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1397 |
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1398 bool Matcher::narrow_oop_use_complex_address() { |
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1399 ShouldNotCallThis(); |
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1400 return true; |
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1401 } |
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1402 |
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1403 bool Matcher::narrow_klass_use_complex_address() { |
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1404 ShouldNotCallThis(); |
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1405 return true; |
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1406 } |
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1407 |
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|
1408 |
| 0 | 1409 // Is it better to copy float constants, or load them directly from memory? |
| 1410 // Intel can load a float constant from a direct address, requiring no | |
| 1411 // extra registers. Most RISCs will have to materialize an address into a | |
| 1412 // register first, so they would do better to copy the constant from stack. | |
| 1413 const bool Matcher::rematerialize_float_constants = true; | |
| 1414 | |
| 1415 // If CPU can load and store mis-aligned doubles directly then no fixup is | |
| 1416 // needed. Else we split the double into 2 integer pieces and move it | |
| 1417 // piece-by-piece. Only happens when passing doubles into C code as the | |
| 1418 // Java calling convention forces doubles to be aligned. | |
| 1419 const bool Matcher::misaligned_doubles_ok = true; | |
| 1420 | |
| 1421 | |
| 1422 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) { | |
| 1423 // Get the memory operand from the node | |
| 1424 uint numopnds = node->num_opnds(); // Virtual call for number of operands | |
| 1425 uint skipped = node->oper_input_base(); // Sum of leaves skipped so far | |
| 1426 assert( idx >= skipped, "idx too low in pd_implicit_null_fixup" ); | |
| 1427 uint opcnt = 1; // First operand | |
| 1428 uint num_edges = node->_opnds[1]->num_edges(); // leaves for first operand | |
| 1429 while( idx >= skipped+num_edges ) { | |
| 1430 skipped += num_edges; | |
| 1431 opcnt++; // Bump operand count | |
| 1432 assert( opcnt < numopnds, "Accessing non-existent operand" ); | |
| 1433 num_edges = node->_opnds[opcnt]->num_edges(); // leaves for next operand | |
| 1434 } | |
| 1435 | |
| 1436 MachOper *memory = node->_opnds[opcnt]; | |
| 1437 MachOper *new_memory = NULL; | |
| 1438 switch (memory->opcode()) { | |
| 1439 case DIRECT: | |
| 1440 case INDOFFSET32X: | |
| 1441 // No transformation necessary. | |
| 1442 return; | |
| 1443 case INDIRECT: | |
| 1444 new_memory = new (C) indirect_win95_safeOper( ); | |
| 1445 break; | |
| 1446 case INDOFFSET8: | |
| 1447 new_memory = new (C) indOffset8_win95_safeOper(memory->disp(NULL, NULL, 0)); | |
| 1448 break; | |
| 1449 case INDOFFSET32: | |
| 1450 new_memory = new (C) indOffset32_win95_safeOper(memory->disp(NULL, NULL, 0)); | |
| 1451 break; | |
| 1452 case INDINDEXOFFSET: | |
| 1453 new_memory = new (C) indIndexOffset_win95_safeOper(memory->disp(NULL, NULL, 0)); | |
| 1454 break; | |
| 1455 case INDINDEXSCALE: | |
| 1456 new_memory = new (C) indIndexScale_win95_safeOper(memory->scale()); | |
| 1457 break; | |
| 1458 case INDINDEXSCALEOFFSET: | |
| 1459 new_memory = new (C) indIndexScaleOffset_win95_safeOper(memory->scale(), memory->disp(NULL, NULL, 0)); | |
| 1460 break; | |
| 1461 case LOAD_LONG_INDIRECT: | |
| 1462 case LOAD_LONG_INDOFFSET32: | |
| 1463 // Does not use EBP as address register, use { EDX, EBX, EDI, ESI} | |
| 1464 return; | |
| 1465 default: | |
| 1466 assert(false, "unexpected memory operand in pd_implicit_null_fixup()"); | |
| 1467 return; | |
| 1468 } | |
| 1469 node->_opnds[opcnt] = new_memory; | |
| 1470 } | |
| 1471 | |
| 1472 // Advertise here if the CPU requires explicit rounding operations | |
| 1473 // to implement the UseStrictFP mode. | |
| 1474 const bool Matcher::strict_fp_requires_explicit_rounding = true; | |
| 1475 | |
|
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1476 // Are floats conerted to double when stored to stack during deoptimization? |
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1477 // On x32 it is stored with convertion only when FPU is used for floats. |
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1478 bool Matcher::float_in_double() { return (UseSSE == 0); } |
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1479 |
| 0 | 1480 // Do ints take an entire long register or just half? |
| 1481 const bool Matcher::int_in_long = false; | |
| 1482 | |
| 1483 // Return whether or not this register is ever used as an argument. This | |
| 1484 // function is used on startup to build the trampoline stubs in generateOptoStub. | |
| 1485 // Registers not mentioned will be killed by the VM call in the trampoline, and | |
| 1486 // arguments in those registers not be available to the callee. | |
| 1487 bool Matcher::can_be_java_arg( int reg ) { | |
| 1488 if( reg == ECX_num || reg == EDX_num ) return true; | |
|
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1489 if( (reg == XMM0_num || reg == XMM1_num ) && UseSSE>=1 ) return true; |
| 0 | 1490 if( (reg == XMM0b_num || reg == XMM1b_num) && UseSSE>=2 ) return true; |
| 1491 return false; | |
| 1492 } | |
| 1493 | |
| 1494 bool Matcher::is_spillable_arg( int reg ) { | |
| 1495 return can_be_java_arg(reg); | |
| 1496 } | |
| 1497 | |
|
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1498 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) { |
|
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1499 // Use hardware integer DIV instruction when |
|
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1500 // it is faster than a code which use multiply. |
|
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1501 // Only when constant divisor fits into 32 bit |
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1502 // (min_jint is excluded to get only correct |
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1503 // positive 32 bit values from negative). |
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1504 return VM_Version::has_fast_idiv() && |
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1505 (divisor == (int)divisor && divisor != min_jint); |
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1506 } |
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1507 |
| 0 | 1508 // Register for DIVI projection of divmodI |
| 1509 RegMask Matcher::divI_proj_mask() { | |
|
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1510 return EAX_REG_mask(); |
| 0 | 1511 } |
| 1512 | |
| 1513 // Register for MODI projection of divmodI | |
| 1514 RegMask Matcher::modI_proj_mask() { | |
|
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1515 return EDX_REG_mask(); |
| 0 | 1516 } |
| 1517 | |
| 1518 // Register for DIVL projection of divmodL | |
| 1519 RegMask Matcher::divL_proj_mask() { | |
| 1520 ShouldNotReachHere(); | |
| 1521 return RegMask(); | |
| 1522 } | |
| 1523 | |
| 1524 // Register for MODL projection of divmodL | |
| 1525 RegMask Matcher::modL_proj_mask() { | |
| 1526 ShouldNotReachHere(); | |
| 1527 return RegMask(); | |
| 1528 } | |
| 1529 | |
|
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1530 const RegMask Matcher::method_handle_invoke_SP_save_mask() { |
|
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1531 return NO_REG_mask(); |
|
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1532 } |
|
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1533 |
|
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1534 // Returns true if the high 32 bits of the value is known to be zero. |
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1535 bool is_operand_hi32_zero(Node* n) { |
|
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1536 int opc = n->Opcode(); |
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1537 if (opc == Op_AndL) { |
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1538 Node* o2 = n->in(2); |
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1539 if (o2->is_Con() && (o2->get_long() & 0xFFFFFFFF00000000LL) == 0LL) { |
|
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1540 return true; |
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|
1541 } |
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1542 } |
|
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1543 if (opc == Op_ConL && (n->get_long() & 0xFFFFFFFF00000000LL) == 0LL) { |
|
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1544 return true; |
|
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|
1545 } |
|
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1546 return false; |
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|
1547 } |
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|
1548 |
| 0 | 1549 %} |
| 1550 | |
| 1551 //----------ENCODING BLOCK----------------------------------------------------- | |
| 1552 // This block specifies the encoding classes used by the compiler to output | |
| 1553 // byte streams. Encoding classes generate functions which are called by | |
| 1554 // Machine Instruction Nodes in order to generate the bit encoding of the | |
| 1555 // instruction. Operands specify their base encoding interface with the | |
| 1556 // interface keyword. There are currently supported four interfaces, | |
| 1557 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an | |
| 1558 // operand to generate a function which returns its register number when | |
| 1559 // queried. CONST_INTER causes an operand to generate a function which | |
| 1560 // returns the value of the constant when queried. MEMORY_INTER causes an | |
| 1561 // operand to generate four functions which return the Base Register, the | |
| 1562 // Index Register, the Scale Value, and the Offset Value of the operand when | |
| 1563 // queried. COND_INTER causes an operand to generate six functions which | |
| 1564 // return the encoding code (ie - encoding bits for the instruction) | |
| 1565 // associated with each basic boolean condition for a conditional instruction. | |
| 1566 // Instructions specify two basic values for encoding. They use the | |
| 1567 // ins_encode keyword to specify their encoding class (which must be one of | |
| 1568 // the class names specified in the encoding block), and they use the | |
| 1569 // opcode keyword to specify, in order, their primary, secondary, and | |
| 1570 // tertiary opcode. Only the opcode sections which a particular instruction | |
| 1571 // needs for encoding need to be specified. | |
| 1572 encode %{ | |
| 1573 // Build emit functions for each basic byte or larger field in the intel | |
| 1574 // encoding scheme (opcode, rm, sib, immediate), and call them from C++ | |
| 1575 // code in the enc_class source block. Emit functions will live in the | |
| 1576 // main source block for now. In future, we can generalize this by | |
| 1577 // adding a syntax that specifies the sizes of fields in an order, | |
| 1578 // so that the adlc can build the emit functions automagically | |
|
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1579 |
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1580 // Emit primary opcode |
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1581 enc_class OpcP %{ |
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1582 emit_opcode(cbuf, $primary); |
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1583 %} |
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1584 |
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1585 // Emit secondary opcode |
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1586 enc_class OpcS %{ |
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1587 emit_opcode(cbuf, $secondary); |
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1588 %} |
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1589 |
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1590 // Emit opcode directly |
|
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1591 enc_class Opcode(immI d8) %{ |
|
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1592 emit_opcode(cbuf, $d8$$constant); |
| 0 | 1593 %} |
| 1594 | |
| 1595 enc_class SizePrefix %{ | |
| 1596 emit_opcode(cbuf,0x66); | |
| 1597 %} | |
| 1598 | |
|
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1599 enc_class RegReg (rRegI dst, rRegI src) %{ // RegReg(Many) |
| 0 | 1600 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); |
| 1601 %} | |
| 1602 | |
|
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1603 enc_class OpcRegReg (immI opcode, rRegI dst, rRegI src) %{ // OpcRegReg(Many) |
| 0 | 1604 emit_opcode(cbuf,$opcode$$constant); |
| 1605 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 1606 %} | |
| 1607 | |
|
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1608 enc_class mov_r32_imm0( rRegI dst ) %{ |
| 0 | 1609 emit_opcode( cbuf, 0xB8 + $dst$$reg ); // 0xB8+ rd -- MOV r32 ,imm32 |
| 1610 emit_d32 ( cbuf, 0x0 ); // imm32==0x0 | |
| 1611 %} | |
| 1612 | |
| 1613 enc_class cdq_enc %{ | |
| 1614 // Full implementation of Java idiv and irem; checks for | |
| 1615 // special case as described in JVM spec., p.243 & p.271. | |
| 1616 // | |
| 1617 // normal case special case | |
| 1618 // | |
| 1619 // input : rax,: dividend min_int | |
| 1620 // reg: divisor -1 | |
| 1621 // | |
| 1622 // output: rax,: quotient (= rax, idiv reg) min_int | |
| 1623 // rdx: remainder (= rax, irem reg) 0 | |
| 1624 // | |
| 1625 // Code sequnce: | |
| 1626 // | |
| 1627 // 81 F8 00 00 00 80 cmp rax,80000000h | |
| 1628 // 0F 85 0B 00 00 00 jne normal_case | |
| 1629 // 33 D2 xor rdx,edx | |
| 1630 // 83 F9 FF cmp rcx,0FFh | |
| 1631 // 0F 84 03 00 00 00 je done | |
| 1632 // normal_case: | |
| 1633 // 99 cdq | |
| 1634 // F7 F9 idiv rax,ecx | |
| 1635 // done: | |
| 1636 // | |
| 1637 emit_opcode(cbuf,0x81); emit_d8(cbuf,0xF8); | |
| 1638 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); | |
| 1639 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x80); // cmp rax,80000000h | |
| 1640 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x85); | |
| 1641 emit_opcode(cbuf,0x0B); emit_d8(cbuf,0x00); | |
| 1642 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // jne normal_case | |
| 1643 emit_opcode(cbuf,0x33); emit_d8(cbuf,0xD2); // xor rdx,edx | |
| 1644 emit_opcode(cbuf,0x83); emit_d8(cbuf,0xF9); emit_d8(cbuf,0xFF); // cmp rcx,0FFh | |
| 1645 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x84); | |
| 1646 emit_opcode(cbuf,0x03); emit_d8(cbuf,0x00); | |
| 1647 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // je done | |
| 1648 // normal_case: | |
| 1649 emit_opcode(cbuf,0x99); // cdq | |
| 1650 // idiv (note: must be emitted by the user of this rule) | |
| 1651 // normal: | |
| 1652 %} | |
| 1653 | |
| 1654 // Dense encoding for older common ops | |
|
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1655 enc_class Opc_plus(immI opcode, rRegI reg) %{ |
| 0 | 1656 emit_opcode(cbuf, $opcode$$constant + $reg$$reg); |
| 1657 %} | |
| 1658 | |
| 1659 | |
| 1660 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension | |
| 1661 enc_class OpcSE (immI imm) %{ // Emit primary opcode and set sign-extend bit | |
| 1662 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 1663 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) { | |
| 1664 emit_opcode(cbuf, $primary | 0x02); | |
| 1665 } | |
| 1666 else { // If 32-bit immediate | |
| 1667 emit_opcode(cbuf, $primary); | |
| 1668 } | |
| 1669 %} | |
| 1670 | |
|
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1671 enc_class OpcSErm (rRegI dst, immI imm) %{ // OpcSEr/m |
| 0 | 1672 // Emit primary opcode and set sign-extend bit |
| 1673 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 1674 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) { | |
| 1675 emit_opcode(cbuf, $primary | 0x02); } | |
| 1676 else { // If 32-bit immediate | |
| 1677 emit_opcode(cbuf, $primary); | |
| 1678 } | |
| 1679 // Emit r/m byte with secondary opcode, after primary opcode. | |
| 1680 emit_rm(cbuf, 0x3, $secondary, $dst$$reg); | |
| 1681 %} | |
| 1682 | |
| 1683 enc_class Con8or32 (immI imm) %{ // Con8or32(storeImmI), 8 or 32 bits | |
| 1684 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 1685 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) { | |
| 1686 $$$emit8$imm$$constant; | |
| 1687 } | |
| 1688 else { // If 32-bit immediate | |
| 1689 // Output immediate | |
| 1690 $$$emit32$imm$$constant; | |
| 1691 } | |
| 1692 %} | |
| 1693 | |
| 1694 enc_class Long_OpcSErm_Lo(eRegL dst, immL imm) %{ | |
| 1695 // Emit primary opcode and set sign-extend bit | |
| 1696 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 1697 int con = (int)$imm$$constant; // Throw away top bits | |
| 1698 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary); | |
| 1699 // Emit r/m byte with secondary opcode, after primary opcode. | |
| 1700 emit_rm(cbuf, 0x3, $secondary, $dst$$reg); | |
| 1701 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con); | |
| 1702 else emit_d32(cbuf,con); | |
| 1703 %} | |
| 1704 | |
| 1705 enc_class Long_OpcSErm_Hi(eRegL dst, immL imm) %{ | |
| 1706 // Emit primary opcode and set sign-extend bit | |
| 1707 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 1708 int con = (int)($imm$$constant >> 32); // Throw away bottom bits | |
| 1709 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary); | |
| 1710 // Emit r/m byte with tertiary opcode, after primary opcode. | |
| 1711 emit_rm(cbuf, 0x3, $tertiary, HIGH_FROM_LOW($dst$$reg)); | |
| 1712 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con); | |
| 1713 else emit_d32(cbuf,con); | |
| 1714 %} | |
| 1715 | |
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1716 enc_class OpcSReg (rRegI dst) %{ // BSWAP |
| 0 | 1717 emit_cc(cbuf, $secondary, $dst$$reg ); |
| 1718 %} | |
| 1719 | |
| 1720 enc_class bswap_long_bytes(eRegL dst) %{ // BSWAP | |
| 1721 int destlo = $dst$$reg; | |
| 1722 int desthi = HIGH_FROM_LOW(destlo); | |
| 1723 // bswap lo | |
| 1724 emit_opcode(cbuf, 0x0F); | |
| 1725 emit_cc(cbuf, 0xC8, destlo); | |
| 1726 // bswap hi | |
| 1727 emit_opcode(cbuf, 0x0F); | |
| 1728 emit_cc(cbuf, 0xC8, desthi); | |
| 1729 // xchg lo and hi | |
| 1730 emit_opcode(cbuf, 0x87); | |
| 1731 emit_rm(cbuf, 0x3, destlo, desthi); | |
| 1732 %} | |
| 1733 | |
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1734 enc_class RegOpc (rRegI div) %{ // IDIV, IMOD, JMP indirect, ... |
| 0 | 1735 emit_rm(cbuf, 0x3, $secondary, $div$$reg ); |
| 1736 %} | |
| 1737 | |
| 1738 enc_class enc_cmov(cmpOp cop ) %{ // CMOV | |
| 1739 $$$emit8$primary; | |
| 1740 emit_cc(cbuf, $secondary, $cop$$cmpcode); | |
| 1741 %} | |
| 1742 | |
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1743 enc_class enc_cmov_dpr(cmpOp cop, regDPR src ) %{ // CMOV |
| 0 | 1744 int op = 0xDA00 + $cop$$cmpcode + ($src$$reg-1); |
| 1745 emit_d8(cbuf, op >> 8 ); | |
| 1746 emit_d8(cbuf, op & 255); | |
| 1747 %} | |
| 1748 | |
| 1749 // emulate a CMOV with a conditional branch around a MOV | |
| 1750 enc_class enc_cmov_branch( cmpOp cop, immI brOffs ) %{ // CMOV | |
| 1751 // Invert sense of branch from sense of CMOV | |
| 1752 emit_cc( cbuf, 0x70, ($cop$$cmpcode^1) ); | |
| 1753 emit_d8( cbuf, $brOffs$$constant ); | |
| 1754 %} | |
| 1755 | |
| 1756 enc_class enc_PartialSubtypeCheck( ) %{ | |
| 1757 Register Redi = as_Register(EDI_enc); // result register | |
| 1758 Register Reax = as_Register(EAX_enc); // super class | |
| 1759 Register Recx = as_Register(ECX_enc); // killed | |
| 1760 Register Resi = as_Register(ESI_enc); // sub class | |
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1761 Label miss; |
| 0 | 1762 |
| 1763 MacroAssembler _masm(&cbuf); | |
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1764 __ check_klass_subtype_slow_path(Resi, Reax, Recx, Redi, |
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1765 NULL, &miss, |
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1766 /*set_cond_codes:*/ true); |
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1767 if ($primary) { |
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1768 __ xorptr(Redi, Redi); |
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1769 } |
| 0 | 1770 __ bind(miss); |
| 1771 %} | |
| 1772 | |
| 1773 enc_class FFree_Float_Stack_All %{ // Free_Float_Stack_All | |
| 1774 MacroAssembler masm(&cbuf); | |
| 1775 int start = masm.offset(); | |
| 1776 if (UseSSE >= 2) { | |
| 1777 if (VerifyFPU) { | |
| 1778 masm.verify_FPU(0, "must be empty in SSE2+ mode"); | |
| 1779 } | |
| 1780 } else { | |
| 1781 // External c_calling_convention expects the FPU stack to be 'clean'. | |
| 1782 // Compiled code leaves it dirty. Do cleanup now. | |
| 1783 masm.empty_FPU_stack(); | |
| 1784 } | |
| 1785 if (sizeof_FFree_Float_Stack_All == -1) { | |
| 1786 sizeof_FFree_Float_Stack_All = masm.offset() - start; | |
| 1787 } else { | |
| 1788 assert(masm.offset() - start == sizeof_FFree_Float_Stack_All, "wrong size"); | |
| 1789 } | |
| 1790 %} | |
| 1791 | |
| 1792 enc_class Verify_FPU_For_Leaf %{ | |
| 1793 if( VerifyFPU ) { | |
| 1794 MacroAssembler masm(&cbuf); | |
| 1795 masm.verify_FPU( -3, "Returning from Runtime Leaf call"); | |
| 1796 } | |
| 1797 %} | |
| 1798 | |
| 1799 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime, Java_To_Runtime_Leaf | |
| 1800 // This is the instruction starting address for relocation info. | |
| 1748 | 1801 cbuf.set_insts_mark(); |
| 0 | 1802 $$$emit8$primary; |
| 1803 // CALL directly to the runtime | |
| 1748 | 1804 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4), |
| 0 | 1805 runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 1806 | |
| 1807 if (UseSSE >= 2) { | |
| 1808 MacroAssembler _masm(&cbuf); | |
| 1809 BasicType rt = tf()->return_type(); | |
| 1810 | |
| 1811 if ((rt == T_FLOAT || rt == T_DOUBLE) && !return_value_is_used()) { | |
| 1812 // A C runtime call where the return value is unused. In SSE2+ | |
| 1813 // mode the result needs to be removed from the FPU stack. It's | |
| 1814 // likely that this function call could be removed by the | |
| 1815 // optimizer if the C function is a pure function. | |
| 1816 __ ffree(0); | |
| 1817 } else if (rt == T_FLOAT) { | |
| 304 | 1818 __ lea(rsp, Address(rsp, -4)); |
| 0 | 1819 __ fstp_s(Address(rsp, 0)); |
| 1820 __ movflt(xmm0, Address(rsp, 0)); | |
| 304 | 1821 __ lea(rsp, Address(rsp, 4)); |
| 0 | 1822 } else if (rt == T_DOUBLE) { |
| 304 | 1823 __ lea(rsp, Address(rsp, -8)); |
| 0 | 1824 __ fstp_d(Address(rsp, 0)); |
| 1825 __ movdbl(xmm0, Address(rsp, 0)); | |
| 304 | 1826 __ lea(rsp, Address(rsp, 8)); |
| 0 | 1827 } |
| 1828 } | |
| 1829 %} | |
| 1830 | |
| 1831 | |
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1832 enc_class pre_call_resets %{ |
| 0 | 1833 // If method sets FPU control word restore it here |
| 1748 | 1834 debug_only(int off0 = cbuf.insts_size()); |
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1835 if (ra_->C->in_24_bit_fp_mode()) { |
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1836 MacroAssembler _masm(&cbuf); |
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1837 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); |
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1838 } |
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1839 if (ra_->C->max_vector_size() > 16) { |
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1840 // Clear upper bits of YMM registers when current compiled code uses |
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1841 // wide vectors to avoid AVX <-> SSE transition penalty during call. |
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1842 MacroAssembler _masm(&cbuf); |
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1843 __ vzeroupper(); |
| 0 | 1844 } |
| 1748 | 1845 debug_only(int off1 = cbuf.insts_size()); |
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1846 assert(off1 - off0 == pre_call_resets_size(), "correct size prediction"); |
| 0 | 1847 %} |
| 1848 | |
| 1849 enc_class post_call_FPU %{ | |
| 1850 // If method sets FPU control word do it here also | |
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1851 if (Compile::current()->in_24_bit_fp_mode()) { |
| 0 | 1852 MacroAssembler masm(&cbuf); |
| 1853 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); | |
| 1854 } | |
| 1855 %} | |
| 1856 | |
| 1857 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL | |
| 1858 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine | |
| 1859 // who we intended to call. | |
| 1748 | 1860 cbuf.set_insts_mark(); |
| 0 | 1861 $$$emit8$primary; |
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1862 if (!_method) { |
| 1748 | 1863 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4), |
| 0 | 1864 runtime_call_Relocation::spec(), RELOC_IMM32 ); |
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1865 } else if (_optimized_virtual) { |
| 1748 | 1866 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4), |
| 0 | 1867 opt_virtual_call_Relocation::spec(), RELOC_IMM32 ); |
| 1868 } else { | |
| 1748 | 1869 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4), |
| 0 | 1870 static_call_Relocation::spec(), RELOC_IMM32 ); |
| 1871 } | |
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1872 if (_method) { // Emit stub for static call. |
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1873 CompiledStaticCall::emit_to_interp_stub(cbuf); |
| 0 | 1874 } |
| 1875 %} | |
| 1876 | |
| 1877 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL | |
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1878 MacroAssembler _masm(&cbuf); |
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1879 __ ic_call((address)$meth$$method); |
| 0 | 1880 %} |
| 1881 | |
| 1882 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL | |
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1883 int disp = in_bytes(Method::from_compiled_offset()); |
| 0 | 1884 assert( -128 <= disp && disp <= 127, "compiled_code_offset isn't small"); |
| 1885 | |
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1886 // CALL *[EAX+in_bytes(Method::from_compiled_code_entry_point_offset())] |
| 1748 | 1887 cbuf.set_insts_mark(); |
| 0 | 1888 $$$emit8$primary; |
| 1889 emit_rm(cbuf, 0x01, $secondary, EAX_enc ); // R/M byte | |
| 1890 emit_d8(cbuf, disp); // Displacement | |
| 1891 | |
| 1892 %} | |
| 1893 | |
| 1894 // Following encoding is no longer used, but may be restored if calling | |
| 1895 // convention changes significantly. | |
| 1896 // Became: Xor_Reg(EBP), Java_To_Runtime( labl ) | |
| 1897 // | |
| 1898 // enc_class Java_Interpreter_Call (label labl) %{ // JAVA INTERPRETER CALL | |
| 1899 // // int ic_reg = Matcher::inline_cache_reg(); | |
| 1900 // // int ic_encode = Matcher::_regEncode[ic_reg]; | |
| 1901 // // int imo_reg = Matcher::interpreter_method_oop_reg(); | |
| 1902 // // int imo_encode = Matcher::_regEncode[imo_reg]; | |
| 1903 // | |
| 1904 // // // Interpreter expects method_oop in EBX, currently a callee-saved register, | |
| 1905 // // // so we load it immediately before the call | |
| 1906 // // emit_opcode(cbuf, 0x8B); // MOV imo_reg,ic_reg # method_oop | |
| 1907 // // emit_rm(cbuf, 0x03, imo_encode, ic_encode ); // R/M byte | |
| 1908 // | |
| 1909 // // xor rbp,ebp | |
| 1910 // emit_opcode(cbuf, 0x33); | |
| 1911 // emit_rm(cbuf, 0x3, EBP_enc, EBP_enc); | |
| 1912 // | |
| 1913 // // CALL to interpreter. | |
| 1748 | 1914 // cbuf.set_insts_mark(); |
| 0 | 1915 // $$$emit8$primary; |
| 1748 | 1916 // emit_d32_reloc(cbuf, ($labl$$label - (int)(cbuf.insts_end()) - 4), |
| 0 | 1917 // runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 1918 // %} | |
| 1919 | |
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1920 enc_class RegOpcImm (rRegI dst, immI8 shift) %{ // SHL, SAR, SHR |
| 0 | 1921 $$$emit8$primary; |
| 1922 emit_rm(cbuf, 0x3, $secondary, $dst$$reg); | |
| 1923 $$$emit8$shift$$constant; | |
| 1924 %} | |
| 1925 | |
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1926 enc_class LdImmI (rRegI dst, immI src) %{ // Load Immediate |
| 0 | 1927 // Load immediate does not have a zero or sign extended version |
| 1928 // for 8-bit immediates | |
| 1929 emit_opcode(cbuf, 0xB8 + $dst$$reg); | |
| 1930 $$$emit32$src$$constant; | |
| 1931 %} | |
| 1932 | |
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1933 enc_class LdImmP (rRegI dst, immI src) %{ // Load Immediate |
| 0 | 1934 // Load immediate does not have a zero or sign extended version |
| 1935 // for 8-bit immediates | |
| 1936 emit_opcode(cbuf, $primary + $dst$$reg); | |
| 1937 $$$emit32$src$$constant; | |
| 1938 %} | |
| 1939 | |
| 1940 enc_class LdImmL_Lo( eRegL dst, immL src) %{ // Load Immediate | |
| 1941 // Load immediate does not have a zero or sign extended version | |
| 1942 // for 8-bit immediates | |
| 1943 int dst_enc = $dst$$reg; | |
| 1944 int src_con = $src$$constant & 0x0FFFFFFFFL; | |
| 1945 if (src_con == 0) { | |
| 1946 // xor dst, dst | |
| 1947 emit_opcode(cbuf, 0x33); | |
| 1948 emit_rm(cbuf, 0x3, dst_enc, dst_enc); | |
| 1949 } else { | |
| 1950 emit_opcode(cbuf, $primary + dst_enc); | |
| 1951 emit_d32(cbuf, src_con); | |
| 1952 } | |
| 1953 %} | |
| 1954 | |
| 1955 enc_class LdImmL_Hi( eRegL dst, immL src) %{ // Load Immediate | |
| 1956 // Load immediate does not have a zero or sign extended version | |
| 1957 // for 8-bit immediates | |
| 1958 int dst_enc = $dst$$reg + 2; | |
| 1959 int src_con = ((julong)($src$$constant)) >> 32; | |
| 1960 if (src_con == 0) { | |
| 1961 // xor dst, dst | |
| 1962 emit_opcode(cbuf, 0x33); | |
| 1963 emit_rm(cbuf, 0x3, dst_enc, dst_enc); | |
| 1964 } else { | |
| 1965 emit_opcode(cbuf, $primary + dst_enc); | |
| 1966 emit_d32(cbuf, src_con); | |
| 1967 } | |
| 1968 %} | |
| 1969 | |
| 1970 | |
| 1971 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
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1972 enc_class enc_Copy( rRegI dst, rRegI src ) %{ |
| 0 | 1973 encode_Copy( cbuf, $dst$$reg, $src$$reg ); |
| 1974 %} | |
| 1975 | |
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1976 enc_class enc_CopyL_Lo( rRegI dst, eRegL src ) %{ |
| 0 | 1977 encode_Copy( cbuf, $dst$$reg, $src$$reg ); |
| 1978 %} | |
| 1979 | |
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1980 enc_class RegReg (rRegI dst, rRegI src) %{ // RegReg(Many) |
| 0 | 1981 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); |
| 1982 %} | |
| 1983 | |
| 1984 enc_class RegReg_Lo(eRegL dst, eRegL src) %{ // RegReg(Many) | |
| 1985 $$$emit8$primary; | |
| 1986 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 1987 %} | |
| 1988 | |
| 1989 enc_class RegReg_Hi(eRegL dst, eRegL src) %{ // RegReg(Many) | |
| 1990 $$$emit8$secondary; | |
| 1991 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg)); | |
| 1992 %} | |
| 1993 | |
| 1994 enc_class RegReg_Lo2(eRegL dst, eRegL src) %{ // RegReg(Many) | |
| 1995 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 1996 %} | |
| 1997 | |
| 1998 enc_class RegReg_Hi2(eRegL dst, eRegL src) %{ // RegReg(Many) | |
| 1999 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg)); | |
| 2000 %} | |
| 2001 | |
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2002 enc_class RegReg_HiLo( eRegL src, rRegI dst ) %{ |
| 0 | 2003 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($src$$reg)); |
| 2004 %} | |
| 2005 | |
| 2006 enc_class Con32 (immI src) %{ // Con32(storeImmI) | |
| 2007 // Output immediate | |
| 2008 $$$emit32$src$$constant; | |
| 2009 %} | |
| 2010 | |
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2011 enc_class Con32FPR_as_bits(immFPR src) %{ // storeF_imm |
| 0 | 2012 // Output Float immediate bits |
| 2013 jfloat jf = $src$$constant; | |
| 2014 int jf_as_bits = jint_cast( jf ); | |
| 2015 emit_d32(cbuf, jf_as_bits); | |
| 2016 %} | |
| 2017 | |
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2018 enc_class Con32F_as_bits(immF src) %{ // storeX_imm |
| 0 | 2019 // Output Float immediate bits |
| 2020 jfloat jf = $src$$constant; | |
| 2021 int jf_as_bits = jint_cast( jf ); | |
| 2022 emit_d32(cbuf, jf_as_bits); | |
| 2023 %} | |
| 2024 | |
| 2025 enc_class Con16 (immI src) %{ // Con16(storeImmI) | |
| 2026 // Output immediate | |
| 2027 $$$emit16$src$$constant; | |
| 2028 %} | |
| 2029 | |
| 2030 enc_class Con_d32(immI src) %{ | |
| 2031 emit_d32(cbuf,$src$$constant); | |
| 2032 %} | |
| 2033 | |
| 2034 enc_class conmemref (eRegP t1) %{ // Con32(storeImmI) | |
| 2035 // Output immediate memory reference | |
| 2036 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 ); | |
| 2037 emit_d32(cbuf, 0x00); | |
| 2038 %} | |
| 2039 | |
| 2040 enc_class lock_prefix( ) %{ | |
| 2041 if( os::is_MP() ) | |
| 2042 emit_opcode(cbuf,0xF0); // [Lock] | |
| 2043 %} | |
| 2044 | |
| 2045 // Cmp-xchg long value. | |
| 2046 // Note: we need to swap rbx, and rcx before and after the | |
| 2047 // cmpxchg8 instruction because the instruction uses | |
| 2048 // rcx as the high order word of the new value to store but | |
| 2049 // our register encoding uses rbx,. | |
| 2050 enc_class enc_cmpxchg8(eSIRegP mem_ptr) %{ | |
| 2051 | |
| 2052 // XCHG rbx,ecx | |
| 2053 emit_opcode(cbuf,0x87); | |
| 2054 emit_opcode(cbuf,0xD9); | |
| 2055 // [Lock] | |
| 2056 if( os::is_MP() ) | |
| 2057 emit_opcode(cbuf,0xF0); | |
| 2058 // CMPXCHG8 [Eptr] | |
| 2059 emit_opcode(cbuf,0x0F); | |
| 2060 emit_opcode(cbuf,0xC7); | |
| 2061 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg ); | |
| 2062 // XCHG rbx,ecx | |
| 2063 emit_opcode(cbuf,0x87); | |
| 2064 emit_opcode(cbuf,0xD9); | |
| 2065 %} | |
| 2066 | |
| 2067 enc_class enc_cmpxchg(eSIRegP mem_ptr) %{ | |
| 2068 // [Lock] | |
| 2069 if( os::is_MP() ) | |
| 2070 emit_opcode(cbuf,0xF0); | |
| 2071 | |
| 2072 // CMPXCHG [Eptr] | |
| 2073 emit_opcode(cbuf,0x0F); | |
| 2074 emit_opcode(cbuf,0xB1); | |
| 2075 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg ); | |
| 2076 %} | |
| 2077 | |
| 2078 enc_class enc_flags_ne_to_boolean( iRegI res ) %{ | |
| 2079 int res_encoding = $res$$reg; | |
| 2080 | |
| 2081 // MOV res,0 | |
| 2082 emit_opcode( cbuf, 0xB8 + res_encoding); | |
| 2083 emit_d32( cbuf, 0 ); | |
| 2084 // JNE,s fail | |
| 2085 emit_opcode(cbuf,0x75); | |
| 2086 emit_d8(cbuf, 5 ); | |
| 2087 // MOV res,1 | |
| 2088 emit_opcode( cbuf, 0xB8 + res_encoding); | |
| 2089 emit_d32( cbuf, 1 ); | |
| 2090 // fail: | |
| 2091 %} | |
| 2092 | |
| 2093 enc_class set_instruction_start( ) %{ | |
| 1748 | 2094 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand |
| 0 | 2095 %} |
| 2096 | |
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2097 enc_class RegMem (rRegI ereg, memory mem) %{ // emit_reg_mem |
| 0 | 2098 int reg_encoding = $ereg$$reg; |
| 2099 int base = $mem$$base; | |
| 2100 int index = $mem$$index; | |
| 2101 int scale = $mem$$scale; | |
| 2102 int displace = $mem$$disp; | |
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2103 relocInfo::relocType disp_reloc = $mem->disp_reloc(); |
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2104 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc); |
| 0 | 2105 %} |
| 2106 | |
| 2107 enc_class RegMem_Hi(eRegL ereg, memory mem) %{ // emit_reg_mem | |
| 2108 int reg_encoding = HIGH_FROM_LOW($ereg$$reg); // Hi register of pair, computed from lo | |
| 2109 int base = $mem$$base; | |
| 2110 int index = $mem$$index; | |
| 2111 int scale = $mem$$scale; | |
| 2112 int displace = $mem$$disp + 4; // Offset is 4 further in memory | |
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2113 assert( $mem->disp_reloc() == relocInfo::none, "Cannot add 4 to oop" ); |
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2114 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, relocInfo::none); |
| 0 | 2115 %} |
| 2116 | |
| 2117 enc_class move_long_small_shift( eRegL dst, immI_1_31 cnt ) %{ | |
| 2118 int r1, r2; | |
| 2119 if( $tertiary == 0xA4 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); } | |
| 2120 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); } | |
| 2121 emit_opcode(cbuf,0x0F); | |
| 2122 emit_opcode(cbuf,$tertiary); | |
| 2123 emit_rm(cbuf, 0x3, r1, r2); | |
| 2124 emit_d8(cbuf,$cnt$$constant); | |
| 2125 emit_d8(cbuf,$primary); | |
| 2126 emit_rm(cbuf, 0x3, $secondary, r1); | |
| 2127 emit_d8(cbuf,$cnt$$constant); | |
| 2128 %} | |
| 2129 | |
| 2130 enc_class move_long_big_shift_sign( eRegL dst, immI_32_63 cnt ) %{ | |
| 2131 emit_opcode( cbuf, 0x8B ); // Move | |
| 2132 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg)); | |
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2133 if( $cnt$$constant > 32 ) { // Shift, if not by zero |
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2134 emit_d8(cbuf,$primary); |
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2135 emit_rm(cbuf, 0x3, $secondary, $dst$$reg); |
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2136 emit_d8(cbuf,$cnt$$constant-32); |
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2137 } |
| 0 | 2138 emit_d8(cbuf,$primary); |
| 2139 emit_rm(cbuf, 0x3, $secondary, HIGH_FROM_LOW($dst$$reg)); | |
| 2140 emit_d8(cbuf,31); | |
| 2141 %} | |
| 2142 | |
| 2143 enc_class move_long_big_shift_clr( eRegL dst, immI_32_63 cnt ) %{ | |
| 2144 int r1, r2; | |
| 2145 if( $secondary == 0x5 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); } | |
| 2146 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); } | |
| 2147 | |
| 2148 emit_opcode( cbuf, 0x8B ); // Move r1,r2 | |
| 2149 emit_rm(cbuf, 0x3, r1, r2); | |
| 2150 if( $cnt$$constant > 32 ) { // Shift, if not by zero | |
| 2151 emit_opcode(cbuf,$primary); | |
| 2152 emit_rm(cbuf, 0x3, $secondary, r1); | |
| 2153 emit_d8(cbuf,$cnt$$constant-32); | |
| 2154 } | |
| 2155 emit_opcode(cbuf,0x33); // XOR r2,r2 | |
| 2156 emit_rm(cbuf, 0x3, r2, r2); | |
| 2157 %} | |
| 2158 | |
| 2159 // Clone of RegMem but accepts an extra parameter to access each | |
| 2160 // half of a double in memory; it never needs relocation info. | |
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2161 enc_class Mov_MemD_half_to_Reg (immI opcode, memory mem, immI disp_for_half, rRegI rm_reg) %{ |
| 0 | 2162 emit_opcode(cbuf,$opcode$$constant); |
| 2163 int reg_encoding = $rm_reg$$reg; | |
| 2164 int base = $mem$$base; | |
| 2165 int index = $mem$$index; | |
| 2166 int scale = $mem$$scale; | |
| 2167 int displace = $mem$$disp + $disp_for_half$$constant; | |
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2168 relocInfo::relocType disp_reloc = relocInfo::none; |
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2169 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc); |
| 0 | 2170 %} |
| 2171 | |
| 2172 // !!!!! Special Custom Code used by MemMove, and stack access instructions !!!!! | |
| 2173 // | |
| 2174 // Clone of RegMem except the RM-byte's reg/opcode field is an ADLC-time constant | |
| 2175 // and it never needs relocation information. | |
| 2176 // Frequently used to move data between FPU's Stack Top and memory. | |
| 2177 enc_class RMopc_Mem_no_oop (immI rm_opcode, memory mem) %{ | |
| 2178 int rm_byte_opcode = $rm_opcode$$constant; | |
| 2179 int base = $mem$$base; | |
| 2180 int index = $mem$$index; | |
| 2181 int scale = $mem$$scale; | |
| 2182 int displace = $mem$$disp; | |
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2183 assert( $mem->disp_reloc() == relocInfo::none, "No oops here because no reloc info allowed" ); |
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2184 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, relocInfo::none); |
| 0 | 2185 %} |
| 2186 | |
| 2187 enc_class RMopc_Mem (immI rm_opcode, memory mem) %{ | |
| 2188 int rm_byte_opcode = $rm_opcode$$constant; | |
| 2189 int base = $mem$$base; | |
| 2190 int index = $mem$$index; | |
| 2191 int scale = $mem$$scale; | |
| 2192 int displace = $mem$$disp; | |
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2193 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals |
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2194 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc); |
| 0 | 2195 %} |
| 2196 | |
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2197 enc_class RegLea (rRegI dst, rRegI src0, immI src1 ) %{ // emit_reg_lea |
| 0 | 2198 int reg_encoding = $dst$$reg; |
| 2199 int base = $src0$$reg; // 0xFFFFFFFF indicates no base | |
| 2200 int index = 0x04; // 0x04 indicates no index | |
| 2201 int scale = 0x00; // 0x00 indicates no scale | |
| 2202 int displace = $src1$$constant; // 0x00 indicates no displacement | |
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2203 relocInfo::relocType disp_reloc = relocInfo::none; |
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2204 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc); |
| 0 | 2205 %} |
| 2206 | |
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2207 enc_class min_enc (rRegI dst, rRegI src) %{ // MIN |
| 0 | 2208 // Compare dst,src |
| 2209 emit_opcode(cbuf,0x3B); | |
| 2210 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 2211 // jmp dst < src around move | |
| 2212 emit_opcode(cbuf,0x7C); | |
| 2213 emit_d8(cbuf,2); | |
| 2214 // move dst,src | |
| 2215 emit_opcode(cbuf,0x8B); | |
| 2216 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 2217 %} | |
| 2218 | |
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2219 enc_class max_enc (rRegI dst, rRegI src) %{ // MAX |
| 0 | 2220 // Compare dst,src |
| 2221 emit_opcode(cbuf,0x3B); | |
| 2222 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 2223 // jmp dst > src around move | |
| 2224 emit_opcode(cbuf,0x7F); | |
| 2225 emit_d8(cbuf,2); | |
| 2226 // move dst,src | |
| 2227 emit_opcode(cbuf,0x8B); | |
| 2228 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 2229 %} | |
| 2230 | |
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2231 enc_class enc_FPR_store(memory mem, regDPR src) %{ |
| 0 | 2232 // If src is FPR1, we can just FST to store it. |
| 2233 // Else we need to FLD it to FPR1, then FSTP to store/pop it. | |
| 2234 int reg_encoding = 0x2; // Just store | |
| 2235 int base = $mem$$base; | |
| 2236 int index = $mem$$index; | |
| 2237 int scale = $mem$$scale; | |
| 2238 int displace = $mem$$disp; | |
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2239 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals |
| 0 | 2240 if( $src$$reg != FPR1L_enc ) { |
| 2241 reg_encoding = 0x3; // Store & pop | |
| 2242 emit_opcode( cbuf, 0xD9 ); // FLD (i.e., push it) | |
| 2243 emit_d8( cbuf, 0xC0-1+$src$$reg ); | |
| 2244 } | |
| 1748 | 2245 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand |
| 0 | 2246 emit_opcode(cbuf,$primary); |
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2247 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc); |
| 0 | 2248 %} |
| 2249 | |
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2250 enc_class neg_reg(rRegI dst) %{ |
| 0 | 2251 // NEG $dst |
| 2252 emit_opcode(cbuf,0xF7); | |
| 2253 emit_rm(cbuf, 0x3, 0x03, $dst$$reg ); | |
| 2254 %} | |
| 2255 | |
| 2256 enc_class setLT_reg(eCXRegI dst) %{ | |
| 2257 // SETLT $dst | |
| 2258 emit_opcode(cbuf,0x0F); | |
| 2259 emit_opcode(cbuf,0x9C); | |
| 2260 emit_rm( cbuf, 0x3, 0x4, $dst$$reg ); | |
| 2261 %} | |
| 2262 | |
| 2263 enc_class enc_cmpLTP(ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp) %{ // cadd_cmpLT | |
| 2264 int tmpReg = $tmp$$reg; | |
| 2265 | |
| 2266 // SUB $p,$q | |
| 2267 emit_opcode(cbuf,0x2B); | |
| 2268 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg); | |
| 2269 // SBB $tmp,$tmp | |
| 2270 emit_opcode(cbuf,0x1B); | |
| 2271 emit_rm(cbuf, 0x3, tmpReg, tmpReg); | |
| 2272 // AND $tmp,$y | |
| 2273 emit_opcode(cbuf,0x23); | |
| 2274 emit_rm(cbuf, 0x3, tmpReg, $y$$reg); | |
| 2275 // ADD $p,$tmp | |
| 2276 emit_opcode(cbuf,0x03); | |
| 2277 emit_rm(cbuf, 0x3, $p$$reg, tmpReg); | |
| 2278 %} | |
| 2279 | |
| 2280 enc_class shift_left_long( eRegL dst, eCXRegI shift ) %{ | |
| 2281 // TEST shift,32 | |
| 2282 emit_opcode(cbuf,0xF7); | |
| 2283 emit_rm(cbuf, 0x3, 0, ECX_enc); | |
| 2284 emit_d32(cbuf,0x20); | |
| 2285 // JEQ,s small | |
| 2286 emit_opcode(cbuf, 0x74); | |
| 2287 emit_d8(cbuf, 0x04); | |
| 2288 // MOV $dst.hi,$dst.lo | |
| 2289 emit_opcode( cbuf, 0x8B ); | |
| 2290 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg ); | |
| 2291 // CLR $dst.lo | |
| 2292 emit_opcode(cbuf, 0x33); | |
| 2293 emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg); | |
| 2294 // small: | |
| 2295 // SHLD $dst.hi,$dst.lo,$shift | |
| 2296 emit_opcode(cbuf,0x0F); | |
| 2297 emit_opcode(cbuf,0xA5); | |
| 2298 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg)); | |
| 2299 // SHL $dst.lo,$shift" | |
| 2300 emit_opcode(cbuf,0xD3); | |
| 2301 emit_rm(cbuf, 0x3, 0x4, $dst$$reg ); | |
| 2302 %} | |
| 2303 | |
| 2304 enc_class shift_right_long( eRegL dst, eCXRegI shift ) %{ | |
| 2305 // TEST shift,32 | |
| 2306 emit_opcode(cbuf,0xF7); | |
| 2307 emit_rm(cbuf, 0x3, 0, ECX_enc); | |
| 2308 emit_d32(cbuf,0x20); | |
| 2309 // JEQ,s small | |
| 2310 emit_opcode(cbuf, 0x74); | |
| 2311 emit_d8(cbuf, 0x04); | |
| 2312 // MOV $dst.lo,$dst.hi | |
| 2313 emit_opcode( cbuf, 0x8B ); | |
| 2314 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) ); | |
| 2315 // CLR $dst.hi | |
| 2316 emit_opcode(cbuf, 0x33); | |
| 2317 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($dst$$reg)); | |
| 2318 // small: | |
| 2319 // SHRD $dst.lo,$dst.hi,$shift | |
| 2320 emit_opcode(cbuf,0x0F); | |
| 2321 emit_opcode(cbuf,0xAD); | |
| 2322 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg); | |
| 2323 // SHR $dst.hi,$shift" | |
| 2324 emit_opcode(cbuf,0xD3); | |
| 2325 emit_rm(cbuf, 0x3, 0x5, HIGH_FROM_LOW($dst$$reg) ); | |
| 2326 %} | |
| 2327 | |
| 2328 enc_class shift_right_arith_long( eRegL dst, eCXRegI shift ) %{ | |
| 2329 // TEST shift,32 | |
| 2330 emit_opcode(cbuf,0xF7); | |
| 2331 emit_rm(cbuf, 0x3, 0, ECX_enc); | |
| 2332 emit_d32(cbuf,0x20); | |
| 2333 // JEQ,s small | |
| 2334 emit_opcode(cbuf, 0x74); | |
| 2335 emit_d8(cbuf, 0x05); | |
| 2336 // MOV $dst.lo,$dst.hi | |
| 2337 emit_opcode( cbuf, 0x8B ); | |
| 2338 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) ); | |
| 2339 // SAR $dst.hi,31 | |
| 2340 emit_opcode(cbuf, 0xC1); | |
| 2341 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW($dst$$reg) ); | |
| 2342 emit_d8(cbuf, 0x1F ); | |
| 2343 // small: | |
| 2344 // SHRD $dst.lo,$dst.hi,$shift | |
| 2345 emit_opcode(cbuf,0x0F); | |
| 2346 emit_opcode(cbuf,0xAD); | |
| 2347 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg); | |
| 2348 // SAR $dst.hi,$shift" | |
| 2349 emit_opcode(cbuf,0xD3); | |
| 2350 emit_rm(cbuf, 0x3, 0x7, HIGH_FROM_LOW($dst$$reg) ); | |
| 2351 %} | |
| 2352 | |
| 2353 | |
| 2354 // ----------------- Encodings for floating point unit ----------------- | |
| 2355 // May leave result in FPU-TOS or FPU reg depending on opcodes | |
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2356 enc_class OpcReg_FPR(regFPR src) %{ // FMUL, FDIV |
| 0 | 2357 $$$emit8$primary; |
| 2358 emit_rm(cbuf, 0x3, $secondary, $src$$reg ); | |
| 2359 %} | |
| 2360 | |
| 2361 // Pop argument in FPR0 with FSTP ST(0) | |
| 2362 enc_class PopFPU() %{ | |
| 2363 emit_opcode( cbuf, 0xDD ); | |
| 2364 emit_d8( cbuf, 0xD8 ); | |
| 2365 %} | |
| 2366 | |
| 2367 // !!!!! equivalent to Pop_Reg_F | |
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2368 enc_class Pop_Reg_DPR( regDPR dst ) %{ |
| 0 | 2369 emit_opcode( cbuf, 0xDD ); // FSTP ST(i) |
| 2370 emit_d8( cbuf, 0xD8+$dst$$reg ); | |
| 2371 %} | |
| 2372 | |
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2373 enc_class Push_Reg_DPR( regDPR dst ) %{ |
| 0 | 2374 emit_opcode( cbuf, 0xD9 ); |
| 2375 emit_d8( cbuf, 0xC0-1+$dst$$reg ); // FLD ST(i-1) | |
| 2376 %} | |
| 2377 | |
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2378 enc_class strictfp_bias1( regDPR dst ) %{ |
| 0 | 2379 emit_opcode( cbuf, 0xDB ); // FLD m80real |
| 2380 emit_opcode( cbuf, 0x2D ); | |
| 2381 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias1() ); | |
| 2382 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0 | |
| 2383 emit_opcode( cbuf, 0xC8+$dst$$reg ); | |
| 2384 %} | |
| 2385 | |
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2386 enc_class strictfp_bias2( regDPR dst ) %{ |
| 0 | 2387 emit_opcode( cbuf, 0xDB ); // FLD m80real |
| 2388 emit_opcode( cbuf, 0x2D ); | |
| 2389 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias2() ); | |
| 2390 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0 | |
| 2391 emit_opcode( cbuf, 0xC8+$dst$$reg ); | |
| 2392 %} | |
| 2393 | |
| 2394 // Special case for moving an integer register to a stack slot. | |
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2395 enc_class OpcPRegSS( stackSlotI dst, rRegI src ) %{ // RegSS |
| 0 | 2396 store_to_stackslot( cbuf, $primary, $src$$reg, $dst$$disp ); |
| 2397 %} | |
| 2398 | |
| 2399 // Special case for moving a register to a stack slot. | |
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2400 enc_class RegSS( stackSlotI dst, rRegI src ) %{ // RegSS |
| 0 | 2401 // Opcode already emitted |
| 2402 emit_rm( cbuf, 0x02, $src$$reg, ESP_enc ); // R/M byte | |
| 2403 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte | |
| 2404 emit_d32(cbuf, $dst$$disp); // Displacement | |
| 2405 %} | |
| 2406 | |
| 2407 // Push the integer in stackSlot 'src' onto FP-stack | |
| 2408 enc_class Push_Mem_I( memory src ) %{ // FILD [ESP+src] | |
| 2409 store_to_stackslot( cbuf, $primary, $secondary, $src$$disp ); | |
| 2410 %} | |
| 2411 | |
| 2412 // Push FPU's TOS float to a stack-slot, and pop FPU-stack | |
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2413 enc_class Pop_Mem_FPR( stackSlotF dst ) %{ // FSTP_S [ESP+dst] |
| 0 | 2414 store_to_stackslot( cbuf, 0xD9, 0x03, $dst$$disp ); |
| 2415 %} | |
| 2416 | |
| 2417 // Same as Pop_Mem_F except for opcode | |
| 2418 // Push FPU's TOS double to a stack-slot, and pop FPU-stack | |
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2419 enc_class Pop_Mem_DPR( stackSlotD dst ) %{ // FSTP_D [ESP+dst] |
| 0 | 2420 store_to_stackslot( cbuf, 0xDD, 0x03, $dst$$disp ); |
| 2421 %} | |
| 2422 | |
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2423 enc_class Pop_Reg_FPR( regFPR dst ) %{ |
| 0 | 2424 emit_opcode( cbuf, 0xDD ); // FSTP ST(i) |
| 2425 emit_d8( cbuf, 0xD8+$dst$$reg ); | |
| 2426 %} | |
| 2427 | |
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2428 enc_class Push_Reg_FPR( regFPR dst ) %{ |
| 0 | 2429 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1) |
| 2430 emit_d8( cbuf, 0xC0-1+$dst$$reg ); | |
| 2431 %} | |
| 2432 | |
| 2433 // Push FPU's float to a stack-slot, and pop FPU-stack | |
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2434 enc_class Pop_Mem_Reg_FPR( stackSlotF dst, regFPR src ) %{ |
| 0 | 2435 int pop = 0x02; |
| 2436 if ($src$$reg != FPR1L_enc) { | |
| 2437 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1) | |
| 2438 emit_d8( cbuf, 0xC0-1+$src$$reg ); | |
| 2439 pop = 0x03; | |
| 2440 } | |
| 2441 store_to_stackslot( cbuf, 0xD9, pop, $dst$$disp ); // FST<P>_S [ESP+dst] | |
| 2442 %} | |
| 2443 | |
| 2444 // Push FPU's double to a stack-slot, and pop FPU-stack | |
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2445 enc_class Pop_Mem_Reg_DPR( stackSlotD dst, regDPR src ) %{ |
| 0 | 2446 int pop = 0x02; |
| 2447 if ($src$$reg != FPR1L_enc) { | |
| 2448 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1) | |
| 2449 emit_d8( cbuf, 0xC0-1+$src$$reg ); | |
| 2450 pop = 0x03; | |
| 2451 } | |
| 2452 store_to_stackslot( cbuf, 0xDD, pop, $dst$$disp ); // FST<P>_D [ESP+dst] | |
| 2453 %} | |
| 2454 | |
| 2455 // Push FPU's double to a FPU-stack-slot, and pop FPU-stack | |
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2456 enc_class Pop_Reg_Reg_DPR( regDPR dst, regFPR src ) %{ |
| 0 | 2457 int pop = 0xD0 - 1; // -1 since we skip FLD |
| 2458 if ($src$$reg != FPR1L_enc) { | |
| 2459 emit_opcode( cbuf, 0xD9 ); // FLD ST(src-1) | |
| 2460 emit_d8( cbuf, 0xC0-1+$src$$reg ); | |
| 2461 pop = 0xD8; | |
| 2462 } | |
| 2463 emit_opcode( cbuf, 0xDD ); | |
| 2464 emit_d8( cbuf, pop+$dst$$reg ); // FST<P> ST(i) | |
| 2465 %} | |
| 2466 | |
| 2467 | |
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2468 enc_class Push_Reg_Mod_DPR( regDPR dst, regDPR src) %{ |
| 0 | 2469 // load dst in FPR0 |
| 2470 emit_opcode( cbuf, 0xD9 ); | |
| 2471 emit_d8( cbuf, 0xC0-1+$dst$$reg ); | |
| 2472 if ($src$$reg != FPR1L_enc) { | |
| 2473 // fincstp | |
| 2474 emit_opcode (cbuf, 0xD9); | |
| 2475 emit_opcode (cbuf, 0xF7); | |
| 2476 // swap src with FPR1: | |
| 2477 // FXCH FPR1 with src | |
| 2478 emit_opcode(cbuf, 0xD9); | |
| 2479 emit_d8(cbuf, 0xC8-1+$src$$reg ); | |
| 2480 // fdecstp | |
| 2481 emit_opcode (cbuf, 0xD9); | |
| 2482 emit_opcode (cbuf, 0xF6); | |
| 2483 } | |
| 2484 %} | |
| 2485 | |
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2486 enc_class Push_ModD_encoding(regD src0, regD src1) %{ |
| 4759 | 2487 MacroAssembler _masm(&cbuf); |
| 2488 __ subptr(rsp, 8); | |
| 2489 __ movdbl(Address(rsp, 0), $src1$$XMMRegister); | |
| 2490 __ fld_d(Address(rsp, 0)); | |
| 2491 __ movdbl(Address(rsp, 0), $src0$$XMMRegister); | |
| 2492 __ fld_d(Address(rsp, 0)); | |
| 2493 %} | |
| 2494 | |
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2495 enc_class Push_ModF_encoding(regF src0, regF src1) %{ |
| 4759 | 2496 MacroAssembler _masm(&cbuf); |
| 2497 __ subptr(rsp, 4); | |
| 2498 __ movflt(Address(rsp, 0), $src1$$XMMRegister); | |
| 2499 __ fld_s(Address(rsp, 0)); | |
| 2500 __ movflt(Address(rsp, 0), $src0$$XMMRegister); | |
| 2501 __ fld_s(Address(rsp, 0)); | |
| 0 | 2502 %} |
| 2503 | |
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2504 enc_class Push_ResultD(regD dst) %{ |
| 4759 | 2505 MacroAssembler _masm(&cbuf); |
| 2506 __ fstp_d(Address(rsp, 0)); | |
| 2507 __ movdbl($dst$$XMMRegister, Address(rsp, 0)); | |
| 2508 __ addptr(rsp, 8); | |
| 0 | 2509 %} |
| 2510 | |
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2511 enc_class Push_ResultF(regF dst, immI d8) %{ |
| 4759 | 2512 MacroAssembler _masm(&cbuf); |
| 2513 __ fstp_s(Address(rsp, 0)); | |
| 2514 __ movflt($dst$$XMMRegister, Address(rsp, 0)); | |
| 2515 __ addptr(rsp, $d8$$constant); | |
| 0 | 2516 %} |
| 2517 | |
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2518 enc_class Push_SrcD(regD src) %{ |
| 4759 | 2519 MacroAssembler _masm(&cbuf); |
| 2520 __ subptr(rsp, 8); | |
| 2521 __ movdbl(Address(rsp, 0), $src$$XMMRegister); | |
| 2522 __ fld_d(Address(rsp, 0)); | |
| 0 | 2523 %} |
| 2524 | |
| 2525 enc_class push_stack_temp_qword() %{ | |
| 4759 | 2526 MacroAssembler _masm(&cbuf); |
| 2527 __ subptr(rsp, 8); | |
| 0 | 2528 %} |
| 2529 | |
| 2530 enc_class pop_stack_temp_qword() %{ | |
| 4759 | 2531 MacroAssembler _masm(&cbuf); |
| 2532 __ addptr(rsp, 8); | |
| 2533 %} | |
| 2534 | |
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2535 enc_class push_xmm_to_fpr1(regD src) %{ |
| 4759 | 2536 MacroAssembler _masm(&cbuf); |
| 2537 __ movdbl(Address(rsp, 0), $src$$XMMRegister); | |
| 2538 __ fld_d(Address(rsp, 0)); | |
| 0 | 2539 %} |
| 2540 | |
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2541 enc_class Push_Result_Mod_DPR( regDPR src) %{ |
| 0 | 2542 if ($src$$reg != FPR1L_enc) { |
| 2543 // fincstp | |
| 2544 emit_opcode (cbuf, 0xD9); | |
| 2545 emit_opcode (cbuf, 0xF7); | |
| 2546 // FXCH FPR1 with src | |
| 2547 emit_opcode(cbuf, 0xD9); | |
| 2548 emit_d8(cbuf, 0xC8-1+$src$$reg ); | |
| 2549 // fdecstp | |
| 2550 emit_opcode (cbuf, 0xD9); | |
| 2551 emit_opcode (cbuf, 0xF6); | |
| 2552 } | |
| 2553 // // following asm replaced with Pop_Reg_F or Pop_Mem_F | |
| 2554 // // FSTP FPR$dst$$reg | |
| 2555 // emit_opcode( cbuf, 0xDD ); | |
| 2556 // emit_d8( cbuf, 0xD8+$dst$$reg ); | |
| 2557 %} | |
| 2558 | |
| 2559 enc_class fnstsw_sahf_skip_parity() %{ | |
| 2560 // fnstsw ax | |
| 2561 emit_opcode( cbuf, 0xDF ); | |
| 2562 emit_opcode( cbuf, 0xE0 ); | |
| 2563 // sahf | |
| 2564 emit_opcode( cbuf, 0x9E ); | |
| 2565 // jnp ::skip | |
| 2566 emit_opcode( cbuf, 0x7B ); | |
| 2567 emit_opcode( cbuf, 0x05 ); | |
| 2568 %} | |
| 2569 | |
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2570 enc_class emitModDPR() %{ |
| 0 | 2571 // fprem must be iterative |
| 2572 // :: loop | |
| 2573 // fprem | |
| 2574 emit_opcode( cbuf, 0xD9 ); | |
| 2575 emit_opcode( cbuf, 0xF8 ); | |
| 2576 // wait | |
| 2577 emit_opcode( cbuf, 0x9b ); | |
| 2578 // fnstsw ax | |
| 2579 emit_opcode( cbuf, 0xDF ); | |
| 2580 emit_opcode( cbuf, 0xE0 ); | |
| 2581 // sahf | |
| 2582 emit_opcode( cbuf, 0x9E ); | |
| 2583 // jp ::loop | |
| 2584 emit_opcode( cbuf, 0x0F ); | |
| 2585 emit_opcode( cbuf, 0x8A ); | |
| 2586 emit_opcode( cbuf, 0xF4 ); | |
| 2587 emit_opcode( cbuf, 0xFF ); | |
| 2588 emit_opcode( cbuf, 0xFF ); | |
| 2589 emit_opcode( cbuf, 0xFF ); | |
| 2590 %} | |
| 2591 | |
| 2592 enc_class fpu_flags() %{ | |
| 2593 // fnstsw_ax | |
| 2594 emit_opcode( cbuf, 0xDF); | |
| 2595 emit_opcode( cbuf, 0xE0); | |
| 2596 // test ax,0x0400 | |
| 2597 emit_opcode( cbuf, 0x66 ); // operand-size prefix for 16-bit immediate | |
| 2598 emit_opcode( cbuf, 0xA9 ); | |
| 2599 emit_d16 ( cbuf, 0x0400 ); | |
| 2600 // // // This sequence works, but stalls for 12-16 cycles on PPro | |
| 2601 // // test rax,0x0400 | |
| 2602 // emit_opcode( cbuf, 0xA9 ); | |
| 2603 // emit_d32 ( cbuf, 0x00000400 ); | |
| 2604 // | |
| 2605 // jz exit (no unordered comparison) | |
| 2606 emit_opcode( cbuf, 0x74 ); | |
| 2607 emit_d8 ( cbuf, 0x02 ); | |
| 2608 // mov ah,1 - treat as LT case (set carry flag) | |
| 2609 emit_opcode( cbuf, 0xB4 ); | |
| 2610 emit_d8 ( cbuf, 0x01 ); | |
| 2611 // sahf | |
| 2612 emit_opcode( cbuf, 0x9E); | |
| 2613 %} | |
| 2614 | |
| 2615 enc_class cmpF_P6_fixup() %{ | |
| 2616 // Fixup the integer flags in case comparison involved a NaN | |
| 2617 // | |
| 2618 // JNP exit (no unordered comparison, P-flag is set by NaN) | |
| 2619 emit_opcode( cbuf, 0x7B ); | |
| 2620 emit_d8 ( cbuf, 0x03 ); | |
| 2621 // MOV AH,1 - treat as LT case (set carry flag) | |
| 2622 emit_opcode( cbuf, 0xB4 ); | |
| 2623 emit_d8 ( cbuf, 0x01 ); | |
| 2624 // SAHF | |
| 2625 emit_opcode( cbuf, 0x9E); | |
| 2626 // NOP // target for branch to avoid branch to branch | |
| 2627 emit_opcode( cbuf, 0x90); | |
| 2628 %} | |
| 2629 | |
| 2630 // fnstsw_ax(); | |
| 2631 // sahf(); | |
| 2632 // movl(dst, nan_result); | |
| 2633 // jcc(Assembler::parity, exit); | |
| 2634 // movl(dst, less_result); | |
| 2635 // jcc(Assembler::below, exit); | |
| 2636 // movl(dst, equal_result); | |
| 2637 // jcc(Assembler::equal, exit); | |
| 2638 // movl(dst, greater_result); | |
| 2639 | |
| 2640 // less_result = 1; | |
| 2641 // greater_result = -1; | |
| 2642 // equal_result = 0; | |
| 2643 // nan_result = -1; | |
| 2644 | |
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2645 enc_class CmpF_Result(rRegI dst) %{ |
| 0 | 2646 // fnstsw_ax(); |
| 2647 emit_opcode( cbuf, 0xDF); | |
| 2648 emit_opcode( cbuf, 0xE0); | |
| 2649 // sahf | |
| 2650 emit_opcode( cbuf, 0x9E); | |
| 2651 // movl(dst, nan_result); | |
| 2652 emit_opcode( cbuf, 0xB8 + $dst$$reg); | |
| 2653 emit_d32( cbuf, -1 ); | |
| 2654 // jcc(Assembler::parity, exit); | |
| 2655 emit_opcode( cbuf, 0x7A ); | |
| 2656 emit_d8 ( cbuf, 0x13 ); | |
| 2657 // movl(dst, less_result); | |
| 2658 emit_opcode( cbuf, 0xB8 + $dst$$reg); | |
| 2659 emit_d32( cbuf, -1 ); | |
| 2660 // jcc(Assembler::below, exit); | |
| 2661 emit_opcode( cbuf, 0x72 ); | |
| 2662 emit_d8 ( cbuf, 0x0C ); | |
| 2663 // movl(dst, equal_result); | |
| 2664 emit_opcode( cbuf, 0xB8 + $dst$$reg); | |
| 2665 emit_d32( cbuf, 0 ); | |
| 2666 // jcc(Assembler::equal, exit); | |
| 2667 emit_opcode( cbuf, 0x74 ); | |
| 2668 emit_d8 ( cbuf, 0x05 ); | |
| 2669 // movl(dst, greater_result); | |
| 2670 emit_opcode( cbuf, 0xB8 + $dst$$reg); | |
| 2671 emit_d32( cbuf, 1 ); | |
| 2672 %} | |
| 2673 | |
| 2674 | |
| 2675 // Compare the longs and set flags | |
| 2676 // BROKEN! Do Not use as-is | |
| 2677 enc_class cmpl_test( eRegL src1, eRegL src2 ) %{ | |
| 2678 // CMP $src1.hi,$src2.hi | |
| 2679 emit_opcode( cbuf, 0x3B ); | |
| 2680 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) ); | |
| 2681 // JNE,s done | |
| 2682 emit_opcode(cbuf,0x75); | |
| 2683 emit_d8(cbuf, 2 ); | |
| 2684 // CMP $src1.lo,$src2.lo | |
| 2685 emit_opcode( cbuf, 0x3B ); | |
| 2686 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg ); | |
| 2687 // done: | |
| 2688 %} | |
| 2689 | |
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2690 enc_class convert_int_long( regL dst, rRegI src ) %{ |
| 0 | 2691 // mov $dst.lo,$src |
| 2692 int dst_encoding = $dst$$reg; | |
| 2693 int src_encoding = $src$$reg; | |
| 2694 encode_Copy( cbuf, dst_encoding , src_encoding ); | |
| 2695 // mov $dst.hi,$src | |
| 2696 encode_Copy( cbuf, HIGH_FROM_LOW(dst_encoding), src_encoding ); | |
| 2697 // sar $dst.hi,31 | |
| 2698 emit_opcode( cbuf, 0xC1 ); | |
| 2699 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW(dst_encoding) ); | |
| 2700 emit_d8(cbuf, 0x1F ); | |
| 2701 %} | |
| 2702 | |
| 2703 enc_class convert_long_double( eRegL src ) %{ | |
| 2704 // push $src.hi | |
| 2705 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg)); | |
| 2706 // push $src.lo | |
| 2707 emit_opcode(cbuf, 0x50+$src$$reg ); | |
| 2708 // fild 64-bits at [SP] | |
| 2709 emit_opcode(cbuf,0xdf); | |
| 2710 emit_d8(cbuf, 0x6C); | |
| 2711 emit_d8(cbuf, 0x24); | |
| 2712 emit_d8(cbuf, 0x00); | |
| 2713 // pop stack | |
| 2714 emit_opcode(cbuf, 0x83); // add SP, #8 | |
| 2715 emit_rm(cbuf, 0x3, 0x00, ESP_enc); | |
| 2716 emit_d8(cbuf, 0x8); | |
| 2717 %} | |
| 2718 | |
| 2719 enc_class multiply_con_and_shift_high( eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr ) %{ | |
| 2720 // IMUL EDX:EAX,$src1 | |
| 2721 emit_opcode( cbuf, 0xF7 ); | |
| 2722 emit_rm( cbuf, 0x3, 0x5, $src1$$reg ); | |
| 2723 // SAR EDX,$cnt-32 | |
| 2724 int shift_count = ((int)$cnt$$constant) - 32; | |
| 2725 if (shift_count > 0) { | |
| 2726 emit_opcode(cbuf, 0xC1); | |
| 2727 emit_rm(cbuf, 0x3, 7, $dst$$reg ); | |
| 2728 emit_d8(cbuf, shift_count); | |
| 2729 } | |
| 2730 %} | |
| 2731 | |
| 2732 // this version doesn't have add sp, 8 | |
| 2733 enc_class convert_long_double2( eRegL src ) %{ | |
| 2734 // push $src.hi | |
| 2735 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg)); | |
| 2736 // push $src.lo | |
| 2737 emit_opcode(cbuf, 0x50+$src$$reg ); | |
| 2738 // fild 64-bits at [SP] | |
| 2739 emit_opcode(cbuf,0xdf); | |
| 2740 emit_d8(cbuf, 0x6C); | |
| 2741 emit_d8(cbuf, 0x24); | |
| 2742 emit_d8(cbuf, 0x00); | |
| 2743 %} | |
| 2744 | |
| 2745 enc_class long_int_multiply( eADXRegL dst, nadxRegI src) %{ | |
| 2746 // Basic idea: long = (long)int * (long)int | |
| 2747 // IMUL EDX:EAX, src | |
| 2748 emit_opcode( cbuf, 0xF7 ); | |
| 2749 emit_rm( cbuf, 0x3, 0x5, $src$$reg); | |
| 2750 %} | |
| 2751 | |
| 2752 enc_class long_uint_multiply( eADXRegL dst, nadxRegI src) %{ | |
| 2753 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL) | |
| 2754 // MUL EDX:EAX, src | |
| 2755 emit_opcode( cbuf, 0xF7 ); | |
| 2756 emit_rm( cbuf, 0x3, 0x4, $src$$reg); | |
| 2757 %} | |
| 2758 | |
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2759 enc_class long_multiply( eADXRegL dst, eRegL src, rRegI tmp ) %{ |
| 0 | 2760 // Basic idea: lo(result) = lo(x_lo * y_lo) |
| 2761 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi) | |
| 2762 // MOV $tmp,$src.lo | |
| 2763 encode_Copy( cbuf, $tmp$$reg, $src$$reg ); | |
| 2764 // IMUL $tmp,EDX | |
| 2765 emit_opcode( cbuf, 0x0F ); | |
| 2766 emit_opcode( cbuf, 0xAF ); | |
| 2767 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) ); | |
| 2768 // MOV EDX,$src.hi | |
| 2769 encode_Copy( cbuf, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg) ); | |
| 2770 // IMUL EDX,EAX | |
| 2771 emit_opcode( cbuf, 0x0F ); | |
| 2772 emit_opcode( cbuf, 0xAF ); | |
| 2773 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg ); | |
| 2774 // ADD $tmp,EDX | |
| 2775 emit_opcode( cbuf, 0x03 ); | |
| 2776 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) ); | |
| 2777 // MUL EDX:EAX,$src.lo | |
| 2778 emit_opcode( cbuf, 0xF7 ); | |
| 2779 emit_rm( cbuf, 0x3, 0x4, $src$$reg ); | |
| 2780 // ADD EDX,ESI | |
| 2781 emit_opcode( cbuf, 0x03 ); | |
| 2782 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $tmp$$reg ); | |
| 2783 %} | |
| 2784 | |
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2785 enc_class long_multiply_con( eADXRegL dst, immL_127 src, rRegI tmp ) %{ |
| 0 | 2786 // Basic idea: lo(result) = lo(src * y_lo) |
| 2787 // hi(result) = hi(src * y_lo) + lo(src * y_hi) | |
| 2788 // IMUL $tmp,EDX,$src | |
| 2789 emit_opcode( cbuf, 0x6B ); | |
| 2790 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) ); | |
| 2791 emit_d8( cbuf, (int)$src$$constant ); | |
| 2792 // MOV EDX,$src | |
| 2793 emit_opcode(cbuf, 0xB8 + EDX_enc); | |
| 2794 emit_d32( cbuf, (int)$src$$constant ); | |
| 2795 // MUL EDX:EAX,EDX | |
| 2796 emit_opcode( cbuf, 0xF7 ); | |
| 2797 emit_rm( cbuf, 0x3, 0x4, EDX_enc ); | |
| 2798 // ADD EDX,ESI | |
| 2799 emit_opcode( cbuf, 0x03 ); | |
| 2800 emit_rm( cbuf, 0x3, EDX_enc, $tmp$$reg ); | |
| 2801 %} | |
| 2802 | |
| 2803 enc_class long_div( eRegL src1, eRegL src2 ) %{ | |
| 2804 // PUSH src1.hi | |
| 2805 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) ); | |
| 2806 // PUSH src1.lo | |
| 2807 emit_opcode(cbuf, 0x50+$src1$$reg ); | |
| 2808 // PUSH src2.hi | |
| 2809 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) ); | |
| 2810 // PUSH src2.lo | |
| 2811 emit_opcode(cbuf, 0x50+$src2$$reg ); | |
| 2812 // CALL directly to the runtime | |
| 1748 | 2813 cbuf.set_insts_mark(); |
| 0 | 2814 emit_opcode(cbuf,0xE8); // Call into runtime |
| 1748 | 2815 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::ldiv) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 0 | 2816 // Restore stack |
| 2817 emit_opcode(cbuf, 0x83); // add SP, #framesize | |
| 2818 emit_rm(cbuf, 0x3, 0x00, ESP_enc); | |
| 2819 emit_d8(cbuf, 4*4); | |
| 2820 %} | |
| 2821 | |
| 2822 enc_class long_mod( eRegL src1, eRegL src2 ) %{ | |
| 2823 // PUSH src1.hi | |
| 2824 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) ); | |
| 2825 // PUSH src1.lo | |
| 2826 emit_opcode(cbuf, 0x50+$src1$$reg ); | |
| 2827 // PUSH src2.hi | |
| 2828 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) ); | |
| 2829 // PUSH src2.lo | |
| 2830 emit_opcode(cbuf, 0x50+$src2$$reg ); | |
| 2831 // CALL directly to the runtime | |
| 1748 | 2832 cbuf.set_insts_mark(); |
| 0 | 2833 emit_opcode(cbuf,0xE8); // Call into runtime |
| 1748 | 2834 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::lrem ) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 0 | 2835 // Restore stack |
| 2836 emit_opcode(cbuf, 0x83); // add SP, #framesize | |
| 2837 emit_rm(cbuf, 0x3, 0x00, ESP_enc); | |
| 2838 emit_d8(cbuf, 4*4); | |
| 2839 %} | |
| 2840 | |
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2841 enc_class long_cmp_flags0( eRegL src, rRegI tmp ) %{ |
| 0 | 2842 // MOV $tmp,$src.lo |
| 2843 emit_opcode(cbuf, 0x8B); | |
| 2844 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg); | |
| 2845 // OR $tmp,$src.hi | |
| 2846 emit_opcode(cbuf, 0x0B); | |
| 2847 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg)); | |
| 2848 %} | |
| 2849 | |
| 2850 enc_class long_cmp_flags1( eRegL src1, eRegL src2 ) %{ | |
| 2851 // CMP $src1.lo,$src2.lo | |
| 2852 emit_opcode( cbuf, 0x3B ); | |
| 2853 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg ); | |
| 2854 // JNE,s skip | |
| 2855 emit_cc(cbuf, 0x70, 0x5); | |
| 2856 emit_d8(cbuf,2); | |
| 2857 // CMP $src1.hi,$src2.hi | |
| 2858 emit_opcode( cbuf, 0x3B ); | |
| 2859 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) ); | |
| 2860 %} | |
| 2861 | |
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2862 enc_class long_cmp_flags2( eRegL src1, eRegL src2, rRegI tmp ) %{ |
| 0 | 2863 // CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits |
| 2864 emit_opcode( cbuf, 0x3B ); | |
| 2865 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg ); | |
| 2866 // MOV $tmp,$src1.hi | |
| 2867 emit_opcode( cbuf, 0x8B ); | |
| 2868 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src1$$reg) ); | |
| 2869 // SBB $tmp,$src2.hi\t! Compute flags for long compare | |
| 2870 emit_opcode( cbuf, 0x1B ); | |
| 2871 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src2$$reg) ); | |
| 2872 %} | |
| 2873 | |
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2874 enc_class long_cmp_flags3( eRegL src, rRegI tmp ) %{ |
| 0 | 2875 // XOR $tmp,$tmp |
| 2876 emit_opcode(cbuf,0x33); // XOR | |
| 2877 emit_rm(cbuf,0x3, $tmp$$reg, $tmp$$reg); | |
| 2878 // CMP $tmp,$src.lo | |
| 2879 emit_opcode( cbuf, 0x3B ); | |
| 2880 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg ); | |
| 2881 // SBB $tmp,$src.hi | |
| 2882 emit_opcode( cbuf, 0x1B ); | |
| 2883 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg) ); | |
| 2884 %} | |
| 2885 | |
| 2886 // Sniff, sniff... smells like Gnu Superoptimizer | |
| 2887 enc_class neg_long( eRegL dst ) %{ | |
| 2888 emit_opcode(cbuf,0xF7); // NEG hi | |
| 2889 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg)); | |
| 2890 emit_opcode(cbuf,0xF7); // NEG lo | |
| 2891 emit_rm (cbuf,0x3, 0x3, $dst$$reg ); | |
| 2892 emit_opcode(cbuf,0x83); // SBB hi,0 | |
| 2893 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg)); | |
| 2894 emit_d8 (cbuf,0 ); | |
| 2895 %} | |
| 2896 | |
| 2897 enc_class enc_pop_rdx() %{ | |
| 2898 emit_opcode(cbuf,0x5A); | |
| 2899 %} | |
| 2900 | |
| 2901 enc_class enc_rethrow() %{ | |
| 1748 | 2902 cbuf.set_insts_mark(); |
| 0 | 2903 emit_opcode(cbuf, 0xE9); // jmp entry |
| 1748 | 2904 emit_d32_reloc(cbuf, (int)OptoRuntime::rethrow_stub() - ((int)cbuf.insts_end())-4, |
| 0 | 2905 runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 2906 %} | |
| 2907 | |
| 2908 | |
| 2909 // Convert a double to an int. Java semantics require we do complex | |
| 2910 // manglelations in the corner cases. So we set the rounding mode to | |
| 2911 // 'zero', store the darned double down as an int, and reset the | |
| 2912 // rounding mode to 'nearest'. The hardware throws an exception which | |
| 2913 // patches up the correct value directly to the stack. | |
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2914 enc_class DPR2I_encoding( regDPR src ) %{ |
| 0 | 2915 // Flip to round-to-zero mode. We attempted to allow invalid-op |
| 2916 // exceptions here, so that a NAN or other corner-case value will | |
| 2917 // thrown an exception (but normal values get converted at full speed). | |
| 2918 // However, I2C adapters and other float-stack manglers leave pending | |
| 2919 // invalid-op exceptions hanging. We would have to clear them before | |
| 2920 // enabling them and that is more expensive than just testing for the | |
| 2921 // invalid value Intel stores down in the corner cases. | |
| 2922 emit_opcode(cbuf,0xD9); // FLDCW trunc | |
| 2923 emit_opcode(cbuf,0x2D); | |
| 2924 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc()); | |
| 2925 // Allocate a word | |
| 2926 emit_opcode(cbuf,0x83); // SUB ESP,4 | |
| 2927 emit_opcode(cbuf,0xEC); | |
| 2928 emit_d8(cbuf,0x04); | |
| 2929 // Encoding assumes a double has been pushed into FPR0. | |
| 2930 // Store down the double as an int, popping the FPU stack | |
| 2931 emit_opcode(cbuf,0xDB); // FISTP [ESP] | |
| 2932 emit_opcode(cbuf,0x1C); | |
| 2933 emit_d8(cbuf,0x24); | |
| 2934 // Restore the rounding mode; mask the exception | |
| 2935 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode | |
| 2936 emit_opcode(cbuf,0x2D); | |
| 2937 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode() | |
| 2938 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24() | |
| 2939 : (int)StubRoutines::addr_fpu_cntrl_wrd_std()); | |
| 2940 | |
| 2941 // Load the converted int; adjust CPU stack | |
| 2942 emit_opcode(cbuf,0x58); // POP EAX | |
| 2943 emit_opcode(cbuf,0x3D); // CMP EAX,imm | |
| 2944 emit_d32 (cbuf,0x80000000); // 0x80000000 | |
| 2945 emit_opcode(cbuf,0x75); // JNE around_slow_call | |
| 2946 emit_d8 (cbuf,0x07); // Size of slow_call | |
| 2947 // Push src onto stack slow-path | |
| 2948 emit_opcode(cbuf,0xD9 ); // FLD ST(i) | |
| 2949 emit_d8 (cbuf,0xC0-1+$src$$reg ); | |
| 2950 // CALL directly to the runtime | |
| 1748 | 2951 cbuf.set_insts_mark(); |
| 0 | 2952 emit_opcode(cbuf,0xE8); // Call into runtime |
| 1748 | 2953 emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 0 | 2954 // Carry on here... |
| 2955 %} | |
| 2956 | |
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2957 enc_class DPR2L_encoding( regDPR src ) %{ |
| 0 | 2958 emit_opcode(cbuf,0xD9); // FLDCW trunc |
| 2959 emit_opcode(cbuf,0x2D); | |
| 2960 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc()); | |
| 2961 // Allocate a word | |
| 2962 emit_opcode(cbuf,0x83); // SUB ESP,8 | |
| 2963 emit_opcode(cbuf,0xEC); | |
| 2964 emit_d8(cbuf,0x08); | |
| 2965 // Encoding assumes a double has been pushed into FPR0. | |
| 2966 // Store down the double as a long, popping the FPU stack | |
| 2967 emit_opcode(cbuf,0xDF); // FISTP [ESP] | |
| 2968 emit_opcode(cbuf,0x3C); | |
| 2969 emit_d8(cbuf,0x24); | |
| 2970 // Restore the rounding mode; mask the exception | |
| 2971 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode | |
| 2972 emit_opcode(cbuf,0x2D); | |
| 2973 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode() | |
| 2974 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24() | |
| 2975 : (int)StubRoutines::addr_fpu_cntrl_wrd_std()); | |
| 2976 | |
| 2977 // Load the converted int; adjust CPU stack | |
| 2978 emit_opcode(cbuf,0x58); // POP EAX | |
| 2979 emit_opcode(cbuf,0x5A); // POP EDX | |
| 2980 emit_opcode(cbuf,0x81); // CMP EDX,imm | |
| 2981 emit_d8 (cbuf,0xFA); // rdx | |
| 2982 emit_d32 (cbuf,0x80000000); // 0x80000000 | |
| 2983 emit_opcode(cbuf,0x75); // JNE around_slow_call | |
| 2984 emit_d8 (cbuf,0x07+4); // Size of slow_call | |
| 2985 emit_opcode(cbuf,0x85); // TEST EAX,EAX | |
| 2986 emit_opcode(cbuf,0xC0); // 2/rax,/rax, | |
| 2987 emit_opcode(cbuf,0x75); // JNE around_slow_call | |
| 2988 emit_d8 (cbuf,0x07); // Size of slow_call | |
| 2989 // Push src onto stack slow-path | |
| 2990 emit_opcode(cbuf,0xD9 ); // FLD ST(i) | |
| 2991 emit_d8 (cbuf,0xC0-1+$src$$reg ); | |
| 2992 // CALL directly to the runtime | |
| 1748 | 2993 cbuf.set_insts_mark(); |
| 0 | 2994 emit_opcode(cbuf,0xE8); // Call into runtime |
| 1748 | 2995 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 0 | 2996 // Carry on here... |
| 2997 %} | |
| 2998 | |
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2999 enc_class FMul_ST_reg( eRegFPR src1 ) %{ |
| 0 | 3000 // Operand was loaded from memory into fp ST (stack top) |
| 3001 // FMUL ST,$src /* D8 C8+i */ | |
| 3002 emit_opcode(cbuf, 0xD8); | |
| 3003 emit_opcode(cbuf, 0xC8 + $src1$$reg); | |
| 3004 %} | |
| 3005 | |
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3006 enc_class FAdd_ST_reg( eRegFPR src2 ) %{ |
| 0 | 3007 // FADDP ST,src2 /* D8 C0+i */ |
| 3008 emit_opcode(cbuf, 0xD8); | |
| 3009 emit_opcode(cbuf, 0xC0 + $src2$$reg); | |
| 3010 //could use FADDP src2,fpST /* DE C0+i */ | |
| 3011 %} | |
| 3012 | |
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3013 enc_class FAddP_reg_ST( eRegFPR src2 ) %{ |
| 0 | 3014 // FADDP src2,ST /* DE C0+i */ |
| 3015 emit_opcode(cbuf, 0xDE); | |
| 3016 emit_opcode(cbuf, 0xC0 + $src2$$reg); | |
| 3017 %} | |
| 3018 | |
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3019 enc_class subFPR_divFPR_encode( eRegFPR src1, eRegFPR src2) %{ |
| 0 | 3020 // Operand has been loaded into fp ST (stack top) |
| 3021 // FSUB ST,$src1 | |
| 3022 emit_opcode(cbuf, 0xD8); | |
| 3023 emit_opcode(cbuf, 0xE0 + $src1$$reg); | |
| 3024 | |
| 3025 // FDIV | |
| 3026 emit_opcode(cbuf, 0xD8); | |
| 3027 emit_opcode(cbuf, 0xF0 + $src2$$reg); | |
| 3028 %} | |
| 3029 | |
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3030 enc_class MulFAddF (eRegFPR src1, eRegFPR src2) %{ |
| 0 | 3031 // Operand was loaded from memory into fp ST (stack top) |
| 3032 // FADD ST,$src /* D8 C0+i */ | |
| 3033 emit_opcode(cbuf, 0xD8); | |
| 3034 emit_opcode(cbuf, 0xC0 + $src1$$reg); | |
| 3035 | |
| 3036 // FMUL ST,src2 /* D8 C*+i */ | |
| 3037 emit_opcode(cbuf, 0xD8); | |
| 3038 emit_opcode(cbuf, 0xC8 + $src2$$reg); | |
| 3039 %} | |
| 3040 | |
| 3041 | |
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3042 enc_class MulFAddFreverse (eRegFPR src1, eRegFPR src2) %{ |
| 0 | 3043 // Operand was loaded from memory into fp ST (stack top) |
| 3044 // FADD ST,$src /* D8 C0+i */ | |
| 3045 emit_opcode(cbuf, 0xD8); | |
| 3046 emit_opcode(cbuf, 0xC0 + $src1$$reg); | |
| 3047 | |
| 3048 // FMULP src2,ST /* DE C8+i */ | |
| 3049 emit_opcode(cbuf, 0xDE); | |
| 3050 emit_opcode(cbuf, 0xC8 + $src2$$reg); | |
| 3051 %} | |
| 3052 | |
| 3053 // Atomically load the volatile long | |
| 3054 enc_class enc_loadL_volatile( memory mem, stackSlotL dst ) %{ | |
| 3055 emit_opcode(cbuf,0xDF); | |
| 3056 int rm_byte_opcode = 0x05; | |
| 3057 int base = $mem$$base; | |
| 3058 int index = $mem$$index; | |
| 3059 int scale = $mem$$scale; | |
| 3060 int displace = $mem$$disp; | |
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3061 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals |
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3062 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc); |
| 0 | 3063 store_to_stackslot( cbuf, 0x0DF, 0x07, $dst$$disp ); |
| 3064 %} | |
| 3065 | |
| 3066 // Volatile Store Long. Must be atomic, so move it into | |
| 3067 // the FP TOS and then do a 64-bit FIST. Has to probe the | |
| 3068 // target address before the store (for null-ptr checks) | |
| 3069 // so the memory operand is used twice in the encoding. | |
| 3070 enc_class enc_storeL_volatile( memory mem, stackSlotL src ) %{ | |
| 3071 store_to_stackslot( cbuf, 0x0DF, 0x05, $src$$disp ); | |
| 1748 | 3072 cbuf.set_insts_mark(); // Mark start of FIST in case $mem has an oop |
| 0 | 3073 emit_opcode(cbuf,0xDF); |
| 3074 int rm_byte_opcode = 0x07; | |
| 3075 int base = $mem$$base; | |
| 3076 int index = $mem$$index; | |
| 3077 int scale = $mem$$scale; | |
| 3078 int displace = $mem$$disp; | |
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3079 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals |
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3080 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc); |
| 0 | 3081 %} |
| 3082 | |
| 3083 // Safepoint Poll. This polls the safepoint page, and causes an | |
| 3084 // exception if it is not readable. Unfortunately, it kills the condition code | |
| 3085 // in the process | |
| 3086 // We current use TESTL [spp],EDI | |
| 3087 // A better choice might be TESTB [spp + pagesize() - CacheLineSize()],0 | |
| 3088 | |
| 3089 enc_class Safepoint_Poll() %{ | |
| 1748 | 3090 cbuf.relocate(cbuf.insts_mark(), relocInfo::poll_type, 0); |
| 0 | 3091 emit_opcode(cbuf,0x85); |
| 3092 emit_rm (cbuf, 0x0, 0x7, 0x5); | |
| 3093 emit_d32(cbuf, (intptr_t)os::get_polling_page()); | |
| 3094 %} | |
| 3095 %} | |
| 3096 | |
| 3097 | |
| 3098 //----------FRAME-------------------------------------------------------------- | |
| 3099 // Definition of frame structure and management information. | |
| 3100 // | |
| 3101 // S T A C K L A Y O U T Allocators stack-slot number | |
| 3102 // | (to get allocators register number | |
| 3103 // G Owned by | | v add OptoReg::stack0()) | |
| 3104 // r CALLER | | | |
| 3105 // o | +--------+ pad to even-align allocators stack-slot | |
| 3106 // w V | pad0 | numbers; owned by CALLER | |
| 3107 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned | |
| 3108 // h ^ | in | 5 | |
| 3109 // | | args | 4 Holes in incoming args owned by SELF | |
| 3110 // | | | | 3 | |
| 3111 // | | +--------+ | |
| 3112 // V | | old out| Empty on Intel, window on Sparc | |
| 3113 // | old |preserve| Must be even aligned. | |
| 3114 // | SP-+--------+----> Matcher::_old_SP, even aligned | |
| 3115 // | | in | 3 area for Intel ret address | |
| 3116 // Owned by |preserve| Empty on Sparc. | |
| 3117 // SELF +--------+ | |
| 3118 // | | pad2 | 2 pad to align old SP | |
| 3119 // | +--------+ 1 | |
| 3120 // | | locks | 0 | |
| 3121 // | +--------+----> OptoReg::stack0(), even aligned | |
| 3122 // | | pad1 | 11 pad to align new SP | |
| 3123 // | +--------+ | |
| 3124 // | | | 10 | |
| 3125 // | | spills | 9 spills | |
| 3126 // V | | 8 (pad0 slot for callee) | |
| 3127 // -----------+--------+----> Matcher::_out_arg_limit, unaligned | |
| 3128 // ^ | out | 7 | |
| 3129 // | | args | 6 Holes in outgoing args owned by CALLEE | |
| 3130 // Owned by +--------+ | |
| 3131 // CALLEE | new out| 6 Empty on Intel, window on Sparc | |
| 3132 // | new |preserve| Must be even-aligned. | |
| 3133 // | SP-+--------+----> Matcher::_new_SP, even aligned | |
| 3134 // | | | | |
| 3135 // | |
| 3136 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is | |
| 3137 // known from SELF's arguments and the Java calling convention. | |
| 3138 // Region 6-7 is determined per call site. | |
| 3139 // Note 2: If the calling convention leaves holes in the incoming argument | |
| 3140 // area, those holes are owned by SELF. Holes in the outgoing area | |
| 3141 // are owned by the CALLEE. Holes should not be nessecary in the | |
| 3142 // incoming area, as the Java calling convention is completely under | |
| 3143 // the control of the AD file. Doubles can be sorted and packed to | |
| 3144 // avoid holes. Holes in the outgoing arguments may be nessecary for | |
| 3145 // varargs C calling conventions. | |
| 3146 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is | |
| 3147 // even aligned with pad0 as needed. | |
| 3148 // Region 6 is even aligned. Region 6-7 is NOT even aligned; | |
| 3149 // region 6-11 is even aligned; it may be padded out more so that | |
| 3150 // the region from SP to FP meets the minimum stack alignment. | |
| 3151 | |
| 3152 frame %{ | |
| 3153 // What direction does stack grow in (assumed to be same for C & Java) | |
| 3154 stack_direction(TOWARDS_LOW); | |
| 3155 | |
| 3156 // These three registers define part of the calling convention | |
| 3157 // between compiled code and the interpreter. | |
| 3158 inline_cache_reg(EAX); // Inline Cache Register | |
| 3159 interpreter_method_oop_reg(EBX); // Method Oop Register when calling interpreter | |
| 3160 | |
| 3161 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset] | |
| 3162 cisc_spilling_operand_name(indOffset32); | |
| 3163 | |
| 3164 // Number of stack slots consumed by locking an object | |
| 3165 sync_stack_slots(1); | |
| 3166 | |
| 3167 // Compiled code's Frame Pointer | |
| 3168 frame_pointer(ESP); | |
| 3169 // Interpreter stores its frame pointer in a register which is | |
| 3170 // stored to the stack by I2CAdaptors. | |
| 3171 // I2CAdaptors convert from interpreted java to compiled java. | |
| 3172 interpreter_frame_pointer(EBP); | |
| 3173 | |
| 3174 // Stack alignment requirement | |
| 3175 // Alignment size in bytes (128-bit -> 16 bytes) | |
| 3176 stack_alignment(StackAlignmentInBytes); | |
| 3177 | |
| 3178 // Number of stack slots between incoming argument block and the start of | |
| 3179 // a new frame. The PROLOG must add this many slots to the stack. The | |
| 3180 // EPILOG must remove this many slots. Intel needs one slot for | |
| 3181 // return address and one for rbp, (must save rbp) | |
| 3182 in_preserve_stack_slots(2+VerifyStackAtCalls); | |
| 3183 | |
| 3184 // Number of outgoing stack slots killed above the out_preserve_stack_slots | |
| 3185 // for calls to C. Supports the var-args backing area for register parms. | |
| 3186 varargs_C_out_slots_killed(0); | |
| 3187 | |
| 3188 // The after-PROLOG location of the return address. Location of | |
| 3189 // return address specifies a type (REG or STACK) and a number | |
| 3190 // representing the register number (i.e. - use a register name) or | |
| 3191 // stack slot. | |
| 3192 // Ret Addr is on stack in slot 0 if no locks or verification or alignment. | |
| 3193 // Otherwise, it is above the locks and verification slot and alignment word | |
| 3194 return_addr(STACK - 1 + | |
| 4950 | 3195 round_to((Compile::current()->in_preserve_stack_slots() + |
| 3196 Compile::current()->fixed_slots()), | |
| 3197 stack_alignment_in_slots())); | |
| 0 | 3198 |
| 3199 // Body of function which returns an integer array locating | |
| 3200 // arguments either in registers or in stack slots. Passed an array | |
| 3201 // of ideal registers called "sig" and a "length" count. Stack-slot | |
| 3202 // offsets are based on outgoing arguments, i.e. a CALLER setting up | |
| 3203 // arguments for a CALLEE. Incoming stack arguments are | |
| 3204 // automatically biased by the preserve_stack_slots field above. | |
| 3205 calling_convention %{ | |
| 3206 // No difference between ingoing/outgoing just pass false | |
| 3207 SharedRuntime::java_calling_convention(sig_bt, regs, length, false); | |
| 3208 %} | |
| 3209 | |
| 3210 | |
| 3211 // Body of function which returns an integer array locating | |
| 3212 // arguments either in registers or in stack slots. Passed an array | |
| 3213 // of ideal registers called "sig" and a "length" count. Stack-slot | |
| 3214 // offsets are based on outgoing arguments, i.e. a CALLER setting up | |
| 3215 // arguments for a CALLEE. Incoming stack arguments are | |
| 3216 // automatically biased by the preserve_stack_slots field above. | |
| 3217 c_calling_convention %{ | |
| 3218 // This is obviously always outgoing | |
|
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3219 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length); |
| 0 | 3220 %} |
| 3221 | |
| 3222 // Location of C & interpreter return values | |
| 3223 c_return_value %{ | |
| 3224 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); | |
|
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3225 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num }; |
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3226 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num }; |
| 0 | 3227 |
| 3228 // in SSE2+ mode we want to keep the FPU stack clean so pretend | |
| 3229 // that C functions return float and double results in XMM0. | |
| 3230 if( ideal_reg == Op_RegD && UseSSE>=2 ) | |
|
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3231 return OptoRegPair(XMM0b_num,XMM0_num); |
| 0 | 3232 if( ideal_reg == Op_RegF && UseSSE>=2 ) |
|
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3233 return OptoRegPair(OptoReg::Bad,XMM0_num); |
| 0 | 3234 |
| 3235 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]); | |
| 3236 %} | |
| 3237 | |
| 3238 // Location of return values | |
| 3239 return_value %{ | |
| 3240 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); | |
|
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3241 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num }; |
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3242 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num }; |
| 0 | 3243 if( ideal_reg == Op_RegD && UseSSE>=2 ) |
|
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3244 return OptoRegPair(XMM0b_num,XMM0_num); |
| 0 | 3245 if( ideal_reg == Op_RegF && UseSSE>=1 ) |
|
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3246 return OptoRegPair(OptoReg::Bad,XMM0_num); |
| 0 | 3247 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]); |
| 3248 %} | |
| 3249 | |
| 3250 %} | |
| 3251 | |
| 3252 //----------ATTRIBUTES--------------------------------------------------------- | |
| 3253 //----------Operand Attributes------------------------------------------------- | |
| 3254 op_attrib op_cost(0); // Required cost attribute | |
| 3255 | |
| 3256 //----------Instruction Attributes--------------------------------------------- | |
| 3257 ins_attrib ins_cost(100); // Required cost attribute | |
| 3258 ins_attrib ins_size(8); // Required size attribute (in bits) | |
| 3259 ins_attrib ins_short_branch(0); // Required flag: is this instruction a | |
| 3260 // non-matching short branch variant of some | |
| 3261 // long branch? | |
| 3262 ins_attrib ins_alignment(1); // Required alignment attribute (must be a power of 2) | |
| 3263 // specifies the alignment that some part of the instruction (not | |
| 3264 // necessarily the start) requires. If > 1, a compute_padding() | |
| 3265 // function must be provided for the instruction | |
| 3266 | |
| 3267 //----------OPERANDS----------------------------------------------------------- | |
| 3268 // Operand definitions must precede instruction definitions for correct parsing | |
| 3269 // in the ADLC because operands constitute user defined types which are used in | |
| 3270 // instruction definitions. | |
| 3271 | |
| 3272 //----------Simple Operands---------------------------------------------------- | |
| 3273 // Immediate Operands | |
| 3274 // Integer Immediate | |
| 3275 operand immI() %{ | |
| 3276 match(ConI); | |
| 3277 | |
| 3278 op_cost(10); | |
| 3279 format %{ %} | |
| 3280 interface(CONST_INTER); | |
| 3281 %} | |
| 3282 | |
| 3283 // Constant for test vs zero | |
| 3284 operand immI0() %{ | |
| 3285 predicate(n->get_int() == 0); | |
| 3286 match(ConI); | |
| 3287 | |
| 3288 op_cost(0); | |
| 3289 format %{ %} | |
| 3290 interface(CONST_INTER); | |
| 3291 %} | |
| 3292 | |
| 3293 // Constant for increment | |
| 3294 operand immI1() %{ | |
| 3295 predicate(n->get_int() == 1); | |
| 3296 match(ConI); | |
| 3297 | |
| 3298 op_cost(0); | |
| 3299 format %{ %} | |
| 3300 interface(CONST_INTER); | |
| 3301 %} | |
| 3302 | |
| 3303 // Constant for decrement | |
| 3304 operand immI_M1() %{ | |
| 3305 predicate(n->get_int() == -1); | |
| 3306 match(ConI); | |
| 3307 | |
| 3308 op_cost(0); | |
| 3309 format %{ %} | |
| 3310 interface(CONST_INTER); | |
| 3311 %} | |
| 3312 | |
| 3313 // Valid scale values for addressing modes | |
| 3314 operand immI2() %{ | |
| 3315 predicate(0 <= n->get_int() && (n->get_int() <= 3)); | |
| 3316 match(ConI); | |
| 3317 | |
| 3318 format %{ %} | |
| 3319 interface(CONST_INTER); | |
| 3320 %} | |
| 3321 | |
| 3322 operand immI8() %{ | |
| 3323 predicate((-128 <= n->get_int()) && (n->get_int() <= 127)); | |
| 3324 match(ConI); | |
| 3325 | |
| 3326 op_cost(5); | |
| 3327 format %{ %} | |
| 3328 interface(CONST_INTER); | |
| 3329 %} | |
| 3330 | |
| 3331 operand immI16() %{ | |
| 3332 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767)); | |
| 3333 match(ConI); | |
| 3334 | |
| 3335 op_cost(10); | |
| 3336 format %{ %} | |
| 3337 interface(CONST_INTER); | |
| 3338 %} | |
| 3339 | |
|
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3340 // Int Immediate non-negative |
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3341 operand immU31() |
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3342 %{ |
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3343 predicate(n->get_int() >= 0); |
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3344 match(ConI); |
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3345 |
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3346 op_cost(0); |
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3347 format %{ %} |
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3348 interface(CONST_INTER); |
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3349 %} |
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3350 |
| 0 | 3351 // Constant for long shifts |
| 3352 operand immI_32() %{ | |
| 3353 predicate( n->get_int() == 32 ); | |
| 3354 match(ConI); | |
| 3355 | |
| 3356 op_cost(0); | |
| 3357 format %{ %} | |
| 3358 interface(CONST_INTER); | |
| 3359 %} | |
| 3360 | |
| 3361 operand immI_1_31() %{ | |
| 3362 predicate( n->get_int() >= 1 && n->get_int() <= 31 ); | |
| 3363 match(ConI); | |
| 3364 | |
| 3365 op_cost(0); | |
| 3366 format %{ %} | |
| 3367 interface(CONST_INTER); | |
| 3368 %} | |
| 3369 | |
| 3370 operand immI_32_63() %{ | |
| 3371 predicate( n->get_int() >= 32 && n->get_int() <= 63 ); | |
| 3372 match(ConI); | |
| 3373 op_cost(0); | |
| 3374 | |
| 3375 format %{ %} | |
| 3376 interface(CONST_INTER); | |
| 3377 %} | |
| 3378 | |
| 219 | 3379 operand immI_1() %{ |
| 3380 predicate( n->get_int() == 1 ); | |
| 3381 match(ConI); | |
| 3382 | |
| 3383 op_cost(0); | |
| 3384 format %{ %} | |
| 3385 interface(CONST_INTER); | |
| 3386 %} | |
| 3387 | |
| 3388 operand immI_2() %{ | |
| 3389 predicate( n->get_int() == 2 ); | |
| 3390 match(ConI); | |
| 3391 | |
| 3392 op_cost(0); | |
| 3393 format %{ %} | |
| 3394 interface(CONST_INTER); | |
| 3395 %} | |
| 3396 | |
| 3397 operand immI_3() %{ | |
| 3398 predicate( n->get_int() == 3 ); | |
| 3399 match(ConI); | |
| 3400 | |
| 3401 op_cost(0); | |
| 3402 format %{ %} | |
| 3403 interface(CONST_INTER); | |
| 3404 %} | |
| 3405 | |
| 0 | 3406 // Pointer Immediate |
| 3407 operand immP() %{ | |
| 3408 match(ConP); | |
| 3409 | |
| 3410 op_cost(10); | |
| 3411 format %{ %} | |
| 3412 interface(CONST_INTER); | |
| 3413 %} | |
| 3414 | |
| 3415 // NULL Pointer Immediate | |
| 3416 operand immP0() %{ | |
| 3417 predicate( n->get_ptr() == 0 ); | |
| 3418 match(ConP); | |
| 3419 op_cost(0); | |
| 3420 | |
| 3421 format %{ %} | |
| 3422 interface(CONST_INTER); | |
| 3423 %} | |
| 3424 | |
| 3425 // Long Immediate | |
| 3426 operand immL() %{ | |
| 3427 match(ConL); | |
| 3428 | |
| 3429 op_cost(20); | |
| 3430 format %{ %} | |
| 3431 interface(CONST_INTER); | |
| 3432 %} | |
| 3433 | |
| 3434 // Long Immediate zero | |
| 3435 operand immL0() %{ | |
| 3436 predicate( n->get_long() == 0L ); | |
| 3437 match(ConL); | |
| 3438 op_cost(0); | |
| 3439 | |
| 3440 format %{ %} | |
| 3441 interface(CONST_INTER); | |
| 3442 %} | |
| 3443 | |
| 403 | 3444 // Long Immediate zero |
| 3445 operand immL_M1() %{ | |
| 3446 predicate( n->get_long() == -1L ); | |
| 3447 match(ConL); | |
| 3448 op_cost(0); | |
| 3449 | |
| 3450 format %{ %} | |
| 3451 interface(CONST_INTER); | |
| 3452 %} | |
| 3453 | |
| 0 | 3454 // Long immediate from 0 to 127. |
| 3455 // Used for a shorter form of long mul by 10. | |
| 3456 operand immL_127() %{ | |
| 3457 predicate((0 <= n->get_long()) && (n->get_long() <= 127)); | |
| 3458 match(ConL); | |
| 3459 op_cost(0); | |
| 3460 | |
| 3461 format %{ %} | |
| 3462 interface(CONST_INTER); | |
| 3463 %} | |
| 3464 | |
| 3465 // Long Immediate: low 32-bit mask | |
| 3466 operand immL_32bits() %{ | |
| 3467 predicate(n->get_long() == 0xFFFFFFFFL); | |
| 3468 match(ConL); | |
| 3469 op_cost(0); | |
| 3470 | |
| 3471 format %{ %} | |
| 3472 interface(CONST_INTER); | |
| 3473 %} | |
| 3474 | |
| 3475 // Long Immediate: low 32-bit mask | |
| 3476 operand immL32() %{ | |
| 3477 predicate(n->get_long() == (int)(n->get_long())); | |
| 3478 match(ConL); | |
| 3479 op_cost(20); | |
| 3480 | |
| 3481 format %{ %} | |
| 3482 interface(CONST_INTER); | |
| 3483 %} | |
| 3484 | |
| 3485 //Double Immediate zero | |
|
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3486 operand immDPR0() %{ |
| 0 | 3487 // Do additional (and counter-intuitive) test against NaN to work around VC++ |
| 3488 // bug that generates code such that NaNs compare equal to 0.0 | |
| 3489 predicate( UseSSE<=1 && n->getd() == 0.0 && !g_isnan(n->getd()) ); | |
| 3490 match(ConD); | |
| 3491 | |
| 3492 op_cost(5); | |
| 3493 format %{ %} | |
| 3494 interface(CONST_INTER); | |
| 3495 %} | |
| 3496 | |
| 2008 | 3497 // Double Immediate one |
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3498 operand immDPR1() %{ |
| 0 | 3499 predicate( UseSSE<=1 && n->getd() == 1.0 ); |
| 3500 match(ConD); | |
| 3501 | |
| 3502 op_cost(5); | |
| 3503 format %{ %} | |
| 3504 interface(CONST_INTER); | |
| 3505 %} | |
| 3506 | |
| 3507 // Double Immediate | |
|
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3508 operand immDPR() %{ |
| 0 | 3509 predicate(UseSSE<=1); |
| 3510 match(ConD); | |
| 3511 | |
| 3512 op_cost(5); | |
| 3513 format %{ %} | |
| 3514 interface(CONST_INTER); | |
| 3515 %} | |
| 3516 | |
|
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3517 operand immD() %{ |
| 0 | 3518 predicate(UseSSE>=2); |
| 3519 match(ConD); | |
| 3520 | |
| 3521 op_cost(5); | |
| 3522 format %{ %} | |
| 3523 interface(CONST_INTER); | |
| 3524 %} | |
| 3525 | |
| 3526 // Double Immediate zero | |
|
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3527 operand immD0() %{ |
| 0 | 3528 // Do additional (and counter-intuitive) test against NaN to work around VC++ |
| 3529 // bug that generates code such that NaNs compare equal to 0.0 AND do not | |
| 3530 // compare equal to -0.0. | |
| 3531 predicate( UseSSE>=2 && jlong_cast(n->getd()) == 0 ); | |
| 3532 match(ConD); | |
| 3533 | |
| 3534 format %{ %} | |
| 3535 interface(CONST_INTER); | |
| 3536 %} | |
| 3537 | |
| 3538 // Float Immediate zero | |
|
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3539 operand immFPR0() %{ |
| 2008 | 3540 predicate(UseSSE == 0 && n->getf() == 0.0F); |
| 3541 match(ConF); | |
| 3542 | |
| 3543 op_cost(5); | |
| 3544 format %{ %} | |
| 3545 interface(CONST_INTER); | |
| 3546 %} | |
| 3547 | |
| 3548 // Float Immediate one | |
|
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3549 operand immFPR1() %{ |
| 2008 | 3550 predicate(UseSSE == 0 && n->getf() == 1.0F); |
| 0 | 3551 match(ConF); |
| 3552 | |
| 3553 op_cost(5); | |
| 3554 format %{ %} | |
| 3555 interface(CONST_INTER); | |
| 3556 %} | |
| 3557 | |
| 3558 // Float Immediate | |
|
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3559 operand immFPR() %{ |
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3560 predicate( UseSSE == 0 ); |
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3561 match(ConF); |
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3562 |
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|
3563 op_cost(5); |
|
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3564 format %{ %} |
|
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3565 interface(CONST_INTER); |
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3566 %} |
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|
3567 |
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3568 // Float Immediate |
| 0 | 3569 operand immF() %{ |
| 3570 predicate(UseSSE >= 1); | |
| 3571 match(ConF); | |
| 3572 | |
| 3573 op_cost(5); | |
| 3574 format %{ %} | |
| 3575 interface(CONST_INTER); | |
| 3576 %} | |
| 3577 | |
| 3578 // Float Immediate zero. Zero and not -0.0 | |
|
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3579 operand immF0() %{ |
| 0 | 3580 predicate( UseSSE >= 1 && jint_cast(n->getf()) == 0 ); |
| 3581 match(ConF); | |
| 3582 | |
| 3583 op_cost(5); | |
| 3584 format %{ %} | |
| 3585 interface(CONST_INTER); | |
| 3586 %} | |
| 3587 | |
| 3588 // Immediates for special shifts (sign extend) | |
| 3589 | |
| 3590 // Constants for increment | |
| 3591 operand immI_16() %{ | |
| 3592 predicate( n->get_int() == 16 ); | |
| 3593 match(ConI); | |
| 3594 | |
| 3595 format %{ %} | |
| 3596 interface(CONST_INTER); | |
| 3597 %} | |
| 3598 | |
| 3599 operand immI_24() %{ | |
| 3600 predicate( n->get_int() == 24 ); | |
| 3601 match(ConI); | |
| 3602 | |
| 3603 format %{ %} | |
| 3604 interface(CONST_INTER); | |
| 3605 %} | |
| 3606 | |
| 3607 // Constant for byte-wide masking | |
| 3608 operand immI_255() %{ | |
| 3609 predicate( n->get_int() == 255 ); | |
| 3610 match(ConI); | |
| 3611 | |
| 3612 format %{ %} | |
| 3613 interface(CONST_INTER); | |
| 3614 %} | |
| 3615 | |
| 785 | 3616 // Constant for short-wide masking |
| 3617 operand immI_65535() %{ | |
| 3618 predicate(n->get_int() == 65535); | |
| 3619 match(ConI); | |
| 3620 | |
| 3621 format %{ %} | |
| 3622 interface(CONST_INTER); | |
| 3623 %} | |
| 3624 | |
| 0 | 3625 // Register Operands |
| 3626 // Integer Register | |
|
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3627 operand rRegI() %{ |
|
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|
3628 constraint(ALLOC_IN_RC(int_reg)); |
| 0 | 3629 match(RegI); |
| 3630 match(xRegI); | |
| 3631 match(eAXRegI); | |
| 3632 match(eBXRegI); | |
| 3633 match(eCXRegI); | |
| 3634 match(eDXRegI); | |
| 3635 match(eDIRegI); | |
| 3636 match(eSIRegI); | |
| 3637 | |
| 3638 format %{ %} | |
| 3639 interface(REG_INTER); | |
| 3640 %} | |
| 3641 | |
| 3642 // Subset of Integer Register | |
|
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3643 operand xRegI(rRegI reg) %{ |
|
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3644 constraint(ALLOC_IN_RC(int_x_reg)); |
| 0 | 3645 match(reg); |
| 3646 match(eAXRegI); | |
| 3647 match(eBXRegI); | |
| 3648 match(eCXRegI); | |
| 3649 match(eDXRegI); | |
| 3650 | |
| 3651 format %{ %} | |
| 3652 interface(REG_INTER); | |
| 3653 %} | |
| 3654 | |
| 3655 // Special Registers | |
| 3656 operand eAXRegI(xRegI reg) %{ | |
| 3657 constraint(ALLOC_IN_RC(eax_reg)); | |
| 3658 match(reg); | |
|
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3659 match(rRegI); |
| 0 | 3660 |
| 3661 format %{ "EAX" %} | |
| 3662 interface(REG_INTER); | |
| 3663 %} | |
| 3664 | |
| 3665 // Special Registers | |
| 3666 operand eBXRegI(xRegI reg) %{ | |
| 3667 constraint(ALLOC_IN_RC(ebx_reg)); | |
| 3668 match(reg); | |
|
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|
3669 match(rRegI); |
| 0 | 3670 |
| 3671 format %{ "EBX" %} | |
| 3672 interface(REG_INTER); | |
| 3673 %} | |
| 3674 | |
| 3675 operand eCXRegI(xRegI reg) %{ | |
| 3676 constraint(ALLOC_IN_RC(ecx_reg)); | |
| 3677 match(reg); | |
|
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3678 match(rRegI); |
| 0 | 3679 |
| 3680 format %{ "ECX" %} | |
| 3681 interface(REG_INTER); | |
| 3682 %} | |
| 3683 | |
| 3684 operand eDXRegI(xRegI reg) %{ | |
| 3685 constraint(ALLOC_IN_RC(edx_reg)); | |
| 3686 match(reg); | |
|
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|
3687 match(rRegI); |
| 0 | 3688 |
| 3689 format %{ "EDX" %} | |
| 3690 interface(REG_INTER); | |
| 3691 %} | |
| 3692 | |
| 3693 operand eDIRegI(xRegI reg) %{ | |
| 3694 constraint(ALLOC_IN_RC(edi_reg)); | |
| 3695 match(reg); | |
|
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|
3696 match(rRegI); |
| 0 | 3697 |
| 3698 format %{ "EDI" %} | |
| 3699 interface(REG_INTER); | |
| 3700 %} | |
| 3701 | |
| 3702 operand naxRegI() %{ | |
| 3703 constraint(ALLOC_IN_RC(nax_reg)); | |
| 3704 match(RegI); | |
| 3705 match(eCXRegI); | |
| 3706 match(eDXRegI); | |
| 3707 match(eSIRegI); | |
| 3708 match(eDIRegI); | |
| 3709 | |
| 3710 format %{ %} | |
| 3711 interface(REG_INTER); | |
| 3712 %} | |
| 3713 | |
| 3714 operand nadxRegI() %{ | |
| 3715 constraint(ALLOC_IN_RC(nadx_reg)); | |
| 3716 match(RegI); | |
| 3717 match(eBXRegI); | |
| 3718 match(eCXRegI); | |
| 3719 match(eSIRegI); | |
| 3720 match(eDIRegI); | |
| 3721 | |
| 3722 format %{ %} | |
| 3723 interface(REG_INTER); | |
| 3724 %} | |
| 3725 | |
| 3726 operand ncxRegI() %{ | |
| 3727 constraint(ALLOC_IN_RC(ncx_reg)); | |
| 3728 match(RegI); | |
| 3729 match(eAXRegI); | |
| 3730 match(eDXRegI); | |
| 3731 match(eSIRegI); | |
| 3732 match(eDIRegI); | |
| 3733 | |
| 3734 format %{ %} | |
| 3735 interface(REG_INTER); | |
| 3736 %} | |
| 3737 | |
| 3738 // // This operand was used by cmpFastUnlock, but conflicted with 'object' reg | |
| 3739 // // | |
| 3740 operand eSIRegI(xRegI reg) %{ | |
| 3741 constraint(ALLOC_IN_RC(esi_reg)); | |
| 3742 match(reg); | |
|
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3743 match(rRegI); |
| 0 | 3744 |
| 3745 format %{ "ESI" %} | |
| 3746 interface(REG_INTER); | |
| 3747 %} | |
| 3748 | |
| 3749 // Pointer Register | |
| 3750 operand anyRegP() %{ | |
| 3751 constraint(ALLOC_IN_RC(any_reg)); | |
| 3752 match(RegP); | |
| 3753 match(eAXRegP); | |
| 3754 match(eBXRegP); | |
| 3755 match(eCXRegP); | |
| 3756 match(eDIRegP); | |
| 3757 match(eRegP); | |
| 3758 | |
| 3759 format %{ %} | |
| 3760 interface(REG_INTER); | |
| 3761 %} | |
| 3762 | |
| 3763 operand eRegP() %{ | |
|
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3764 constraint(ALLOC_IN_RC(int_reg)); |
| 0 | 3765 match(RegP); |
| 3766 match(eAXRegP); | |
| 3767 match(eBXRegP); | |
| 3768 match(eCXRegP); | |
| 3769 match(eDIRegP); | |
| 3770 | |
| 3771 format %{ %} | |
| 3772 interface(REG_INTER); | |
| 3773 %} | |
| 3774 | |
| 3775 // On windows95, EBP is not safe to use for implicit null tests. | |
| 3776 operand eRegP_no_EBP() %{ | |
|
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3777 constraint(ALLOC_IN_RC(int_reg_no_ebp)); |
| 0 | 3778 match(RegP); |
| 3779 match(eAXRegP); | |
| 3780 match(eBXRegP); | |
| 3781 match(eCXRegP); | |
| 3782 match(eDIRegP); | |
| 3783 | |
| 3784 op_cost(100); | |
| 3785 format %{ %} | |
| 3786 interface(REG_INTER); | |
| 3787 %} | |
| 3788 | |
| 3789 operand naxRegP() %{ | |
| 3790 constraint(ALLOC_IN_RC(nax_reg)); | |
| 3791 match(RegP); | |
| 3792 match(eBXRegP); | |
| 3793 match(eDXRegP); | |
| 3794 match(eCXRegP); | |
| 3795 match(eSIRegP); | |
| 3796 match(eDIRegP); | |
| 3797 | |
| 3798 format %{ %} | |
| 3799 interface(REG_INTER); | |
| 3800 %} | |
| 3801 | |
| 3802 operand nabxRegP() %{ | |
| 3803 constraint(ALLOC_IN_RC(nabx_reg)); | |
| 3804 match(RegP); | |
| 3805 match(eCXRegP); | |
| 3806 match(eDXRegP); | |
| 3807 match(eSIRegP); | |
| 3808 match(eDIRegP); | |
| 3809 | |
| 3810 format %{ %} | |
| 3811 interface(REG_INTER); | |
| 3812 %} | |
| 3813 | |
| 3814 operand pRegP() %{ | |
| 3815 constraint(ALLOC_IN_RC(p_reg)); | |
| 3816 match(RegP); | |
| 3817 match(eBXRegP); | |
| 3818 match(eDXRegP); | |
| 3819 match(eSIRegP); | |
| 3820 match(eDIRegP); | |
| 3821 | |
| 3822 format %{ %} | |
| 3823 interface(REG_INTER); | |
| 3824 %} | |
| 3825 | |
| 3826 // Special Registers | |
| 3827 // Return a pointer value | |
| 3828 operand eAXRegP(eRegP reg) %{ | |
| 3829 constraint(ALLOC_IN_RC(eax_reg)); | |
| 3830 match(reg); | |
| 3831 format %{ "EAX" %} | |
| 3832 interface(REG_INTER); | |
| 3833 %} | |
| 3834 | |
| 3835 // Used in AtomicAdd | |
| 3836 operand eBXRegP(eRegP reg) %{ | |
| 3837 constraint(ALLOC_IN_RC(ebx_reg)); | |
| 3838 match(reg); | |
| 3839 format %{ "EBX" %} | |
| 3840 interface(REG_INTER); | |
| 3841 %} | |
| 3842 | |
| 3843 // Tail-call (interprocedural jump) to interpreter | |
| 3844 operand eCXRegP(eRegP reg) %{ | |
| 3845 constraint(ALLOC_IN_RC(ecx_reg)); | |
| 3846 match(reg); | |
| 3847 format %{ "ECX" %} | |
| 3848 interface(REG_INTER); | |
| 3849 %} | |
| 3850 | |
| 3851 operand eSIRegP(eRegP reg) %{ | |
| 3852 constraint(ALLOC_IN_RC(esi_reg)); | |
| 3853 match(reg); | |
| 3854 format %{ "ESI" %} | |
| 3855 interface(REG_INTER); | |
| 3856 %} | |
| 3857 | |
| 3858 // Used in rep stosw | |
| 3859 operand eDIRegP(eRegP reg) %{ | |
| 3860 constraint(ALLOC_IN_RC(edi_reg)); | |
| 3861 match(reg); | |
| 3862 format %{ "EDI" %} | |
| 3863 interface(REG_INTER); | |
| 3864 %} | |
| 3865 | |
| 3866 operand eRegL() %{ | |
| 3867 constraint(ALLOC_IN_RC(long_reg)); | |
| 3868 match(RegL); | |
| 3869 match(eADXRegL); | |
| 3870 | |
| 3871 format %{ %} | |
| 3872 interface(REG_INTER); | |
| 3873 %} | |
| 3874 | |
| 3875 operand eADXRegL( eRegL reg ) %{ | |
| 3876 constraint(ALLOC_IN_RC(eadx_reg)); | |
| 3877 match(reg); | |
| 3878 | |
| 3879 format %{ "EDX:EAX" %} | |
| 3880 interface(REG_INTER); | |
| 3881 %} | |
| 3882 | |
| 3883 operand eBCXRegL( eRegL reg ) %{ | |
| 3884 constraint(ALLOC_IN_RC(ebcx_reg)); | |
| 3885 match(reg); | |
| 3886 | |
| 3887 format %{ "EBX:ECX" %} | |
| 3888 interface(REG_INTER); | |
| 3889 %} | |
| 3890 | |
| 3891 // Special case for integer high multiply | |
| 3892 operand eADXRegL_low_only() %{ | |
| 3893 constraint(ALLOC_IN_RC(eadx_reg)); | |
| 3894 match(RegL); | |
| 3895 | |
| 3896 format %{ "EAX" %} | |
| 3897 interface(REG_INTER); | |
| 3898 %} | |
| 3899 | |
| 3900 // Flags register, used as output of compare instructions | |
| 3901 operand eFlagsReg() %{ | |
| 3902 constraint(ALLOC_IN_RC(int_flags)); | |
| 3903 match(RegFlags); | |
| 3904 | |
| 3905 format %{ "EFLAGS" %} | |
| 3906 interface(REG_INTER); | |
| 3907 %} | |
| 3908 | |
| 3909 // Flags register, used as output of FLOATING POINT compare instructions | |
| 3910 operand eFlagsRegU() %{ | |
| 3911 constraint(ALLOC_IN_RC(int_flags)); | |
| 3912 match(RegFlags); | |
| 3913 | |
| 3914 format %{ "EFLAGS_U" %} | |
| 3915 interface(REG_INTER); | |
| 3916 %} | |
| 3917 | |
|
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|
3918 operand eFlagsRegUCF() %{ |
|
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|
3919 constraint(ALLOC_IN_RC(int_flags)); |
|
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|
3920 match(RegFlags); |
|
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|
3921 predicate(false); |
|
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|
3922 |
|
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|
3923 format %{ "EFLAGS_U_CF" %} |
|
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3924 interface(REG_INTER); |
|
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|
3925 %} |
|
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|
3926 |
| 0 | 3927 // Condition Code Register used by long compare |
| 3928 operand flagsReg_long_LTGE() %{ | |
| 3929 constraint(ALLOC_IN_RC(int_flags)); | |
| 3930 match(RegFlags); | |
| 3931 format %{ "FLAGS_LTGE" %} | |
| 3932 interface(REG_INTER); | |
| 3933 %} | |
| 3934 operand flagsReg_long_EQNE() %{ | |
| 3935 constraint(ALLOC_IN_RC(int_flags)); | |
| 3936 match(RegFlags); | |
| 3937 format %{ "FLAGS_EQNE" %} | |
| 3938 interface(REG_INTER); | |
| 3939 %} | |
| 3940 operand flagsReg_long_LEGT() %{ | |
| 3941 constraint(ALLOC_IN_RC(int_flags)); | |
| 3942 match(RegFlags); | |
| 3943 format %{ "FLAGS_LEGT" %} | |
| 3944 interface(REG_INTER); | |
| 3945 %} | |
| 3946 | |
| 3947 // Float register operands | |
|
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3948 operand regDPR() %{ |
| 0 | 3949 predicate( UseSSE < 2 ); |
|
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3950 constraint(ALLOC_IN_RC(fp_dbl_reg)); |
| 0 | 3951 match(RegD); |
| 3952 match(regDPR1); | |
| 3953 match(regDPR2); | |
| 3954 format %{ %} | |
| 3955 interface(REG_INTER); | |
| 3956 %} | |
| 3957 | |
|
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3958 operand regDPR1(regDPR reg) %{ |
| 0 | 3959 predicate( UseSSE < 2 ); |
|
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3960 constraint(ALLOC_IN_RC(fp_dbl_reg0)); |
| 0 | 3961 match(reg); |
| 3962 format %{ "FPR1" %} | |
| 3963 interface(REG_INTER); | |
| 3964 %} | |
| 3965 | |
|
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3966 operand regDPR2(regDPR reg) %{ |
| 0 | 3967 predicate( UseSSE < 2 ); |
|
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3968 constraint(ALLOC_IN_RC(fp_dbl_reg1)); |
| 0 | 3969 match(reg); |
| 3970 format %{ "FPR2" %} | |
| 3971 interface(REG_INTER); | |
| 3972 %} | |
| 3973 | |
|
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3974 operand regnotDPR1(regDPR reg) %{ |
| 0 | 3975 predicate( UseSSE < 2 ); |
|
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3976 constraint(ALLOC_IN_RC(fp_dbl_notreg0)); |
| 0 | 3977 match(reg); |
| 3978 format %{ %} | |
| 3979 interface(REG_INTER); | |
| 3980 %} | |
| 3981 | |
| 3982 // Float register operands | |
|
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3983 operand regFPR() %{ |
| 0 | 3984 predicate( UseSSE < 2 ); |
|
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3985 constraint(ALLOC_IN_RC(fp_flt_reg)); |
| 0 | 3986 match(RegF); |
| 3987 match(regFPR1); | |
| 3988 format %{ %} | |
| 3989 interface(REG_INTER); | |
| 3990 %} | |
| 3991 | |
| 3992 // Float register operands | |
|
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3993 operand regFPR1(regFPR reg) %{ |
| 0 | 3994 predicate( UseSSE < 2 ); |
|
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3995 constraint(ALLOC_IN_RC(fp_flt_reg0)); |
| 0 | 3996 match(reg); |
| 3997 format %{ "FPR1" %} | |
| 3998 interface(REG_INTER); | |
| 3999 %} | |
| 4000 | |
|
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4001 // XMM Float register operands |
|
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4002 operand regF() %{ |
| 0 | 4003 predicate( UseSSE>=1 ); |
|
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4004 constraint(ALLOC_IN_RC(float_reg)); |
| 0 | 4005 match(RegF); |
| 4006 format %{ %} | |
| 4007 interface(REG_INTER); | |
| 4008 %} | |
| 4009 | |
|
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4010 // XMM Double register operands |
|
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|
4011 operand regD() %{ |
|
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4012 predicate( UseSSE>=2 ); |
|
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4013 constraint(ALLOC_IN_RC(double_reg)); |
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4014 match(RegD); |
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4015 format %{ %} |
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4016 interface(REG_INTER); |
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4017 %} |
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|
4018 |
| 0 | 4019 |
| 4020 //----------Memory Operands---------------------------------------------------- | |
| 4021 // Direct Memory Operand | |
| 4022 operand direct(immP addr) %{ | |
| 4023 match(addr); | |
| 4024 | |
| 4025 format %{ "[$addr]" %} | |
| 4026 interface(MEMORY_INTER) %{ | |
| 4027 base(0xFFFFFFFF); | |
| 4028 index(0x4); | |
| 4029 scale(0x0); | |
| 4030 disp($addr); | |
| 4031 %} | |
| 4032 %} | |
| 4033 | |
| 4034 // Indirect Memory Operand | |
| 4035 operand indirect(eRegP reg) %{ | |
|
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4036 constraint(ALLOC_IN_RC(int_reg)); |
| 0 | 4037 match(reg); |
| 4038 | |
| 4039 format %{ "[$reg]" %} | |
| 4040 interface(MEMORY_INTER) %{ | |
| 4041 base($reg); | |
| 4042 index(0x4); | |
| 4043 scale(0x0); | |
| 4044 disp(0x0); | |
| 4045 %} | |
| 4046 %} | |
| 4047 | |
| 4048 // Indirect Memory Plus Short Offset Operand | |
| 4049 operand indOffset8(eRegP reg, immI8 off) %{ | |
| 4050 match(AddP reg off); | |
| 4051 | |
| 4052 format %{ "[$reg + $off]" %} | |
| 4053 interface(MEMORY_INTER) %{ | |
| 4054 base($reg); | |
| 4055 index(0x4); | |
| 4056 scale(0x0); | |
| 4057 disp($off); | |
| 4058 %} | |
| 4059 %} | |
| 4060 | |
| 4061 // Indirect Memory Plus Long Offset Operand | |
| 4062 operand indOffset32(eRegP reg, immI off) %{ | |
| 4063 match(AddP reg off); | |
| 4064 | |
| 4065 format %{ "[$reg + $off]" %} | |
| 4066 interface(MEMORY_INTER) %{ | |
| 4067 base($reg); | |
| 4068 index(0x4); | |
| 4069 scale(0x0); | |
| 4070 disp($off); | |
| 4071 %} | |
| 4072 %} | |
| 4073 | |
| 4074 // Indirect Memory Plus Long Offset Operand | |
|
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4075 operand indOffset32X(rRegI reg, immP off) %{ |
| 0 | 4076 match(AddP off reg); |
| 4077 | |
| 4078 format %{ "[$reg + $off]" %} | |
| 4079 interface(MEMORY_INTER) %{ | |
| 4080 base($reg); | |
| 4081 index(0x4); | |
| 4082 scale(0x0); | |
| 4083 disp($off); | |
| 4084 %} | |
| 4085 %} | |
| 4086 | |
| 4087 // Indirect Memory Plus Index Register Plus Offset Operand | |
|
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4088 operand indIndexOffset(eRegP reg, rRegI ireg, immI off) %{ |
| 0 | 4089 match(AddP (AddP reg ireg) off); |
| 4090 | |
| 4091 op_cost(10); | |
| 4092 format %{"[$reg + $off + $ireg]" %} | |
| 4093 interface(MEMORY_INTER) %{ | |
| 4094 base($reg); | |
| 4095 index($ireg); | |
| 4096 scale(0x0); | |
| 4097 disp($off); | |
| 4098 %} | |
| 4099 %} | |
| 4100 | |
| 4101 // Indirect Memory Plus Index Register Plus Offset Operand | |
|
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4102 operand indIndex(eRegP reg, rRegI ireg) %{ |
| 0 | 4103 match(AddP reg ireg); |
| 4104 | |
| 4105 op_cost(10); | |
| 4106 format %{"[$reg + $ireg]" %} | |
| 4107 interface(MEMORY_INTER) %{ | |
| 4108 base($reg); | |
| 4109 index($ireg); | |
| 4110 scale(0x0); | |
| 4111 disp(0x0); | |
| 4112 %} | |
| 4113 %} | |
| 4114 | |
| 4115 // // ------------------------------------------------------------------------- | |
| 4116 // // 486 architecture doesn't support "scale * index + offset" with out a base | |
| 4117 // // ------------------------------------------------------------------------- | |
| 4118 // // Scaled Memory Operands | |
| 4119 // // Indirect Memory Times Scale Plus Offset Operand | |
|
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4120 // operand indScaleOffset(immP off, rRegI ireg, immI2 scale) %{ |
| 0 | 4121 // match(AddP off (LShiftI ireg scale)); |
| 4122 // | |
| 4123 // op_cost(10); | |
| 4124 // format %{"[$off + $ireg << $scale]" %} | |
| 4125 // interface(MEMORY_INTER) %{ | |
| 4126 // base(0x4); | |
| 4127 // index($ireg); | |
| 4128 // scale($scale); | |
| 4129 // disp($off); | |
| 4130 // %} | |
| 4131 // %} | |
| 4132 | |
| 4133 // Indirect Memory Times Scale Plus Index Register | |
|
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4134 operand indIndexScale(eRegP reg, rRegI ireg, immI2 scale) %{ |
| 0 | 4135 match(AddP reg (LShiftI ireg scale)); |
| 4136 | |
| 4137 op_cost(10); | |
| 4138 format %{"[$reg + $ireg << $scale]" %} | |
| 4139 interface(MEMORY_INTER) %{ | |
| 4140 base($reg); | |
| 4141 index($ireg); | |
| 4142 scale($scale); | |
| 4143 disp(0x0); | |
| 4144 %} | |
| 4145 %} | |
| 4146 | |
| 4147 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand | |
|
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4148 operand indIndexScaleOffset(eRegP reg, immI off, rRegI ireg, immI2 scale) %{ |
| 0 | 4149 match(AddP (AddP reg (LShiftI ireg scale)) off); |
| 4150 | |
| 4151 op_cost(10); | |
| 4152 format %{"[$reg + $off + $ireg << $scale]" %} | |
| 4153 interface(MEMORY_INTER) %{ | |
| 4154 base($reg); | |
| 4155 index($ireg); | |
| 4156 scale($scale); | |
| 4157 disp($off); | |
| 4158 %} | |
| 4159 %} | |
| 4160 | |
| 4161 //----------Load Long Memory Operands------------------------------------------ | |
| 4162 // The load-long idiom will use it's address expression again after loading | |
| 4163 // the first word of the long. If the load-long destination overlaps with | |
| 4164 // registers used in the addressing expression, the 2nd half will be loaded | |
| 4165 // from a clobbered address. Fix this by requiring that load-long use | |
| 4166 // address registers that do not overlap with the load-long target. | |
| 4167 | |
| 4168 // load-long support | |
| 4169 operand load_long_RegP() %{ | |
| 4170 constraint(ALLOC_IN_RC(esi_reg)); | |
| 4171 match(RegP); | |
| 4172 match(eSIRegP); | |
| 4173 op_cost(100); | |
| 4174 format %{ %} | |
| 4175 interface(REG_INTER); | |
| 4176 %} | |
| 4177 | |
| 4178 // Indirect Memory Operand Long | |
| 4179 operand load_long_indirect(load_long_RegP reg) %{ | |
| 4180 constraint(ALLOC_IN_RC(esi_reg)); | |
| 4181 match(reg); | |
| 4182 | |
| 4183 format %{ "[$reg]" %} | |
| 4184 interface(MEMORY_INTER) %{ | |
| 4185 base($reg); | |
| 4186 index(0x4); | |
| 4187 scale(0x0); | |
| 4188 disp(0x0); | |
| 4189 %} | |
| 4190 %} | |
| 4191 | |
| 4192 // Indirect Memory Plus Long Offset Operand | |
| 4193 operand load_long_indOffset32(load_long_RegP reg, immI off) %{ | |
| 4194 match(AddP reg off); | |
| 4195 | |
| 4196 format %{ "[$reg + $off]" %} | |
| 4197 interface(MEMORY_INTER) %{ | |
| 4198 base($reg); | |
| 4199 index(0x4); | |
| 4200 scale(0x0); | |
| 4201 disp($off); | |
| 4202 %} | |
| 4203 %} | |
| 4204 | |
| 4205 opclass load_long_memory(load_long_indirect, load_long_indOffset32); | |
| 4206 | |
| 4207 | |
| 4208 //----------Special Memory Operands-------------------------------------------- | |
| 4209 // Stack Slot Operand - This operand is used for loading and storing temporary | |
| 4210 // values on the stack where a match requires a value to | |
| 4211 // flow through memory. | |
| 4212 operand stackSlotP(sRegP reg) %{ | |
| 4213 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4214 // No match rule because this operand is only generated in matching | |
| 4215 format %{ "[$reg]" %} | |
| 4216 interface(MEMORY_INTER) %{ | |
| 4217 base(0x4); // ESP | |
| 4218 index(0x4); // No Index | |
| 4219 scale(0x0); // No Scale | |
| 4220 disp($reg); // Stack Offset | |
| 4221 %} | |
| 4222 %} | |
| 4223 | |
| 4224 operand stackSlotI(sRegI reg) %{ | |
| 4225 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4226 // No match rule because this operand is only generated in matching | |
| 4227 format %{ "[$reg]" %} | |
| 4228 interface(MEMORY_INTER) %{ | |
| 4229 base(0x4); // ESP | |
| 4230 index(0x4); // No Index | |
| 4231 scale(0x0); // No Scale | |
| 4232 disp($reg); // Stack Offset | |
| 4233 %} | |
| 4234 %} | |
| 4235 | |
| 4236 operand stackSlotF(sRegF reg) %{ | |
| 4237 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4238 // No match rule because this operand is only generated in matching | |
| 4239 format %{ "[$reg]" %} | |
| 4240 interface(MEMORY_INTER) %{ | |
| 4241 base(0x4); // ESP | |
| 4242 index(0x4); // No Index | |
| 4243 scale(0x0); // No Scale | |
| 4244 disp($reg); // Stack Offset | |
| 4245 %} | |
| 4246 %} | |
| 4247 | |
| 4248 operand stackSlotD(sRegD reg) %{ | |
| 4249 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4250 // No match rule because this operand is only generated in matching | |
| 4251 format %{ "[$reg]" %} | |
| 4252 interface(MEMORY_INTER) %{ | |
| 4253 base(0x4); // ESP | |
| 4254 index(0x4); // No Index | |
| 4255 scale(0x0); // No Scale | |
| 4256 disp($reg); // Stack Offset | |
| 4257 %} | |
| 4258 %} | |
| 4259 | |
| 4260 operand stackSlotL(sRegL reg) %{ | |
| 4261 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4262 // No match rule because this operand is only generated in matching | |
| 4263 format %{ "[$reg]" %} | |
| 4264 interface(MEMORY_INTER) %{ | |
| 4265 base(0x4); // ESP | |
| 4266 index(0x4); // No Index | |
| 4267 scale(0x0); // No Scale | |
| 4268 disp($reg); // Stack Offset | |
| 4269 %} | |
| 4270 %} | |
| 4271 | |
| 4272 //----------Memory Operands - Win95 Implicit Null Variants---------------- | |
| 4273 // Indirect Memory Operand | |
| 4274 operand indirect_win95_safe(eRegP_no_EBP reg) | |
| 4275 %{ | |
|
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4276 constraint(ALLOC_IN_RC(int_reg)); |
| 0 | 4277 match(reg); |
| 4278 | |
| 4279 op_cost(100); | |
| 4280 format %{ "[$reg]" %} | |
| 4281 interface(MEMORY_INTER) %{ | |
| 4282 base($reg); | |
| 4283 index(0x4); | |
| 4284 scale(0x0); | |
| 4285 disp(0x0); | |
| 4286 %} | |
| 4287 %} | |
| 4288 | |
| 4289 // Indirect Memory Plus Short Offset Operand | |
| 4290 operand indOffset8_win95_safe(eRegP_no_EBP reg, immI8 off) | |
| 4291 %{ | |
| 4292 match(AddP reg off); | |
| 4293 | |
| 4294 op_cost(100); | |
| 4295 format %{ "[$reg + $off]" %} | |
| 4296 interface(MEMORY_INTER) %{ | |
| 4297 base($reg); | |
| 4298 index(0x4); | |
| 4299 scale(0x0); | |
| 4300 disp($off); | |
| 4301 %} | |
| 4302 %} | |
| 4303 | |
| 4304 // Indirect Memory Plus Long Offset Operand | |
| 4305 operand indOffset32_win95_safe(eRegP_no_EBP reg, immI off) | |
| 4306 %{ | |
| 4307 match(AddP reg off); | |
| 4308 | |
| 4309 op_cost(100); | |
| 4310 format %{ "[$reg + $off]" %} | |
| 4311 interface(MEMORY_INTER) %{ | |
| 4312 base($reg); | |
| 4313 index(0x4); | |
| 4314 scale(0x0); | |
| 4315 disp($off); | |
| 4316 %} | |
| 4317 %} | |
| 4318 | |
| 4319 // Indirect Memory Plus Index Register Plus Offset Operand | |
|
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4320 operand indIndexOffset_win95_safe(eRegP_no_EBP reg, rRegI ireg, immI off) |
| 0 | 4321 %{ |
| 4322 match(AddP (AddP reg ireg) off); | |
| 4323 | |
| 4324 op_cost(100); | |
| 4325 format %{"[$reg + $off + $ireg]" %} | |
| 4326 interface(MEMORY_INTER) %{ | |
| 4327 base($reg); | |
| 4328 index($ireg); | |
| 4329 scale(0x0); | |
| 4330 disp($off); | |
| 4331 %} | |
| 4332 %} | |
| 4333 | |
| 4334 // Indirect Memory Times Scale Plus Index Register | |
|
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4335 operand indIndexScale_win95_safe(eRegP_no_EBP reg, rRegI ireg, immI2 scale) |
| 0 | 4336 %{ |
| 4337 match(AddP reg (LShiftI ireg scale)); | |
| 4338 | |
| 4339 op_cost(100); | |
| 4340 format %{"[$reg + $ireg << $scale]" %} | |
| 4341 interface(MEMORY_INTER) %{ | |
| 4342 base($reg); | |
| 4343 index($ireg); | |
| 4344 scale($scale); | |
| 4345 disp(0x0); | |
| 4346 %} | |
| 4347 %} | |
| 4348 | |
| 4349 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand | |
|
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4350 operand indIndexScaleOffset_win95_safe(eRegP_no_EBP reg, immI off, rRegI ireg, immI2 scale) |
| 0 | 4351 %{ |
| 4352 match(AddP (AddP reg (LShiftI ireg scale)) off); | |
| 4353 | |
| 4354 op_cost(100); | |
| 4355 format %{"[$reg + $off + $ireg << $scale]" %} | |
| 4356 interface(MEMORY_INTER) %{ | |
| 4357 base($reg); | |
| 4358 index($ireg); | |
| 4359 scale($scale); | |
| 4360 disp($off); | |
| 4361 %} | |
| 4362 %} | |
| 4363 | |
| 4364 //----------Conditional Branch Operands---------------------------------------- | |
| 4365 // Comparison Op - This is the operation of the comparison, and is limited to | |
| 4366 // the following set of codes: | |
| 4367 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=) | |
| 4368 // | |
| 4369 // Other attributes of the comparison, such as unsignedness, are specified | |
| 4370 // by the comparison instruction that sets a condition code flags register. | |
| 4371 // That result is represented by a flags operand whose subtype is appropriate | |
| 4372 // to the unsignedness (etc.) of the comparison. | |
| 4373 // | |
| 4374 // Later, the instruction which matches both the Comparison Op (a Bool) and | |
| 4375 // the flags (produced by the Cmp) specifies the coding of the comparison op | |
| 4376 // by matching a specific subtype of Bool operand below, such as cmpOpU. | |
| 4377 | |
| 4378 // Comparision Code | |
| 4379 operand cmpOp() %{ | |
| 4380 match(Bool); | |
| 4381 | |
| 4382 format %{ "" %} | |
| 4383 interface(COND_INTER) %{ | |
|
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4384 equal(0x4, "e"); |
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4385 not_equal(0x5, "ne"); |
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4386 less(0xC, "l"); |
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4387 greater_equal(0xD, "ge"); |
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4388 less_equal(0xE, "le"); |
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4389 greater(0xF, "g"); |
| 12323 | 4390 overflow(0x0, "o"); |
| 4391 no_overflow(0x1, "no"); | |
| 0 | 4392 %} |
| 4393 %} | |
| 4394 | |
| 4395 // Comparison Code, unsigned compare. Used by FP also, with | |
| 4396 // C2 (unordered) turned into GT or LT already. The other bits | |
| 4397 // C0 and C3 are turned into Carry & Zero flags. | |
| 4398 operand cmpOpU() %{ | |
| 4399 match(Bool); | |
| 4400 | |
| 4401 format %{ "" %} | |
| 4402 interface(COND_INTER) %{ | |
|
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4403 equal(0x4, "e"); |
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4404 not_equal(0x5, "ne"); |
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4405 less(0x2, "b"); |
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|
4406 greater_equal(0x3, "nb"); |
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|
4407 less_equal(0x6, "be"); |
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|
4408 greater(0x7, "nbe"); |
| 12323 | 4409 overflow(0x0, "o"); |
| 4410 no_overflow(0x1, "no"); | |
|
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4411 %} |
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4412 %} |
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|
4413 |
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4414 // Floating comparisons that don't require any fixup for the unordered case |
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4415 operand cmpOpUCF() %{ |
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4416 match(Bool); |
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|
4417 predicate(n->as_Bool()->_test._test == BoolTest::lt || |
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4418 n->as_Bool()->_test._test == BoolTest::ge || |
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4419 n->as_Bool()->_test._test == BoolTest::le || |
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4420 n->as_Bool()->_test._test == BoolTest::gt); |
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|
4421 format %{ "" %} |
|
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4422 interface(COND_INTER) %{ |
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|
4423 equal(0x4, "e"); |
|
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|
4424 not_equal(0x5, "ne"); |
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|
4425 less(0x2, "b"); |
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|
4426 greater_equal(0x3, "nb"); |
|
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|
4427 less_equal(0x6, "be"); |
|
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|
4428 greater(0x7, "nbe"); |
| 12323 | 4429 overflow(0x0, "o"); |
| 4430 no_overflow(0x1, "no"); | |
|
415
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|
4431 %} |
|
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|
4432 %} |
|
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|
4433 |
|
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|
4434 |
|
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|
4435 // Floating comparisons that can be fixed up with extra conditional jumps |
|
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|
4436 operand cmpOpUCF2() %{ |
|
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|
4437 match(Bool); |
|
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|
4438 predicate(n->as_Bool()->_test._test == BoolTest::ne || |
|
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|
4439 n->as_Bool()->_test._test == BoolTest::eq); |
|
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|
4440 format %{ "" %} |
|
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|
4441 interface(COND_INTER) %{ |
|
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|
4442 equal(0x4, "e"); |
|
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|
4443 not_equal(0x5, "ne"); |
|
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|
4444 less(0x2, "b"); |
|
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|
4445 greater_equal(0x3, "nb"); |
|
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|
4446 less_equal(0x6, "be"); |
|
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|
4447 greater(0x7, "nbe"); |
| 12323 | 4448 overflow(0x0, "o"); |
| 4449 no_overflow(0x1, "no"); | |
| 0 | 4450 %} |
| 4451 %} | |
| 4452 | |
| 4453 // Comparison Code for FP conditional move | |
| 4454 operand cmpOp_fcmov() %{ | |
| 4455 match(Bool); | |
| 4456 | |
| 12323 | 4457 predicate(n->as_Bool()->_test._test != BoolTest::overflow && |
| 4458 n->as_Bool()->_test._test != BoolTest::no_overflow); | |
| 0 | 4459 format %{ "" %} |
| 4460 interface(COND_INTER) %{ | |
| 4461 equal (0x0C8); | |
| 4462 not_equal (0x1C8); | |
| 4463 less (0x0C0); | |
| 4464 greater_equal(0x1C0); | |
| 4465 less_equal (0x0D0); | |
| 4466 greater (0x1D0); | |
| 12323 | 4467 overflow(0x0, "o"); // not really supported by the instruction |
| 4468 no_overflow(0x1, "no"); // not really supported by the instruction | |
| 0 | 4469 %} |
| 4470 %} | |
| 4471 | |
| 4472 // Comparision Code used in long compares | |
| 4473 operand cmpOp_commute() %{ | |
| 4474 match(Bool); | |
| 4475 | |
| 4476 format %{ "" %} | |
| 4477 interface(COND_INTER) %{ | |
|
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|
4478 equal(0x4, "e"); |
|
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changeset
|
4479 not_equal(0x5, "ne"); |
|
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|
4480 less(0xF, "g"); |
|
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|
4481 greater_equal(0xE, "le"); |
|
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|
4482 less_equal(0xD, "ge"); |
|
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|
4483 greater(0xC, "l"); |
| 12323 | 4484 overflow(0x0, "o"); |
| 4485 no_overflow(0x1, "no"); | |
| 0 | 4486 %} |
| 4487 %} | |
| 4488 | |
| 4489 //----------OPERAND CLASSES---------------------------------------------------- | |
| 4490 // Operand Classes are groups of operands that are used as to simplify | |
| 605 | 4491 // instruction definitions by not requiring the AD writer to specify separate |
| 0 | 4492 // instructions for every form of operand when the instruction accepts |
| 4493 // multiple operand types with the same basic encoding and format. The classic | |
| 4494 // case of this is memory operands. | |
| 4495 | |
| 4496 opclass memory(direct, indirect, indOffset8, indOffset32, indOffset32X, indIndexOffset, | |
| 4497 indIndex, indIndexScale, indIndexScaleOffset); | |
| 4498 | |
| 4499 // Long memory operations are encoded in 2 instructions and a +4 offset. | |
| 4500 // This means some kind of offset is always required and you cannot use | |
| 4501 // an oop as the offset (done when working on static globals). | |
| 4502 opclass long_memory(direct, indirect, indOffset8, indOffset32, indIndexOffset, | |
| 4503 indIndex, indIndexScale, indIndexScaleOffset); | |
| 4504 | |
| 4505 | |
| 4506 //----------PIPELINE----------------------------------------------------------- | |
| 4507 // Rules which define the behavior of the target architectures pipeline. | |
| 4508 pipeline %{ | |
| 4509 | |
| 4510 //----------ATTRIBUTES--------------------------------------------------------- | |
| 4511 attributes %{ | |
| 4512 variable_size_instructions; // Fixed size instructions | |
| 4513 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle | |
| 4514 instruction_unit_size = 1; // An instruction is 1 bytes long | |
| 4515 instruction_fetch_unit_size = 16; // The processor fetches one line | |
| 4516 instruction_fetch_units = 1; // of 16 bytes | |
| 4517 | |
| 4518 // List of nop instructions | |
| 4519 nops( MachNop ); | |
| 4520 %} | |
| 4521 | |
| 4522 //----------RESOURCES---------------------------------------------------------- | |
| 4523 // Resources are the functional units available to the machine | |
| 4524 | |
| 4525 // Generic P2/P3 pipeline | |
| 4526 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of | |
| 4527 // 3 instructions decoded per cycle. | |
| 4528 // 2 load/store ops per cycle, 1 branch, 1 FPU, | |
| 4529 // 2 ALU op, only ALU0 handles mul/div instructions. | |
| 4530 resources( D0, D1, D2, DECODE = D0 | D1 | D2, | |
| 4531 MS0, MS1, MEM = MS0 | MS1, | |
| 4532 BR, FPU, | |
| 4533 ALU0, ALU1, ALU = ALU0 | ALU1 ); | |
| 4534 | |
| 4535 //----------PIPELINE DESCRIPTION----------------------------------------------- | |
| 4536 // Pipeline Description specifies the stages in the machine's pipeline | |
| 4537 | |
| 4538 // Generic P2/P3 pipeline | |
| 4539 pipe_desc(S0, S1, S2, S3, S4, S5); | |
| 4540 | |
| 4541 //----------PIPELINE CLASSES--------------------------------------------------- | |
| 4542 // Pipeline Classes describe the stages in which input and output are | |
| 4543 // referenced by the hardware pipeline. | |
| 4544 | |
| 4545 // Naming convention: ialu or fpu | |
| 4546 // Then: _reg | |
| 4547 // Then: _reg if there is a 2nd register | |
| 4548 // Then: _long if it's a pair of instructions implementing a long | |
| 4549 // Then: _fat if it requires the big decoder | |
| 4550 // Or: _mem if it requires the big decoder and a memory unit. | |
| 4551 | |
| 4552 // Integer ALU reg operation | |
|
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4553 pipe_class ialu_reg(rRegI dst) %{ |
| 0 | 4554 single_instruction; |
| 4555 dst : S4(write); | |
| 4556 dst : S3(read); | |
| 4557 DECODE : S0; // any decoder | |
| 4558 ALU : S3; // any alu | |
| 4559 %} | |
| 4560 | |
| 4561 // Long ALU reg operation | |
| 4562 pipe_class ialu_reg_long(eRegL dst) %{ | |
| 4563 instruction_count(2); | |
| 4564 dst : S4(write); | |
| 4565 dst : S3(read); | |
| 4566 DECODE : S0(2); // any 2 decoders | |
| 4567 ALU : S3(2); // both alus | |
| 4568 %} | |
| 4569 | |
| 4570 // Integer ALU reg operation using big decoder | |
|
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4571 pipe_class ialu_reg_fat(rRegI dst) %{ |
| 0 | 4572 single_instruction; |
| 4573 dst : S4(write); | |
| 4574 dst : S3(read); | |
| 4575 D0 : S0; // big decoder only | |
| 4576 ALU : S3; // any alu | |
| 4577 %} | |
| 4578 | |
| 4579 // Long ALU reg operation using big decoder | |
| 4580 pipe_class ialu_reg_long_fat(eRegL dst) %{ | |
| 4581 instruction_count(2); | |
| 4582 dst : S4(write); | |
| 4583 dst : S3(read); | |
| 4584 D0 : S0(2); // big decoder only; twice | |
| 4585 ALU : S3(2); // any 2 alus | |
| 4586 %} | |
| 4587 | |
| 4588 // Integer ALU reg-reg operation | |
|
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4589 pipe_class ialu_reg_reg(rRegI dst, rRegI src) %{ |
| 0 | 4590 single_instruction; |
| 4591 dst : S4(write); | |
| 4592 src : S3(read); | |
| 4593 DECODE : S0; // any decoder | |
| 4594 ALU : S3; // any alu | |
| 4595 %} | |
| 4596 | |
| 4597 // Long ALU reg-reg operation | |
| 4598 pipe_class ialu_reg_reg_long(eRegL dst, eRegL src) %{ | |
| 4599 instruction_count(2); | |
| 4600 dst : S4(write); | |
| 4601 src : S3(read); | |
| 4602 DECODE : S0(2); // any 2 decoders | |
| 4603 ALU : S3(2); // both alus | |
| 4604 %} | |
| 4605 | |
| 4606 // Integer ALU reg-reg operation | |
|
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|
4607 pipe_class ialu_reg_reg_fat(rRegI dst, memory src) %{ |
| 0 | 4608 single_instruction; |
| 4609 dst : S4(write); | |
| 4610 src : S3(read); | |
| 4611 D0 : S0; // big decoder only | |
| 4612 ALU : S3; // any alu | |
| 4613 %} | |
| 4614 | |
| 4615 // Long ALU reg-reg operation | |
| 4616 pipe_class ialu_reg_reg_long_fat(eRegL dst, eRegL src) %{ | |
| 4617 instruction_count(2); | |
| 4618 dst : S4(write); | |
| 4619 src : S3(read); | |
| 4620 D0 : S0(2); // big decoder only; twice | |
| 4621 ALU : S3(2); // both alus | |
| 4622 %} | |
| 4623 | |
| 4624 // Integer ALU reg-mem operation | |
|
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|
4625 pipe_class ialu_reg_mem(rRegI dst, memory mem) %{ |
| 0 | 4626 single_instruction; |
| 4627 dst : S5(write); | |
| 4628 mem : S3(read); | |
| 4629 D0 : S0; // big decoder only | |
| 4630 ALU : S4; // any alu | |
| 4631 MEM : S3; // any mem | |
| 4632 %} | |
| 4633 | |
| 4634 // Long ALU reg-mem operation | |
| 4635 pipe_class ialu_reg_long_mem(eRegL dst, load_long_memory mem) %{ | |
| 4636 instruction_count(2); | |
| 4637 dst : S5(write); | |
| 4638 mem : S3(read); | |
| 4639 D0 : S0(2); // big decoder only; twice | |
| 4640 ALU : S4(2); // any 2 alus | |
| 4641 MEM : S3(2); // both mems | |
| 4642 %} | |
| 4643 | |
| 4644 // Integer mem operation (prefetch) | |
| 4645 pipe_class ialu_mem(memory mem) | |
| 4646 %{ | |
| 4647 single_instruction; | |
| 4648 mem : S3(read); | |
| 4649 D0 : S0; // big decoder only | |
| 4650 MEM : S3; // any mem | |
| 4651 %} | |
| 4652 | |
| 4653 // Integer Store to Memory | |
|
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|
4654 pipe_class ialu_mem_reg(memory mem, rRegI src) %{ |
| 0 | 4655 single_instruction; |
| 4656 mem : S3(read); | |
| 4657 src : S5(read); | |
| 4658 D0 : S0; // big decoder only | |
| 4659 ALU : S4; // any alu | |
| 4660 MEM : S3; | |
| 4661 %} | |
| 4662 | |
| 4663 // Long Store to Memory | |
| 4664 pipe_class ialu_mem_long_reg(memory mem, eRegL src) %{ | |
| 4665 instruction_count(2); | |
| 4666 mem : S3(read); | |
| 4667 src : S5(read); | |
| 4668 D0 : S0(2); // big decoder only; twice | |
| 4669 ALU : S4(2); // any 2 alus | |
| 4670 MEM : S3(2); // Both mems | |
| 4671 %} | |
| 4672 | |
| 4673 // Integer Store to Memory | |
| 4674 pipe_class ialu_mem_imm(memory mem) %{ | |
| 4675 single_instruction; | |
| 4676 mem : S3(read); | |
| 4677 D0 : S0; // big decoder only | |
| 4678 ALU : S4; // any alu | |
| 4679 MEM : S3; | |
| 4680 %} | |
| 4681 | |
| 4682 // Integer ALU0 reg-reg operation | |
|
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|
4683 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src) %{ |
| 0 | 4684 single_instruction; |
| 4685 dst : S4(write); | |
| 4686 src : S3(read); | |
| 4687 D0 : S0; // Big decoder only | |
| 4688 ALU0 : S3; // only alu0 | |
| 4689 %} | |
| 4690 | |
| 4691 // Integer ALU0 reg-mem operation | |
|
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|
4692 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem) %{ |
| 0 | 4693 single_instruction; |
| 4694 dst : S5(write); | |
| 4695 mem : S3(read); | |
| 4696 D0 : S0; // big decoder only | |
| 4697 ALU0 : S4; // ALU0 only | |
| 4698 MEM : S3; // any mem | |
| 4699 %} | |
| 4700 | |
| 4701 // Integer ALU reg-reg operation | |
|
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|
4702 pipe_class ialu_cr_reg_reg(eFlagsReg cr, rRegI src1, rRegI src2) %{ |
| 0 | 4703 single_instruction; |
| 4704 cr : S4(write); | |
| 4705 src1 : S3(read); | |
| 4706 src2 : S3(read); | |
| 4707 DECODE : S0; // any decoder | |
| 4708 ALU : S3; // any alu | |
| 4709 %} | |
| 4710 | |
| 4711 // Integer ALU reg-imm operation | |
|
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|
4712 pipe_class ialu_cr_reg_imm(eFlagsReg cr, rRegI src1) %{ |
| 0 | 4713 single_instruction; |
| 4714 cr : S4(write); | |
| 4715 src1 : S3(read); | |
| 4716 DECODE : S0; // any decoder | |
| 4717 ALU : S3; // any alu | |
| 4718 %} | |
| 4719 | |
| 4720 // Integer ALU reg-mem operation | |
|
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|
4721 pipe_class ialu_cr_reg_mem(eFlagsReg cr, rRegI src1, memory src2) %{ |
| 0 | 4722 single_instruction; |
| 4723 cr : S4(write); | |
| 4724 src1 : S3(read); | |
| 4725 src2 : S3(read); | |
| 4726 D0 : S0; // big decoder only | |
| 4727 ALU : S4; // any alu | |
| 4728 MEM : S3; | |
| 4729 %} | |
| 4730 | |
| 4731 // Conditional move reg-reg | |
|
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|
4732 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y ) %{ |
| 0 | 4733 instruction_count(4); |
| 4734 y : S4(read); | |
| 4735 q : S3(read); | |
| 4736 p : S3(read); | |
| 4737 DECODE : S0(4); // any decoder | |
| 4738 %} | |
| 4739 | |
| 4740 // Conditional move reg-reg | |
|
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|
4741 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, eFlagsReg cr ) %{ |
| 0 | 4742 single_instruction; |
| 4743 dst : S4(write); | |
| 4744 src : S3(read); | |
| 4745 cr : S3(read); | |
| 4746 DECODE : S0; // any decoder | |
| 4747 %} | |
| 4748 | |
| 4749 // Conditional move reg-mem | |
|
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|
4750 pipe_class pipe_cmov_mem( eFlagsReg cr, rRegI dst, memory src) %{ |
| 0 | 4751 single_instruction; |
| 4752 dst : S4(write); | |
| 4753 src : S3(read); | |
| 4754 cr : S3(read); | |
| 4755 DECODE : S0; // any decoder | |
| 4756 MEM : S3; | |
| 4757 %} | |
| 4758 | |
| 4759 // Conditional move reg-reg long | |
| 4760 pipe_class pipe_cmov_reg_long( eFlagsReg cr, eRegL dst, eRegL src) %{ | |
| 4761 single_instruction; | |
| 4762 dst : S4(write); | |
| 4763 src : S3(read); | |
| 4764 cr : S3(read); | |
| 4765 DECODE : S0(2); // any 2 decoders | |
| 4766 %} | |
| 4767 | |
| 4768 // Conditional move double reg-reg | |
|
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|
4769 pipe_class pipe_cmovDPR_reg( eFlagsReg cr, regDPR1 dst, regDPR src) %{ |
| 0 | 4770 single_instruction; |
| 4771 dst : S4(write); | |
| 4772 src : S3(read); | |
| 4773 cr : S3(read); | |
| 4774 DECODE : S0; // any decoder | |
| 4775 %} | |
| 4776 | |
| 4777 // Float reg-reg operation | |
|
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|
4778 pipe_class fpu_reg(regDPR dst) %{ |
| 0 | 4779 instruction_count(2); |
| 4780 dst : S3(read); | |
| 4781 DECODE : S0(2); // any 2 decoders | |
| 4782 FPU : S3; | |
| 4783 %} | |
| 4784 | |
| 4785 // Float reg-reg operation | |
|
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|
4786 pipe_class fpu_reg_reg(regDPR dst, regDPR src) %{ |
| 0 | 4787 instruction_count(2); |
| 4788 dst : S4(write); | |
| 4789 src : S3(read); | |
| 4790 DECODE : S0(2); // any 2 decoders | |
| 4791 FPU : S3; | |
| 4792 %} | |
| 4793 | |
| 4794 // Float reg-reg operation | |
|
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|
4795 pipe_class fpu_reg_reg_reg(regDPR dst, regDPR src1, regDPR src2) %{ |
| 0 | 4796 instruction_count(3); |
| 4797 dst : S4(write); | |
| 4798 src1 : S3(read); | |
| 4799 src2 : S3(read); | |
| 4800 DECODE : S0(3); // any 3 decoders | |
| 4801 FPU : S3(2); | |
| 4802 %} | |
| 4803 | |
| 4804 // Float reg-reg operation | |
|
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|
4805 pipe_class fpu_reg_reg_reg_reg(regDPR dst, regDPR src1, regDPR src2, regDPR src3) %{ |
| 0 | 4806 instruction_count(4); |
| 4807 dst : S4(write); | |
| 4808 src1 : S3(read); | |
| 4809 src2 : S3(read); | |
| 4810 src3 : S3(read); | |
| 4811 DECODE : S0(4); // any 3 decoders | |
| 4812 FPU : S3(2); | |
| 4813 %} | |
| 4814 | |
| 4815 // Float reg-reg operation | |
|
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|
4816 pipe_class fpu_reg_mem_reg_reg(regDPR dst, memory src1, regDPR src2, regDPR src3) %{ |
| 0 | 4817 instruction_count(4); |
| 4818 dst : S4(write); | |
| 4819 src1 : S3(read); | |
| 4820 src2 : S3(read); | |
| 4821 src3 : S3(read); | |
| 4822 DECODE : S1(3); // any 3 decoders | |
| 4823 D0 : S0; // Big decoder only | |
| 4824 FPU : S3(2); | |
| 4825 MEM : S3; | |
| 4826 %} | |
| 4827 | |
| 4828 // Float reg-mem operation | |
|
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|
4829 pipe_class fpu_reg_mem(regDPR dst, memory mem) %{ |
| 0 | 4830 instruction_count(2); |
| 4831 dst : S5(write); | |
| 4832 mem : S3(read); | |
| 4833 D0 : S0; // big decoder only | |
| 4834 DECODE : S1; // any decoder for FPU POP | |
| 4835 FPU : S4; | |
| 4836 MEM : S3; // any mem | |
| 4837 %} | |
| 4838 | |
| 4839 // Float reg-mem operation | |
|
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|
4840 pipe_class fpu_reg_reg_mem(regDPR dst, regDPR src1, memory mem) %{ |
| 0 | 4841 instruction_count(3); |
| 4842 dst : S5(write); | |
| 4843 src1 : S3(read); | |
| 4844 mem : S3(read); | |
| 4845 D0 : S0; // big decoder only | |
| 4846 DECODE : S1(2); // any decoder for FPU POP | |
| 4847 FPU : S4; | |
| 4848 MEM : S3; // any mem | |
| 4849 %} | |
| 4850 | |
| 4851 // Float mem-reg operation | |
|
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|
4852 pipe_class fpu_mem_reg(memory mem, regDPR src) %{ |
| 0 | 4853 instruction_count(2); |
| 4854 src : S5(read); | |
| 4855 mem : S3(read); | |
| 4856 DECODE : S0; // any decoder for FPU PUSH | |
| 4857 D0 : S1; // big decoder only | |
| 4858 FPU : S4; | |
| 4859 MEM : S3; // any mem | |
| 4860 %} | |
| 4861 | |
|
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|
4862 pipe_class fpu_mem_reg_reg(memory mem, regDPR src1, regDPR src2) %{ |
| 0 | 4863 instruction_count(3); |
| 4864 src1 : S3(read); | |
| 4865 src2 : S3(read); | |
| 4866 mem : S3(read); | |
| 4867 DECODE : S0(2); // any decoder for FPU PUSH | |
| 4868 D0 : S1; // big decoder only | |
| 4869 FPU : S4; | |
| 4870 MEM : S3; // any mem | |
| 4871 %} | |
| 4872 | |
|
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|
4873 pipe_class fpu_mem_reg_mem(memory mem, regDPR src1, memory src2) %{ |
| 0 | 4874 instruction_count(3); |
| 4875 src1 : S3(read); | |
| 4876 src2 : S3(read); | |
| 4877 mem : S4(read); | |
| 4878 DECODE : S0; // any decoder for FPU PUSH | |
| 4879 D0 : S0(2); // big decoder only | |
| 4880 FPU : S4; | |
| 4881 MEM : S3(2); // any mem | |
| 4882 %} | |
| 4883 | |
| 4884 pipe_class fpu_mem_mem(memory dst, memory src1) %{ | |
| 4885 instruction_count(2); | |
| 4886 src1 : S3(read); | |
| 4887 dst : S4(read); | |
| 4888 D0 : S0(2); // big decoder only | |
| 4889 MEM : S3(2); // any mem | |
| 4890 %} | |
| 4891 | |
| 4892 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2) %{ | |
| 4893 instruction_count(3); | |
| 4894 src1 : S3(read); | |
| 4895 src2 : S3(read); | |
| 4896 dst : S4(read); | |
| 4897 D0 : S0(3); // big decoder only | |
| 4898 FPU : S4; | |
| 4899 MEM : S3(3); // any mem | |
| 4900 %} | |
| 4901 | |
|
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|
4902 pipe_class fpu_mem_reg_con(memory mem, regDPR src1) %{ |
| 0 | 4903 instruction_count(3); |
| 4904 src1 : S4(read); | |
| 4905 mem : S4(read); | |
| 4906 DECODE : S0; // any decoder for FPU PUSH | |
| 4907 D0 : S0(2); // big decoder only | |
| 4908 FPU : S4; | |
| 4909 MEM : S3(2); // any mem | |
| 4910 %} | |
| 4911 | |
| 4912 // Float load constant | |
|
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|
4913 pipe_class fpu_reg_con(regDPR dst) %{ |
| 0 | 4914 instruction_count(2); |
| 4915 dst : S5(write); | |
| 4916 D0 : S0; // big decoder only for the load | |
| 4917 DECODE : S1; // any decoder for FPU POP | |
| 4918 FPU : S4; | |
| 4919 MEM : S3; // any mem | |
| 4920 %} | |
| 4921 | |
| 4922 // Float load constant | |
|
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|
4923 pipe_class fpu_reg_reg_con(regDPR dst, regDPR src) %{ |
| 0 | 4924 instruction_count(3); |
| 4925 dst : S5(write); | |
| 4926 src : S3(read); | |
| 4927 D0 : S0; // big decoder only for the load | |
| 4928 DECODE : S1(2); // any decoder for FPU POP | |
| 4929 FPU : S4; | |
| 4930 MEM : S3; // any mem | |
| 4931 %} | |
| 4932 | |
| 4933 // UnConditional branch | |
| 4934 pipe_class pipe_jmp( label labl ) %{ | |
| 4935 single_instruction; | |
| 4936 BR : S3; | |
| 4937 %} | |
| 4938 | |
| 4939 // Conditional branch | |
| 4940 pipe_class pipe_jcc( cmpOp cmp, eFlagsReg cr, label labl ) %{ | |
| 4941 single_instruction; | |
| 4942 cr : S1(read); | |
| 4943 BR : S3; | |
| 4944 %} | |
| 4945 | |
| 4946 // Allocation idiom | |
| 4947 pipe_class pipe_cmpxchg( eRegP dst, eRegP heap_ptr ) %{ | |
| 4948 instruction_count(1); force_serialization; | |
| 4949 fixed_latency(6); | |
| 4950 heap_ptr : S3(read); | |
| 4951 DECODE : S0(3); | |
| 4952 D0 : S2; | |
| 4953 MEM : S3; | |
| 4954 ALU : S3(2); | |
| 4955 dst : S5(write); | |
| 4956 BR : S5; | |
| 4957 %} | |
| 4958 | |
| 4959 // Generic big/slow expanded idiom | |
| 4960 pipe_class pipe_slow( ) %{ | |
| 4961 instruction_count(10); multiple_bundles; force_serialization; | |
| 4962 fixed_latency(100); | |
| 4963 D0 : S0(2); | |
| 4964 MEM : S3(2); | |
| 4965 %} | |
| 4966 | |
| 4967 // The real do-nothing guy | |
| 4968 pipe_class empty( ) %{ | |
| 4969 instruction_count(0); | |
| 4970 %} | |
| 4971 | |
| 4972 // Define the class for the Nop node | |
| 4973 define %{ | |
| 4974 MachNop = empty; | |
| 4975 %} | |
| 4976 | |
| 4977 %} | |
| 4978 | |
| 4979 //----------INSTRUCTIONS------------------------------------------------------- | |
| 4980 // | |
| 4981 // match -- States which machine-independent subtree may be replaced | |
| 4982 // by this instruction. | |
| 4983 // ins_cost -- The estimated cost of this instruction is used by instruction | |
| 4984 // selection to identify a minimum cost tree of machine | |
| 4985 // instructions that matches a tree of machine-independent | |
| 4986 // instructions. | |
| 4987 // format -- A string providing the disassembly for this instruction. | |
| 4988 // The value of an instruction's operand may be inserted | |
| 4989 // by referring to it with a '$' prefix. | |
| 4990 // opcode -- Three instruction opcodes may be provided. These are referred | |
| 4991 // to within an encode class as $primary, $secondary, and $tertiary | |
| 4992 // respectively. The primary opcode is commonly used to | |
| 4993 // indicate the type of machine instruction, while secondary | |
| 4994 // and tertiary are often used for prefix options or addressing | |
| 4995 // modes. | |
| 4996 // ins_encode -- A list of encode classes with parameters. The encode class | |
| 4997 // name must have been defined in an 'enc_class' specification | |
| 4998 // in the encode section of the architecture description. | |
| 4999 | |
| 5000 //----------BSWAP-Instruction-------------------------------------------------- | |
|
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|
5001 instruct bytes_reverse_int(rRegI dst) %{ |
| 0 | 5002 match(Set dst (ReverseBytesI dst)); |
| 5003 | |
| 5004 format %{ "BSWAP $dst" %} | |
| 5005 opcode(0x0F, 0xC8); | |
| 5006 ins_encode( OpcP, OpcSReg(dst) ); | |
| 5007 ins_pipe( ialu_reg ); | |
| 5008 %} | |
| 5009 | |
| 5010 instruct bytes_reverse_long(eRegL dst) %{ | |
| 5011 match(Set dst (ReverseBytesL dst)); | |
| 5012 | |
| 5013 format %{ "BSWAP $dst.lo\n\t" | |
| 5014 "BSWAP $dst.hi\n\t" | |
| 5015 "XCHG $dst.lo $dst.hi" %} | |
| 5016 | |
| 5017 ins_cost(125); | |
| 5018 ins_encode( bswap_long_bytes(dst) ); | |
| 5019 ins_pipe( ialu_reg_reg); | |
| 5020 %} | |
| 5021 | |
|
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|
5022 instruct bytes_reverse_unsigned_short(rRegI dst, eFlagsReg cr) %{ |
|
1396
d7f654633cfe
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1274
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changeset
|
5023 match(Set dst (ReverseBytesUS dst)); |
|
6138
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|
5024 effect(KILL cr); |
|
1396
d7f654633cfe
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1274
diff
changeset
|
5025 |
|
d7f654633cfe
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diff
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|
5026 format %{ "BSWAP $dst\n\t" |
|
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1274
diff
changeset
|
5027 "SHR $dst,16\n\t" %} |
|
d7f654633cfe
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diff
changeset
|
5028 ins_encode %{ |
|
d7f654633cfe
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parents:
1274
diff
changeset
|
5029 __ bswapl($dst$$Register); |
|
d7f654633cfe
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parents:
1274
diff
changeset
|
5030 __ shrl($dst$$Register, 16); |
|
d7f654633cfe
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parents:
1274
diff
changeset
|
5031 %} |
|
d7f654633cfe
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parents:
1274
diff
changeset
|
5032 ins_pipe( ialu_reg ); |
|
d7f654633cfe
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parents:
1274
diff
changeset
|
5033 %} |
|
d7f654633cfe
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1274
diff
changeset
|
5034 |
|
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|
5035 instruct bytes_reverse_short(rRegI dst, eFlagsReg cr) %{ |
|
1396
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1274
diff
changeset
|
5036 match(Set dst (ReverseBytesS dst)); |
|
6138
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|
5037 effect(KILL cr); |
|
1396
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parents:
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diff
changeset
|
5038 |
|
d7f654633cfe
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diff
changeset
|
5039 format %{ "BSWAP $dst\n\t" |
|
d7f654633cfe
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1274
diff
changeset
|
5040 "SAR $dst,16\n\t" %} |
|
d7f654633cfe
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1274
diff
changeset
|
5041 ins_encode %{ |
|
d7f654633cfe
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parents:
1274
diff
changeset
|
5042 __ bswapl($dst$$Register); |
|
d7f654633cfe
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parents:
1274
diff
changeset
|
5043 __ sarl($dst$$Register, 16); |
|
d7f654633cfe
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parents:
1274
diff
changeset
|
5044 %} |
|
d7f654633cfe
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parents:
1274
diff
changeset
|
5045 ins_pipe( ialu_reg ); |
|
d7f654633cfe
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parents:
1274
diff
changeset
|
5046 %} |
|
d7f654633cfe
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1274
diff
changeset
|
5047 |
| 0 | 5048 |
|
775
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changeset
|
5049 //---------- Zeros Count Instructions ------------------------------------------ |
|
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|
5050 |
|
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changeset
|
5051 instruct countLeadingZerosI(rRegI dst, rRegI src, eFlagsReg cr) %{ |
|
775
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681
diff
changeset
|
5052 predicate(UseCountLeadingZerosInstruction); |
|
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diff
changeset
|
5053 match(Set dst (CountLeadingZerosI src)); |
|
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681
diff
changeset
|
5054 effect(KILL cr); |
|
93c14e5562c4
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681
diff
changeset
|
5055 |
|
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681
diff
changeset
|
5056 format %{ "LZCNT $dst, $src\t# count leading zeros (int)" %} |
|
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|
5057 ins_encode %{ |
|
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changeset
|
5058 __ lzcntl($dst$$Register, $src$$Register); |
|
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|
5059 %} |
|
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changeset
|
5060 ins_pipe(ialu_reg); |
|
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|
5061 %} |
|
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|
5062 |
|
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|
5063 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, eFlagsReg cr) %{ |
|
775
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changeset
|
5064 predicate(!UseCountLeadingZerosInstruction); |
|
93c14e5562c4
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681
diff
changeset
|
5065 match(Set dst (CountLeadingZerosI src)); |
|
93c14e5562c4
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681
diff
changeset
|
5066 effect(KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5067 |
|
93c14e5562c4
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681
diff
changeset
|
5068 format %{ "BSR $dst, $src\t# count leading zeros (int)\n\t" |
|
93c14e5562c4
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diff
changeset
|
5069 "JNZ skip\n\t" |
|
93c14e5562c4
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diff
changeset
|
5070 "MOV $dst, -1\n" |
|
93c14e5562c4
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changeset
|
5071 "skip:\n\t" |
|
93c14e5562c4
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changeset
|
5072 "NEG $dst\n\t" |
|
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changeset
|
5073 "ADD $dst, 31" %} |
|
93c14e5562c4
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changeset
|
5074 ins_encode %{ |
|
93c14e5562c4
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diff
changeset
|
5075 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
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diff
changeset
|
5076 Register Rsrc = $src$$Register; |
|
93c14e5562c4
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diff
changeset
|
5077 Label skip; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
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681
diff
changeset
|
5078 __ bsrl(Rdst, Rsrc); |
|
93c14e5562c4
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diff
changeset
|
5079 __ jccb(Assembler::notZero, skip); |
|
93c14e5562c4
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diff
changeset
|
5080 __ movl(Rdst, -1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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681
diff
changeset
|
5081 __ bind(skip); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
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681
diff
changeset
|
5082 __ negl(Rdst); |
|
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6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
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681
diff
changeset
|
5083 __ addl(Rdst, BitsPerInt - 1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5084 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5085 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5086 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5087 |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5088 instruct countLeadingZerosL(rRegI dst, eRegL src, eFlagsReg cr) %{ |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5089 predicate(UseCountLeadingZerosInstruction); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5090 match(Set dst (CountLeadingZerosL src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5091 effect(TEMP dst, KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5092 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5093 format %{ "LZCNT $dst, $src.hi\t# count leading zeros (long)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5094 "JNC done\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5095 "LZCNT $dst, $src.lo\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5096 "ADD $dst, 32\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5097 "done:" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5098 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5099 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5100 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5101 Label done; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5102 __ lzcntl(Rdst, HIGH_FROM_LOW(Rsrc)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5103 __ jccb(Assembler::carryClear, done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5104 __ lzcntl(Rdst, Rsrc); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5105 __ addl(Rdst, BitsPerInt); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5106 __ bind(done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5107 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5108 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5109 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5110 |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5111 instruct countLeadingZerosL_bsr(rRegI dst, eRegL src, eFlagsReg cr) %{ |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5112 predicate(!UseCountLeadingZerosInstruction); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5113 match(Set dst (CountLeadingZerosL src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5114 effect(TEMP dst, KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5115 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5116 format %{ "BSR $dst, $src.hi\t# count leading zeros (long)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5117 "JZ msw_is_zero\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5118 "ADD $dst, 32\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5119 "JMP not_zero\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5120 "msw_is_zero:\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5121 "BSR $dst, $src.lo\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5122 "JNZ not_zero\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5123 "MOV $dst, -1\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5124 "not_zero:\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5125 "NEG $dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5126 "ADD $dst, 63\n" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5127 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5128 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5129 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5130 Label msw_is_zero; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5131 Label not_zero; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5132 __ bsrl(Rdst, HIGH_FROM_LOW(Rsrc)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5133 __ jccb(Assembler::zero, msw_is_zero); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5134 __ addl(Rdst, BitsPerInt); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5135 __ jmpb(not_zero); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5136 __ bind(msw_is_zero); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5137 __ bsrl(Rdst, Rsrc); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5138 __ jccb(Assembler::notZero, not_zero); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5139 __ movl(Rdst, -1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5140 __ bind(not_zero); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5141 __ negl(Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5142 __ addl(Rdst, BitsPerLong - 1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5143 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5144 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5145 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5146 |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5147 instruct countTrailingZerosI(rRegI dst, rRegI src, eFlagsReg cr) %{ |
|
17729
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5148 predicate(UseCountTrailingZerosInstruction); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5149 match(Set dst (CountTrailingZerosI src)); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5150 effect(KILL cr); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5151 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5152 format %{ "TZCNT $dst, $src\t# count trailing zeros (int)" %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5153 ins_encode %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5154 __ tzcntl($dst$$Register, $src$$Register); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5155 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5156 ins_pipe(ialu_reg); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5157 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5158 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5159 instruct countTrailingZerosI_bsf(rRegI dst, rRegI src, eFlagsReg cr) %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5160 predicate(!UseCountTrailingZerosInstruction); |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5161 match(Set dst (CountTrailingZerosI src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5162 effect(KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5163 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5164 format %{ "BSF $dst, $src\t# count trailing zeros (int)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5165 "JNZ done\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5166 "MOV $dst, 32\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5167 "done:" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5168 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5169 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5170 Label done; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5171 __ bsfl(Rdst, $src$$Register); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5172 __ jccb(Assembler::notZero, done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5173 __ movl(Rdst, BitsPerInt); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5174 __ bind(done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5175 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5176 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5177 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5178 |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5179 instruct countTrailingZerosL(rRegI dst, eRegL src, eFlagsReg cr) %{ |
|
17729
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5180 predicate(UseCountTrailingZerosInstruction); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5181 match(Set dst (CountTrailingZerosL src)); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5182 effect(TEMP dst, KILL cr); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5183 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5184 format %{ "TZCNT $dst, $src.lo\t# count trailing zeros (long) \n\t" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5185 "JNC done\n\t" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5186 "TZCNT $dst, $src.hi\n\t" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5187 "ADD $dst, 32\n" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5188 "done:" %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5189 ins_encode %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5190 Register Rdst = $dst$$Register; |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5191 Register Rsrc = $src$$Register; |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5192 Label done; |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5193 __ tzcntl(Rdst, Rsrc); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5194 __ jccb(Assembler::carryClear, done); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5195 __ tzcntl(Rdst, HIGH_FROM_LOW(Rsrc)); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5196 __ addl(Rdst, BitsPerInt); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5197 __ bind(done); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5198 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5199 ins_pipe(ialu_reg); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5200 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5201 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5202 instruct countTrailingZerosL_bsf(rRegI dst, eRegL src, eFlagsReg cr) %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5203 predicate(!UseCountTrailingZerosInstruction); |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5204 match(Set dst (CountTrailingZerosL src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5205 effect(TEMP dst, KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5206 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5207 format %{ "BSF $dst, $src.lo\t# count trailing zeros (long)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5208 "JNZ done\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5209 "BSF $dst, $src.hi\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5210 "JNZ msw_not_zero\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5211 "MOV $dst, 32\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5212 "msw_not_zero:\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5213 "ADD $dst, 32\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5214 "done:" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5215 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5216 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5217 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5218 Label msw_not_zero; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5219 Label done; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5220 __ bsfl(Rdst, Rsrc); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5221 __ jccb(Assembler::notZero, done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5222 __ bsfl(Rdst, HIGH_FROM_LOW(Rsrc)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5223 __ jccb(Assembler::notZero, msw_not_zero); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5224 __ movl(Rdst, BitsPerInt); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5225 __ bind(msw_not_zero); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5226 __ addl(Rdst, BitsPerInt); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5227 __ bind(done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5228 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5229 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5230 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5231 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5232 |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5233 //---------- Population Count Instructions ------------------------------------- |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5234 |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5235 instruct popCountI(rRegI dst, rRegI src, eFlagsReg cr) %{ |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5236 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5237 match(Set dst (PopCountI src)); |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
5238 effect(KILL cr); |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5239 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5240 format %{ "POPCNT $dst, $src" %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5241 ins_encode %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5242 __ popcntl($dst$$Register, $src$$Register); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5243 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5244 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5245 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5246 |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5247 instruct popCountI_mem(rRegI dst, memory mem, eFlagsReg cr) %{ |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5248 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5249 match(Set dst (PopCountI (LoadI mem))); |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
5250 effect(KILL cr); |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5251 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5252 format %{ "POPCNT $dst, $mem" %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5253 ins_encode %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5254 __ popcntl($dst$$Register, $mem$$Address); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5255 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5256 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5257 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5258 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5259 // Note: Long.bitCount(long) returns an int. |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5260 instruct popCountL(rRegI dst, eRegL src, rRegI tmp, eFlagsReg cr) %{ |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5261 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5262 match(Set dst (PopCountL src)); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5263 effect(KILL cr, TEMP tmp, TEMP dst); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5264 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5265 format %{ "POPCNT $dst, $src.lo\n\t" |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5266 "POPCNT $tmp, $src.hi\n\t" |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5267 "ADD $dst, $tmp" %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5268 ins_encode %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5269 __ popcntl($dst$$Register, $src$$Register); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5270 __ popcntl($tmp$$Register, HIGH_FROM_LOW($src$$Register)); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5271 __ addl($dst$$Register, $tmp$$Register); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5272 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5273 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5274 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5275 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5276 // Note: Long.bitCount(long) returns an int. |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5277 instruct popCountL_mem(rRegI dst, memory mem, rRegI tmp, eFlagsReg cr) %{ |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5278 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5279 match(Set dst (PopCountL (LoadL mem))); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5280 effect(KILL cr, TEMP tmp, TEMP dst); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5281 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5282 format %{ "POPCNT $dst, $mem\n\t" |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5283 "POPCNT $tmp, $mem+4\n\t" |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5284 "ADD $dst, $tmp" %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5285 ins_encode %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5286 //__ popcntl($dst$$Register, $mem$$Address$$first); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5287 //__ popcntl($tmp$$Register, $mem$$Address$$second); |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
5288 __ popcntl($dst$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none)); |
|
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
5289 __ popcntl($tmp$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, relocInfo::none)); |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5290 __ addl($dst$$Register, $tmp$$Register); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5291 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5292 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5293 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5294 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5295 |
| 0 | 5296 //----------Load/Store/Move Instructions--------------------------------------- |
| 5297 //----------Load Instructions-------------------------------------------------- | |
| 5298 // Load Byte (8bit signed) | |
| 5299 instruct loadB(xRegI dst, memory mem) %{ | |
| 5300 match(Set dst (LoadB mem)); | |
| 5301 | |
| 5302 ins_cost(125); | |
| 624 | 5303 format %{ "MOVSX8 $dst,$mem\t# byte" %} |
| 5304 | |
| 5305 ins_encode %{ | |
| 5306 __ movsbl($dst$$Register, $mem$$Address); | |
| 5307 %} | |
| 5308 | |
| 5309 ins_pipe(ialu_reg_mem); | |
| 5310 %} | |
| 5311 | |
| 5312 // Load Byte (8bit signed) into Long Register | |
| 824 | 5313 instruct loadB2L(eRegL dst, memory mem, eFlagsReg cr) %{ |
| 624 | 5314 match(Set dst (ConvI2L (LoadB mem))); |
| 824 | 5315 effect(KILL cr); |
| 624 | 5316 |
| 5317 ins_cost(375); | |
| 5318 format %{ "MOVSX8 $dst.lo,$mem\t# byte -> long\n\t" | |
| 5319 "MOV $dst.hi,$dst.lo\n\t" | |
| 5320 "SAR $dst.hi,7" %} | |
| 5321 | |
| 5322 ins_encode %{ | |
| 5323 __ movsbl($dst$$Register, $mem$$Address); | |
| 5324 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register. | |
| 5325 __ sarl(HIGH_FROM_LOW($dst$$Register), 7); // 24+1 MSB are already signed extended. | |
| 5326 %} | |
| 5327 | |
| 5328 ins_pipe(ialu_reg_mem); | |
| 5329 %} | |
| 5330 | |
| 5331 // Load Unsigned Byte (8bit UNsigned) | |
| 5332 instruct loadUB(xRegI dst, memory mem) %{ | |
| 5333 match(Set dst (LoadUB mem)); | |
| 0 | 5334 |
| 5335 ins_cost(125); | |
| 624 | 5336 format %{ "MOVZX8 $dst,$mem\t# ubyte -> int" %} |
| 5337 | |
| 5338 ins_encode %{ | |
| 5339 __ movzbl($dst$$Register, $mem$$Address); | |
| 5340 %} | |
| 5341 | |
| 5342 ins_pipe(ialu_reg_mem); | |
| 5343 %} | |
| 5344 | |
| 5345 // Load Unsigned Byte (8 bit UNsigned) into Long Register | |
| 824 | 5346 instruct loadUB2L(eRegL dst, memory mem, eFlagsReg cr) %{ |
| 624 | 5347 match(Set dst (ConvI2L (LoadUB mem))); |
| 824 | 5348 effect(KILL cr); |
| 624 | 5349 |
| 5350 ins_cost(250); | |
| 5351 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte -> long\n\t" | |
| 5352 "XOR $dst.hi,$dst.hi" %} | |
| 5353 | |
| 5354 ins_encode %{ | |
| 824 | 5355 Register Rdst = $dst$$Register; |
| 5356 __ movzbl(Rdst, $mem$$Address); | |
| 5357 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); | |
| 5358 %} | |
| 5359 | |
| 5360 ins_pipe(ialu_reg_mem); | |
| 5361 %} | |
| 5362 | |
| 5363 // Load Unsigned Byte (8 bit UNsigned) with mask into Long Register | |
| 5364 instruct loadUB2L_immI8(eRegL dst, memory mem, immI8 mask, eFlagsReg cr) %{ | |
| 5365 match(Set dst (ConvI2L (AndI (LoadUB mem) mask))); | |
| 5366 effect(KILL cr); | |
| 5367 | |
| 5368 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte & 8-bit mask -> long\n\t" | |
| 5369 "XOR $dst.hi,$dst.hi\n\t" | |
| 5370 "AND $dst.lo,$mask" %} | |
| 5371 ins_encode %{ | |
| 5372 Register Rdst = $dst$$Register; | |
| 5373 __ movzbl(Rdst, $mem$$Address); | |
| 5374 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); | |
| 5375 __ andl(Rdst, $mask$$constant); | |
| 5376 %} | |
| 624 | 5377 ins_pipe(ialu_reg_mem); |
| 5378 %} | |
| 5379 | |
| 5380 // Load Short (16bit signed) | |
|
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5381 instruct loadS(rRegI dst, memory mem) %{ |
| 624 | 5382 match(Set dst (LoadS mem)); |
| 5383 | |
| 5384 ins_cost(125); | |
| 5385 format %{ "MOVSX $dst,$mem\t# short" %} | |
| 5386 | |
| 5387 ins_encode %{ | |
| 5388 __ movswl($dst$$Register, $mem$$Address); | |
| 5389 %} | |
| 5390 | |
| 5391 ins_pipe(ialu_reg_mem); | |
| 5392 %} | |
| 5393 | |
| 785 | 5394 // Load Short (16 bit signed) to Byte (8 bit signed) |
|
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5395 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{ |
| 785 | 5396 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour)); |
| 5397 | |
| 5398 ins_cost(125); | |
| 5399 format %{ "MOVSX $dst, $mem\t# short -> byte" %} | |
| 5400 ins_encode %{ | |
| 5401 __ movsbl($dst$$Register, $mem$$Address); | |
| 5402 %} | |
| 5403 ins_pipe(ialu_reg_mem); | |
| 5404 %} | |
| 5405 | |
| 624 | 5406 // Load Short (16bit signed) into Long Register |
| 824 | 5407 instruct loadS2L(eRegL dst, memory mem, eFlagsReg cr) %{ |
| 624 | 5408 match(Set dst (ConvI2L (LoadS mem))); |
| 824 | 5409 effect(KILL cr); |
| 624 | 5410 |
| 5411 ins_cost(375); | |
| 5412 format %{ "MOVSX $dst.lo,$mem\t# short -> long\n\t" | |
| 5413 "MOV $dst.hi,$dst.lo\n\t" | |
| 5414 "SAR $dst.hi,15" %} | |
| 5415 | |
| 5416 ins_encode %{ | |
| 5417 __ movswl($dst$$Register, $mem$$Address); | |
| 5418 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register. | |
| 5419 __ sarl(HIGH_FROM_LOW($dst$$Register), 15); // 16+1 MSB are already signed extended. | |
| 5420 %} | |
| 5421 | |
| 5422 ins_pipe(ialu_reg_mem); | |
| 0 | 5423 %} |
| 5424 | |
|
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|
5425 // Load Unsigned Short/Char (16bit unsigned) |
|
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5426 instruct loadUS(rRegI dst, memory mem) %{ |
|
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|
5427 match(Set dst (LoadUS mem)); |
| 0 | 5428 |
| 5429 ins_cost(125); | |
| 624 | 5430 format %{ "MOVZX $dst,$mem\t# ushort/char -> int" %} |
| 5431 | |
| 5432 ins_encode %{ | |
| 5433 __ movzwl($dst$$Register, $mem$$Address); | |
| 5434 %} | |
| 5435 | |
| 5436 ins_pipe(ialu_reg_mem); | |
| 5437 %} | |
| 5438 | |
| 785 | 5439 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed) |
|
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5440 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{ |
| 785 | 5441 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour)); |
| 5442 | |
| 5443 ins_cost(125); | |
| 5444 format %{ "MOVSX $dst, $mem\t# ushort -> byte" %} | |
| 5445 ins_encode %{ | |
| 5446 __ movsbl($dst$$Register, $mem$$Address); | |
| 5447 %} | |
| 5448 ins_pipe(ialu_reg_mem); | |
| 5449 %} | |
| 5450 | |
| 624 | 5451 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register |
| 824 | 5452 instruct loadUS2L(eRegL dst, memory mem, eFlagsReg cr) %{ |
| 624 | 5453 match(Set dst (ConvI2L (LoadUS mem))); |
| 824 | 5454 effect(KILL cr); |
| 624 | 5455 |
| 5456 ins_cost(250); | |
| 5457 format %{ "MOVZX $dst.lo,$mem\t# ushort/char -> long\n\t" | |
| 5458 "XOR $dst.hi,$dst.hi" %} | |
| 5459 | |
| 5460 ins_encode %{ | |
| 5461 __ movzwl($dst$$Register, $mem$$Address); | |
| 5462 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register)); | |
| 5463 %} | |
| 5464 | |
| 5465 ins_pipe(ialu_reg_mem); | |
| 0 | 5466 %} |
| 5467 | |
| 824 | 5468 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register |
| 5469 instruct loadUS2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{ | |
| 5470 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
| 5471 effect(KILL cr); | |
| 5472 | |
| 5473 format %{ "MOVZX8 $dst.lo,$mem\t# ushort/char & 0xFF -> long\n\t" | |
| 5474 "XOR $dst.hi,$dst.hi" %} | |
| 5475 ins_encode %{ | |
| 5476 Register Rdst = $dst$$Register; | |
| 5477 __ movzbl(Rdst, $mem$$Address); | |
| 5478 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); | |
| 5479 %} | |
| 5480 ins_pipe(ialu_reg_mem); | |
| 5481 %} | |
| 5482 | |
| 5483 // Load Unsigned Short/Char (16 bit UNsigned) with a 16-bit mask into Long Register | |
| 5484 instruct loadUS2L_immI16(eRegL dst, memory mem, immI16 mask, eFlagsReg cr) %{ | |
| 5485 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
| 5486 effect(KILL cr); | |
| 5487 | |
| 5488 format %{ "MOVZX $dst.lo, $mem\t# ushort/char & 16-bit mask -> long\n\t" | |
| 5489 "XOR $dst.hi,$dst.hi\n\t" | |
| 5490 "AND $dst.lo,$mask" %} | |
| 5491 ins_encode %{ | |
| 5492 Register Rdst = $dst$$Register; | |
| 5493 __ movzwl(Rdst, $mem$$Address); | |
| 5494 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); | |
| 5495 __ andl(Rdst, $mask$$constant); | |
| 5496 %} | |
| 5497 ins_pipe(ialu_reg_mem); | |
| 5498 %} | |
| 5499 | |
| 0 | 5500 // Load Integer |
|
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5501 instruct loadI(rRegI dst, memory mem) %{ |
| 0 | 5502 match(Set dst (LoadI mem)); |
| 5503 | |
| 5504 ins_cost(125); | |
| 624 | 5505 format %{ "MOV $dst,$mem\t# int" %} |
| 5506 | |
| 5507 ins_encode %{ | |
| 5508 __ movl($dst$$Register, $mem$$Address); | |
| 5509 %} | |
| 5510 | |
| 5511 ins_pipe(ialu_reg_mem); | |
| 5512 %} | |
| 5513 | |
| 785 | 5514 // Load Integer (32 bit signed) to Byte (8 bit signed) |
|
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5515 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{ |
| 785 | 5516 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour)); |
| 5517 | |
| 5518 ins_cost(125); | |
| 5519 format %{ "MOVSX $dst, $mem\t# int -> byte" %} | |
| 5520 ins_encode %{ | |
| 5521 __ movsbl($dst$$Register, $mem$$Address); | |
| 5522 %} | |
| 5523 ins_pipe(ialu_reg_mem); | |
| 5524 %} | |
| 5525 | |
| 5526 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned) | |
|
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5527 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{ |
| 785 | 5528 match(Set dst (AndI (LoadI mem) mask)); |
| 5529 | |
| 5530 ins_cost(125); | |
| 5531 format %{ "MOVZX $dst, $mem\t# int -> ubyte" %} | |
| 5532 ins_encode %{ | |
| 5533 __ movzbl($dst$$Register, $mem$$Address); | |
| 5534 %} | |
| 5535 ins_pipe(ialu_reg_mem); | |
| 5536 %} | |
| 5537 | |
| 5538 // Load Integer (32 bit signed) to Short (16 bit signed) | |
|
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5539 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{ |
| 785 | 5540 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen)); |
| 5541 | |
| 5542 ins_cost(125); | |
| 5543 format %{ "MOVSX $dst, $mem\t# int -> short" %} | |
| 5544 ins_encode %{ | |
| 5545 __ movswl($dst$$Register, $mem$$Address); | |
| 5546 %} | |
| 5547 ins_pipe(ialu_reg_mem); | |
| 5548 %} | |
| 5549 | |
| 5550 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned) | |
|
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5551 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{ |
| 785 | 5552 match(Set dst (AndI (LoadI mem) mask)); |
| 5553 | |
| 5554 ins_cost(125); | |
| 5555 format %{ "MOVZX $dst, $mem\t# int -> ushort/char" %} | |
| 5556 ins_encode %{ | |
| 5557 __ movzwl($dst$$Register, $mem$$Address); | |
| 5558 %} | |
| 5559 ins_pipe(ialu_reg_mem); | |
| 5560 %} | |
| 5561 | |
| 624 | 5562 // Load Integer into Long Register |
| 824 | 5563 instruct loadI2L(eRegL dst, memory mem, eFlagsReg cr) %{ |
| 624 | 5564 match(Set dst (ConvI2L (LoadI mem))); |
| 824 | 5565 effect(KILL cr); |
| 624 | 5566 |
| 5567 ins_cost(375); | |
| 5568 format %{ "MOV $dst.lo,$mem\t# int -> long\n\t" | |
| 5569 "MOV $dst.hi,$dst.lo\n\t" | |
| 5570 "SAR $dst.hi,31" %} | |
| 5571 | |
| 5572 ins_encode %{ | |
| 5573 __ movl($dst$$Register, $mem$$Address); | |
| 5574 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register. | |
| 5575 __ sarl(HIGH_FROM_LOW($dst$$Register), 31); | |
| 5576 %} | |
| 5577 | |
| 5578 ins_pipe(ialu_reg_mem); | |
| 5579 %} | |
| 5580 | |
| 824 | 5581 // Load Integer with mask 0xFF into Long Register |
| 5582 instruct loadI2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{ | |
| 5583 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
| 5584 effect(KILL cr); | |
| 5585 | |
| 5586 format %{ "MOVZX8 $dst.lo,$mem\t# int & 0xFF -> long\n\t" | |
| 5587 "XOR $dst.hi,$dst.hi" %} | |
| 5588 ins_encode %{ | |
| 5589 Register Rdst = $dst$$Register; | |
| 5590 __ movzbl(Rdst, $mem$$Address); | |
| 5591 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); | |
| 5592 %} | |
| 5593 ins_pipe(ialu_reg_mem); | |
| 5594 %} | |
| 5595 | |
| 5596 // Load Integer with mask 0xFFFF into Long Register | |
| 5597 instruct loadI2L_immI_65535(eRegL dst, memory mem, immI_65535 mask, eFlagsReg cr) %{ | |
| 5598 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
| 5599 effect(KILL cr); | |
| 5600 | |
| 5601 format %{ "MOVZX $dst.lo,$mem\t# int & 0xFFFF -> long\n\t" | |
| 5602 "XOR $dst.hi,$dst.hi" %} | |
| 5603 ins_encode %{ | |
| 5604 Register Rdst = $dst$$Register; | |
| 5605 __ movzwl(Rdst, $mem$$Address); | |
| 5606 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); | |
| 5607 %} | |
| 5608 ins_pipe(ialu_reg_mem); | |
| 5609 %} | |
| 5610 | |
|
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5611 // Load Integer with 31-bit mask into Long Register |
|
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5612 instruct loadI2L_immU31(eRegL dst, memory mem, immU31 mask, eFlagsReg cr) %{ |
| 824 | 5613 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); |
| 5614 effect(KILL cr); | |
| 5615 | |
|
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5616 format %{ "MOV $dst.lo,$mem\t# int & 31-bit mask -> long\n\t" |
| 824 | 5617 "XOR $dst.hi,$dst.hi\n\t" |
| 5618 "AND $dst.lo,$mask" %} | |
| 5619 ins_encode %{ | |
| 5620 Register Rdst = $dst$$Register; | |
| 5621 __ movl(Rdst, $mem$$Address); | |
| 5622 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); | |
| 5623 __ andl(Rdst, $mask$$constant); | |
| 5624 %} | |
| 5625 ins_pipe(ialu_reg_mem); | |
| 5626 %} | |
| 5627 | |
| 624 | 5628 // Load Unsigned Integer into Long Register |
| 6849 | 5629 instruct loadUI2L(eRegL dst, memory mem, immL_32bits mask, eFlagsReg cr) %{ |
| 5630 match(Set dst (AndL (ConvI2L (LoadI mem)) mask)); | |
| 824 | 5631 effect(KILL cr); |
| 624 | 5632 |
| 5633 ins_cost(250); | |
| 5634 format %{ "MOV $dst.lo,$mem\t# uint -> long\n\t" | |
| 5635 "XOR $dst.hi,$dst.hi" %} | |
| 5636 | |
| 5637 ins_encode %{ | |
| 5638 __ movl($dst$$Register, $mem$$Address); | |
| 5639 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register)); | |
| 5640 %} | |
| 5641 | |
| 5642 ins_pipe(ialu_reg_mem); | |
| 0 | 5643 %} |
| 5644 | |
| 5645 // Load Long. Cannot clobber address while loading, so restrict address | |
| 5646 // register to ESI | |
| 5647 instruct loadL(eRegL dst, load_long_memory mem) %{ | |
| 5648 predicate(!((LoadLNode*)n)->require_atomic_access()); | |
| 5649 match(Set dst (LoadL mem)); | |
| 5650 | |
| 5651 ins_cost(250); | |
| 624 | 5652 format %{ "MOV $dst.lo,$mem\t# long\n\t" |
| 0 | 5653 "MOV $dst.hi,$mem+4" %} |
| 624 | 5654 |
| 5655 ins_encode %{ | |
|
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5656 Address Amemlo = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none); |
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5657 Address Amemhi = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, relocInfo::none); |
| 624 | 5658 __ movl($dst$$Register, Amemlo); |
| 5659 __ movl(HIGH_FROM_LOW($dst$$Register), Amemhi); | |
| 5660 %} | |
| 5661 | |
| 5662 ins_pipe(ialu_reg_long_mem); | |
| 0 | 5663 %} |
| 5664 | |
| 5665 // Volatile Load Long. Must be atomic, so do 64-bit FILD | |
| 5666 // then store it down to the stack and reload on the int | |
| 5667 // side. | |
| 5668 instruct loadL_volatile(stackSlotL dst, memory mem) %{ | |
| 5669 predicate(UseSSE<=1 && ((LoadLNode*)n)->require_atomic_access()); | |
| 5670 match(Set dst (LoadL mem)); | |
| 5671 | |
| 5672 ins_cost(200); | |
| 5673 format %{ "FILD $mem\t# Atomic volatile long load\n\t" | |
| 5674 "FISTp $dst" %} | |
| 5675 ins_encode(enc_loadL_volatile(mem,dst)); | |
| 5676 ins_pipe( fpu_reg_mem ); | |
| 5677 %} | |
| 5678 | |
|
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5679 instruct loadLX_volatile(stackSlotL dst, memory mem, regD tmp) %{ |
| 0 | 5680 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access()); |
| 5681 match(Set dst (LoadL mem)); | |
| 5682 effect(TEMP tmp); | |
| 5683 ins_cost(180); | |
| 5684 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t" | |
| 5685 "MOVSD $dst,$tmp" %} | |
| 4759 | 5686 ins_encode %{ |
| 5687 __ movdbl($tmp$$XMMRegister, $mem$$Address); | |
| 5688 __ movdbl(Address(rsp, $dst$$disp), $tmp$$XMMRegister); | |
| 5689 %} | |
| 0 | 5690 ins_pipe( pipe_slow ); |
| 5691 %} | |
| 5692 | |
|
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5693 instruct loadLX_reg_volatile(eRegL dst, memory mem, regD tmp) %{ |
| 0 | 5694 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access()); |
| 5695 match(Set dst (LoadL mem)); | |
| 5696 effect(TEMP tmp); | |
| 5697 ins_cost(160); | |
| 5698 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t" | |
| 5699 "MOVD $dst.lo,$tmp\n\t" | |
| 5700 "PSRLQ $tmp,32\n\t" | |
| 5701 "MOVD $dst.hi,$tmp" %} | |
| 4759 | 5702 ins_encode %{ |
| 5703 __ movdbl($tmp$$XMMRegister, $mem$$Address); | |
| 5704 __ movdl($dst$$Register, $tmp$$XMMRegister); | |
| 5705 __ psrlq($tmp$$XMMRegister, 32); | |
| 5706 __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister); | |
| 5707 %} | |
| 0 | 5708 ins_pipe( pipe_slow ); |
| 5709 %} | |
| 5710 | |
| 5711 // Load Range | |
|
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5712 instruct loadRange(rRegI dst, memory mem) %{ |
| 0 | 5713 match(Set dst (LoadRange mem)); |
| 5714 | |
| 5715 ins_cost(125); | |
| 5716 format %{ "MOV $dst,$mem" %} | |
| 5717 opcode(0x8B); | |
| 5718 ins_encode( OpcP, RegMem(dst,mem)); | |
| 5719 ins_pipe( ialu_reg_mem ); | |
| 5720 %} | |
| 5721 | |
| 5722 | |
| 5723 // Load Pointer | |
| 5724 instruct loadP(eRegP dst, memory mem) %{ | |
| 5725 match(Set dst (LoadP mem)); | |
| 5726 | |
| 5727 ins_cost(125); | |
| 5728 format %{ "MOV $dst,$mem" %} | |
| 5729 opcode(0x8B); | |
| 5730 ins_encode( OpcP, RegMem(dst,mem)); | |
| 5731 ins_pipe( ialu_reg_mem ); | |
| 5732 %} | |
| 5733 | |
| 5734 // Load Klass Pointer | |
| 5735 instruct loadKlass(eRegP dst, memory mem) %{ | |
| 5736 match(Set dst (LoadKlass mem)); | |
| 5737 | |
| 5738 ins_cost(125); | |
| 5739 format %{ "MOV $dst,$mem" %} | |
| 5740 opcode(0x8B); | |
| 5741 ins_encode( OpcP, RegMem(dst,mem)); | |
| 5742 ins_pipe( ialu_reg_mem ); | |
| 5743 %} | |
| 5744 | |
| 5745 // Load Double | |
|
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|
5746 instruct loadDPR(regDPR dst, memory mem) %{ |
| 0 | 5747 predicate(UseSSE<=1); |
| 5748 match(Set dst (LoadD mem)); | |
| 5749 | |
| 5750 ins_cost(150); | |
| 5751 format %{ "FLD_D ST,$mem\n\t" | |
| 5752 "FSTP $dst" %} | |
| 5753 opcode(0xDD); /* DD /0 */ | |
| 5754 ins_encode( OpcP, RMopc_Mem(0x00,mem), | |
|
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|
5755 Pop_Reg_DPR(dst) ); |
| 0 | 5756 ins_pipe( fpu_reg_mem ); |
| 5757 %} | |
| 5758 | |
| 5759 // Load Double to XMM | |
|
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5760 instruct loadD(regD dst, memory mem) %{ |
| 0 | 5761 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper); |
| 5762 match(Set dst (LoadD mem)); | |
| 5763 ins_cost(145); | |
| 5764 format %{ "MOVSD $dst,$mem" %} | |
| 4759 | 5765 ins_encode %{ |
| 5766 __ movdbl ($dst$$XMMRegister, $mem$$Address); | |
| 5767 %} | |
| 0 | 5768 ins_pipe( pipe_slow ); |
| 5769 %} | |
| 5770 | |
|
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5771 instruct loadD_partial(regD dst, memory mem) %{ |
| 0 | 5772 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper); |
| 5773 match(Set dst (LoadD mem)); | |
| 5774 ins_cost(145); | |
| 5775 format %{ "MOVLPD $dst,$mem" %} | |
| 4759 | 5776 ins_encode %{ |
| 5777 __ movdbl ($dst$$XMMRegister, $mem$$Address); | |
| 5778 %} | |
| 0 | 5779 ins_pipe( pipe_slow ); |
| 5780 %} | |
| 5781 | |
| 5782 // Load to XMM register (single-precision floating point) | |
| 5783 // MOVSS instruction | |
|
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5784 instruct loadF(regF dst, memory mem) %{ |
| 0 | 5785 predicate(UseSSE>=1); |
| 5786 match(Set dst (LoadF mem)); | |
| 5787 ins_cost(145); | |
| 5788 format %{ "MOVSS $dst,$mem" %} | |
| 4759 | 5789 ins_encode %{ |
| 5790 __ movflt ($dst$$XMMRegister, $mem$$Address); | |
| 5791 %} | |
| 0 | 5792 ins_pipe( pipe_slow ); |
| 5793 %} | |
| 5794 | |
| 5795 // Load Float | |
|
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5796 instruct loadFPR(regFPR dst, memory mem) %{ |
| 0 | 5797 predicate(UseSSE==0); |
| 5798 match(Set dst (LoadF mem)); | |
| 5799 | |
| 5800 ins_cost(150); | |
| 5801 format %{ "FLD_S ST,$mem\n\t" | |
| 5802 "FSTP $dst" %} | |
| 5803 opcode(0xD9); /* D9 /0 */ | |
| 5804 ins_encode( OpcP, RMopc_Mem(0x00,mem), | |
|
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5805 Pop_Reg_FPR(dst) ); |
| 0 | 5806 ins_pipe( fpu_reg_mem ); |
| 5807 %} | |
| 5808 | |
| 5809 // Load Effective Address | |
| 5810 instruct leaP8(eRegP dst, indOffset8 mem) %{ | |
| 5811 match(Set dst mem); | |
| 5812 | |
| 5813 ins_cost(110); | |
| 5814 format %{ "LEA $dst,$mem" %} | |
| 5815 opcode(0x8D); | |
| 5816 ins_encode( OpcP, RegMem(dst,mem)); | |
| 5817 ins_pipe( ialu_reg_reg_fat ); | |
| 5818 %} | |
| 5819 | |
| 5820 instruct leaP32(eRegP dst, indOffset32 mem) %{ | |
| 5821 match(Set dst mem); | |
| 5822 | |
| 5823 ins_cost(110); | |
| 5824 format %{ "LEA $dst,$mem" %} | |
| 5825 opcode(0x8D); | |
| 5826 ins_encode( OpcP, RegMem(dst,mem)); | |
| 5827 ins_pipe( ialu_reg_reg_fat ); | |
| 5828 %} | |
| 5829 | |
| 5830 instruct leaPIdxOff(eRegP dst, indIndexOffset mem) %{ | |
| 5831 match(Set dst mem); | |
| 5832 | |
| 5833 ins_cost(110); | |
| 5834 format %{ "LEA $dst,$mem" %} | |
| 5835 opcode(0x8D); | |
| 5836 ins_encode( OpcP, RegMem(dst,mem)); | |
| 5837 ins_pipe( ialu_reg_reg_fat ); | |
| 5838 %} | |
| 5839 | |
| 5840 instruct leaPIdxScale(eRegP dst, indIndexScale mem) %{ | |
| 5841 match(Set dst mem); | |
| 5842 | |
| 5843 ins_cost(110); | |
| 5844 format %{ "LEA $dst,$mem" %} | |
| 5845 opcode(0x8D); | |
| 5846 ins_encode( OpcP, RegMem(dst,mem)); | |
| 5847 ins_pipe( ialu_reg_reg_fat ); | |
| 5848 %} | |
| 5849 | |
| 5850 instruct leaPIdxScaleOff(eRegP dst, indIndexScaleOffset mem) %{ | |
| 5851 match(Set dst mem); | |
| 5852 | |
| 5853 ins_cost(110); | |
| 5854 format %{ "LEA $dst,$mem" %} | |
| 5855 opcode(0x8D); | |
| 5856 ins_encode( OpcP, RegMem(dst,mem)); | |
| 5857 ins_pipe( ialu_reg_reg_fat ); | |
| 5858 %} | |
| 5859 | |
| 5860 // Load Constant | |
|
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5861 instruct loadConI(rRegI dst, immI src) %{ |
| 0 | 5862 match(Set dst src); |
| 5863 | |
| 5864 format %{ "MOV $dst,$src" %} | |
| 5865 ins_encode( LdImmI(dst, src) ); | |
| 5866 ins_pipe( ialu_reg_fat ); | |
| 5867 %} | |
| 5868 | |
| 5869 // Load Constant zero | |
|
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5870 instruct loadConI0(rRegI dst, immI0 src, eFlagsReg cr) %{ |
| 0 | 5871 match(Set dst src); |
| 5872 effect(KILL cr); | |
| 5873 | |
| 5874 ins_cost(50); | |
| 5875 format %{ "XOR $dst,$dst" %} | |
| 5876 opcode(0x33); /* + rd */ | |
| 5877 ins_encode( OpcP, RegReg( dst, dst ) ); | |
| 5878 ins_pipe( ialu_reg ); | |
| 5879 %} | |
| 5880 | |
| 5881 instruct loadConP(eRegP dst, immP src) %{ | |
| 5882 match(Set dst src); | |
| 5883 | |
| 5884 format %{ "MOV $dst,$src" %} | |
| 5885 opcode(0xB8); /* + rd */ | |
| 5886 ins_encode( LdImmP(dst, src) ); | |
| 5887 ins_pipe( ialu_reg_fat ); | |
| 5888 %} | |
| 5889 | |
| 5890 instruct loadConL(eRegL dst, immL src, eFlagsReg cr) %{ | |
| 5891 match(Set dst src); | |
| 5892 effect(KILL cr); | |
| 5893 ins_cost(200); | |
| 5894 format %{ "MOV $dst.lo,$src.lo\n\t" | |
| 5895 "MOV $dst.hi,$src.hi" %} | |
| 5896 opcode(0xB8); | |
| 5897 ins_encode( LdImmL_Lo(dst, src), LdImmL_Hi(dst, src) ); | |
| 5898 ins_pipe( ialu_reg_long_fat ); | |
| 5899 %} | |
| 5900 | |
| 5901 instruct loadConL0(eRegL dst, immL0 src, eFlagsReg cr) %{ | |
| 5902 match(Set dst src); | |
| 5903 effect(KILL cr); | |
| 5904 ins_cost(150); | |
| 5905 format %{ "XOR $dst.lo,$dst.lo\n\t" | |
| 5906 "XOR $dst.hi,$dst.hi" %} | |
| 5907 opcode(0x33,0x33); | |
| 5908 ins_encode( RegReg_Lo(dst,dst), RegReg_Hi(dst, dst) ); | |
| 5909 ins_pipe( ialu_reg_long ); | |
| 5910 %} | |
| 5911 | |
|
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5912 // The instruction usage is guarded by predicate in operand immFPR(). |
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5913 instruct loadConFPR(regFPR dst, immFPR con) %{ |
| 2008 | 5914 match(Set dst con); |
| 5915 ins_cost(125); | |
| 5916 format %{ "FLD_S ST,[$constantaddress]\t# load from constant table: float=$con\n\t" | |
| 5917 "FSTP $dst" %} | |
| 5918 ins_encode %{ | |
| 5919 __ fld_s($constantaddress($con)); | |
| 5920 __ fstp_d($dst$$reg); | |
| 5921 %} | |
| 5922 ins_pipe(fpu_reg_con); | |
| 5923 %} | |
| 5924 | |
|
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5925 // The instruction usage is guarded by predicate in operand immFPR0(). |
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5926 instruct loadConFPR0(regFPR dst, immFPR0 con) %{ |
| 2008 | 5927 match(Set dst con); |
| 0 | 5928 ins_cost(125); |
| 2008 | 5929 format %{ "FLDZ ST\n\t" |
| 0 | 5930 "FSTP $dst" %} |
| 2008 | 5931 ins_encode %{ |
| 5932 __ fldz(); | |
| 5933 __ fstp_d($dst$$reg); | |
| 5934 %} | |
| 5935 ins_pipe(fpu_reg_con); | |
| 5936 %} | |
| 5937 | |
|
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5938 // The instruction usage is guarded by predicate in operand immFPR1(). |
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5939 instruct loadConFPR1(regFPR dst, immFPR1 con) %{ |
| 2008 | 5940 match(Set dst con); |
| 5941 ins_cost(125); | |
| 5942 format %{ "FLD1 ST\n\t" | |
| 5943 "FSTP $dst" %} | |
| 5944 ins_encode %{ | |
| 5945 __ fld1(); | |
| 5946 __ fstp_d($dst$$reg); | |
| 5947 %} | |
| 5948 ins_pipe(fpu_reg_con); | |
| 0 | 5949 %} |
| 5950 | |
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5951 // The instruction usage is guarded by predicate in operand immF(). |
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5952 instruct loadConF(regF dst, immF con) %{ |
| 0 | 5953 match(Set dst con); |
| 5954 ins_cost(125); | |
| 2008 | 5955 format %{ "MOVSS $dst,[$constantaddress]\t# load from constant table: float=$con" %} |
| 5956 ins_encode %{ | |
| 5957 __ movflt($dst$$XMMRegister, $constantaddress($con)); | |
| 5958 %} | |
| 5959 ins_pipe(pipe_slow); | |
| 0 | 5960 %} |
| 5961 | |
|
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5962 // The instruction usage is guarded by predicate in operand immF0(). |
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5963 instruct loadConF0(regF dst, immF0 src) %{ |
| 0 | 5964 match(Set dst src); |
| 5965 ins_cost(100); | |
| 5966 format %{ "XORPS $dst,$dst\t# float 0.0" %} | |
| 2008 | 5967 ins_encode %{ |
| 5968 __ xorps($dst$$XMMRegister, $dst$$XMMRegister); | |
| 5969 %} | |
| 5970 ins_pipe(pipe_slow); | |
| 0 | 5971 %} |
| 5972 | |
|
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5973 // The instruction usage is guarded by predicate in operand immDPR(). |
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5974 instruct loadConDPR(regDPR dst, immDPR con) %{ |
| 2008 | 5975 match(Set dst con); |
| 5976 ins_cost(125); | |
| 5977 | |
| 5978 format %{ "FLD_D ST,[$constantaddress]\t# load from constant table: double=$con\n\t" | |
| 5979 "FSTP $dst" %} | |
| 5980 ins_encode %{ | |
| 5981 __ fld_d($constantaddress($con)); | |
| 5982 __ fstp_d($dst$$reg); | |
| 5983 %} | |
| 5984 ins_pipe(fpu_reg_con); | |
| 5985 %} | |
| 5986 | |
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5987 // The instruction usage is guarded by predicate in operand immDPR0(). |
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5988 instruct loadConDPR0(regDPR dst, immDPR0 con) %{ |
| 2008 | 5989 match(Set dst con); |
| 0 | 5990 ins_cost(125); |
| 5991 | |
| 2008 | 5992 format %{ "FLDZ ST\n\t" |
| 0 | 5993 "FSTP $dst" %} |
| 2008 | 5994 ins_encode %{ |
| 5995 __ fldz(); | |
| 5996 __ fstp_d($dst$$reg); | |
| 5997 %} | |
| 5998 ins_pipe(fpu_reg_con); | |
| 5999 %} | |
| 6000 | |
|
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6001 // The instruction usage is guarded by predicate in operand immDPR1(). |
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6002 instruct loadConDPR1(regDPR dst, immDPR1 con) %{ |
| 2008 | 6003 match(Set dst con); |
| 6004 ins_cost(125); | |
| 6005 | |
| 6006 format %{ "FLD1 ST\n\t" | |
| 6007 "FSTP $dst" %} | |
| 6008 ins_encode %{ | |
| 6009 __ fld1(); | |
| 6010 __ fstp_d($dst$$reg); | |
| 6011 %} | |
| 6012 ins_pipe(fpu_reg_con); | |
| 0 | 6013 %} |
| 6014 | |
|
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6015 // The instruction usage is guarded by predicate in operand immD(). |
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6016 instruct loadConD(regD dst, immD con) %{ |
| 0 | 6017 match(Set dst con); |
| 6018 ins_cost(125); | |
| 2008 | 6019 format %{ "MOVSD $dst,[$constantaddress]\t# load from constant table: double=$con" %} |
| 6020 ins_encode %{ | |
| 6021 __ movdbl($dst$$XMMRegister, $constantaddress($con)); | |
| 6022 %} | |
| 6023 ins_pipe(pipe_slow); | |
| 0 | 6024 %} |
| 6025 | |
|
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6026 // The instruction usage is guarded by predicate in operand immD0(). |
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6027 instruct loadConD0(regD dst, immD0 src) %{ |
| 0 | 6028 match(Set dst src); |
| 6029 ins_cost(100); | |
| 6030 format %{ "XORPD $dst,$dst\t# double 0.0" %} | |
| 4759 | 6031 ins_encode %{ |
| 6032 __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister); | |
| 6033 %} | |
| 0 | 6034 ins_pipe( pipe_slow ); |
| 6035 %} | |
| 6036 | |
| 6037 // Load Stack Slot | |
|
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6038 instruct loadSSI(rRegI dst, stackSlotI src) %{ |
| 0 | 6039 match(Set dst src); |
| 6040 ins_cost(125); | |
| 6041 | |
| 6042 format %{ "MOV $dst,$src" %} | |
| 6043 opcode(0x8B); | |
| 6044 ins_encode( OpcP, RegMem(dst,src)); | |
| 6045 ins_pipe( ialu_reg_mem ); | |
| 6046 %} | |
| 6047 | |
| 6048 instruct loadSSL(eRegL dst, stackSlotL src) %{ | |
| 6049 match(Set dst src); | |
| 6050 | |
| 6051 ins_cost(200); | |
| 6052 format %{ "MOV $dst,$src.lo\n\t" | |
| 6053 "MOV $dst+4,$src.hi" %} | |
| 6054 opcode(0x8B, 0x8B); | |
| 6055 ins_encode( OpcP, RegMem( dst, src ), OpcS, RegMem_Hi( dst, src ) ); | |
| 6056 ins_pipe( ialu_mem_long_reg ); | |
| 6057 %} | |
| 6058 | |
| 6059 // Load Stack Slot | |
| 6060 instruct loadSSP(eRegP dst, stackSlotP src) %{ | |
| 6061 match(Set dst src); | |
| 6062 ins_cost(125); | |
| 6063 | |
| 6064 format %{ "MOV $dst,$src" %} | |
| 6065 opcode(0x8B); | |
| 6066 ins_encode( OpcP, RegMem(dst,src)); | |
| 6067 ins_pipe( ialu_reg_mem ); | |
| 6068 %} | |
| 6069 | |
| 6070 // Load Stack Slot | |
|
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6071 instruct loadSSF(regFPR dst, stackSlotF src) %{ |
| 0 | 6072 match(Set dst src); |
| 6073 ins_cost(125); | |
| 6074 | |
| 6075 format %{ "FLD_S $src\n\t" | |
| 6076 "FSTP $dst" %} | |
| 6077 opcode(0xD9); /* D9 /0, FLD m32real */ | |
| 6078 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src), | |
|
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6079 Pop_Reg_FPR(dst) ); |
| 0 | 6080 ins_pipe( fpu_reg_mem ); |
| 6081 %} | |
| 6082 | |
| 6083 // Load Stack Slot | |
|
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6084 instruct loadSSD(regDPR dst, stackSlotD src) %{ |
| 0 | 6085 match(Set dst src); |
| 6086 ins_cost(125); | |
| 6087 | |
| 6088 format %{ "FLD_D $src\n\t" | |
| 6089 "FSTP $dst" %} | |
| 6090 opcode(0xDD); /* DD /0, FLD m64real */ | |
| 6091 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src), | |
|
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6092 Pop_Reg_DPR(dst) ); |
| 0 | 6093 ins_pipe( fpu_reg_mem ); |
| 6094 %} | |
| 6095 | |
| 6096 // Prefetch instructions. | |
| 6097 // Must be safe to execute with invalid address (cannot fault). | |
| 6098 | |
| 6099 instruct prefetchr0( memory mem ) %{ | |
| 2479 | 6100 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch()); |
| 0 | 6101 match(PrefetchRead mem); |
| 6102 ins_cost(0); | |
| 6103 size(0); | |
| 6104 format %{ "PREFETCHR (non-SSE is empty encoding)" %} | |
| 6105 ins_encode(); | |
| 6106 ins_pipe(empty); | |
| 6107 %} | |
| 6108 | |
| 6109 instruct prefetchr( memory mem ) %{ | |
| 2479 | 6110 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch() || ReadPrefetchInstr==3); |
| 0 | 6111 match(PrefetchRead mem); |
| 6112 ins_cost(100); | |
| 6113 | |
| 6114 format %{ "PREFETCHR $mem\t! Prefetch into level 1 cache for read" %} | |
| 3854 | 6115 ins_encode %{ |
| 6116 __ prefetchr($mem$$Address); | |
| 6117 %} | |
| 0 | 6118 ins_pipe(ialu_mem); |
| 6119 %} | |
| 6120 | |
| 6121 instruct prefetchrNTA( memory mem ) %{ | |
| 6122 predicate(UseSSE>=1 && ReadPrefetchInstr==0); | |
| 6123 match(PrefetchRead mem); | |
| 6124 ins_cost(100); | |
| 6125 | |
| 6126 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for read" %} | |
| 3854 | 6127 ins_encode %{ |
| 6128 __ prefetchnta($mem$$Address); | |
| 6129 %} | |
| 0 | 6130 ins_pipe(ialu_mem); |
| 6131 %} | |
| 6132 | |
| 6133 instruct prefetchrT0( memory mem ) %{ | |
| 6134 predicate(UseSSE>=1 && ReadPrefetchInstr==1); | |
| 6135 match(PrefetchRead mem); | |
| 6136 ins_cost(100); | |
| 6137 | |
| 6138 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for read" %} | |
| 3854 | 6139 ins_encode %{ |
| 6140 __ prefetcht0($mem$$Address); | |
| 6141 %} | |
| 0 | 6142 ins_pipe(ialu_mem); |
| 6143 %} | |
| 6144 | |
| 6145 instruct prefetchrT2( memory mem ) %{ | |
| 6146 predicate(UseSSE>=1 && ReadPrefetchInstr==2); | |
| 6147 match(PrefetchRead mem); | |
| 6148 ins_cost(100); | |
| 6149 | |
| 6150 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for read" %} | |
| 3854 | 6151 ins_encode %{ |
| 6152 __ prefetcht2($mem$$Address); | |
| 6153 %} | |
| 0 | 6154 ins_pipe(ialu_mem); |
| 6155 %} | |
| 6156 | |
| 6157 instruct prefetchw0( memory mem ) %{ | |
| 2479 | 6158 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch()); |
| 0 | 6159 match(PrefetchWrite mem); |
| 6160 ins_cost(0); | |
| 6161 size(0); | |
| 6162 format %{ "Prefetch (non-SSE is empty encoding)" %} | |
| 6163 ins_encode(); | |
| 6164 ins_pipe(empty); | |
| 6165 %} | |
| 6166 | |
| 6167 instruct prefetchw( memory mem ) %{ | |
| 3854 | 6168 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch()); |
| 0 | 6169 match( PrefetchWrite mem ); |
| 6170 ins_cost(100); | |
| 6171 | |
| 6172 format %{ "PREFETCHW $mem\t! Prefetch into L1 cache and mark modified" %} | |
| 3854 | 6173 ins_encode %{ |
| 6174 __ prefetchw($mem$$Address); | |
| 6175 %} | |
| 0 | 6176 ins_pipe(ialu_mem); |
| 6177 %} | |
| 6178 | |
| 6179 instruct prefetchwNTA( memory mem ) %{ | |
| 3854 | 6180 predicate(UseSSE>=1); |
| 0 | 6181 match(PrefetchWrite mem); |
| 6182 ins_cost(100); | |
| 6183 | |
| 6184 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for write" %} | |
| 3854 | 6185 ins_encode %{ |
| 6186 __ prefetchnta($mem$$Address); | |
| 6187 %} | |
| 0 | 6188 ins_pipe(ialu_mem); |
| 6189 %} | |
| 6190 | |
| 3854 | 6191 // Prefetch instructions for allocation. |
| 6192 | |
| 6193 instruct prefetchAlloc0( memory mem ) %{ | |
| 6194 predicate(UseSSE==0 && AllocatePrefetchInstr!=3); | |
| 6195 match(PrefetchAllocation mem); | |
| 6196 ins_cost(0); | |
| 6197 size(0); | |
| 6198 format %{ "Prefetch allocation (non-SSE is empty encoding)" %} | |
| 6199 ins_encode(); | |
| 6200 ins_pipe(empty); | |
| 6201 %} | |
| 6202 | |
| 6203 instruct prefetchAlloc( memory mem ) %{ | |
| 6204 predicate(AllocatePrefetchInstr==3); | |
| 6205 match( PrefetchAllocation mem ); | |
| 0 | 6206 ins_cost(100); |
| 6207 | |
| 3854 | 6208 format %{ "PREFETCHW $mem\t! Prefetch allocation into L1 cache and mark modified" %} |
| 6209 ins_encode %{ | |
| 6210 __ prefetchw($mem$$Address); | |
| 6211 %} | |
| 6212 ins_pipe(ialu_mem); | |
| 6213 %} | |
| 6214 | |
| 6215 instruct prefetchAllocNTA( memory mem ) %{ | |
| 6216 predicate(UseSSE>=1 && AllocatePrefetchInstr==0); | |
| 6217 match(PrefetchAllocation mem); | |
| 6218 ins_cost(100); | |
| 6219 | |
| 6220 format %{ "PREFETCHNTA $mem\t! Prefetch allocation into non-temporal cache for write" %} | |
| 6221 ins_encode %{ | |
| 6222 __ prefetchnta($mem$$Address); | |
| 6223 %} | |
| 0 | 6224 ins_pipe(ialu_mem); |
| 6225 %} | |
| 6226 | |
| 3854 | 6227 instruct prefetchAllocT0( memory mem ) %{ |
| 6228 predicate(UseSSE>=1 && AllocatePrefetchInstr==1); | |
| 6229 match(PrefetchAllocation mem); | |
| 0 | 6230 ins_cost(100); |
| 6231 | |
| 3854 | 6232 format %{ "PREFETCHT0 $mem\t! Prefetch allocation into L1 and L2 caches for write" %} |
| 6233 ins_encode %{ | |
| 6234 __ prefetcht0($mem$$Address); | |
| 6235 %} | |
| 6236 ins_pipe(ialu_mem); | |
| 6237 %} | |
| 6238 | |
| 6239 instruct prefetchAllocT2( memory mem ) %{ | |
| 6240 predicate(UseSSE>=1 && AllocatePrefetchInstr==2); | |
| 6241 match(PrefetchAllocation mem); | |
| 6242 ins_cost(100); | |
| 6243 | |
| 6244 format %{ "PREFETCHT2 $mem\t! Prefetch allocation into L2 cache for write" %} | |
| 6245 ins_encode %{ | |
| 6246 __ prefetcht2($mem$$Address); | |
| 6247 %} | |
| 0 | 6248 ins_pipe(ialu_mem); |
| 6249 %} | |
| 6250 | |
| 6251 //----------Store Instructions------------------------------------------------- | |
| 6252 | |
| 6253 // Store Byte | |
| 6254 instruct storeB(memory mem, xRegI src) %{ | |
| 6255 match(Set mem (StoreB mem src)); | |
| 6256 | |
| 6257 ins_cost(125); | |
| 6258 format %{ "MOV8 $mem,$src" %} | |
| 6259 opcode(0x88); | |
| 6260 ins_encode( OpcP, RegMem( src, mem ) ); | |
| 6261 ins_pipe( ialu_mem_reg ); | |
| 6262 %} | |
| 6263 | |
| 6264 // Store Char/Short | |
|
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6265 instruct storeC(memory mem, rRegI src) %{ |
| 0 | 6266 match(Set mem (StoreC mem src)); |
| 6267 | |
| 6268 ins_cost(125); | |
| 6269 format %{ "MOV16 $mem,$src" %} | |
| 6270 opcode(0x89, 0x66); | |
| 6271 ins_encode( OpcS, OpcP, RegMem( src, mem ) ); | |
| 6272 ins_pipe( ialu_mem_reg ); | |
| 6273 %} | |
| 6274 | |
| 6275 // Store Integer | |
|
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6276 instruct storeI(memory mem, rRegI src) %{ |
| 0 | 6277 match(Set mem (StoreI mem src)); |
| 6278 | |
| 6279 ins_cost(125); | |
| 6280 format %{ "MOV $mem,$src" %} | |
| 6281 opcode(0x89); | |
| 6282 ins_encode( OpcP, RegMem( src, mem ) ); | |
| 6283 ins_pipe( ialu_mem_reg ); | |
| 6284 %} | |
| 6285 | |
| 6286 // Store Long | |
| 6287 instruct storeL(long_memory mem, eRegL src) %{ | |
| 6288 predicate(!((StoreLNode*)n)->require_atomic_access()); | |
| 6289 match(Set mem (StoreL mem src)); | |
| 6290 | |
| 6291 ins_cost(200); | |
| 6292 format %{ "MOV $mem,$src.lo\n\t" | |
| 6293 "MOV $mem+4,$src.hi" %} | |
| 6294 opcode(0x89, 0x89); | |
| 6295 ins_encode( OpcP, RegMem( src, mem ), OpcS, RegMem_Hi( src, mem ) ); | |
| 6296 ins_pipe( ialu_mem_long_reg ); | |
| 6297 %} | |
| 6298 | |
| 824 | 6299 // Store Long to Integer |
| 6300 instruct storeL2I(memory mem, eRegL src) %{ | |
| 6301 match(Set mem (StoreI mem (ConvL2I src))); | |
| 6302 | |
| 6303 format %{ "MOV $mem,$src.lo\t# long -> int" %} | |
| 6304 ins_encode %{ | |
| 6305 __ movl($mem$$Address, $src$$Register); | |
| 6306 %} | |
| 6307 ins_pipe(ialu_mem_reg); | |
| 6308 %} | |
| 6309 | |
| 0 | 6310 // Volatile Store Long. Must be atomic, so move it into |
| 6311 // the FP TOS and then do a 64-bit FIST. Has to probe the | |
| 6312 // target address before the store (for null-ptr checks) | |
| 6313 // so the memory operand is used twice in the encoding. | |
| 6314 instruct storeL_volatile(memory mem, stackSlotL src, eFlagsReg cr ) %{ | |
| 6315 predicate(UseSSE<=1 && ((StoreLNode*)n)->require_atomic_access()); | |
| 6316 match(Set mem (StoreL mem src)); | |
| 6317 effect( KILL cr ); | |
| 6318 ins_cost(400); | |
| 6319 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t" | |
| 6320 "FILD $src\n\t" | |
| 6321 "FISTp $mem\t # 64-bit atomic volatile long store" %} | |
| 6322 opcode(0x3B); | |
| 6323 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeL_volatile(mem,src)); | |
| 6324 ins_pipe( fpu_reg_mem ); | |
| 6325 %} | |
| 6326 | |
|
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6327 instruct storeLX_volatile(memory mem, stackSlotL src, regD tmp, eFlagsReg cr) %{ |
| 0 | 6328 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access()); |
| 6329 match(Set mem (StoreL mem src)); | |
| 6330 effect( TEMP tmp, KILL cr ); | |
| 6331 ins_cost(380); | |
| 6332 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t" | |
| 6333 "MOVSD $tmp,$src\n\t" | |
| 6334 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %} | |
| 4759 | 6335 ins_encode %{ |
| 6336 __ cmpl(rax, $mem$$Address); | |
| 6337 __ movdbl($tmp$$XMMRegister, Address(rsp, $src$$disp)); | |
| 6338 __ movdbl($mem$$Address, $tmp$$XMMRegister); | |
| 6339 %} | |
| 0 | 6340 ins_pipe( pipe_slow ); |
| 6341 %} | |
| 6342 | |
|
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6343 instruct storeLX_reg_volatile(memory mem, eRegL src, regD tmp2, regD tmp, eFlagsReg cr) %{ |
| 0 | 6344 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access()); |
| 6345 match(Set mem (StoreL mem src)); | |
| 6346 effect( TEMP tmp2 , TEMP tmp, KILL cr ); | |
| 6347 ins_cost(360); | |
| 6348 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t" | |
| 6349 "MOVD $tmp,$src.lo\n\t" | |
| 6350 "MOVD $tmp2,$src.hi\n\t" | |
| 6351 "PUNPCKLDQ $tmp,$tmp2\n\t" | |
| 6352 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %} | |
| 4759 | 6353 ins_encode %{ |
| 6354 __ cmpl(rax, $mem$$Address); | |
| 6355 __ movdl($tmp$$XMMRegister, $src$$Register); | |
| 6356 __ movdl($tmp2$$XMMRegister, HIGH_FROM_LOW($src$$Register)); | |
| 6357 __ punpckldq($tmp$$XMMRegister, $tmp2$$XMMRegister); | |
| 6358 __ movdbl($mem$$Address, $tmp$$XMMRegister); | |
| 6359 %} | |
| 0 | 6360 ins_pipe( pipe_slow ); |
| 6361 %} | |
| 6362 | |
| 6363 // Store Pointer; for storing unknown oops and raw pointers | |
| 6364 instruct storeP(memory mem, anyRegP src) %{ | |
| 6365 match(Set mem (StoreP mem src)); | |
| 6366 | |
| 6367 ins_cost(125); | |
| 6368 format %{ "MOV $mem,$src" %} | |
| 6369 opcode(0x89); | |
| 6370 ins_encode( OpcP, RegMem( src, mem ) ); | |
| 6371 ins_pipe( ialu_mem_reg ); | |
| 6372 %} | |
| 6373 | |
| 6374 // Store Integer Immediate | |
| 6375 instruct storeImmI(memory mem, immI src) %{ | |
| 6376 match(Set mem (StoreI mem src)); | |
| 6377 | |
| 6378 ins_cost(150); | |
| 6379 format %{ "MOV $mem,$src" %} | |
| 6380 opcode(0xC7); /* C7 /0 */ | |
| 6381 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src )); | |
| 6382 ins_pipe( ialu_mem_imm ); | |
| 6383 %} | |
| 6384 | |
| 6385 // Store Short/Char Immediate | |
| 6386 instruct storeImmI16(memory mem, immI16 src) %{ | |
| 6387 predicate(UseStoreImmI16); | |
| 6388 match(Set mem (StoreC mem src)); | |
| 6389 | |
| 6390 ins_cost(150); | |
| 6391 format %{ "MOV16 $mem,$src" %} | |
| 6392 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */ | |
| 6393 ins_encode( SizePrefix, OpcP, RMopc_Mem(0x00,mem), Con16( src )); | |
| 6394 ins_pipe( ialu_mem_imm ); | |
| 6395 %} | |
| 6396 | |
| 6397 // Store Pointer Immediate; null pointers or constant oops that do not | |
| 6398 // need card-mark barriers. | |
| 6399 instruct storeImmP(memory mem, immP src) %{ | |
| 6400 match(Set mem (StoreP mem src)); | |
| 6401 | |
| 6402 ins_cost(150); | |
| 6403 format %{ "MOV $mem,$src" %} | |
| 6404 opcode(0xC7); /* C7 /0 */ | |
| 6405 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src )); | |
| 6406 ins_pipe( ialu_mem_imm ); | |
| 6407 %} | |
| 6408 | |
| 6409 // Store Byte Immediate | |
| 6410 instruct storeImmB(memory mem, immI8 src) %{ | |
| 6411 match(Set mem (StoreB mem src)); | |
| 6412 | |
| 6413 ins_cost(150); | |
| 6414 format %{ "MOV8 $mem,$src" %} | |
| 6415 opcode(0xC6); /* C6 /0 */ | |
| 6416 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src )); | |
| 6417 ins_pipe( ialu_mem_imm ); | |
| 6418 %} | |
| 6419 | |
| 6420 // Store CMS card-mark Immediate | |
| 6421 instruct storeImmCM(memory mem, immI8 src) %{ | |
| 6422 match(Set mem (StoreCM mem src)); | |
| 6423 | |
| 6424 ins_cost(150); | |
| 6425 format %{ "MOV8 $mem,$src\t! CMS card-mark imm0" %} | |
| 6426 opcode(0xC6); /* C6 /0 */ | |
| 6427 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src )); | |
| 6428 ins_pipe( ialu_mem_imm ); | |
| 6429 %} | |
| 6430 | |
| 6431 // Store Double | |
|
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6432 instruct storeDPR( memory mem, regDPR1 src) %{ |
| 0 | 6433 predicate(UseSSE<=1); |
| 6434 match(Set mem (StoreD mem src)); | |
| 6435 | |
| 6436 ins_cost(100); | |
| 6437 format %{ "FST_D $mem,$src" %} | |
| 6438 opcode(0xDD); /* DD /2 */ | |
|
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6439 ins_encode( enc_FPR_store(mem,src) ); |
| 0 | 6440 ins_pipe( fpu_mem_reg ); |
| 6441 %} | |
| 6442 | |
| 6443 // Store double does rounding on x86 | |
|
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6444 instruct storeDPR_rounded( memory mem, regDPR1 src) %{ |
| 0 | 6445 predicate(UseSSE<=1); |
| 6446 match(Set mem (StoreD mem (RoundDouble src))); | |
| 6447 | |
| 6448 ins_cost(100); | |
| 6449 format %{ "FST_D $mem,$src\t# round" %} | |
| 6450 opcode(0xDD); /* DD /2 */ | |
|
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6451 ins_encode( enc_FPR_store(mem,src) ); |
| 0 | 6452 ins_pipe( fpu_mem_reg ); |
| 6453 %} | |
| 6454 | |
| 6455 // Store XMM register to memory (double-precision floating points) | |
| 6456 // MOVSD instruction | |
|
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6457 instruct storeD(memory mem, regD src) %{ |
| 0 | 6458 predicate(UseSSE>=2); |
| 6459 match(Set mem (StoreD mem src)); | |
| 6460 ins_cost(95); | |
| 6461 format %{ "MOVSD $mem,$src" %} | |
| 4759 | 6462 ins_encode %{ |
| 6463 __ movdbl($mem$$Address, $src$$XMMRegister); | |
| 6464 %} | |
| 0 | 6465 ins_pipe( pipe_slow ); |
| 6466 %} | |
| 6467 | |
| 6468 // Store XMM register to memory (single-precision floating point) | |
| 6469 // MOVSS instruction | |
|
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6470 instruct storeF(memory mem, regF src) %{ |
| 0 | 6471 predicate(UseSSE>=1); |
| 6472 match(Set mem (StoreF mem src)); | |
| 6473 ins_cost(95); | |
| 6474 format %{ "MOVSS $mem,$src" %} | |
| 4759 | 6475 ins_encode %{ |
| 6476 __ movflt($mem$$Address, $src$$XMMRegister); | |
| 6477 %} | |
| 0 | 6478 ins_pipe( pipe_slow ); |
| 6479 %} | |
| 6480 | |
| 6481 // Store Float | |
|
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6482 instruct storeFPR( memory mem, regFPR1 src) %{ |
| 0 | 6483 predicate(UseSSE==0); |
| 6484 match(Set mem (StoreF mem src)); | |
| 6485 | |
| 6486 ins_cost(100); | |
| 6487 format %{ "FST_S $mem,$src" %} | |
| 6488 opcode(0xD9); /* D9 /2 */ | |
|
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6489 ins_encode( enc_FPR_store(mem,src) ); |
| 0 | 6490 ins_pipe( fpu_mem_reg ); |
| 6491 %} | |
| 6492 | |
| 6493 // Store Float does rounding on x86 | |
|
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6494 instruct storeFPR_rounded( memory mem, regFPR1 src) %{ |
| 0 | 6495 predicate(UseSSE==0); |
| 6496 match(Set mem (StoreF mem (RoundFloat src))); | |
| 6497 | |
| 6498 ins_cost(100); | |
| 6499 format %{ "FST_S $mem,$src\t# round" %} | |
| 6500 opcode(0xD9); /* D9 /2 */ | |
|
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6501 ins_encode( enc_FPR_store(mem,src) ); |
| 0 | 6502 ins_pipe( fpu_mem_reg ); |
| 6503 %} | |
| 6504 | |
| 6505 // Store Float does rounding on x86 | |
|
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6506 instruct storeFPR_Drounded( memory mem, regDPR1 src) %{ |
| 0 | 6507 predicate(UseSSE<=1); |
| 6508 match(Set mem (StoreF mem (ConvD2F src))); | |
| 6509 | |
| 6510 ins_cost(100); | |
| 6511 format %{ "FST_S $mem,$src\t# D-round" %} | |
| 6512 opcode(0xD9); /* D9 /2 */ | |
|
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6513 ins_encode( enc_FPR_store(mem,src) ); |
| 0 | 6514 ins_pipe( fpu_mem_reg ); |
| 6515 %} | |
| 6516 | |
| 6517 // Store immediate Float value (it is faster than store from FPU register) | |
|
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6518 // The instruction usage is guarded by predicate in operand immFPR(). |
|
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6519 instruct storeFPR_imm( memory mem, immFPR src) %{ |
|
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6520 match(Set mem (StoreF mem src)); |
|
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6521 |
|
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6522 ins_cost(50); |
|
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6523 format %{ "MOV $mem,$src\t# store float" %} |
|
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6524 opcode(0xC7); /* C7 /0 */ |
|
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6525 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32FPR_as_bits( src )); |
|
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6526 ins_pipe( ialu_mem_imm ); |
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6527 %} |
|
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6528 |
|
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6529 // Store immediate Float value (it is faster than store from XMM register) |
| 0 | 6530 // The instruction usage is guarded by predicate in operand immF(). |
| 6531 instruct storeF_imm( memory mem, immF src) %{ | |
| 6532 match(Set mem (StoreF mem src)); | |
| 6533 | |
| 6534 ins_cost(50); | |
| 6535 format %{ "MOV $mem,$src\t# store float" %} | |
| 6536 opcode(0xC7); /* C7 /0 */ | |
| 6537 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32F_as_bits( src )); | |
| 6538 ins_pipe( ialu_mem_imm ); | |
| 6539 %} | |
| 6540 | |
| 6541 // Store Integer to stack slot | |
|
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6542 instruct storeSSI(stackSlotI dst, rRegI src) %{ |
| 0 | 6543 match(Set dst src); |
| 6544 | |
| 6545 ins_cost(100); | |
| 6546 format %{ "MOV $dst,$src" %} | |
| 6547 opcode(0x89); | |
| 6548 ins_encode( OpcPRegSS( dst, src ) ); | |
| 6549 ins_pipe( ialu_mem_reg ); | |
| 6550 %} | |
| 6551 | |
| 6552 // Store Integer to stack slot | |
| 6553 instruct storeSSP(stackSlotP dst, eRegP src) %{ | |
| 6554 match(Set dst src); | |
| 6555 | |
| 6556 ins_cost(100); | |
| 6557 format %{ "MOV $dst,$src" %} | |
| 6558 opcode(0x89); | |
| 6559 ins_encode( OpcPRegSS( dst, src ) ); | |
| 6560 ins_pipe( ialu_mem_reg ); | |
| 6561 %} | |
| 6562 | |
| 6563 // Store Long to stack slot | |
| 6564 instruct storeSSL(stackSlotL dst, eRegL src) %{ | |
| 6565 match(Set dst src); | |
| 6566 | |
| 6567 ins_cost(200); | |
| 6568 format %{ "MOV $dst,$src.lo\n\t" | |
| 6569 "MOV $dst+4,$src.hi" %} | |
| 6570 opcode(0x89, 0x89); | |
| 6571 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) ); | |
| 6572 ins_pipe( ialu_mem_long_reg ); | |
| 6573 %} | |
| 6574 | |
| 6575 //----------MemBar Instructions----------------------------------------------- | |
| 6576 // Memory barrier flavors | |
| 6577 | |
| 6578 instruct membar_acquire() %{ | |
| 6579 match(MemBarAcquire); | |
|
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6580 match(LoadFence); |
| 0 | 6581 ins_cost(400); |
| 6582 | |
| 6583 size(0); | |
|
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6584 format %{ "MEMBAR-acquire ! (empty encoding)" %} |
|
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6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6585 ins_encode(); |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6586 ins_pipe(empty); |
| 0 | 6587 %} |
| 6588 | |
| 6589 instruct membar_acquire_lock() %{ | |
|
3849
f1c12354c3f7
7074017: Introduce MemBarAcquireLock/MemBarReleaseLock nodes for monitor enter/exit code paths
roland
parents:
3842
diff
changeset
|
6590 match(MemBarAcquireLock); |
| 0 | 6591 ins_cost(0); |
| 6592 | |
| 6593 size(0); | |
| 6594 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %} | |
| 6595 ins_encode( ); | |
| 6596 ins_pipe(empty); | |
| 6597 %} | |
| 6598 | |
| 6599 instruct membar_release() %{ | |
| 6600 match(MemBarRelease); | |
|
14439
50fdb38839eb
8028515: PPPC64 (part 113.2): opto: Introduce LoadFence/StoreFence.
goetz
parents:
14428
diff
changeset
|
6601 match(StoreFence); |
| 0 | 6602 ins_cost(400); |
| 6603 | |
| 6604 size(0); | |
|
671
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6605 format %{ "MEMBAR-release ! (empty encoding)" %} |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6606 ins_encode( ); |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6607 ins_pipe(empty); |
| 0 | 6608 %} |
| 6609 | |
| 6610 instruct membar_release_lock() %{ | |
|
3849
f1c12354c3f7
7074017: Introduce MemBarAcquireLock/MemBarReleaseLock nodes for monitor enter/exit code paths
roland
parents:
3842
diff
changeset
|
6611 match(MemBarReleaseLock); |
| 0 | 6612 ins_cost(0); |
| 6613 | |
| 6614 size(0); | |
| 6615 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %} | |
| 6616 ins_encode( ); | |
| 6617 ins_pipe(empty); | |
| 6618 %} | |
| 6619 | |
|
671
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6620 instruct membar_volatile(eFlagsReg cr) %{ |
| 0 | 6621 match(MemBarVolatile); |
|
671
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6622 effect(KILL cr); |
| 0 | 6623 ins_cost(400); |
| 6624 | |
|
671
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6625 format %{ |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6626 $$template |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6627 if (os::is_MP()) { |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6628 $$emit$$"LOCK ADDL [ESP + #0], 0\t! membar_volatile" |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6629 } else { |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6630 $$emit$$"MEMBAR-volatile ! (empty encoding)" |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6631 } |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6632 %} |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6633 ins_encode %{ |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6634 __ membar(Assembler::StoreLoad); |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6635 %} |
| 0 | 6636 ins_pipe(pipe_slow); |
| 6637 %} | |
| 6638 | |
| 6639 instruct unnecessary_membar_volatile() %{ | |
| 6640 match(MemBarVolatile); | |
| 6641 predicate(Matcher::post_store_load_barrier(n)); | |
| 6642 ins_cost(0); | |
| 6643 | |
| 6644 size(0); | |
| 6645 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %} | |
| 6646 ins_encode( ); | |
| 6647 ins_pipe(empty); | |
| 6648 %} | |
| 6649 | |
|
4763
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4761
diff
changeset
|
6650 instruct membar_storestore() %{ |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4761
diff
changeset
|
6651 match(MemBarStoreStore); |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4761
diff
changeset
|
6652 ins_cost(0); |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4761
diff
changeset
|
6653 |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4761
diff
changeset
|
6654 size(0); |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4761
diff
changeset
|
6655 format %{ "MEMBAR-storestore (empty encoding)" %} |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4761
diff
changeset
|
6656 ins_encode( ); |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4761
diff
changeset
|
6657 ins_pipe(empty); |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4761
diff
changeset
|
6658 %} |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4761
diff
changeset
|
6659 |
| 0 | 6660 //----------Move Instructions-------------------------------------------------- |
| 6661 instruct castX2P(eAXRegP dst, eAXRegI src) %{ | |
| 6662 match(Set dst (CastX2P src)); | |
| 6663 format %{ "# X2P $dst, $src" %} | |
| 6664 ins_encode( /*empty encoding*/ ); | |
| 6665 ins_cost(0); | |
| 6666 ins_pipe(empty); | |
| 6667 %} | |
| 6668 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
6669 instruct castP2X(rRegI dst, eRegP src ) %{ |
| 0 | 6670 match(Set dst (CastP2X src)); |
| 6671 ins_cost(50); | |
| 6672 format %{ "MOV $dst, $src\t# CastP2X" %} | |
| 6673 ins_encode( enc_Copy( dst, src) ); | |
| 6674 ins_pipe( ialu_reg_reg ); | |
| 6675 %} | |
| 6676 | |
| 6677 //----------Conditional Move--------------------------------------------------- | |
| 6678 // Conditional move | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
6679 instruct jmovI_reg(cmpOp cop, eFlagsReg cr, rRegI dst, rRegI src) %{ |
| 4047 | 6680 predicate(!VM_Version::supports_cmov() ); |
| 6681 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); | |
| 6682 ins_cost(200); | |
| 6683 format %{ "J$cop,us skip\t# signed cmove\n\t" | |
| 6684 "MOV $dst,$src\n" | |
| 6685 "skip:" %} | |
| 6686 ins_encode %{ | |
| 6687 Label Lskip; | |
| 6688 // Invert sense of branch from sense of CMOV | |
| 6689 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip); | |
| 6690 __ movl($dst$$Register, $src$$Register); | |
| 6691 __ bind(Lskip); | |
| 6692 %} | |
| 6693 ins_pipe( pipe_cmov_reg ); | |
| 6694 %} | |
| 6695 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
6696 instruct jmovI_regU(cmpOpU cop, eFlagsRegU cr, rRegI dst, rRegI src) %{ |
| 4047 | 6697 predicate(!VM_Version::supports_cmov() ); |
| 6698 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); | |
| 6699 ins_cost(200); | |
| 6700 format %{ "J$cop,us skip\t# unsigned cmove\n\t" | |
| 6701 "MOV $dst,$src\n" | |
| 6702 "skip:" %} | |
| 6703 ins_encode %{ | |
| 6704 Label Lskip; | |
| 6705 // Invert sense of branch from sense of CMOV | |
| 6706 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip); | |
| 6707 __ movl($dst$$Register, $src$$Register); | |
| 6708 __ bind(Lskip); | |
| 6709 %} | |
| 6710 ins_pipe( pipe_cmov_reg ); | |
| 6711 %} | |
| 6712 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
6713 instruct cmovI_reg(rRegI dst, rRegI src, eFlagsReg cr, cmpOp cop ) %{ |
| 0 | 6714 predicate(VM_Version::supports_cmov() ); |
| 6715 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); | |
| 6716 ins_cost(200); | |
| 6717 format %{ "CMOV$cop $dst,$src" %} | |
| 6718 opcode(0x0F,0x40); | |
| 6719 ins_encode( enc_cmov(cop), RegReg( dst, src ) ); | |
| 6720 ins_pipe( pipe_cmov_reg ); | |
| 6721 %} | |
| 6722 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
6723 instruct cmovI_regU( cmpOpU cop, eFlagsRegU cr, rRegI dst, rRegI src ) %{ |
| 0 | 6724 predicate(VM_Version::supports_cmov() ); |
| 6725 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); | |
| 6726 ins_cost(200); | |
| 6727 format %{ "CMOV$cop $dst,$src" %} | |
| 6728 opcode(0x0F,0x40); | |
| 6729 ins_encode( enc_cmov(cop), RegReg( dst, src ) ); | |
| 6730 ins_pipe( pipe_cmov_reg ); | |
| 6731 %} | |
| 6732 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
6733 instruct cmovI_regUCF( cmpOpUCF cop, eFlagsRegUCF cr, rRegI dst, rRegI src ) %{ |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6734 predicate(VM_Version::supports_cmov() ); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6735 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6736 ins_cost(200); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6737 expand %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6738 cmovI_regU(cop, cr, dst, src); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6739 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6740 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6741 |
| 0 | 6742 // Conditional move |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
6743 instruct cmovI_mem(cmpOp cop, eFlagsReg cr, rRegI dst, memory src) %{ |
| 0 | 6744 predicate(VM_Version::supports_cmov() ); |
| 6745 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); | |
| 6746 ins_cost(250); | |
| 6747 format %{ "CMOV$cop $dst,$src" %} | |
| 6748 opcode(0x0F,0x40); | |
| 6749 ins_encode( enc_cmov(cop), RegMem( dst, src ) ); | |
| 6750 ins_pipe( pipe_cmov_mem ); | |
| 6751 %} | |
| 6752 | |
| 6753 // Conditional move | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
6754 instruct cmovI_memU(cmpOpU cop, eFlagsRegU cr, rRegI dst, memory src) %{ |
| 0 | 6755 predicate(VM_Version::supports_cmov() ); |
| 6756 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); | |
| 6757 ins_cost(250); | |
| 6758 format %{ "CMOV$cop $dst,$src" %} | |
| 6759 opcode(0x0F,0x40); | |
| 6760 ins_encode( enc_cmov(cop), RegMem( dst, src ) ); | |
| 6761 ins_pipe( pipe_cmov_mem ); | |
| 6762 %} | |
| 6763 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
6764 instruct cmovI_memUCF(cmpOpUCF cop, eFlagsRegUCF cr, rRegI dst, memory src) %{ |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6765 predicate(VM_Version::supports_cmov() ); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6766 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6767 ins_cost(250); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6768 expand %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6769 cmovI_memU(cop, cr, dst, src); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6770 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6771 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6772 |
| 0 | 6773 // Conditional move |
| 6774 instruct cmovP_reg(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{ | |
| 6775 predicate(VM_Version::supports_cmov() ); | |
| 6776 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); | |
| 6777 ins_cost(200); | |
| 6778 format %{ "CMOV$cop $dst,$src\t# ptr" %} | |
| 6779 opcode(0x0F,0x40); | |
| 6780 ins_encode( enc_cmov(cop), RegReg( dst, src ) ); | |
| 6781 ins_pipe( pipe_cmov_reg ); | |
| 6782 %} | |
| 6783 | |
| 6784 // Conditional move (non-P6 version) | |
| 6785 // Note: a CMoveP is generated for stubs and native wrappers | |
| 6786 // regardless of whether we are on a P6, so we | |
| 6787 // emulate a cmov here | |
| 6788 instruct cmovP_reg_nonP6(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{ | |
| 6789 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); | |
| 6790 ins_cost(300); | |
| 6791 format %{ "Jn$cop skip\n\t" | |
| 6792 "MOV $dst,$src\t# pointer\n" | |
| 6793 "skip:" %} | |
| 6794 opcode(0x8b); | |
| 6795 ins_encode( enc_cmov_branch(cop, 0x2), OpcP, RegReg(dst, src)); | |
| 6796 ins_pipe( pipe_cmov_reg ); | |
| 6797 %} | |
| 6798 | |
| 6799 // Conditional move | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6800 instruct cmovP_regU(cmpOpU cop, eFlagsRegU cr, eRegP dst, eRegP src ) %{ |
| 0 | 6801 predicate(VM_Version::supports_cmov() ); |
| 6802 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); | |
| 6803 ins_cost(200); | |
| 6804 format %{ "CMOV$cop $dst,$src\t# ptr" %} | |
| 6805 opcode(0x0F,0x40); | |
| 6806 ins_encode( enc_cmov(cop), RegReg( dst, src ) ); | |
| 6807 ins_pipe( pipe_cmov_reg ); | |
| 6808 %} | |
| 6809 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6810 instruct cmovP_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegP dst, eRegP src ) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6811 predicate(VM_Version::supports_cmov() ); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6812 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6813 ins_cost(200); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6814 expand %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6815 cmovP_regU(cop, cr, dst, src); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6816 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6817 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6818 |
| 0 | 6819 // DISABLED: Requires the ADLC to emit a bottom_type call that |
| 6820 // correctly meets the two pointer arguments; one is an incoming | |
| 6821 // register but the other is a memory operand. ALSO appears to | |
| 6822 // be buggy with implicit null checks. | |
| 6823 // | |
| 6824 //// Conditional move | |
| 6825 //instruct cmovP_mem(cmpOp cop, eFlagsReg cr, eRegP dst, memory src) %{ | |
| 6826 // predicate(VM_Version::supports_cmov() ); | |
| 6827 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src)))); | |
| 6828 // ins_cost(250); | |
| 6829 // format %{ "CMOV$cop $dst,$src\t# ptr" %} | |
| 6830 // opcode(0x0F,0x40); | |
| 6831 // ins_encode( enc_cmov(cop), RegMem( dst, src ) ); | |
| 6832 // ins_pipe( pipe_cmov_mem ); | |
| 6833 //%} | |
| 6834 // | |
| 6835 //// Conditional move | |
| 6836 //instruct cmovP_memU(cmpOpU cop, eFlagsRegU cr, eRegP dst, memory src) %{ | |
| 6837 // predicate(VM_Version::supports_cmov() ); | |
| 6838 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src)))); | |
| 6839 // ins_cost(250); | |
| 6840 // format %{ "CMOV$cop $dst,$src\t# ptr" %} | |
| 6841 // opcode(0x0F,0x40); | |
| 6842 // ins_encode( enc_cmov(cop), RegMem( dst, src ) ); | |
| 6843 // ins_pipe( pipe_cmov_mem ); | |
| 6844 //%} | |
| 6845 | |
| 6846 // Conditional move | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6847 instruct fcmovDPR_regU(cmpOp_fcmov cop, eFlagsRegU cr, regDPR1 dst, regDPR src) %{ |
| 0 | 6848 predicate(UseSSE<=1); |
| 6849 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); | |
| 6850 ins_cost(200); | |
| 6851 format %{ "FCMOV$cop $dst,$src\t# double" %} | |
| 6852 opcode(0xDA); | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6853 ins_encode( enc_cmov_dpr(cop,src) ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6854 ins_pipe( pipe_cmovDPR_reg ); |
| 0 | 6855 %} |
| 6856 | |
| 6857 // Conditional move | |
|
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|
6858 instruct fcmovFPR_regU(cmpOp_fcmov cop, eFlagsRegU cr, regFPR1 dst, regFPR src) %{ |
| 0 | 6859 predicate(UseSSE==0); |
| 6860 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); | |
| 6861 ins_cost(200); | |
| 6862 format %{ "FCMOV$cop $dst,$src\t# float" %} | |
| 6863 opcode(0xDA); | |
|
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|
6864 ins_encode( enc_cmov_dpr(cop,src) ); |
|
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|
6865 ins_pipe( pipe_cmovDPR_reg ); |
| 0 | 6866 %} |
| 6867 | |
| 6868 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned. | |
|
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|
6869 instruct fcmovDPR_regS(cmpOp cop, eFlagsReg cr, regDPR dst, regDPR src) %{ |
| 0 | 6870 predicate(UseSSE<=1); |
| 6871 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); | |
| 6872 ins_cost(200); | |
| 6873 format %{ "Jn$cop skip\n\t" | |
| 6874 "MOV $dst,$src\t# double\n" | |
| 6875 "skip:" %} | |
| 6876 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */ | |
|
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|
6877 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_DPR(src), OpcP, RegOpc(dst) ); |
|
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|
6878 ins_pipe( pipe_cmovDPR_reg ); |
| 0 | 6879 %} |
| 6880 | |
| 6881 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned. | |
|
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|
6882 instruct fcmovFPR_regS(cmpOp cop, eFlagsReg cr, regFPR dst, regFPR src) %{ |
| 0 | 6883 predicate(UseSSE==0); |
| 6884 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); | |
| 6885 ins_cost(200); | |
| 6886 format %{ "Jn$cop skip\n\t" | |
| 6887 "MOV $dst,$src\t# float\n" | |
| 6888 "skip:" %} | |
| 6889 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */ | |
|
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|
6890 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_FPR(src), OpcP, RegOpc(dst) ); |
|
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|
6891 ins_pipe( pipe_cmovDPR_reg ); |
| 0 | 6892 %} |
| 6893 | |
| 6894 // No CMOVE with SSE/SSE2 | |
|
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|
6895 instruct fcmovF_regS(cmpOp cop, eFlagsReg cr, regF dst, regF src) %{ |
| 0 | 6896 predicate (UseSSE>=1); |
| 6897 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); | |
| 6898 ins_cost(200); | |
| 6899 format %{ "Jn$cop skip\n\t" | |
| 6900 "MOVSS $dst,$src\t# float\n" | |
| 6901 "skip:" %} | |
| 6902 ins_encode %{ | |
| 6903 Label skip; | |
| 6904 // Invert sense of branch from sense of CMOV | |
| 6905 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip); | |
| 6906 __ movflt($dst$$XMMRegister, $src$$XMMRegister); | |
| 6907 __ bind(skip); | |
| 6908 %} | |
| 6909 ins_pipe( pipe_slow ); | |
| 6910 %} | |
| 6911 | |
| 6912 // No CMOVE with SSE/SSE2 | |
|
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|
6913 instruct fcmovD_regS(cmpOp cop, eFlagsReg cr, regD dst, regD src) %{ |
| 0 | 6914 predicate (UseSSE>=2); |
| 6915 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); | |
| 6916 ins_cost(200); | |
| 6917 format %{ "Jn$cop skip\n\t" | |
| 6918 "MOVSD $dst,$src\t# float\n" | |
| 6919 "skip:" %} | |
| 6920 ins_encode %{ | |
| 6921 Label skip; | |
| 6922 // Invert sense of branch from sense of CMOV | |
| 6923 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip); | |
| 6924 __ movdbl($dst$$XMMRegister, $src$$XMMRegister); | |
| 6925 __ bind(skip); | |
| 6926 %} | |
| 6927 ins_pipe( pipe_slow ); | |
| 6928 %} | |
| 6929 | |
| 6930 // unsigned version | |
|
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|
6931 instruct fcmovF_regU(cmpOpU cop, eFlagsRegU cr, regF dst, regF src) %{ |
| 0 | 6932 predicate (UseSSE>=1); |
| 6933 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); | |
| 6934 ins_cost(200); | |
| 6935 format %{ "Jn$cop skip\n\t" | |
| 6936 "MOVSS $dst,$src\t# float\n" | |
| 6937 "skip:" %} | |
| 6938 ins_encode %{ | |
| 6939 Label skip; | |
| 6940 // Invert sense of branch from sense of CMOV | |
| 6941 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip); | |
| 6942 __ movflt($dst$$XMMRegister, $src$$XMMRegister); | |
| 6943 __ bind(skip); | |
| 6944 %} | |
| 6945 ins_pipe( pipe_slow ); | |
| 6946 %} | |
| 6947 | |
|
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|
6948 instruct fcmovF_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regF dst, regF src) %{ |
|
415
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|
6949 predicate (UseSSE>=1); |
|
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|
6950 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); |
|
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|
6951 ins_cost(200); |
|
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diff
changeset
|
6952 expand %{ |
|
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changeset
|
6953 fcmovF_regU(cop, cr, dst, src); |
|
415
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|
6954 %} |
|
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changeset
|
6955 %} |
|
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diff
changeset
|
6956 |
| 0 | 6957 // unsigned version |
|
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|
6958 instruct fcmovD_regU(cmpOpU cop, eFlagsRegU cr, regD dst, regD src) %{ |
| 0 | 6959 predicate (UseSSE>=2); |
| 6960 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); | |
| 6961 ins_cost(200); | |
| 6962 format %{ "Jn$cop skip\n\t" | |
| 6963 "MOVSD $dst,$src\t# float\n" | |
| 6964 "skip:" %} | |
| 6965 ins_encode %{ | |
| 6966 Label skip; | |
| 6967 // Invert sense of branch from sense of CMOV | |
| 6968 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip); | |
| 6969 __ movdbl($dst$$XMMRegister, $src$$XMMRegister); | |
| 6970 __ bind(skip); | |
| 6971 %} | |
| 6972 ins_pipe( pipe_slow ); | |
| 6973 %} | |
| 6974 | |
|
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|
6975 instruct fcmovD_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regD dst, regD src) %{ |
|
415
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changeset
|
6976 predicate (UseSSE>=2); |
|
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diff
changeset
|
6977 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); |
|
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|
6978 ins_cost(200); |
|
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diff
changeset
|
6979 expand %{ |
|
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changeset
|
6980 fcmovD_regU(cop, cr, dst, src); |
|
415
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diff
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|
6981 %} |
|
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parents:
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diff
changeset
|
6982 %} |
|
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diff
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|
6983 |
| 0 | 6984 instruct cmovL_reg(cmpOp cop, eFlagsReg cr, eRegL dst, eRegL src) %{ |
| 6985 predicate(VM_Version::supports_cmov() ); | |
| 6986 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); | |
| 6987 ins_cost(200); | |
| 6988 format %{ "CMOV$cop $dst.lo,$src.lo\n\t" | |
| 6989 "CMOV$cop $dst.hi,$src.hi" %} | |
| 6990 opcode(0x0F,0x40); | |
| 6991 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) ); | |
| 6992 ins_pipe( pipe_cmov_reg_long ); | |
| 6993 %} | |
| 6994 | |
| 6995 instruct cmovL_regU(cmpOpU cop, eFlagsRegU cr, eRegL dst, eRegL src) %{ | |
| 6996 predicate(VM_Version::supports_cmov() ); | |
| 6997 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); | |
| 6998 ins_cost(200); | |
| 6999 format %{ "CMOV$cop $dst.lo,$src.lo\n\t" | |
| 7000 "CMOV$cop $dst.hi,$src.hi" %} | |
| 7001 opcode(0x0F,0x40); | |
| 7002 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) ); | |
| 7003 ins_pipe( pipe_cmov_reg_long ); | |
| 7004 %} | |
| 7005 | |
|
415
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changeset
|
7006 instruct cmovL_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegL dst, eRegL src) %{ |
|
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parents:
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diff
changeset
|
7007 predicate(VM_Version::supports_cmov() ); |
|
4d9884b01ba6
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diff
changeset
|
7008 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); |
|
4d9884b01ba6
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diff
changeset
|
7009 ins_cost(200); |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
7010 expand %{ |
|
4d9884b01ba6
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diff
changeset
|
7011 cmovL_regU(cop, cr, dst, src); |
|
4d9884b01ba6
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parents:
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diff
changeset
|
7012 %} |
|
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never
parents:
403
diff
changeset
|
7013 %} |
|
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diff
changeset
|
7014 |
| 0 | 7015 //----------Arithmetic Instructions-------------------------------------------- |
| 7016 //----------Addition Instructions---------------------------------------------- | |
| 12323 | 7017 |
| 0 | 7018 // Integer Addition Instructions |
|
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|
7019 instruct addI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 7020 match(Set dst (AddI dst src)); |
| 7021 effect(KILL cr); | |
| 7022 | |
| 7023 size(2); | |
| 7024 format %{ "ADD $dst,$src" %} | |
| 7025 opcode(0x03); | |
| 7026 ins_encode( OpcP, RegReg( dst, src) ); | |
| 7027 ins_pipe( ialu_reg_reg ); | |
| 7028 %} | |
| 7029 | |
|
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changeset
|
7030 instruct addI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{ |
| 0 | 7031 match(Set dst (AddI dst src)); |
| 7032 effect(KILL cr); | |
| 7033 | |
| 7034 format %{ "ADD $dst,$src" %} | |
| 7035 opcode(0x81, 0x00); /* /0 id */ | |
| 7036 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); | |
| 7037 ins_pipe( ialu_reg ); | |
| 7038 %} | |
| 7039 | |
|
6179
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|
7040 instruct incI_eReg(rRegI dst, immI1 src, eFlagsReg cr) %{ |
| 0 | 7041 predicate(UseIncDec); |
| 7042 match(Set dst (AddI dst src)); | |
| 7043 effect(KILL cr); | |
| 7044 | |
| 7045 size(1); | |
| 7046 format %{ "INC $dst" %} | |
| 7047 opcode(0x40); /* */ | |
| 7048 ins_encode( Opc_plus( primary, dst ) ); | |
| 7049 ins_pipe( ialu_reg ); | |
| 7050 %} | |
| 7051 | |
|
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|
7052 instruct leaI_eReg_immI(rRegI dst, rRegI src0, immI src1) %{ |
| 0 | 7053 match(Set dst (AddI src0 src1)); |
| 7054 ins_cost(110); | |
| 7055 | |
| 7056 format %{ "LEA $dst,[$src0 + $src1]" %} | |
| 7057 opcode(0x8D); /* 0x8D /r */ | |
| 7058 ins_encode( OpcP, RegLea( dst, src0, src1 ) ); | |
| 7059 ins_pipe( ialu_reg_reg ); | |
| 7060 %} | |
| 7061 | |
| 7062 instruct leaP_eReg_immI(eRegP dst, eRegP src0, immI src1) %{ | |
| 7063 match(Set dst (AddP src0 src1)); | |
| 7064 ins_cost(110); | |
| 7065 | |
| 7066 format %{ "LEA $dst,[$src0 + $src1]\t# ptr" %} | |
| 7067 opcode(0x8D); /* 0x8D /r */ | |
| 7068 ins_encode( OpcP, RegLea( dst, src0, src1 ) ); | |
| 7069 ins_pipe( ialu_reg_reg ); | |
| 7070 %} | |
| 7071 | |
|
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|
7072 instruct decI_eReg(rRegI dst, immI_M1 src, eFlagsReg cr) %{ |
| 0 | 7073 predicate(UseIncDec); |
| 7074 match(Set dst (AddI dst src)); | |
| 7075 effect(KILL cr); | |
| 7076 | |
| 7077 size(1); | |
| 7078 format %{ "DEC $dst" %} | |
| 7079 opcode(0x48); /* */ | |
| 7080 ins_encode( Opc_plus( primary, dst ) ); | |
| 7081 ins_pipe( ialu_reg ); | |
| 7082 %} | |
| 7083 | |
|
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|
7084 instruct addP_eReg(eRegP dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 7085 match(Set dst (AddP dst src)); |
| 7086 effect(KILL cr); | |
| 7087 | |
| 7088 size(2); | |
| 7089 format %{ "ADD $dst,$src" %} | |
| 7090 opcode(0x03); | |
| 7091 ins_encode( OpcP, RegReg( dst, src) ); | |
| 7092 ins_pipe( ialu_reg_reg ); | |
| 7093 %} | |
| 7094 | |
| 7095 instruct addP_eReg_imm(eRegP dst, immI src, eFlagsReg cr) %{ | |
| 7096 match(Set dst (AddP dst src)); | |
| 7097 effect(KILL cr); | |
| 7098 | |
| 7099 format %{ "ADD $dst,$src" %} | |
| 7100 opcode(0x81,0x00); /* Opcode 81 /0 id */ | |
| 7101 // ins_encode( RegImm( dst, src) ); | |
| 7102 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); | |
| 7103 ins_pipe( ialu_reg ); | |
| 7104 %} | |
| 7105 | |
|
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|
7106 instruct addI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{ |
| 0 | 7107 match(Set dst (AddI dst (LoadI src))); |
| 7108 effect(KILL cr); | |
| 7109 | |
| 7110 ins_cost(125); | |
| 7111 format %{ "ADD $dst,$src" %} | |
| 7112 opcode(0x03); | |
| 7113 ins_encode( OpcP, RegMem( dst, src) ); | |
| 7114 ins_pipe( ialu_reg_mem ); | |
| 7115 %} | |
| 7116 | |
|
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changeset
|
7117 instruct addI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 7118 match(Set dst (StoreI dst (AddI (LoadI dst) src))); |
| 7119 effect(KILL cr); | |
| 7120 | |
| 7121 ins_cost(150); | |
| 7122 format %{ "ADD $dst,$src" %} | |
| 7123 opcode(0x01); /* Opcode 01 /r */ | |
| 7124 ins_encode( OpcP, RegMem( src, dst ) ); | |
| 7125 ins_pipe( ialu_mem_reg ); | |
| 7126 %} | |
| 7127 | |
| 7128 // Add Memory with Immediate | |
| 7129 instruct addI_mem_imm(memory dst, immI src, eFlagsReg cr) %{ | |
| 7130 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 7131 effect(KILL cr); | |
| 7132 | |
| 7133 ins_cost(125); | |
| 7134 format %{ "ADD $dst,$src" %} | |
| 7135 opcode(0x81); /* Opcode 81 /0 id */ | |
| 7136 ins_encode( OpcSE( src ), RMopc_Mem(0x00,dst), Con8or32( src ) ); | |
| 7137 ins_pipe( ialu_mem_imm ); | |
| 7138 %} | |
| 7139 | |
| 7140 instruct incI_mem(memory dst, immI1 src, eFlagsReg cr) %{ | |
| 7141 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 7142 effect(KILL cr); | |
| 7143 | |
| 7144 ins_cost(125); | |
| 7145 format %{ "INC $dst" %} | |
| 7146 opcode(0xFF); /* Opcode FF /0 */ | |
| 7147 ins_encode( OpcP, RMopc_Mem(0x00,dst)); | |
| 7148 ins_pipe( ialu_mem_imm ); | |
| 7149 %} | |
| 7150 | |
| 7151 instruct decI_mem(memory dst, immI_M1 src, eFlagsReg cr) %{ | |
| 7152 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 7153 effect(KILL cr); | |
| 7154 | |
| 7155 ins_cost(125); | |
| 7156 format %{ "DEC $dst" %} | |
| 7157 opcode(0xFF); /* Opcode FF /1 */ | |
| 7158 ins_encode( OpcP, RMopc_Mem(0x01,dst)); | |
| 7159 ins_pipe( ialu_mem_imm ); | |
| 7160 %} | |
| 7161 | |
| 7162 | |
| 7163 instruct checkCastPP( eRegP dst ) %{ | |
| 7164 match(Set dst (CheckCastPP dst)); | |
| 7165 | |
| 7166 size(0); | |
| 7167 format %{ "#checkcastPP of $dst" %} | |
| 7168 ins_encode( /*empty encoding*/ ); | |
| 7169 ins_pipe( empty ); | |
| 7170 %} | |
| 7171 | |
| 7172 instruct castPP( eRegP dst ) %{ | |
| 7173 match(Set dst (CastPP dst)); | |
| 7174 format %{ "#castPP of $dst" %} | |
| 7175 ins_encode( /*empty encoding*/ ); | |
| 7176 ins_pipe( empty ); | |
| 7177 %} | |
| 7178 | |
|
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changeset
|
7179 instruct castII( rRegI dst ) %{ |
| 0 | 7180 match(Set dst (CastII dst)); |
| 7181 format %{ "#castII of $dst" %} | |
| 7182 ins_encode( /*empty encoding*/ ); | |
| 7183 ins_cost(0); | |
| 7184 ins_pipe( empty ); | |
| 7185 %} | |
| 7186 | |
| 7187 | |
| 7188 // Load-locked - same as a regular pointer load when used with compare-swap | |
| 7189 instruct loadPLocked(eRegP dst, memory mem) %{ | |
| 7190 match(Set dst (LoadPLocked mem)); | |
| 7191 | |
| 7192 ins_cost(125); | |
| 7193 format %{ "MOV $dst,$mem\t# Load ptr. locked" %} | |
| 7194 opcode(0x8B); | |
| 7195 ins_encode( OpcP, RegMem(dst,mem)); | |
| 7196 ins_pipe( ialu_reg_mem ); | |
| 7197 %} | |
| 7198 | |
| 7199 // Conditional-store of the updated heap-top. | |
| 7200 // Used during allocation of the shared heap. | |
| 7201 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel. | |
| 7202 instruct storePConditional( memory heap_top_ptr, eAXRegP oldval, eRegP newval, eFlagsReg cr ) %{ | |
| 7203 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval))); | |
| 7204 // EAX is killed if there is contention, but then it's also unused. | |
| 7205 // In the common case of no contention, EAX holds the new oop address. | |
| 7206 format %{ "CMPXCHG $heap_top_ptr,$newval\t# If EAX==$heap_top_ptr Then store $newval into $heap_top_ptr" %} | |
| 7207 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval,heap_top_ptr) ); | |
| 7208 ins_pipe( pipe_cmpxchg ); | |
| 7209 %} | |
| 7210 | |
|
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7211 // Conditional-store of an int value. |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7212 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG on Intel. |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
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diff
changeset
|
7213 instruct storeIConditional( memory mem, eAXRegI oldval, rRegI newval, eFlagsReg cr ) %{ |
|
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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parents:
415
diff
changeset
|
7214 match(Set cr (StoreIConditional mem (Binary oldval newval))); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7215 effect(KILL oldval); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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parents:
415
diff
changeset
|
7216 format %{ "CMPXCHG $mem,$newval\t# If EAX==$mem Then store $newval into $mem" %} |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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parents:
415
diff
changeset
|
7217 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval, mem) ); |
| 0 | 7218 ins_pipe( pipe_cmpxchg ); |
| 7219 %} | |
| 7220 | |
|
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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parents:
415
diff
changeset
|
7221 // Conditional-store of a long value. |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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parents:
415
diff
changeset
|
7222 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG8 on Intel. |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7223 instruct storeLConditional( memory mem, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{ |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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parents:
415
diff
changeset
|
7224 match(Set cr (StoreLConditional mem (Binary oldval newval))); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7225 effect(KILL oldval); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7226 format %{ "XCHG EBX,ECX\t# correct order for CMPXCHG8 instruction\n\t" |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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parents:
415
diff
changeset
|
7227 "CMPXCHG8 $mem,ECX:EBX\t# If EDX:EAX==$mem Then store ECX:EBX into $mem\n\t" |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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parents:
415
diff
changeset
|
7228 "XCHG EBX,ECX" |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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parents:
415
diff
changeset
|
7229 %} |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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parents:
415
diff
changeset
|
7230 ins_encode %{ |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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parents:
415
diff
changeset
|
7231 // Note: we need to swap rbx, and rcx before and after the |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7232 // cmpxchg8 instruction because the instruction uses |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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parents:
415
diff
changeset
|
7233 // rcx as the high order word of the new value to store but |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7234 // our register encoding uses rbx. |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7235 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc)); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7236 if( os::is_MP() ) |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7237 __ lock(); |
| 624 | 7238 __ cmpxchg8($mem$$Address); |
|
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7239 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc)); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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parents:
415
diff
changeset
|
7240 %} |
| 0 | 7241 ins_pipe( pipe_cmpxchg ); |
| 7242 %} | |
| 7243 | |
| 7244 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them | |
| 7245 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
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parents:
6143
diff
changeset
|
7246 instruct compareAndSwapL( rRegI res, eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{ |
|
6795
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7247 predicate(VM_Version::supports_cx8()); |
| 0 | 7248 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval))); |
| 7249 effect(KILL cr, KILL oldval); | |
| 7250 format %{ "CMPXCHG8 [$mem_ptr],$newval\t# If EDX:EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t" | |
| 7251 "MOV $res,0\n\t" | |
| 7252 "JNE,s fail\n\t" | |
| 7253 "MOV $res,1\n" | |
| 7254 "fail:" %} | |
| 7255 ins_encode( enc_cmpxchg8(mem_ptr), | |
| 7256 enc_flags_ne_to_boolean(res) ); | |
| 7257 ins_pipe( pipe_cmpxchg ); | |
| 7258 %} | |
| 7259 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7260 instruct compareAndSwapP( rRegI res, pRegP mem_ptr, eAXRegP oldval, eCXRegP newval, eFlagsReg cr) %{ |
| 0 | 7261 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval))); |
| 7262 effect(KILL cr, KILL oldval); | |
| 7263 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t" | |
| 7264 "MOV $res,0\n\t" | |
| 7265 "JNE,s fail\n\t" | |
| 7266 "MOV $res,1\n" | |
| 7267 "fail:" %} | |
| 7268 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) ); | |
| 7269 ins_pipe( pipe_cmpxchg ); | |
| 7270 %} | |
| 7271 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7272 instruct compareAndSwapI( rRegI res, pRegP mem_ptr, eAXRegI oldval, eCXRegI newval, eFlagsReg cr) %{ |
| 0 | 7273 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval))); |
| 7274 effect(KILL cr, KILL oldval); | |
| 7275 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t" | |
| 7276 "MOV $res,0\n\t" | |
| 7277 "JNE,s fail\n\t" | |
| 7278 "MOV $res,1\n" | |
| 7279 "fail:" %} | |
| 7280 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) ); | |
| 7281 ins_pipe( pipe_cmpxchg ); | |
| 7282 %} | |
| 7283 | |
|
6795
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7284 instruct xaddI_no_res( memory mem, Universe dummy, immI add, eFlagsReg cr) %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7285 predicate(n->as_LoadStore()->result_not_used()); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7286 match(Set dummy (GetAndAddI mem add)); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7287 effect(KILL cr); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7288 format %{ "ADDL [$mem],$add" %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7289 ins_encode %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7290 if (os::is_MP()) { __ lock(); } |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7291 __ addl($mem$$Address, $add$$constant); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7292 %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7293 ins_pipe( pipe_cmpxchg ); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7294 %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7295 |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7296 instruct xaddI( memory mem, rRegI newval, eFlagsReg cr) %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7297 match(Set newval (GetAndAddI mem newval)); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7298 effect(KILL cr); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7299 format %{ "XADDL [$mem],$newval" %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7300 ins_encode %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7301 if (os::is_MP()) { __ lock(); } |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7302 __ xaddl($mem$$Address, $newval$$Register); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7303 %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7304 ins_pipe( pipe_cmpxchg ); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7305 %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7306 |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7307 instruct xchgI( memory mem, rRegI newval) %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7308 match(Set newval (GetAndSetI mem newval)); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7309 format %{ "XCHGL $newval,[$mem]" %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7310 ins_encode %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7311 __ xchgl($newval$$Register, $mem$$Address); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7312 %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7313 ins_pipe( pipe_cmpxchg ); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7314 %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7315 |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7316 instruct xchgP( memory mem, pRegP newval) %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7317 match(Set newval (GetAndSetP mem newval)); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7318 format %{ "XCHGL $newval,[$mem]" %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7319 ins_encode %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7320 __ xchgl($newval$$Register, $mem$$Address); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7321 %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7322 ins_pipe( pipe_cmpxchg ); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7323 %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7324 |
| 0 | 7325 //----------Subtraction Instructions------------------------------------------- |
|
12972
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7326 |
| 0 | 7327 // Integer Subtraction Instructions |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7328 instruct subI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 7329 match(Set dst (SubI dst src)); |
| 7330 effect(KILL cr); | |
| 7331 | |
| 7332 size(2); | |
| 7333 format %{ "SUB $dst,$src" %} | |
| 7334 opcode(0x2B); | |
| 7335 ins_encode( OpcP, RegReg( dst, src) ); | |
| 7336 ins_pipe( ialu_reg_reg ); | |
| 7337 %} | |
| 7338 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
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changeset
|
7339 instruct subI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{ |
| 0 | 7340 match(Set dst (SubI dst src)); |
| 7341 effect(KILL cr); | |
| 7342 | |
| 7343 format %{ "SUB $dst,$src" %} | |
| 7344 opcode(0x81,0x05); /* Opcode 81 /5 */ | |
| 7345 // ins_encode( RegImm( dst, src) ); | |
| 7346 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); | |
| 7347 ins_pipe( ialu_reg ); | |
| 7348 %} | |
| 7349 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7350 instruct subI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{ |
| 0 | 7351 match(Set dst (SubI dst (LoadI src))); |
| 7352 effect(KILL cr); | |
| 7353 | |
| 7354 ins_cost(125); | |
| 7355 format %{ "SUB $dst,$src" %} | |
| 7356 opcode(0x2B); | |
| 7357 ins_encode( OpcP, RegMem( dst, src) ); | |
| 7358 ins_pipe( ialu_reg_mem ); | |
| 7359 %} | |
| 7360 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7361 instruct subI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 7362 match(Set dst (StoreI dst (SubI (LoadI dst) src))); |
| 7363 effect(KILL cr); | |
| 7364 | |
| 7365 ins_cost(150); | |
| 7366 format %{ "SUB $dst,$src" %} | |
| 7367 opcode(0x29); /* Opcode 29 /r */ | |
| 7368 ins_encode( OpcP, RegMem( src, dst ) ); | |
| 7369 ins_pipe( ialu_mem_reg ); | |
| 7370 %} | |
| 7371 | |
| 7372 // Subtract from a pointer | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7373 instruct subP_eReg(eRegP dst, rRegI src, immI0 zero, eFlagsReg cr) %{ |
| 0 | 7374 match(Set dst (AddP dst (SubI zero src))); |
| 7375 effect(KILL cr); | |
| 7376 | |
| 7377 size(2); | |
| 7378 format %{ "SUB $dst,$src" %} | |
| 7379 opcode(0x2B); | |
| 7380 ins_encode( OpcP, RegReg( dst, src) ); | |
| 7381 ins_pipe( ialu_reg_reg ); | |
| 7382 %} | |
| 7383 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7384 instruct negI_eReg(rRegI dst, immI0 zero, eFlagsReg cr) %{ |
| 0 | 7385 match(Set dst (SubI zero dst)); |
| 7386 effect(KILL cr); | |
| 7387 | |
| 7388 size(2); | |
| 7389 format %{ "NEG $dst" %} | |
| 7390 opcode(0xF7,0x03); // Opcode F7 /3 | |
| 7391 ins_encode( OpcP, RegOpc( dst ) ); | |
| 7392 ins_pipe( ialu_reg ); | |
| 7393 %} | |
| 7394 | |
| 7395 //----------Multiplication/Division Instructions------------------------------- | |
| 7396 // Integer Multiplication Instructions | |
| 7397 // Multiply Register | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7398 instruct mulI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 7399 match(Set dst (MulI dst src)); |
| 7400 effect(KILL cr); | |
| 7401 | |
| 7402 size(3); | |
| 7403 ins_cost(300); | |
| 7404 format %{ "IMUL $dst,$src" %} | |
| 7405 opcode(0xAF, 0x0F); | |
| 7406 ins_encode( OpcS, OpcP, RegReg( dst, src) ); | |
| 7407 ins_pipe( ialu_reg_reg_alu0 ); | |
| 7408 %} | |
| 7409 | |
| 7410 // Multiply 32-bit Immediate | |
|
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|
7411 instruct mulI_eReg_imm(rRegI dst, rRegI src, immI imm, eFlagsReg cr) %{ |
| 0 | 7412 match(Set dst (MulI src imm)); |
| 7413 effect(KILL cr); | |
| 7414 | |
| 7415 ins_cost(300); | |
| 7416 format %{ "IMUL $dst,$src,$imm" %} | |
| 7417 opcode(0x69); /* 69 /r id */ | |
| 7418 ins_encode( OpcSE(imm), RegReg( dst, src ), Con8or32( imm ) ); | |
| 7419 ins_pipe( ialu_reg_reg_alu0 ); | |
| 7420 %} | |
| 7421 | |
| 7422 instruct loadConL_low_only(eADXRegL_low_only dst, immL32 src, eFlagsReg cr) %{ | |
| 7423 match(Set dst src); | |
| 7424 effect(KILL cr); | |
| 7425 | |
| 7426 // Note that this is artificially increased to make it more expensive than loadConL | |
| 7427 ins_cost(250); | |
| 7428 format %{ "MOV EAX,$src\t// low word only" %} | |
| 7429 opcode(0xB8); | |
| 7430 ins_encode( LdImmL_Lo(dst, src) ); | |
| 7431 ins_pipe( ialu_reg_fat ); | |
| 7432 %} | |
| 7433 | |
| 7434 // Multiply by 32-bit Immediate, taking the shifted high order results | |
| 7435 // (special case for shift by 32) | |
| 7436 instruct mulI_imm_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32 cnt, eFlagsReg cr) %{ | |
| 7437 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt))); | |
| 7438 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL && | |
| 7439 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint && | |
| 7440 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint ); | |
| 7441 effect(USE src1, KILL cr); | |
| 7442 | |
| 7443 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only | |
| 7444 ins_cost(0*100 + 1*400 - 150); | |
| 7445 format %{ "IMUL EDX:EAX,$src1" %} | |
| 7446 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) ); | |
| 7447 ins_pipe( pipe_slow ); | |
| 7448 %} | |
| 7449 | |
| 7450 // Multiply by 32-bit Immediate, taking the shifted high order results | |
| 7451 instruct mulI_imm_RShift_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr) %{ | |
| 7452 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt))); | |
| 7453 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL && | |
| 7454 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint && | |
| 7455 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint ); | |
| 7456 effect(USE src1, KILL cr); | |
| 7457 | |
| 7458 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only | |
| 7459 ins_cost(1*100 + 1*400 - 150); | |
| 7460 format %{ "IMUL EDX:EAX,$src1\n\t" | |
| 7461 "SAR EDX,$cnt-32" %} | |
| 7462 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) ); | |
| 7463 ins_pipe( pipe_slow ); | |
| 7464 %} | |
| 7465 | |
| 7466 // Multiply Memory 32-bit Immediate | |
|
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|
7467 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, eFlagsReg cr) %{ |
| 0 | 7468 match(Set dst (MulI (LoadI src) imm)); |
| 7469 effect(KILL cr); | |
| 7470 | |
| 7471 ins_cost(300); | |
| 7472 format %{ "IMUL $dst,$src,$imm" %} | |
| 7473 opcode(0x69); /* 69 /r id */ | |
| 7474 ins_encode( OpcSE(imm), RegMem( dst, src ), Con8or32( imm ) ); | |
| 7475 ins_pipe( ialu_reg_mem_alu0 ); | |
| 7476 %} | |
| 7477 | |
| 7478 // Multiply Memory | |
|
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|
7479 instruct mulI(rRegI dst, memory src, eFlagsReg cr) %{ |
| 0 | 7480 match(Set dst (MulI dst (LoadI src))); |
| 7481 effect(KILL cr); | |
| 7482 | |
| 7483 ins_cost(350); | |
| 7484 format %{ "IMUL $dst,$src" %} | |
| 7485 opcode(0xAF, 0x0F); | |
| 7486 ins_encode( OpcS, OpcP, RegMem( dst, src) ); | |
| 7487 ins_pipe( ialu_reg_mem_alu0 ); | |
| 7488 %} | |
| 7489 | |
| 7490 // Multiply Register Int to Long | |
| 7491 instruct mulI2L(eADXRegL dst, eAXRegI src, nadxRegI src1, eFlagsReg flags) %{ | |
| 7492 // Basic Idea: long = (long)int * (long)int | |
| 7493 match(Set dst (MulL (ConvI2L src) (ConvI2L src1))); | |
| 7494 effect(DEF dst, USE src, USE src1, KILL flags); | |
| 7495 | |
| 7496 ins_cost(300); | |
| 7497 format %{ "IMUL $dst,$src1" %} | |
| 7498 | |
| 7499 ins_encode( long_int_multiply( dst, src1 ) ); | |
| 7500 ins_pipe( ialu_reg_reg_alu0 ); | |
| 7501 %} | |
| 7502 | |
| 7503 instruct mulIS_eReg(eADXRegL dst, immL_32bits mask, eFlagsReg flags, eAXRegI src, nadxRegI src1) %{ | |
| 7504 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL) | |
| 7505 match(Set dst (MulL (AndL (ConvI2L src) mask) (AndL (ConvI2L src1) mask))); | |
| 7506 effect(KILL flags); | |
| 7507 | |
| 7508 ins_cost(300); | |
| 7509 format %{ "MUL $dst,$src1" %} | |
| 7510 | |
| 7511 ins_encode( long_uint_multiply(dst, src1) ); | |
| 7512 ins_pipe( ialu_reg_reg_alu0 ); | |
| 7513 %} | |
| 7514 | |
| 7515 // Multiply Register Long | |
|
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7516 instruct mulL_eReg(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{ |
| 0 | 7517 match(Set dst (MulL dst src)); |
| 7518 effect(KILL cr, TEMP tmp); | |
| 7519 ins_cost(4*100+3*400); | |
| 7520 // Basic idea: lo(result) = lo(x_lo * y_lo) | |
| 7521 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi) | |
| 7522 format %{ "MOV $tmp,$src.lo\n\t" | |
| 7523 "IMUL $tmp,EDX\n\t" | |
| 7524 "MOV EDX,$src.hi\n\t" | |
| 7525 "IMUL EDX,EAX\n\t" | |
| 7526 "ADD $tmp,EDX\n\t" | |
| 7527 "MUL EDX:EAX,$src.lo\n\t" | |
| 7528 "ADD EDX,$tmp" %} | |
| 7529 ins_encode( long_multiply( dst, src, tmp ) ); | |
| 7530 ins_pipe( pipe_slow ); | |
| 7531 %} | |
| 7532 | |
|
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|
7533 // Multiply Register Long where the left operand's high 32 bits are zero |
|
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7534 instruct mulL_eReg_lhi0(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{ |
|
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|
7535 predicate(is_operand_hi32_zero(n->in(1))); |
|
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|
7536 match(Set dst (MulL dst src)); |
|
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|
7537 effect(KILL cr, TEMP tmp); |
|
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|
7538 ins_cost(2*100+2*400); |
|
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|
7539 // Basic idea: lo(result) = lo(x_lo * y_lo) |
|
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7540 // hi(result) = hi(x_lo * y_lo) + lo(x_lo * y_hi) where lo(x_hi * y_lo) = 0 because x_hi = 0 |
|
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|
7541 format %{ "MOV $tmp,$src.hi\n\t" |
|
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|
7542 "IMUL $tmp,EAX\n\t" |
|
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|
7543 "MUL EDX:EAX,$src.lo\n\t" |
|
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|
7544 "ADD EDX,$tmp" %} |
|
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|
7545 ins_encode %{ |
|
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|
7546 __ movl($tmp$$Register, HIGH_FROM_LOW($src$$Register)); |
|
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|
7547 __ imull($tmp$$Register, rax); |
|
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|
7548 __ mull($src$$Register); |
|
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|
7549 __ addl(rdx, $tmp$$Register); |
|
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|
7550 %} |
|
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changeset
|
7551 ins_pipe( pipe_slow ); |
|
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|
7552 %} |
|
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changeset
|
7553 |
|
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|
7554 // Multiply Register Long where the right operand's high 32 bits are zero |
|
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|
7555 instruct mulL_eReg_rhi0(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{ |
|
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|
7556 predicate(is_operand_hi32_zero(n->in(2))); |
|
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|
7557 match(Set dst (MulL dst src)); |
|
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|
7558 effect(KILL cr, TEMP tmp); |
|
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|
7559 ins_cost(2*100+2*400); |
|
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|
7560 // Basic idea: lo(result) = lo(x_lo * y_lo) |
|
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|
7561 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) where lo(x_lo * y_hi) = 0 because y_hi = 0 |
|
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|
7562 format %{ "MOV $tmp,$src.lo\n\t" |
|
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|
7563 "IMUL $tmp,EDX\n\t" |
|
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|
7564 "MUL EDX:EAX,$src.lo\n\t" |
|
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|
7565 "ADD EDX,$tmp" %} |
|
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|
7566 ins_encode %{ |
|
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|
7567 __ movl($tmp$$Register, $src$$Register); |
|
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|
7568 __ imull($tmp$$Register, rdx); |
|
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|
7569 __ mull($src$$Register); |
|
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|
7570 __ addl(rdx, $tmp$$Register); |
|
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|
7571 %} |
|
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diff
changeset
|
7572 ins_pipe( pipe_slow ); |
|
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changeset
|
7573 %} |
|
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diff
changeset
|
7574 |
|
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diff
changeset
|
7575 // Multiply Register Long where the left and the right operands' high 32 bits are zero |
|
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1137
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|
7576 instruct mulL_eReg_hi0(eADXRegL dst, eRegL src, eFlagsReg cr) %{ |
|
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|
7577 predicate(is_operand_hi32_zero(n->in(1)) && is_operand_hi32_zero(n->in(2))); |
|
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|
7578 match(Set dst (MulL dst src)); |
|
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changeset
|
7579 effect(KILL cr); |
|
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changeset
|
7580 ins_cost(1*400); |
|
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changeset
|
7581 // Basic idea: lo(result) = lo(x_lo * y_lo) |
|
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diff
changeset
|
7582 // hi(result) = hi(x_lo * y_lo) where lo(x_hi * y_lo) = 0 and lo(x_lo * y_hi) = 0 because x_hi = 0 and y_hi = 0 |
|
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changeset
|
7583 format %{ "MUL EDX:EAX,$src.lo\n\t" %} |
|
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changeset
|
7584 ins_encode %{ |
|
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|
7585 __ mull($src$$Register); |
|
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changeset
|
7586 %} |
|
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changeset
|
7587 ins_pipe( pipe_slow ); |
|
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changeset
|
7588 %} |
|
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|
7589 |
| 0 | 7590 // Multiply Register Long by small constant |
|
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|
7591 instruct mulL_eReg_con(eADXRegL dst, immL_127 src, rRegI tmp, eFlagsReg cr) %{ |
| 0 | 7592 match(Set dst (MulL dst src)); |
| 7593 effect(KILL cr, TEMP tmp); | |
| 7594 ins_cost(2*100+2*400); | |
| 7595 size(12); | |
| 7596 // Basic idea: lo(result) = lo(src * EAX) | |
| 7597 // hi(result) = hi(src * EAX) + lo(src * EDX) | |
| 7598 format %{ "IMUL $tmp,EDX,$src\n\t" | |
| 7599 "MOV EDX,$src\n\t" | |
| 7600 "MUL EDX\t# EDX*EAX -> EDX:EAX\n\t" | |
| 7601 "ADD EDX,$tmp" %} | |
| 7602 ins_encode( long_multiply_con( dst, src, tmp ) ); | |
| 7603 ins_pipe( pipe_slow ); | |
| 7604 %} | |
| 7605 | |
| 7606 // Integer DIV with Register | |
| 7607 instruct divI_eReg(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{ | |
| 7608 match(Set rax (DivI rax div)); | |
| 7609 effect(KILL rdx, KILL cr); | |
| 7610 size(26); | |
| 7611 ins_cost(30*100+10*100); | |
| 7612 format %{ "CMP EAX,0x80000000\n\t" | |
| 7613 "JNE,s normal\n\t" | |
| 7614 "XOR EDX,EDX\n\t" | |
| 7615 "CMP ECX,-1\n\t" | |
| 7616 "JE,s done\n" | |
| 7617 "normal: CDQ\n\t" | |
| 7618 "IDIV $div\n\t" | |
| 7619 "done:" %} | |
| 7620 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 7621 ins_encode( cdq_enc, OpcP, RegOpc(div) ); | |
| 7622 ins_pipe( ialu_reg_reg_alu0 ); | |
| 7623 %} | |
| 7624 | |
| 7625 // Divide Register Long | |
| 7626 instruct divL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{ | |
| 7627 match(Set dst (DivL src1 src2)); | |
| 7628 effect( KILL cr, KILL cx, KILL bx ); | |
| 7629 ins_cost(10000); | |
| 7630 format %{ "PUSH $src1.hi\n\t" | |
| 7631 "PUSH $src1.lo\n\t" | |
| 7632 "PUSH $src2.hi\n\t" | |
| 7633 "PUSH $src2.lo\n\t" | |
| 7634 "CALL SharedRuntime::ldiv\n\t" | |
| 7635 "ADD ESP,16" %} | |
| 7636 ins_encode( long_div(src1,src2) ); | |
| 7637 ins_pipe( pipe_slow ); | |
| 7638 %} | |
| 7639 | |
| 7640 // Integer DIVMOD with Register, both quotient and mod results | |
| 7641 instruct divModI_eReg_divmod(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{ | |
| 7642 match(DivModI rax div); | |
| 7643 effect(KILL cr); | |
| 7644 size(26); | |
| 7645 ins_cost(30*100+10*100); | |
| 7646 format %{ "CMP EAX,0x80000000\n\t" | |
| 7647 "JNE,s normal\n\t" | |
| 7648 "XOR EDX,EDX\n\t" | |
| 7649 "CMP ECX,-1\n\t" | |
| 7650 "JE,s done\n" | |
| 7651 "normal: CDQ\n\t" | |
| 7652 "IDIV $div\n\t" | |
| 7653 "done:" %} | |
| 7654 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 7655 ins_encode( cdq_enc, OpcP, RegOpc(div) ); | |
| 7656 ins_pipe( pipe_slow ); | |
| 7657 %} | |
| 7658 | |
| 7659 // Integer MOD with Register | |
| 7660 instruct modI_eReg(eDXRegI rdx, eAXRegI rax, eCXRegI div, eFlagsReg cr) %{ | |
| 7661 match(Set rdx (ModI rax div)); | |
| 7662 effect(KILL rax, KILL cr); | |
| 7663 | |
| 7664 size(26); | |
| 7665 ins_cost(300); | |
| 7666 format %{ "CDQ\n\t" | |
| 7667 "IDIV $div" %} | |
| 7668 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 7669 ins_encode( cdq_enc, OpcP, RegOpc(div) ); | |
| 7670 ins_pipe( ialu_reg_reg_alu0 ); | |
| 7671 %} | |
| 7672 | |
| 7673 // Remainder Register Long | |
| 7674 instruct modL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{ | |
| 7675 match(Set dst (ModL src1 src2)); | |
| 7676 effect( KILL cr, KILL cx, KILL bx ); | |
| 7677 ins_cost(10000); | |
| 7678 format %{ "PUSH $src1.hi\n\t" | |
| 7679 "PUSH $src1.lo\n\t" | |
| 7680 "PUSH $src2.hi\n\t" | |
| 7681 "PUSH $src2.lo\n\t" | |
| 7682 "CALL SharedRuntime::lrem\n\t" | |
| 7683 "ADD ESP,16" %} | |
| 7684 ins_encode( long_mod(src1,src2) ); | |
| 7685 ins_pipe( pipe_slow ); | |
| 7686 %} | |
| 7687 | |
|
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|
7688 // Divide Register Long (no special case since divisor != -1) |
|
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|
7689 instruct divL_eReg_imm32( eADXRegL dst, immL32 imm, rRegI tmp, rRegI tmp2, eFlagsReg cr ) %{ |
|
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|
7690 match(Set dst (DivL dst imm)); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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|
7691 effect( TEMP tmp, TEMP tmp2, KILL cr ); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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|
7692 ins_cost(1000); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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|
7693 format %{ "MOV $tmp,abs($imm) # ldiv EDX:EAX,$imm\n\t" |
| 1920 | 7694 "XOR $tmp2,$tmp2\n\t" |
|
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|
7695 "CMP $tmp,EDX\n\t" |
|
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|
7696 "JA,s fast\n\t" |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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|
7697 "MOV $tmp2,EAX\n\t" |
|
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6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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|
7698 "MOV EAX,EDX\n\t" |
| 1920 | 7699 "MOV EDX,0\n\t" |
| 7700 "JLE,s pos\n\t" | |
| 7701 "LNEG EAX : $tmp2\n\t" | |
| 7702 "DIV $tmp # unsigned division\n\t" | |
| 7703 "XCHG EAX,$tmp2\n\t" | |
| 7704 "DIV $tmp\n\t" | |
| 7705 "LNEG $tmp2 : EAX\n\t" | |
|
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|
7706 "JMP,s done\n" |
| 1920 | 7707 "pos:\n\t" |
| 7708 "DIV $tmp\n\t" | |
| 7709 "XCHG EAX,$tmp2\n" | |
|
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|
7710 "fast:\n\t" |
| 1920 | 7711 "DIV $tmp\n" |
|
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|
7712 "done:\n\t" |
| 1920 | 7713 "MOV EDX,$tmp2\n\t" |
|
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|
7714 "NEG EDX:EAX # if $imm < 0" %} |
|
ae065c367d93
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kvn
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|
7715 ins_encode %{ |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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|
7716 int con = (int)$imm$$constant; |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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|
7717 assert(con != 0 && con != -1 && con != min_jint, "wrong divisor"); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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|
7718 int pcon = (con > 0) ? con : -con; |
| 1920 | 7719 Label Lfast, Lpos, Ldone; |
|
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|
7720 |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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|
7721 __ movl($tmp$$Register, pcon); |
| 1920 | 7722 __ xorl($tmp2$$Register,$tmp2$$Register); |
|
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|
7723 __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register)); |
| 1920 | 7724 __ jccb(Assembler::above, Lfast); // result fits into 32 bit |
|
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|
7725 |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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|
7726 __ movl($tmp2$$Register, $dst$$Register); // save |
|
ae065c367d93
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kvn
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|
7727 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register)); |
| 1920 | 7728 __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags |
| 7729 __ jccb(Assembler::lessEqual, Lpos); // result is positive | |
| 7730 | |
| 7731 // Negative dividend. | |
| 7732 // convert value to positive to use unsigned division | |
| 7733 __ lneg($dst$$Register, $tmp2$$Register); | |
| 7734 __ divl($tmp$$Register); | |
|
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|
7735 __ xchgl($dst$$Register, $tmp2$$Register); |
| 1920 | 7736 __ divl($tmp$$Register); |
| 7737 // revert result back to negative | |
| 7738 __ lneg($tmp2$$Register, $dst$$Register); | |
|
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|
7739 __ jmpb(Ldone); |
|
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6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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|
7740 |
| 1920 | 7741 __ bind(Lpos); |
| 7742 __ divl($tmp$$Register); // Use unsigned division | |
| 7743 __ xchgl($dst$$Register, $tmp2$$Register); | |
| 7744 // Fallthrow for final divide, tmp2 has 32 bit hi result | |
| 7745 | |
|
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|
7746 __ bind(Lfast); |
| 1920 | 7747 // fast path: src is positive |
| 7748 __ divl($tmp$$Register); // Use unsigned division | |
|
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|
7749 |
|
ae065c367d93
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|
7750 __ bind(Ldone); |
| 1920 | 7751 __ movl(HIGH_FROM_LOW($dst$$Register),$tmp2$$Register); |
|
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|
7752 if (con < 0) { |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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|
7753 __ lneg(HIGH_FROM_LOW($dst$$Register), $dst$$Register); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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|
7754 } |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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diff
changeset
|
7755 %} |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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diff
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|
7756 ins_pipe( pipe_slow ); |
|
ae065c367d93
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kvn
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|
7757 %} |
|
ae065c367d93
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kvn
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diff
changeset
|
7758 |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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|
7759 // Remainder Register Long (remainder fit into 32 bits) |
|
6179
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|
7760 instruct modL_eReg_imm32( eADXRegL dst, immL32 imm, rRegI tmp, rRegI tmp2, eFlagsReg cr ) %{ |
|
1914
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|
7761 match(Set dst (ModL dst imm)); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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1748
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|
7762 effect( TEMP tmp, TEMP tmp2, KILL cr ); |
|
ae065c367d93
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kvn
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|
7763 ins_cost(1000); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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|
7764 format %{ "MOV $tmp,abs($imm) # lrem EDX:EAX,$imm\n\t" |
|
ae065c367d93
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kvn
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|
7765 "CMP $tmp,EDX\n\t" |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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|
7766 "JA,s fast\n\t" |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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1748
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|
7767 "MOV $tmp2,EAX\n\t" |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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|
7768 "MOV EAX,EDX\n\t" |
| 1920 | 7769 "MOV EDX,0\n\t" |
| 7770 "JLE,s pos\n\t" | |
| 7771 "LNEG EAX : $tmp2\n\t" | |
| 7772 "DIV $tmp # unsigned division\n\t" | |
| 7773 "MOV EAX,$tmp2\n\t" | |
| 7774 "DIV $tmp\n\t" | |
| 7775 "NEG EDX\n\t" | |
| 7776 "JMP,s done\n" | |
| 7777 "pos:\n\t" | |
| 7778 "DIV $tmp\n\t" | |
|
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|
7779 "MOV EAX,$tmp2\n" |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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|
7780 "fast:\n\t" |
| 1920 | 7781 "DIV $tmp\n" |
| 7782 "done:\n\t" | |
|
1914
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|
7783 "MOV EAX,EDX\n\t" |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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|
7784 "SAR EDX,31\n\t" %} |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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|
7785 ins_encode %{ |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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diff
changeset
|
7786 int con = (int)$imm$$constant; |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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1748
diff
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|
7787 assert(con != 0 && con != -1 && con != min_jint, "wrong divisor"); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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diff
changeset
|
7788 int pcon = (con > 0) ? con : -con; |
| 1920 | 7789 Label Lfast, Lpos, Ldone; |
|
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kvn
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diff
changeset
|
7790 |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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diff
changeset
|
7791 __ movl($tmp$$Register, pcon); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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changeset
|
7792 __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register)); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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|
7793 __ jccb(Assembler::above, Lfast); // src is positive and result fits into 32 bit |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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|
7794 |
|
ae065c367d93
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kvn
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changeset
|
7795 __ movl($tmp2$$Register, $dst$$Register); // save |
|
ae065c367d93
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kvn
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changeset
|
7796 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register)); |
| 1920 | 7797 __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags |
| 7798 __ jccb(Assembler::lessEqual, Lpos); // result is positive | |
| 7799 | |
| 7800 // Negative dividend. | |
| 7801 // convert value to positive to use unsigned division | |
| 7802 __ lneg($dst$$Register, $tmp2$$Register); | |
| 7803 __ divl($tmp$$Register); | |
| 7804 __ movl($dst$$Register, $tmp2$$Register); | |
| 7805 __ divl($tmp$$Register); | |
| 7806 // revert remainder back to negative | |
| 7807 __ negl(HIGH_FROM_LOW($dst$$Register)); | |
| 7808 __ jmpb(Ldone); | |
| 7809 | |
| 7810 __ bind(Lpos); | |
| 7811 __ divl($tmp$$Register); | |
|
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|
7812 __ movl($dst$$Register, $tmp2$$Register); |
|
ae065c367d93
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|
7813 |
|
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|
7814 __ bind(Lfast); |
| 1920 | 7815 // fast path: src is positive |
| 7816 __ divl($tmp$$Register); | |
| 7817 | |
| 7818 __ bind(Ldone); | |
|
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|
7819 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register)); |
|
ae065c367d93
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|
7820 __ sarl(HIGH_FROM_LOW($dst$$Register), 31); // result sign |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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changeset
|
7821 |
|
ae065c367d93
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kvn
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diff
changeset
|
7822 %} |
|
ae065c367d93
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changeset
|
7823 ins_pipe( pipe_slow ); |
|
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|
7824 %} |
|
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|
7825 |
| 0 | 7826 // Integer Shift Instructions |
| 7827 // Shift Left by one | |
|
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|
7828 instruct shlI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{ |
| 0 | 7829 match(Set dst (LShiftI dst shift)); |
| 7830 effect(KILL cr); | |
| 7831 | |
| 7832 size(2); | |
| 7833 format %{ "SHL $dst,$shift" %} | |
| 7834 opcode(0xD1, 0x4); /* D1 /4 */ | |
| 7835 ins_encode( OpcP, RegOpc( dst ) ); | |
| 7836 ins_pipe( ialu_reg ); | |
| 7837 %} | |
| 7838 | |
| 7839 // Shift Left by 8-bit immediate | |
|
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|
7840 instruct salI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{ |
| 0 | 7841 match(Set dst (LShiftI dst shift)); |
| 7842 effect(KILL cr); | |
| 7843 | |
| 7844 size(3); | |
| 7845 format %{ "SHL $dst,$shift" %} | |
| 7846 opcode(0xC1, 0x4); /* C1 /4 ib */ | |
| 7847 ins_encode( RegOpcImm( dst, shift) ); | |
| 7848 ins_pipe( ialu_reg ); | |
| 7849 %} | |
| 7850 | |
| 7851 // Shift Left by variable | |
|
6179
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changeset
|
7852 instruct salI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{ |
| 0 | 7853 match(Set dst (LShiftI dst shift)); |
| 7854 effect(KILL cr); | |
| 7855 | |
| 7856 size(2); | |
| 7857 format %{ "SHL $dst,$shift" %} | |
| 7858 opcode(0xD3, 0x4); /* D3 /4 */ | |
| 7859 ins_encode( OpcP, RegOpc( dst ) ); | |
| 7860 ins_pipe( ialu_reg_reg ); | |
| 7861 %} | |
| 7862 | |
| 7863 // Arithmetic shift right by one | |
|
6179
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changeset
|
7864 instruct sarI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{ |
| 0 | 7865 match(Set dst (RShiftI dst shift)); |
| 7866 effect(KILL cr); | |
| 7867 | |
| 7868 size(2); | |
| 7869 format %{ "SAR $dst,$shift" %} | |
| 7870 opcode(0xD1, 0x7); /* D1 /7 */ | |
| 7871 ins_encode( OpcP, RegOpc( dst ) ); | |
| 7872 ins_pipe( ialu_reg ); | |
| 7873 %} | |
| 7874 | |
| 7875 // Arithmetic shift right by one | |
| 7876 instruct sarI_mem_1(memory dst, immI1 shift, eFlagsReg cr) %{ | |
| 7877 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift))); | |
| 7878 effect(KILL cr); | |
| 7879 format %{ "SAR $dst,$shift" %} | |
| 7880 opcode(0xD1, 0x7); /* D1 /7 */ | |
| 7881 ins_encode( OpcP, RMopc_Mem(secondary,dst) ); | |
| 7882 ins_pipe( ialu_mem_imm ); | |
| 7883 %} | |
| 7884 | |
| 7885 // Arithmetic Shift Right by 8-bit immediate | |
|
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|
7886 instruct sarI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{ |
| 0 | 7887 match(Set dst (RShiftI dst shift)); |
| 7888 effect(KILL cr); | |
| 7889 | |
| 7890 size(3); | |
| 7891 format %{ "SAR $dst,$shift" %} | |
| 7892 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 7893 ins_encode( RegOpcImm( dst, shift ) ); | |
| 7894 ins_pipe( ialu_mem_imm ); | |
| 7895 %} | |
| 7896 | |
| 7897 // Arithmetic Shift Right by 8-bit immediate | |
| 7898 instruct sarI_mem_imm(memory dst, immI8 shift, eFlagsReg cr) %{ | |
| 7899 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift))); | |
| 7900 effect(KILL cr); | |
| 7901 | |
| 7902 format %{ "SAR $dst,$shift" %} | |
| 7903 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 7904 ins_encode( OpcP, RMopc_Mem(secondary, dst ), Con8or32( shift ) ); | |
| 7905 ins_pipe( ialu_mem_imm ); | |
| 7906 %} | |
| 7907 | |
| 7908 // Arithmetic Shift Right by variable | |
|
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|
7909 instruct sarI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{ |
| 0 | 7910 match(Set dst (RShiftI dst shift)); |
| 7911 effect(KILL cr); | |
| 7912 | |
| 7913 size(2); | |
| 7914 format %{ "SAR $dst,$shift" %} | |
| 7915 opcode(0xD3, 0x7); /* D3 /7 */ | |
| 7916 ins_encode( OpcP, RegOpc( dst ) ); | |
| 7917 ins_pipe( ialu_reg_reg ); | |
| 7918 %} | |
| 7919 | |
| 7920 // Logical shift right by one | |
|
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|
7921 instruct shrI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{ |
| 0 | 7922 match(Set dst (URShiftI dst shift)); |
| 7923 effect(KILL cr); | |
| 7924 | |
| 7925 size(2); | |
| 7926 format %{ "SHR $dst,$shift" %} | |
| 7927 opcode(0xD1, 0x5); /* D1 /5 */ | |
| 7928 ins_encode( OpcP, RegOpc( dst ) ); | |
| 7929 ins_pipe( ialu_reg ); | |
| 7930 %} | |
| 7931 | |
| 7932 // Logical Shift Right by 8-bit immediate | |
|
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|
7933 instruct shrI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{ |
| 0 | 7934 match(Set dst (URShiftI dst shift)); |
| 7935 effect(KILL cr); | |
| 7936 | |
| 7937 size(3); | |
| 7938 format %{ "SHR $dst,$shift" %} | |
| 7939 opcode(0xC1, 0x5); /* C1 /5 ib */ | |
| 7940 ins_encode( RegOpcImm( dst, shift) ); | |
| 7941 ins_pipe( ialu_reg ); | |
| 7942 %} | |
| 7943 | |
|
420
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6462850: generate biased locking code in C2 ideal graph
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diff
changeset
|
7944 |
| 0 | 7945 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24. |
| 7946 // This idiom is used by the compiler for the i2b bytecode. | |
|
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|
7947 instruct i2b(rRegI dst, xRegI src, immI_24 twentyfour) %{ |
| 0 | 7948 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour)); |
| 7949 | |
| 7950 size(3); | |
| 7951 format %{ "MOVSX $dst,$src :8" %} | |
| 785 | 7952 ins_encode %{ |
| 7953 __ movsbl($dst$$Register, $src$$Register); | |
| 7954 %} | |
| 7955 ins_pipe(ialu_reg_reg); | |
| 0 | 7956 %} |
| 7957 | |
| 7958 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16. | |
| 7959 // This idiom is used by the compiler the i2s bytecode. | |
|
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|
7960 instruct i2s(rRegI dst, xRegI src, immI_16 sixteen) %{ |
| 0 | 7961 match(Set dst (RShiftI (LShiftI src sixteen) sixteen)); |
| 7962 | |
| 7963 size(3); | |
| 7964 format %{ "MOVSX $dst,$src :16" %} | |
| 785 | 7965 ins_encode %{ |
| 7966 __ movswl($dst$$Register, $src$$Register); | |
| 7967 %} | |
| 7968 ins_pipe(ialu_reg_reg); | |
| 0 | 7969 %} |
| 7970 | |
| 7971 | |
| 7972 // Logical Shift Right by variable | |
|
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|
7973 instruct shrI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{ |
| 0 | 7974 match(Set dst (URShiftI dst shift)); |
| 7975 effect(KILL cr); | |
| 7976 | |
| 7977 size(2); | |
| 7978 format %{ "SHR $dst,$shift" %} | |
| 7979 opcode(0xD3, 0x5); /* D3 /5 */ | |
| 7980 ins_encode( OpcP, RegOpc( dst ) ); | |
| 7981 ins_pipe( ialu_reg_reg ); | |
| 7982 %} | |
| 7983 | |
| 7984 | |
| 7985 //----------Logical Instructions----------------------------------------------- | |
| 7986 //----------Integer Logical Instructions--------------------------------------- | |
| 7987 // And Instructions | |
| 7988 // And Register with Register | |
|
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|
7989 instruct andI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 7990 match(Set dst (AndI dst src)); |
| 7991 effect(KILL cr); | |
| 7992 | |
| 7993 size(2); | |
| 7994 format %{ "AND $dst,$src" %} | |
| 7995 opcode(0x23); | |
| 7996 ins_encode( OpcP, RegReg( dst, src) ); | |
| 7997 ins_pipe( ialu_reg_reg ); | |
| 7998 %} | |
| 7999 | |
| 8000 // And Register with Immediate | |
|
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|
8001 instruct andI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{ |
| 0 | 8002 match(Set dst (AndI dst src)); |
| 8003 effect(KILL cr); | |
| 8004 | |
| 8005 format %{ "AND $dst,$src" %} | |
| 8006 opcode(0x81,0x04); /* Opcode 81 /4 */ | |
| 8007 // ins_encode( RegImm( dst, src) ); | |
| 8008 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); | |
| 8009 ins_pipe( ialu_reg ); | |
| 8010 %} | |
| 8011 | |
| 8012 // And Register with Memory | |
|
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|
8013 instruct andI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{ |
| 0 | 8014 match(Set dst (AndI dst (LoadI src))); |
| 8015 effect(KILL cr); | |
| 8016 | |
| 8017 ins_cost(125); | |
| 8018 format %{ "AND $dst,$src" %} | |
| 8019 opcode(0x23); | |
| 8020 ins_encode( OpcP, RegMem( dst, src) ); | |
| 8021 ins_pipe( ialu_reg_mem ); | |
| 8022 %} | |
| 8023 | |
| 8024 // And Memory with Register | |
|
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|
8025 instruct andI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 8026 match(Set dst (StoreI dst (AndI (LoadI dst) src))); |
| 8027 effect(KILL cr); | |
| 8028 | |
| 8029 ins_cost(150); | |
| 8030 format %{ "AND $dst,$src" %} | |
| 8031 opcode(0x21); /* Opcode 21 /r */ | |
| 8032 ins_encode( OpcP, RegMem( src, dst ) ); | |
| 8033 ins_pipe( ialu_mem_reg ); | |
| 8034 %} | |
| 8035 | |
| 8036 // And Memory with Immediate | |
| 8037 instruct andI_mem_imm(memory dst, immI src, eFlagsReg cr) %{ | |
| 8038 match(Set dst (StoreI dst (AndI (LoadI dst) src))); | |
| 8039 effect(KILL cr); | |
| 8040 | |
| 8041 ins_cost(125); | |
| 8042 format %{ "AND $dst,$src" %} | |
| 8043 opcode(0x81, 0x4); /* Opcode 81 /4 id */ | |
| 8044 // ins_encode( MemImm( dst, src) ); | |
| 8045 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) ); | |
| 8046 ins_pipe( ialu_mem_imm ); | |
| 8047 %} | |
| 8048 | |
|
17729
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|
8049 // BMI1 instructions |
|
8a8ff6b577ed
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|
8050 instruct andnI_rReg_rReg_rReg(rRegI dst, rRegI src1, rRegI src2, immI_M1 minus_1, eFlagsReg cr) %{ |
|
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|
8051 match(Set dst (AndI (XorI src1 minus_1) src2)); |
|
8a8ff6b577ed
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|
8052 predicate(UseBMI1Instructions); |
|
8a8ff6b577ed
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changeset
|
8053 effect(KILL cr); |
|
8a8ff6b577ed
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|
8054 |
|
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|
8055 format %{ "ANDNL $dst, $src1, $src2" %} |
|
8a8ff6b577ed
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|
8056 |
|
8a8ff6b577ed
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changeset
|
8057 ins_encode %{ |
|
8a8ff6b577ed
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|
8058 __ andnl($dst$$Register, $src1$$Register, $src2$$Register); |
|
8a8ff6b577ed
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|
8059 %} |
|
8a8ff6b577ed
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changeset
|
8060 ins_pipe(ialu_reg); |
|
8a8ff6b577ed
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|
8061 %} |
|
8a8ff6b577ed
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changeset
|
8062 |
|
8a8ff6b577ed
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changeset
|
8063 instruct andnI_rReg_rReg_mem(rRegI dst, rRegI src1, memory src2, immI_M1 minus_1, eFlagsReg cr) %{ |
|
8a8ff6b577ed
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|
8064 match(Set dst (AndI (XorI src1 minus_1) (LoadI src2) )); |
|
8a8ff6b577ed
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changeset
|
8065 predicate(UseBMI1Instructions); |
|
8a8ff6b577ed
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changeset
|
8066 effect(KILL cr); |
|
8a8ff6b577ed
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changeset
|
8067 |
|
8a8ff6b577ed
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changeset
|
8068 ins_cost(125); |
|
8a8ff6b577ed
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changeset
|
8069 format %{ "ANDNL $dst, $src1, $src2" %} |
|
8a8ff6b577ed
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changeset
|
8070 |
|
8a8ff6b577ed
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changeset
|
8071 ins_encode %{ |
|
8a8ff6b577ed
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|
8072 __ andnl($dst$$Register, $src1$$Register, $src2$$Address); |
|
8a8ff6b577ed
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|
8073 %} |
|
8a8ff6b577ed
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changeset
|
8074 ins_pipe(ialu_reg_mem); |
|
8a8ff6b577ed
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changeset
|
8075 %} |
|
8a8ff6b577ed
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changeset
|
8076 |
|
8a8ff6b577ed
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changeset
|
8077 instruct blsiI_rReg_rReg(rRegI dst, rRegI src, immI0 imm_zero, eFlagsReg cr) %{ |
|
8a8ff6b577ed
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|
8078 match(Set dst (AndI (SubI imm_zero src) src)); |
|
8a8ff6b577ed
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diff
changeset
|
8079 predicate(UseBMI1Instructions); |
|
8a8ff6b577ed
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diff
changeset
|
8080 effect(KILL cr); |
|
8a8ff6b577ed
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changeset
|
8081 |
|
8a8ff6b577ed
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changeset
|
8082 format %{ "BLSIL $dst, $src" %} |
|
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changeset
|
8083 |
|
8a8ff6b577ed
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changeset
|
8084 ins_encode %{ |
|
8a8ff6b577ed
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changeset
|
8085 __ blsil($dst$$Register, $src$$Register); |
|
8a8ff6b577ed
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changeset
|
8086 %} |
|
8a8ff6b577ed
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changeset
|
8087 ins_pipe(ialu_reg); |
|
8a8ff6b577ed
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changeset
|
8088 %} |
|
8a8ff6b577ed
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changeset
|
8089 |
|
8a8ff6b577ed
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changeset
|
8090 instruct blsiI_rReg_mem(rRegI dst, memory src, immI0 imm_zero, eFlagsReg cr) %{ |
|
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|
8091 match(Set dst (AndI (SubI imm_zero (LoadI src) ) (LoadI src) )); |
|
8a8ff6b577ed
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changeset
|
8092 predicate(UseBMI1Instructions); |
|
8a8ff6b577ed
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changeset
|
8093 effect(KILL cr); |
|
8a8ff6b577ed
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changeset
|
8094 |
|
8a8ff6b577ed
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changeset
|
8095 ins_cost(125); |
|
8a8ff6b577ed
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changeset
|
8096 format %{ "BLSIL $dst, $src" %} |
|
8a8ff6b577ed
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changeset
|
8097 |
|
8a8ff6b577ed
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changeset
|
8098 ins_encode %{ |
|
8a8ff6b577ed
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changeset
|
8099 __ blsil($dst$$Register, $src$$Address); |
|
8a8ff6b577ed
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changeset
|
8100 %} |
|
8a8ff6b577ed
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changeset
|
8101 ins_pipe(ialu_reg_mem); |
|
8a8ff6b577ed
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|
8102 %} |
|
8a8ff6b577ed
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changeset
|
8103 |
|
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|
8104 instruct blsmskI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, eFlagsReg cr) |
|
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|
8105 %{ |
|
8a8ff6b577ed
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|
8106 match(Set dst (XorI (AddI src minus_1) src)); |
|
8a8ff6b577ed
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changeset
|
8107 predicate(UseBMI1Instructions); |
|
8a8ff6b577ed
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changeset
|
8108 effect(KILL cr); |
|
8a8ff6b577ed
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changeset
|
8109 |
|
8a8ff6b577ed
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changeset
|
8110 format %{ "BLSMSKL $dst, $src" %} |
|
8a8ff6b577ed
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changeset
|
8111 |
|
8a8ff6b577ed
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changeset
|
8112 ins_encode %{ |
|
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changeset
|
8113 __ blsmskl($dst$$Register, $src$$Register); |
|
8a8ff6b577ed
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changeset
|
8114 %} |
|
8a8ff6b577ed
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changeset
|
8115 |
|
8a8ff6b577ed
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parents:
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changeset
|
8116 ins_pipe(ialu_reg); |
|
8a8ff6b577ed
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changeset
|
8117 %} |
|
8a8ff6b577ed
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iveresov
parents:
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changeset
|
8118 |
|
8a8ff6b577ed
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changeset
|
8119 instruct blsmskI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, eFlagsReg cr) |
|
8a8ff6b577ed
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changeset
|
8120 %{ |
|
8a8ff6b577ed
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changeset
|
8121 match(Set dst (XorI (AddI (LoadI src) minus_1) (LoadI src) )); |
|
8a8ff6b577ed
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iveresov
parents:
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changeset
|
8122 predicate(UseBMI1Instructions); |
|
8a8ff6b577ed
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changeset
|
8123 effect(KILL cr); |
|
8a8ff6b577ed
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diff
changeset
|
8124 |
|
8a8ff6b577ed
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changeset
|
8125 ins_cost(125); |
|
8a8ff6b577ed
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changeset
|
8126 format %{ "BLSMSKL $dst, $src" %} |
|
8a8ff6b577ed
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changeset
|
8127 |
|
8a8ff6b577ed
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|
8128 ins_encode %{ |
|
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|
8129 __ blsmskl($dst$$Register, $src$$Address); |
|
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|
8130 %} |
|
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|
8131 |
|
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|
8132 ins_pipe(ialu_reg_mem); |
|
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|
8133 %} |
|
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|
8134 |
|
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|
8135 instruct blsrI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, eFlagsReg cr) |
|
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|
8136 %{ |
|
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|
8137 match(Set dst (AndI (AddI src minus_1) src) ); |
|
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|
8138 predicate(UseBMI1Instructions); |
|
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|
8139 effect(KILL cr); |
|
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|
8140 |
|
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|
8141 format %{ "BLSRL $dst, $src" %} |
|
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|
8142 |
|
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|
8143 ins_encode %{ |
|
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|
8144 __ blsrl($dst$$Register, $src$$Register); |
|
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|
8145 %} |
|
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|
8146 |
|
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|
8147 ins_pipe(ialu_reg); |
|
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|
8148 %} |
|
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|
8149 |
|
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|
8150 instruct blsrI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, eFlagsReg cr) |
|
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|
8151 %{ |
|
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8152 match(Set dst (AndI (AddI (LoadI src) minus_1) (LoadI src) )); |
|
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|
8153 predicate(UseBMI1Instructions); |
|
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|
8154 effect(KILL cr); |
|
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|
8155 |
|
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|
8156 ins_cost(125); |
|
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|
8157 format %{ "BLSRL $dst, $src" %} |
|
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|
8158 |
|
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|
8159 ins_encode %{ |
|
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|
8160 __ blsrl($dst$$Register, $src$$Address); |
|
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|
8161 %} |
|
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|
8162 |
|
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|
8163 ins_pipe(ialu_reg_mem); |
|
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|
8164 %} |
|
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|
8165 |
| 0 | 8166 // Or Instructions |
| 8167 // Or Register with Register | |
|
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8168 instruct orI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 8169 match(Set dst (OrI dst src)); |
| 8170 effect(KILL cr); | |
| 8171 | |
| 8172 size(2); | |
| 8173 format %{ "OR $dst,$src" %} | |
| 8174 opcode(0x0B); | |
| 8175 ins_encode( OpcP, RegReg( dst, src) ); | |
| 8176 ins_pipe( ialu_reg_reg ); | |
| 8177 %} | |
| 8178 | |
|
6179
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8179 instruct orI_eReg_castP2X(rRegI dst, eRegP src, eFlagsReg cr) %{ |
|
420
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|
8180 match(Set dst (OrI dst (CastP2X src))); |
|
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|
8181 effect(KILL cr); |
|
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changeset
|
8182 |
|
a1980da045cc
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|
8183 size(2); |
|
a1980da045cc
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changeset
|
8184 format %{ "OR $dst,$src" %} |
|
a1980da045cc
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415
diff
changeset
|
8185 opcode(0x0B); |
|
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|
8186 ins_encode( OpcP, RegReg( dst, src) ); |
|
a1980da045cc
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|
8187 ins_pipe( ialu_reg_reg ); |
|
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415
diff
changeset
|
8188 %} |
|
a1980da045cc
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415
diff
changeset
|
8189 |
|
a1980da045cc
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diff
changeset
|
8190 |
| 0 | 8191 // Or Register with Immediate |
|
6179
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|
8192 instruct orI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{ |
| 0 | 8193 match(Set dst (OrI dst src)); |
| 8194 effect(KILL cr); | |
| 8195 | |
| 8196 format %{ "OR $dst,$src" %} | |
| 8197 opcode(0x81,0x01); /* Opcode 81 /1 id */ | |
| 8198 // ins_encode( RegImm( dst, src) ); | |
| 8199 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); | |
| 8200 ins_pipe( ialu_reg ); | |
| 8201 %} | |
| 8202 | |
| 8203 // Or Register with Memory | |
|
6179
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|
8204 instruct orI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{ |
| 0 | 8205 match(Set dst (OrI dst (LoadI src))); |
| 8206 effect(KILL cr); | |
| 8207 | |
| 8208 ins_cost(125); | |
| 8209 format %{ "OR $dst,$src" %} | |
| 8210 opcode(0x0B); | |
| 8211 ins_encode( OpcP, RegMem( dst, src) ); | |
| 8212 ins_pipe( ialu_reg_mem ); | |
| 8213 %} | |
| 8214 | |
| 8215 // Or Memory with Register | |
|
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|
8216 instruct orI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 8217 match(Set dst (StoreI dst (OrI (LoadI dst) src))); |
| 8218 effect(KILL cr); | |
| 8219 | |
| 8220 ins_cost(150); | |
| 8221 format %{ "OR $dst,$src" %} | |
| 8222 opcode(0x09); /* Opcode 09 /r */ | |
| 8223 ins_encode( OpcP, RegMem( src, dst ) ); | |
| 8224 ins_pipe( ialu_mem_reg ); | |
| 8225 %} | |
| 8226 | |
| 8227 // Or Memory with Immediate | |
| 8228 instruct orI_mem_imm(memory dst, immI src, eFlagsReg cr) %{ | |
| 8229 match(Set dst (StoreI dst (OrI (LoadI dst) src))); | |
| 8230 effect(KILL cr); | |
| 8231 | |
| 8232 ins_cost(125); | |
| 8233 format %{ "OR $dst,$src" %} | |
| 8234 opcode(0x81,0x1); /* Opcode 81 /1 id */ | |
| 8235 // ins_encode( MemImm( dst, src) ); | |
| 8236 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) ); | |
| 8237 ins_pipe( ialu_mem_imm ); | |
| 8238 %} | |
| 8239 | |
| 8240 // ROL/ROR | |
| 8241 // ROL expand | |
|
6179
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|
8242 instruct rolI_eReg_imm1(rRegI dst, immI1 shift, eFlagsReg cr) %{ |
| 0 | 8243 effect(USE_DEF dst, USE shift, KILL cr); |
| 8244 | |
| 8245 format %{ "ROL $dst, $shift" %} | |
| 8246 opcode(0xD1, 0x0); /* Opcode D1 /0 */ | |
| 8247 ins_encode( OpcP, RegOpc( dst )); | |
| 8248 ins_pipe( ialu_reg ); | |
| 8249 %} | |
| 8250 | |
|
6179
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|
8251 instruct rolI_eReg_imm8(rRegI dst, immI8 shift, eFlagsReg cr) %{ |
| 0 | 8252 effect(USE_DEF dst, USE shift, KILL cr); |
| 8253 | |
| 8254 format %{ "ROL $dst, $shift" %} | |
| 8255 opcode(0xC1, 0x0); /*Opcode /C1 /0 */ | |
| 8256 ins_encode( RegOpcImm(dst, shift) ); | |
| 8257 ins_pipe(ialu_reg); | |
| 8258 %} | |
| 8259 | |
| 8260 instruct rolI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr) %{ | |
| 8261 effect(USE_DEF dst, USE shift, KILL cr); | |
| 8262 | |
| 8263 format %{ "ROL $dst, $shift" %} | |
| 8264 opcode(0xD3, 0x0); /* Opcode D3 /0 */ | |
| 8265 ins_encode(OpcP, RegOpc(dst)); | |
| 8266 ins_pipe( ialu_reg_reg ); | |
| 8267 %} | |
| 8268 // end of ROL expand | |
| 8269 | |
| 8270 // ROL 32bit by one once | |
|
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|
8271 instruct rolI_eReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, eFlagsReg cr) %{ |
| 0 | 8272 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift))); |
| 8273 | |
| 8274 expand %{ | |
| 8275 rolI_eReg_imm1(dst, lshift, cr); | |
| 8276 %} | |
| 8277 %} | |
| 8278 | |
| 8279 // ROL 32bit var by imm8 once | |
|
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|
8280 instruct rolI_eReg_i8(rRegI dst, immI8 lshift, immI8 rshift, eFlagsReg cr) %{ |
| 0 | 8281 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); |
| 8282 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift))); | |
| 8283 | |
| 8284 expand %{ | |
| 8285 rolI_eReg_imm8(dst, lshift, cr); | |
| 8286 %} | |
| 8287 %} | |
| 8288 | |
| 8289 // ROL 32bit var by var once | |
| 8290 instruct rolI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{ | |
| 8291 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift)))); | |
| 8292 | |
| 8293 expand %{ | |
| 8294 rolI_eReg_CL(dst, shift, cr); | |
| 8295 %} | |
| 8296 %} | |
| 8297 | |
| 8298 // ROL 32bit var by var once | |
| 8299 instruct rolI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{ | |
| 8300 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift)))); | |
| 8301 | |
| 8302 expand %{ | |
| 8303 rolI_eReg_CL(dst, shift, cr); | |
| 8304 %} | |
| 8305 %} | |
| 8306 | |
| 8307 // ROR expand | |
|
6179
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|
8308 instruct rorI_eReg_imm1(rRegI dst, immI1 shift, eFlagsReg cr) %{ |
| 0 | 8309 effect(USE_DEF dst, USE shift, KILL cr); |
| 8310 | |
| 8311 format %{ "ROR $dst, $shift" %} | |
| 8312 opcode(0xD1,0x1); /* Opcode D1 /1 */ | |
| 8313 ins_encode( OpcP, RegOpc( dst ) ); | |
| 8314 ins_pipe( ialu_reg ); | |
| 8315 %} | |
| 8316 | |
|
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|
8317 instruct rorI_eReg_imm8(rRegI dst, immI8 shift, eFlagsReg cr) %{ |
| 0 | 8318 effect (USE_DEF dst, USE shift, KILL cr); |
| 8319 | |
| 8320 format %{ "ROR $dst, $shift" %} | |
| 8321 opcode(0xC1, 0x1); /* Opcode /C1 /1 ib */ | |
| 8322 ins_encode( RegOpcImm(dst, shift) ); | |
| 8323 ins_pipe( ialu_reg ); | |
| 8324 %} | |
| 8325 | |
| 8326 instruct rorI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr)%{ | |
| 8327 effect(USE_DEF dst, USE shift, KILL cr); | |
| 8328 | |
| 8329 format %{ "ROR $dst, $shift" %} | |
| 8330 opcode(0xD3, 0x1); /* Opcode D3 /1 */ | |
| 8331 ins_encode(OpcP, RegOpc(dst)); | |
| 8332 ins_pipe( ialu_reg_reg ); | |
| 8333 %} | |
| 8334 // end of ROR expand | |
| 8335 | |
| 8336 // ROR right once | |
|
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|
8337 instruct rorI_eReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, eFlagsReg cr) %{ |
| 0 | 8338 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift))); |
| 8339 | |
| 8340 expand %{ | |
| 8341 rorI_eReg_imm1(dst, rshift, cr); | |
| 8342 %} | |
| 8343 %} | |
| 8344 | |
| 8345 // ROR 32bit by immI8 once | |
|
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changeset
|
8346 instruct rorI_eReg_i8(rRegI dst, immI8 rshift, immI8 lshift, eFlagsReg cr) %{ |
| 0 | 8347 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); |
| 8348 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift))); | |
| 8349 | |
| 8350 expand %{ | |
| 8351 rorI_eReg_imm8(dst, rshift, cr); | |
| 8352 %} | |
| 8353 %} | |
| 8354 | |
| 8355 // ROR 32bit var by var once | |
| 8356 instruct rorI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{ | |
| 8357 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift)))); | |
| 8358 | |
| 8359 expand %{ | |
| 8360 rorI_eReg_CL(dst, shift, cr); | |
| 8361 %} | |
| 8362 %} | |
| 8363 | |
| 8364 // ROR 32bit var by var once | |
| 8365 instruct rorI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{ | |
| 8366 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift)))); | |
| 8367 | |
| 8368 expand %{ | |
| 8369 rorI_eReg_CL(dst, shift, cr); | |
| 8370 %} | |
| 8371 %} | |
| 8372 | |
| 8373 // Xor Instructions | |
| 8374 // Xor Register with Register | |
|
6179
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|
8375 instruct xorI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 8376 match(Set dst (XorI dst src)); |
| 8377 effect(KILL cr); | |
| 8378 | |
| 8379 size(2); | |
| 8380 format %{ "XOR $dst,$src" %} | |
| 8381 opcode(0x33); | |
| 8382 ins_encode( OpcP, RegReg( dst, src) ); | |
| 8383 ins_pipe( ialu_reg_reg ); | |
| 8384 %} | |
| 8385 | |
| 403 | 8386 // Xor Register with Immediate -1 |
|
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|
8387 instruct xorI_eReg_im1(rRegI dst, immI_M1 imm) %{ |
| 403 | 8388 match(Set dst (XorI dst imm)); |
| 8389 | |
| 8390 size(2); | |
| 8391 format %{ "NOT $dst" %} | |
| 8392 ins_encode %{ | |
| 8393 __ notl($dst$$Register); | |
| 8394 %} | |
| 8395 ins_pipe( ialu_reg ); | |
| 8396 %} | |
| 8397 | |
| 0 | 8398 // Xor Register with Immediate |
|
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|
8399 instruct xorI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{ |
| 0 | 8400 match(Set dst (XorI dst src)); |
| 8401 effect(KILL cr); | |
| 8402 | |
| 8403 format %{ "XOR $dst,$src" %} | |
| 8404 opcode(0x81,0x06); /* Opcode 81 /6 id */ | |
| 8405 // ins_encode( RegImm( dst, src) ); | |
| 8406 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); | |
| 8407 ins_pipe( ialu_reg ); | |
| 8408 %} | |
| 8409 | |
| 8410 // Xor Register with Memory | |
|
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|
8411 instruct xorI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{ |
| 0 | 8412 match(Set dst (XorI dst (LoadI src))); |
| 8413 effect(KILL cr); | |
| 8414 | |
| 8415 ins_cost(125); | |
| 8416 format %{ "XOR $dst,$src" %} | |
| 8417 opcode(0x33); | |
| 8418 ins_encode( OpcP, RegMem(dst, src) ); | |
| 8419 ins_pipe( ialu_reg_mem ); | |
| 8420 %} | |
| 8421 | |
| 8422 // Xor Memory with Register | |
|
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8423 instruct xorI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 8424 match(Set dst (StoreI dst (XorI (LoadI dst) src))); |
| 8425 effect(KILL cr); | |
| 8426 | |
| 8427 ins_cost(150); | |
| 8428 format %{ "XOR $dst,$src" %} | |
| 8429 opcode(0x31); /* Opcode 31 /r */ | |
| 8430 ins_encode( OpcP, RegMem( src, dst ) ); | |
| 8431 ins_pipe( ialu_mem_reg ); | |
| 8432 %} | |
| 8433 | |
| 8434 // Xor Memory with Immediate | |
| 8435 instruct xorI_mem_imm(memory dst, immI src, eFlagsReg cr) %{ | |
| 8436 match(Set dst (StoreI dst (XorI (LoadI dst) src))); | |
| 8437 effect(KILL cr); | |
| 8438 | |
| 8439 ins_cost(125); | |
| 8440 format %{ "XOR $dst,$src" %} | |
| 8441 opcode(0x81,0x6); /* Opcode 81 /6 id */ | |
| 8442 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) ); | |
| 8443 ins_pipe( ialu_mem_imm ); | |
| 8444 %} | |
| 8445 | |
| 8446 //----------Convert Int to Boolean--------------------------------------------- | |
| 8447 | |
|
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|
8448 instruct movI_nocopy(rRegI dst, rRegI src) %{ |
| 0 | 8449 effect( DEF dst, USE src ); |
| 8450 format %{ "MOV $dst,$src" %} | |
| 8451 ins_encode( enc_Copy( dst, src) ); | |
| 8452 ins_pipe( ialu_reg_reg ); | |
| 8453 %} | |
| 8454 | |
|
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|
8455 instruct ci2b( rRegI dst, rRegI src, eFlagsReg cr ) %{ |
| 0 | 8456 effect( USE_DEF dst, USE src, KILL cr ); |
| 8457 | |
| 8458 size(4); | |
| 8459 format %{ "NEG $dst\n\t" | |
| 8460 "ADC $dst,$src" %} | |
| 8461 ins_encode( neg_reg(dst), | |
| 8462 OpcRegReg(0x13,dst,src) ); | |
| 8463 ins_pipe( ialu_reg_reg_long ); | |
| 8464 %} | |
| 8465 | |
|
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|
8466 instruct convI2B( rRegI dst, rRegI src, eFlagsReg cr ) %{ |
| 0 | 8467 match(Set dst (Conv2B src)); |
| 8468 | |
| 8469 expand %{ | |
| 8470 movI_nocopy(dst,src); | |
| 8471 ci2b(dst,src,cr); | |
| 8472 %} | |
| 8473 %} | |
| 8474 | |
|
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|
8475 instruct movP_nocopy(rRegI dst, eRegP src) %{ |
| 0 | 8476 effect( DEF dst, USE src ); |
| 8477 format %{ "MOV $dst,$src" %} | |
| 8478 ins_encode( enc_Copy( dst, src) ); | |
| 8479 ins_pipe( ialu_reg_reg ); | |
| 8480 %} | |
| 8481 | |
|
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|
8482 instruct cp2b( rRegI dst, eRegP src, eFlagsReg cr ) %{ |
| 0 | 8483 effect( USE_DEF dst, USE src, KILL cr ); |
| 8484 format %{ "NEG $dst\n\t" | |
| 8485 "ADC $dst,$src" %} | |
| 8486 ins_encode( neg_reg(dst), | |
| 8487 OpcRegReg(0x13,dst,src) ); | |
| 8488 ins_pipe( ialu_reg_reg_long ); | |
| 8489 %} | |
| 8490 | |
|
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|
8491 instruct convP2B( rRegI dst, eRegP src, eFlagsReg cr ) %{ |
| 0 | 8492 match(Set dst (Conv2B src)); |
| 8493 | |
| 8494 expand %{ | |
| 8495 movP_nocopy(dst,src); | |
| 8496 cp2b(dst,src,cr); | |
| 8497 %} | |
| 8498 %} | |
| 8499 | |
| 9154 | 8500 instruct cmpLTMask(eCXRegI dst, ncxRegI p, ncxRegI q, eFlagsReg cr) %{ |
| 0 | 8501 match(Set dst (CmpLTMask p q)); |
| 9154 | 8502 effect(KILL cr); |
| 0 | 8503 ins_cost(400); |
| 8504 | |
| 8505 // SETlt can only use low byte of EAX,EBX, ECX, or EDX as destination | |
| 8506 format %{ "XOR $dst,$dst\n\t" | |
| 8507 "CMP $p,$q\n\t" | |
| 8508 "SETlt $dst\n\t" | |
| 8509 "NEG $dst" %} | |
| 9154 | 8510 ins_encode %{ |
| 8511 Register Rp = $p$$Register; | |
| 8512 Register Rq = $q$$Register; | |
| 8513 Register Rd = $dst$$Register; | |
| 8514 Label done; | |
| 8515 __ xorl(Rd, Rd); | |
| 8516 __ cmpl(Rp, Rq); | |
| 8517 __ setb(Assembler::less, Rd); | |
| 8518 __ negl(Rd); | |
| 8519 %} | |
| 8520 | |
| 8521 ins_pipe(pipe_slow); | |
| 8522 %} | |
| 8523 | |
| 8524 instruct cmpLTMask0(rRegI dst, immI0 zero, eFlagsReg cr) %{ | |
| 0 | 8525 match(Set dst (CmpLTMask dst zero)); |
| 9154 | 8526 effect(DEF dst, KILL cr); |
| 0 | 8527 ins_cost(100); |
| 8528 | |
| 9154 | 8529 format %{ "SAR $dst,31\t# cmpLTMask0" %} |
| 8530 ins_encode %{ | |
| 8531 __ sarl($dst$$Register, 31); | |
| 8532 %} | |
| 8533 ins_pipe(ialu_reg); | |
| 8534 %} | |
| 8535 | |
| 8536 /* better to save a register than avoid a branch */ | |
| 8537 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y, eFlagsReg cr) %{ | |
| 0 | 8538 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))); |
| 9154 | 8539 effect(KILL cr); |
| 0 | 8540 ins_cost(400); |
| 9154 | 8541 format %{ "SUB $p,$q\t# cadd_cmpLTMask\n\t" |
| 8542 "JGE done\n\t" | |
| 8543 "ADD $p,$y\n" | |
| 8544 "done: " %} | |
| 8545 ins_encode %{ | |
| 8546 Register Rp = $p$$Register; | |
| 8547 Register Rq = $q$$Register; | |
| 8548 Register Ry = $y$$Register; | |
| 8549 Label done; | |
| 8550 __ subl(Rp, Rq); | |
| 8551 __ jccb(Assembler::greaterEqual, done); | |
| 8552 __ addl(Rp, Ry); | |
| 8553 __ bind(done); | |
| 8554 %} | |
| 8555 | |
| 8556 ins_pipe(pipe_cmplt); | |
| 8557 %} | |
| 8558 | |
| 8559 /* better to save a register than avoid a branch */ | |
| 8560 instruct and_cmpLTMask(rRegI p, rRegI q, rRegI y, eFlagsReg cr) %{ | |
| 8561 match(Set y (AndI (CmpLTMask p q) y)); | |
| 8562 effect(KILL cr); | |
| 8563 | |
| 8564 ins_cost(300); | |
| 8565 | |
| 8566 format %{ "CMPL $p, $q\t# and_cmpLTMask\n\t" | |
| 8567 "JLT done\n\t" | |
| 8568 "XORL $y, $y\n" | |
| 8569 "done: " %} | |
| 8570 ins_encode %{ | |
| 8571 Register Rp = $p$$Register; | |
| 8572 Register Rq = $q$$Register; | |
| 8573 Register Ry = $y$$Register; | |
| 8574 Label done; | |
| 8575 __ cmpl(Rp, Rq); | |
| 8576 __ jccb(Assembler::less, done); | |
| 8577 __ xorl(Ry, Ry); | |
| 8578 __ bind(done); | |
| 8579 %} | |
| 8580 | |
| 8581 ins_pipe(pipe_cmplt); | |
| 0 | 8582 %} |
| 8583 | |
| 8584 /* If I enable this, I encourage spilling in the inner loop of compress. | |
| 9154 | 8585 instruct cadd_cmpLTMask_mem(ncxRegI p, ncxRegI q, memory y, eCXRegI tmp, eFlagsReg cr) %{ |
| 0 | 8586 match(Set p (AddI (AndI (CmpLTMask p q) (LoadI y)) (SubI p q))); |
| 8587 */ | |
|
17726
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|
8588 //----------Overflow Math Instructions----------------------------------------- |
|
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|
8589 |
|
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|
8590 instruct overflowAddI_eReg(eFlagsReg cr, eAXRegI op1, rRegI op2) |
|
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8591 %{ |
|
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|
8592 match(Set cr (OverflowAddI op1 op2)); |
|
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8593 effect(DEF cr, USE_KILL op1, USE op2); |
|
085b304a1cc5
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|
8594 |
|
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|
8595 format %{ "ADD $op1, $op2\t# overflow check int" %} |
|
085b304a1cc5
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|
8596 |
|
085b304a1cc5
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|
8597 ins_encode %{ |
|
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|
8598 __ addl($op1$$Register, $op2$$Register); |
|
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|
8599 %} |
|
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|
8600 ins_pipe(ialu_reg_reg); |
|
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|
8601 %} |
|
085b304a1cc5
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|
8602 |
|
085b304a1cc5
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|
8603 instruct overflowAddI_rReg_imm(eFlagsReg cr, eAXRegI op1, immI op2) |
|
085b304a1cc5
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|
8604 %{ |
|
085b304a1cc5
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|
8605 match(Set cr (OverflowAddI op1 op2)); |
|
085b304a1cc5
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8606 effect(DEF cr, USE_KILL op1, USE op2); |
|
085b304a1cc5
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|
8607 |
|
085b304a1cc5
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|
8608 format %{ "ADD $op1, $op2\t# overflow check int" %} |
|
085b304a1cc5
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|
8609 |
|
085b304a1cc5
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|
8610 ins_encode %{ |
|
085b304a1cc5
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|
8611 __ addl($op1$$Register, $op2$$constant); |
|
085b304a1cc5
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|
8612 %} |
|
085b304a1cc5
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|
8613 ins_pipe(ialu_reg_reg); |
|
085b304a1cc5
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|
8614 %} |
|
085b304a1cc5
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|
8615 |
|
085b304a1cc5
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|
8616 instruct overflowSubI_rReg(eFlagsReg cr, rRegI op1, rRegI op2) |
|
085b304a1cc5
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|
8617 %{ |
|
085b304a1cc5
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|
8618 match(Set cr (OverflowSubI op1 op2)); |
|
085b304a1cc5
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|
8619 |
|
085b304a1cc5
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|
8620 format %{ "CMP $op1, $op2\t# overflow check int" %} |
|
085b304a1cc5
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|
8621 ins_encode %{ |
|
085b304a1cc5
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|
8622 __ cmpl($op1$$Register, $op2$$Register); |
|
085b304a1cc5
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|
8623 %} |
|
085b304a1cc5
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|
8624 ins_pipe(ialu_reg_reg); |
|
085b304a1cc5
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|
8625 %} |
|
085b304a1cc5
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changeset
|
8626 |
|
085b304a1cc5
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|
8627 instruct overflowSubI_rReg_imm(eFlagsReg cr, rRegI op1, immI op2) |
|
085b304a1cc5
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|
8628 %{ |
|
085b304a1cc5
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|
8629 match(Set cr (OverflowSubI op1 op2)); |
|
085b304a1cc5
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|
8630 |
|
085b304a1cc5
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|
8631 format %{ "CMP $op1, $op2\t# overflow check int" %} |
|
085b304a1cc5
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|
8632 ins_encode %{ |
|
085b304a1cc5
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|
8633 __ cmpl($op1$$Register, $op2$$constant); |
|
085b304a1cc5
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|
8634 %} |
|
085b304a1cc5
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|
8635 ins_pipe(ialu_reg_reg); |
|
085b304a1cc5
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|
8636 %} |
|
085b304a1cc5
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|
8637 |
|
085b304a1cc5
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|
8638 instruct overflowNegI_rReg(eFlagsReg cr, immI0 zero, eAXRegI op2) |
|
085b304a1cc5
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|
8639 %{ |
|
085b304a1cc5
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|
8640 match(Set cr (OverflowSubI zero op2)); |
|
085b304a1cc5
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|
8641 effect(DEF cr, USE_KILL op2); |
|
085b304a1cc5
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|
8642 |
|
085b304a1cc5
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|
8643 format %{ "NEG $op2\t# overflow check int" %} |
|
085b304a1cc5
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|
8644 ins_encode %{ |
|
085b304a1cc5
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|
8645 __ negl($op2$$Register); |
|
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|
8646 %} |
|
085b304a1cc5
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|
8647 ins_pipe(ialu_reg_reg); |
|
085b304a1cc5
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|
8648 %} |
|
085b304a1cc5
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changeset
|
8649 |
|
085b304a1cc5
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|
8650 instruct overflowMulI_rReg(eFlagsReg cr, eAXRegI op1, rRegI op2) |
|
085b304a1cc5
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|
8651 %{ |
|
085b304a1cc5
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|
8652 match(Set cr (OverflowMulI op1 op2)); |
|
085b304a1cc5
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|
8653 effect(DEF cr, USE_KILL op1, USE op2); |
|
085b304a1cc5
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|
8654 |
|
085b304a1cc5
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|
8655 format %{ "IMUL $op1, $op2\t# overflow check int" %} |
|
085b304a1cc5
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|
8656 ins_encode %{ |
|
085b304a1cc5
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|
8657 __ imull($op1$$Register, $op2$$Register); |
|
085b304a1cc5
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|
8658 %} |
|
085b304a1cc5
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|
8659 ins_pipe(ialu_reg_reg_alu0); |
|
085b304a1cc5
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|
8660 %} |
|
085b304a1cc5
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changeset
|
8661 |
|
085b304a1cc5
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|
8662 instruct overflowMulI_rReg_imm(eFlagsReg cr, rRegI op1, immI op2, rRegI tmp) |
|
085b304a1cc5
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|
8663 %{ |
|
085b304a1cc5
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|
8664 match(Set cr (OverflowMulI op1 op2)); |
|
085b304a1cc5
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|
8665 effect(DEF cr, TEMP tmp, USE op1, USE op2); |
|
085b304a1cc5
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|
8666 |
|
085b304a1cc5
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|
8667 format %{ "IMUL $tmp, $op1, $op2\t# overflow check int" %} |
|
085b304a1cc5
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|
8668 ins_encode %{ |
|
085b304a1cc5
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changeset
|
8669 __ imull($tmp$$Register, $op1$$Register, $op2$$constant); |
|
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8027754: Enable loop optimizations for loops with MathExact inside
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diff
changeset
|
8670 %} |
|
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diff
changeset
|
8671 ins_pipe(ialu_reg_reg_alu0); |
|
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17714
diff
changeset
|
8672 %} |
| 0 | 8673 |
| 8674 //----------Long Instructions------------------------------------------------ | |
| 8675 // Add Long Register with Register | |
| 8676 instruct addL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ | |
| 8677 match(Set dst (AddL dst src)); | |
| 8678 effect(KILL cr); | |
| 8679 ins_cost(200); | |
| 8680 format %{ "ADD $dst.lo,$src.lo\n\t" | |
| 8681 "ADC $dst.hi,$src.hi" %} | |
| 8682 opcode(0x03, 0x13); | |
| 8683 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) ); | |
| 8684 ins_pipe( ialu_reg_reg_long ); | |
| 8685 %} | |
| 8686 | |
| 8687 // Add Long Register with Immediate | |
| 8688 instruct addL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ | |
| 8689 match(Set dst (AddL dst src)); | |
| 8690 effect(KILL cr); | |
| 8691 format %{ "ADD $dst.lo,$src.lo\n\t" | |
| 8692 "ADC $dst.hi,$src.hi" %} | |
| 8693 opcode(0x81,0x00,0x02); /* Opcode 81 /0, 81 /2 */ | |
| 8694 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); | |
| 8695 ins_pipe( ialu_reg_long ); | |
| 8696 %} | |
| 8697 | |
| 8698 // Add Long Register with Memory | |
| 8699 instruct addL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ | |
| 8700 match(Set dst (AddL dst (LoadL mem))); | |
| 8701 effect(KILL cr); | |
| 8702 ins_cost(125); | |
| 8703 format %{ "ADD $dst.lo,$mem\n\t" | |
| 8704 "ADC $dst.hi,$mem+4" %} | |
| 8705 opcode(0x03, 0x13); | |
| 8706 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); | |
| 8707 ins_pipe( ialu_reg_long_mem ); | |
| 8708 %} | |
| 8709 | |
| 8710 // Subtract Long Register with Register. | |
| 8711 instruct subL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ | |
| 8712 match(Set dst (SubL dst src)); | |
| 8713 effect(KILL cr); | |
| 8714 ins_cost(200); | |
| 8715 format %{ "SUB $dst.lo,$src.lo\n\t" | |
| 8716 "SBB $dst.hi,$src.hi" %} | |
| 8717 opcode(0x2B, 0x1B); | |
| 8718 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) ); | |
| 8719 ins_pipe( ialu_reg_reg_long ); | |
| 8720 %} | |
| 8721 | |
| 8722 // Subtract Long Register with Immediate | |
| 8723 instruct subL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ | |
| 8724 match(Set dst (SubL dst src)); | |
| 8725 effect(KILL cr); | |
| 8726 format %{ "SUB $dst.lo,$src.lo\n\t" | |
| 8727 "SBB $dst.hi,$src.hi" %} | |
| 8728 opcode(0x81,0x05,0x03); /* Opcode 81 /5, 81 /3 */ | |
| 8729 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); | |
| 8730 ins_pipe( ialu_reg_long ); | |
| 8731 %} | |
| 8732 | |
| 8733 // Subtract Long Register with Memory | |
| 8734 instruct subL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ | |
| 8735 match(Set dst (SubL dst (LoadL mem))); | |
| 8736 effect(KILL cr); | |
| 8737 ins_cost(125); | |
| 8738 format %{ "SUB $dst.lo,$mem\n\t" | |
| 8739 "SBB $dst.hi,$mem+4" %} | |
| 8740 opcode(0x2B, 0x1B); | |
| 8741 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); | |
| 8742 ins_pipe( ialu_reg_long_mem ); | |
| 8743 %} | |
| 8744 | |
| 8745 instruct negL_eReg(eRegL dst, immL0 zero, eFlagsReg cr) %{ | |
| 8746 match(Set dst (SubL zero dst)); | |
| 8747 effect(KILL cr); | |
| 8748 ins_cost(300); | |
| 8749 format %{ "NEG $dst.hi\n\tNEG $dst.lo\n\tSBB $dst.hi,0" %} | |
| 8750 ins_encode( neg_long(dst) ); | |
| 8751 ins_pipe( ialu_reg_reg_long ); | |
| 8752 %} | |
| 8753 | |
| 8754 // And Long Register with Register | |
| 8755 instruct andL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ | |
| 8756 match(Set dst (AndL dst src)); | |
| 8757 effect(KILL cr); | |
| 8758 format %{ "AND $dst.lo,$src.lo\n\t" | |
| 8759 "AND $dst.hi,$src.hi" %} | |
| 8760 opcode(0x23,0x23); | |
| 8761 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) ); | |
| 8762 ins_pipe( ialu_reg_reg_long ); | |
| 8763 %} | |
| 8764 | |
| 8765 // And Long Register with Immediate | |
| 8766 instruct andL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ | |
| 8767 match(Set dst (AndL dst src)); | |
| 8768 effect(KILL cr); | |
| 8769 format %{ "AND $dst.lo,$src.lo\n\t" | |
| 8770 "AND $dst.hi,$src.hi" %} | |
| 8771 opcode(0x81,0x04,0x04); /* Opcode 81 /4, 81 /4 */ | |
| 8772 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); | |
| 8773 ins_pipe( ialu_reg_long ); | |
| 8774 %} | |
| 8775 | |
| 8776 // And Long Register with Memory | |
| 8777 instruct andL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ | |
| 8778 match(Set dst (AndL dst (LoadL mem))); | |
| 8779 effect(KILL cr); | |
| 8780 ins_cost(125); | |
| 8781 format %{ "AND $dst.lo,$mem\n\t" | |
| 8782 "AND $dst.hi,$mem+4" %} | |
| 8783 opcode(0x23, 0x23); | |
| 8784 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); | |
| 8785 ins_pipe( ialu_reg_long_mem ); | |
| 8786 %} | |
| 8787 | |
|
17729
8a8ff6b577ed
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diff
changeset
|
8788 // BMI1 instructions |
|
8a8ff6b577ed
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changeset
|
8789 instruct andnL_eReg_eReg_eReg(eRegL dst, eRegL src1, eRegL src2, immL_M1 minus_1, eFlagsReg cr) %{ |
|
8a8ff6b577ed
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|
8790 match(Set dst (AndL (XorL src1 minus_1) src2)); |
|
8a8ff6b577ed
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diff
changeset
|
8791 predicate(UseBMI1Instructions); |
|
8a8ff6b577ed
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diff
changeset
|
8792 effect(KILL cr, TEMP dst); |
|
8a8ff6b577ed
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parents:
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diff
changeset
|
8793 |
|
8a8ff6b577ed
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diff
changeset
|
8794 format %{ "ANDNL $dst.lo, $src1.lo, $src2.lo\n\t" |
|
8a8ff6b577ed
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diff
changeset
|
8795 "ANDNL $dst.hi, $src1.hi, $src2.hi" |
|
8a8ff6b577ed
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diff
changeset
|
8796 %} |
|
8a8ff6b577ed
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diff
changeset
|
8797 |
|
8a8ff6b577ed
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parents:
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diff
changeset
|
8798 ins_encode %{ |
|
8a8ff6b577ed
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diff
changeset
|
8799 Register Rdst = $dst$$Register; |
|
8a8ff6b577ed
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diff
changeset
|
8800 Register Rsrc1 = $src1$$Register; |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
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diff
changeset
|
8801 Register Rsrc2 = $src2$$Register; |
|
8a8ff6b577ed
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diff
changeset
|
8802 __ andnl(Rdst, Rsrc1, Rsrc2); |
|
8a8ff6b577ed
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diff
changeset
|
8803 __ andnl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rsrc1), HIGH_FROM_LOW(Rsrc2)); |
|
8a8ff6b577ed
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17726
diff
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|
8804 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
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diff
changeset
|
8805 ins_pipe(ialu_reg_reg_long); |
|
8a8ff6b577ed
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diff
changeset
|
8806 %} |
|
8a8ff6b577ed
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parents:
17726
diff
changeset
|
8807 |
|
8a8ff6b577ed
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parents:
17726
diff
changeset
|
8808 instruct andnL_eReg_eReg_mem(eRegL dst, eRegL src1, memory src2, immL_M1 minus_1, eFlagsReg cr) %{ |
|
8a8ff6b577ed
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diff
changeset
|
8809 match(Set dst (AndL (XorL src1 minus_1) (LoadL src2) )); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
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parents:
17726
diff
changeset
|
8810 predicate(UseBMI1Instructions); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
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parents:
17726
diff
changeset
|
8811 effect(KILL cr, TEMP dst); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
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parents:
17726
diff
changeset
|
8812 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
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17726
diff
changeset
|
8813 ins_cost(125); |
|
8a8ff6b577ed
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17726
diff
changeset
|
8814 format %{ "ANDNL $dst.lo, $src1.lo, $src2\n\t" |
|
8a8ff6b577ed
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17726
diff
changeset
|
8815 "ANDNL $dst.hi, $src1.hi, $src2+4" |
|
8a8ff6b577ed
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parents:
17726
diff
changeset
|
8816 %} |
|
8a8ff6b577ed
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parents:
17726
diff
changeset
|
8817 |
|
8a8ff6b577ed
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parents:
17726
diff
changeset
|
8818 ins_encode %{ |
|
8a8ff6b577ed
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parents:
17726
diff
changeset
|
8819 Register Rdst = $dst$$Register; |
|
8a8ff6b577ed
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iveresov
parents:
17726
diff
changeset
|
8820 Register Rsrc1 = $src1$$Register; |
|
8a8ff6b577ed
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parents:
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diff
changeset
|
8821 Address src2_hi = Address::make_raw($src2$$base, $src2$$index, $src2$$scale, $src2$$disp + 4, relocInfo::none); |
|
8a8ff6b577ed
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parents:
17726
diff
changeset
|
8822 |
|
8a8ff6b577ed
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17726
diff
changeset
|
8823 __ andnl(Rdst, Rsrc1, $src2$$Address); |
|
8a8ff6b577ed
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parents:
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diff
changeset
|
8824 __ andnl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rsrc1), src2_hi); |
|
8a8ff6b577ed
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iveresov
parents:
17726
diff
changeset
|
8825 %} |
|
8a8ff6b577ed
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iveresov
parents:
17726
diff
changeset
|
8826 ins_pipe(ialu_reg_mem); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8827 %} |
|
8a8ff6b577ed
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parents:
17726
diff
changeset
|
8828 |
|
8a8ff6b577ed
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parents:
17726
diff
changeset
|
8829 instruct blsiL_eReg_eReg(eRegL dst, eRegL src, immL0 imm_zero, eFlagsReg cr) %{ |
|
8a8ff6b577ed
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diff
changeset
|
8830 match(Set dst (AndL (SubL imm_zero src) src)); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
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parents:
17726
diff
changeset
|
8831 predicate(UseBMI1Instructions); |
|
8a8ff6b577ed
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parents:
17726
diff
changeset
|
8832 effect(KILL cr, TEMP dst); |
|
8a8ff6b577ed
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parents:
17726
diff
changeset
|
8833 |
|
8a8ff6b577ed
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parents:
17726
diff
changeset
|
8834 format %{ "MOVL $dst.hi, 0\n\t" |
|
8a8ff6b577ed
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diff
changeset
|
8835 "BLSIL $dst.lo, $src.lo\n\t" |
|
8a8ff6b577ed
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diff
changeset
|
8836 "JNZ done\n\t" |
|
8a8ff6b577ed
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parents:
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diff
changeset
|
8837 "BLSIL $dst.hi, $src.hi\n" |
|
8a8ff6b577ed
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17726
diff
changeset
|
8838 "done:" |
|
8a8ff6b577ed
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parents:
17726
diff
changeset
|
8839 %} |
|
8a8ff6b577ed
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parents:
17726
diff
changeset
|
8840 |
|
8a8ff6b577ed
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parents:
17726
diff
changeset
|
8841 ins_encode %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8842 Label done; |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
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parents:
17726
diff
changeset
|
8843 Register Rdst = $dst$$Register; |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
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parents:
17726
diff
changeset
|
8844 Register Rsrc = $src$$Register; |
|
8a8ff6b577ed
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parents:
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diff
changeset
|
8845 __ movl(HIGH_FROM_LOW(Rdst), 0); |
|
8a8ff6b577ed
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diff
changeset
|
8846 __ blsil(Rdst, Rsrc); |
|
8a8ff6b577ed
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parents:
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diff
changeset
|
8847 __ jccb(Assembler::notZero, done); |
|
8a8ff6b577ed
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diff
changeset
|
8848 __ blsil(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rsrc)); |
|
8a8ff6b577ed
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parents:
17726
diff
changeset
|
8849 __ bind(done); |
|
8a8ff6b577ed
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parents:
17726
diff
changeset
|
8850 %} |
|
8a8ff6b577ed
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parents:
17726
diff
changeset
|
8851 ins_pipe(ialu_reg); |
|
8a8ff6b577ed
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parents:
17726
diff
changeset
|
8852 %} |
|
8a8ff6b577ed
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parents:
17726
diff
changeset
|
8853 |
|
8a8ff6b577ed
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parents:
17726
diff
changeset
|
8854 instruct blsiL_eReg_mem(eRegL dst, memory src, immL0 imm_zero, eFlagsReg cr) %{ |
|
8a8ff6b577ed
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|
8855 match(Set dst (AndL (SubL imm_zero (LoadL src) ) (LoadL src) )); |
|
8a8ff6b577ed
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parents:
17726
diff
changeset
|
8856 predicate(UseBMI1Instructions); |
|
8a8ff6b577ed
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parents:
17726
diff
changeset
|
8857 effect(KILL cr, TEMP dst); |
|
8a8ff6b577ed
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parents:
17726
diff
changeset
|
8858 |
|
8a8ff6b577ed
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17726
diff
changeset
|
8859 ins_cost(125); |
|
8a8ff6b577ed
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diff
changeset
|
8860 format %{ "MOVL $dst.hi, 0\n\t" |
|
8a8ff6b577ed
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diff
changeset
|
8861 "BLSIL $dst.lo, $src\n\t" |
|
8a8ff6b577ed
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diff
changeset
|
8862 "JNZ done\n\t" |
|
8a8ff6b577ed
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diff
changeset
|
8863 "BLSIL $dst.hi, $src+4\n" |
|
8a8ff6b577ed
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diff
changeset
|
8864 "done:" |
|
8a8ff6b577ed
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parents:
17726
diff
changeset
|
8865 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8866 |
|
8a8ff6b577ed
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parents:
17726
diff
changeset
|
8867 ins_encode %{ |
|
8a8ff6b577ed
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parents:
17726
diff
changeset
|
8868 Label done; |
|
8a8ff6b577ed
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parents:
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diff
changeset
|
8869 Register Rdst = $dst$$Register; |
|
8a8ff6b577ed
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changeset
|
8870 Address src_hi = Address::make_raw($src$$base, $src$$index, $src$$scale, $src$$disp + 4, relocInfo::none); |
|
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diff
changeset
|
8871 |
|
8a8ff6b577ed
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parents:
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diff
changeset
|
8872 __ movl(HIGH_FROM_LOW(Rdst), 0); |
|
8a8ff6b577ed
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iveresov
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diff
changeset
|
8873 __ blsil(Rdst, $src$$Address); |
|
8a8ff6b577ed
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diff
changeset
|
8874 __ jccb(Assembler::notZero, done); |
|
8a8ff6b577ed
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diff
changeset
|
8875 __ blsil(HIGH_FROM_LOW(Rdst), src_hi); |
|
8a8ff6b577ed
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iveresov
parents:
17726
diff
changeset
|
8876 __ bind(done); |
|
8a8ff6b577ed
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iveresov
parents:
17726
diff
changeset
|
8877 %} |
|
8a8ff6b577ed
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iveresov
parents:
17726
diff
changeset
|
8878 ins_pipe(ialu_reg_mem); |
|
8a8ff6b577ed
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diff
changeset
|
8879 %} |
|
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iveresov
parents:
17726
diff
changeset
|
8880 |
|
8a8ff6b577ed
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iveresov
parents:
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diff
changeset
|
8881 instruct blsmskL_eReg_eReg(eRegL dst, eRegL src, immL_M1 minus_1, eFlagsReg cr) |
|
8a8ff6b577ed
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diff
changeset
|
8882 %{ |
|
8a8ff6b577ed
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iveresov
parents:
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diff
changeset
|
8883 match(Set dst (XorL (AddL src minus_1) src)); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
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parents:
17726
diff
changeset
|
8884 predicate(UseBMI1Instructions); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8885 effect(KILL cr, TEMP dst); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8886 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
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diff
changeset
|
8887 format %{ "MOVL $dst.hi, 0\n\t" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
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diff
changeset
|
8888 "BLSMSKL $dst.lo, $src.lo\n\t" |
|
8a8ff6b577ed
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iveresov
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diff
changeset
|
8889 "JNC done\n\t" |
|
8a8ff6b577ed
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diff
changeset
|
8890 "BLSMSKL $dst.hi, $src.hi\n" |
|
8a8ff6b577ed
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parents:
17726
diff
changeset
|
8891 "done:" |
|
8a8ff6b577ed
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iveresov
parents:
17726
diff
changeset
|
8892 %} |
|
8a8ff6b577ed
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iveresov
parents:
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diff
changeset
|
8893 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8894 ins_encode %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
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diff
changeset
|
8895 Label done; |
|
8a8ff6b577ed
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iveresov
parents:
17726
diff
changeset
|
8896 Register Rdst = $dst$$Register; |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
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parents:
17726
diff
changeset
|
8897 Register Rsrc = $src$$Register; |
|
8a8ff6b577ed
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diff
changeset
|
8898 __ movl(HIGH_FROM_LOW(Rdst), 0); |
|
8a8ff6b577ed
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parents:
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diff
changeset
|
8899 __ blsmskl(Rdst, Rsrc); |
|
8a8ff6b577ed
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parents:
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diff
changeset
|
8900 __ jccb(Assembler::carryClear, done); |
|
8a8ff6b577ed
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parents:
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diff
changeset
|
8901 __ blsmskl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rsrc)); |
|
8a8ff6b577ed
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diff
changeset
|
8902 __ bind(done); |
|
8a8ff6b577ed
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iveresov
parents:
17726
diff
changeset
|
8903 %} |
|
8a8ff6b577ed
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iveresov
parents:
17726
diff
changeset
|
8904 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8905 ins_pipe(ialu_reg); |
|
8a8ff6b577ed
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iveresov
parents:
17726
diff
changeset
|
8906 %} |
|
8a8ff6b577ed
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iveresov
parents:
17726
diff
changeset
|
8907 |
|
8a8ff6b577ed
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iveresov
parents:
17726
diff
changeset
|
8908 instruct blsmskL_eReg_mem(eRegL dst, memory src, immL_M1 minus_1, eFlagsReg cr) |
|
8a8ff6b577ed
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parents:
17726
diff
changeset
|
8909 %{ |
|
8a8ff6b577ed
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parents:
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diff
changeset
|
8910 match(Set dst (XorL (AddL (LoadL src) minus_1) (LoadL src) )); |
|
8a8ff6b577ed
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iveresov
parents:
17726
diff
changeset
|
8911 predicate(UseBMI1Instructions); |
|
8a8ff6b577ed
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iveresov
parents:
17726
diff
changeset
|
8912 effect(KILL cr, TEMP dst); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8913 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8914 ins_cost(125); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
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diff
changeset
|
8915 format %{ "MOVL $dst.hi, 0\n\t" |
|
8a8ff6b577ed
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parents:
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diff
changeset
|
8916 "BLSMSKL $dst.lo, $src\n\t" |
|
8a8ff6b577ed
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parents:
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diff
changeset
|
8917 "JNC done\n\t" |
|
8a8ff6b577ed
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parents:
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diff
changeset
|
8918 "BLSMSKL $dst.hi, $src+4\n" |
|
8a8ff6b577ed
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iveresov
parents:
17726
diff
changeset
|
8919 "done:" |
|
8a8ff6b577ed
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iveresov
parents:
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diff
changeset
|
8920 %} |
|
8a8ff6b577ed
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iveresov
parents:
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diff
changeset
|
8921 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8922 ins_encode %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8923 Label done; |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8924 Register Rdst = $dst$$Register; |
|
8a8ff6b577ed
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parents:
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diff
changeset
|
8925 Address src_hi = Address::make_raw($src$$base, $src$$index, $src$$scale, $src$$disp + 4, relocInfo::none); |
|
8a8ff6b577ed
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parents:
17726
diff
changeset
|
8926 |
|
8a8ff6b577ed
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iveresov
parents:
17726
diff
changeset
|
8927 __ movl(HIGH_FROM_LOW(Rdst), 0); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
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diff
changeset
|
8928 __ blsmskl(Rdst, $src$$Address); |
|
8a8ff6b577ed
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parents:
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diff
changeset
|
8929 __ jccb(Assembler::carryClear, done); |
|
8a8ff6b577ed
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parents:
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diff
changeset
|
8930 __ blsmskl(HIGH_FROM_LOW(Rdst), src_hi); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8931 __ bind(done); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8932 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8933 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8934 ins_pipe(ialu_reg_mem); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8935 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8936 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8937 instruct blsrL_eReg_eReg(eRegL dst, eRegL src, immL_M1 minus_1, eFlagsReg cr) |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8938 %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8939 match(Set dst (AndL (AddL src minus_1) src) ); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8940 predicate(UseBMI1Instructions); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8941 effect(KILL cr, TEMP dst); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8942 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8943 format %{ "MOVL $dst.hi, $src.hi\n\t" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8944 "BLSRL $dst.lo, $src.lo\n\t" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8945 "JNC done\n\t" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8946 "BLSRL $dst.hi, $src.hi\n" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8947 "done:" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8948 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8949 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8950 ins_encode %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8951 Label done; |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8952 Register Rdst = $dst$$Register; |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8953 Register Rsrc = $src$$Register; |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8954 __ movl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rsrc)); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8955 __ blsrl(Rdst, Rsrc); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8956 __ jccb(Assembler::carryClear, done); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8957 __ blsrl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rsrc)); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8958 __ bind(done); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8959 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8960 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8961 ins_pipe(ialu_reg); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8962 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8963 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8964 instruct blsrL_eReg_mem(eRegL dst, memory src, immL_M1 minus_1, eFlagsReg cr) |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8965 %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8966 match(Set dst (AndL (AddL (LoadL src) minus_1) (LoadL src) )); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8967 predicate(UseBMI1Instructions); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8968 effect(KILL cr, TEMP dst); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8969 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8970 ins_cost(125); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8971 format %{ "MOVL $dst.hi, $src+4\n\t" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8972 "BLSRL $dst.lo, $src\n\t" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8973 "JNC done\n\t" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8974 "BLSRL $dst.hi, $src+4\n" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8975 "done:" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8976 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8977 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8978 ins_encode %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8979 Label done; |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8980 Register Rdst = $dst$$Register; |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8981 Address src_hi = Address::make_raw($src$$base, $src$$index, $src$$scale, $src$$disp + 4, relocInfo::none); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8982 __ movl(HIGH_FROM_LOW(Rdst), src_hi); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8983 __ blsrl(Rdst, $src$$Address); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8984 __ jccb(Assembler::carryClear, done); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8985 __ blsrl(HIGH_FROM_LOW(Rdst), src_hi); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8986 __ bind(done); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8987 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8988 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8989 ins_pipe(ialu_reg_mem); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8990 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8991 |
| 0 | 8992 // Or Long Register with Register |
| 8993 instruct orl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ | |
| 8994 match(Set dst (OrL dst src)); | |
| 8995 effect(KILL cr); | |
| 8996 format %{ "OR $dst.lo,$src.lo\n\t" | |
| 8997 "OR $dst.hi,$src.hi" %} | |
| 8998 opcode(0x0B,0x0B); | |
| 8999 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) ); | |
| 9000 ins_pipe( ialu_reg_reg_long ); | |
| 9001 %} | |
| 9002 | |
| 9003 // Or Long Register with Immediate | |
| 9004 instruct orl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ | |
| 9005 match(Set dst (OrL dst src)); | |
| 9006 effect(KILL cr); | |
| 9007 format %{ "OR $dst.lo,$src.lo\n\t" | |
| 9008 "OR $dst.hi,$src.hi" %} | |
| 9009 opcode(0x81,0x01,0x01); /* Opcode 81 /1, 81 /1 */ | |
| 9010 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); | |
| 9011 ins_pipe( ialu_reg_long ); | |
| 9012 %} | |
| 9013 | |
| 9014 // Or Long Register with Memory | |
| 9015 instruct orl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ | |
| 9016 match(Set dst (OrL dst (LoadL mem))); | |
| 9017 effect(KILL cr); | |
| 9018 ins_cost(125); | |
| 9019 format %{ "OR $dst.lo,$mem\n\t" | |
| 9020 "OR $dst.hi,$mem+4" %} | |
| 9021 opcode(0x0B,0x0B); | |
| 9022 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); | |
| 9023 ins_pipe( ialu_reg_long_mem ); | |
| 9024 %} | |
| 9025 | |
| 9026 // Xor Long Register with Register | |
| 9027 instruct xorl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ | |
| 9028 match(Set dst (XorL dst src)); | |
| 9029 effect(KILL cr); | |
| 9030 format %{ "XOR $dst.lo,$src.lo\n\t" | |
| 9031 "XOR $dst.hi,$src.hi" %} | |
| 9032 opcode(0x33,0x33); | |
| 9033 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) ); | |
| 9034 ins_pipe( ialu_reg_reg_long ); | |
| 9035 %} | |
| 9036 | |
| 403 | 9037 // Xor Long Register with Immediate -1 |
| 9038 instruct xorl_eReg_im1(eRegL dst, immL_M1 imm) %{ | |
| 9039 match(Set dst (XorL dst imm)); | |
| 9040 format %{ "NOT $dst.lo\n\t" | |
| 9041 "NOT $dst.hi" %} | |
| 9042 ins_encode %{ | |
| 9043 __ notl($dst$$Register); | |
| 9044 __ notl(HIGH_FROM_LOW($dst$$Register)); | |
| 9045 %} | |
| 9046 ins_pipe( ialu_reg_long ); | |
| 9047 %} | |
| 9048 | |
| 0 | 9049 // Xor Long Register with Immediate |
| 9050 instruct xorl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ | |
| 9051 match(Set dst (XorL dst src)); | |
| 9052 effect(KILL cr); | |
| 9053 format %{ "XOR $dst.lo,$src.lo\n\t" | |
| 9054 "XOR $dst.hi,$src.hi" %} | |
| 9055 opcode(0x81,0x06,0x06); /* Opcode 81 /6, 81 /6 */ | |
| 9056 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); | |
| 9057 ins_pipe( ialu_reg_long ); | |
| 9058 %} | |
| 9059 | |
| 9060 // Xor Long Register with Memory | |
| 9061 instruct xorl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ | |
| 9062 match(Set dst (XorL dst (LoadL mem))); | |
| 9063 effect(KILL cr); | |
| 9064 ins_cost(125); | |
| 9065 format %{ "XOR $dst.lo,$mem\n\t" | |
| 9066 "XOR $dst.hi,$mem+4" %} | |
| 9067 opcode(0x33,0x33); | |
| 9068 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); | |
| 9069 ins_pipe( ialu_reg_long_mem ); | |
| 9070 %} | |
| 9071 | |
| 219 | 9072 // Shift Left Long by 1 |
| 9073 instruct shlL_eReg_1(eRegL dst, immI_1 cnt, eFlagsReg cr) %{ | |
| 9074 predicate(UseNewLongLShift); | |
| 9075 match(Set dst (LShiftL dst cnt)); | |
| 9076 effect(KILL cr); | |
| 9077 ins_cost(100); | |
| 9078 format %{ "ADD $dst.lo,$dst.lo\n\t" | |
| 9079 "ADC $dst.hi,$dst.hi" %} | |
| 9080 ins_encode %{ | |
| 9081 __ addl($dst$$Register,$dst$$Register); | |
| 9082 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); | |
| 9083 %} | |
| 9084 ins_pipe( ialu_reg_long ); | |
| 9085 %} | |
| 9086 | |
| 9087 // Shift Left Long by 2 | |
| 9088 instruct shlL_eReg_2(eRegL dst, immI_2 cnt, eFlagsReg cr) %{ | |
| 9089 predicate(UseNewLongLShift); | |
| 9090 match(Set dst (LShiftL dst cnt)); | |
| 9091 effect(KILL cr); | |
| 9092 ins_cost(100); | |
| 9093 format %{ "ADD $dst.lo,$dst.lo\n\t" | |
| 9094 "ADC $dst.hi,$dst.hi\n\t" | |
| 9095 "ADD $dst.lo,$dst.lo\n\t" | |
| 9096 "ADC $dst.hi,$dst.hi" %} | |
| 9097 ins_encode %{ | |
| 9098 __ addl($dst$$Register,$dst$$Register); | |
| 9099 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); | |
| 9100 __ addl($dst$$Register,$dst$$Register); | |
| 9101 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); | |
| 9102 %} | |
| 9103 ins_pipe( ialu_reg_long ); | |
| 9104 %} | |
| 9105 | |
| 9106 // Shift Left Long by 3 | |
| 9107 instruct shlL_eReg_3(eRegL dst, immI_3 cnt, eFlagsReg cr) %{ | |
| 9108 predicate(UseNewLongLShift); | |
| 9109 match(Set dst (LShiftL dst cnt)); | |
| 9110 effect(KILL cr); | |
| 9111 ins_cost(100); | |
| 9112 format %{ "ADD $dst.lo,$dst.lo\n\t" | |
| 9113 "ADC $dst.hi,$dst.hi\n\t" | |
| 9114 "ADD $dst.lo,$dst.lo\n\t" | |
| 9115 "ADC $dst.hi,$dst.hi\n\t" | |
| 9116 "ADD $dst.lo,$dst.lo\n\t" | |
| 9117 "ADC $dst.hi,$dst.hi" %} | |
| 9118 ins_encode %{ | |
| 9119 __ addl($dst$$Register,$dst$$Register); | |
| 9120 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); | |
| 9121 __ addl($dst$$Register,$dst$$Register); | |
| 9122 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); | |
| 9123 __ addl($dst$$Register,$dst$$Register); | |
| 9124 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); | |
| 9125 %} | |
| 9126 ins_pipe( ialu_reg_long ); | |
| 9127 %} | |
| 9128 | |
| 0 | 9129 // Shift Left Long by 1-31 |
| 9130 instruct shlL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{ | |
| 9131 match(Set dst (LShiftL dst cnt)); | |
| 9132 effect(KILL cr); | |
| 9133 ins_cost(200); | |
| 9134 format %{ "SHLD $dst.hi,$dst.lo,$cnt\n\t" | |
| 9135 "SHL $dst.lo,$cnt" %} | |
| 9136 opcode(0xC1, 0x4, 0xA4); /* 0F/A4, then C1 /4 ib */ | |
| 9137 ins_encode( move_long_small_shift(dst,cnt) ); | |
| 9138 ins_pipe( ialu_reg_long ); | |
| 9139 %} | |
| 9140 | |
| 9141 // Shift Left Long by 32-63 | |
| 9142 instruct shlL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{ | |
| 9143 match(Set dst (LShiftL dst cnt)); | |
| 9144 effect(KILL cr); | |
| 9145 ins_cost(300); | |
| 9146 format %{ "MOV $dst.hi,$dst.lo\n" | |
| 9147 "\tSHL $dst.hi,$cnt-32\n" | |
| 9148 "\tXOR $dst.lo,$dst.lo" %} | |
| 9149 opcode(0xC1, 0x4); /* C1 /4 ib */ | |
| 9150 ins_encode( move_long_big_shift_clr(dst,cnt) ); | |
| 9151 ins_pipe( ialu_reg_long ); | |
| 9152 %} | |
| 9153 | |
| 9154 // Shift Left Long by variable | |
| 9155 instruct salL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{ | |
| 9156 match(Set dst (LShiftL dst shift)); | |
| 9157 effect(KILL cr); | |
| 9158 ins_cost(500+200); | |
| 9159 size(17); | |
| 9160 format %{ "TEST $shift,32\n\t" | |
| 9161 "JEQ,s small\n\t" | |
| 9162 "MOV $dst.hi,$dst.lo\n\t" | |
| 9163 "XOR $dst.lo,$dst.lo\n" | |
| 9164 "small:\tSHLD $dst.hi,$dst.lo,$shift\n\t" | |
| 9165 "SHL $dst.lo,$shift" %} | |
| 9166 ins_encode( shift_left_long( dst, shift ) ); | |
| 9167 ins_pipe( pipe_slow ); | |
| 9168 %} | |
| 9169 | |
| 9170 // Shift Right Long by 1-31 | |
| 9171 instruct shrL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{ | |
| 9172 match(Set dst (URShiftL dst cnt)); | |
| 9173 effect(KILL cr); | |
| 9174 ins_cost(200); | |
| 9175 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t" | |
| 9176 "SHR $dst.hi,$cnt" %} | |
| 9177 opcode(0xC1, 0x5, 0xAC); /* 0F/AC, then C1 /5 ib */ | |
| 9178 ins_encode( move_long_small_shift(dst,cnt) ); | |
| 9179 ins_pipe( ialu_reg_long ); | |
| 9180 %} | |
| 9181 | |
| 9182 // Shift Right Long by 32-63 | |
| 9183 instruct shrL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{ | |
| 9184 match(Set dst (URShiftL dst cnt)); | |
| 9185 effect(KILL cr); | |
| 9186 ins_cost(300); | |
| 9187 format %{ "MOV $dst.lo,$dst.hi\n" | |
| 9188 "\tSHR $dst.lo,$cnt-32\n" | |
| 9189 "\tXOR $dst.hi,$dst.hi" %} | |
| 9190 opcode(0xC1, 0x5); /* C1 /5 ib */ | |
| 9191 ins_encode( move_long_big_shift_clr(dst,cnt) ); | |
| 9192 ins_pipe( ialu_reg_long ); | |
| 9193 %} | |
| 9194 | |
| 9195 // Shift Right Long by variable | |
| 9196 instruct shrL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{ | |
| 9197 match(Set dst (URShiftL dst shift)); | |
| 9198 effect(KILL cr); | |
| 9199 ins_cost(600); | |
| 9200 size(17); | |
| 9201 format %{ "TEST $shift,32\n\t" | |
| 9202 "JEQ,s small\n\t" | |
| 9203 "MOV $dst.lo,$dst.hi\n\t" | |
| 9204 "XOR $dst.hi,$dst.hi\n" | |
| 9205 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t" | |
| 9206 "SHR $dst.hi,$shift" %} | |
| 9207 ins_encode( shift_right_long( dst, shift ) ); | |
| 9208 ins_pipe( pipe_slow ); | |
| 9209 %} | |
| 9210 | |
| 9211 // Shift Right Long by 1-31 | |
| 9212 instruct sarL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{ | |
| 9213 match(Set dst (RShiftL dst cnt)); | |
| 9214 effect(KILL cr); | |
| 9215 ins_cost(200); | |
| 9216 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t" | |
| 9217 "SAR $dst.hi,$cnt" %} | |
| 9218 opcode(0xC1, 0x7, 0xAC); /* 0F/AC, then C1 /7 ib */ | |
| 9219 ins_encode( move_long_small_shift(dst,cnt) ); | |
| 9220 ins_pipe( ialu_reg_long ); | |
| 9221 %} | |
| 9222 | |
| 9223 // Shift Right Long by 32-63 | |
| 9224 instruct sarL_eReg_32_63( eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{ | |
| 9225 match(Set dst (RShiftL dst cnt)); | |
| 9226 effect(KILL cr); | |
| 9227 ins_cost(300); | |
| 9228 format %{ "MOV $dst.lo,$dst.hi\n" | |
| 9229 "\tSAR $dst.lo,$cnt-32\n" | |
| 9230 "\tSAR $dst.hi,31" %} | |
| 9231 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 9232 ins_encode( move_long_big_shift_sign(dst,cnt) ); | |
| 9233 ins_pipe( ialu_reg_long ); | |
| 9234 %} | |
| 9235 | |
| 9236 // Shift Right arithmetic Long by variable | |
| 9237 instruct sarL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{ | |
| 9238 match(Set dst (RShiftL dst shift)); | |
| 9239 effect(KILL cr); | |
| 9240 ins_cost(600); | |
| 9241 size(18); | |
| 9242 format %{ "TEST $shift,32\n\t" | |
| 9243 "JEQ,s small\n\t" | |
| 9244 "MOV $dst.lo,$dst.hi\n\t" | |
| 9245 "SAR $dst.hi,31\n" | |
| 9246 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t" | |
| 9247 "SAR $dst.hi,$shift" %} | |
| 9248 ins_encode( shift_right_arith_long( dst, shift ) ); | |
| 9249 ins_pipe( pipe_slow ); | |
| 9250 %} | |
| 9251 | |
| 9252 | |
| 9253 //----------Double Instructions------------------------------------------------ | |
| 9254 // Double Math | |
| 9255 | |
| 9256 // Compare & branch | |
| 9257 | |
| 9258 // P6 version of float compare, sets condition codes in EFLAGS | |
|
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9259 instruct cmpDPR_cc_P6(eFlagsRegU cr, regDPR src1, regDPR src2, eAXRegI rax) %{ |
| 0 | 9260 predicate(VM_Version::supports_cmov() && UseSSE <=1); |
| 9261 match(Set cr (CmpD src1 src2)); | |
| 9262 effect(KILL rax); | |
| 9263 ins_cost(150); | |
| 9264 format %{ "FLD $src1\n\t" | |
| 9265 "FUCOMIP ST,$src2 // P6 instruction\n\t" | |
| 9266 "JNP exit\n\t" | |
| 9267 "MOV ah,1 // saw a NaN, set CF\n\t" | |
| 9268 "SAHF\n" | |
| 9269 "exit:\tNOP // avoid branch to branch" %} | |
| 9270 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */ | |
|
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9271 ins_encode( Push_Reg_DPR(src1), |
| 0 | 9272 OpcP, RegOpc(src2), |
| 9273 cmpF_P6_fixup ); | |
| 9274 ins_pipe( pipe_slow ); | |
| 9275 %} | |
| 9276 | |
|
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9277 instruct cmpDPR_cc_P6CF(eFlagsRegUCF cr, regDPR src1, regDPR src2) %{ |
|
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|
9278 predicate(VM_Version::supports_cmov() && UseSSE <=1); |
|
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9279 match(Set cr (CmpD src1 src2)); |
|
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9280 ins_cost(150); |
|
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9281 format %{ "FLD $src1\n\t" |
|
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9282 "FUCOMIP ST,$src2 // P6 instruction" %} |
|
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|
9283 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */ |
|
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9284 ins_encode( Push_Reg_DPR(src1), |
|
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|
9285 OpcP, RegOpc(src2)); |
|
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|
9286 ins_pipe( pipe_slow ); |
|
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|
9287 %} |
|
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|
9288 |
| 0 | 9289 // Compare & branch |
|
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9290 instruct cmpDPR_cc(eFlagsRegU cr, regDPR src1, regDPR src2, eAXRegI rax) %{ |
| 0 | 9291 predicate(UseSSE<=1); |
| 9292 match(Set cr (CmpD src1 src2)); | |
| 9293 effect(KILL rax); | |
| 9294 ins_cost(200); | |
| 9295 format %{ "FLD $src1\n\t" | |
| 9296 "FCOMp $src2\n\t" | |
| 9297 "FNSTSW AX\n\t" | |
| 9298 "TEST AX,0x400\n\t" | |
| 9299 "JZ,s flags\n\t" | |
| 9300 "MOV AH,1\t# unordered treat as LT\n" | |
| 9301 "flags:\tSAHF" %} | |
| 9302 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */ | |
|
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|
9303 ins_encode( Push_Reg_DPR(src1), |
| 0 | 9304 OpcP, RegOpc(src2), |
| 9305 fpu_flags); | |
| 9306 ins_pipe( pipe_slow ); | |
| 9307 %} | |
| 9308 | |
| 9309 // Compare vs zero into -1,0,1 | |
|
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9310 instruct cmpDPR_0(rRegI dst, regDPR src1, immDPR0 zero, eAXRegI rax, eFlagsReg cr) %{ |
| 0 | 9311 predicate(UseSSE<=1); |
| 9312 match(Set dst (CmpD3 src1 zero)); | |
| 9313 effect(KILL cr, KILL rax); | |
| 9314 ins_cost(280); | |
| 9315 format %{ "FTSTD $dst,$src1" %} | |
| 9316 opcode(0xE4, 0xD9); | |
|
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9317 ins_encode( Push_Reg_DPR(src1), |
| 0 | 9318 OpcS, OpcP, PopFPU, |
| 9319 CmpF_Result(dst)); | |
| 9320 ins_pipe( pipe_slow ); | |
| 9321 %} | |
| 9322 | |
| 9323 // Compare into -1,0,1 | |
|
6179
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9324 instruct cmpDPR_reg(rRegI dst, regDPR src1, regDPR src2, eAXRegI rax, eFlagsReg cr) %{ |
| 0 | 9325 predicate(UseSSE<=1); |
| 9326 match(Set dst (CmpD3 src1 src2)); | |
| 9327 effect(KILL cr, KILL rax); | |
| 9328 ins_cost(300); | |
| 9329 format %{ "FCMPD $dst,$src1,$src2" %} | |
| 9330 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */ | |
|
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9331 ins_encode( Push_Reg_DPR(src1), |
| 0 | 9332 OpcP, RegOpc(src2), |
| 9333 CmpF_Result(dst)); | |
| 9334 ins_pipe( pipe_slow ); | |
| 9335 %} | |
| 9336 | |
| 9337 // float compare and set condition codes in EFLAGS by XMM regs | |
|
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9338 instruct cmpD_cc(eFlagsRegU cr, regD src1, regD src2) %{ |
| 0 | 9339 predicate(UseSSE>=2); |
| 4759 | 9340 match(Set cr (CmpD src1 src2)); |
| 9341 ins_cost(145); | |
| 9342 format %{ "UCOMISD $src1,$src2\n\t" | |
| 9343 "JNP,s exit\n\t" | |
| 9344 "PUSHF\t# saw NaN, set CF\n\t" | |
| 9345 "AND [rsp], #0xffffff2b\n\t" | |
| 9346 "POPF\n" | |
| 9347 "exit:" %} | |
| 9348 ins_encode %{ | |
| 9349 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister); | |
| 9350 emit_cmpfp_fixup(_masm); | |
| 9351 %} | |
| 9352 ins_pipe( pipe_slow ); | |
| 9353 %} | |
| 9354 | |
|
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9355 instruct cmpD_ccCF(eFlagsRegUCF cr, regD src1, regD src2) %{ |
|
415
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|
9356 predicate(UseSSE>=2); |
| 4759 | 9357 match(Set cr (CmpD src1 src2)); |
|
415
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|
9358 ins_cost(100); |
| 4759 | 9359 format %{ "UCOMISD $src1,$src2" %} |
| 9360 ins_encode %{ | |
| 9361 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister); | |
| 9362 %} | |
|
415
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|
9363 ins_pipe( pipe_slow ); |
|
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|
9364 %} |
|
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|
9365 |
| 0 | 9366 // float compare and set condition codes in EFLAGS by XMM regs |
|
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9367 instruct cmpD_ccmem(eFlagsRegU cr, regD src1, memory src2) %{ |
| 0 | 9368 predicate(UseSSE>=2); |
| 4759 | 9369 match(Set cr (CmpD src1 (LoadD src2))); |
| 0 | 9370 ins_cost(145); |
| 4759 | 9371 format %{ "UCOMISD $src1,$src2\n\t" |
| 9372 "JNP,s exit\n\t" | |
| 9373 "PUSHF\t# saw NaN, set CF\n\t" | |
| 9374 "AND [rsp], #0xffffff2b\n\t" | |
| 9375 "POPF\n" | |
| 9376 "exit:" %} | |
| 9377 ins_encode %{ | |
| 9378 __ ucomisd($src1$$XMMRegister, $src2$$Address); | |
| 9379 emit_cmpfp_fixup(_masm); | |
| 9380 %} | |
| 9381 ins_pipe( pipe_slow ); | |
| 9382 %} | |
| 9383 | |
|
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9384 instruct cmpD_ccmemCF(eFlagsRegUCF cr, regD src1, memory src2) %{ |
|
415
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|
9385 predicate(UseSSE>=2); |
| 4759 | 9386 match(Set cr (CmpD src1 (LoadD src2))); |
|
415
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|
9387 ins_cost(100); |
| 4759 | 9388 format %{ "UCOMISD $src1,$src2" %} |
| 9389 ins_encode %{ | |
| 9390 __ ucomisd($src1$$XMMRegister, $src2$$Address); | |
| 9391 %} | |
|
415
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changeset
|
9392 ins_pipe( pipe_slow ); |
|
4d9884b01ba6
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diff
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|
9393 %} |
|
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|
9394 |
| 0 | 9395 // Compare into -1,0,1 in XMM |
|
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9396 instruct cmpD_reg(xRegI dst, regD src1, regD src2, eFlagsReg cr) %{ |
| 0 | 9397 predicate(UseSSE>=2); |
| 9398 match(Set dst (CmpD3 src1 src2)); | |
| 9399 effect(KILL cr); | |
| 9400 ins_cost(255); | |
| 4759 | 9401 format %{ "UCOMISD $src1, $src2\n\t" |
| 9402 "MOV $dst, #-1\n\t" | |
| 9403 "JP,s done\n\t" | |
| 9404 "JB,s done\n\t" | |
| 9405 "SETNE $dst\n\t" | |
| 9406 "MOVZB $dst, $dst\n" | |
| 9407 "done:" %} | |
| 9408 ins_encode %{ | |
| 9409 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister); | |
| 9410 emit_cmpfp3(_masm, $dst$$Register); | |
| 9411 %} | |
| 0 | 9412 ins_pipe( pipe_slow ); |
| 9413 %} | |
| 9414 | |
| 9415 // Compare into -1,0,1 in XMM and memory | |
|
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9416 instruct cmpD_regmem(xRegI dst, regD src1, memory src2, eFlagsReg cr) %{ |
| 0 | 9417 predicate(UseSSE>=2); |
| 4759 | 9418 match(Set dst (CmpD3 src1 (LoadD src2))); |
| 0 | 9419 effect(KILL cr); |
| 9420 ins_cost(275); | |
| 4759 | 9421 format %{ "UCOMISD $src1, $src2\n\t" |
| 9422 "MOV $dst, #-1\n\t" | |
| 9423 "JP,s done\n\t" | |
| 9424 "JB,s done\n\t" | |
| 9425 "SETNE $dst\n\t" | |
| 9426 "MOVZB $dst, $dst\n" | |
| 9427 "done:" %} | |
| 9428 ins_encode %{ | |
| 9429 __ ucomisd($src1$$XMMRegister, $src2$$Address); | |
| 9430 emit_cmpfp3(_masm, $dst$$Register); | |
| 9431 %} | |
| 0 | 9432 ins_pipe( pipe_slow ); |
| 9433 %} | |
| 9434 | |
| 9435 | |
|
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9436 instruct subDPR_reg(regDPR dst, regDPR src) %{ |
| 0 | 9437 predicate (UseSSE <=1); |
| 9438 match(Set dst (SubD dst src)); | |
| 9439 | |
| 9440 format %{ "FLD $src\n\t" | |
| 9441 "DSUBp $dst,ST" %} | |
| 9442 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */ | |
| 9443 ins_cost(150); | |
|
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9444 ins_encode( Push_Reg_DPR(src), |
| 0 | 9445 OpcP, RegOpc(dst) ); |
| 9446 ins_pipe( fpu_reg_reg ); | |
| 9447 %} | |
| 9448 | |
|
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9449 instruct subDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{ |
| 0 | 9450 predicate (UseSSE <=1); |
| 9451 match(Set dst (RoundDouble (SubD src1 src2))); | |
| 9452 ins_cost(250); | |
| 9453 | |
| 9454 format %{ "FLD $src2\n\t" | |
| 9455 "DSUB ST,$src1\n\t" | |
| 9456 "FSTP_D $dst\t# D-round" %} | |
| 9457 opcode(0xD8, 0x5); | |
|
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9458 ins_encode( Push_Reg_DPR(src2), |
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9459 OpcP, RegOpc(src1), Pop_Mem_DPR(dst) ); |
| 0 | 9460 ins_pipe( fpu_mem_reg_reg ); |
| 9461 %} | |
| 9462 | |
| 9463 | |
|
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9464 instruct subDPR_reg_mem(regDPR dst, memory src) %{ |
| 0 | 9465 predicate (UseSSE <=1); |
| 9466 match(Set dst (SubD dst (LoadD src))); | |
| 9467 ins_cost(150); | |
| 9468 | |
| 9469 format %{ "FLD $src\n\t" | |
| 9470 "DSUBp $dst,ST" %} | |
| 9471 opcode(0xDE, 0x5, 0xDD); /* DE C0+i */ /* LoadD DD /0 */ | |
| 9472 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src), | |
| 9473 OpcP, RegOpc(dst) ); | |
| 9474 ins_pipe( fpu_reg_mem ); | |
| 9475 %} | |
| 9476 | |
|
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9477 instruct absDPR_reg(regDPR1 dst, regDPR1 src) %{ |
| 0 | 9478 predicate (UseSSE<=1); |
| 9479 match(Set dst (AbsD src)); | |
| 9480 ins_cost(100); | |
| 9481 format %{ "FABS" %} | |
| 9482 opcode(0xE1, 0xD9); | |
| 9483 ins_encode( OpcS, OpcP ); | |
| 9484 ins_pipe( fpu_reg_reg ); | |
| 9485 %} | |
| 9486 | |
|
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9487 instruct negDPR_reg(regDPR1 dst, regDPR1 src) %{ |
| 0 | 9488 predicate(UseSSE<=1); |
| 9489 match(Set dst (NegD src)); | |
| 9490 ins_cost(100); | |
| 9491 format %{ "FCHS" %} | |
| 9492 opcode(0xE0, 0xD9); | |
| 9493 ins_encode( OpcS, OpcP ); | |
| 9494 ins_pipe( fpu_reg_reg ); | |
| 9495 %} | |
| 9496 | |
|
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9497 instruct addDPR_reg(regDPR dst, regDPR src) %{ |
| 0 | 9498 predicate(UseSSE<=1); |
| 9499 match(Set dst (AddD dst src)); | |
| 9500 format %{ "FLD $src\n\t" | |
| 9501 "DADD $dst,ST" %} | |
| 9502 size(4); | |
| 9503 ins_cost(150); | |
| 9504 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/ | |
|
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9505 ins_encode( Push_Reg_DPR(src), |
| 0 | 9506 OpcP, RegOpc(dst) ); |
| 9507 ins_pipe( fpu_reg_reg ); | |
| 9508 %} | |
| 9509 | |
| 9510 | |
|
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9511 instruct addDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{ |
| 0 | 9512 predicate(UseSSE<=1); |
| 9513 match(Set dst (RoundDouble (AddD src1 src2))); | |
| 9514 ins_cost(250); | |
| 9515 | |
| 9516 format %{ "FLD $src2\n\t" | |
| 9517 "DADD ST,$src1\n\t" | |
| 9518 "FSTP_D $dst\t# D-round" %} | |
| 9519 opcode(0xD8, 0x0); /* D8 C0+i or D8 /0*/ | |
|
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9520 ins_encode( Push_Reg_DPR(src2), |
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9521 OpcP, RegOpc(src1), Pop_Mem_DPR(dst) ); |
| 0 | 9522 ins_pipe( fpu_mem_reg_reg ); |
| 9523 %} | |
| 9524 | |
| 9525 | |
|
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9526 instruct addDPR_reg_mem(regDPR dst, memory src) %{ |
| 0 | 9527 predicate(UseSSE<=1); |
| 9528 match(Set dst (AddD dst (LoadD src))); | |
| 9529 ins_cost(150); | |
| 9530 | |
| 9531 format %{ "FLD $src\n\t" | |
| 9532 "DADDp $dst,ST" %} | |
| 9533 opcode(0xDE, 0x0, 0xDD); /* DE C0+i */ /* LoadD DD /0 */ | |
| 9534 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src), | |
| 9535 OpcP, RegOpc(dst) ); | |
| 9536 ins_pipe( fpu_reg_mem ); | |
| 9537 %} | |
| 9538 | |
| 9539 // add-to-memory | |
|
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9540 instruct addDPR_mem_reg(memory dst, regDPR src) %{ |
| 0 | 9541 predicate(UseSSE<=1); |
| 9542 match(Set dst (StoreD dst (RoundDouble (AddD (LoadD dst) src)))); | |
| 9543 ins_cost(150); | |
| 9544 | |
| 9545 format %{ "FLD_D $dst\n\t" | |
| 9546 "DADD ST,$src\n\t" | |
| 9547 "FST_D $dst" %} | |
| 9548 opcode(0xDD, 0x0); | |
| 9549 ins_encode( Opcode(0xDD), RMopc_Mem(0x00,dst), | |
| 9550 Opcode(0xD8), RegOpc(src), | |
| 9551 set_instruction_start, | |
| 9552 Opcode(0xDD), RMopc_Mem(0x03,dst) ); | |
| 9553 ins_pipe( fpu_reg_mem ); | |
| 9554 %} | |
| 9555 | |
|
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9556 instruct addDPR_reg_imm1(regDPR dst, immDPR1 con) %{ |
| 0 | 9557 predicate(UseSSE<=1); |
| 2008 | 9558 match(Set dst (AddD dst con)); |
| 0 | 9559 ins_cost(125); |
| 9560 format %{ "FLD1\n\t" | |
| 9561 "DADDp $dst,ST" %} | |
| 2008 | 9562 ins_encode %{ |
| 9563 __ fld1(); | |
| 9564 __ faddp($dst$$reg); | |
| 9565 %} | |
| 9566 ins_pipe(fpu_reg); | |
| 9567 %} | |
| 9568 | |
|
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9569 instruct addDPR_reg_imm(regDPR dst, immDPR con) %{ |
| 0 | 9570 predicate(UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 ); |
| 2008 | 9571 match(Set dst (AddD dst con)); |
| 0 | 9572 ins_cost(200); |
| 2008 | 9573 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t" |
| 0 | 9574 "DADDp $dst,ST" %} |
| 2008 | 9575 ins_encode %{ |
| 9576 __ fld_d($constantaddress($con)); | |
| 9577 __ faddp($dst$$reg); | |
| 9578 %} | |
| 9579 ins_pipe(fpu_reg_mem); | |
| 0 | 9580 %} |
| 9581 | |
|
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9582 instruct addDPR_reg_imm_round(stackSlotD dst, regDPR src, immDPR con) %{ |
| 0 | 9583 predicate(UseSSE<=1 && _kids[0]->_kids[1]->_leaf->getd() != 0.0 && _kids[0]->_kids[1]->_leaf->getd() != 1.0 ); |
| 9584 match(Set dst (RoundDouble (AddD src con))); | |
| 9585 ins_cost(200); | |
| 2008 | 9586 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t" |
| 0 | 9587 "DADD ST,$src\n\t" |
| 9588 "FSTP_D $dst\t# D-round" %} | |
| 2008 | 9589 ins_encode %{ |
| 9590 __ fld_d($constantaddress($con)); | |
| 9591 __ fadd($src$$reg); | |
| 9592 __ fstp_d(Address(rsp, $dst$$disp)); | |
| 9593 %} | |
| 9594 ins_pipe(fpu_mem_reg_con); | |
| 0 | 9595 %} |
| 9596 | |
|
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9597 instruct mulDPR_reg(regDPR dst, regDPR src) %{ |
| 0 | 9598 predicate(UseSSE<=1); |
| 9599 match(Set dst (MulD dst src)); | |
| 9600 format %{ "FLD $src\n\t" | |
| 9601 "DMULp $dst,ST" %} | |
| 9602 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/ | |
| 9603 ins_cost(150); | |
|
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9604 ins_encode( Push_Reg_DPR(src), |
| 0 | 9605 OpcP, RegOpc(dst) ); |
| 9606 ins_pipe( fpu_reg_reg ); | |
| 9607 %} | |
| 9608 | |
| 9609 // Strict FP instruction biases argument before multiply then | |
| 9610 // biases result to avoid double rounding of subnormals. | |
| 9611 // | |
| 9612 // scale arg1 by multiplying arg1 by 2^(-15360) | |
| 9613 // load arg2 | |
| 9614 // multiply scaled arg1 by arg2 | |
| 9615 // rescale product by 2^(15360) | |
| 9616 // | |
|
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9617 instruct strictfp_mulDPR_reg(regDPR1 dst, regnotDPR1 src) %{ |
| 0 | 9618 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() ); |
| 9619 match(Set dst (MulD dst src)); | |
| 9620 ins_cost(1); // Select this instruction for all strict FP double multiplies | |
| 9621 | |
| 9622 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t" | |
| 9623 "DMULp $dst,ST\n\t" | |
| 9624 "FLD $src\n\t" | |
| 9625 "DMULp $dst,ST\n\t" | |
| 9626 "FLD StubRoutines::_fpu_subnormal_bias2\n\t" | |
| 9627 "DMULp $dst,ST\n\t" %} | |
| 9628 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/ | |
| 9629 ins_encode( strictfp_bias1(dst), | |
|
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9630 Push_Reg_DPR(src), |
| 0 | 9631 OpcP, RegOpc(dst), |
| 9632 strictfp_bias2(dst) ); | |
| 9633 ins_pipe( fpu_reg_reg ); | |
| 9634 %} | |
| 9635 | |
|
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9636 instruct mulDPR_reg_imm(regDPR dst, immDPR con) %{ |
| 0 | 9637 predicate( UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 ); |
| 2008 | 9638 match(Set dst (MulD dst con)); |
| 0 | 9639 ins_cost(200); |
| 2008 | 9640 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t" |
| 0 | 9641 "DMULp $dst,ST" %} |
| 2008 | 9642 ins_encode %{ |
| 9643 __ fld_d($constantaddress($con)); | |
| 9644 __ fmulp($dst$$reg); | |
| 9645 %} | |
| 9646 ins_pipe(fpu_reg_mem); | |
| 0 | 9647 %} |
| 9648 | |
| 9649 | |
|
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9650 instruct mulDPR_reg_mem(regDPR dst, memory src) %{ |
| 0 | 9651 predicate( UseSSE<=1 ); |
| 9652 match(Set dst (MulD dst (LoadD src))); | |
| 9653 ins_cost(200); | |
| 9654 format %{ "FLD_D $src\n\t" | |
| 9655 "DMULp $dst,ST" %} | |
| 9656 opcode(0xDE, 0x1, 0xDD); /* DE C8+i or DE /1*/ /* LoadD DD /0 */ | |
| 9657 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src), | |
| 9658 OpcP, RegOpc(dst) ); | |
| 9659 ins_pipe( fpu_reg_mem ); | |
| 9660 %} | |
| 9661 | |
| 9662 // | |
| 9663 // Cisc-alternate to reg-reg multiply | |
|
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9664 instruct mulDPR_reg_mem_cisc(regDPR dst, regDPR src, memory mem) %{ |
| 0 | 9665 predicate( UseSSE<=1 ); |
| 9666 match(Set dst (MulD src (LoadD mem))); | |
| 9667 ins_cost(250); | |
| 9668 format %{ "FLD_D $mem\n\t" | |
| 9669 "DMUL ST,$src\n\t" | |
| 9670 "FSTP_D $dst" %} | |
| 9671 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadD D9 /0 */ | |
| 9672 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem), | |
|
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9673 OpcReg_FPR(src), |
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9674 Pop_Reg_DPR(dst) ); |
| 0 | 9675 ins_pipe( fpu_reg_reg_mem ); |
| 9676 %} | |
| 9677 | |
| 9678 | |
|
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9679 // MACRO3 -- addDPR a mulDPR |
| 0 | 9680 // This instruction is a '2-address' instruction in that the result goes |
| 9681 // back to src2. This eliminates a move from the macro; possibly the | |
| 9682 // register allocator will have to add it back (and maybe not). | |
|
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9683 instruct addDPR_mulDPR_reg(regDPR src2, regDPR src1, regDPR src0) %{ |
| 0 | 9684 predicate( UseSSE<=1 ); |
| 9685 match(Set src2 (AddD (MulD src0 src1) src2)); | |
| 9686 format %{ "FLD $src0\t# ===MACRO3d===\n\t" | |
| 9687 "DMUL ST,$src1\n\t" | |
| 9688 "DADDp $src2,ST" %} | |
| 9689 ins_cost(250); | |
| 9690 opcode(0xDD); /* LoadD DD /0 */ | |
|
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9691 ins_encode( Push_Reg_FPR(src0), |
| 0 | 9692 FMul_ST_reg(src1), |
| 9693 FAddP_reg_ST(src2) ); | |
| 9694 ins_pipe( fpu_reg_reg_reg ); | |
| 9695 %} | |
| 9696 | |
| 9697 | |
|
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9698 // MACRO3 -- subDPR a mulDPR |
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9699 instruct subDPR_mulDPR_reg(regDPR src2, regDPR src1, regDPR src0) %{ |
| 0 | 9700 predicate( UseSSE<=1 ); |
| 9701 match(Set src2 (SubD (MulD src0 src1) src2)); | |
| 9702 format %{ "FLD $src0\t# ===MACRO3d===\n\t" | |
| 9703 "DMUL ST,$src1\n\t" | |
| 9704 "DSUBRp $src2,ST" %} | |
| 9705 ins_cost(250); | |
|
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9706 ins_encode( Push_Reg_FPR(src0), |
| 0 | 9707 FMul_ST_reg(src1), |
| 9708 Opcode(0xDE), Opc_plus(0xE0,src2)); | |
| 9709 ins_pipe( fpu_reg_reg_reg ); | |
| 9710 %} | |
| 9711 | |
| 9712 | |
|
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9713 instruct divDPR_reg(regDPR dst, regDPR src) %{ |
| 0 | 9714 predicate( UseSSE<=1 ); |
| 9715 match(Set dst (DivD dst src)); | |
| 9716 | |
| 9717 format %{ "FLD $src\n\t" | |
| 9718 "FDIVp $dst,ST" %} | |
| 9719 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/ | |
| 9720 ins_cost(150); | |
|
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9721 ins_encode( Push_Reg_DPR(src), |
| 0 | 9722 OpcP, RegOpc(dst) ); |
| 9723 ins_pipe( fpu_reg_reg ); | |
| 9724 %} | |
| 9725 | |
| 9726 // Strict FP instruction biases argument before division then | |
| 9727 // biases result, to avoid double rounding of subnormals. | |
| 9728 // | |
| 9729 // scale dividend by multiplying dividend by 2^(-15360) | |
| 9730 // load divisor | |
| 9731 // divide scaled dividend by divisor | |
| 9732 // rescale quotient by 2^(15360) | |
| 9733 // | |
|
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9734 instruct strictfp_divDPR_reg(regDPR1 dst, regnotDPR1 src) %{ |
| 0 | 9735 predicate (UseSSE<=1); |
| 9736 match(Set dst (DivD dst src)); | |
| 9737 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() ); | |
| 9738 ins_cost(01); | |
| 9739 | |
| 9740 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t" | |
| 9741 "DMULp $dst,ST\n\t" | |
| 9742 "FLD $src\n\t" | |
| 9743 "FDIVp $dst,ST\n\t" | |
| 9744 "FLD StubRoutines::_fpu_subnormal_bias2\n\t" | |
| 9745 "DMULp $dst,ST\n\t" %} | |
| 9746 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/ | |
| 9747 ins_encode( strictfp_bias1(dst), | |
|
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diff
changeset
|
9748 Push_Reg_DPR(src), |
| 0 | 9749 OpcP, RegOpc(dst), |
| 9750 strictfp_bias2(dst) ); | |
| 9751 ins_pipe( fpu_reg_reg ); | |
| 9752 %} | |
| 9753 | |
|
4761
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diff
changeset
|
9754 instruct divDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{ |
| 0 | 9755 predicate( UseSSE<=1 && !(Compile::current()->has_method() && Compile::current()->method()->is_strict()) ); |
| 9756 match(Set dst (RoundDouble (DivD src1 src2))); | |
| 9757 | |
| 9758 format %{ "FLD $src1\n\t" | |
| 9759 "FDIV ST,$src2\n\t" | |
| 9760 "FSTP_D $dst\t# D-round" %} | |
| 9761 opcode(0xD8, 0x6); /* D8 F0+i or D8 /6 */ | |
|
4761
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diff
changeset
|
9762 ins_encode( Push_Reg_DPR(src1), |
|
65149e74c706
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diff
changeset
|
9763 OpcP, RegOpc(src2), Pop_Mem_DPR(dst) ); |
| 0 | 9764 ins_pipe( fpu_mem_reg_reg ); |
| 9765 %} | |
| 9766 | |
| 9767 | |
|
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|
9768 instruct modDPR_reg(regDPR dst, regDPR src, eAXRegI rax, eFlagsReg cr) %{ |
| 0 | 9769 predicate(UseSSE<=1); |
| 9770 match(Set dst (ModD dst src)); | |
|
4761
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diff
changeset
|
9771 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS |
| 0 | 9772 |
| 9773 format %{ "DMOD $dst,$src" %} | |
| 9774 ins_cost(250); | |
|
4761
65149e74c706
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diff
changeset
|
9775 ins_encode(Push_Reg_Mod_DPR(dst, src), |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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diff
changeset
|
9776 emitModDPR(), |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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diff
changeset
|
9777 Push_Result_Mod_DPR(src), |
|
65149e74c706
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diff
changeset
|
9778 Pop_Reg_DPR(dst)); |
|
65149e74c706
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diff
changeset
|
9779 ins_pipe( pipe_slow ); |
|
65149e74c706
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diff
changeset
|
9780 %} |
|
65149e74c706
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diff
changeset
|
9781 |
|
65149e74c706
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changeset
|
9782 instruct modD_reg(regD dst, regD src0, regD src1, eAXRegI rax, eFlagsReg cr) %{ |
| 0 | 9783 predicate(UseSSE>=2); |
| 9784 match(Set dst (ModD src0 src1)); | |
| 9785 effect(KILL rax, KILL cr); | |
| 9786 | |
| 9787 format %{ "SUB ESP,8\t # DMOD\n" | |
| 9788 "\tMOVSD [ESP+0],$src1\n" | |
| 9789 "\tFLD_D [ESP+0]\n" | |
| 9790 "\tMOVSD [ESP+0],$src0\n" | |
| 9791 "\tFLD_D [ESP+0]\n" | |
| 9792 "loop:\tFPREM\n" | |
| 9793 "\tFWAIT\n" | |
| 9794 "\tFNSTSW AX\n" | |
| 9795 "\tSAHF\n" | |
| 9796 "\tJP loop\n" | |
| 9797 "\tFSTP_D [ESP+0]\n" | |
| 9798 "\tMOVSD $dst,[ESP+0]\n" | |
| 9799 "\tADD ESP,8\n" | |
| 9800 "\tFSTP ST0\t # Restore FPU Stack" | |
| 9801 %} | |
| 9802 ins_cost(250); | |
|
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changeset
|
9803 ins_encode( Push_ModD_encoding(src0, src1), emitModDPR(), Push_ResultD(dst), PopFPU); |
|
65149e74c706
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changeset
|
9804 ins_pipe( pipe_slow ); |
|
65149e74c706
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kvn
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diff
changeset
|
9805 %} |
|
65149e74c706
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diff
changeset
|
9806 |
|
65149e74c706
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changeset
|
9807 instruct sinDPR_reg(regDPR1 dst, regDPR1 src) %{ |
| 0 | 9808 predicate (UseSSE<=1); |
| 9809 match(Set dst (SinD src)); | |
| 9810 ins_cost(1800); | |
| 9811 format %{ "DSIN $dst" %} | |
| 9812 opcode(0xD9, 0xFE); | |
| 9813 ins_encode( OpcP, OpcS ); | |
| 9814 ins_pipe( pipe_slow ); | |
| 9815 %} | |
| 9816 | |
|
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changeset
|
9817 instruct sinD_reg(regD dst, eFlagsReg cr) %{ |
| 0 | 9818 predicate (UseSSE>=2); |
| 9819 match(Set dst (SinD dst)); | |
|
4761
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changeset
|
9820 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8" |
| 0 | 9821 ins_cost(1800); |
| 9822 format %{ "DSIN $dst" %} | |
| 9823 opcode(0xD9, 0xFE); | |
|
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diff
changeset
|
9824 ins_encode( Push_SrcD(dst), OpcP, OpcS, Push_ResultD(dst) ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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changeset
|
9825 ins_pipe( pipe_slow ); |
|
65149e74c706
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kvn
parents:
4759
diff
changeset
|
9826 %} |
|
65149e74c706
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kvn
parents:
4759
diff
changeset
|
9827 |
|
65149e74c706
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diff
changeset
|
9828 instruct cosDPR_reg(regDPR1 dst, regDPR1 src) %{ |
| 0 | 9829 predicate (UseSSE<=1); |
| 9830 match(Set dst (CosD src)); | |
| 9831 ins_cost(1800); | |
| 9832 format %{ "DCOS $dst" %} | |
| 9833 opcode(0xD9, 0xFF); | |
| 9834 ins_encode( OpcP, OpcS ); | |
| 9835 ins_pipe( pipe_slow ); | |
| 9836 %} | |
| 9837 | |
|
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diff
changeset
|
9838 instruct cosD_reg(regD dst, eFlagsReg cr) %{ |
| 0 | 9839 predicate (UseSSE>=2); |
| 9840 match(Set dst (CosD dst)); | |
|
4761
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diff
changeset
|
9841 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8" |
| 0 | 9842 ins_cost(1800); |
| 9843 format %{ "DCOS $dst" %} | |
| 9844 opcode(0xD9, 0xFF); | |
|
4761
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4759
diff
changeset
|
9845 ins_encode( Push_SrcD(dst), OpcP, OpcS, Push_ResultD(dst) ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
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4759
diff
changeset
|
9846 ins_pipe( pipe_slow ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9847 %} |
|
65149e74c706
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kvn
parents:
4759
diff
changeset
|
9848 |
|
65149e74c706
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parents:
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diff
changeset
|
9849 instruct tanDPR_reg(regDPR1 dst, regDPR1 src) %{ |
| 0 | 9850 predicate (UseSSE<=1); |
| 9851 match(Set dst(TanD src)); | |
| 9852 format %{ "DTAN $dst" %} | |
| 9853 ins_encode( Opcode(0xD9), Opcode(0xF2), // fptan | |
| 9854 Opcode(0xDD), Opcode(0xD8)); // fstp st | |
| 9855 ins_pipe( pipe_slow ); | |
| 9856 %} | |
| 9857 | |
|
4761
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diff
changeset
|
9858 instruct tanD_reg(regD dst, eFlagsReg cr) %{ |
| 0 | 9859 predicate (UseSSE>=2); |
| 9860 match(Set dst(TanD dst)); | |
|
4761
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diff
changeset
|
9861 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8" |
| 0 | 9862 format %{ "DTAN $dst" %} |
|
4761
65149e74c706
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diff
changeset
|
9863 ins_encode( Push_SrcD(dst), |
| 0 | 9864 Opcode(0xD9), Opcode(0xF2), // fptan |
| 9865 Opcode(0xDD), Opcode(0xD8), // fstp st | |
|
4761
65149e74c706
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4759
diff
changeset
|
9866 Push_ResultD(dst) ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
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4759
diff
changeset
|
9867 ins_pipe( pipe_slow ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9868 %} |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9869 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9870 instruct atanDPR_reg(regDPR dst, regDPR src) %{ |
| 0 | 9871 predicate (UseSSE<=1); |
| 9872 match(Set dst(AtanD dst src)); | |
| 9873 format %{ "DATA $dst,$src" %} | |
| 9874 opcode(0xD9, 0xF3); | |
|
4761
65149e74c706
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kvn
parents:
4759
diff
changeset
|
9875 ins_encode( Push_Reg_DPR(src), |
| 0 | 9876 OpcP, OpcS, RegOpc(dst) ); |
| 9877 ins_pipe( pipe_slow ); | |
| 9878 %} | |
| 9879 | |
|
4761
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kvn
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4759
diff
changeset
|
9880 instruct atanD_reg(regD dst, regD src, eFlagsReg cr) %{ |
| 0 | 9881 predicate (UseSSE>=2); |
| 9882 match(Set dst(AtanD dst src)); | |
|
4761
65149e74c706
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kvn
parents:
4759
diff
changeset
|
9883 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8" |
| 0 | 9884 format %{ "DATA $dst,$src" %} |
| 9885 opcode(0xD9, 0xF3); | |
|
4761
65149e74c706
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parents:
4759
diff
changeset
|
9886 ins_encode( Push_SrcD(src), |
|
65149e74c706
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kvn
parents:
4759
diff
changeset
|
9887 OpcP, OpcS, Push_ResultD(dst) ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9888 ins_pipe( pipe_slow ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9889 %} |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9890 |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9891 instruct sqrtDPR_reg(regDPR dst, regDPR src) %{ |
| 0 | 9892 predicate (UseSSE<=1); |
| 9893 match(Set dst (SqrtD src)); | |
| 9894 format %{ "DSQRT $dst,$src" %} | |
| 9895 opcode(0xFA, 0xD9); | |
|
4761
65149e74c706
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kvn
parents:
4759
diff
changeset
|
9896 ins_encode( Push_Reg_DPR(src), |
|
65149e74c706
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kvn
parents:
4759
diff
changeset
|
9897 OpcS, OpcP, Pop_Reg_DPR(dst) ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9898 ins_pipe( pipe_slow ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9899 %} |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
9900 |
|
6084
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9901 instruct powDPR_reg(regDPR X, regDPR1 Y, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{ |
| 0 | 9902 predicate (UseSSE<=1); |
| 9903 match(Set Y (PowD X Y)); // Raise X to the Yth power | |
|
6084
6759698e3140
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roland
parents:
5934
diff
changeset
|
9904 effect(KILL rax, KILL rdx, KILL rcx, KILL cr); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9905 format %{ "fast_pow $X $Y -> $Y // KILL $rax, $rcx, $rdx" %} |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9906 ins_encode %{ |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9907 __ subptr(rsp, 8); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9908 __ fld_s($X$$reg - 1); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9909 __ fast_pow(); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9910 __ addptr(rsp, 8); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9911 %} |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9912 ins_pipe( pipe_slow ); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9913 %} |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9914 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9915 instruct powD_reg(regD dst, regD src0, regD src1, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{ |
| 0 | 9916 predicate (UseSSE>=2); |
| 9917 match(Set dst (PowD src0 src1)); // Raise src0 to the src1'th power | |
|
6084
6759698e3140
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roland
parents:
5934
diff
changeset
|
9918 effect(KILL rax, KILL rdx, KILL rcx, KILL cr); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9919 format %{ "fast_pow $src0 $src1 -> $dst // KILL $rax, $rcx, $rdx" %} |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9920 ins_encode %{ |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9921 __ subptr(rsp, 8); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9922 __ movdbl(Address(rsp, 0), $src1$$XMMRegister); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9923 __ fld_d(Address(rsp, 0)); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9924 __ movdbl(Address(rsp, 0), $src0$$XMMRegister); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9925 __ fld_d(Address(rsp, 0)); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9926 __ fast_pow(); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9927 __ fstp_d(Address(rsp, 0)); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9928 __ movdbl($dst$$XMMRegister, Address(rsp, 0)); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9929 __ addptr(rsp, 8); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9930 %} |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9931 ins_pipe( pipe_slow ); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9932 %} |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9933 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9934 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9935 instruct expDPR_reg(regDPR1 dpr1, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{ |
| 0 | 9936 predicate (UseSSE<=1); |
| 9937 match(Set dpr1 (ExpD dpr1)); | |
|
6084
6759698e3140
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roland
parents:
5934
diff
changeset
|
9938 effect(KILL rax, KILL rcx, KILL rdx, KILL cr); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9939 format %{ "fast_exp $dpr1 -> $dpr1 // KILL $rax, $rcx, $rdx" %} |
|
6759698e3140
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diff
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|
9940 ins_encode %{ |
|
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diff
changeset
|
9941 __ fast_exp(); |
|
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5934
diff
changeset
|
9942 %} |
|
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diff
changeset
|
9943 ins_pipe( pipe_slow ); |
|
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roland
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5934
diff
changeset
|
9944 %} |
|
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diff
changeset
|
9945 |
|
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diff
changeset
|
9946 instruct expD_reg(regD dst, regD src, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{ |
| 0 | 9947 predicate (UseSSE>=2); |
| 9948 match(Set dst (ExpD src)); | |
|
6084
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diff
changeset
|
9949 effect(KILL rax, KILL rcx, KILL rdx, KILL cr); |
|
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|
9950 format %{ "fast_exp $dst -> $src // KILL $rax, $rcx, $rdx" %} |
|
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diff
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|
9951 ins_encode %{ |
|
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|
9952 __ subptr(rsp, 8); |
|
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|
9953 __ movdbl(Address(rsp, 0), $src$$XMMRegister); |
|
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|
9954 __ fld_d(Address(rsp, 0)); |
|
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diff
changeset
|
9955 __ fast_exp(); |
|
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5934
diff
changeset
|
9956 __ fstp_d(Address(rsp, 0)); |
|
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|
9957 __ movdbl($dst$$XMMRegister, Address(rsp, 0)); |
|
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|
9958 __ addptr(rsp, 8); |
|
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diff
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|
9959 %} |
|
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changeset
|
9960 ins_pipe( pipe_slow ); |
|
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diff
changeset
|
9961 %} |
|
4761
65149e74c706
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diff
changeset
|
9962 |
|
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|
9963 instruct log10DPR_reg(regDPR1 dst, regDPR1 src) %{ |
| 0 | 9964 predicate (UseSSE<=1); |
| 9965 // The source Double operand on FPU stack | |
| 9966 match(Set dst (Log10D src)); | |
| 9967 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number | |
| 9968 // fxch ; swap ST(0) with ST(1) | |
| 9969 // fyl2x ; compute log_10(2) * log_2(x) | |
| 9970 format %{ "FLDLG2 \t\t\t#Log10\n\t" | |
| 9971 "FXCH \n\t" | |
| 9972 "FYL2X \t\t\t# Q=Log10*Log_2(x)" | |
| 9973 %} | |
| 9974 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2 | |
| 9975 Opcode(0xD9), Opcode(0xC9), // fxch | |
| 9976 Opcode(0xD9), Opcode(0xF1)); // fyl2x | |
| 9977 | |
| 9978 ins_pipe( pipe_slow ); | |
| 9979 %} | |
| 9980 | |
|
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|
9981 instruct log10D_reg(regD dst, regD src, eFlagsReg cr) %{ |
| 0 | 9982 predicate (UseSSE>=2); |
| 9983 effect(KILL cr); | |
| 9984 match(Set dst (Log10D src)); | |
| 9985 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number | |
| 9986 // fyl2x ; compute log_10(2) * log_2(x) | |
| 9987 format %{ "FLDLG2 \t\t\t#Log10\n\t" | |
| 9988 "FYL2X \t\t\t# Q=Log10*Log_2(x)" | |
| 9989 %} | |
| 9990 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2 | |
|
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|
9991 Push_SrcD(src), |
| 0 | 9992 Opcode(0xD9), Opcode(0xF1), // fyl2x |
|
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|
9993 Push_ResultD(dst)); |
|
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changeset
|
9994 |
|
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changeset
|
9995 ins_pipe( pipe_slow ); |
|
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diff
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|
9996 %} |
|
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|
9997 |
|
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|
9998 instruct logDPR_reg(regDPR1 dst, regDPR1 src) %{ |
| 0 | 9999 predicate (UseSSE<=1); |
| 10000 // The source Double operand on FPU stack | |
| 10001 match(Set dst (LogD src)); | |
| 10002 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number | |
| 10003 // fxch ; swap ST(0) with ST(1) | |
| 10004 // fyl2x ; compute log_e(2) * log_2(x) | |
| 10005 format %{ "FLDLN2 \t\t\t#Log_e\n\t" | |
| 10006 "FXCH \n\t" | |
| 10007 "FYL2X \t\t\t# Q=Log_e*Log_2(x)" | |
| 10008 %} | |
| 10009 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2 | |
| 10010 Opcode(0xD9), Opcode(0xC9), // fxch | |
| 10011 Opcode(0xD9), Opcode(0xF1)); // fyl2x | |
| 10012 | |
| 10013 ins_pipe( pipe_slow ); | |
| 10014 %} | |
| 10015 | |
|
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|
10016 instruct logD_reg(regD dst, regD src, eFlagsReg cr) %{ |
| 0 | 10017 predicate (UseSSE>=2); |
| 10018 effect(KILL cr); | |
| 10019 // The source and result Double operands in XMM registers | |
| 10020 match(Set dst (LogD src)); | |
| 10021 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number | |
| 10022 // fyl2x ; compute log_e(2) * log_2(x) | |
| 10023 format %{ "FLDLN2 \t\t\t#Log_e\n\t" | |
| 10024 "FYL2X \t\t\t# Q=Log_e*Log_2(x)" | |
| 10025 %} | |
| 10026 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2 | |
|
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|
10027 Push_SrcD(src), |
| 0 | 10028 Opcode(0xD9), Opcode(0xF1), // fyl2x |
|
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|
10029 Push_ResultD(dst)); |
| 0 | 10030 ins_pipe( pipe_slow ); |
| 10031 %} | |
| 10032 | |
| 10033 //-------------Float Instructions------------------------------- | |
| 10034 // Float Math | |
| 10035 | |
| 10036 // Code for float compare: | |
| 10037 // fcompp(); | |
| 10038 // fwait(); fnstsw_ax(); | |
| 10039 // sahf(); | |
| 10040 // movl(dst, unordered_result); | |
| 10041 // jcc(Assembler::parity, exit); | |
| 10042 // movl(dst, less_result); | |
| 10043 // jcc(Assembler::below, exit); | |
| 10044 // movl(dst, equal_result); | |
| 10045 // jcc(Assembler::equal, exit); | |
| 10046 // movl(dst, greater_result); | |
| 10047 // exit: | |
| 10048 | |
| 10049 // P6 version of float compare, sets condition codes in EFLAGS | |
|
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|
10050 instruct cmpFPR_cc_P6(eFlagsRegU cr, regFPR src1, regFPR src2, eAXRegI rax) %{ |
| 0 | 10051 predicate(VM_Version::supports_cmov() && UseSSE == 0); |
| 10052 match(Set cr (CmpF src1 src2)); | |
| 10053 effect(KILL rax); | |
| 10054 ins_cost(150); | |
| 10055 format %{ "FLD $src1\n\t" | |
| 10056 "FUCOMIP ST,$src2 // P6 instruction\n\t" | |
| 10057 "JNP exit\n\t" | |
| 10058 "MOV ah,1 // saw a NaN, set CF (treat as LT)\n\t" | |
| 10059 "SAHF\n" | |
| 10060 "exit:\tNOP // avoid branch to branch" %} | |
| 10061 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */ | |
|
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diff
changeset
|
10062 ins_encode( Push_Reg_DPR(src1), |
| 0 | 10063 OpcP, RegOpc(src2), |
| 10064 cmpF_P6_fixup ); | |
| 10065 ins_pipe( pipe_slow ); | |
| 10066 %} | |
| 10067 | |
|
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|
10068 instruct cmpFPR_cc_P6CF(eFlagsRegUCF cr, regFPR src1, regFPR src2) %{ |
|
415
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changeset
|
10069 predicate(VM_Version::supports_cmov() && UseSSE == 0); |
|
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changeset
|
10070 match(Set cr (CmpF src1 src2)); |
|
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diff
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|
10071 ins_cost(100); |
|
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diff
changeset
|
10072 format %{ "FLD $src1\n\t" |
|
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diff
changeset
|
10073 "FUCOMIP ST,$src2 // P6 instruction" %} |
|
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changeset
|
10074 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */ |
|
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|
10075 ins_encode( Push_Reg_DPR(src1), |
|
415
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changeset
|
10076 OpcP, RegOpc(src2)); |
|
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diff
changeset
|
10077 ins_pipe( pipe_slow ); |
|
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diff
changeset
|
10078 %} |
|
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changeset
|
10079 |
| 0 | 10080 |
| 10081 // Compare & branch | |
|
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|
10082 instruct cmpFPR_cc(eFlagsRegU cr, regFPR src1, regFPR src2, eAXRegI rax) %{ |
| 0 | 10083 predicate(UseSSE == 0); |
| 10084 match(Set cr (CmpF src1 src2)); | |
| 10085 effect(KILL rax); | |
| 10086 ins_cost(200); | |
| 10087 format %{ "FLD $src1\n\t" | |
| 10088 "FCOMp $src2\n\t" | |
| 10089 "FNSTSW AX\n\t" | |
| 10090 "TEST AX,0x400\n\t" | |
| 10091 "JZ,s flags\n\t" | |
| 10092 "MOV AH,1\t# unordered treat as LT\n" | |
| 10093 "flags:\tSAHF" %} | |
| 10094 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */ | |
|
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changeset
|
10095 ins_encode( Push_Reg_DPR(src1), |
| 0 | 10096 OpcP, RegOpc(src2), |
| 10097 fpu_flags); | |
| 10098 ins_pipe( pipe_slow ); | |
| 10099 %} | |
| 10100 | |
| 10101 // Compare vs zero into -1,0,1 | |
|
6179
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|
10102 instruct cmpFPR_0(rRegI dst, regFPR src1, immFPR0 zero, eAXRegI rax, eFlagsReg cr) %{ |
| 0 | 10103 predicate(UseSSE == 0); |
| 10104 match(Set dst (CmpF3 src1 zero)); | |
| 10105 effect(KILL cr, KILL rax); | |
| 10106 ins_cost(280); | |
| 10107 format %{ "FTSTF $dst,$src1" %} | |
| 10108 opcode(0xE4, 0xD9); | |
|
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|
10109 ins_encode( Push_Reg_DPR(src1), |
| 0 | 10110 OpcS, OpcP, PopFPU, |
| 10111 CmpF_Result(dst)); | |
| 10112 ins_pipe( pipe_slow ); | |
| 10113 %} | |
| 10114 | |
| 10115 // Compare into -1,0,1 | |
|
6179
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|
10116 instruct cmpFPR_reg(rRegI dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{ |
| 0 | 10117 predicate(UseSSE == 0); |
| 10118 match(Set dst (CmpF3 src1 src2)); | |
| 10119 effect(KILL cr, KILL rax); | |
| 10120 ins_cost(300); | |
| 10121 format %{ "FCMPF $dst,$src1,$src2" %} | |
| 10122 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */ | |
|
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changeset
|
10123 ins_encode( Push_Reg_DPR(src1), |
| 0 | 10124 OpcP, RegOpc(src2), |
| 10125 CmpF_Result(dst)); | |
| 10126 ins_pipe( pipe_slow ); | |
| 10127 %} | |
| 10128 | |
| 10129 // float compare and set condition codes in EFLAGS by XMM regs | |
|
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|
10130 instruct cmpF_cc(eFlagsRegU cr, regF src1, regF src2) %{ |
| 0 | 10131 predicate(UseSSE>=1); |
| 4759 | 10132 match(Set cr (CmpF src1 src2)); |
| 0 | 10133 ins_cost(145); |
| 4759 | 10134 format %{ "UCOMISS $src1,$src2\n\t" |
| 10135 "JNP,s exit\n\t" | |
| 10136 "PUSHF\t# saw NaN, set CF\n\t" | |
| 10137 "AND [rsp], #0xffffff2b\n\t" | |
| 10138 "POPF\n" | |
| 10139 "exit:" %} | |
| 10140 ins_encode %{ | |
| 10141 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister); | |
| 10142 emit_cmpfp_fixup(_masm); | |
| 10143 %} | |
| 10144 ins_pipe( pipe_slow ); | |
| 10145 %} | |
| 10146 | |
|
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|
10147 instruct cmpF_ccCF(eFlagsRegUCF cr, regF src1, regF src2) %{ |
|
415
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changeset
|
10148 predicate(UseSSE>=1); |
| 4759 | 10149 match(Set cr (CmpF src1 src2)); |
|
415
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changeset
|
10150 ins_cost(100); |
| 4759 | 10151 format %{ "UCOMISS $src1,$src2" %} |
| 10152 ins_encode %{ | |
| 10153 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister); | |
| 10154 %} | |
|
415
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diff
changeset
|
10155 ins_pipe( pipe_slow ); |
|
4d9884b01ba6
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diff
changeset
|
10156 %} |
|
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diff
changeset
|
10157 |
| 0 | 10158 // float compare and set condition codes in EFLAGS by XMM regs |
|
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|
10159 instruct cmpF_ccmem(eFlagsRegU cr, regF src1, memory src2) %{ |
| 0 | 10160 predicate(UseSSE>=1); |
| 4759 | 10161 match(Set cr (CmpF src1 (LoadF src2))); |
| 0 | 10162 ins_cost(165); |
| 4759 | 10163 format %{ "UCOMISS $src1,$src2\n\t" |
| 10164 "JNP,s exit\n\t" | |
| 10165 "PUSHF\t# saw NaN, set CF\n\t" | |
| 10166 "AND [rsp], #0xffffff2b\n\t" | |
| 10167 "POPF\n" | |
| 10168 "exit:" %} | |
| 10169 ins_encode %{ | |
| 10170 __ ucomiss($src1$$XMMRegister, $src2$$Address); | |
| 10171 emit_cmpfp_fixup(_masm); | |
| 10172 %} | |
| 10173 ins_pipe( pipe_slow ); | |
| 10174 %} | |
| 10175 | |
|
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changeset
|
10176 instruct cmpF_ccmemCF(eFlagsRegUCF cr, regF src1, memory src2) %{ |
|
415
4d9884b01ba6
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diff
changeset
|
10177 predicate(UseSSE>=1); |
| 4759 | 10178 match(Set cr (CmpF src1 (LoadF src2))); |
|
415
4d9884b01ba6
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diff
changeset
|
10179 ins_cost(100); |
| 4759 | 10180 format %{ "UCOMISS $src1,$src2" %} |
| 10181 ins_encode %{ | |
| 10182 __ ucomiss($src1$$XMMRegister, $src2$$Address); | |
| 10183 %} | |
|
415
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diff
changeset
|
10184 ins_pipe( pipe_slow ); |
|
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diff
changeset
|
10185 %} |
|
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diff
changeset
|
10186 |
| 0 | 10187 // Compare into -1,0,1 in XMM |
|
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10188 instruct cmpF_reg(xRegI dst, regF src1, regF src2, eFlagsReg cr) %{ |
| 0 | 10189 predicate(UseSSE>=1); |
| 10190 match(Set dst (CmpF3 src1 src2)); | |
| 10191 effect(KILL cr); | |
| 10192 ins_cost(255); | |
| 4759 | 10193 format %{ "UCOMISS $src1, $src2\n\t" |
| 10194 "MOV $dst, #-1\n\t" | |
| 10195 "JP,s done\n\t" | |
| 10196 "JB,s done\n\t" | |
| 10197 "SETNE $dst\n\t" | |
| 10198 "MOVZB $dst, $dst\n" | |
| 10199 "done:" %} | |
| 10200 ins_encode %{ | |
| 10201 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister); | |
| 10202 emit_cmpfp3(_masm, $dst$$Register); | |
| 10203 %} | |
| 0 | 10204 ins_pipe( pipe_slow ); |
| 10205 %} | |
| 10206 | |
| 10207 // Compare into -1,0,1 in XMM and memory | |
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10208 instruct cmpF_regmem(xRegI dst, regF src1, memory src2, eFlagsReg cr) %{ |
| 0 | 10209 predicate(UseSSE>=1); |
| 4759 | 10210 match(Set dst (CmpF3 src1 (LoadF src2))); |
| 0 | 10211 effect(KILL cr); |
| 10212 ins_cost(275); | |
| 4759 | 10213 format %{ "UCOMISS $src1, $src2\n\t" |
| 10214 "MOV $dst, #-1\n\t" | |
| 10215 "JP,s done\n\t" | |
| 10216 "JB,s done\n\t" | |
| 10217 "SETNE $dst\n\t" | |
| 10218 "MOVZB $dst, $dst\n" | |
| 10219 "done:" %} | |
| 10220 ins_encode %{ | |
| 10221 __ ucomiss($src1$$XMMRegister, $src2$$Address); | |
| 10222 emit_cmpfp3(_masm, $dst$$Register); | |
| 10223 %} | |
| 0 | 10224 ins_pipe( pipe_slow ); |
| 10225 %} | |
| 10226 | |
| 10227 // Spill to obtain 24-bit precision | |
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10228 instruct subFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{ |
| 0 | 10229 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10230 match(Set dst (SubF src1 src2)); | |
| 10231 | |
| 10232 format %{ "FSUB $dst,$src1 - $src2" %} | |
| 10233 opcode(0xD8, 0x4); /* D8 E0+i or D8 /4 mod==0x3 ;; result in TOS */ | |
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10234 ins_encode( Push_Reg_FPR(src1), |
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10235 OpcReg_FPR(src2), |
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10236 Pop_Mem_FPR(dst) ); |
| 0 | 10237 ins_pipe( fpu_mem_reg_reg ); |
| 10238 %} | |
| 10239 // | |
| 10240 // This instruction does not round to 24-bits | |
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10241 instruct subFPR_reg(regFPR dst, regFPR src) %{ |
| 0 | 10242 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10243 match(Set dst (SubF dst src)); | |
| 10244 | |
| 10245 format %{ "FSUB $dst,$src" %} | |
| 10246 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */ | |
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10247 ins_encode( Push_Reg_FPR(src), |
| 0 | 10248 OpcP, RegOpc(dst) ); |
| 10249 ins_pipe( fpu_reg_reg ); | |
| 10250 %} | |
| 10251 | |
| 10252 // Spill to obtain 24-bit precision | |
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10253 instruct addFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{ |
| 0 | 10254 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10255 match(Set dst (AddF src1 src2)); | |
| 10256 | |
| 10257 format %{ "FADD $dst,$src1,$src2" %} | |
| 10258 opcode(0xD8, 0x0); /* D8 C0+i */ | |
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10259 ins_encode( Push_Reg_FPR(src2), |
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10260 OpcReg_FPR(src1), |
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10261 Pop_Mem_FPR(dst) ); |
| 0 | 10262 ins_pipe( fpu_mem_reg_reg ); |
| 10263 %} | |
| 10264 // | |
| 10265 // This instruction does not round to 24-bits | |
|
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10266 instruct addFPR_reg(regFPR dst, regFPR src) %{ |
| 0 | 10267 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10268 match(Set dst (AddF dst src)); | |
| 10269 | |
| 10270 format %{ "FLD $src\n\t" | |
| 10271 "FADDp $dst,ST" %} | |
| 10272 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/ | |
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10273 ins_encode( Push_Reg_FPR(src), |
| 0 | 10274 OpcP, RegOpc(dst) ); |
| 10275 ins_pipe( fpu_reg_reg ); | |
| 10276 %} | |
| 10277 | |
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10278 instruct absFPR_reg(regFPR1 dst, regFPR1 src) %{ |
| 0 | 10279 predicate(UseSSE==0); |
| 10280 match(Set dst (AbsF src)); | |
| 10281 ins_cost(100); | |
| 10282 format %{ "FABS" %} | |
| 10283 opcode(0xE1, 0xD9); | |
| 10284 ins_encode( OpcS, OpcP ); | |
| 10285 ins_pipe( fpu_reg_reg ); | |
| 10286 %} | |
| 10287 | |
|
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10288 instruct negFPR_reg(regFPR1 dst, regFPR1 src) %{ |
| 0 | 10289 predicate(UseSSE==0); |
| 10290 match(Set dst (NegF src)); | |
| 10291 ins_cost(100); | |
| 10292 format %{ "FCHS" %} | |
| 10293 opcode(0xE0, 0xD9); | |
| 10294 ins_encode( OpcS, OpcP ); | |
| 10295 ins_pipe( fpu_reg_reg ); | |
| 10296 %} | |
| 10297 | |
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10298 // Cisc-alternate to addFPR_reg |
| 0 | 10299 // Spill to obtain 24-bit precision |
|
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10300 instruct addFPR24_reg_mem(stackSlotF dst, regFPR src1, memory src2) %{ |
| 0 | 10301 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10302 match(Set dst (AddF src1 (LoadF src2))); | |
| 10303 | |
| 10304 format %{ "FLD $src2\n\t" | |
| 10305 "FADD ST,$src1\n\t" | |
| 10306 "FSTP_S $dst" %} | |
| 10307 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */ | |
| 10308 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), | |
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10309 OpcReg_FPR(src1), |
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10310 Pop_Mem_FPR(dst) ); |
| 0 | 10311 ins_pipe( fpu_mem_reg_mem ); |
| 10312 %} | |
| 10313 // | |
|
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10314 // Cisc-alternate to addFPR_reg |
| 0 | 10315 // This instruction does not round to 24-bits |
|
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10316 instruct addFPR_reg_mem(regFPR dst, memory src) %{ |
| 0 | 10317 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10318 match(Set dst (AddF dst (LoadF src))); | |
| 10319 | |
| 10320 format %{ "FADD $dst,$src" %} | |
| 10321 opcode(0xDE, 0x0, 0xD9); /* DE C0+i or DE /0*/ /* LoadF D9 /0 */ | |
| 10322 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src), | |
| 10323 OpcP, RegOpc(dst) ); | |
| 10324 ins_pipe( fpu_reg_mem ); | |
| 10325 %} | |
| 10326 | |
| 10327 // // Following two instructions for _222_mpegaudio | |
| 10328 // Spill to obtain 24-bit precision | |
|
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10329 instruct addFPR24_mem_reg(stackSlotF dst, regFPR src2, memory src1 ) %{ |
| 0 | 10330 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10331 match(Set dst (AddF src1 src2)); | |
| 10332 | |
| 10333 format %{ "FADD $dst,$src1,$src2" %} | |
| 10334 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */ | |
| 10335 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src1), | |
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10336 OpcReg_FPR(src2), |
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10337 Pop_Mem_FPR(dst) ); |
| 0 | 10338 ins_pipe( fpu_mem_reg_mem ); |
| 10339 %} | |
| 10340 | |
| 10341 // Cisc-spill variant | |
| 10342 // Spill to obtain 24-bit precision | |
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10343 instruct addFPR24_mem_cisc(stackSlotF dst, memory src1, memory src2) %{ |
| 0 | 10344 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10345 match(Set dst (AddF src1 (LoadF src2))); | |
| 10346 | |
| 10347 format %{ "FADD $dst,$src1,$src2 cisc" %} | |
| 10348 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */ | |
| 10349 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), | |
| 10350 set_instruction_start, | |
| 10351 OpcP, RMopc_Mem(secondary,src1), | |
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10352 Pop_Mem_FPR(dst) ); |
| 0 | 10353 ins_pipe( fpu_mem_mem_mem ); |
| 10354 %} | |
| 10355 | |
| 10356 // Spill to obtain 24-bit precision | |
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10357 instruct addFPR24_mem_mem(stackSlotF dst, memory src1, memory src2) %{ |
| 0 | 10358 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10359 match(Set dst (AddF src1 src2)); | |
| 10360 | |
| 10361 format %{ "FADD $dst,$src1,$src2" %} | |
| 10362 opcode(0xD8, 0x0, 0xD9); /* D8 /0 */ /* LoadF D9 /0 */ | |
| 10363 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), | |
| 10364 set_instruction_start, | |
| 10365 OpcP, RMopc_Mem(secondary,src1), | |
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10366 Pop_Mem_FPR(dst) ); |
| 0 | 10367 ins_pipe( fpu_mem_mem_mem ); |
| 10368 %} | |
| 10369 | |
| 10370 | |
| 10371 // Spill to obtain 24-bit precision | |
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10372 instruct addFPR24_reg_imm(stackSlotF dst, regFPR src, immFPR con) %{ |
| 0 | 10373 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 2008 | 10374 match(Set dst (AddF src con)); |
| 10375 format %{ "FLD $src\n\t" | |
| 10376 "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t" | |
| 0 | 10377 "FSTP_S $dst" %} |
| 2008 | 10378 ins_encode %{ |
| 10379 __ fld_s($src$$reg - 1); // FLD ST(i-1) | |
| 10380 __ fadd_s($constantaddress($con)); | |
| 10381 __ fstp_s(Address(rsp, $dst$$disp)); | |
| 10382 %} | |
| 10383 ins_pipe(fpu_mem_reg_con); | |
| 0 | 10384 %} |
| 10385 // | |
| 10386 // This instruction does not round to 24-bits | |
|
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10387 instruct addFPR_reg_imm(regFPR dst, regFPR src, immFPR con) %{ |
| 0 | 10388 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 2008 | 10389 match(Set dst (AddF src con)); |
| 10390 format %{ "FLD $src\n\t" | |
| 10391 "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t" | |
| 10392 "FSTP $dst" %} | |
| 10393 ins_encode %{ | |
| 10394 __ fld_s($src$$reg - 1); // FLD ST(i-1) | |
| 10395 __ fadd_s($constantaddress($con)); | |
| 10396 __ fstp_d($dst$$reg); | |
| 10397 %} | |
| 10398 ins_pipe(fpu_reg_reg_con); | |
| 0 | 10399 %} |
| 10400 | |
| 10401 // Spill to obtain 24-bit precision | |
|
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10402 instruct mulFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{ |
| 0 | 10403 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10404 match(Set dst (MulF src1 src2)); | |
| 10405 | |
| 10406 format %{ "FLD $src1\n\t" | |
| 10407 "FMUL $src2\n\t" | |
| 10408 "FSTP_S $dst" %} | |
| 10409 opcode(0xD8, 0x1); /* D8 C8+i or D8 /1 ;; result in TOS */ | |
|
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10410 ins_encode( Push_Reg_FPR(src1), |
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10411 OpcReg_FPR(src2), |
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10412 Pop_Mem_FPR(dst) ); |
| 0 | 10413 ins_pipe( fpu_mem_reg_reg ); |
| 10414 %} | |
| 10415 // | |
| 10416 // This instruction does not round to 24-bits | |
|
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10417 instruct mulFPR_reg(regFPR dst, regFPR src1, regFPR src2) %{ |
| 0 | 10418 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10419 match(Set dst (MulF src1 src2)); | |
| 10420 | |
| 10421 format %{ "FLD $src1\n\t" | |
| 10422 "FMUL $src2\n\t" | |
| 10423 "FSTP_S $dst" %} | |
| 10424 opcode(0xD8, 0x1); /* D8 C8+i */ | |
|
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10425 ins_encode( Push_Reg_FPR(src2), |
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10426 OpcReg_FPR(src1), |
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10427 Pop_Reg_FPR(dst) ); |
| 0 | 10428 ins_pipe( fpu_reg_reg_reg ); |
| 10429 %} | |
| 10430 | |
| 10431 | |
| 10432 // Spill to obtain 24-bit precision | |
| 10433 // Cisc-alternate to reg-reg multiply | |
|
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10434 instruct mulFPR24_reg_mem(stackSlotF dst, regFPR src1, memory src2) %{ |
| 0 | 10435 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10436 match(Set dst (MulF src1 (LoadF src2))); | |
| 10437 | |
| 10438 format %{ "FLD_S $src2\n\t" | |
| 10439 "FMUL $src1\n\t" | |
| 10440 "FSTP_S $dst" %} | |
| 10441 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or DE /1*/ /* LoadF D9 /0 */ | |
| 10442 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), | |
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10443 OpcReg_FPR(src1), |
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10444 Pop_Mem_FPR(dst) ); |
| 0 | 10445 ins_pipe( fpu_mem_reg_mem ); |
| 10446 %} | |
| 10447 // | |
| 10448 // This instruction does not round to 24-bits | |
| 10449 // Cisc-alternate to reg-reg multiply | |
|
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10450 instruct mulFPR_reg_mem(regFPR dst, regFPR src1, memory src2) %{ |
| 0 | 10451 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10452 match(Set dst (MulF src1 (LoadF src2))); | |
| 10453 | |
| 10454 format %{ "FMUL $dst,$src1,$src2" %} | |
| 10455 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadF D9 /0 */ | |
| 10456 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), | |
|
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10457 OpcReg_FPR(src1), |
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10458 Pop_Reg_FPR(dst) ); |
| 0 | 10459 ins_pipe( fpu_reg_reg_mem ); |
| 10460 %} | |
| 10461 | |
| 10462 // Spill to obtain 24-bit precision | |
|
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10463 instruct mulFPR24_mem_mem(stackSlotF dst, memory src1, memory src2) %{ |
| 0 | 10464 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10465 match(Set dst (MulF src1 src2)); | |
| 10466 | |
| 10467 format %{ "FMUL $dst,$src1,$src2" %} | |
| 10468 opcode(0xD8, 0x1, 0xD9); /* D8 /1 */ /* LoadF D9 /0 */ | |
| 10469 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), | |
| 10470 set_instruction_start, | |
| 10471 OpcP, RMopc_Mem(secondary,src1), | |
|
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10472 Pop_Mem_FPR(dst) ); |
| 0 | 10473 ins_pipe( fpu_mem_mem_mem ); |
| 10474 %} | |
| 10475 | |
| 10476 // Spill to obtain 24-bit precision | |
|
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10477 instruct mulFPR24_reg_imm(stackSlotF dst, regFPR src, immFPR con) %{ |
| 0 | 10478 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 2008 | 10479 match(Set dst (MulF src con)); |
| 10480 | |
| 10481 format %{ "FLD $src\n\t" | |
| 10482 "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t" | |
| 10483 "FSTP_S $dst" %} | |
| 10484 ins_encode %{ | |
| 10485 __ fld_s($src$$reg - 1); // FLD ST(i-1) | |
| 10486 __ fmul_s($constantaddress($con)); | |
| 10487 __ fstp_s(Address(rsp, $dst$$disp)); | |
| 10488 %} | |
| 10489 ins_pipe(fpu_mem_reg_con); | |
| 0 | 10490 %} |
| 10491 // | |
| 10492 // This instruction does not round to 24-bits | |
|
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10493 instruct mulFPR_reg_imm(regFPR dst, regFPR src, immFPR con) %{ |
| 0 | 10494 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 2008 | 10495 match(Set dst (MulF src con)); |
| 10496 | |
| 10497 format %{ "FLD $src\n\t" | |
| 10498 "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t" | |
| 10499 "FSTP $dst" %} | |
| 10500 ins_encode %{ | |
| 10501 __ fld_s($src$$reg - 1); // FLD ST(i-1) | |
| 10502 __ fmul_s($constantaddress($con)); | |
| 10503 __ fstp_d($dst$$reg); | |
| 10504 %} | |
| 10505 ins_pipe(fpu_reg_reg_con); | |
| 0 | 10506 %} |
| 10507 | |
| 10508 | |
| 10509 // | |
|
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10510 // MACRO1 -- subsume unshared load into mulFPR |
| 0 | 10511 // This instruction does not round to 24-bits |
|
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10512 instruct mulFPR_reg_load1(regFPR dst, regFPR src, memory mem1 ) %{ |
| 0 | 10513 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10514 match(Set dst (MulF (LoadF mem1) src)); | |
| 10515 | |
| 10516 format %{ "FLD $mem1 ===MACRO1===\n\t" | |
| 10517 "FMUL ST,$src\n\t" | |
| 10518 "FSTP $dst" %} | |
| 10519 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or D8 /1 */ /* LoadF D9 /0 */ | |
| 10520 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem1), | |
|
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10521 OpcReg_FPR(src), |
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10522 Pop_Reg_FPR(dst) ); |
| 0 | 10523 ins_pipe( fpu_reg_reg_mem ); |
| 10524 %} | |
| 10525 // | |
|
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10526 // MACRO2 -- addFPR a mulFPR which subsumed an unshared load |
| 0 | 10527 // This instruction does not round to 24-bits |
|
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10528 instruct addFPR_mulFPR_reg_load1(regFPR dst, memory mem1, regFPR src1, regFPR src2) %{ |
| 0 | 10529 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10530 match(Set dst (AddF (MulF (LoadF mem1) src1) src2)); | |
| 10531 ins_cost(95); | |
| 10532 | |
| 10533 format %{ "FLD $mem1 ===MACRO2===\n\t" | |
|
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10534 "FMUL ST,$src1 subsume mulFPR left load\n\t" |
| 0 | 10535 "FADD ST,$src2\n\t" |
| 10536 "FSTP $dst" %} | |
| 10537 opcode(0xD9); /* LoadF D9 /0 */ | |
| 10538 ins_encode( OpcP, RMopc_Mem(0x00,mem1), | |
| 10539 FMul_ST_reg(src1), | |
| 10540 FAdd_ST_reg(src2), | |
|
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10541 Pop_Reg_FPR(dst) ); |
| 0 | 10542 ins_pipe( fpu_reg_mem_reg_reg ); |
| 10543 %} | |
| 10544 | |
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10545 // MACRO3 -- addFPR a mulFPR |
| 0 | 10546 // This instruction does not round to 24-bits. It is a '2-address' |
| 10547 // instruction in that the result goes back to src2. This eliminates | |
| 10548 // a move from the macro; possibly the register allocator will have | |
| 10549 // to add it back (and maybe not). | |
|
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10550 instruct addFPR_mulFPR_reg(regFPR src2, regFPR src1, regFPR src0) %{ |
| 0 | 10551 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10552 match(Set src2 (AddF (MulF src0 src1) src2)); | |
| 10553 | |
| 10554 format %{ "FLD $src0 ===MACRO3===\n\t" | |
| 10555 "FMUL ST,$src1\n\t" | |
| 10556 "FADDP $src2,ST" %} | |
| 10557 opcode(0xD9); /* LoadF D9 /0 */ | |
|
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10558 ins_encode( Push_Reg_FPR(src0), |
| 0 | 10559 FMul_ST_reg(src1), |
| 10560 FAddP_reg_ST(src2) ); | |
| 10561 ins_pipe( fpu_reg_reg_reg ); | |
| 10562 %} | |
| 10563 | |
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10564 // MACRO4 -- divFPR subFPR |
| 0 | 10565 // This instruction does not round to 24-bits |
|
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10566 instruct subFPR_divFPR_reg(regFPR dst, regFPR src1, regFPR src2, regFPR src3) %{ |
| 0 | 10567 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10568 match(Set dst (DivF (SubF src2 src1) src3)); | |
| 10569 | |
| 10570 format %{ "FLD $src2 ===MACRO4===\n\t" | |
| 10571 "FSUB ST,$src1\n\t" | |
| 10572 "FDIV ST,$src3\n\t" | |
| 10573 "FSTP $dst" %} | |
| 10574 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/ | |
|
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10575 ins_encode( Push_Reg_FPR(src2), |
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10576 subFPR_divFPR_encode(src1,src3), |
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10577 Pop_Reg_FPR(dst) ); |
| 0 | 10578 ins_pipe( fpu_reg_reg_reg_reg ); |
| 10579 %} | |
| 10580 | |
| 10581 // Spill to obtain 24-bit precision | |
|
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10582 instruct divFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{ |
| 0 | 10583 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10584 match(Set dst (DivF src1 src2)); | |
| 10585 | |
| 10586 format %{ "FDIV $dst,$src1,$src2" %} | |
| 10587 opcode(0xD8, 0x6); /* D8 F0+i or DE /6*/ | |
|
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10588 ins_encode( Push_Reg_FPR(src1), |
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10589 OpcReg_FPR(src2), |
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10590 Pop_Mem_FPR(dst) ); |
| 0 | 10591 ins_pipe( fpu_mem_reg_reg ); |
| 10592 %} | |
| 10593 // | |
| 10594 // This instruction does not round to 24-bits | |
|
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10595 instruct divFPR_reg(regFPR dst, regFPR src) %{ |
| 0 | 10596 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10597 match(Set dst (DivF dst src)); | |
| 10598 | |
| 10599 format %{ "FDIV $dst,$src" %} | |
| 10600 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/ | |
|
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10601 ins_encode( Push_Reg_FPR(src), |
| 0 | 10602 OpcP, RegOpc(dst) ); |
| 10603 ins_pipe( fpu_reg_reg ); | |
| 10604 %} | |
| 10605 | |
| 10606 | |
| 10607 // Spill to obtain 24-bit precision | |
|
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10608 instruct modFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{ |
| 0 | 10609 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10610 match(Set dst (ModF src1 src2)); | |
|
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10611 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS |
| 0 | 10612 |
| 10613 format %{ "FMOD $dst,$src1,$src2" %} | |
|
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10614 ins_encode( Push_Reg_Mod_DPR(src1, src2), |
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10615 emitModDPR(), |
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10616 Push_Result_Mod_DPR(src2), |
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10617 Pop_Mem_FPR(dst)); |
| 0 | 10618 ins_pipe( pipe_slow ); |
| 10619 %} | |
| 10620 // | |
| 10621 // This instruction does not round to 24-bits | |
|
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10622 instruct modFPR_reg(regFPR dst, regFPR src, eAXRegI rax, eFlagsReg cr) %{ |
| 0 | 10623 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10624 match(Set dst (ModF dst src)); | |
|
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10625 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS |
| 0 | 10626 |
| 10627 format %{ "FMOD $dst,$src" %} | |
|
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10628 ins_encode(Push_Reg_Mod_DPR(dst, src), |
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10629 emitModDPR(), |
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10630 Push_Result_Mod_DPR(src), |
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10631 Pop_Reg_FPR(dst)); |
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10632 ins_pipe( pipe_slow ); |
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10633 %} |
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10634 |
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10635 instruct modF_reg(regF dst, regF src0, regF src1, eAXRegI rax, eFlagsReg cr) %{ |
| 0 | 10636 predicate(UseSSE>=1); |
| 10637 match(Set dst (ModF src0 src1)); | |
| 10638 effect(KILL rax, KILL cr); | |
| 10639 format %{ "SUB ESP,4\t # FMOD\n" | |
| 10640 "\tMOVSS [ESP+0],$src1\n" | |
| 10641 "\tFLD_S [ESP+0]\n" | |
| 10642 "\tMOVSS [ESP+0],$src0\n" | |
| 10643 "\tFLD_S [ESP+0]\n" | |
| 10644 "loop:\tFPREM\n" | |
| 10645 "\tFWAIT\n" | |
| 10646 "\tFNSTSW AX\n" | |
| 10647 "\tSAHF\n" | |
| 10648 "\tJP loop\n" | |
| 10649 "\tFSTP_S [ESP+0]\n" | |
| 10650 "\tMOVSS $dst,[ESP+0]\n" | |
| 10651 "\tADD ESP,4\n" | |
| 10652 "\tFSTP ST0\t # Restore FPU Stack" | |
| 10653 %} | |
| 10654 ins_cost(250); | |
|
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10655 ins_encode( Push_ModF_encoding(src0, src1), emitModDPR(), Push_ResultF(dst,0x4), PopFPU); |
| 0 | 10656 ins_pipe( pipe_slow ); |
| 10657 %} | |
| 10658 | |
| 10659 | |
| 10660 //----------Arithmetic Conversion Instructions--------------------------------- | |
| 10661 // The conversions operations are all Alpha sorted. Please keep it that way! | |
| 10662 | |
|
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10663 instruct roundFloat_mem_reg(stackSlotF dst, regFPR src) %{ |
| 0 | 10664 predicate(UseSSE==0); |
| 10665 match(Set dst (RoundFloat src)); | |
| 10666 ins_cost(125); | |
| 10667 format %{ "FST_S $dst,$src\t# F-round" %} | |
|
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10668 ins_encode( Pop_Mem_Reg_FPR(dst, src) ); |
| 0 | 10669 ins_pipe( fpu_mem_reg ); |
| 10670 %} | |
| 10671 | |
|
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10672 instruct roundDouble_mem_reg(stackSlotD dst, regDPR src) %{ |
| 0 | 10673 predicate(UseSSE<=1); |
| 10674 match(Set dst (RoundDouble src)); | |
| 10675 ins_cost(125); | |
| 10676 format %{ "FST_D $dst,$src\t# D-round" %} | |
|
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10677 ins_encode( Pop_Mem_Reg_DPR(dst, src) ); |
| 0 | 10678 ins_pipe( fpu_mem_reg ); |
| 10679 %} | |
| 10680 | |
| 10681 // Force rounding to 24-bit precision and 6-bit exponent | |
|
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10682 instruct convDPR2FPR_reg(stackSlotF dst, regDPR src) %{ |
| 0 | 10683 predicate(UseSSE==0); |
| 10684 match(Set dst (ConvD2F src)); | |
| 10685 format %{ "FST_S $dst,$src\t# F-round" %} | |
| 10686 expand %{ | |
| 10687 roundFloat_mem_reg(dst,src); | |
| 10688 %} | |
| 10689 %} | |
| 10690 | |
| 10691 // Force rounding to 24-bit precision and 6-bit exponent | |
|
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10692 instruct convDPR2F_reg(regF dst, regDPR src, eFlagsReg cr) %{ |
| 0 | 10693 predicate(UseSSE==1); |
| 10694 match(Set dst (ConvD2F src)); | |
| 10695 effect( KILL cr ); | |
| 10696 format %{ "SUB ESP,4\n\t" | |
| 10697 "FST_S [ESP],$src\t# F-round\n\t" | |
| 10698 "MOVSS $dst,[ESP]\n\t" | |
| 10699 "ADD ESP,4" %} | |
| 4759 | 10700 ins_encode %{ |
| 10701 __ subptr(rsp, 4); | |
| 10702 if ($src$$reg != FPR1L_enc) { | |
| 10703 __ fld_s($src$$reg-1); | |
| 10704 __ fstp_s(Address(rsp, 0)); | |
| 10705 } else { | |
| 10706 __ fst_s(Address(rsp, 0)); | |
| 10707 } | |
| 10708 __ movflt($dst$$XMMRegister, Address(rsp, 0)); | |
| 10709 __ addptr(rsp, 4); | |
| 10710 %} | |
| 0 | 10711 ins_pipe( pipe_slow ); |
| 10712 %} | |
| 10713 | |
| 10714 // Force rounding double precision to single precision | |
|
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10715 instruct convD2F_reg(regF dst, regD src) %{ |
| 0 | 10716 predicate(UseSSE>=2); |
| 10717 match(Set dst (ConvD2F src)); | |
| 10718 format %{ "CVTSD2SS $dst,$src\t# F-round" %} | |
| 4759 | 10719 ins_encode %{ |
| 10720 __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister); | |
| 10721 %} | |
| 0 | 10722 ins_pipe( pipe_slow ); |
| 10723 %} | |
| 10724 | |
|
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10725 instruct convFPR2DPR_reg_reg(regDPR dst, regFPR src) %{ |
| 0 | 10726 predicate(UseSSE==0); |
| 10727 match(Set dst (ConvF2D src)); | |
| 10728 format %{ "FST_S $dst,$src\t# D-round" %} | |
|
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10729 ins_encode( Pop_Reg_Reg_DPR(dst, src)); |
| 0 | 10730 ins_pipe( fpu_reg_reg ); |
| 10731 %} | |
| 10732 | |
|
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10733 instruct convFPR2D_reg(stackSlotD dst, regFPR src) %{ |
| 0 | 10734 predicate(UseSSE==1); |
| 10735 match(Set dst (ConvF2D src)); | |
| 10736 format %{ "FST_D $dst,$src\t# D-round" %} | |
| 10737 expand %{ | |
| 10738 roundDouble_mem_reg(dst,src); | |
| 10739 %} | |
| 10740 %} | |
| 10741 | |
|
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10742 instruct convF2DPR_reg(regDPR dst, regF src, eFlagsReg cr) %{ |
| 0 | 10743 predicate(UseSSE==1); |
| 10744 match(Set dst (ConvF2D src)); | |
| 10745 effect( KILL cr ); | |
| 10746 format %{ "SUB ESP,4\n\t" | |
| 10747 "MOVSS [ESP] $src\n\t" | |
| 10748 "FLD_S [ESP]\n\t" | |
| 10749 "ADD ESP,4\n\t" | |
| 10750 "FSTP $dst\t# D-round" %} | |
| 4759 | 10751 ins_encode %{ |
| 10752 __ subptr(rsp, 4); | |
| 10753 __ movflt(Address(rsp, 0), $src$$XMMRegister); | |
| 10754 __ fld_s(Address(rsp, 0)); | |
| 10755 __ addptr(rsp, 4); | |
| 10756 __ fstp_d($dst$$reg); | |
| 10757 %} | |
| 0 | 10758 ins_pipe( pipe_slow ); |
| 10759 %} | |
| 10760 | |
|
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10761 instruct convF2D_reg(regD dst, regF src) %{ |
| 0 | 10762 predicate(UseSSE>=2); |
| 10763 match(Set dst (ConvF2D src)); | |
| 10764 format %{ "CVTSS2SD $dst,$src\t# D-round" %} | |
| 4759 | 10765 ins_encode %{ |
| 10766 __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister); | |
| 10767 %} | |
| 0 | 10768 ins_pipe( pipe_slow ); |
| 10769 %} | |
| 10770 | |
| 10771 // Convert a double to an int. If the double is a NAN, stuff a zero in instead. | |
|
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10772 instruct convDPR2I_reg_reg( eAXRegI dst, eDXRegI tmp, regDPR src, eFlagsReg cr ) %{ |
| 0 | 10773 predicate(UseSSE<=1); |
| 10774 match(Set dst (ConvD2I src)); | |
| 10775 effect( KILL tmp, KILL cr ); | |
| 10776 format %{ "FLD $src\t# Convert double to int \n\t" | |
| 10777 "FLDCW trunc mode\n\t" | |
| 10778 "SUB ESP,4\n\t" | |
| 10779 "FISTp [ESP + #0]\n\t" | |
| 10780 "FLDCW std/24-bit mode\n\t" | |
| 10781 "POP EAX\n\t" | |
| 10782 "CMP EAX,0x80000000\n\t" | |
| 10783 "JNE,s fast\n\t" | |
| 10784 "FLD_D $src\n\t" | |
| 10785 "CALL d2i_wrapper\n" | |
| 10786 "fast:" %} | |
|
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10787 ins_encode( Push_Reg_DPR(src), DPR2I_encoding(src) ); |
| 0 | 10788 ins_pipe( pipe_slow ); |
| 10789 %} | |
| 10790 | |
| 10791 // Convert a double to an int. If the double is a NAN, stuff a zero in instead. | |
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10792 instruct convD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regD src, eFlagsReg cr ) %{ |
| 0 | 10793 predicate(UseSSE>=2); |
| 10794 match(Set dst (ConvD2I src)); | |
| 10795 effect( KILL tmp, KILL cr ); | |
| 10796 format %{ "CVTTSD2SI $dst, $src\n\t" | |
| 10797 "CMP $dst,0x80000000\n\t" | |
| 10798 "JNE,s fast\n\t" | |
| 10799 "SUB ESP, 8\n\t" | |
| 10800 "MOVSD [ESP], $src\n\t" | |
| 10801 "FLD_D [ESP]\n\t" | |
| 10802 "ADD ESP, 8\n\t" | |
| 10803 "CALL d2i_wrapper\n" | |
| 10804 "fast:" %} | |
| 4759 | 10805 ins_encode %{ |
| 10806 Label fast; | |
| 10807 __ cvttsd2sil($dst$$Register, $src$$XMMRegister); | |
| 10808 __ cmpl($dst$$Register, 0x80000000); | |
| 10809 __ jccb(Assembler::notEqual, fast); | |
| 10810 __ subptr(rsp, 8); | |
| 10811 __ movdbl(Address(rsp, 0), $src$$XMMRegister); | |
| 10812 __ fld_d(Address(rsp, 0)); | |
| 10813 __ addptr(rsp, 8); | |
| 10814 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2i_wrapper()))); | |
| 10815 __ bind(fast); | |
| 10816 %} | |
| 0 | 10817 ins_pipe( pipe_slow ); |
| 10818 %} | |
| 10819 | |
|
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10820 instruct convDPR2L_reg_reg( eADXRegL dst, regDPR src, eFlagsReg cr ) %{ |
| 0 | 10821 predicate(UseSSE<=1); |
| 10822 match(Set dst (ConvD2L src)); | |
| 10823 effect( KILL cr ); | |
| 10824 format %{ "FLD $src\t# Convert double to long\n\t" | |
| 10825 "FLDCW trunc mode\n\t" | |
| 10826 "SUB ESP,8\n\t" | |
| 10827 "FISTp [ESP + #0]\n\t" | |
| 10828 "FLDCW std/24-bit mode\n\t" | |
| 10829 "POP EAX\n\t" | |
| 10830 "POP EDX\n\t" | |
| 10831 "CMP EDX,0x80000000\n\t" | |
| 10832 "JNE,s fast\n\t" | |
| 10833 "TEST EAX,EAX\n\t" | |
| 10834 "JNE,s fast\n\t" | |
| 10835 "FLD $src\n\t" | |
| 10836 "CALL d2l_wrapper\n" | |
| 10837 "fast:" %} | |
|
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10838 ins_encode( Push_Reg_DPR(src), DPR2L_encoding(src) ); |
| 0 | 10839 ins_pipe( pipe_slow ); |
| 10840 %} | |
| 10841 | |
| 10842 // XMM lacks a float/double->long conversion, so use the old FPU stack. | |
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10843 instruct convD2L_reg_reg( eADXRegL dst, regD src, eFlagsReg cr ) %{ |
| 0 | 10844 predicate (UseSSE>=2); |
| 10845 match(Set dst (ConvD2L src)); | |
| 10846 effect( KILL cr ); | |
| 10847 format %{ "SUB ESP,8\t# Convert double to long\n\t" | |
| 10848 "MOVSD [ESP],$src\n\t" | |
| 10849 "FLD_D [ESP]\n\t" | |
| 10850 "FLDCW trunc mode\n\t" | |
| 10851 "FISTp [ESP + #0]\n\t" | |
| 10852 "FLDCW std/24-bit mode\n\t" | |
| 10853 "POP EAX\n\t" | |
| 10854 "POP EDX\n\t" | |
| 10855 "CMP EDX,0x80000000\n\t" | |
| 10856 "JNE,s fast\n\t" | |
| 10857 "TEST EAX,EAX\n\t" | |
| 10858 "JNE,s fast\n\t" | |
| 10859 "SUB ESP,8\n\t" | |
| 10860 "MOVSD [ESP],$src\n\t" | |
| 10861 "FLD_D [ESP]\n\t" | |
| 4759 | 10862 "ADD ESP,8\n\t" |
| 0 | 10863 "CALL d2l_wrapper\n" |
| 10864 "fast:" %} | |
| 4759 | 10865 ins_encode %{ |
| 10866 Label fast; | |
| 10867 __ subptr(rsp, 8); | |
| 10868 __ movdbl(Address(rsp, 0), $src$$XMMRegister); | |
| 10869 __ fld_d(Address(rsp, 0)); | |
| 10870 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc())); | |
| 10871 __ fistp_d(Address(rsp, 0)); | |
| 10872 // Restore the rounding mode, mask the exception | |
| 10873 if (Compile::current()->in_24_bit_fp_mode()) { | |
| 10874 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); | |
| 10875 } else { | |
| 10876 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); | |
| 10877 } | |
| 10878 // Load the converted long, adjust CPU stack | |
| 10879 __ pop(rax); | |
| 10880 __ pop(rdx); | |
| 10881 __ cmpl(rdx, 0x80000000); | |
| 10882 __ jccb(Assembler::notEqual, fast); | |
| 10883 __ testl(rax, rax); | |
| 10884 __ jccb(Assembler::notEqual, fast); | |
| 10885 __ subptr(rsp, 8); | |
| 10886 __ movdbl(Address(rsp, 0), $src$$XMMRegister); | |
| 10887 __ fld_d(Address(rsp, 0)); | |
| 10888 __ addptr(rsp, 8); | |
| 10889 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2l_wrapper()))); | |
| 10890 __ bind(fast); | |
| 10891 %} | |
| 0 | 10892 ins_pipe( pipe_slow ); |
| 10893 %} | |
| 10894 | |
| 10895 // Convert a double to an int. Java semantics require we do complex | |
| 10896 // manglations in the corner cases. So we set the rounding mode to | |
| 10897 // 'zero', store the darned double down as an int, and reset the | |
| 10898 // rounding mode to 'nearest'. The hardware stores a flag value down | |
| 10899 // if we would overflow or converted a NAN; we check for this and | |
| 10900 // and go the slow path if needed. | |
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10901 instruct convFPR2I_reg_reg(eAXRegI dst, eDXRegI tmp, regFPR src, eFlagsReg cr ) %{ |
| 0 | 10902 predicate(UseSSE==0); |
| 10903 match(Set dst (ConvF2I src)); | |
| 10904 effect( KILL tmp, KILL cr ); | |
| 10905 format %{ "FLD $src\t# Convert float to int \n\t" | |
| 10906 "FLDCW trunc mode\n\t" | |
| 10907 "SUB ESP,4\n\t" | |
| 10908 "FISTp [ESP + #0]\n\t" | |
| 10909 "FLDCW std/24-bit mode\n\t" | |
| 10910 "POP EAX\n\t" | |
| 10911 "CMP EAX,0x80000000\n\t" | |
| 10912 "JNE,s fast\n\t" | |
| 10913 "FLD $src\n\t" | |
| 10914 "CALL d2i_wrapper\n" | |
| 10915 "fast:" %} | |
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10916 // DPR2I_encoding works for FPR2I |
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10917 ins_encode( Push_Reg_FPR(src), DPR2I_encoding(src) ); |
| 0 | 10918 ins_pipe( pipe_slow ); |
| 10919 %} | |
| 10920 | |
| 10921 // Convert a float in xmm to an int reg. | |
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10922 instruct convF2I_reg(eAXRegI dst, eDXRegI tmp, regF src, eFlagsReg cr ) %{ |
| 0 | 10923 predicate(UseSSE>=1); |
| 10924 match(Set dst (ConvF2I src)); | |
| 10925 effect( KILL tmp, KILL cr ); | |
| 10926 format %{ "CVTTSS2SI $dst, $src\n\t" | |
| 10927 "CMP $dst,0x80000000\n\t" | |
| 10928 "JNE,s fast\n\t" | |
| 10929 "SUB ESP, 4\n\t" | |
| 10930 "MOVSS [ESP], $src\n\t" | |
| 10931 "FLD [ESP]\n\t" | |
| 10932 "ADD ESP, 4\n\t" | |
| 10933 "CALL d2i_wrapper\n" | |
| 10934 "fast:" %} | |
| 4759 | 10935 ins_encode %{ |
| 10936 Label fast; | |
| 10937 __ cvttss2sil($dst$$Register, $src$$XMMRegister); | |
| 10938 __ cmpl($dst$$Register, 0x80000000); | |
| 10939 __ jccb(Assembler::notEqual, fast); | |
| 10940 __ subptr(rsp, 4); | |
| 10941 __ movflt(Address(rsp, 0), $src$$XMMRegister); | |
| 10942 __ fld_s(Address(rsp, 0)); | |
| 10943 __ addptr(rsp, 4); | |
| 10944 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2i_wrapper()))); | |
| 10945 __ bind(fast); | |
| 10946 %} | |
| 0 | 10947 ins_pipe( pipe_slow ); |
| 10948 %} | |
| 10949 | |
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10950 instruct convFPR2L_reg_reg( eADXRegL dst, regFPR src, eFlagsReg cr ) %{ |
| 0 | 10951 predicate(UseSSE==0); |
| 10952 match(Set dst (ConvF2L src)); | |
| 10953 effect( KILL cr ); | |
| 10954 format %{ "FLD $src\t# Convert float to long\n\t" | |
| 10955 "FLDCW trunc mode\n\t" | |
| 10956 "SUB ESP,8\n\t" | |
| 10957 "FISTp [ESP + #0]\n\t" | |
| 10958 "FLDCW std/24-bit mode\n\t" | |
| 10959 "POP EAX\n\t" | |
| 10960 "POP EDX\n\t" | |
| 10961 "CMP EDX,0x80000000\n\t" | |
| 10962 "JNE,s fast\n\t" | |
| 10963 "TEST EAX,EAX\n\t" | |
| 10964 "JNE,s fast\n\t" | |
| 10965 "FLD $src\n\t" | |
| 10966 "CALL d2l_wrapper\n" | |
| 10967 "fast:" %} | |
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10968 // DPR2L_encoding works for FPR2L |
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10969 ins_encode( Push_Reg_FPR(src), DPR2L_encoding(src) ); |
| 0 | 10970 ins_pipe( pipe_slow ); |
| 10971 %} | |
| 10972 | |
| 10973 // XMM lacks a float/double->long conversion, so use the old FPU stack. | |
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10974 instruct convF2L_reg_reg( eADXRegL dst, regF src, eFlagsReg cr ) %{ |
| 0 | 10975 predicate (UseSSE>=1); |
| 10976 match(Set dst (ConvF2L src)); | |
| 10977 effect( KILL cr ); | |
| 10978 format %{ "SUB ESP,8\t# Convert float to long\n\t" | |
| 10979 "MOVSS [ESP],$src\n\t" | |
| 10980 "FLD_S [ESP]\n\t" | |
| 10981 "FLDCW trunc mode\n\t" | |
| 10982 "FISTp [ESP + #0]\n\t" | |
| 10983 "FLDCW std/24-bit mode\n\t" | |
| 10984 "POP EAX\n\t" | |
| 10985 "POP EDX\n\t" | |
| 10986 "CMP EDX,0x80000000\n\t" | |
| 10987 "JNE,s fast\n\t" | |
| 10988 "TEST EAX,EAX\n\t" | |
| 10989 "JNE,s fast\n\t" | |
| 10990 "SUB ESP,4\t# Convert float to long\n\t" | |
| 10991 "MOVSS [ESP],$src\n\t" | |
| 10992 "FLD_S [ESP]\n\t" | |
| 10993 "ADD ESP,4\n\t" | |
| 10994 "CALL d2l_wrapper\n" | |
| 10995 "fast:" %} | |
| 4759 | 10996 ins_encode %{ |
| 10997 Label fast; | |
| 10998 __ subptr(rsp, 8); | |
| 10999 __ movflt(Address(rsp, 0), $src$$XMMRegister); | |
| 11000 __ fld_s(Address(rsp, 0)); | |
| 11001 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc())); | |
| 11002 __ fistp_d(Address(rsp, 0)); | |
| 11003 // Restore the rounding mode, mask the exception | |
| 11004 if (Compile::current()->in_24_bit_fp_mode()) { | |
| 11005 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); | |
| 11006 } else { | |
| 11007 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); | |
| 11008 } | |
| 11009 // Load the converted long, adjust CPU stack | |
| 11010 __ pop(rax); | |
| 11011 __ pop(rdx); | |
| 11012 __ cmpl(rdx, 0x80000000); | |
| 11013 __ jccb(Assembler::notEqual, fast); | |
| 11014 __ testl(rax, rax); | |
| 11015 __ jccb(Assembler::notEqual, fast); | |
| 11016 __ subptr(rsp, 4); | |
| 11017 __ movflt(Address(rsp, 0), $src$$XMMRegister); | |
| 11018 __ fld_s(Address(rsp, 0)); | |
| 11019 __ addptr(rsp, 4); | |
| 11020 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2l_wrapper()))); | |
| 11021 __ bind(fast); | |
| 11022 %} | |
| 0 | 11023 ins_pipe( pipe_slow ); |
| 11024 %} | |
| 11025 | |
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11026 instruct convI2DPR_reg(regDPR dst, stackSlotI src) %{ |
| 0 | 11027 predicate( UseSSE<=1 ); |
| 11028 match(Set dst (ConvI2D src)); | |
| 11029 format %{ "FILD $src\n\t" | |
| 11030 "FSTP $dst" %} | |
| 11031 opcode(0xDB, 0x0); /* DB /0 */ | |
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11032 ins_encode(Push_Mem_I(src), Pop_Reg_DPR(dst)); |
| 0 | 11033 ins_pipe( fpu_reg_mem ); |
| 11034 %} | |
| 11035 | |
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11036 instruct convI2D_reg(regD dst, rRegI src) %{ |
| 71 | 11037 predicate( UseSSE>=2 && !UseXmmI2D ); |
| 0 | 11038 match(Set dst (ConvI2D src)); |
| 11039 format %{ "CVTSI2SD $dst,$src" %} | |
| 4759 | 11040 ins_encode %{ |
| 11041 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register); | |
| 11042 %} | |
| 0 | 11043 ins_pipe( pipe_slow ); |
| 11044 %} | |
| 11045 | |
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11046 instruct convI2D_mem(regD dst, memory mem) %{ |
| 0 | 11047 predicate( UseSSE>=2 ); |
| 11048 match(Set dst (ConvI2D (LoadI mem))); | |
| 11049 format %{ "CVTSI2SD $dst,$mem" %} | |
| 4759 | 11050 ins_encode %{ |
| 11051 __ cvtsi2sdl ($dst$$XMMRegister, $mem$$Address); | |
| 11052 %} | |
| 0 | 11053 ins_pipe( pipe_slow ); |
| 11054 %} | |
| 11055 | |
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11056 instruct convXI2D_reg(regD dst, rRegI src) |
| 71 | 11057 %{ |
| 11058 predicate( UseSSE>=2 && UseXmmI2D ); | |
| 11059 match(Set dst (ConvI2D src)); | |
| 11060 | |
| 11061 format %{ "MOVD $dst,$src\n\t" | |
| 11062 "CVTDQ2PD $dst,$dst\t# i2d" %} | |
| 11063 ins_encode %{ | |
| 304 | 11064 __ movdl($dst$$XMMRegister, $src$$Register); |
| 71 | 11065 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister); |
| 11066 %} | |
| 11067 ins_pipe(pipe_slow); // XXX | |
| 11068 %} | |
| 11069 | |
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11070 instruct convI2DPR_mem(regDPR dst, memory mem) %{ |
| 0 | 11071 predicate( UseSSE<=1 && !Compile::current()->select_24_bit_instr()); |
| 11072 match(Set dst (ConvI2D (LoadI mem))); | |
| 11073 format %{ "FILD $mem\n\t" | |
| 11074 "FSTP $dst" %} | |
| 11075 opcode(0xDB); /* DB /0 */ | |
| 11076 ins_encode( OpcP, RMopc_Mem(0x00,mem), | |
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11077 Pop_Reg_DPR(dst)); |
| 0 | 11078 ins_pipe( fpu_reg_mem ); |
| 11079 %} | |
| 11080 | |
| 11081 // Convert a byte to a float; no rounding step needed. | |
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11082 instruct conv24I2FPR_reg(regFPR dst, stackSlotI src) %{ |
| 0 | 11083 predicate( UseSSE==0 && n->in(1)->Opcode() == Op_AndI && n->in(1)->in(2)->is_Con() && n->in(1)->in(2)->get_int() == 255 ); |
| 11084 match(Set dst (ConvI2F src)); | |
| 11085 format %{ "FILD $src\n\t" | |
| 11086 "FSTP $dst" %} | |
| 11087 | |
| 11088 opcode(0xDB, 0x0); /* DB /0 */ | |
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11089 ins_encode(Push_Mem_I(src), Pop_Reg_FPR(dst)); |
| 0 | 11090 ins_pipe( fpu_reg_mem ); |
| 11091 %} | |
| 11092 | |
| 11093 // In 24-bit mode, force exponent rounding by storing back out | |
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11094 instruct convI2FPR_SSF(stackSlotF dst, stackSlotI src) %{ |
| 0 | 11095 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 11096 match(Set dst (ConvI2F src)); | |
| 11097 ins_cost(200); | |
| 11098 format %{ "FILD $src\n\t" | |
| 11099 "FSTP_S $dst" %} | |
| 11100 opcode(0xDB, 0x0); /* DB /0 */ | |
| 11101 ins_encode( Push_Mem_I(src), | |
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11102 Pop_Mem_FPR(dst)); |
| 0 | 11103 ins_pipe( fpu_mem_mem ); |
| 11104 %} | |
| 11105 | |
| 11106 // In 24-bit mode, force exponent rounding by storing back out | |
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11107 instruct convI2FPR_SSF_mem(stackSlotF dst, memory mem) %{ |
| 0 | 11108 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 11109 match(Set dst (ConvI2F (LoadI mem))); | |
| 11110 ins_cost(200); | |
| 11111 format %{ "FILD $mem\n\t" | |
| 11112 "FSTP_S $dst" %} | |
| 11113 opcode(0xDB); /* DB /0 */ | |
| 11114 ins_encode( OpcP, RMopc_Mem(0x00,mem), | |
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11115 Pop_Mem_FPR(dst)); |
| 0 | 11116 ins_pipe( fpu_mem_mem ); |
| 11117 %} | |
| 11118 | |
| 11119 // This instruction does not round to 24-bits | |
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11120 instruct convI2FPR_reg(regFPR dst, stackSlotI src) %{ |
| 0 | 11121 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 11122 match(Set dst (ConvI2F src)); | |
| 11123 format %{ "FILD $src\n\t" | |
| 11124 "FSTP $dst" %} | |
| 11125 opcode(0xDB, 0x0); /* DB /0 */ | |
| 11126 ins_encode( Push_Mem_I(src), | |
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11127 Pop_Reg_FPR(dst)); |
| 0 | 11128 ins_pipe( fpu_reg_mem ); |
| 11129 %} | |
| 11130 | |
| 11131 // This instruction does not round to 24-bits | |
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11132 instruct convI2FPR_mem(regFPR dst, memory mem) %{ |
| 0 | 11133 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 11134 match(Set dst (ConvI2F (LoadI mem))); | |
| 11135 format %{ "FILD $mem\n\t" | |
| 11136 "FSTP $dst" %} | |
| 11137 opcode(0xDB); /* DB /0 */ | |
| 11138 ins_encode( OpcP, RMopc_Mem(0x00,mem), | |
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11139 Pop_Reg_FPR(dst)); |
| 0 | 11140 ins_pipe( fpu_reg_mem ); |
| 11141 %} | |
| 11142 | |
| 11143 // Convert an int to a float in xmm; no rounding step needed. | |
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11144 instruct convI2F_reg(regF dst, rRegI src) %{ |
| 71 | 11145 predicate( UseSSE==1 || UseSSE>=2 && !UseXmmI2F ); |
| 0 | 11146 match(Set dst (ConvI2F src)); |
| 11147 format %{ "CVTSI2SS $dst, $src" %} | |
| 4759 | 11148 ins_encode %{ |
| 11149 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register); | |
| 11150 %} | |
| 0 | 11151 ins_pipe( pipe_slow ); |
| 11152 %} | |
| 11153 | |
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11154 instruct convXI2F_reg(regF dst, rRegI src) |
| 71 | 11155 %{ |
| 11156 predicate( UseSSE>=2 && UseXmmI2F ); | |
| 11157 match(Set dst (ConvI2F src)); | |
| 11158 | |
| 11159 format %{ "MOVD $dst,$src\n\t" | |
| 11160 "CVTDQ2PS $dst,$dst\t# i2f" %} | |
| 11161 ins_encode %{ | |
| 304 | 11162 __ movdl($dst$$XMMRegister, $src$$Register); |
| 71 | 11163 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister); |
| 11164 %} | |
| 11165 ins_pipe(pipe_slow); // XXX | |
| 11166 %} | |
| 11167 | |
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11168 instruct convI2L_reg( eRegL dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 11169 match(Set dst (ConvI2L src)); |
| 11170 effect(KILL cr); | |
| 624 | 11171 ins_cost(375); |
| 0 | 11172 format %{ "MOV $dst.lo,$src\n\t" |
| 11173 "MOV $dst.hi,$src\n\t" | |
| 11174 "SAR $dst.hi,31" %} | |
| 11175 ins_encode(convert_int_long(dst,src)); | |
| 11176 ins_pipe( ialu_reg_reg_long ); | |
| 11177 %} | |
| 11178 | |
| 11179 // Zero-extend convert int to long | |
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11180 instruct convI2L_reg_zex(eRegL dst, rRegI src, immL_32bits mask, eFlagsReg flags ) %{ |
| 0 | 11181 match(Set dst (AndL (ConvI2L src) mask) ); |
| 11182 effect( KILL flags ); | |
| 624 | 11183 ins_cost(250); |
| 0 | 11184 format %{ "MOV $dst.lo,$src\n\t" |
| 11185 "XOR $dst.hi,$dst.hi" %} | |
| 11186 opcode(0x33); // XOR | |
| 11187 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) ); | |
| 11188 ins_pipe( ialu_reg_reg_long ); | |
| 11189 %} | |
| 11190 | |
| 11191 // Zero-extend long | |
| 11192 instruct zerox_long(eRegL dst, eRegL src, immL_32bits mask, eFlagsReg flags ) %{ | |
| 11193 match(Set dst (AndL src mask) ); | |
| 11194 effect( KILL flags ); | |
| 624 | 11195 ins_cost(250); |
| 0 | 11196 format %{ "MOV $dst.lo,$src.lo\n\t" |
| 11197 "XOR $dst.hi,$dst.hi\n\t" %} | |
| 11198 opcode(0x33); // XOR | |
| 11199 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) ); | |
| 11200 ins_pipe( ialu_reg_reg_long ); | |
| 11201 %} | |
| 11202 | |
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11203 instruct convL2DPR_reg( stackSlotD dst, eRegL src, eFlagsReg cr) %{ |
| 0 | 11204 predicate (UseSSE<=1); |
| 11205 match(Set dst (ConvL2D src)); | |
| 11206 effect( KILL cr ); | |
| 11207 format %{ "PUSH $src.hi\t# Convert long to double\n\t" | |
| 11208 "PUSH $src.lo\n\t" | |
| 11209 "FILD ST,[ESP + #0]\n\t" | |
| 11210 "ADD ESP,8\n\t" | |
| 11211 "FSTP_D $dst\t# D-round" %} | |
| 11212 opcode(0xDF, 0x5); /* DF /5 */ | |
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11213 ins_encode(convert_long_double(src), Pop_Mem_DPR(dst)); |
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11214 ins_pipe( pipe_slow ); |
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11215 %} |
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11216 |
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11217 instruct convL2D_reg( regD dst, eRegL src, eFlagsReg cr) %{ |
| 0 | 11218 predicate (UseSSE>=2); |
| 11219 match(Set dst (ConvL2D src)); | |
| 11220 effect( KILL cr ); | |
| 11221 format %{ "PUSH $src.hi\t# Convert long to double\n\t" | |
| 11222 "PUSH $src.lo\n\t" | |
| 11223 "FILD_D [ESP]\n\t" | |
| 11224 "FSTP_D [ESP]\n\t" | |
| 11225 "MOVSD $dst,[ESP]\n\t" | |
| 11226 "ADD ESP,8" %} | |
| 11227 opcode(0xDF, 0x5); /* DF /5 */ | |
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11228 ins_encode(convert_long_double2(src), Push_ResultD(dst)); |
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11229 ins_pipe( pipe_slow ); |
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11230 %} |
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11231 |
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11232 instruct convL2F_reg( regF dst, eRegL src, eFlagsReg cr) %{ |
| 0 | 11233 predicate (UseSSE>=1); |
| 11234 match(Set dst (ConvL2F src)); | |
| 11235 effect( KILL cr ); | |
| 11236 format %{ "PUSH $src.hi\t# Convert long to single float\n\t" | |
| 11237 "PUSH $src.lo\n\t" | |
| 11238 "FILD_D [ESP]\n\t" | |
| 11239 "FSTP_S [ESP]\n\t" | |
| 11240 "MOVSS $dst,[ESP]\n\t" | |
| 11241 "ADD ESP,8" %} | |
| 11242 opcode(0xDF, 0x5); /* DF /5 */ | |
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11243 ins_encode(convert_long_double2(src), Push_ResultF(dst,0x8)); |
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11244 ins_pipe( pipe_slow ); |
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11245 %} |
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11246 |
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11247 instruct convL2FPR_reg( stackSlotF dst, eRegL src, eFlagsReg cr) %{ |
| 0 | 11248 match(Set dst (ConvL2F src)); |
| 11249 effect( KILL cr ); | |
| 11250 format %{ "PUSH $src.hi\t# Convert long to single float\n\t" | |
| 11251 "PUSH $src.lo\n\t" | |
| 11252 "FILD ST,[ESP + #0]\n\t" | |
| 11253 "ADD ESP,8\n\t" | |
| 11254 "FSTP_S $dst\t# F-round" %} | |
| 11255 opcode(0xDF, 0x5); /* DF /5 */ | |
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11256 ins_encode(convert_long_double(src), Pop_Mem_FPR(dst)); |
| 0 | 11257 ins_pipe( pipe_slow ); |
| 11258 %} | |
| 11259 | |
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11260 instruct convL2I_reg( rRegI dst, eRegL src ) %{ |
| 0 | 11261 match(Set dst (ConvL2I src)); |
| 11262 effect( DEF dst, USE src ); | |
| 11263 format %{ "MOV $dst,$src.lo" %} | |
| 11264 ins_encode(enc_CopyL_Lo(dst,src)); | |
| 11265 ins_pipe( ialu_reg_reg ); | |
| 11266 %} | |
| 11267 | |
| 11268 | |
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11269 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{ |
| 0 | 11270 match(Set dst (MoveF2I src)); |
| 11271 effect( DEF dst, USE src ); | |
| 11272 ins_cost(100); | |
| 11273 format %{ "MOV $dst,$src\t# MoveF2I_stack_reg" %} | |
| 4759 | 11274 ins_encode %{ |
| 11275 __ movl($dst$$Register, Address(rsp, $src$$disp)); | |
| 11276 %} | |
| 0 | 11277 ins_pipe( ialu_reg_mem ); |
| 11278 %} | |
| 11279 | |
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11280 instruct MoveFPR2I_reg_stack(stackSlotI dst, regFPR src) %{ |
| 0 | 11281 predicate(UseSSE==0); |
| 11282 match(Set dst (MoveF2I src)); | |
| 11283 effect( DEF dst, USE src ); | |
| 11284 | |
| 11285 ins_cost(125); | |
| 11286 format %{ "FST_S $dst,$src\t# MoveF2I_reg_stack" %} | |
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11287 ins_encode( Pop_Mem_Reg_FPR(dst, src) ); |
| 0 | 11288 ins_pipe( fpu_mem_reg ); |
| 11289 %} | |
| 11290 | |
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11291 instruct MoveF2I_reg_stack_sse(stackSlotI dst, regF src) %{ |
| 0 | 11292 predicate(UseSSE>=1); |
| 11293 match(Set dst (MoveF2I src)); | |
| 11294 effect( DEF dst, USE src ); | |
| 11295 | |
| 11296 ins_cost(95); | |
| 11297 format %{ "MOVSS $dst,$src\t# MoveF2I_reg_stack_sse" %} | |
| 4759 | 11298 ins_encode %{ |
| 11299 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister); | |
| 11300 %} | |
| 0 | 11301 ins_pipe( pipe_slow ); |
| 11302 %} | |
| 11303 | |
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11304 instruct MoveF2I_reg_reg_sse(rRegI dst, regF src) %{ |
| 0 | 11305 predicate(UseSSE>=2); |
| 11306 match(Set dst (MoveF2I src)); | |
| 11307 effect( DEF dst, USE src ); | |
| 11308 ins_cost(85); | |
| 11309 format %{ "MOVD $dst,$src\t# MoveF2I_reg_reg_sse" %} | |
| 4759 | 11310 ins_encode %{ |
| 11311 __ movdl($dst$$Register, $src$$XMMRegister); | |
| 11312 %} | |
| 0 | 11313 ins_pipe( pipe_slow ); |
| 11314 %} | |
| 11315 | |
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11316 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{ |
| 0 | 11317 match(Set dst (MoveI2F src)); |
| 11318 effect( DEF dst, USE src ); | |
| 11319 | |
| 11320 ins_cost(100); | |
| 11321 format %{ "MOV $dst,$src\t# MoveI2F_reg_stack" %} | |
| 4759 | 11322 ins_encode %{ |
| 11323 __ movl(Address(rsp, $dst$$disp), $src$$Register); | |
| 11324 %} | |
| 0 | 11325 ins_pipe( ialu_mem_reg ); |
| 11326 %} | |
| 11327 | |
| 11328 | |
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11329 instruct MoveI2FPR_stack_reg(regFPR dst, stackSlotI src) %{ |
| 0 | 11330 predicate(UseSSE==0); |
| 11331 match(Set dst (MoveI2F src)); | |
| 11332 effect(DEF dst, USE src); | |
| 11333 | |
| 11334 ins_cost(125); | |
| 11335 format %{ "FLD_S $src\n\t" | |
| 11336 "FSTP $dst\t# MoveI2F_stack_reg" %} | |
| 11337 opcode(0xD9); /* D9 /0, FLD m32real */ | |
| 11338 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src), | |
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11339 Pop_Reg_FPR(dst) ); |
| 0 | 11340 ins_pipe( fpu_reg_mem ); |
| 11341 %} | |
| 11342 | |
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11343 instruct MoveI2F_stack_reg_sse(regF dst, stackSlotI src) %{ |
| 0 | 11344 predicate(UseSSE>=1); |
| 11345 match(Set dst (MoveI2F src)); | |
| 11346 effect( DEF dst, USE src ); | |
| 11347 | |
| 11348 ins_cost(95); | |
| 11349 format %{ "MOVSS $dst,$src\t# MoveI2F_stack_reg_sse" %} | |
| 4759 | 11350 ins_encode %{ |
| 11351 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp)); | |
| 11352 %} | |
| 0 | 11353 ins_pipe( pipe_slow ); |
| 11354 %} | |
| 11355 | |
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11356 instruct MoveI2F_reg_reg_sse(regF dst, rRegI src) %{ |
| 0 | 11357 predicate(UseSSE>=2); |
| 11358 match(Set dst (MoveI2F src)); | |
| 11359 effect( DEF dst, USE src ); | |
| 11360 | |
| 11361 ins_cost(85); | |
| 11362 format %{ "MOVD $dst,$src\t# MoveI2F_reg_reg_sse" %} | |
| 4759 | 11363 ins_encode %{ |
| 11364 __ movdl($dst$$XMMRegister, $src$$Register); | |
| 11365 %} | |
| 0 | 11366 ins_pipe( pipe_slow ); |
| 11367 %} | |
| 11368 | |
| 11369 instruct MoveD2L_stack_reg(eRegL dst, stackSlotD src) %{ | |
| 11370 match(Set dst (MoveD2L src)); | |
| 11371 effect(DEF dst, USE src); | |
| 11372 | |
| 11373 ins_cost(250); | |
| 11374 format %{ "MOV $dst.lo,$src\n\t" | |
| 11375 "MOV $dst.hi,$src+4\t# MoveD2L_stack_reg" %} | |
| 11376 opcode(0x8B, 0x8B); | |
| 11377 ins_encode( OpcP, RegMem(dst,src), OpcS, RegMem_Hi(dst,src)); | |
| 11378 ins_pipe( ialu_mem_long_reg ); | |
| 11379 %} | |
| 11380 | |
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11381 instruct MoveDPR2L_reg_stack(stackSlotL dst, regDPR src) %{ |
| 0 | 11382 predicate(UseSSE<=1); |
| 11383 match(Set dst (MoveD2L src)); | |
| 11384 effect(DEF dst, USE src); | |
| 11385 | |
| 11386 ins_cost(125); | |
| 11387 format %{ "FST_D $dst,$src\t# MoveD2L_reg_stack" %} | |
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11388 ins_encode( Pop_Mem_Reg_DPR(dst, src) ); |
| 0 | 11389 ins_pipe( fpu_mem_reg ); |
| 11390 %} | |
| 11391 | |
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11392 instruct MoveD2L_reg_stack_sse(stackSlotL dst, regD src) %{ |
| 0 | 11393 predicate(UseSSE>=2); |
| 11394 match(Set dst (MoveD2L src)); | |
| 11395 effect(DEF dst, USE src); | |
| 11396 ins_cost(95); | |
| 11397 format %{ "MOVSD $dst,$src\t# MoveD2L_reg_stack_sse" %} | |
| 4759 | 11398 ins_encode %{ |
| 11399 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister); | |
| 11400 %} | |
| 0 | 11401 ins_pipe( pipe_slow ); |
| 11402 %} | |
| 11403 | |
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11404 instruct MoveD2L_reg_reg_sse(eRegL dst, regD src, regD tmp) %{ |
| 0 | 11405 predicate(UseSSE>=2); |
| 11406 match(Set dst (MoveD2L src)); | |
| 11407 effect(DEF dst, USE src, TEMP tmp); | |
| 11408 ins_cost(85); | |
| 11409 format %{ "MOVD $dst.lo,$src\n\t" | |
| 11410 "PSHUFLW $tmp,$src,0x4E\n\t" | |
| 11411 "MOVD $dst.hi,$tmp\t# MoveD2L_reg_reg_sse" %} | |
| 4759 | 11412 ins_encode %{ |
| 11413 __ movdl($dst$$Register, $src$$XMMRegister); | |
| 11414 __ pshuflw($tmp$$XMMRegister, $src$$XMMRegister, 0x4e); | |
| 11415 __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister); | |
| 11416 %} | |
| 0 | 11417 ins_pipe( pipe_slow ); |
| 11418 %} | |
| 11419 | |
| 11420 instruct MoveL2D_reg_stack(stackSlotD dst, eRegL src) %{ | |
| 11421 match(Set dst (MoveL2D src)); | |
| 11422 effect(DEF dst, USE src); | |
| 11423 | |
| 11424 ins_cost(200); | |
| 11425 format %{ "MOV $dst,$src.lo\n\t" | |
| 11426 "MOV $dst+4,$src.hi\t# MoveL2D_reg_stack" %} | |
| 11427 opcode(0x89, 0x89); | |
| 11428 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) ); | |
| 11429 ins_pipe( ialu_mem_long_reg ); | |
| 11430 %} | |
| 11431 | |
| 11432 | |
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11433 instruct MoveL2DPR_stack_reg(regDPR dst, stackSlotL src) %{ |
| 0 | 11434 predicate(UseSSE<=1); |
| 11435 match(Set dst (MoveL2D src)); | |
| 11436 effect(DEF dst, USE src); | |
| 11437 ins_cost(125); | |
| 11438 | |
| 11439 format %{ "FLD_D $src\n\t" | |
| 11440 "FSTP $dst\t# MoveL2D_stack_reg" %} | |
| 11441 opcode(0xDD); /* DD /0, FLD m64real */ | |
| 11442 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src), | |
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11443 Pop_Reg_DPR(dst) ); |
| 0 | 11444 ins_pipe( fpu_reg_mem ); |
| 11445 %} | |
| 11446 | |
| 11447 | |
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11448 instruct MoveL2D_stack_reg_sse(regD dst, stackSlotL src) %{ |
| 0 | 11449 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper); |
| 11450 match(Set dst (MoveL2D src)); | |
| 11451 effect(DEF dst, USE src); | |
| 11452 | |
| 11453 ins_cost(95); | |
| 11454 format %{ "MOVSD $dst,$src\t# MoveL2D_stack_reg_sse" %} | |
| 4759 | 11455 ins_encode %{ |
| 11456 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp)); | |
| 11457 %} | |
| 0 | 11458 ins_pipe( pipe_slow ); |
| 11459 %} | |
| 11460 | |
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11461 instruct MoveL2D_stack_reg_sse_partial(regD dst, stackSlotL src) %{ |
| 0 | 11462 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper); |
| 11463 match(Set dst (MoveL2D src)); | |
| 11464 effect(DEF dst, USE src); | |
| 11465 | |
| 11466 ins_cost(95); | |
| 11467 format %{ "MOVLPD $dst,$src\t# MoveL2D_stack_reg_sse" %} | |
| 4759 | 11468 ins_encode %{ |
| 11469 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp)); | |
| 11470 %} | |
| 0 | 11471 ins_pipe( pipe_slow ); |
| 11472 %} | |
| 11473 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11474 instruct MoveL2D_reg_reg_sse(regD dst, eRegL src, regD tmp) %{ |
| 0 | 11475 predicate(UseSSE>=2); |
| 11476 match(Set dst (MoveL2D src)); | |
| 11477 effect(TEMP dst, USE src, TEMP tmp); | |
| 11478 ins_cost(85); | |
| 11479 format %{ "MOVD $dst,$src.lo\n\t" | |
| 11480 "MOVD $tmp,$src.hi\n\t" | |
| 11481 "PUNPCKLDQ $dst,$tmp\t# MoveL2D_reg_reg_sse" %} | |
| 4759 | 11482 ins_encode %{ |
| 11483 __ movdl($dst$$XMMRegister, $src$$Register); | |
| 11484 __ movdl($tmp$$XMMRegister, HIGH_FROM_LOW($src$$Register)); | |
| 11485 __ punpckldq($dst$$XMMRegister, $tmp$$XMMRegister); | |
| 11486 %} | |
| 0 | 11487 ins_pipe( pipe_slow ); |
| 11488 %} | |
| 11489 | |
| 11490 | |
| 11491 // ======================================================================= | |
| 11492 // fast clearing of an array | |
| 11493 instruct rep_stos(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{ | |
|
7474
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6853
diff
changeset
|
11494 predicate(!UseFastStosb); |
| 0 | 11495 match(Set dummy (ClearArray cnt base)); |
| 11496 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr); | |
|
7474
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6853
diff
changeset
|
11497 format %{ "XOR EAX,EAX\t# ClearArray:\n\t" |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6853
diff
changeset
|
11498 "SHL ECX,1\t# Convert doublewords to words\n\t" |
| 0 | 11499 "REP STOS\t# store EAX into [EDI++] while ECX--" %} |
|
7474
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6853
diff
changeset
|
11500 ins_encode %{ |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6853
diff
changeset
|
11501 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register); |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6853
diff
changeset
|
11502 %} |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6853
diff
changeset
|
11503 ins_pipe( pipe_slow ); |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6853
diff
changeset
|
11504 %} |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6853
diff
changeset
|
11505 |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6853
diff
changeset
|
11506 instruct rep_fast_stosb(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{ |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6853
diff
changeset
|
11507 predicate(UseFastStosb); |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6853
diff
changeset
|
11508 match(Set dummy (ClearArray cnt base)); |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6853
diff
changeset
|
11509 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr); |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6853
diff
changeset
|
11510 format %{ "XOR EAX,EAX\t# ClearArray:\n\t" |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6853
diff
changeset
|
11511 "SHL ECX,3\t# Convert doublewords to bytes\n\t" |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6853
diff
changeset
|
11512 "REP STOSB\t# store EAX into [EDI++] while ECX--" %} |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6853
diff
changeset
|
11513 ins_encode %{ |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6853
diff
changeset
|
11514 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register); |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6853
diff
changeset
|
11515 %} |
| 0 | 11516 ins_pipe( pipe_slow ); |
| 11517 %} | |
| 11518 | |
| 2262 | 11519 instruct string_compare(eDIRegP str1, eCXRegI cnt1, eSIRegP str2, eDXRegI cnt2, |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11520 eAXRegI result, regD tmp1, eFlagsReg cr) %{ |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11521 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); |
| 2262 | 11522 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr); |
| 11523 | |
| 11524 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %} | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11525 ins_encode %{ |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11526 __ string_compare($str1$$Register, $str2$$Register, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11527 $cnt1$$Register, $cnt2$$Register, $result$$Register, |
| 2262 | 11528 $tmp1$$XMMRegister); |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11529 %} |
| 681 | 11530 ins_pipe( pipe_slow ); |
| 11531 %} | |
| 11532 | |
| 11533 // fast string equals | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11534 instruct string_equals(eDIRegP str1, eSIRegP str2, eCXRegI cnt, eAXRegI result, |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11535 regD tmp1, regD tmp2, eBXRegI tmp3, eFlagsReg cr) %{ |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11536 match(Set result (StrEquals (Binary str1 str2) cnt)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11537 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11538 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11539 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %} |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11540 ins_encode %{ |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11541 __ char_arrays_equals(false, $str1$$Register, $str2$$Register, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11542 $cnt$$Register, $result$$Register, $tmp3$$Register, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11543 $tmp1$$XMMRegister, $tmp2$$XMMRegister); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11544 %} |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11545 ins_pipe( pipe_slow ); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11546 %} |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11547 |
|
2320
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11548 // fast search of substring with known size. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11549 instruct string_indexof_con(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, immI int_cnt2, |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11550 eBXRegI result, regD vec, eAXRegI cnt2, eCXRegI tmp, eFlagsReg cr) %{ |
|
2320
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11551 predicate(UseSSE42Intrinsics); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11552 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2))); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11553 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11554 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11555 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %} |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11556 ins_encode %{ |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11557 int icnt2 = (int)$int_cnt2$$constant; |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11558 if (icnt2 >= 8) { |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11559 // IndexOf for constant substrings with size >= 8 elements |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11560 // which don't need to be loaded through stack. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11561 __ string_indexofC8($str1$$Register, $str2$$Register, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11562 $cnt1$$Register, $cnt2$$Register, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11563 icnt2, $result$$Register, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11564 $vec$$XMMRegister, $tmp$$Register); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11565 } else { |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11566 // Small strings are loaded through stack if they cross page boundary. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11567 __ string_indexof($str1$$Register, $str2$$Register, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11568 $cnt1$$Register, $cnt2$$Register, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11569 icnt2, $result$$Register, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11570 $vec$$XMMRegister, $tmp$$Register); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11571 } |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11572 %} |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11573 ins_pipe( pipe_slow ); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11574 %} |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11575 |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11576 instruct string_indexof(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, eAXRegI cnt2, |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11577 eBXRegI result, regD vec, eCXRegI tmp, eFlagsReg cr) %{ |
| 681 | 11578 predicate(UseSSE42Intrinsics); |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11579 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2))); |
|
2320
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11580 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11581 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11582 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %} |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11583 ins_encode %{ |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11584 __ string_indexof($str1$$Register, $str2$$Register, |
|
2320
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11585 $cnt1$$Register, $cnt2$$Register, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11586 (-1), $result$$Register, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11587 $vec$$XMMRegister, $tmp$$Register); |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11588 %} |
| 0 | 11589 ins_pipe( pipe_slow ); |
| 11590 %} | |
| 11591 | |
|
169
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
11592 // fast array equals |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11593 instruct array_equals(eDIRegP ary1, eSIRegP ary2, eAXRegI result, |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11594 regD tmp1, regD tmp2, eCXRegI tmp3, eBXRegI tmp4, eFlagsReg cr) |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11595 %{ |
|
169
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
11596 match(Set result (AryEq ary1 ary2)); |
| 681 | 11597 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr); |
|
169
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
11598 //ins_cost(300); |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
11599 |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11600 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %} |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11601 ins_encode %{ |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11602 __ char_arrays_equals(true, $ary1$$Register, $ary2$$Register, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11603 $tmp3$$Register, $result$$Register, $tmp4$$Register, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11604 $tmp1$$XMMRegister, $tmp2$$XMMRegister); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11605 %} |
|
169
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
11606 ins_pipe( pipe_slow ); |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
11607 %} |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
11608 |
|
7637
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
11609 // encode char[] to byte[] in ISO_8859_1 |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
11610 instruct encode_iso_array(eSIRegP src, eDIRegP dst, eDXRegI len, |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
11611 regD tmp1, regD tmp2, regD tmp3, regD tmp4, |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
11612 eCXRegI tmp5, eAXRegI result, eFlagsReg cr) %{ |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
11613 match(Set result (EncodeISOArray src (Binary dst len))); |
|
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11614 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr); |
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11615 |
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11616 format %{ "Encode array $src,$dst,$len -> $result // KILL ECX, EDX, $tmp1, $tmp2, $tmp3, $tmp4, ESI, EDI " %} |
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11617 ins_encode %{ |
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11618 __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register, |
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11619 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister, |
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11620 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register); |
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11621 %} |
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11622 ins_pipe( pipe_slow ); |
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11623 %} |
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11624 |
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11625 |
| 0 | 11626 //----------Control Flow Instructions------------------------------------------ |
| 11627 // Signed compare Instructions | |
|
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11628 instruct compI_eReg(eFlagsReg cr, rRegI op1, rRegI op2) %{ |
| 0 | 11629 match(Set cr (CmpI op1 op2)); |
| 11630 effect( DEF cr, USE op1, USE op2 ); | |
| 11631 format %{ "CMP $op1,$op2" %} | |
| 11632 opcode(0x3B); /* Opcode 3B /r */ | |
| 11633 ins_encode( OpcP, RegReg( op1, op2) ); | |
| 11634 ins_pipe( ialu_cr_reg_reg ); | |
| 11635 %} | |
| 11636 | |
|
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11637 instruct compI_eReg_imm(eFlagsReg cr, rRegI op1, immI op2) %{ |
| 0 | 11638 match(Set cr (CmpI op1 op2)); |
| 11639 effect( DEF cr, USE op1 ); | |
| 11640 format %{ "CMP $op1,$op2" %} | |
| 11641 opcode(0x81,0x07); /* Opcode 81 /7 */ | |
| 11642 // ins_encode( RegImm( op1, op2) ); /* Was CmpImm */ | |
| 11643 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) ); | |
| 11644 ins_pipe( ialu_cr_reg_imm ); | |
| 11645 %} | |
| 11646 | |
| 11647 // Cisc-spilled version of cmpI_eReg | |
|
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11648 instruct compI_eReg_mem(eFlagsReg cr, rRegI op1, memory op2) %{ |
| 0 | 11649 match(Set cr (CmpI op1 (LoadI op2))); |
| 11650 | |
| 11651 format %{ "CMP $op1,$op2" %} | |
| 11652 ins_cost(500); | |
| 11653 opcode(0x3B); /* Opcode 3B /r */ | |
| 11654 ins_encode( OpcP, RegMem( op1, op2) ); | |
| 11655 ins_pipe( ialu_cr_reg_mem ); | |
| 11656 %} | |
| 11657 | |
|
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11658 instruct testI_reg( eFlagsReg cr, rRegI src, immI0 zero ) %{ |
| 0 | 11659 match(Set cr (CmpI src zero)); |
| 11660 effect( DEF cr, USE src ); | |
| 11661 | |
| 11662 format %{ "TEST $src,$src" %} | |
| 11663 opcode(0x85); | |
| 11664 ins_encode( OpcP, RegReg( src, src ) ); | |
| 11665 ins_pipe( ialu_cr_reg_imm ); | |
| 11666 %} | |
| 11667 | |
|
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11668 instruct testI_reg_imm( eFlagsReg cr, rRegI src, immI con, immI0 zero ) %{ |
| 0 | 11669 match(Set cr (CmpI (AndI src con) zero)); |
| 11670 | |
| 11671 format %{ "TEST $src,$con" %} | |
| 11672 opcode(0xF7,0x00); | |
| 11673 ins_encode( OpcP, RegOpc(src), Con32(con) ); | |
| 11674 ins_pipe( ialu_cr_reg_imm ); | |
| 11675 %} | |
| 11676 | |
|
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11677 instruct testI_reg_mem( eFlagsReg cr, rRegI src, memory mem, immI0 zero ) %{ |
| 0 | 11678 match(Set cr (CmpI (AndI src mem) zero)); |
| 11679 | |
| 11680 format %{ "TEST $src,$mem" %} | |
| 11681 opcode(0x85); | |
| 11682 ins_encode( OpcP, RegMem( src, mem ) ); | |
| 11683 ins_pipe( ialu_cr_reg_mem ); | |
| 11684 %} | |
| 11685 | |
| 11686 // Unsigned compare Instructions; really, same as signed except they | |
| 11687 // produce an eFlagsRegU instead of eFlagsReg. | |
|
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11688 instruct compU_eReg(eFlagsRegU cr, rRegI op1, rRegI op2) %{ |
| 0 | 11689 match(Set cr (CmpU op1 op2)); |
| 11690 | |
| 11691 format %{ "CMPu $op1,$op2" %} | |
| 11692 opcode(0x3B); /* Opcode 3B /r */ | |
| 11693 ins_encode( OpcP, RegReg( op1, op2) ); | |
| 11694 ins_pipe( ialu_cr_reg_reg ); | |
| 11695 %} | |
| 11696 | |
|
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11697 instruct compU_eReg_imm(eFlagsRegU cr, rRegI op1, immI op2) %{ |
| 0 | 11698 match(Set cr (CmpU op1 op2)); |
| 11699 | |
| 11700 format %{ "CMPu $op1,$op2" %} | |
| 11701 opcode(0x81,0x07); /* Opcode 81 /7 */ | |
| 11702 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) ); | |
| 11703 ins_pipe( ialu_cr_reg_imm ); | |
| 11704 %} | |
| 11705 | |
| 11706 // // Cisc-spilled version of cmpU_eReg | |
|
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11707 instruct compU_eReg_mem(eFlagsRegU cr, rRegI op1, memory op2) %{ |
| 0 | 11708 match(Set cr (CmpU op1 (LoadI op2))); |
| 11709 | |
| 11710 format %{ "CMPu $op1,$op2" %} | |
| 11711 ins_cost(500); | |
| 11712 opcode(0x3B); /* Opcode 3B /r */ | |
| 11713 ins_encode( OpcP, RegMem( op1, op2) ); | |
| 11714 ins_pipe( ialu_cr_reg_mem ); | |
| 11715 %} | |
| 11716 | |
| 11717 // // Cisc-spilled version of cmpU_eReg | |
|
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11718 //instruct compU_mem_eReg(eFlagsRegU cr, memory op1, rRegI op2) %{ |
| 0 | 11719 // match(Set cr (CmpU (LoadI op1) op2)); |
| 11720 // | |
| 11721 // format %{ "CMPu $op1,$op2" %} | |
| 11722 // ins_cost(500); | |
| 11723 // opcode(0x39); /* Opcode 39 /r */ | |
| 11724 // ins_encode( OpcP, RegMem( op1, op2) ); | |
| 11725 //%} | |
| 11726 | |
|
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11727 instruct testU_reg( eFlagsRegU cr, rRegI src, immI0 zero ) %{ |
| 0 | 11728 match(Set cr (CmpU src zero)); |
| 11729 | |
| 11730 format %{ "TESTu $src,$src" %} | |
| 11731 opcode(0x85); | |
| 11732 ins_encode( OpcP, RegReg( src, src ) ); | |
| 11733 ins_pipe( ialu_cr_reg_imm ); | |
| 11734 %} | |
| 11735 | |
| 11736 // Unsigned pointer compare Instructions | |
| 11737 instruct compP_eReg(eFlagsRegU cr, eRegP op1, eRegP op2) %{ | |
| 11738 match(Set cr (CmpP op1 op2)); | |
| 11739 | |
| 11740 format %{ "CMPu $op1,$op2" %} | |
| 11741 opcode(0x3B); /* Opcode 3B /r */ | |
| 11742 ins_encode( OpcP, RegReg( op1, op2) ); | |
| 11743 ins_pipe( ialu_cr_reg_reg ); | |
| 11744 %} | |
| 11745 | |
| 11746 instruct compP_eReg_imm(eFlagsRegU cr, eRegP op1, immP op2) %{ | |
| 11747 match(Set cr (CmpP op1 op2)); | |
| 11748 | |
| 11749 format %{ "CMPu $op1,$op2" %} | |
| 11750 opcode(0x81,0x07); /* Opcode 81 /7 */ | |
| 11751 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) ); | |
| 11752 ins_pipe( ialu_cr_reg_imm ); | |
| 11753 %} | |
| 11754 | |
| 11755 // // Cisc-spilled version of cmpP_eReg | |
| 11756 instruct compP_eReg_mem(eFlagsRegU cr, eRegP op1, memory op2) %{ | |
| 11757 match(Set cr (CmpP op1 (LoadP op2))); | |
| 11758 | |
| 11759 format %{ "CMPu $op1,$op2" %} | |
| 11760 ins_cost(500); | |
| 11761 opcode(0x3B); /* Opcode 3B /r */ | |
| 11762 ins_encode( OpcP, RegMem( op1, op2) ); | |
| 11763 ins_pipe( ialu_cr_reg_mem ); | |
| 11764 %} | |
| 11765 | |
| 11766 // // Cisc-spilled version of cmpP_eReg | |
| 11767 //instruct compP_mem_eReg(eFlagsRegU cr, memory op1, eRegP op2) %{ | |
| 11768 // match(Set cr (CmpP (LoadP op1) op2)); | |
| 11769 // | |
| 11770 // format %{ "CMPu $op1,$op2" %} | |
| 11771 // ins_cost(500); | |
| 11772 // opcode(0x39); /* Opcode 39 /r */ | |
| 11773 // ins_encode( OpcP, RegMem( op1, op2) ); | |
| 11774 //%} | |
| 11775 | |
| 11776 // Compare raw pointer (used in out-of-heap check). | |
| 11777 // Only works because non-oop pointers must be raw pointers | |
| 11778 // and raw pointers have no anti-dependencies. | |
| 11779 instruct compP_mem_eReg( eFlagsRegU cr, eRegP op1, memory op2 ) %{ | |
|
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11780 predicate( n->in(2)->in(2)->bottom_type()->reloc() == relocInfo::none ); |
| 0 | 11781 match(Set cr (CmpP op1 (LoadP op2))); |
| 11782 | |
| 11783 format %{ "CMPu $op1,$op2" %} | |
| 11784 opcode(0x3B); /* Opcode 3B /r */ | |
| 11785 ins_encode( OpcP, RegMem( op1, op2) ); | |
| 11786 ins_pipe( ialu_cr_reg_mem ); | |
| 11787 %} | |
| 11788 | |
| 11789 // | |
| 11790 // This will generate a signed flags result. This should be ok | |
| 11791 // since any compare to a zero should be eq/neq. | |
| 11792 instruct testP_reg( eFlagsReg cr, eRegP src, immP0 zero ) %{ | |
| 11793 match(Set cr (CmpP src zero)); | |
| 11794 | |
| 11795 format %{ "TEST $src,$src" %} | |
| 11796 opcode(0x85); | |
| 11797 ins_encode( OpcP, RegReg( src, src ) ); | |
| 11798 ins_pipe( ialu_cr_reg_imm ); | |
| 11799 %} | |
| 11800 | |
| 11801 // Cisc-spilled version of testP_reg | |
| 11802 // This will generate a signed flags result. This should be ok | |
| 11803 // since any compare to a zero should be eq/neq. | |
| 11804 instruct testP_Reg_mem( eFlagsReg cr, memory op, immI0 zero ) %{ | |
| 11805 match(Set cr (CmpP (LoadP op) zero)); | |
| 11806 | |
| 11807 format %{ "TEST $op,0xFFFFFFFF" %} | |
| 11808 ins_cost(500); | |
| 11809 opcode(0xF7); /* Opcode F7 /0 */ | |
| 11810 ins_encode( OpcP, RMopc_Mem(0x00,op), Con_d32(0xFFFFFFFF) ); | |
| 11811 ins_pipe( ialu_cr_reg_imm ); | |
| 11812 %} | |
| 11813 | |
| 11814 // Yanked all unsigned pointer compare operations. | |
| 11815 // Pointer compares are done with CmpP which is already unsigned. | |
| 11816 | |
| 11817 //----------Max and Min-------------------------------------------------------- | |
| 11818 // Min Instructions | |
| 11819 //// | |
| 11820 // *** Min and Max using the conditional move are slower than the | |
| 11821 // *** branch version on a Pentium III. | |
| 11822 // // Conditional move for min | |
|
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11823 //instruct cmovI_reg_lt( rRegI op2, rRegI op1, eFlagsReg cr ) %{ |
| 0 | 11824 // effect( USE_DEF op2, USE op1, USE cr ); |
| 11825 // format %{ "CMOVlt $op2,$op1\t! min" %} | |
| 11826 // opcode(0x4C,0x0F); | |
| 11827 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) ); | |
| 11828 // ins_pipe( pipe_cmov_reg ); | |
| 11829 //%} | |
| 11830 // | |
| 11831 //// Min Register with Register (P6 version) | |
|
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11832 //instruct minI_eReg_p6( rRegI op1, rRegI op2 ) %{ |
| 0 | 11833 // predicate(VM_Version::supports_cmov() ); |
| 11834 // match(Set op2 (MinI op1 op2)); | |
| 11835 // ins_cost(200); | |
| 11836 // expand %{ | |
| 11837 // eFlagsReg cr; | |
| 11838 // compI_eReg(cr,op1,op2); | |
| 11839 // cmovI_reg_lt(op2,op1,cr); | |
| 11840 // %} | |
| 11841 //%} | |
| 11842 | |
| 11843 // Min Register with Register (generic version) | |
|
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11844 instruct minI_eReg(rRegI dst, rRegI src, eFlagsReg flags) %{ |
| 0 | 11845 match(Set dst (MinI dst src)); |
| 11846 effect(KILL flags); | |
| 11847 ins_cost(300); | |
| 11848 | |
| 11849 format %{ "MIN $dst,$src" %} | |
| 11850 opcode(0xCC); | |
| 11851 ins_encode( min_enc(dst,src) ); | |
| 11852 ins_pipe( pipe_slow ); | |
| 11853 %} | |
| 11854 | |
| 11855 // Max Register with Register | |
| 11856 // *** Min and Max using the conditional move are slower than the | |
| 11857 // *** branch version on a Pentium III. | |
| 11858 // // Conditional move for max | |
|
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11859 //instruct cmovI_reg_gt( rRegI op2, rRegI op1, eFlagsReg cr ) %{ |
| 0 | 11860 // effect( USE_DEF op2, USE op1, USE cr ); |
| 11861 // format %{ "CMOVgt $op2,$op1\t! max" %} | |
| 11862 // opcode(0x4F,0x0F); | |
| 11863 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) ); | |
| 11864 // ins_pipe( pipe_cmov_reg ); | |
| 11865 //%} | |
| 11866 // | |
| 11867 // // Max Register with Register (P6 version) | |
|
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11868 //instruct maxI_eReg_p6( rRegI op1, rRegI op2 ) %{ |
| 0 | 11869 // predicate(VM_Version::supports_cmov() ); |
| 11870 // match(Set op2 (MaxI op1 op2)); | |
| 11871 // ins_cost(200); | |
| 11872 // expand %{ | |
| 11873 // eFlagsReg cr; | |
| 11874 // compI_eReg(cr,op1,op2); | |
| 11875 // cmovI_reg_gt(op2,op1,cr); | |
| 11876 // %} | |
| 11877 //%} | |
| 11878 | |
| 11879 // Max Register with Register (generic version) | |
|
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11880 instruct maxI_eReg(rRegI dst, rRegI src, eFlagsReg flags) %{ |
| 0 | 11881 match(Set dst (MaxI dst src)); |
| 11882 effect(KILL flags); | |
| 11883 ins_cost(300); | |
| 11884 | |
| 11885 format %{ "MAX $dst,$src" %} | |
| 11886 opcode(0xCC); | |
| 11887 ins_encode( max_enc(dst,src) ); | |
| 11888 ins_pipe( pipe_slow ); | |
| 11889 %} | |
| 11890 | |
| 11891 // ============================================================================ | |
| 3345 | 11892 // Counted Loop limit node which represents exact final iterator value. |
| 11893 // Note: the resulting value should fit into integer range since | |
| 11894 // counted loops have limit check on overflow. | |
| 11895 instruct loopLimit_eReg(eAXRegI limit, nadxRegI init, immI stride, eDXRegI limit_hi, nadxRegI tmp, eFlagsReg flags) %{ | |
| 11896 match(Set limit (LoopLimit (Binary init limit) stride)); | |
| 11897 effect(TEMP limit_hi, TEMP tmp, KILL flags); | |
| 11898 ins_cost(300); | |
| 11899 | |
| 11900 format %{ "loopLimit $init,$limit,$stride # $limit = $init + $stride *( $limit - $init + $stride -1)/ $stride, kills $limit_hi" %} | |
| 11901 ins_encode %{ | |
| 11902 int strd = (int)$stride$$constant; | |
| 11903 assert(strd != 1 && strd != -1, "sanity"); | |
| 11904 int m1 = (strd > 0) ? 1 : -1; | |
| 11905 // Convert limit to long (EAX:EDX) | |
| 11906 __ cdql(); | |
| 11907 // Convert init to long (init:tmp) | |
| 11908 __ movl($tmp$$Register, $init$$Register); | |
| 11909 __ sarl($tmp$$Register, 31); | |
| 11910 // $limit - $init | |
| 11911 __ subl($limit$$Register, $init$$Register); | |
| 11912 __ sbbl($limit_hi$$Register, $tmp$$Register); | |
| 11913 // + ($stride - 1) | |
| 11914 if (strd > 0) { | |
| 11915 __ addl($limit$$Register, (strd - 1)); | |
| 11916 __ adcl($limit_hi$$Register, 0); | |
| 11917 __ movl($tmp$$Register, strd); | |
| 11918 } else { | |
| 11919 __ addl($limit$$Register, (strd + 1)); | |
| 11920 __ adcl($limit_hi$$Register, -1); | |
| 11921 __ lneg($limit_hi$$Register, $limit$$Register); | |
| 11922 __ movl($tmp$$Register, -strd); | |
| 11923 } | |
| 11924 // signed devision: (EAX:EDX) / pos_stride | |
| 11925 __ idivl($tmp$$Register); | |
| 11926 if (strd < 0) { | |
| 11927 // restore sign | |
| 11928 __ negl($tmp$$Register); | |
| 11929 } | |
| 11930 // (EAX) * stride | |
| 11931 __ mull($tmp$$Register); | |
| 11932 // + init (ignore upper bits) | |
| 11933 __ addl($limit$$Register, $init$$Register); | |
| 11934 %} | |
| 11935 ins_pipe( pipe_slow ); | |
| 11936 %} | |
| 11937 | |
| 11938 // ============================================================================ | |
| 0 | 11939 // Branch Instructions |
| 11940 // Jump Table | |
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11941 instruct jumpXtnd(rRegI switch_val) %{ |
| 0 | 11942 match(Jump switch_val); |
| 11943 ins_cost(350); | |
| 2008 | 11944 format %{ "JMP [$constantaddress](,$switch_val,1)\n\t" %} |
| 11945 ins_encode %{ | |
| 0 | 11946 // Jump to Address(table_base + switch_reg) |
| 11947 Address index(noreg, $switch_val$$Register, Address::times_1); | |
| 2008 | 11948 __ jump(ArrayAddress($constantaddress, index)); |
| 0 | 11949 %} |
| 11950 ins_pipe(pipe_jmp); | |
| 11951 %} | |
| 11952 | |
| 11953 // Jump Direct - Label defines a relative address from JMP+1 | |
| 11954 instruct jmpDir(label labl) %{ | |
| 11955 match(Goto); | |
| 11956 effect(USE labl); | |
| 11957 | |
| 11958 ins_cost(300); | |
| 11959 format %{ "JMP $labl" %} | |
| 11960 size(5); | |
| 3851 | 11961 ins_encode %{ |
| 11962 Label* L = $labl$$label; | |
| 11963 __ jmp(*L, false); // Always long jump | |
| 11964 %} | |
| 0 | 11965 ins_pipe( pipe_jmp ); |
| 11966 %} | |
| 11967 | |
| 11968 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 11969 instruct jmpCon(cmpOp cop, eFlagsReg cr, label labl) %{ | |
| 11970 match(If cop cr); | |
| 11971 effect(USE labl); | |
| 11972 | |
| 11973 ins_cost(300); | |
| 11974 format %{ "J$cop $labl" %} | |
| 11975 size(6); | |
| 3851 | 11976 ins_encode %{ |
| 11977 Label* L = $labl$$label; | |
| 11978 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 11979 %} | |
| 0 | 11980 ins_pipe( pipe_jcc ); |
| 11981 %} | |
| 11982 | |
| 11983 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 11984 instruct jmpLoopEnd(cmpOp cop, eFlagsReg cr, label labl) %{ | |
| 11985 match(CountedLoopEnd cop cr); | |
| 11986 effect(USE labl); | |
| 11987 | |
| 11988 ins_cost(300); | |
| 11989 format %{ "J$cop $labl\t# Loop end" %} | |
| 11990 size(6); | |
| 3851 | 11991 ins_encode %{ |
| 11992 Label* L = $labl$$label; | |
| 11993 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 11994 %} | |
| 0 | 11995 ins_pipe( pipe_jcc ); |
| 11996 %} | |
| 11997 | |
| 11998 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 11999 instruct jmpLoopEndU(cmpOpU cop, eFlagsRegU cmp, label labl) %{ | |
| 12000 match(CountedLoopEnd cop cmp); | |
| 12001 effect(USE labl); | |
| 12002 | |
| 12003 ins_cost(300); | |
| 12004 format %{ "J$cop,u $labl\t# Loop end" %} | |
| 12005 size(6); | |
| 3851 | 12006 ins_encode %{ |
| 12007 Label* L = $labl$$label; | |
| 12008 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 12009 %} | |
| 0 | 12010 ins_pipe( pipe_jcc ); |
| 12011 %} | |
| 12012 | |
|
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|
12013 instruct jmpLoopEndUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{ |
|
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|
12014 match(CountedLoopEnd cop cmp); |
|
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|
12015 effect(USE labl); |
|
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|
12016 |
|
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changeset
|
12017 ins_cost(200); |
|
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|
12018 format %{ "J$cop,u $labl\t# Loop end" %} |
|
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|
12019 size(6); |
| 3851 | 12020 ins_encode %{ |
| 12021 Label* L = $labl$$label; | |
| 12022 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 12023 %} | |
|
415
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|
12024 ins_pipe( pipe_jcc ); |
|
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|
12025 %} |
|
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|
12026 |
| 0 | 12027 // Jump Direct Conditional - using unsigned comparison |
| 12028 instruct jmpConU(cmpOpU cop, eFlagsRegU cmp, label labl) %{ | |
| 12029 match(If cop cmp); | |
| 12030 effect(USE labl); | |
| 12031 | |
| 12032 ins_cost(300); | |
| 12033 format %{ "J$cop,u $labl" %} | |
| 12034 size(6); | |
| 3851 | 12035 ins_encode %{ |
| 12036 Label* L = $labl$$label; | |
| 12037 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 12038 %} | |
|
415
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|
12039 ins_pipe(pipe_jcc); |
|
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diff
changeset
|
12040 %} |
|
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changeset
|
12041 |
|
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changeset
|
12042 instruct jmpConUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{ |
|
4d9884b01ba6
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|
12043 match(If cop cmp); |
|
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diff
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|
12044 effect(USE labl); |
|
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|
12045 |
|
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changeset
|
12046 ins_cost(200); |
|
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|
12047 format %{ "J$cop,u $labl" %} |
|
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|
12048 size(6); |
| 3851 | 12049 ins_encode %{ |
| 12050 Label* L = $labl$$label; | |
| 12051 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 12052 %} | |
|
415
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|
12053 ins_pipe(pipe_jcc); |
|
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diff
changeset
|
12054 %} |
|
4d9884b01ba6
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parents:
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diff
changeset
|
12055 |
|
4d9884b01ba6
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parents:
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diff
changeset
|
12056 instruct jmpConUCF2(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{ |
|
4d9884b01ba6
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diff
changeset
|
12057 match(If cop cmp); |
|
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never
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diff
changeset
|
12058 effect(USE labl); |
|
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diff
changeset
|
12059 |
|
4d9884b01ba6
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diff
changeset
|
12060 ins_cost(200); |
|
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diff
changeset
|
12061 format %{ $$template |
|
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diff
changeset
|
12062 if ($cop$$cmpcode == Assembler::notEqual) { |
|
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|
12063 $$emit$$"JP,u $labl\n\t" |
|
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|
12064 $$emit$$"J$cop,u $labl" |
|
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|
12065 } else { |
|
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changeset
|
12066 $$emit$$"JP,u done\n\t" |
|
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|
12067 $$emit$$"J$cop,u $labl\n\t" |
|
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changeset
|
12068 $$emit$$"done:" |
|
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changeset
|
12069 } |
|
4d9884b01ba6
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changeset
|
12070 %} |
|
4d9884b01ba6
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diff
changeset
|
12071 ins_encode %{ |
|
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changeset
|
12072 Label* l = $labl$$label; |
|
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|
12073 if ($cop$$cmpcode == Assembler::notEqual) { |
| 3851 | 12074 __ jcc(Assembler::parity, *l, false); |
| 12075 __ jcc(Assembler::notEqual, *l, false); | |
|
415
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|
12076 } else if ($cop$$cmpcode == Assembler::equal) { |
| 3851 | 12077 Label done; |
| 12078 __ jccb(Assembler::parity, done); | |
| 12079 __ jcc(Assembler::equal, *l, false); | |
| 12080 __ bind(done); | |
|
415
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|
12081 } else { |
|
4d9884b01ba6
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changeset
|
12082 ShouldNotReachHere(); |
|
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changeset
|
12083 } |
|
4d9884b01ba6
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changeset
|
12084 %} |
|
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changeset
|
12085 ins_pipe(pipe_jcc); |
| 0 | 12086 %} |
| 12087 | |
| 12088 // ============================================================================ | |
| 12089 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass | |
| 12090 // array for an instance of the superklass. Set a hidden internal cache on a | |
| 12091 // hit (cache is checked with exposed code in gen_subtype_check()). Return | |
| 12092 // NZ for a miss or zero for a hit. The encoding ALSO sets flags. | |
| 12093 instruct partialSubtypeCheck( eDIRegP result, eSIRegP sub, eAXRegP super, eCXRegI rcx, eFlagsReg cr ) %{ | |
| 12094 match(Set result (PartialSubtypeCheck sub super)); | |
| 12095 effect( KILL rcx, KILL cr ); | |
| 12096 | |
| 12097 ins_cost(1100); // slightly larger than the next version | |
|
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
12098 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t" |
|
6831
d8ce2825b193
8000213: NPG: Should have renamed arrayKlass and typeArrayKlass
coleenp
parents:
6795
diff
changeset
|
12099 "MOV ECX,[EDI+ArrayKlass::length]\t# length to scan\n\t" |
|
d8ce2825b193
8000213: NPG: Should have renamed arrayKlass and typeArrayKlass
coleenp
parents:
6795
diff
changeset
|
12100 "ADD EDI,ArrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t" |
| 0 | 12101 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t" |
| 12102 "JNE,s miss\t\t# Missed: EDI not-zero\n\t" | |
| 12103 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache\n\t" | |
| 12104 "XOR $result,$result\t\t Hit: EDI zero\n\t" | |
| 12105 "miss:\t" %} | |
| 12106 | |
| 12107 opcode(0x1); // Force a XOR of EDI | |
| 12108 ins_encode( enc_PartialSubtypeCheck() ); | |
| 12109 ins_pipe( pipe_slow ); | |
| 12110 %} | |
| 12111 | |
| 12112 instruct partialSubtypeCheck_vs_Zero( eFlagsReg cr, eSIRegP sub, eAXRegP super, eCXRegI rcx, eDIRegP result, immP0 zero ) %{ | |
| 12113 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero)); | |
| 12114 effect( KILL rcx, KILL result ); | |
| 12115 | |
| 12116 ins_cost(1000); | |
|
644
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
12117 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t" |
|
6831
d8ce2825b193
8000213: NPG: Should have renamed arrayKlass and typeArrayKlass
coleenp
parents:
6795
diff
changeset
|
12118 "MOV ECX,[EDI+ArrayKlass::length]\t# length to scan\n\t" |
|
d8ce2825b193
8000213: NPG: Should have renamed arrayKlass and typeArrayKlass
coleenp
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6795
diff
changeset
|
12119 "ADD EDI,ArrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t" |
| 0 | 12120 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t" |
| 12121 "JNE,s miss\t\t# Missed: flags NZ\n\t" | |
| 12122 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache, flags Z\n\t" | |
| 12123 "miss:\t" %} | |
| 12124 | |
| 12125 opcode(0x0); // No need to XOR EDI | |
| 12126 ins_encode( enc_PartialSubtypeCheck() ); | |
| 12127 ins_pipe( pipe_slow ); | |
| 12128 %} | |
| 12129 | |
| 12130 // ============================================================================ | |
| 12131 // Branch Instructions -- short offset versions | |
| 12132 // | |
| 12133 // These instructions are used to replace jumps of a long offset (the default | |
| 12134 // match) with jumps of a shorter offset. These instructions are all tagged | |
| 12135 // with the ins_short_branch attribute, which causes the ADLC to suppress the | |
| 12136 // match rules in general matching. Instead, the ADLC generates a conversion | |
| 12137 // method in the MachNode which can be used to do in-place replacement of the | |
| 12138 // long variant with the shorter variant. The compiler will determine if a | |
| 12139 // branch can be taken by the is_short_branch_offset() predicate in the machine | |
| 12140 // specific code section of the file. | |
| 12141 | |
| 12142 // Jump Direct - Label defines a relative address from JMP+1 | |
| 12143 instruct jmpDir_short(label labl) %{ | |
| 12144 match(Goto); | |
| 12145 effect(USE labl); | |
| 12146 | |
| 12147 ins_cost(300); | |
| 12148 format %{ "JMP,s $labl" %} | |
| 12149 size(2); | |
| 3851 | 12150 ins_encode %{ |
| 12151 Label* L = $labl$$label; | |
| 12152 __ jmpb(*L); | |
| 12153 %} | |
| 0 | 12154 ins_pipe( pipe_jmp ); |
| 12155 ins_short_branch(1); | |
| 12156 %} | |
| 12157 | |
| 12158 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 12159 instruct jmpCon_short(cmpOp cop, eFlagsReg cr, label labl) %{ | |
| 12160 match(If cop cr); | |
| 12161 effect(USE labl); | |
| 12162 | |
| 12163 ins_cost(300); | |
| 12164 format %{ "J$cop,s $labl" %} | |
| 12165 size(2); | |
| 3851 | 12166 ins_encode %{ |
| 12167 Label* L = $labl$$label; | |
| 12168 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 12169 %} | |
| 0 | 12170 ins_pipe( pipe_jcc ); |
| 12171 ins_short_branch(1); | |
| 12172 %} | |
| 12173 | |
| 12174 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 12175 instruct jmpLoopEnd_short(cmpOp cop, eFlagsReg cr, label labl) %{ | |
| 12176 match(CountedLoopEnd cop cr); | |
| 12177 effect(USE labl); | |
| 12178 | |
| 12179 ins_cost(300); | |
|
415
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|
12180 format %{ "J$cop,s $labl\t# Loop end" %} |
| 0 | 12181 size(2); |
| 3851 | 12182 ins_encode %{ |
| 12183 Label* L = $labl$$label; | |
| 12184 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 12185 %} | |
| 0 | 12186 ins_pipe( pipe_jcc ); |
| 12187 ins_short_branch(1); | |
| 12188 %} | |
| 12189 | |
| 12190 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 12191 instruct jmpLoopEndU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{ | |
| 12192 match(CountedLoopEnd cop cmp); | |
| 12193 effect(USE labl); | |
| 12194 | |
| 12195 ins_cost(300); | |
|
415
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diff
changeset
|
12196 format %{ "J$cop,us $labl\t# Loop end" %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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parents:
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changeset
|
12197 size(2); |
| 3851 | 12198 ins_encode %{ |
| 12199 Label* L = $labl$$label; | |
| 12200 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 12201 %} | |
|
415
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changeset
|
12202 ins_pipe( pipe_jcc ); |
|
4d9884b01ba6
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parents:
403
diff
changeset
|
12203 ins_short_branch(1); |
|
4d9884b01ba6
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parents:
403
diff
changeset
|
12204 %} |
|
4d9884b01ba6
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parents:
403
diff
changeset
|
12205 |
|
4d9884b01ba6
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diff
changeset
|
12206 instruct jmpLoopEndUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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diff
changeset
|
12207 match(CountedLoopEnd cop cmp); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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403
diff
changeset
|
12208 effect(USE labl); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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parents:
403
diff
changeset
|
12209 |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
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403
diff
changeset
|
12210 ins_cost(300); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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parents:
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diff
changeset
|
12211 format %{ "J$cop,us $labl\t# Loop end" %} |
| 0 | 12212 size(2); |
| 3851 | 12213 ins_encode %{ |
| 12214 Label* L = $labl$$label; | |
| 12215 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 12216 %} | |
| 0 | 12217 ins_pipe( pipe_jcc ); |
| 12218 ins_short_branch(1); | |
| 12219 %} | |
| 12220 | |
| 12221 // Jump Direct Conditional - using unsigned comparison | |
| 12222 instruct jmpConU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{ | |
| 12223 match(If cop cmp); | |
| 12224 effect(USE labl); | |
| 12225 | |
| 12226 ins_cost(300); | |
| 12227 format %{ "J$cop,us $labl" %} | |
| 12228 size(2); | |
| 3851 | 12229 ins_encode %{ |
| 12230 Label* L = $labl$$label; | |
| 12231 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 12232 %} | |
| 0 | 12233 ins_pipe( pipe_jcc ); |
| 12234 ins_short_branch(1); | |
| 12235 %} | |
| 12236 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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parents:
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diff
changeset
|
12237 instruct jmpConUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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parents:
403
diff
changeset
|
12238 match(If cop cmp); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12239 effect(USE labl); |
|
4d9884b01ba6
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parents:
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|
12240 |
|
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|
12241 ins_cost(300); |
|
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|
12242 format %{ "J$cop,us $labl" %} |
|
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diff
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|
12243 size(2); |
| 3851 | 12244 ins_encode %{ |
| 12245 Label* L = $labl$$label; | |
| 12246 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 12247 %} | |
|
415
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|
12248 ins_pipe( pipe_jcc ); |
|
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|
12249 ins_short_branch(1); |
|
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changeset
|
12250 %} |
|
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parents:
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diff
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|
12251 |
|
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diff
changeset
|
12252 instruct jmpConUCF2_short(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{ |
|
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|
12253 match(If cop cmp); |
|
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|
12254 effect(USE labl); |
|
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|
12255 |
|
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diff
changeset
|
12256 ins_cost(300); |
|
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diff
changeset
|
12257 format %{ $$template |
|
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|
12258 if ($cop$$cmpcode == Assembler::notEqual) { |
|
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|
12259 $$emit$$"JP,u,s $labl\n\t" |
|
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|
12260 $$emit$$"J$cop,u,s $labl" |
|
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|
12261 } else { |
|
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changeset
|
12262 $$emit$$"JP,u,s done\n\t" |
|
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|
12263 $$emit$$"J$cop,u,s $labl\n\t" |
|
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changeset
|
12264 $$emit$$"done:" |
|
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never
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changeset
|
12265 } |
|
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never
parents:
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diff
changeset
|
12266 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12267 size(4); |
|
4d9884b01ba6
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never
parents:
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diff
changeset
|
12268 ins_encode %{ |
|
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never
parents:
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diff
changeset
|
12269 Label* l = $labl$$label; |
|
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diff
changeset
|
12270 if ($cop$$cmpcode == Assembler::notEqual) { |
| 3851 | 12271 __ jccb(Assembler::parity, *l); |
| 12272 __ jccb(Assembler::notEqual, *l); | |
|
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|
12273 } else if ($cop$$cmpcode == Assembler::equal) { |
| 3851 | 12274 Label done; |
| 12275 __ jccb(Assembler::parity, done); | |
| 12276 __ jccb(Assembler::equal, *l); | |
| 12277 __ bind(done); | |
|
415
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|
12278 } else { |
| 3851 | 12279 ShouldNotReachHere(); |
| 12280 } | |
|
415
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diff
changeset
|
12281 %} |
|
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diff
changeset
|
12282 ins_pipe(pipe_jcc); |
|
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|
12283 ins_short_branch(1); |
|
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diff
changeset
|
12284 %} |
|
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|
12285 |
| 0 | 12286 // ============================================================================ |
| 12287 // Long Compare | |
| 12288 // | |
| 12289 // Currently we hold longs in 2 registers. Comparing such values efficiently | |
| 12290 // is tricky. The flavor of compare used depends on whether we are testing | |
| 12291 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit. | |
| 12292 // The GE test is the negated LT test. The LE test can be had by commuting | |
| 12293 // the operands (yielding a GE test) and then negating; negate again for the | |
| 12294 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the | |
| 12295 // NE test is negated from that. | |
| 12296 | |
| 12297 // Due to a shortcoming in the ADLC, it mixes up expressions like: | |
| 12298 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the | |
| 12299 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections | |
| 12300 // are collapsed internally in the ADLC's dfa-gen code. The match for | |
| 12301 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the | |
| 12302 // foo match ends up with the wrong leaf. One fix is to not match both | |
| 12303 // reg-reg and reg-zero forms of long-compare. This is unfortunate because | |
| 12304 // both forms beat the trinary form of long-compare and both are very useful | |
| 12305 // on Intel which has so few registers. | |
| 12306 | |
| 12307 // Manifest a CmpL result in an integer register. Very painful. | |
| 12308 // This is the test to avoid. | |
| 12309 instruct cmpL3_reg_reg(eSIRegI dst, eRegL src1, eRegL src2, eFlagsReg flags ) %{ | |
| 12310 match(Set dst (CmpL3 src1 src2)); | |
| 12311 effect( KILL flags ); | |
| 12312 ins_cost(1000); | |
| 12313 format %{ "XOR $dst,$dst\n\t" | |
| 12314 "CMP $src1.hi,$src2.hi\n\t" | |
| 12315 "JLT,s m_one\n\t" | |
| 12316 "JGT,s p_one\n\t" | |
| 12317 "CMP $src1.lo,$src2.lo\n\t" | |
| 12318 "JB,s m_one\n\t" | |
| 12319 "JEQ,s done\n" | |
| 12320 "p_one:\tINC $dst\n\t" | |
| 12321 "JMP,s done\n" | |
| 12322 "m_one:\tDEC $dst\n" | |
| 12323 "done:" %} | |
| 12324 ins_encode %{ | |
| 12325 Label p_one, m_one, done; | |
| 304 | 12326 __ xorptr($dst$$Register, $dst$$Register); |
| 0 | 12327 __ cmpl(HIGH_FROM_LOW($src1$$Register), HIGH_FROM_LOW($src2$$Register)); |
| 12328 __ jccb(Assembler::less, m_one); | |
| 12329 __ jccb(Assembler::greater, p_one); | |
| 12330 __ cmpl($src1$$Register, $src2$$Register); | |
| 12331 __ jccb(Assembler::below, m_one); | |
| 12332 __ jccb(Assembler::equal, done); | |
| 12333 __ bind(p_one); | |
| 304 | 12334 __ incrementl($dst$$Register); |
| 0 | 12335 __ jmpb(done); |
| 12336 __ bind(m_one); | |
| 304 | 12337 __ decrementl($dst$$Register); |
| 0 | 12338 __ bind(done); |
| 12339 %} | |
| 12340 ins_pipe( pipe_slow ); | |
| 12341 %} | |
| 12342 | |
| 12343 //====== | |
| 12344 // Manifest a CmpL result in the normal flags. Only good for LT or GE | |
| 12345 // compares. Can be used for LE or GT compares by reversing arguments. | |
| 12346 // NOT GOOD FOR EQ/NE tests. | |
| 12347 instruct cmpL_zero_flags_LTGE( flagsReg_long_LTGE flags, eRegL src, immL0 zero ) %{ | |
| 12348 match( Set flags (CmpL src zero )); | |
| 12349 ins_cost(100); | |
| 12350 format %{ "TEST $src.hi,$src.hi" %} | |
| 12351 opcode(0x85); | |
| 12352 ins_encode( OpcP, RegReg_Hi2( src, src ) ); | |
| 12353 ins_pipe( ialu_cr_reg_reg ); | |
| 12354 %} | |
| 12355 | |
| 12356 // Manifest a CmpL result in the normal flags. Only good for LT or GE | |
| 12357 // compares. Can be used for LE or GT compares by reversing arguments. | |
| 12358 // NOT GOOD FOR EQ/NE tests. | |
|
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|
12359 instruct cmpL_reg_flags_LTGE( flagsReg_long_LTGE flags, eRegL src1, eRegL src2, rRegI tmp ) %{ |
| 0 | 12360 match( Set flags (CmpL src1 src2 )); |
| 12361 effect( TEMP tmp ); | |
| 12362 ins_cost(300); | |
| 12363 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t" | |
| 12364 "MOV $tmp,$src1.hi\n\t" | |
| 12365 "SBB $tmp,$src2.hi\t! Compute flags for long compare" %} | |
| 12366 ins_encode( long_cmp_flags2( src1, src2, tmp ) ); | |
| 12367 ins_pipe( ialu_cr_reg_reg ); | |
| 12368 %} | |
| 12369 | |
| 12370 // Long compares reg < zero/req OR reg >= zero/req. | |
| 12371 // Just a wrapper for a normal branch, plus the predicate test. | |
| 12372 instruct cmpL_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, label labl) %{ | |
| 12373 match(If cmp flags); | |
| 12374 effect(USE labl); | |
| 12375 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); | |
| 12376 expand %{ | |
| 12377 jmpCon(cmp,flags,labl); // JLT or JGE... | |
| 12378 %} | |
| 12379 %} | |
| 12380 | |
| 12381 // Compare 2 longs and CMOVE longs. | |
| 12382 instruct cmovLL_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, eRegL src) %{ | |
| 12383 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src))); | |
| 12384 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); | |
| 12385 ins_cost(400); | |
| 12386 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" | |
| 12387 "CMOV$cmp $dst.hi,$src.hi" %} | |
| 12388 opcode(0x0F,0x40); | |
| 12389 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) ); | |
| 12390 ins_pipe( pipe_cmov_reg_long ); | |
| 12391 %} | |
| 12392 | |
| 12393 instruct cmovLL_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, load_long_memory src) %{ | |
| 12394 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src)))); | |
| 12395 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); | |
| 12396 ins_cost(500); | |
| 12397 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" | |
| 12398 "CMOV$cmp $dst.hi,$src.hi" %} | |
| 12399 opcode(0x0F,0x40); | |
| 12400 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) ); | |
| 12401 ins_pipe( pipe_cmov_reg_long ); | |
| 12402 %} | |
| 12403 | |
| 12404 // Compare 2 longs and CMOVE ints. | |
|
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|
12405 instruct cmovII_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, rRegI dst, rRegI src) %{ |
| 0 | 12406 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); |
| 12407 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src))); | |
| 12408 ins_cost(200); | |
| 12409 format %{ "CMOV$cmp $dst,$src" %} | |
| 12410 opcode(0x0F,0x40); | |
| 12411 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); | |
| 12412 ins_pipe( pipe_cmov_reg ); | |
| 12413 %} | |
| 12414 | |
|
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|
12415 instruct cmovII_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, rRegI dst, memory src) %{ |
| 0 | 12416 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); |
| 12417 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src)))); | |
| 12418 ins_cost(250); | |
| 12419 format %{ "CMOV$cmp $dst,$src" %} | |
| 12420 opcode(0x0F,0x40); | |
| 12421 ins_encode( enc_cmov(cmp), RegMem( dst, src ) ); | |
| 12422 ins_pipe( pipe_cmov_mem ); | |
| 12423 %} | |
| 12424 | |
| 12425 // Compare 2 longs and CMOVE ints. | |
| 12426 instruct cmovPP_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegP dst, eRegP src) %{ | |
| 12427 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); | |
| 12428 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src))); | |
| 12429 ins_cost(200); | |
| 12430 format %{ "CMOV$cmp $dst,$src" %} | |
| 12431 opcode(0x0F,0x40); | |
| 12432 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); | |
| 12433 ins_pipe( pipe_cmov_reg ); | |
| 12434 %} | |
| 12435 | |
| 12436 // Compare 2 longs and CMOVE doubles | |
|
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|
12437 instruct cmovDDPR_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regDPR dst, regDPR src) %{ |
| 0 | 12438 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); |
| 12439 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); | |
| 12440 ins_cost(200); | |
| 12441 expand %{ | |
|
4761
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|
12442 fcmovDPR_regS(cmp,flags,dst,src); |
| 0 | 12443 %} |
| 12444 %} | |
| 12445 | |
| 12446 // Compare 2 longs and CMOVE doubles | |
|
4761
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|
12447 instruct cmovDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regD dst, regD src) %{ |
| 0 | 12448 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); |
| 12449 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); | |
| 12450 ins_cost(200); | |
| 12451 expand %{ | |
|
4761
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|
12452 fcmovD_regS(cmp,flags,dst,src); |
|
65149e74c706
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|
12453 %} |
|
65149e74c706
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|
12454 %} |
|
65149e74c706
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|
12455 |
|
65149e74c706
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|
12456 instruct cmovFFPR_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regFPR dst, regFPR src) %{ |
|
65149e74c706
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|
12457 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); |
|
65149e74c706
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|
12458 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); |
|
65149e74c706
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changeset
|
12459 ins_cost(200); |
|
65149e74c706
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changeset
|
12460 expand %{ |
|
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|
12461 fcmovFPR_regS(cmp,flags,dst,src); |
| 0 | 12462 %} |
| 12463 %} | |
| 12464 | |
| 12465 instruct cmovFF_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regF dst, regF src) %{ | |
|
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|
12466 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); |
| 0 | 12467 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); |
| 12468 ins_cost(200); | |
| 12469 expand %{ | |
| 12470 fcmovF_regS(cmp,flags,dst,src); | |
| 12471 %} | |
| 12472 %} | |
| 12473 | |
| 12474 //====== | |
| 12475 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares. | |
|
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12476 instruct cmpL_zero_flags_EQNE( flagsReg_long_EQNE flags, eRegL src, immL0 zero, rRegI tmp ) %{ |
| 0 | 12477 match( Set flags (CmpL src zero )); |
| 12478 effect(TEMP tmp); | |
| 12479 ins_cost(200); | |
| 12480 format %{ "MOV $tmp,$src.lo\n\t" | |
| 12481 "OR $tmp,$src.hi\t! Long is EQ/NE 0?" %} | |
| 12482 ins_encode( long_cmp_flags0( src, tmp ) ); | |
| 12483 ins_pipe( ialu_reg_reg_long ); | |
| 12484 %} | |
| 12485 | |
| 12486 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares. | |
| 12487 instruct cmpL_reg_flags_EQNE( flagsReg_long_EQNE flags, eRegL src1, eRegL src2 ) %{ | |
| 12488 match( Set flags (CmpL src1 src2 )); | |
| 12489 ins_cost(200+300); | |
| 12490 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t" | |
| 12491 "JNE,s skip\n\t" | |
| 12492 "CMP $src1.hi,$src2.hi\n\t" | |
| 12493 "skip:\t" %} | |
| 12494 ins_encode( long_cmp_flags1( src1, src2 ) ); | |
| 12495 ins_pipe( ialu_cr_reg_reg ); | |
| 12496 %} | |
| 12497 | |
| 12498 // Long compare reg == zero/reg OR reg != zero/reg | |
| 12499 // Just a wrapper for a normal branch, plus the predicate test. | |
| 12500 instruct cmpL_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, label labl) %{ | |
| 12501 match(If cmp flags); | |
| 12502 effect(USE labl); | |
| 12503 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); | |
| 12504 expand %{ | |
| 12505 jmpCon(cmp,flags,labl); // JEQ or JNE... | |
| 12506 %} | |
| 12507 %} | |
| 12508 | |
| 12509 // Compare 2 longs and CMOVE longs. | |
| 12510 instruct cmovLL_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, eRegL src) %{ | |
| 12511 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src))); | |
| 12512 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); | |
| 12513 ins_cost(400); | |
| 12514 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" | |
| 12515 "CMOV$cmp $dst.hi,$src.hi" %} | |
| 12516 opcode(0x0F,0x40); | |
| 12517 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) ); | |
| 12518 ins_pipe( pipe_cmov_reg_long ); | |
| 12519 %} | |
| 12520 | |
| 12521 instruct cmovLL_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, load_long_memory src) %{ | |
| 12522 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src)))); | |
| 12523 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); | |
| 12524 ins_cost(500); | |
| 12525 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" | |
| 12526 "CMOV$cmp $dst.hi,$src.hi" %} | |
| 12527 opcode(0x0F,0x40); | |
| 12528 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) ); | |
| 12529 ins_pipe( pipe_cmov_reg_long ); | |
| 12530 %} | |
| 12531 | |
| 12532 // Compare 2 longs and CMOVE ints. | |
|
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12533 instruct cmovII_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, rRegI dst, rRegI src) %{ |
| 0 | 12534 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); |
| 12535 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src))); | |
| 12536 ins_cost(200); | |
| 12537 format %{ "CMOV$cmp $dst,$src" %} | |
| 12538 opcode(0x0F,0x40); | |
| 12539 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); | |
| 12540 ins_pipe( pipe_cmov_reg ); | |
| 12541 %} | |
| 12542 | |
|
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12543 instruct cmovII_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, rRegI dst, memory src) %{ |
| 0 | 12544 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); |
| 12545 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src)))); | |
| 12546 ins_cost(250); | |
| 12547 format %{ "CMOV$cmp $dst,$src" %} | |
| 12548 opcode(0x0F,0x40); | |
| 12549 ins_encode( enc_cmov(cmp), RegMem( dst, src ) ); | |
| 12550 ins_pipe( pipe_cmov_mem ); | |
| 12551 %} | |
| 12552 | |
| 12553 // Compare 2 longs and CMOVE ints. | |
| 12554 instruct cmovPP_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegP dst, eRegP src) %{ | |
| 12555 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); | |
| 12556 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src))); | |
| 12557 ins_cost(200); | |
| 12558 format %{ "CMOV$cmp $dst,$src" %} | |
| 12559 opcode(0x0F,0x40); | |
| 12560 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); | |
| 12561 ins_pipe( pipe_cmov_reg ); | |
| 12562 %} | |
| 12563 | |
| 12564 // Compare 2 longs and CMOVE doubles | |
|
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12565 instruct cmovDDPR_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regDPR dst, regDPR src) %{ |
| 0 | 12566 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); |
| 12567 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); | |
| 12568 ins_cost(200); | |
| 12569 expand %{ | |
|
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12570 fcmovDPR_regS(cmp,flags,dst,src); |
| 0 | 12571 %} |
| 12572 %} | |
| 12573 | |
| 12574 // Compare 2 longs and CMOVE doubles | |
|
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12575 instruct cmovDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regD dst, regD src) %{ |
| 0 | 12576 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); |
| 12577 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); | |
| 12578 ins_cost(200); | |
| 12579 expand %{ | |
|
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12580 fcmovD_regS(cmp,flags,dst,src); |
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12581 %} |
|
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12582 %} |
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12583 |
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12584 instruct cmovFFPR_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regFPR dst, regFPR src) %{ |
|
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12585 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); |
|
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12586 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); |
|
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12587 ins_cost(200); |
|
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12588 expand %{ |
|
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12589 fcmovFPR_regS(cmp,flags,dst,src); |
| 0 | 12590 %} |
| 12591 %} | |
| 12592 | |
| 12593 instruct cmovFF_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regF dst, regF src) %{ | |
|
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12594 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); |
| 0 | 12595 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); |
| 12596 ins_cost(200); | |
| 12597 expand %{ | |
| 12598 fcmovF_regS(cmp,flags,dst,src); | |
| 12599 %} | |
| 12600 %} | |
| 12601 | |
| 12602 //====== | |
| 12603 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares. | |
| 12604 // Same as cmpL_reg_flags_LEGT except must negate src | |
|
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12605 instruct cmpL_zero_flags_LEGT( flagsReg_long_LEGT flags, eRegL src, immL0 zero, rRegI tmp ) %{ |
| 0 | 12606 match( Set flags (CmpL src zero )); |
| 12607 effect( TEMP tmp ); | |
| 12608 ins_cost(300); | |
| 12609 format %{ "XOR $tmp,$tmp\t# Long compare for -$src < 0, use commuted test\n\t" | |
| 12610 "CMP $tmp,$src.lo\n\t" | |
| 12611 "SBB $tmp,$src.hi\n\t" %} | |
| 12612 ins_encode( long_cmp_flags3(src, tmp) ); | |
| 12613 ins_pipe( ialu_reg_reg_long ); | |
| 12614 %} | |
| 12615 | |
| 12616 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares. | |
| 12617 // Same as cmpL_reg_flags_LTGE except operands swapped. Swapping operands | |
| 12618 // requires a commuted test to get the same result. | |
|
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12619 instruct cmpL_reg_flags_LEGT( flagsReg_long_LEGT flags, eRegL src1, eRegL src2, rRegI tmp ) %{ |
| 0 | 12620 match( Set flags (CmpL src1 src2 )); |
| 12621 effect( TEMP tmp ); | |
| 12622 ins_cost(300); | |
| 12623 format %{ "CMP $src2.lo,$src1.lo\t! Long compare, swapped operands, use with commuted test\n\t" | |
| 12624 "MOV $tmp,$src2.hi\n\t" | |
| 12625 "SBB $tmp,$src1.hi\t! Compute flags for long compare" %} | |
| 12626 ins_encode( long_cmp_flags2( src2, src1, tmp ) ); | |
| 12627 ins_pipe( ialu_cr_reg_reg ); | |
| 12628 %} | |
| 12629 | |
| 12630 // Long compares reg < zero/req OR reg >= zero/req. | |
| 12631 // Just a wrapper for a normal branch, plus the predicate test | |
| 12632 instruct cmpL_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, label labl) %{ | |
| 12633 match(If cmp flags); | |
| 12634 effect(USE labl); | |
| 12635 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le ); | |
| 12636 ins_cost(300); | |
| 12637 expand %{ | |
| 12638 jmpCon(cmp,flags,labl); // JGT or JLE... | |
| 12639 %} | |
| 12640 %} | |
| 12641 | |
| 12642 // Compare 2 longs and CMOVE longs. | |
| 12643 instruct cmovLL_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, eRegL src) %{ | |
| 12644 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src))); | |
| 12645 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); | |
| 12646 ins_cost(400); | |
| 12647 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" | |
| 12648 "CMOV$cmp $dst.hi,$src.hi" %} | |
| 12649 opcode(0x0F,0x40); | |
| 12650 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) ); | |
| 12651 ins_pipe( pipe_cmov_reg_long ); | |
| 12652 %} | |
| 12653 | |
| 12654 instruct cmovLL_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, load_long_memory src) %{ | |
| 12655 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src)))); | |
| 12656 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); | |
| 12657 ins_cost(500); | |
| 12658 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" | |
| 12659 "CMOV$cmp $dst.hi,$src.hi+4" %} | |
| 12660 opcode(0x0F,0x40); | |
| 12661 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) ); | |
| 12662 ins_pipe( pipe_cmov_reg_long ); | |
| 12663 %} | |
| 12664 | |
| 12665 // Compare 2 longs and CMOVE ints. | |
|
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12666 instruct cmovII_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, rRegI dst, rRegI src) %{ |
| 0 | 12667 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); |
| 12668 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src))); | |
| 12669 ins_cost(200); | |
| 12670 format %{ "CMOV$cmp $dst,$src" %} | |
| 12671 opcode(0x0F,0x40); | |
| 12672 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); | |
| 12673 ins_pipe( pipe_cmov_reg ); | |
| 12674 %} | |
| 12675 | |
|
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12676 instruct cmovII_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, rRegI dst, memory src) %{ |
| 0 | 12677 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); |
| 12678 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src)))); | |
| 12679 ins_cost(250); | |
| 12680 format %{ "CMOV$cmp $dst,$src" %} | |
| 12681 opcode(0x0F,0x40); | |
| 12682 ins_encode( enc_cmov(cmp), RegMem( dst, src ) ); | |
| 12683 ins_pipe( pipe_cmov_mem ); | |
| 12684 %} | |
| 12685 | |
| 12686 // Compare 2 longs and CMOVE ptrs. | |
| 12687 instruct cmovPP_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegP dst, eRegP src) %{ | |
| 12688 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); | |
| 12689 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src))); | |
| 12690 ins_cost(200); | |
| 12691 format %{ "CMOV$cmp $dst,$src" %} | |
| 12692 opcode(0x0F,0x40); | |
| 12693 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); | |
| 12694 ins_pipe( pipe_cmov_reg ); | |
| 12695 %} | |
| 12696 | |
| 12697 // Compare 2 longs and CMOVE doubles | |
|
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12698 instruct cmovDDPR_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regDPR dst, regDPR src) %{ |
| 0 | 12699 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ); |
| 12700 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); | |
| 12701 ins_cost(200); | |
| 12702 expand %{ | |
|
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|
12703 fcmovDPR_regS(cmp,flags,dst,src); |
| 0 | 12704 %} |
| 12705 %} | |
| 12706 | |
| 12707 // Compare 2 longs and CMOVE doubles | |
|
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12708 instruct cmovDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regD dst, regD src) %{ |
| 0 | 12709 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ); |
| 12710 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); | |
| 12711 ins_cost(200); | |
| 12712 expand %{ | |
|
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12713 fcmovD_regS(cmp,flags,dst,src); |
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12714 %} |
|
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12715 %} |
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|
12716 |
|
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12717 instruct cmovFFPR_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regFPR dst, regFPR src) %{ |
|
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12718 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ); |
|
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12719 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); |
|
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12720 ins_cost(200); |
|
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12721 expand %{ |
|
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12722 fcmovFPR_regS(cmp,flags,dst,src); |
|
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12723 %} |
|
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|
12724 %} |
|
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|
12725 |
| 0 | 12726 |
| 12727 instruct cmovFF_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regF dst, regF src) %{ | |
|
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12728 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ); |
| 0 | 12729 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); |
| 12730 ins_cost(200); | |
| 12731 expand %{ | |
| 12732 fcmovF_regS(cmp,flags,dst,src); | |
| 12733 %} | |
| 12734 %} | |
| 12735 | |
| 12736 | |
| 12737 // ============================================================================ | |
| 12738 // Procedure Call/Return Instructions | |
| 12739 // Call Java Static Instruction | |
| 12740 // Note: If this code changes, the corresponding ret_addr_offset() and | |
| 12741 // compute_padding() functions will have to be adjusted. | |
| 12742 instruct CallStaticJavaDirect(method meth) %{ | |
| 12743 match(CallStaticJava); | |
| 12744 effect(USE meth); | |
| 12745 | |
| 12746 ins_cost(300); | |
| 12747 format %{ "CALL,static " %} | |
| 12748 opcode(0xE8); /* E8 cd */ | |
|
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|
12749 ins_encode( pre_call_resets, |
| 0 | 12750 Java_Static_Call( meth ), |
| 12751 call_epilog, | |
| 12752 post_call_FPU ); | |
| 12753 ins_pipe( pipe_slow ); | |
| 12754 ins_alignment(4); | |
| 12755 %} | |
| 12756 | |
| 12757 // Call Java Dynamic Instruction | |
| 12758 // Note: If this code changes, the corresponding ret_addr_offset() and | |
| 12759 // compute_padding() functions will have to be adjusted. | |
| 12760 instruct CallDynamicJavaDirect(method meth) %{ | |
| 12761 match(CallDynamicJava); | |
| 12762 effect(USE meth); | |
| 12763 | |
| 12764 ins_cost(300); | |
| 12765 format %{ "MOV EAX,(oop)-1\n\t" | |
| 12766 "CALL,dynamic" %} | |
| 12767 opcode(0xE8); /* E8 cd */ | |
|
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|
12768 ins_encode( pre_call_resets, |
| 0 | 12769 Java_Dynamic_Call( meth ), |
| 12770 call_epilog, | |
| 12771 post_call_FPU ); | |
| 12772 ins_pipe( pipe_slow ); | |
| 12773 ins_alignment(4); | |
| 12774 %} | |
| 12775 | |
| 12776 // Call Runtime Instruction | |
| 12777 instruct CallRuntimeDirect(method meth) %{ | |
| 12778 match(CallRuntime ); | |
| 12779 effect(USE meth); | |
| 12780 | |
| 12781 ins_cost(300); | |
| 12782 format %{ "CALL,runtime " %} | |
| 12783 opcode(0xE8); /* E8 cd */ | |
| 12784 // Use FFREEs to clear entries in float stack | |
|
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12785 ins_encode( pre_call_resets, |
| 0 | 12786 FFree_Float_Stack_All, |
| 12787 Java_To_Runtime( meth ), | |
| 12788 post_call_FPU ); | |
| 12789 ins_pipe( pipe_slow ); | |
| 12790 %} | |
| 12791 | |
| 12792 // Call runtime without safepoint | |
| 12793 instruct CallLeafDirect(method meth) %{ | |
| 12794 match(CallLeaf); | |
| 12795 effect(USE meth); | |
| 12796 | |
| 12797 ins_cost(300); | |
| 12798 format %{ "CALL_LEAF,runtime " %} | |
| 12799 opcode(0xE8); /* E8 cd */ | |
|
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12800 ins_encode( pre_call_resets, |
| 0 | 12801 FFree_Float_Stack_All, |
| 12802 Java_To_Runtime( meth ), | |
| 12803 Verify_FPU_For_Leaf, post_call_FPU ); | |
| 12804 ins_pipe( pipe_slow ); | |
| 12805 %} | |
| 12806 | |
| 12807 instruct CallLeafNoFPDirect(method meth) %{ | |
| 12808 match(CallLeafNoFP); | |
| 12809 effect(USE meth); | |
| 12810 | |
| 12811 ins_cost(300); | |
| 12812 format %{ "CALL_LEAF_NOFP,runtime " %} | |
| 12813 opcode(0xE8); /* E8 cd */ | |
| 12814 ins_encode(Java_To_Runtime(meth)); | |
| 12815 ins_pipe( pipe_slow ); | |
| 12816 %} | |
| 12817 | |
| 12818 | |
| 12819 // Return Instruction | |
| 12820 // Remove the return address & jump to it. | |
| 12821 instruct Ret() %{ | |
| 12822 match(Return); | |
| 12823 format %{ "RET" %} | |
| 12824 opcode(0xC3); | |
| 12825 ins_encode(OpcP); | |
| 12826 ins_pipe( pipe_jmp ); | |
| 12827 %} | |
| 12828 | |
| 12829 // Tail Call; Jump from runtime stub to Java code. | |
| 12830 // Also known as an 'interprocedural jump'. | |
| 12831 // Target of jump will eventually return to caller. | |
| 12832 // TailJump below removes the return address. | |
| 12833 instruct TailCalljmpInd(eRegP_no_EBP jump_target, eBXRegP method_oop) %{ | |
| 12834 match(TailCall jump_target method_oop ); | |
| 12835 ins_cost(300); | |
| 12836 format %{ "JMP $jump_target \t# EBX holds method oop" %} | |
| 12837 opcode(0xFF, 0x4); /* Opcode FF /4 */ | |
| 12838 ins_encode( OpcP, RegOpc(jump_target) ); | |
| 12839 ins_pipe( pipe_jmp ); | |
| 12840 %} | |
| 12841 | |
| 12842 | |
| 12843 // Tail Jump; remove the return address; jump to target. | |
| 12844 // TailCall above leaves the return address around. | |
| 12845 instruct tailjmpInd(eRegP_no_EBP jump_target, eAXRegP ex_oop) %{ | |
| 12846 match( TailJump jump_target ex_oop ); | |
| 12847 ins_cost(300); | |
| 12848 format %{ "POP EDX\t# pop return address into dummy\n\t" | |
| 12849 "JMP $jump_target " %} | |
| 12850 opcode(0xFF, 0x4); /* Opcode FF /4 */ | |
| 12851 ins_encode( enc_pop_rdx, | |
| 12852 OpcP, RegOpc(jump_target) ); | |
| 12853 ins_pipe( pipe_jmp ); | |
| 12854 %} | |
| 12855 | |
| 12856 // Create exception oop: created by stack-crawling runtime code. | |
| 12857 // Created exception is now available to this handler, and is setup | |
| 12858 // just prior to jumping to this handler. No code emitted. | |
| 12859 instruct CreateException( eAXRegP ex_oop ) | |
| 12860 %{ | |
| 12861 match(Set ex_oop (CreateEx)); | |
| 12862 | |
| 12863 size(0); | |
| 12864 // use the following format syntax | |
| 12865 format %{ "# exception oop is in EAX; no code emitted" %} | |
| 12866 ins_encode(); | |
| 12867 ins_pipe( empty ); | |
| 12868 %} | |
| 12869 | |
| 12870 | |
| 12871 // Rethrow exception: | |
| 12872 // The exception oop will come in the first argument position. | |
| 12873 // Then JUMP (not call) to the rethrow stub code. | |
| 12874 instruct RethrowException() | |
| 12875 %{ | |
| 12876 match(Rethrow); | |
| 12877 | |
| 12878 // use the following format syntax | |
| 12879 format %{ "JMP rethrow_stub" %} | |
| 12880 ins_encode(enc_rethrow); | |
| 12881 ins_pipe( pipe_jmp ); | |
| 12882 %} | |
| 12883 | |
| 12884 // inlined locking and unlocking | |
| 12885 | |
| 17780 | 12886 instruct cmpFastLockRTM(eFlagsReg cr, eRegP object, eBXRegP box, eAXRegI tmp, eDXRegI scr, rRegI cx1, rRegI cx2) %{ |
| 12887 predicate(Compile::current()->use_rtm()); | |
| 12888 match(Set cr (FastLock object box)); | |
| 12889 effect(TEMP tmp, TEMP scr, TEMP cx1, TEMP cx2, USE_KILL box); | |
| 12890 ins_cost(300); | |
| 12891 format %{ "FASTLOCK $object,$box\t! kills $box,$tmp,$scr,$cx1,$cx2" %} | |
| 12892 ins_encode %{ | |
| 12893 __ fast_lock($object$$Register, $box$$Register, $tmp$$Register, | |
| 12894 $scr$$Register, $cx1$$Register, $cx2$$Register, | |
| 12895 _counters, _rtm_counters, _stack_rtm_counters, | |
| 12896 ((Method*)(ra_->C->method()->constant_encoding()))->method_data(), | |
| 12897 true, ra_->C->profile_rtm()); | |
| 12898 %} | |
| 12899 ins_pipe(pipe_slow); | |
| 12900 %} | |
| 12901 | |
|
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12902 instruct cmpFastLock(eFlagsReg cr, eRegP object, eBXRegP box, eAXRegI tmp, eRegP scr) %{ |
| 17780 | 12903 predicate(!Compile::current()->use_rtm()); |
|
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12904 match(Set cr (FastLock object box)); |
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12905 effect(TEMP tmp, TEMP scr, USE_KILL box); |
| 0 | 12906 ins_cost(300); |
| 4777 | 12907 format %{ "FASTLOCK $object,$box\t! kills $box,$tmp,$scr" %} |
|
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12908 ins_encode %{ |
| 17780 | 12909 __ fast_lock($object$$Register, $box$$Register, $tmp$$Register, |
| 12910 $scr$$Register, noreg, noreg, _counters, NULL, NULL, NULL, false, false); | |
|
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12911 %} |
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12912 ins_pipe(pipe_slow); |
|
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12913 %} |
|
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12914 |
|
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12915 instruct cmpFastUnlock(eFlagsReg cr, eRegP object, eAXRegP box, eRegP tmp ) %{ |
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12916 match(Set cr (FastUnlock object box)); |
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12917 effect(TEMP tmp, USE_KILL box); |
| 0 | 12918 ins_cost(300); |
| 4777 | 12919 format %{ "FASTUNLOCK $object,$box\t! kills $box,$tmp" %} |
|
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12920 ins_encode %{ |
| 17780 | 12921 __ fast_unlock($object$$Register, $box$$Register, $tmp$$Register, ra_->C->use_rtm()); |
|
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12922 %} |
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12923 ins_pipe(pipe_slow); |
| 0 | 12924 %} |
| 12925 | |
| 12926 | |
| 12927 | |
| 12928 // ============================================================================ | |
| 12929 // Safepoint Instruction | |
| 12930 instruct safePoint_poll(eFlagsReg cr) %{ | |
| 12931 match(SafePoint); | |
| 12932 effect(KILL cr); | |
| 12933 | |
| 12934 // TODO-FIXME: we currently poll at offset 0 of the safepoint polling page. | |
| 12935 // On SPARC that might be acceptable as we can generate the address with | |
| 12936 // just a sethi, saving an or. By polling at offset 0 we can end up | |
| 12937 // putting additional pressure on the index-0 in the D$. Because of | |
| 12938 // alignment (just like the situation at hand) the lower indices tend | |
| 12939 // to see more traffic. It'd be better to change the polling address | |
| 12940 // to offset 0 of the last $line in the polling page. | |
| 12941 | |
| 12942 format %{ "TSTL #polladdr,EAX\t! Safepoint: poll for GC" %} | |
| 12943 ins_cost(125); | |
| 12944 size(6) ; | |
| 12945 ins_encode( Safepoint_Poll() ); | |
| 12946 ins_pipe( ialu_reg_mem ); | |
| 12947 %} | |
| 12948 | |
| 4950 | 12949 |
| 12950 // ============================================================================ | |
| 12951 // This name is KNOWN by the ADLC and cannot be changed. | |
| 12952 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type | |
| 12953 // for this guy. | |
| 12954 instruct tlsLoadP(eRegP dst, eFlagsReg cr) %{ | |
| 12955 match(Set dst (ThreadLocal)); | |
| 12956 effect(DEF dst, KILL cr); | |
| 12957 | |
| 12958 format %{ "MOV $dst, Thread::current()" %} | |
| 12959 ins_encode %{ | |
| 12960 Register dstReg = as_Register($dst$$reg); | |
| 12961 __ get_thread(dstReg); | |
| 12962 %} | |
| 12963 ins_pipe( ialu_reg_fat ); | |
| 12964 %} | |
| 12965 | |
| 12966 | |
| 12967 | |
| 0 | 12968 //----------PEEPHOLE RULES----------------------------------------------------- |
| 12969 // These must follow all instruction definitions as they use the names | |
| 12970 // defined in the instructions definitions. | |
| 12971 // | |
| 605 | 12972 // peepmatch ( root_instr_name [preceding_instruction]* ); |
| 0 | 12973 // |
| 12974 // peepconstraint %{ | |
| 12975 // (instruction_number.operand_name relational_op instruction_number.operand_name | |
| 12976 // [, ...] ); | |
| 12977 // // instruction numbers are zero-based using left to right order in peepmatch | |
| 12978 // | |
| 12979 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) ); | |
| 12980 // // provide an instruction_number.operand_name for each operand that appears | |
| 12981 // // in the replacement instruction's match rule | |
| 12982 // | |
| 12983 // ---------VM FLAGS--------------------------------------------------------- | |
| 12984 // | |
| 12985 // All peephole optimizations can be turned off using -XX:-OptoPeephole | |
| 12986 // | |
| 12987 // Each peephole rule is given an identifying number starting with zero and | |
| 12988 // increasing by one in the order seen by the parser. An individual peephole | |
| 12989 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=# | |
| 12990 // on the command-line. | |
| 12991 // | |
| 12992 // ---------CURRENT LIMITATIONS---------------------------------------------- | |
| 12993 // | |
| 12994 // Only match adjacent instructions in same basic block | |
| 12995 // Only equality constraints | |
| 12996 // Only constraints between operands, not (0.dest_reg == EAX_enc) | |
| 12997 // Only one replacement instruction | |
| 12998 // | |
| 12999 // ---------EXAMPLE---------------------------------------------------------- | |
| 13000 // | |
| 13001 // // pertinent parts of existing instructions in architecture description | |
|
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13002 // instruct movI(rRegI dst, rRegI src) %{ |
| 0 | 13003 // match(Set dst (CopyI src)); |
| 13004 // %} | |
| 13005 // | |
|
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13006 // instruct incI_eReg(rRegI dst, immI1 src, eFlagsReg cr) %{ |
| 0 | 13007 // match(Set dst (AddI dst src)); |
| 13008 // effect(KILL cr); | |
| 13009 // %} | |
| 13010 // | |
| 13011 // // Change (inc mov) to lea | |
| 13012 // peephole %{ | |
| 13013 // // increment preceeded by register-register move | |
| 13014 // peepmatch ( incI_eReg movI ); | |
| 13015 // // require that the destination register of the increment | |
| 13016 // // match the destination register of the move | |
| 13017 // peepconstraint ( 0.dst == 1.dst ); | |
| 13018 // // construct a replacement instruction that sets | |
| 13019 // // the destination to ( move's source register + one ) | |
| 13020 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); | |
| 13021 // %} | |
| 13022 // | |
| 13023 // Implementation no longer uses movX instructions since | |
| 13024 // machine-independent system no longer uses CopyX nodes. | |
| 13025 // | |
| 13026 // peephole %{ | |
| 13027 // peepmatch ( incI_eReg movI ); | |
| 13028 // peepconstraint ( 0.dst == 1.dst ); | |
| 13029 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); | |
| 13030 // %} | |
| 13031 // | |
| 13032 // peephole %{ | |
| 13033 // peepmatch ( decI_eReg movI ); | |
| 13034 // peepconstraint ( 0.dst == 1.dst ); | |
| 13035 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); | |
| 13036 // %} | |
| 13037 // | |
| 13038 // peephole %{ | |
| 13039 // peepmatch ( addI_eReg_imm movI ); | |
| 13040 // peepconstraint ( 0.dst == 1.dst ); | |
| 13041 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); | |
| 13042 // %} | |
| 13043 // | |
| 13044 // peephole %{ | |
| 13045 // peepmatch ( addP_eReg_imm movP ); | |
| 13046 // peepconstraint ( 0.dst == 1.dst ); | |
| 13047 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) ); | |
| 13048 // %} | |
| 13049 | |
| 13050 // // Change load of spilled value to only a spill | |
|
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13051 // instruct storeI(memory mem, rRegI src) %{ |
| 0 | 13052 // match(Set mem (StoreI mem src)); |
| 13053 // %} | |
| 13054 // | |
|
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13055 // instruct loadI(rRegI dst, memory mem) %{ |
| 0 | 13056 // match(Set dst (LoadI mem)); |
| 13057 // %} | |
| 13058 // | |
| 13059 peephole %{ | |
| 13060 peepmatch ( loadI storeI ); | |
| 13061 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem ); | |
| 13062 peepreplace ( storeI( 1.mem 1.mem 1.src ) ); | |
| 13063 %} | |
| 13064 | |
| 13065 //----------SMARTSPILL RULES--------------------------------------------------- | |
| 13066 // These must follow all instruction definitions as they use the names | |
| 13067 // defined in the instructions definitions. |