Mercurial > hg > graal-jvmci-8
annotate src/cpu/x86/vm/x86_32.ad @ 23050:e8260b6328fb
8068945: Use RBP register as proper frame pointer in JIT compiled code on x86
Summary: Introduce the PreserveFramePointer flag to control if RBP is used as the frame pointer or as a general purpose register.
Reviewed-by: kvn, roland, dlong, enevill, shade
| author | zmajo |
|---|---|
| date | Fri, 29 May 2015 10:58:45 +0200 |
| parents | 0bf37f737702 |
| children | dd9cc155639c faef2a237329 |
| rev | line source |
|---|---|
| 0 | 1 // |
| 9154 | 2 // Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. |
| 0 | 3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 4 // | |
| 5 // This code is free software; you can redistribute it and/or modify it | |
| 6 // under the terms of the GNU General Public License version 2 only, as | |
| 7 // published by the Free Software Foundation. | |
| 8 // | |
| 9 // This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 // version 2 for more details (a copy is included in the LICENSE file that | |
| 13 // accompanied this code). | |
| 14 // | |
| 15 // You should have received a copy of the GNU General Public License version | |
| 16 // 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 // | |
|
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19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 // or visit www.oracle.com if you need additional information or have any |
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21 // questions. |
| 0 | 22 // |
| 23 // | |
| 24 | |
| 25 // X86 Architecture Description File | |
| 26 | |
| 27 //----------REGISTER DEFINITION BLOCK------------------------------------------ | |
| 28 // This information is used by the matcher and the register allocator to | |
| 29 // describe individual registers and classes of registers within the target | |
| 30 // archtecture. | |
| 31 | |
| 32 register %{ | |
| 33 //----------Architecture Description Register Definitions---------------------- | |
| 34 // General Registers | |
| 35 // "reg_def" name ( register save type, C convention save type, | |
| 36 // ideal register type, encoding ); | |
| 37 // Register Save Types: | |
| 38 // | |
| 39 // NS = No-Save: The register allocator assumes that these registers | |
| 40 // can be used without saving upon entry to the method, & | |
| 41 // that they do not need to be saved at call sites. | |
| 42 // | |
| 43 // SOC = Save-On-Call: The register allocator assumes that these registers | |
| 44 // can be used without saving upon entry to the method, | |
| 45 // but that they must be saved at call sites. | |
| 46 // | |
| 47 // SOE = Save-On-Entry: The register allocator assumes that these registers | |
| 48 // must be saved before using them upon entry to the | |
| 49 // method, but they do not need to be saved at call | |
| 50 // sites. | |
| 51 // | |
| 52 // AS = Always-Save: The register allocator assumes that these registers | |
| 53 // must be saved before using them upon entry to the | |
| 54 // method, & that they must be saved at call sites. | |
| 55 // | |
| 56 // Ideal Register Type is used to determine how to save & restore a | |
| 57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get | |
| 58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI. | |
| 59 // | |
| 60 // The encoding number is the actual bit-pattern placed into the opcodes. | |
| 61 | |
| 62 // General Registers | |
| 63 // Previously set EBX, ESI, and EDI as save-on-entry for java code | |
| 64 // Turn off SOE in java-code due to frequent use of uncommon-traps. | |
| 65 // Now that allocator is better, turn on ESI and EDI as SOE registers. | |
| 66 | |
| 67 reg_def EBX(SOC, SOE, Op_RegI, 3, rbx->as_VMReg()); | |
| 68 reg_def ECX(SOC, SOC, Op_RegI, 1, rcx->as_VMReg()); | |
| 69 reg_def ESI(SOC, SOE, Op_RegI, 6, rsi->as_VMReg()); | |
| 70 reg_def EDI(SOC, SOE, Op_RegI, 7, rdi->as_VMReg()); | |
| 71 // now that adapter frames are gone EBP is always saved and restored by the prolog/epilog code | |
| 72 reg_def EBP(NS, SOE, Op_RegI, 5, rbp->as_VMReg()); | |
| 73 reg_def EDX(SOC, SOC, Op_RegI, 2, rdx->as_VMReg()); | |
| 74 reg_def EAX(SOC, SOC, Op_RegI, 0, rax->as_VMReg()); | |
| 75 reg_def ESP( NS, NS, Op_RegI, 4, rsp->as_VMReg()); | |
| 76 | |
| 77 // Float registers. We treat TOS/FPR0 special. It is invisible to the | |
| 78 // allocator, and only shows up in the encodings. | |
| 79 reg_def FPR0L( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad()); | |
| 80 reg_def FPR0H( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad()); | |
| 81 // Ok so here's the trick FPR1 is really st(0) except in the midst | |
| 82 // of emission of assembly for a machnode. During the emission the fpu stack | |
| 83 // is pushed making FPR1 == st(1) temporarily. However at any safepoint | |
| 84 // the stack will not have this element so FPR1 == st(0) from the | |
| 85 // oopMap viewpoint. This same weirdness with numbering causes | |
| 86 // instruction encoding to have to play games with the register | |
| 87 // encode to correct for this 0/1 issue. See MachSpillCopyNode::implementation | |
| 88 // where it does flt->flt moves to see an example | |
| 89 // | |
| 90 reg_def FPR1L( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg()); | |
| 91 reg_def FPR1H( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg()->next()); | |
| 92 reg_def FPR2L( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg()); | |
| 93 reg_def FPR2H( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg()->next()); | |
| 94 reg_def FPR3L( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg()); | |
| 95 reg_def FPR3H( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg()->next()); | |
| 96 reg_def FPR4L( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg()); | |
| 97 reg_def FPR4H( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg()->next()); | |
| 98 reg_def FPR5L( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg()); | |
| 99 reg_def FPR5H( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg()->next()); | |
| 100 reg_def FPR6L( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()); | |
| 101 reg_def FPR6H( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()->next()); | |
| 102 reg_def FPR7L( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()); | |
| 103 reg_def FPR7H( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()->next()); | |
| 104 | |
| 105 // Specify priority of register selection within phases of register | |
| 106 // allocation. Highest priority is first. A useful heuristic is to | |
| 107 // give registers a low priority when they are required by machine | |
| 108 // instructions, like EAX and EDX. Registers which are used as | |
| 605 | 109 // pairs must fall on an even boundary (witness the FPR#L's in this list). |
| 0 | 110 // For the Intel integer registers, the equivalent Long pairs are |
| 111 // EDX:EAX, EBX:ECX, and EDI:EBP. | |
| 112 alloc_class chunk0( ECX, EBX, EBP, EDI, EAX, EDX, ESI, ESP, | |
| 113 FPR0L, FPR0H, FPR1L, FPR1H, FPR2L, FPR2H, | |
| 114 FPR3L, FPR3H, FPR4L, FPR4H, FPR5L, FPR5H, | |
| 115 FPR6L, FPR6H, FPR7L, FPR7H ); | |
| 116 | |
| 117 | |
| 118 //----------Architecture Description Register Classes-------------------------- | |
| 119 // Several register classes are automatically defined based upon information in | |
| 120 // this architecture description. | |
| 121 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ ) | |
| 122 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ ) | |
| 123 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ ) | |
| 124 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ ) | |
| 125 // | |
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126 // Class for no registers (empty set). |
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127 reg_class no_reg(); |
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128 |
| 0 | 129 // Class for all registers |
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130 reg_class any_reg_with_ebp(EAX, EDX, EBP, EDI, ESI, ECX, EBX, ESP); |
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131 // Class for all registers (excluding EBP) |
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132 reg_class any_reg_no_ebp(EAX, EDX, EDI, ESI, ECX, EBX, ESP); |
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133 // Dynamic register class that selects at runtime between register classes |
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134 // any_reg and any_no_ebp_reg (depending on the value of the flag PreserveFramePointer). |
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135 // Equivalent to: return PreserveFramePointer ? any_no_ebp_reg : any_reg; |
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136 reg_class_dynamic any_reg(any_reg_no_ebp, any_reg_with_ebp, %{ PreserveFramePointer %}); |
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137 |
| 0 | 138 // Class for general registers |
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139 reg_class int_reg_with_ebp(EAX, EDX, EBP, EDI, ESI, ECX, EBX); |
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140 // Class for general registers (excluding EBP). |
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141 // This register class can be used for implicit null checks on win95. |
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142 // It is also safe for use by tailjumps (we don't want to allocate in ebp). |
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143 // Used also if the PreserveFramePointer flag is true. |
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144 reg_class int_reg_no_ebp(EAX, EDX, EDI, ESI, ECX, EBX); |
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145 // Dynamic register class that selects between int_reg and int_reg_no_ebp. |
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146 reg_class_dynamic int_reg(int_reg_no_ebp, int_reg_with_ebp, %{ PreserveFramePointer %}); |
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147 |
| 0 | 148 // Class of "X" registers |
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149 reg_class int_x_reg(EBX, ECX, EDX, EAX); |
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150 |
| 0 | 151 // Class of registers that can appear in an address with no offset. |
| 152 // EBP and ESP require an extra instruction byte for zero offset. | |
| 153 // Used in fast-unlock | |
| 154 reg_class p_reg(EDX, EDI, ESI, EBX); | |
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155 |
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156 // Class for general registers excluding ECX |
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157 reg_class ncx_reg_with_ebp(EAX, EDX, EBP, EDI, ESI, EBX); |
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158 // Class for general registers excluding ECX (and EBP) |
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159 reg_class ncx_reg_no_ebp(EAX, EDX, EDI, ESI, EBX); |
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160 // Dynamic register class that selects between ncx_reg and ncx_reg_no_ebp. |
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161 reg_class_dynamic ncx_reg(ncx_reg_no_ebp, ncx_reg_with_ebp, %{ PreserveFramePointer %}); |
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162 |
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163 // Class for general registers excluding EAX |
| 0 | 164 reg_class nax_reg(EDX, EDI, ESI, ECX, EBX); |
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165 |
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166 // Class for general registers excluding EAX and EBX. |
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167 reg_class nabx_reg_with_ebp(EDX, EDI, ESI, ECX, EBP); |
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168 // Class for general registers excluding EAX and EBX (and EBP) |
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169 reg_class nabx_reg_no_ebp(EDX, EDI, ESI, ECX); |
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170 // Dynamic register class that selects between nabx_reg and nabx_reg_no_ebp. |
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171 reg_class_dynamic nabx_reg(nabx_reg_no_ebp, nabx_reg_with_ebp, %{ PreserveFramePointer %}); |
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172 |
| 0 | 173 // Class of EAX (for multiply and divide operations) |
| 174 reg_class eax_reg(EAX); | |
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175 |
| 0 | 176 // Class of EBX (for atomic add) |
| 177 reg_class ebx_reg(EBX); | |
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178 |
| 0 | 179 // Class of ECX (for shift and JCXZ operations and cmpLTMask) |
| 180 reg_class ecx_reg(ECX); | |
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181 |
| 0 | 182 // Class of EDX (for multiply and divide operations) |
| 183 reg_class edx_reg(EDX); | |
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184 |
| 0 | 185 // Class of EDI (for synchronization) |
| 186 reg_class edi_reg(EDI); | |
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187 |
| 0 | 188 // Class of ESI (for synchronization) |
| 189 reg_class esi_reg(ESI); | |
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190 |
| 0 | 191 // Singleton class for stack pointer |
| 192 reg_class sp_reg(ESP); | |
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193 |
| 0 | 194 // Singleton class for instruction pointer |
| 195 // reg_class ip_reg(EIP); | |
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196 |
| 0 | 197 // Class of integer register pairs |
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198 reg_class long_reg_with_ebp( EAX,EDX, ECX,EBX, EBP,EDI ); |
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199 // Class of integer register pairs (excluding EBP and EDI); |
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200 reg_class long_reg_no_ebp( EAX,EDX, ECX,EBX ); |
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201 // Dynamic register class that selects between long_reg and long_reg_no_ebp. |
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202 reg_class_dynamic long_reg(long_reg_no_ebp, long_reg_with_ebp, %{ PreserveFramePointer %}); |
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203 |
| 0 | 204 // Class of integer register pairs that aligns with calling convention |
| 205 reg_class eadx_reg( EAX,EDX ); | |
| 206 reg_class ebcx_reg( ECX,EBX ); | |
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207 |
| 0 | 208 // Not AX or DX, used in divides |
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209 reg_class nadx_reg_with_ebp(EBX, ECX, ESI, EDI, EBP); |
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210 // Not AX or DX (and neither EBP), used in divides |
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211 reg_class nadx_reg_no_ebp(EBX, ECX, ESI, EDI); |
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212 // Dynamic register class that selects between nadx_reg and nadx_reg_no_ebp. |
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213 reg_class_dynamic nadx_reg(nadx_reg_no_ebp, nadx_reg_with_ebp, %{ PreserveFramePointer %}); |
| 0 | 214 |
| 215 // Floating point registers. Notice FPR0 is not a choice. | |
| 216 // FPR0 is not ever allocated; we use clever encodings to fake | |
| 217 // a 2-address instructions out of Intels FP stack. | |
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218 reg_class fp_flt_reg( FPR1L,FPR2L,FPR3L,FPR4L,FPR5L,FPR6L,FPR7L ); |
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219 |
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220 reg_class fp_dbl_reg( FPR1L,FPR1H, FPR2L,FPR2H, FPR3L,FPR3H, |
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221 FPR4L,FPR4H, FPR5L,FPR5H, FPR6L,FPR6H, |
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222 FPR7L,FPR7H ); |
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223 |
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224 reg_class fp_flt_reg0( FPR1L ); |
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225 reg_class fp_dbl_reg0( FPR1L,FPR1H ); |
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226 reg_class fp_dbl_reg1( FPR2L,FPR2H ); |
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227 reg_class fp_dbl_notreg0( FPR2L,FPR2H, FPR3L,FPR3H, FPR4L,FPR4H, |
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228 FPR5L,FPR5H, FPR6L,FPR6H, FPR7L,FPR7H ); |
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229 |
| 0 | 230 %} |
| 231 | |
| 232 | |
| 233 //----------SOURCE BLOCK------------------------------------------------------- | |
| 234 // This is a block of C++ code which provides values, functions, and | |
| 235 // definitions necessary in the rest of the architecture description | |
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236 source_hpp %{ |
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237 // Must be visible to the DFA in dfa_x86_32.cpp |
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238 extern bool is_operand_hi32_zero(Node* n); |
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239 %} |
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240 |
| 0 | 241 source %{ |
| 304 | 242 #define RELOC_IMM32 Assembler::imm_operand |
| 0 | 243 #define RELOC_DISP32 Assembler::disp32_operand |
| 244 | |
| 245 #define __ _masm. | |
| 246 | |
| 247 // How to find the high register of a Long pair, given the low register | |
| 248 #define HIGH_FROM_LOW(x) ((x)+2) | |
| 249 | |
| 250 // These masks are used to provide 128-bit aligned bitmasks to the XMM | |
| 251 // instructions, to allow sign-masking or sign-bit flipping. They allow | |
| 252 // fast versions of NegF/NegD and AbsF/AbsD. | |
| 253 | |
| 254 // Note: 'double' and 'long long' have 32-bits alignment on x86. | |
| 255 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) { | |
| 256 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address | |
| 257 // of 128-bits operands for SSE instructions. | |
| 258 jlong *operand = (jlong*)(((uintptr_t)adr)&((uintptr_t)(~0xF))); | |
| 259 // Store the value to a 128-bits operand. | |
| 260 operand[0] = lo; | |
| 261 operand[1] = hi; | |
| 262 return operand; | |
| 263 } | |
| 264 | |
| 265 // Buffer for 128-bits masks used by SSE instructions. | |
| 266 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment) | |
| 267 | |
| 268 // Static initialization during VM startup. | |
| 269 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF)); | |
| 270 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF)); | |
| 271 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000)); | |
| 272 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000)); | |
| 273 | |
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274 // Offset hacking within calls. |
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275 static int pre_call_resets_size() { |
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276 int size = 0; |
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277 Compile* C = Compile::current(); |
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278 if (C->in_24_bit_fp_mode()) { |
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279 size += 6; // fldcw |
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280 } |
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281 if (C->max_vector_size() > 16) { |
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282 size += 3; // vzeroupper |
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283 } |
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284 return size; |
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285 } |
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286 |
| 0 | 287 // !!!!! Special hack to get all type of calls to specify the byte offset |
| 288 // from the start of the call to the point where the return address | |
| 289 // will point. | |
| 290 int MachCallStaticJavaNode::ret_addr_offset() { | |
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291 return 5 + pre_call_resets_size(); // 5 bytes from start of call to where return address points |
| 0 | 292 } |
| 293 | |
| 294 int MachCallDynamicJavaNode::ret_addr_offset() { | |
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295 return 10 + pre_call_resets_size(); // 10 bytes from start of call to where return address points |
| 0 | 296 } |
| 297 | |
| 298 static int sizeof_FFree_Float_Stack_All = -1; | |
| 299 | |
| 300 int MachCallRuntimeNode::ret_addr_offset() { | |
| 301 assert(sizeof_FFree_Float_Stack_All != -1, "must have been emitted already"); | |
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302 return sizeof_FFree_Float_Stack_All + 5 + pre_call_resets_size(); |
| 0 | 303 } |
| 304 | |
| 305 // Indicate if the safepoint node needs the polling page as an input. | |
| 306 // Since x86 does have absolute addressing, it doesn't. | |
| 307 bool SafePointNode::needs_polling_address_input() { | |
| 308 return false; | |
| 309 } | |
| 310 | |
| 311 // | |
| 312 // Compute padding required for nodes which need alignment | |
| 313 // | |
| 314 | |
| 315 // The address of the call instruction needs to be 4-byte aligned to | |
| 316 // ensure that it does not span a cache line so that it can be patched. | |
| 317 int CallStaticJavaDirectNode::compute_padding(int current_offset) const { | |
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318 current_offset += pre_call_resets_size(); // skip fldcw, if any |
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319 current_offset += 1; // skip call opcode byte |
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320 return round_to(current_offset, alignment_required()) - current_offset; |
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321 } |
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322 |
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323 // The address of the call instruction needs to be 4-byte aligned to |
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324 // ensure that it does not span a cache line so that it can be patched. |
| 0 | 325 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const { |
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326 current_offset += pre_call_resets_size(); // skip fldcw, if any |
| 0 | 327 current_offset += 5; // skip MOV instruction |
| 328 current_offset += 1; // skip call opcode byte | |
| 329 return round_to(current_offset, alignment_required()) - current_offset; | |
| 330 } | |
| 331 | |
| 332 // EMIT_RM() | |
| 333 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) { | |
| 334 unsigned char c = (unsigned char)((f1 << 6) | (f2 << 3) | f3); | |
| 1748 | 335 cbuf.insts()->emit_int8(c); |
| 0 | 336 } |
| 337 | |
| 338 // EMIT_CC() | |
| 339 void emit_cc(CodeBuffer &cbuf, int f1, int f2) { | |
| 340 unsigned char c = (unsigned char)( f1 | f2 ); | |
| 1748 | 341 cbuf.insts()->emit_int8(c); |
| 0 | 342 } |
| 343 | |
| 344 // EMIT_OPCODE() | |
| 345 void emit_opcode(CodeBuffer &cbuf, int code) { | |
| 1748 | 346 cbuf.insts()->emit_int8((unsigned char) code); |
| 0 | 347 } |
| 348 | |
| 349 // EMIT_OPCODE() w/ relocation information | |
| 350 void emit_opcode(CodeBuffer &cbuf, int code, relocInfo::relocType reloc, int offset = 0) { | |
| 1748 | 351 cbuf.relocate(cbuf.insts_mark() + offset, reloc); |
| 0 | 352 emit_opcode(cbuf, code); |
| 353 } | |
| 354 | |
| 355 // EMIT_D8() | |
| 356 void emit_d8(CodeBuffer &cbuf, int d8) { | |
| 1748 | 357 cbuf.insts()->emit_int8((unsigned char) d8); |
| 0 | 358 } |
| 359 | |
| 360 // EMIT_D16() | |
| 361 void emit_d16(CodeBuffer &cbuf, int d16) { | |
| 1748 | 362 cbuf.insts()->emit_int16(d16); |
| 0 | 363 } |
| 364 | |
| 365 // EMIT_D32() | |
| 366 void emit_d32(CodeBuffer &cbuf, int d32) { | |
| 1748 | 367 cbuf.insts()->emit_int32(d32); |
| 0 | 368 } |
| 369 | |
| 370 // emit 32 bit value and construct relocation entry from relocInfo::relocType | |
| 371 void emit_d32_reloc(CodeBuffer &cbuf, int d32, relocInfo::relocType reloc, | |
| 372 int format) { | |
| 1748 | 373 cbuf.relocate(cbuf.insts_mark(), reloc, format); |
| 374 cbuf.insts()->emit_int32(d32); | |
| 0 | 375 } |
| 376 | |
| 377 // emit 32 bit value and construct relocation entry from RelocationHolder | |
| 378 void emit_d32_reloc(CodeBuffer &cbuf, int d32, RelocationHolder const& rspec, | |
| 379 int format) { | |
| 380 #ifdef ASSERT | |
| 381 if (rspec.reloc()->type() == relocInfo::oop_type && d32 != 0 && d32 != (int)Universe::non_oop_word()) { | |
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382 assert(cast_to_oop(d32)->is_oop() && (ScavengeRootsInCode || !cast_to_oop(d32)->is_scavengable()), "cannot embed scavengable oops in code"); |
| 0 | 383 } |
| 384 #endif | |
| 1748 | 385 cbuf.relocate(cbuf.insts_mark(), rspec, format); |
| 386 cbuf.insts()->emit_int32(d32); | |
| 0 | 387 } |
| 388 | |
| 389 // Access stack slot for load or store | |
| 390 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp) { | |
| 391 emit_opcode( cbuf, opcode ); // (e.g., FILD [ESP+src]) | |
| 392 if( -128 <= disp && disp <= 127 ) { | |
| 393 emit_rm( cbuf, 0x01, rm_field, ESP_enc ); // R/M byte | |
| 394 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte | |
| 395 emit_d8 (cbuf, disp); // Displacement // R/M byte | |
| 396 } else { | |
| 397 emit_rm( cbuf, 0x02, rm_field, ESP_enc ); // R/M byte | |
| 398 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte | |
| 399 emit_d32(cbuf, disp); // Displacement // R/M byte | |
| 400 } | |
| 401 } | |
| 402 | |
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403 // rRegI ereg, memory mem) %{ // emit_reg_mem |
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404 void encode_RegMem( CodeBuffer &cbuf, int reg_encoding, int base, int index, int scale, int displace, relocInfo::relocType disp_reloc ) { |
| 0 | 405 // There is no index & no scale, use form without SIB byte |
| 406 if ((index == 0x4) && | |
| 407 (scale == 0) && (base != ESP_enc)) { | |
| 408 // If no displacement, mode is 0x0; unless base is [EBP] | |
| 409 if ( (displace == 0) && (base != EBP_enc) ) { | |
| 410 emit_rm(cbuf, 0x0, reg_encoding, base); | |
| 411 } | |
| 412 else { // If 8-bit displacement, mode 0x1 | |
| 413 if ((displace >= -128) && (displace <= 127) | |
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414 && (disp_reloc == relocInfo::none) ) { |
| 0 | 415 emit_rm(cbuf, 0x1, reg_encoding, base); |
| 416 emit_d8(cbuf, displace); | |
| 417 } | |
| 418 else { // If 32-bit displacement | |
| 419 if (base == -1) { // Special flag for absolute address | |
| 420 emit_rm(cbuf, 0x0, reg_encoding, 0x5); | |
| 421 // (manual lies; no SIB needed here) | |
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422 if ( disp_reloc != relocInfo::none ) { |
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423 emit_d32_reloc(cbuf, displace, disp_reloc, 1); |
| 0 | 424 } else { |
| 425 emit_d32 (cbuf, displace); | |
| 426 } | |
| 427 } | |
| 428 else { // Normal base + offset | |
| 429 emit_rm(cbuf, 0x2, reg_encoding, base); | |
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430 if ( disp_reloc != relocInfo::none ) { |
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431 emit_d32_reloc(cbuf, displace, disp_reloc, 1); |
| 0 | 432 } else { |
| 433 emit_d32 (cbuf, displace); | |
| 434 } | |
| 435 } | |
| 436 } | |
| 437 } | |
| 438 } | |
| 439 else { // Else, encode with the SIB byte | |
| 440 // If no displacement, mode is 0x0; unless base is [EBP] | |
| 441 if (displace == 0 && (base != EBP_enc)) { // If no displacement | |
| 442 emit_rm(cbuf, 0x0, reg_encoding, 0x4); | |
| 443 emit_rm(cbuf, scale, index, base); | |
| 444 } | |
| 445 else { // If 8-bit displacement, mode 0x1 | |
| 446 if ((displace >= -128) && (displace <= 127) | |
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447 && (disp_reloc == relocInfo::none) ) { |
| 0 | 448 emit_rm(cbuf, 0x1, reg_encoding, 0x4); |
| 449 emit_rm(cbuf, scale, index, base); | |
| 450 emit_d8(cbuf, displace); | |
| 451 } | |
| 452 else { // If 32-bit displacement | |
| 453 if (base == 0x04 ) { | |
| 454 emit_rm(cbuf, 0x2, reg_encoding, 0x4); | |
| 455 emit_rm(cbuf, scale, index, 0x04); | |
| 456 } else { | |
| 457 emit_rm(cbuf, 0x2, reg_encoding, 0x4); | |
| 458 emit_rm(cbuf, scale, index, base); | |
| 459 } | |
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460 if ( disp_reloc != relocInfo::none ) { |
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461 emit_d32_reloc(cbuf, displace, disp_reloc, 1); |
| 0 | 462 } else { |
| 463 emit_d32 (cbuf, displace); | |
| 464 } | |
| 465 } | |
| 466 } | |
| 467 } | |
| 468 } | |
| 469 | |
| 470 | |
| 471 void encode_Copy( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) { | |
| 472 if( dst_encoding == src_encoding ) { | |
| 473 // reg-reg copy, use an empty encoding | |
| 474 } else { | |
| 475 emit_opcode( cbuf, 0x8B ); | |
| 476 emit_rm(cbuf, 0x3, dst_encoding, src_encoding ); | |
| 477 } | |
| 478 } | |
| 479 | |
| 4759 | 480 void emit_cmpfp_fixup(MacroAssembler& _masm) { |
| 481 Label exit; | |
| 482 __ jccb(Assembler::noParity, exit); | |
| 483 __ pushf(); | |
| 484 // | |
| 485 // comiss/ucomiss instructions set ZF,PF,CF flags and | |
| 486 // zero OF,AF,SF for NaN values. | |
| 487 // Fixup flags by zeroing ZF,PF so that compare of NaN | |
| 488 // values returns 'less than' result (CF is set). | |
| 489 // Leave the rest of flags unchanged. | |
| 490 // | |
| 491 // 7 6 5 4 3 2 1 0 | |
| 492 // |S|Z|r|A|r|P|r|C| (r - reserved bit) | |
| 493 // 0 0 1 0 1 0 1 1 (0x2B) | |
| 494 // | |
| 495 __ andl(Address(rsp, 0), 0xffffff2b); | |
| 496 __ popf(); | |
| 497 __ bind(exit); | |
| 498 } | |
| 499 | |
| 500 void emit_cmpfp3(MacroAssembler& _masm, Register dst) { | |
| 501 Label done; | |
| 502 __ movl(dst, -1); | |
| 503 __ jcc(Assembler::parity, done); | |
| 504 __ jcc(Assembler::below, done); | |
| 505 __ setb(Assembler::notEqual, dst); | |
| 506 __ movzbl(dst, dst); | |
| 507 __ bind(done); | |
| 0 | 508 } |
| 509 | |
| 510 | |
| 511 //============================================================================= | |
| 2008 | 512 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty; |
| 513 | |
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514 int Compile::ConstantTable::calculate_table_base_offset() const { |
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515 return 0; // absolute addressing, no offset |
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516 } |
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517 |
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518 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; } |
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519 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) { |
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520 ShouldNotReachHere(); |
|
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521 } |
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522 |
| 2008 | 523 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const { |
| 524 // Empty encoding | |
| 525 } | |
| 526 | |
| 527 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const { | |
| 528 return 0; | |
| 529 } | |
| 530 | |
| 531 #ifndef PRODUCT | |
| 532 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const { | |
| 533 st->print("# MachConstantBaseNode (empty encoding)"); | |
| 534 } | |
| 535 #endif | |
| 536 | |
| 537 | |
| 538 //============================================================================= | |
| 0 | 539 #ifndef PRODUCT |
|
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540 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const { |
| 0 | 541 Compile* C = ra_->C; |
| 542 | |
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543 int framesize = C->frame_size_in_bytes(); |
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544 int bangsize = C->bang_size_in_bytes(); |
| 0 | 545 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); |
|
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546 // Remove wordSize for return addr which is already pushed. |
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547 framesize -= wordSize; |
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548 |
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549 if (C->need_stack_bang(bangsize)) { |
| 0 | 550 framesize -= wordSize; |
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551 st->print("# stack bang (%d bytes)", bangsize); |
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552 st->print("\n\t"); |
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553 st->print("PUSH EBP\t# Save EBP"); |
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554 if (PreserveFramePointer) { |
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555 st->print("\n\t"); |
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556 st->print("MOV EBP, ESP\t# Save the caller's SP into EBP"); |
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557 } |
| 0 | 558 if (framesize) { |
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559 st->print("\n\t"); |
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560 st->print("SUB ESP, #%d\t# Create frame",framesize); |
| 0 | 561 } |
| 562 } else { | |
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563 st->print("SUB ESP, #%d\t# Create frame",framesize); |
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564 st->print("\n\t"); |
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565 framesize -= wordSize; |
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566 st->print("MOV [ESP + #%d], EBP\t# Save EBP",framesize); |
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567 if (PreserveFramePointer) { |
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568 st->print("\n\t"); |
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569 st->print("MOV EBP, [ESP + #%d]\t# Save the caller's SP into EBP", (framesize + wordSize)); |
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570 } |
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571 } |
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572 |
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573 if (VerifyStackAtCalls) { |
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574 st->print("\n\t"); |
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575 framesize -= wordSize; |
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576 st->print("MOV [ESP + #%d], 0xBADB100D\t# Majik cookie for stack depth check",framesize); |
| 0 | 577 } |
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578 |
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579 if( C->in_24_bit_fp_mode() ) { |
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580 st->print("\n\t"); |
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581 st->print("FLDCW \t# load 24 bit fpu control word"); |
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582 } |
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583 if (UseSSE >= 2 && VerifyFPU) { |
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584 st->print("\n\t"); |
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585 st->print("# verify FPU stack (must be clean on entry)"); |
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586 } |
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587 |
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588 #ifdef ASSERT |
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589 if (VerifyStackAtCalls) { |
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590 st->print("\n\t"); |
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591 st->print("# stack alignment check"); |
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592 } |
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593 #endif |
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594 st->cr(); |
| 0 | 595 } |
| 596 #endif | |
| 597 | |
| 598 | |
| 599 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 600 Compile* C = ra_->C; | |
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601 MacroAssembler _masm(&cbuf); |
| 0 | 602 |
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603 int framesize = C->frame_size_in_bytes(); |
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604 int bangsize = C->bang_size_in_bytes(); |
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605 |
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606 __ verified_entry(framesize, C->need_stack_bang(bangsize)?bangsize:0, C->in_24_bit_fp_mode()); |
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607 |
| 1748 | 608 C->set_frame_complete(cbuf.insts_size()); |
| 0 | 609 |
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610 if (C->has_mach_constant_base_node()) { |
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611 // NOTE: We set the table base offset here because users might be |
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612 // emitted before MachConstantBaseNode. |
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613 Compile::ConstantTable& constant_table = C->constant_table(); |
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614 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset()); |
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615 } |
| 0 | 616 } |
| 617 | |
| 618 uint MachPrologNode::size(PhaseRegAlloc *ra_) const { | |
| 619 return MachNode::size(ra_); // too many variables; just compute it the hard way | |
| 620 } | |
| 621 | |
| 622 int MachPrologNode::reloc() const { | |
| 623 return 0; // a large enough number | |
| 624 } | |
| 625 | |
| 626 //============================================================================= | |
| 627 #ifndef PRODUCT | |
| 628 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream* st ) const { | |
| 629 Compile *C = ra_->C; | |
|
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630 int framesize = C->frame_size_in_bytes(); |
| 0 | 631 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); |
| 632 // Remove two words for return addr and rbp, | |
| 633 framesize -= 2*wordSize; | |
| 634 | |
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635 if (C->max_vector_size() > 16) { |
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636 st->print("VZEROUPPER"); |
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637 st->cr(); st->print("\t"); |
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638 } |
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639 if (C->in_24_bit_fp_mode()) { |
| 0 | 640 st->print("FLDCW standard control word"); |
| 641 st->cr(); st->print("\t"); | |
| 642 } | |
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643 if (framesize) { |
| 0 | 644 st->print("ADD ESP,%d\t# Destroy frame",framesize); |
| 645 st->cr(); st->print("\t"); | |
| 646 } | |
| 647 st->print_cr("POPL EBP"); st->print("\t"); | |
|
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648 if (do_polling() && C->is_method_compilation()) { |
| 0 | 649 st->print("TEST PollPage,EAX\t! Poll Safepoint"); |
| 650 st->cr(); st->print("\t"); | |
| 651 } | |
| 652 } | |
| 653 #endif | |
| 654 | |
| 655 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 656 Compile *C = ra_->C; | |
| 657 | |
|
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658 if (C->max_vector_size() > 16) { |
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659 // Clear upper bits of YMM registers when current compiled code uses |
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660 // wide vectors to avoid AVX <-> SSE transition penalty during call. |
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661 MacroAssembler masm(&cbuf); |
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662 masm.vzeroupper(); |
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663 } |
| 0 | 664 // If method set FPU control word, restore to standard control word |
|
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665 if (C->in_24_bit_fp_mode()) { |
| 0 | 666 MacroAssembler masm(&cbuf); |
| 667 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); | |
| 668 } | |
| 669 | |
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670 int framesize = C->frame_size_in_bytes(); |
| 0 | 671 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); |
| 672 // Remove two words for return addr and rbp, | |
| 673 framesize -= 2*wordSize; | |
| 674 | |
| 675 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here | |
| 676 | |
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677 if (framesize >= 128) { |
| 0 | 678 emit_opcode(cbuf, 0x81); // add SP, #framesize |
| 679 emit_rm(cbuf, 0x3, 0x00, ESP_enc); | |
| 680 emit_d32(cbuf, framesize); | |
|
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681 } else if (framesize) { |
| 0 | 682 emit_opcode(cbuf, 0x83); // add SP, #framesize |
| 683 emit_rm(cbuf, 0x3, 0x00, ESP_enc); | |
| 684 emit_d8(cbuf, framesize); | |
| 685 } | |
| 686 | |
| 687 emit_opcode(cbuf, 0x58 | EBP_enc); | |
| 688 | |
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689 if (do_polling() && C->is_method_compilation()) { |
| 1748 | 690 cbuf.relocate(cbuf.insts_end(), relocInfo::poll_return_type, 0); |
| 0 | 691 emit_opcode(cbuf,0x85); |
| 692 emit_rm(cbuf, 0x0, EAX_enc, 0x5); // EAX | |
| 693 emit_d32(cbuf, (intptr_t)os::get_polling_page()); | |
| 694 } | |
| 695 } | |
| 696 | |
| 697 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const { | |
| 698 Compile *C = ra_->C; | |
| 699 // If method set FPU control word, restore to standard control word | |
| 700 int size = C->in_24_bit_fp_mode() ? 6 : 0; | |
|
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701 if (C->max_vector_size() > 16) size += 3; // vzeroupper |
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702 if (do_polling() && C->is_method_compilation()) size += 6; |
| 0 | 703 |
|
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704 int framesize = C->frame_size_in_bytes(); |
| 0 | 705 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); |
| 706 // Remove two words for return addr and rbp, | |
| 707 framesize -= 2*wordSize; | |
| 708 | |
| 709 size++; // popl rbp, | |
| 710 | |
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711 if (framesize >= 128) { |
| 0 | 712 size += 6; |
| 713 } else { | |
| 714 size += framesize ? 3 : 0; | |
| 715 } | |
| 716 return size; | |
| 717 } | |
| 718 | |
| 719 int MachEpilogNode::reloc() const { | |
| 720 return 0; // a large enough number | |
| 721 } | |
| 722 | |
| 723 const Pipeline * MachEpilogNode::pipeline() const { | |
| 724 return MachNode::pipeline_class(); | |
| 725 } | |
| 726 | |
| 727 int MachEpilogNode::safepoint_offset() const { return 0; } | |
| 728 | |
| 729 //============================================================================= | |
| 730 | |
| 731 enum RC { rc_bad, rc_int, rc_float, rc_xmm, rc_stack }; | |
| 732 static enum RC rc_class( OptoReg::Name reg ) { | |
| 733 | |
| 734 if( !OptoReg::is_valid(reg) ) return rc_bad; | |
| 735 if (OptoReg::is_stack(reg)) return rc_stack; | |
| 736 | |
| 737 VMReg r = OptoReg::as_VMReg(reg); | |
| 738 if (r->is_Register()) return rc_int; | |
| 739 if (r->is_FloatRegister()) { | |
| 740 assert(UseSSE < 2, "shouldn't be used in SSE2+ mode"); | |
| 741 return rc_float; | |
| 742 } | |
| 743 assert(r->is_XMMRegister(), "must be"); | |
| 744 return rc_xmm; | |
| 745 } | |
| 746 | |
|
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747 static int impl_helper( CodeBuffer *cbuf, bool do_size, bool is_load, int offset, int reg, |
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748 int opcode, const char *op_str, int size, outputStream* st ) { |
| 0 | 749 if( cbuf ) { |
| 750 emit_opcode (*cbuf, opcode ); | |
|
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751 encode_RegMem(*cbuf, Matcher::_regEncode[reg], ESP_enc, 0x4, 0, offset, relocInfo::none); |
| 0 | 752 #ifndef PRODUCT |
| 753 } else if( !do_size ) { | |
|
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754 if( size != 0 ) st->print("\n\t"); |
| 0 | 755 if( opcode == 0x8B || opcode == 0x89 ) { // MOV |
|
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756 if( is_load ) st->print("%s %s,[ESP + #%d]",op_str,Matcher::regName[reg],offset); |
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757 else st->print("%s [ESP + #%d],%s",op_str,offset,Matcher::regName[reg]); |
| 0 | 758 } else { // FLD, FST, PUSH, POP |
|
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759 st->print("%s [ESP + #%d]",op_str,offset); |
| 0 | 760 } |
| 761 #endif | |
| 762 } | |
| 763 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4); | |
| 764 return size+3+offset_size; | |
| 765 } | |
| 766 | |
| 767 // Helper for XMM registers. Extra opcode bits, limited syntax. | |
| 768 static int impl_x_helper( CodeBuffer *cbuf, bool do_size, bool is_load, | |
|
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769 int offset, int reg_lo, int reg_hi, int size, outputStream* st ) { |
| 4759 | 770 if (cbuf) { |
| 771 MacroAssembler _masm(cbuf); | |
| 772 if (reg_lo+1 == reg_hi) { // double move? | |
| 773 if (is_load) { | |
| 774 __ movdbl(as_XMMRegister(Matcher::_regEncode[reg_lo]), Address(rsp, offset)); | |
| 775 } else { | |
| 776 __ movdbl(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[reg_lo])); | |
| 777 } | |
| 0 | 778 } else { |
| 4759 | 779 if (is_load) { |
| 780 __ movflt(as_XMMRegister(Matcher::_regEncode[reg_lo]), Address(rsp, offset)); | |
| 781 } else { | |
| 782 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[reg_lo])); | |
| 783 } | |
| 0 | 784 } |
| 785 #ifndef PRODUCT | |
| 4759 | 786 } else if (!do_size) { |
| 787 if (size != 0) st->print("\n\t"); | |
| 788 if (reg_lo+1 == reg_hi) { // double move? | |
| 789 if (is_load) st->print("%s %s,[ESP + #%d]", | |
| 790 UseXmmLoadAndClearUpper ? "MOVSD " : "MOVLPD", | |
| 791 Matcher::regName[reg_lo], offset); | |
| 792 else st->print("MOVSD [ESP + #%d],%s", | |
| 793 offset, Matcher::regName[reg_lo]); | |
| 0 | 794 } else { |
| 4759 | 795 if (is_load) st->print("MOVSS %s,[ESP + #%d]", |
| 796 Matcher::regName[reg_lo], offset); | |
| 797 else st->print("MOVSS [ESP + #%d],%s", | |
| 798 offset, Matcher::regName[reg_lo]); | |
| 0 | 799 } |
| 800 #endif | |
| 801 } | |
| 802 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4); | |
|
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803 // VEX_2bytes prefix is used if UseAVX > 0, so it takes the same 2 bytes as SIMD prefix. |
| 0 | 804 return size+5+offset_size; |
| 805 } | |
| 806 | |
| 807 | |
| 808 static int impl_movx_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo, | |
|
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809 int src_hi, int dst_hi, int size, outputStream* st ) { |
| 4759 | 810 if (cbuf) { |
| 811 MacroAssembler _masm(cbuf); | |
| 812 if (src_lo+1 == src_hi && dst_lo+1 == dst_hi) { // double move? | |
| 813 __ movdbl(as_XMMRegister(Matcher::_regEncode[dst_lo]), | |
| 814 as_XMMRegister(Matcher::_regEncode[src_lo])); | |
| 815 } else { | |
| 816 __ movflt(as_XMMRegister(Matcher::_regEncode[dst_lo]), | |
| 817 as_XMMRegister(Matcher::_regEncode[src_lo])); | |
| 818 } | |
| 0 | 819 #ifndef PRODUCT |
| 4759 | 820 } else if (!do_size) { |
| 821 if (size != 0) st->print("\n\t"); | |
| 822 if (UseXmmRegToRegMoveAll) {//Use movaps,movapd to move between xmm registers | |
| 823 if (src_lo+1 == src_hi && dst_lo+1 == dst_hi) { // double move? | |
|
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824 st->print("MOVAPD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]); |
| 0 | 825 } else { |
|
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826 st->print("MOVAPS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]); |
| 0 | 827 } |
| 4759 | 828 } else { |
| 0 | 829 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move? |
|
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830 st->print("MOVSD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]); |
| 0 | 831 } else { |
|
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832 st->print("MOVSS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]); |
| 0 | 833 } |
| 4759 | 834 } |
| 0 | 835 #endif |
| 836 } | |
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837 // VEX_2bytes prefix is used if UseAVX > 0, and it takes the same 2 bytes as SIMD prefix. |
| 4759 | 838 // Only MOVAPS SSE prefix uses 1 byte. |
| 839 int sz = 4; | |
| 840 if (!(src_lo+1 == src_hi && dst_lo+1 == dst_hi) && | |
| 841 UseXmmRegToRegMoveAll && (UseAVX == 0)) sz = 3; | |
| 842 return size + sz; | |
| 0 | 843 } |
| 844 | |
|
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845 static int impl_movgpr2x_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo, |
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846 int src_hi, int dst_hi, int size, outputStream* st ) { |
|
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847 // 32-bit |
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848 if (cbuf) { |
| 4759 | 849 MacroAssembler _masm(cbuf); |
| 850 __ movdl(as_XMMRegister(Matcher::_regEncode[dst_lo]), | |
| 851 as_Register(Matcher::_regEncode[src_lo])); | |
|
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852 #ifndef PRODUCT |
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853 } else if (!do_size) { |
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854 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]); |
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855 #endif |
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856 } |
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857 return 4; |
|
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858 } |
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|
859 |
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|
860 |
|
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861 static int impl_movx2gpr_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo, |
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862 int src_hi, int dst_hi, int size, outputStream* st ) { |
|
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863 // 32-bit |
|
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|
864 if (cbuf) { |
| 4759 | 865 MacroAssembler _masm(cbuf); |
| 866 __ movdl(as_Register(Matcher::_regEncode[dst_lo]), | |
| 867 as_XMMRegister(Matcher::_regEncode[src_lo])); | |
|
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868 #ifndef PRODUCT |
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|
869 } else if (!do_size) { |
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870 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]); |
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871 #endif |
|
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|
872 } |
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|
873 return 4; |
|
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|
874 } |
|
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|
875 |
|
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876 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int size, outputStream* st ) { |
| 0 | 877 if( cbuf ) { |
| 878 emit_opcode(*cbuf, 0x8B ); | |
| 879 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst], Matcher::_regEncode[src] ); | |
| 880 #ifndef PRODUCT | |
| 881 } else if( !do_size ) { | |
|
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882 if( size != 0 ) st->print("\n\t"); |
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883 st->print("MOV %s,%s",Matcher::regName[dst],Matcher::regName[src]); |
| 0 | 884 #endif |
| 885 } | |
| 886 return size+2; | |
| 887 } | |
| 888 | |
|
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889 static int impl_fp_store_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int src_hi, int dst_lo, int dst_hi, |
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890 int offset, int size, outputStream* st ) { |
| 0 | 891 if( src_lo != FPR1L_num ) { // Move value to top of FP stack, if not already there |
| 892 if( cbuf ) { | |
| 893 emit_opcode( *cbuf, 0xD9 ); // FLD (i.e., push it) | |
| 894 emit_d8( *cbuf, 0xC0-1+Matcher::_regEncode[src_lo] ); | |
| 895 #ifndef PRODUCT | |
| 896 } else if( !do_size ) { | |
|
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897 if( size != 0 ) st->print("\n\t"); |
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898 st->print("FLD %s",Matcher::regName[src_lo]); |
| 0 | 899 #endif |
| 900 } | |
| 901 size += 2; | |
| 902 } | |
| 903 | |
| 904 int st_op = (src_lo != FPR1L_num) ? EBX_num /*store & pop*/ : EDX_num /*store no pop*/; | |
| 905 const char *op_str; | |
| 906 int op; | |
| 907 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double store? | |
| 908 op_str = (src_lo != FPR1L_num) ? "FSTP_D" : "FST_D "; | |
| 909 op = 0xDD; | |
| 910 } else { // 32-bit store | |
| 911 op_str = (src_lo != FPR1L_num) ? "FSTP_S" : "FST_S "; | |
| 912 op = 0xD9; | |
| 913 assert( !OptoReg::is_valid(src_hi) && !OptoReg::is_valid(dst_hi), "no non-adjacent float-stores" ); | |
| 914 } | |
| 915 | |
|
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916 return impl_helper(cbuf,do_size,false,offset,st_op,op,op_str,size, st); |
| 0 | 917 } |
| 918 | |
|
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919 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad. |
|
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920 static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo, |
|
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921 int src_hi, int dst_hi, uint ireg, outputStream* st); |
|
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|
922 |
|
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923 static int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load, |
|
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924 int stack_offset, int reg, uint ireg, outputStream* st); |
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925 |
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926 static int vec_stack_to_stack_helper(CodeBuffer *cbuf, bool do_size, int src_offset, |
|
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927 int dst_offset, uint ireg, outputStream* st) { |
|
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928 int calc_size = 0; |
|
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929 int src_offset_size = (src_offset == 0) ? 0 : ((src_offset < 0x80) ? 1 : 4); |
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930 int dst_offset_size = (dst_offset == 0) ? 0 : ((dst_offset < 0x80) ? 1 : 4); |
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931 switch (ireg) { |
|
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932 case Op_VecS: |
|
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933 calc_size = 3+src_offset_size + 3+dst_offset_size; |
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|
934 break; |
|
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935 case Op_VecD: |
|
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936 calc_size = 3+src_offset_size + 3+dst_offset_size; |
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937 src_offset += 4; |
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938 dst_offset += 4; |
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939 src_offset_size = (src_offset == 0) ? 0 : ((src_offset < 0x80) ? 1 : 4); |
|
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940 dst_offset_size = (dst_offset == 0) ? 0 : ((dst_offset < 0x80) ? 1 : 4); |
|
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941 calc_size += 3+src_offset_size + 3+dst_offset_size; |
|
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942 break; |
|
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|
943 case Op_VecX: |
|
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944 calc_size = 6 + 6 + 5+src_offset_size + 5+dst_offset_size; |
|
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|
945 break; |
|
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946 case Op_VecY: |
|
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|
947 calc_size = 6 + 6 + 5+src_offset_size + 5+dst_offset_size; |
|
8c92982cbbc4
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changeset
|
948 break; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
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parents:
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diff
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|
949 default: |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
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|
950 ShouldNotReachHere(); |
|
8c92982cbbc4
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|
951 } |
|
8c92982cbbc4
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|
952 if (cbuf) { |
|
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|
953 MacroAssembler _masm(cbuf); |
|
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|
954 int offset = __ offset(); |
|
8c92982cbbc4
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|
955 switch (ireg) { |
|
8c92982cbbc4
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|
956 case Op_VecS: |
|
8c92982cbbc4
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|
957 __ pushl(Address(rsp, src_offset)); |
|
8c92982cbbc4
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|
958 __ popl (Address(rsp, dst_offset)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
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|
959 break; |
|
8c92982cbbc4
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|
960 case Op_VecD: |
|
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|
961 __ pushl(Address(rsp, src_offset)); |
|
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|
962 __ popl (Address(rsp, dst_offset)); |
|
8c92982cbbc4
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|
963 __ pushl(Address(rsp, src_offset+4)); |
|
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|
964 __ popl (Address(rsp, dst_offset+4)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
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|
965 break; |
|
8c92982cbbc4
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|
966 case Op_VecX: |
|
8c92982cbbc4
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|
967 __ movdqu(Address(rsp, -16), xmm0); |
|
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|
968 __ movdqu(xmm0, Address(rsp, src_offset)); |
|
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|
969 __ movdqu(Address(rsp, dst_offset), xmm0); |
|
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970 __ movdqu(xmm0, Address(rsp, -16)); |
|
8c92982cbbc4
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|
971 break; |
|
8c92982cbbc4
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|
972 case Op_VecY: |
|
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|
973 __ vmovdqu(Address(rsp, -32), xmm0); |
|
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974 __ vmovdqu(xmm0, Address(rsp, src_offset)); |
|
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975 __ vmovdqu(Address(rsp, dst_offset), xmm0); |
|
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976 __ vmovdqu(xmm0, Address(rsp, -32)); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
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|
977 break; |
|
8c92982cbbc4
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kvn
parents:
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|
978 default: |
|
8c92982cbbc4
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|
979 ShouldNotReachHere(); |
|
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|
980 } |
|
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|
981 int size = __ offset() - offset; |
|
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|
982 assert(size == calc_size, "incorrect size calculattion"); |
|
8c92982cbbc4
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|
983 return size; |
|
8c92982cbbc4
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|
984 #ifndef PRODUCT |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
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|
985 } else if (!do_size) { |
|
8c92982cbbc4
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|
986 switch (ireg) { |
|
8c92982cbbc4
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|
987 case Op_VecS: |
|
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|
988 st->print("pushl [rsp + #%d]\t# 32-bit mem-mem spill\n\t" |
|
8c92982cbbc4
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|
989 "popl [rsp + #%d]", |
|
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|
990 src_offset, dst_offset); |
|
8c92982cbbc4
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|
991 break; |
|
8c92982cbbc4
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|
992 case Op_VecD: |
|
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|
993 st->print("pushl [rsp + #%d]\t# 64-bit mem-mem spill\n\t" |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
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|
994 "popq [rsp + #%d]\n\t" |
|
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|
995 "pushl [rsp + #%d]\n\t" |
|
8c92982cbbc4
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|
996 "popq [rsp + #%d]", |
|
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997 src_offset, dst_offset, src_offset+4, dst_offset+4); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
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|
998 break; |
|
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|
999 case Op_VecX: |
|
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|
1000 st->print("movdqu [rsp - #16], xmm0\t# 128-bit mem-mem spill\n\t" |
|
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|
1001 "movdqu xmm0, [rsp + #%d]\n\t" |
|
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|
1002 "movdqu [rsp + #%d], xmm0\n\t" |
|
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|
1003 "movdqu xmm0, [rsp - #16]", |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
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|
1004 src_offset, dst_offset); |
|
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|
1005 break; |
|
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|
1006 case Op_VecY: |
|
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|
1007 st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t" |
|
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|
1008 "vmovdqu xmm0, [rsp + #%d]\n\t" |
|
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1009 "vmovdqu [rsp + #%d], xmm0\n\t" |
|
8c92982cbbc4
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|
1010 "vmovdqu xmm0, [rsp - #32]", |
|
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|
1011 src_offset, dst_offset); |
|
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changeset
|
1012 break; |
|
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|
1013 default: |
|
8c92982cbbc4
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|
1014 ShouldNotReachHere(); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
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|
1015 } |
|
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|
1016 #endif |
|
8c92982cbbc4
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|
1017 } |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
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changeset
|
1018 return calc_size; |
|
8c92982cbbc4
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|
1019 } |
|
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|
1020 |
| 0 | 1021 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const { |
| 1022 // Get registers to move | |
| 1023 OptoReg::Name src_second = ra_->get_reg_second(in(1)); | |
| 1024 OptoReg::Name src_first = ra_->get_reg_first(in(1)); | |
| 1025 OptoReg::Name dst_second = ra_->get_reg_second(this ); | |
| 1026 OptoReg::Name dst_first = ra_->get_reg_first(this ); | |
| 1027 | |
| 1028 enum RC src_second_rc = rc_class(src_second); | |
| 1029 enum RC src_first_rc = rc_class(src_first); | |
| 1030 enum RC dst_second_rc = rc_class(dst_second); | |
| 1031 enum RC dst_first_rc = rc_class(dst_first); | |
| 1032 | |
| 1033 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" ); | |
| 1034 | |
| 1035 // Generate spill code! | |
| 1036 int size = 0; | |
| 1037 | |
| 1038 if( src_first == dst_first && src_second == dst_second ) | |
| 1039 return size; // Self copy, no move | |
| 1040 | |
|
6179
8c92982cbbc4
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|
1041 if (bottom_type()->isa_vect() != NULL) { |
|
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1042 uint ireg = ideal_reg(); |
|
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1043 assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity"); |
|
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1044 assert((src_first_rc != rc_float && dst_first_rc != rc_float), "sanity"); |
|
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1045 assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY), "sanity"); |
|
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1046 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) { |
|
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|
1047 // mem -> mem |
|
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|
1048 int src_offset = ra_->reg2offset(src_first); |
|
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|
1049 int dst_offset = ra_->reg2offset(dst_first); |
|
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|
1050 return vec_stack_to_stack_helper(cbuf, do_size, src_offset, dst_offset, ireg, st); |
|
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|
1051 } else if (src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) { |
|
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1052 return vec_mov_helper(cbuf, do_size, src_first, dst_first, src_second, dst_second, ireg, st); |
|
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1053 } else if (src_first_rc == rc_xmm && dst_first_rc == rc_stack ) { |
|
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|
1054 int stack_offset = ra_->reg2offset(dst_first); |
|
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1055 return vec_spill_helper(cbuf, do_size, false, stack_offset, src_first, ireg, st); |
|
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1056 } else if (src_first_rc == rc_stack && dst_first_rc == rc_xmm ) { |
|
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|
1057 int stack_offset = ra_->reg2offset(src_first); |
|
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1058 return vec_spill_helper(cbuf, do_size, true, stack_offset, dst_first, ireg, st); |
|
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1059 } else { |
|
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|
1060 ShouldNotReachHere(); |
|
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|
1061 } |
|
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|
1062 } |
|
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|
1063 |
| 0 | 1064 // -------------------------------------- |
| 1065 // Check for mem-mem move. push/pop to move. | |
| 1066 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) { | |
| 1067 if( src_second == dst_first ) { // overlapping stack copy ranges | |
| 1068 assert( src_second_rc == rc_stack && dst_second_rc == rc_stack, "we only expect a stk-stk copy here" ); | |
|
415
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diff
changeset
|
1069 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st); |
|
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403
diff
changeset
|
1070 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st); |
| 0 | 1071 src_second_rc = dst_second_rc = rc_bad; // flag as already moved the second bits |
| 1072 } | |
| 1073 // move low bits | |
|
415
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parents:
403
diff
changeset
|
1074 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),ESI_num,0xFF,"PUSH ",size, st); |
|
4d9884b01ba6
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parents:
403
diff
changeset
|
1075 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),EAX_num,0x8F,"POP ",size, st); |
| 0 | 1076 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { // mov second bits |
|
415
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parents:
403
diff
changeset
|
1077 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st); |
|
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diff
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|
1078 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st); |
| 0 | 1079 } |
| 1080 return size; | |
| 1081 } | |
| 1082 | |
| 1083 // -------------------------------------- | |
| 1084 // Check for integer reg-reg copy | |
| 1085 if( src_first_rc == rc_int && dst_first_rc == rc_int ) | |
|
415
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6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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parents:
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diff
changeset
|
1086 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,size, st); |
| 0 | 1087 |
| 1088 // Check for integer store | |
| 1089 if( src_first_rc == rc_int && dst_first_rc == rc_stack ) | |
|
415
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parents:
403
diff
changeset
|
1090 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first,0x89,"MOV ",size, st); |
| 0 | 1091 |
| 1092 // Check for integer load | |
| 1093 if( dst_first_rc == rc_int && src_first_rc == rc_stack ) | |
|
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1094 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first,0x8B,"MOV ",size, st); |
| 0 | 1095 |
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1096 // Check for integer reg-xmm reg copy |
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1097 if( src_first_rc == rc_int && dst_first_rc == rc_xmm ) { |
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1098 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad), |
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1099 "no 64 bit integer-float reg moves" ); |
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1100 return impl_movgpr2x_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st); |
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1101 } |
| 0 | 1102 // -------------------------------------- |
| 1103 // Check for float reg-reg copy | |
| 1104 if( src_first_rc == rc_float && dst_first_rc == rc_float ) { | |
| 1105 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) || | |
| 1106 (src_first+1 == src_second && dst_first+1 == dst_second), "no non-adjacent float-moves" ); | |
| 1107 if( cbuf ) { | |
| 1108 | |
| 1109 // Note the mucking with the register encode to compensate for the 0/1 | |
| 1110 // indexing issue mentioned in a comment in the reg_def sections | |
| 1111 // for FPR registers many lines above here. | |
| 1112 | |
| 1113 if( src_first != FPR1L_num ) { | |
| 1114 emit_opcode (*cbuf, 0xD9 ); // FLD ST(i) | |
| 1115 emit_d8 (*cbuf, 0xC0+Matcher::_regEncode[src_first]-1 ); | |
| 1116 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i) | |
| 1117 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] ); | |
| 1118 } else { | |
| 1119 emit_opcode (*cbuf, 0xDD ); // FST ST(i) | |
| 1120 emit_d8 (*cbuf, 0xD0+Matcher::_regEncode[dst_first]-1 ); | |
| 1121 } | |
| 1122 #ifndef PRODUCT | |
| 1123 } else if( !do_size ) { | |
| 1124 if( size != 0 ) st->print("\n\t"); | |
| 1125 if( src_first != FPR1L_num ) st->print("FLD %s\n\tFSTP %s",Matcher::regName[src_first],Matcher::regName[dst_first]); | |
| 1126 else st->print( "FST %s", Matcher::regName[dst_first]); | |
| 1127 #endif | |
| 1128 } | |
| 1129 return size + ((src_first != FPR1L_num) ? 2+2 : 2); | |
| 1130 } | |
| 1131 | |
| 1132 // Check for float store | |
| 1133 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) { | |
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1134 return impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,ra_->reg2offset(dst_first),size, st); |
| 0 | 1135 } |
| 1136 | |
| 1137 // Check for float load | |
| 1138 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) { | |
| 1139 int offset = ra_->reg2offset(src_first); | |
| 1140 const char *op_str; | |
| 1141 int op; | |
| 1142 if( src_first+1 == src_second && dst_first+1 == dst_second ) { // double load? | |
| 1143 op_str = "FLD_D"; | |
| 1144 op = 0xDD; | |
| 1145 } else { // 32-bit load | |
| 1146 op_str = "FLD_S"; | |
| 1147 op = 0xD9; | |
| 1148 assert( src_second_rc == rc_bad && dst_second_rc == rc_bad, "no non-adjacent float-loads" ); | |
| 1149 } | |
| 1150 if( cbuf ) { | |
| 1151 emit_opcode (*cbuf, op ); | |
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1152 encode_RegMem(*cbuf, 0x0, ESP_enc, 0x4, 0, offset, relocInfo::none); |
| 0 | 1153 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i) |
| 1154 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] ); | |
| 1155 #ifndef PRODUCT | |
| 1156 } else if( !do_size ) { | |
| 1157 if( size != 0 ) st->print("\n\t"); | |
| 1158 st->print("%s ST,[ESP + #%d]\n\tFSTP %s",op_str, offset,Matcher::regName[dst_first]); | |
| 1159 #endif | |
| 1160 } | |
| 1161 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4); | |
| 1162 return size + 3+offset_size+2; | |
| 1163 } | |
| 1164 | |
| 1165 // Check for xmm reg-reg copy | |
| 1166 if( src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) { | |
| 1167 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) || | |
| 1168 (src_first+1 == src_second && dst_first+1 == dst_second), | |
| 1169 "no non-adjacent float-moves" ); | |
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1170 return impl_movx_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st); |
| 0 | 1171 } |
| 1172 | |
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1173 // Check for xmm reg-integer reg copy |
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1174 if( src_first_rc == rc_xmm && dst_first_rc == rc_int ) { |
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1175 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad), |
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1176 "no 64 bit float-integer reg moves" ); |
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1177 return impl_movx2gpr_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st); |
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1178 } |
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1179 |
| 0 | 1180 // Check for xmm store |
| 1181 if( src_first_rc == rc_xmm && dst_first_rc == rc_stack ) { | |
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1182 return impl_x_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first, src_second, size, st); |
| 0 | 1183 } |
| 1184 | |
| 1185 // Check for float xmm load | |
| 1186 if( dst_first_rc == rc_xmm && src_first_rc == rc_stack ) { | |
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1187 return impl_x_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first, dst_second, size, st); |
| 0 | 1188 } |
| 1189 | |
| 1190 // Copy from float reg to xmm reg | |
| 1191 if( dst_first_rc == rc_xmm && src_first_rc == rc_float ) { | |
| 1192 // copy to the top of stack from floating point reg | |
| 1193 // and use LEA to preserve flags | |
| 1194 if( cbuf ) { | |
| 1195 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP-8] | |
| 1196 emit_rm(*cbuf, 0x1, ESP_enc, 0x04); | |
| 1197 emit_rm(*cbuf, 0x0, 0x04, ESP_enc); | |
| 1198 emit_d8(*cbuf,0xF8); | |
| 1199 #ifndef PRODUCT | |
| 1200 } else if( !do_size ) { | |
| 1201 if( size != 0 ) st->print("\n\t"); | |
| 1202 st->print("LEA ESP,[ESP-8]"); | |
| 1203 #endif | |
| 1204 } | |
| 1205 size += 4; | |
| 1206 | |
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1207 size = impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,0,size, st); |
| 0 | 1208 |
| 1209 // Copy from the temp memory to the xmm reg. | |
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1210 size = impl_x_helper(cbuf,do_size,true ,0,dst_first, dst_second, size, st); |
| 0 | 1211 |
| 1212 if( cbuf ) { | |
| 1213 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP+8] | |
| 1214 emit_rm(*cbuf, 0x1, ESP_enc, 0x04); | |
| 1215 emit_rm(*cbuf, 0x0, 0x04, ESP_enc); | |
| 1216 emit_d8(*cbuf,0x08); | |
| 1217 #ifndef PRODUCT | |
| 1218 } else if( !do_size ) { | |
| 1219 if( size != 0 ) st->print("\n\t"); | |
| 1220 st->print("LEA ESP,[ESP+8]"); | |
| 1221 #endif | |
| 1222 } | |
| 1223 size += 4; | |
| 1224 return size; | |
| 1225 } | |
| 1226 | |
| 1227 assert( size > 0, "missed a case" ); | |
| 1228 | |
| 1229 // -------------------------------------------------------------------- | |
| 1230 // Check for second bits still needing moving. | |
| 1231 if( src_second == dst_second ) | |
| 1232 return size; // Self copy; no move | |
| 1233 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" ); | |
| 1234 | |
| 1235 // Check for second word int-int move | |
| 1236 if( src_second_rc == rc_int && dst_second_rc == rc_int ) | |
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1237 return impl_mov_helper(cbuf,do_size,src_second,dst_second,size, st); |
| 0 | 1238 |
| 1239 // Check for second word integer store | |
| 1240 if( src_second_rc == rc_int && dst_second_rc == rc_stack ) | |
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1241 return impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),src_second,0x89,"MOV ",size, st); |
| 0 | 1242 |
| 1243 // Check for second word integer load | |
| 1244 if( dst_second_rc == rc_int && src_second_rc == rc_stack ) | |
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1245 return impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),dst_second,0x8B,"MOV ",size, st); |
| 0 | 1246 |
| 1247 | |
| 1248 Unimplemented(); | |
| 1249 } | |
| 1250 | |
| 1251 #ifndef PRODUCT | |
| 4950 | 1252 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const { |
| 0 | 1253 implementation( NULL, ra_, false, st ); |
| 1254 } | |
| 1255 #endif | |
| 1256 | |
| 1257 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1258 implementation( &cbuf, ra_, false, NULL ); | |
| 1259 } | |
| 1260 | |
| 1261 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const { | |
| 1262 return implementation( NULL, ra_, true, NULL ); | |
| 1263 } | |
| 1264 | |
| 1265 | |
| 1266 //============================================================================= | |
| 1267 #ifndef PRODUCT | |
| 1268 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream* st ) const { | |
| 1269 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
| 1270 int reg = ra_->get_reg_first(this); | |
| 1271 st->print("LEA %s,[ESP + #%d]",Matcher::regName[reg],offset); | |
| 1272 } | |
| 1273 #endif | |
| 1274 | |
| 1275 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1276 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
| 1277 int reg = ra_->get_encode(this); | |
| 1278 if( offset >= 128 ) { | |
| 1279 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset] | |
| 1280 emit_rm(cbuf, 0x2, reg, 0x04); | |
| 1281 emit_rm(cbuf, 0x0, 0x04, ESP_enc); | |
| 1282 emit_d32(cbuf, offset); | |
| 1283 } | |
| 1284 else { | |
| 1285 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset] | |
| 1286 emit_rm(cbuf, 0x1, reg, 0x04); | |
| 1287 emit_rm(cbuf, 0x0, 0x04, ESP_enc); | |
| 1288 emit_d8(cbuf, offset); | |
| 1289 } | |
| 1290 } | |
| 1291 | |
| 1292 uint BoxLockNode::size(PhaseRegAlloc *ra_) const { | |
| 1293 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
| 1294 if( offset >= 128 ) { | |
| 1295 return 7; | |
| 1296 } | |
| 1297 else { | |
| 1298 return 4; | |
| 1299 } | |
| 1300 } | |
| 1301 | |
| 1302 //============================================================================= | |
| 1303 #ifndef PRODUCT | |
| 1304 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream* st ) const { | |
| 1305 st->print_cr( "CMP EAX,[ECX+4]\t# Inline cache check"); | |
| 1306 st->print_cr("\tJNE SharedRuntime::handle_ic_miss_stub"); | |
| 1307 st->print_cr("\tNOP"); | |
| 1308 st->print_cr("\tNOP"); | |
| 1309 if( !OptoBreakpoint ) | |
| 1310 st->print_cr("\tNOP"); | |
| 1311 } | |
| 1312 #endif | |
| 1313 | |
| 1314 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1315 MacroAssembler masm(&cbuf); | |
| 1316 #ifdef ASSERT | |
| 1748 | 1317 uint insts_size = cbuf.insts_size(); |
| 0 | 1318 #endif |
| 304 | 1319 masm.cmpptr(rax, Address(rcx, oopDesc::klass_offset_in_bytes())); |
| 0 | 1320 masm.jump_cc(Assembler::notEqual, |
| 1321 RuntimeAddress(SharedRuntime::get_ic_miss_stub())); | |
| 1322 /* WARNING these NOPs are critical so that verified entry point is properly | |
| 1323 aligned for patching by NativeJump::patch_verified_entry() */ | |
| 1324 int nops_cnt = 2; | |
| 1325 if( !OptoBreakpoint ) // Leave space for int3 | |
| 1326 nops_cnt += 1; | |
| 1327 masm.nop(nops_cnt); | |
| 1328 | |
| 1748 | 1329 assert(cbuf.insts_size() - insts_size == size(ra_), "checking code size of inline cache node"); |
| 0 | 1330 } |
| 1331 | |
| 1332 uint MachUEPNode::size(PhaseRegAlloc *ra_) const { | |
| 1333 return OptoBreakpoint ? 11 : 12; | |
| 1334 } | |
| 1335 | |
| 1336 | |
| 1337 //============================================================================= | |
| 1338 | |
| 1339 int Matcher::regnum_to_fpu_offset(int regnum) { | |
| 1340 return regnum - 32; // The FP registers are in the second chunk | |
| 1341 } | |
| 1342 | |
| 1343 // This is UltraSparc specific, true just means we have fast l2f conversion | |
| 1344 const bool Matcher::convL2FSupported(void) { | |
| 1345 return true; | |
| 1346 } | |
| 1347 | |
| 1348 // Is this branch offset short enough that a short branch can be used? | |
| 1349 // | |
| 1350 // NOTE: If the platform does not provide any short branch variants, then | |
| 1351 // this method should return false for offset 0. | |
| 3851 | 1352 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) { |
| 1353 // The passed offset is relative to address of the branch. | |
| 1354 // On 86 a branch displacement is calculated relative to address | |
| 1355 // of a next instruction. | |
| 1356 offset -= br_size; | |
| 1357 | |
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1358 // the short version of jmpConUCF2 contains multiple branches, |
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1359 // making the reach slightly less |
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1360 if (rule == jmpConUCF2_rule) |
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1361 return (-126 <= offset && offset <= 125); |
| 0 | 1362 return (-128 <= offset && offset <= 127); |
| 1363 } | |
| 1364 | |
| 1365 const bool Matcher::isSimpleConstant64(jlong value) { | |
| 1366 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?. | |
| 1367 return false; | |
| 1368 } | |
| 1369 | |
| 1370 // The ecx parameter to rep stos for the ClearArray node is in dwords. | |
| 1371 const bool Matcher::init_array_count_is_in_bytes = false; | |
| 1372 | |
| 1373 // Threshold size for cleararray. | |
| 1374 const int Matcher::init_array_short_size = 8 * BytesPerLong; | |
| 1375 | |
| 4047 | 1376 // Needs 2 CMOV's for longs. |
| 1377 const int Matcher::long_cmove_cost() { return 1; } | |
| 1378 | |
| 1379 // No CMOVF/CMOVD with SSE/SSE2 | |
| 1380 const int Matcher::float_cmove_cost() { return (UseSSE>=1) ? ConditionalMoveLimit : 0; } | |
| 1381 | |
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1382 // Does the CPU require late expand (see block.cpp for description of late expand)? |
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1383 const bool Matcher::require_postalloc_expand = false; |
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1384 |
| 0 | 1385 // Should the Matcher clone shifts on addressing modes, expecting them to |
| 1386 // be subsumed into complex addressing expressions or compute them into | |
| 1387 // registers? True for Intel but false for most RISCs | |
| 1388 const bool Matcher::clone_shift_expressions = true; | |
| 1389 | |
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1390 // Do we need to mask the count passed to shift instructions or does |
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1391 // the cpu only look at the lower 5/6 bits anyway? |
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1392 const bool Matcher::need_masked_shift_count = false; |
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1393 |
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1394 bool Matcher::narrow_oop_use_complex_address() { |
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1395 ShouldNotCallThis(); |
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1396 return true; |
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1397 } |
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1398 |
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1399 bool Matcher::narrow_klass_use_complex_address() { |
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1400 ShouldNotCallThis(); |
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1401 return true; |
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1402 } |
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1403 |
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1404 |
| 0 | 1405 // Is it better to copy float constants, or load them directly from memory? |
| 1406 // Intel can load a float constant from a direct address, requiring no | |
| 1407 // extra registers. Most RISCs will have to materialize an address into a | |
| 1408 // register first, so they would do better to copy the constant from stack. | |
| 1409 const bool Matcher::rematerialize_float_constants = true; | |
| 1410 | |
| 1411 // If CPU can load and store mis-aligned doubles directly then no fixup is | |
| 1412 // needed. Else we split the double into 2 integer pieces and move it | |
| 1413 // piece-by-piece. Only happens when passing doubles into C code as the | |
| 1414 // Java calling convention forces doubles to be aligned. | |
| 1415 const bool Matcher::misaligned_doubles_ok = true; | |
| 1416 | |
| 1417 | |
| 1418 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) { | |
| 1419 // Get the memory operand from the node | |
| 1420 uint numopnds = node->num_opnds(); // Virtual call for number of operands | |
| 1421 uint skipped = node->oper_input_base(); // Sum of leaves skipped so far | |
| 1422 assert( idx >= skipped, "idx too low in pd_implicit_null_fixup" ); | |
| 1423 uint opcnt = 1; // First operand | |
| 1424 uint num_edges = node->_opnds[1]->num_edges(); // leaves for first operand | |
| 1425 while( idx >= skipped+num_edges ) { | |
| 1426 skipped += num_edges; | |
| 1427 opcnt++; // Bump operand count | |
| 1428 assert( opcnt < numopnds, "Accessing non-existent operand" ); | |
| 1429 num_edges = node->_opnds[opcnt]->num_edges(); // leaves for next operand | |
| 1430 } | |
| 1431 | |
| 1432 MachOper *memory = node->_opnds[opcnt]; | |
| 1433 MachOper *new_memory = NULL; | |
| 1434 switch (memory->opcode()) { | |
| 1435 case DIRECT: | |
| 1436 case INDOFFSET32X: | |
| 1437 // No transformation necessary. | |
| 1438 return; | |
| 1439 case INDIRECT: | |
| 1440 new_memory = new (C) indirect_win95_safeOper( ); | |
| 1441 break; | |
| 1442 case INDOFFSET8: | |
| 1443 new_memory = new (C) indOffset8_win95_safeOper(memory->disp(NULL, NULL, 0)); | |
| 1444 break; | |
| 1445 case INDOFFSET32: | |
| 1446 new_memory = new (C) indOffset32_win95_safeOper(memory->disp(NULL, NULL, 0)); | |
| 1447 break; | |
| 1448 case INDINDEXOFFSET: | |
| 1449 new_memory = new (C) indIndexOffset_win95_safeOper(memory->disp(NULL, NULL, 0)); | |
| 1450 break; | |
| 1451 case INDINDEXSCALE: | |
| 1452 new_memory = new (C) indIndexScale_win95_safeOper(memory->scale()); | |
| 1453 break; | |
| 1454 case INDINDEXSCALEOFFSET: | |
| 1455 new_memory = new (C) indIndexScaleOffset_win95_safeOper(memory->scale(), memory->disp(NULL, NULL, 0)); | |
| 1456 break; | |
| 1457 case LOAD_LONG_INDIRECT: | |
| 1458 case LOAD_LONG_INDOFFSET32: | |
| 1459 // Does not use EBP as address register, use { EDX, EBX, EDI, ESI} | |
| 1460 return; | |
| 1461 default: | |
| 1462 assert(false, "unexpected memory operand in pd_implicit_null_fixup()"); | |
| 1463 return; | |
| 1464 } | |
| 1465 node->_opnds[opcnt] = new_memory; | |
| 1466 } | |
| 1467 | |
| 1468 // Advertise here if the CPU requires explicit rounding operations | |
| 1469 // to implement the UseStrictFP mode. | |
| 1470 const bool Matcher::strict_fp_requires_explicit_rounding = true; | |
| 1471 | |
|
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1472 // Are floats conerted to double when stored to stack during deoptimization? |
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1473 // On x32 it is stored with convertion only when FPU is used for floats. |
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1474 bool Matcher::float_in_double() { return (UseSSE == 0); } |
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1475 |
| 0 | 1476 // Do ints take an entire long register or just half? |
| 1477 const bool Matcher::int_in_long = false; | |
| 1478 | |
| 1479 // Return whether or not this register is ever used as an argument. This | |
| 1480 // function is used on startup to build the trampoline stubs in generateOptoStub. | |
| 1481 // Registers not mentioned will be killed by the VM call in the trampoline, and | |
| 1482 // arguments in those registers not be available to the callee. | |
| 1483 bool Matcher::can_be_java_arg( int reg ) { | |
| 1484 if( reg == ECX_num || reg == EDX_num ) return true; | |
|
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1485 if( (reg == XMM0_num || reg == XMM1_num ) && UseSSE>=1 ) return true; |
| 0 | 1486 if( (reg == XMM0b_num || reg == XMM1b_num) && UseSSE>=2 ) return true; |
| 1487 return false; | |
| 1488 } | |
| 1489 | |
| 1490 bool Matcher::is_spillable_arg( int reg ) { | |
| 1491 return can_be_java_arg(reg); | |
| 1492 } | |
| 1493 | |
|
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1494 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) { |
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1495 // Use hardware integer DIV instruction when |
|
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1496 // it is faster than a code which use multiply. |
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1497 // Only when constant divisor fits into 32 bit |
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1498 // (min_jint is excluded to get only correct |
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1499 // positive 32 bit values from negative). |
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1500 return VM_Version::has_fast_idiv() && |
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1501 (divisor == (int)divisor && divisor != min_jint); |
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1502 } |
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1503 |
| 0 | 1504 // Register for DIVI projection of divmodI |
| 1505 RegMask Matcher::divI_proj_mask() { | |
|
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1506 return EAX_REG_mask(); |
| 0 | 1507 } |
| 1508 | |
| 1509 // Register for MODI projection of divmodI | |
| 1510 RegMask Matcher::modI_proj_mask() { | |
|
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1511 return EDX_REG_mask(); |
| 0 | 1512 } |
| 1513 | |
| 1514 // Register for DIVL projection of divmodL | |
| 1515 RegMask Matcher::divL_proj_mask() { | |
| 1516 ShouldNotReachHere(); | |
| 1517 return RegMask(); | |
| 1518 } | |
| 1519 | |
| 1520 // Register for MODL projection of divmodL | |
| 1521 RegMask Matcher::modL_proj_mask() { | |
| 1522 ShouldNotReachHere(); | |
| 1523 return RegMask(); | |
| 1524 } | |
| 1525 | |
|
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1526 const RegMask Matcher::method_handle_invoke_SP_save_mask() { |
|
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1527 return NO_REG_mask(); |
|
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1528 } |
|
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1529 |
|
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1530 // Returns true if the high 32 bits of the value is known to be zero. |
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1531 bool is_operand_hi32_zero(Node* n) { |
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1532 int opc = n->Opcode(); |
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1533 if (opc == Op_AndL) { |
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1534 Node* o2 = n->in(2); |
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1535 if (o2->is_Con() && (o2->get_long() & 0xFFFFFFFF00000000LL) == 0LL) { |
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1536 return true; |
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1537 } |
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1538 } |
|
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1539 if (opc == Op_ConL && (n->get_long() & 0xFFFFFFFF00000000LL) == 0LL) { |
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1540 return true; |
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|
1541 } |
|
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1542 return false; |
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1543 } |
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|
1544 |
| 0 | 1545 %} |
| 1546 | |
| 1547 //----------ENCODING BLOCK----------------------------------------------------- | |
| 1548 // This block specifies the encoding classes used by the compiler to output | |
| 1549 // byte streams. Encoding classes generate functions which are called by | |
| 1550 // Machine Instruction Nodes in order to generate the bit encoding of the | |
| 1551 // instruction. Operands specify their base encoding interface with the | |
| 1552 // interface keyword. There are currently supported four interfaces, | |
| 1553 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an | |
| 1554 // operand to generate a function which returns its register number when | |
| 1555 // queried. CONST_INTER causes an operand to generate a function which | |
| 1556 // returns the value of the constant when queried. MEMORY_INTER causes an | |
| 1557 // operand to generate four functions which return the Base Register, the | |
| 1558 // Index Register, the Scale Value, and the Offset Value of the operand when | |
| 1559 // queried. COND_INTER causes an operand to generate six functions which | |
| 1560 // return the encoding code (ie - encoding bits for the instruction) | |
| 1561 // associated with each basic boolean condition for a conditional instruction. | |
| 1562 // Instructions specify two basic values for encoding. They use the | |
| 1563 // ins_encode keyword to specify their encoding class (which must be one of | |
| 1564 // the class names specified in the encoding block), and they use the | |
| 1565 // opcode keyword to specify, in order, their primary, secondary, and | |
| 1566 // tertiary opcode. Only the opcode sections which a particular instruction | |
| 1567 // needs for encoding need to be specified. | |
| 1568 encode %{ | |
| 1569 // Build emit functions for each basic byte or larger field in the intel | |
| 1570 // encoding scheme (opcode, rm, sib, immediate), and call them from C++ | |
| 1571 // code in the enc_class source block. Emit functions will live in the | |
| 1572 // main source block for now. In future, we can generalize this by | |
| 1573 // adding a syntax that specifies the sizes of fields in an order, | |
| 1574 // so that the adlc can build the emit functions automagically | |
|
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1575 |
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1576 // Emit primary opcode |
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1577 enc_class OpcP %{ |
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1578 emit_opcode(cbuf, $primary); |
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1579 %} |
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1580 |
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1581 // Emit secondary opcode |
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1582 enc_class OpcS %{ |
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1583 emit_opcode(cbuf, $secondary); |
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1584 %} |
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1585 |
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1586 // Emit opcode directly |
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1587 enc_class Opcode(immI d8) %{ |
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1588 emit_opcode(cbuf, $d8$$constant); |
| 0 | 1589 %} |
| 1590 | |
| 1591 enc_class SizePrefix %{ | |
| 1592 emit_opcode(cbuf,0x66); | |
| 1593 %} | |
| 1594 | |
|
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1595 enc_class RegReg (rRegI dst, rRegI src) %{ // RegReg(Many) |
| 0 | 1596 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); |
| 1597 %} | |
| 1598 | |
|
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1599 enc_class OpcRegReg (immI opcode, rRegI dst, rRegI src) %{ // OpcRegReg(Many) |
| 0 | 1600 emit_opcode(cbuf,$opcode$$constant); |
| 1601 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 1602 %} | |
| 1603 | |
|
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1604 enc_class mov_r32_imm0( rRegI dst ) %{ |
| 0 | 1605 emit_opcode( cbuf, 0xB8 + $dst$$reg ); // 0xB8+ rd -- MOV r32 ,imm32 |
| 1606 emit_d32 ( cbuf, 0x0 ); // imm32==0x0 | |
| 1607 %} | |
| 1608 | |
| 1609 enc_class cdq_enc %{ | |
| 1610 // Full implementation of Java idiv and irem; checks for | |
| 1611 // special case as described in JVM spec., p.243 & p.271. | |
| 1612 // | |
| 1613 // normal case special case | |
| 1614 // | |
| 1615 // input : rax,: dividend min_int | |
| 1616 // reg: divisor -1 | |
| 1617 // | |
| 1618 // output: rax,: quotient (= rax, idiv reg) min_int | |
| 1619 // rdx: remainder (= rax, irem reg) 0 | |
| 1620 // | |
| 1621 // Code sequnce: | |
| 1622 // | |
| 1623 // 81 F8 00 00 00 80 cmp rax,80000000h | |
| 1624 // 0F 85 0B 00 00 00 jne normal_case | |
| 1625 // 33 D2 xor rdx,edx | |
| 1626 // 83 F9 FF cmp rcx,0FFh | |
| 1627 // 0F 84 03 00 00 00 je done | |
| 1628 // normal_case: | |
| 1629 // 99 cdq | |
| 1630 // F7 F9 idiv rax,ecx | |
| 1631 // done: | |
| 1632 // | |
| 1633 emit_opcode(cbuf,0x81); emit_d8(cbuf,0xF8); | |
| 1634 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); | |
| 1635 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x80); // cmp rax,80000000h | |
| 1636 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x85); | |
| 1637 emit_opcode(cbuf,0x0B); emit_d8(cbuf,0x00); | |
| 1638 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // jne normal_case | |
| 1639 emit_opcode(cbuf,0x33); emit_d8(cbuf,0xD2); // xor rdx,edx | |
| 1640 emit_opcode(cbuf,0x83); emit_d8(cbuf,0xF9); emit_d8(cbuf,0xFF); // cmp rcx,0FFh | |
| 1641 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x84); | |
| 1642 emit_opcode(cbuf,0x03); emit_d8(cbuf,0x00); | |
| 1643 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // je done | |
| 1644 // normal_case: | |
| 1645 emit_opcode(cbuf,0x99); // cdq | |
| 1646 // idiv (note: must be emitted by the user of this rule) | |
| 1647 // normal: | |
| 1648 %} | |
| 1649 | |
| 1650 // Dense encoding for older common ops | |
|
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1651 enc_class Opc_plus(immI opcode, rRegI reg) %{ |
| 0 | 1652 emit_opcode(cbuf, $opcode$$constant + $reg$$reg); |
| 1653 %} | |
| 1654 | |
| 1655 | |
| 1656 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension | |
| 1657 enc_class OpcSE (immI imm) %{ // Emit primary opcode and set sign-extend bit | |
| 1658 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 1659 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) { | |
| 1660 emit_opcode(cbuf, $primary | 0x02); | |
| 1661 } | |
| 1662 else { // If 32-bit immediate | |
| 1663 emit_opcode(cbuf, $primary); | |
| 1664 } | |
| 1665 %} | |
| 1666 | |
|
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1667 enc_class OpcSErm (rRegI dst, immI imm) %{ // OpcSEr/m |
| 0 | 1668 // Emit primary opcode and set sign-extend bit |
| 1669 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 1670 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) { | |
| 1671 emit_opcode(cbuf, $primary | 0x02); } | |
| 1672 else { // If 32-bit immediate | |
| 1673 emit_opcode(cbuf, $primary); | |
| 1674 } | |
| 1675 // Emit r/m byte with secondary opcode, after primary opcode. | |
| 1676 emit_rm(cbuf, 0x3, $secondary, $dst$$reg); | |
| 1677 %} | |
| 1678 | |
| 1679 enc_class Con8or32 (immI imm) %{ // Con8or32(storeImmI), 8 or 32 bits | |
| 1680 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 1681 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) { | |
| 1682 $$$emit8$imm$$constant; | |
| 1683 } | |
| 1684 else { // If 32-bit immediate | |
| 1685 // Output immediate | |
| 1686 $$$emit32$imm$$constant; | |
| 1687 } | |
| 1688 %} | |
| 1689 | |
| 1690 enc_class Long_OpcSErm_Lo(eRegL dst, immL imm) %{ | |
| 1691 // Emit primary opcode and set sign-extend bit | |
| 1692 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 1693 int con = (int)$imm$$constant; // Throw away top bits | |
| 1694 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary); | |
| 1695 // Emit r/m byte with secondary opcode, after primary opcode. | |
| 1696 emit_rm(cbuf, 0x3, $secondary, $dst$$reg); | |
| 1697 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con); | |
| 1698 else emit_d32(cbuf,con); | |
| 1699 %} | |
| 1700 | |
| 1701 enc_class Long_OpcSErm_Hi(eRegL dst, immL imm) %{ | |
| 1702 // Emit primary opcode and set sign-extend bit | |
| 1703 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 1704 int con = (int)($imm$$constant >> 32); // Throw away bottom bits | |
| 1705 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary); | |
| 1706 // Emit r/m byte with tertiary opcode, after primary opcode. | |
| 1707 emit_rm(cbuf, 0x3, $tertiary, HIGH_FROM_LOW($dst$$reg)); | |
| 1708 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con); | |
| 1709 else emit_d32(cbuf,con); | |
| 1710 %} | |
| 1711 | |
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1712 enc_class OpcSReg (rRegI dst) %{ // BSWAP |
| 0 | 1713 emit_cc(cbuf, $secondary, $dst$$reg ); |
| 1714 %} | |
| 1715 | |
| 1716 enc_class bswap_long_bytes(eRegL dst) %{ // BSWAP | |
| 1717 int destlo = $dst$$reg; | |
| 1718 int desthi = HIGH_FROM_LOW(destlo); | |
| 1719 // bswap lo | |
| 1720 emit_opcode(cbuf, 0x0F); | |
| 1721 emit_cc(cbuf, 0xC8, destlo); | |
| 1722 // bswap hi | |
| 1723 emit_opcode(cbuf, 0x0F); | |
| 1724 emit_cc(cbuf, 0xC8, desthi); | |
| 1725 // xchg lo and hi | |
| 1726 emit_opcode(cbuf, 0x87); | |
| 1727 emit_rm(cbuf, 0x3, destlo, desthi); | |
| 1728 %} | |
| 1729 | |
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1730 enc_class RegOpc (rRegI div) %{ // IDIV, IMOD, JMP indirect, ... |
| 0 | 1731 emit_rm(cbuf, 0x3, $secondary, $div$$reg ); |
| 1732 %} | |
| 1733 | |
| 1734 enc_class enc_cmov(cmpOp cop ) %{ // CMOV | |
| 1735 $$$emit8$primary; | |
| 1736 emit_cc(cbuf, $secondary, $cop$$cmpcode); | |
| 1737 %} | |
| 1738 | |
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1739 enc_class enc_cmov_dpr(cmpOp cop, regDPR src ) %{ // CMOV |
| 0 | 1740 int op = 0xDA00 + $cop$$cmpcode + ($src$$reg-1); |
| 1741 emit_d8(cbuf, op >> 8 ); | |
| 1742 emit_d8(cbuf, op & 255); | |
| 1743 %} | |
| 1744 | |
| 1745 // emulate a CMOV with a conditional branch around a MOV | |
| 1746 enc_class enc_cmov_branch( cmpOp cop, immI brOffs ) %{ // CMOV | |
| 1747 // Invert sense of branch from sense of CMOV | |
| 1748 emit_cc( cbuf, 0x70, ($cop$$cmpcode^1) ); | |
| 1749 emit_d8( cbuf, $brOffs$$constant ); | |
| 1750 %} | |
| 1751 | |
| 1752 enc_class enc_PartialSubtypeCheck( ) %{ | |
| 1753 Register Redi = as_Register(EDI_enc); // result register | |
| 1754 Register Reax = as_Register(EAX_enc); // super class | |
| 1755 Register Recx = as_Register(ECX_enc); // killed | |
| 1756 Register Resi = as_Register(ESI_enc); // sub class | |
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1757 Label miss; |
| 0 | 1758 |
| 1759 MacroAssembler _masm(&cbuf); | |
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1760 __ check_klass_subtype_slow_path(Resi, Reax, Recx, Redi, |
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1761 NULL, &miss, |
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1762 /*set_cond_codes:*/ true); |
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1763 if ($primary) { |
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1764 __ xorptr(Redi, Redi); |
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1765 } |
| 0 | 1766 __ bind(miss); |
| 1767 %} | |
| 1768 | |
| 1769 enc_class FFree_Float_Stack_All %{ // Free_Float_Stack_All | |
| 1770 MacroAssembler masm(&cbuf); | |
| 1771 int start = masm.offset(); | |
| 1772 if (UseSSE >= 2) { | |
| 1773 if (VerifyFPU) { | |
| 1774 masm.verify_FPU(0, "must be empty in SSE2+ mode"); | |
| 1775 } | |
| 1776 } else { | |
| 1777 // External c_calling_convention expects the FPU stack to be 'clean'. | |
| 1778 // Compiled code leaves it dirty. Do cleanup now. | |
| 1779 masm.empty_FPU_stack(); | |
| 1780 } | |
| 1781 if (sizeof_FFree_Float_Stack_All == -1) { | |
| 1782 sizeof_FFree_Float_Stack_All = masm.offset() - start; | |
| 1783 } else { | |
| 1784 assert(masm.offset() - start == sizeof_FFree_Float_Stack_All, "wrong size"); | |
| 1785 } | |
| 1786 %} | |
| 1787 | |
| 1788 enc_class Verify_FPU_For_Leaf %{ | |
| 1789 if( VerifyFPU ) { | |
| 1790 MacroAssembler masm(&cbuf); | |
| 1791 masm.verify_FPU( -3, "Returning from Runtime Leaf call"); | |
| 1792 } | |
| 1793 %} | |
| 1794 | |
| 1795 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime, Java_To_Runtime_Leaf | |
| 1796 // This is the instruction starting address for relocation info. | |
| 1748 | 1797 cbuf.set_insts_mark(); |
| 0 | 1798 $$$emit8$primary; |
| 1799 // CALL directly to the runtime | |
| 1748 | 1800 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4), |
| 0 | 1801 runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 1802 | |
| 1803 if (UseSSE >= 2) { | |
| 1804 MacroAssembler _masm(&cbuf); | |
| 1805 BasicType rt = tf()->return_type(); | |
| 1806 | |
| 1807 if ((rt == T_FLOAT || rt == T_DOUBLE) && !return_value_is_used()) { | |
| 1808 // A C runtime call where the return value is unused. In SSE2+ | |
| 1809 // mode the result needs to be removed from the FPU stack. It's | |
| 1810 // likely that this function call could be removed by the | |
| 1811 // optimizer if the C function is a pure function. | |
| 1812 __ ffree(0); | |
| 1813 } else if (rt == T_FLOAT) { | |
| 304 | 1814 __ lea(rsp, Address(rsp, -4)); |
| 0 | 1815 __ fstp_s(Address(rsp, 0)); |
| 1816 __ movflt(xmm0, Address(rsp, 0)); | |
| 304 | 1817 __ lea(rsp, Address(rsp, 4)); |
| 0 | 1818 } else if (rt == T_DOUBLE) { |
| 304 | 1819 __ lea(rsp, Address(rsp, -8)); |
| 0 | 1820 __ fstp_d(Address(rsp, 0)); |
| 1821 __ movdbl(xmm0, Address(rsp, 0)); | |
| 304 | 1822 __ lea(rsp, Address(rsp, 8)); |
| 0 | 1823 } |
| 1824 } | |
| 1825 %} | |
| 1826 | |
| 1827 | |
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1828 enc_class pre_call_resets %{ |
| 0 | 1829 // If method sets FPU control word restore it here |
| 1748 | 1830 debug_only(int off0 = cbuf.insts_size()); |
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1831 if (ra_->C->in_24_bit_fp_mode()) { |
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1832 MacroAssembler _masm(&cbuf); |
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1833 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); |
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1834 } |
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1835 if (ra_->C->max_vector_size() > 16) { |
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1836 // Clear upper bits of YMM registers when current compiled code uses |
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1837 // wide vectors to avoid AVX <-> SSE transition penalty during call. |
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1838 MacroAssembler _masm(&cbuf); |
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1839 __ vzeroupper(); |
| 0 | 1840 } |
| 1748 | 1841 debug_only(int off1 = cbuf.insts_size()); |
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1842 assert(off1 - off0 == pre_call_resets_size(), "correct size prediction"); |
| 0 | 1843 %} |
| 1844 | |
| 1845 enc_class post_call_FPU %{ | |
| 1846 // If method sets FPU control word do it here also | |
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1847 if (Compile::current()->in_24_bit_fp_mode()) { |
| 0 | 1848 MacroAssembler masm(&cbuf); |
| 1849 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); | |
| 1850 } | |
| 1851 %} | |
| 1852 | |
| 1853 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL | |
| 1854 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine | |
| 1855 // who we intended to call. | |
| 1748 | 1856 cbuf.set_insts_mark(); |
| 0 | 1857 $$$emit8$primary; |
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1858 if (!_method) { |
| 1748 | 1859 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4), |
| 0 | 1860 runtime_call_Relocation::spec(), RELOC_IMM32 ); |
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1861 } else if (_optimized_virtual) { |
| 1748 | 1862 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4), |
| 0 | 1863 opt_virtual_call_Relocation::spec(), RELOC_IMM32 ); |
| 1864 } else { | |
| 1748 | 1865 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4), |
| 0 | 1866 static_call_Relocation::spec(), RELOC_IMM32 ); |
| 1867 } | |
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1868 if (_method) { // Emit stub for static call. |
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1869 CompiledStaticCall::emit_to_interp_stub(cbuf); |
| 0 | 1870 } |
| 1871 %} | |
| 1872 | |
| 1873 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL | |
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1874 MacroAssembler _masm(&cbuf); |
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1875 __ ic_call((address)$meth$$method); |
| 0 | 1876 %} |
| 1877 | |
| 1878 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL | |
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1879 int disp = in_bytes(Method::from_compiled_offset()); |
| 0 | 1880 assert( -128 <= disp && disp <= 127, "compiled_code_offset isn't small"); |
| 1881 | |
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1882 // CALL *[EAX+in_bytes(Method::from_compiled_code_entry_point_offset())] |
| 1748 | 1883 cbuf.set_insts_mark(); |
| 0 | 1884 $$$emit8$primary; |
| 1885 emit_rm(cbuf, 0x01, $secondary, EAX_enc ); // R/M byte | |
| 1886 emit_d8(cbuf, disp); // Displacement | |
| 1887 | |
| 1888 %} | |
| 1889 | |
| 1890 // Following encoding is no longer used, but may be restored if calling | |
| 1891 // convention changes significantly. | |
| 1892 // Became: Xor_Reg(EBP), Java_To_Runtime( labl ) | |
| 1893 // | |
| 1894 // enc_class Java_Interpreter_Call (label labl) %{ // JAVA INTERPRETER CALL | |
| 1895 // // int ic_reg = Matcher::inline_cache_reg(); | |
| 1896 // // int ic_encode = Matcher::_regEncode[ic_reg]; | |
| 1897 // // int imo_reg = Matcher::interpreter_method_oop_reg(); | |
| 1898 // // int imo_encode = Matcher::_regEncode[imo_reg]; | |
| 1899 // | |
| 1900 // // // Interpreter expects method_oop in EBX, currently a callee-saved register, | |
| 1901 // // // so we load it immediately before the call | |
| 1902 // // emit_opcode(cbuf, 0x8B); // MOV imo_reg,ic_reg # method_oop | |
| 1903 // // emit_rm(cbuf, 0x03, imo_encode, ic_encode ); // R/M byte | |
| 1904 // | |
| 1905 // // xor rbp,ebp | |
| 1906 // emit_opcode(cbuf, 0x33); | |
| 1907 // emit_rm(cbuf, 0x3, EBP_enc, EBP_enc); | |
| 1908 // | |
| 1909 // // CALL to interpreter. | |
| 1748 | 1910 // cbuf.set_insts_mark(); |
| 0 | 1911 // $$$emit8$primary; |
| 1748 | 1912 // emit_d32_reloc(cbuf, ($labl$$label - (int)(cbuf.insts_end()) - 4), |
| 0 | 1913 // runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 1914 // %} | |
| 1915 | |
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1916 enc_class RegOpcImm (rRegI dst, immI8 shift) %{ // SHL, SAR, SHR |
| 0 | 1917 $$$emit8$primary; |
| 1918 emit_rm(cbuf, 0x3, $secondary, $dst$$reg); | |
| 1919 $$$emit8$shift$$constant; | |
| 1920 %} | |
| 1921 | |
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1922 enc_class LdImmI (rRegI dst, immI src) %{ // Load Immediate |
| 0 | 1923 // Load immediate does not have a zero or sign extended version |
| 1924 // for 8-bit immediates | |
| 1925 emit_opcode(cbuf, 0xB8 + $dst$$reg); | |
| 1926 $$$emit32$src$$constant; | |
| 1927 %} | |
| 1928 | |
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1929 enc_class LdImmP (rRegI dst, immI src) %{ // Load Immediate |
| 0 | 1930 // Load immediate does not have a zero or sign extended version |
| 1931 // for 8-bit immediates | |
| 1932 emit_opcode(cbuf, $primary + $dst$$reg); | |
| 1933 $$$emit32$src$$constant; | |
| 1934 %} | |
| 1935 | |
| 1936 enc_class LdImmL_Lo( eRegL dst, immL src) %{ // Load Immediate | |
| 1937 // Load immediate does not have a zero or sign extended version | |
| 1938 // for 8-bit immediates | |
| 1939 int dst_enc = $dst$$reg; | |
| 1940 int src_con = $src$$constant & 0x0FFFFFFFFL; | |
| 1941 if (src_con == 0) { | |
| 1942 // xor dst, dst | |
| 1943 emit_opcode(cbuf, 0x33); | |
| 1944 emit_rm(cbuf, 0x3, dst_enc, dst_enc); | |
| 1945 } else { | |
| 1946 emit_opcode(cbuf, $primary + dst_enc); | |
| 1947 emit_d32(cbuf, src_con); | |
| 1948 } | |
| 1949 %} | |
| 1950 | |
| 1951 enc_class LdImmL_Hi( eRegL dst, immL src) %{ // Load Immediate | |
| 1952 // Load immediate does not have a zero or sign extended version | |
| 1953 // for 8-bit immediates | |
| 1954 int dst_enc = $dst$$reg + 2; | |
| 1955 int src_con = ((julong)($src$$constant)) >> 32; | |
| 1956 if (src_con == 0) { | |
| 1957 // xor dst, dst | |
| 1958 emit_opcode(cbuf, 0x33); | |
| 1959 emit_rm(cbuf, 0x3, dst_enc, dst_enc); | |
| 1960 } else { | |
| 1961 emit_opcode(cbuf, $primary + dst_enc); | |
| 1962 emit_d32(cbuf, src_con); | |
| 1963 } | |
| 1964 %} | |
| 1965 | |
| 1966 | |
| 1967 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
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1968 enc_class enc_Copy( rRegI dst, rRegI src ) %{ |
| 0 | 1969 encode_Copy( cbuf, $dst$$reg, $src$$reg ); |
| 1970 %} | |
| 1971 | |
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1972 enc_class enc_CopyL_Lo( rRegI dst, eRegL src ) %{ |
| 0 | 1973 encode_Copy( cbuf, $dst$$reg, $src$$reg ); |
| 1974 %} | |
| 1975 | |
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1976 enc_class RegReg (rRegI dst, rRegI src) %{ // RegReg(Many) |
| 0 | 1977 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); |
| 1978 %} | |
| 1979 | |
| 1980 enc_class RegReg_Lo(eRegL dst, eRegL src) %{ // RegReg(Many) | |
| 1981 $$$emit8$primary; | |
| 1982 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 1983 %} | |
| 1984 | |
| 1985 enc_class RegReg_Hi(eRegL dst, eRegL src) %{ // RegReg(Many) | |
| 1986 $$$emit8$secondary; | |
| 1987 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg)); | |
| 1988 %} | |
| 1989 | |
| 1990 enc_class RegReg_Lo2(eRegL dst, eRegL src) %{ // RegReg(Many) | |
| 1991 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 1992 %} | |
| 1993 | |
| 1994 enc_class RegReg_Hi2(eRegL dst, eRegL src) %{ // RegReg(Many) | |
| 1995 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg)); | |
| 1996 %} | |
| 1997 | |
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1998 enc_class RegReg_HiLo( eRegL src, rRegI dst ) %{ |
| 0 | 1999 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($src$$reg)); |
| 2000 %} | |
| 2001 | |
| 2002 enc_class Con32 (immI src) %{ // Con32(storeImmI) | |
| 2003 // Output immediate | |
| 2004 $$$emit32$src$$constant; | |
| 2005 %} | |
| 2006 | |
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2007 enc_class Con32FPR_as_bits(immFPR src) %{ // storeF_imm |
| 0 | 2008 // Output Float immediate bits |
| 2009 jfloat jf = $src$$constant; | |
| 2010 int jf_as_bits = jint_cast( jf ); | |
| 2011 emit_d32(cbuf, jf_as_bits); | |
| 2012 %} | |
| 2013 | |
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2014 enc_class Con32F_as_bits(immF src) %{ // storeX_imm |
| 0 | 2015 // Output Float immediate bits |
| 2016 jfloat jf = $src$$constant; | |
| 2017 int jf_as_bits = jint_cast( jf ); | |
| 2018 emit_d32(cbuf, jf_as_bits); | |
| 2019 %} | |
| 2020 | |
| 2021 enc_class Con16 (immI src) %{ // Con16(storeImmI) | |
| 2022 // Output immediate | |
| 2023 $$$emit16$src$$constant; | |
| 2024 %} | |
| 2025 | |
| 2026 enc_class Con_d32(immI src) %{ | |
| 2027 emit_d32(cbuf,$src$$constant); | |
| 2028 %} | |
| 2029 | |
| 2030 enc_class conmemref (eRegP t1) %{ // Con32(storeImmI) | |
| 2031 // Output immediate memory reference | |
| 2032 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 ); | |
| 2033 emit_d32(cbuf, 0x00); | |
| 2034 %} | |
| 2035 | |
| 2036 enc_class lock_prefix( ) %{ | |
| 2037 if( os::is_MP() ) | |
| 2038 emit_opcode(cbuf,0xF0); // [Lock] | |
| 2039 %} | |
| 2040 | |
| 2041 // Cmp-xchg long value. | |
| 2042 // Note: we need to swap rbx, and rcx before and after the | |
| 2043 // cmpxchg8 instruction because the instruction uses | |
| 2044 // rcx as the high order word of the new value to store but | |
| 2045 // our register encoding uses rbx,. | |
| 2046 enc_class enc_cmpxchg8(eSIRegP mem_ptr) %{ | |
| 2047 | |
| 2048 // XCHG rbx,ecx | |
| 2049 emit_opcode(cbuf,0x87); | |
| 2050 emit_opcode(cbuf,0xD9); | |
| 2051 // [Lock] | |
| 2052 if( os::is_MP() ) | |
| 2053 emit_opcode(cbuf,0xF0); | |
| 2054 // CMPXCHG8 [Eptr] | |
| 2055 emit_opcode(cbuf,0x0F); | |
| 2056 emit_opcode(cbuf,0xC7); | |
| 2057 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg ); | |
| 2058 // XCHG rbx,ecx | |
| 2059 emit_opcode(cbuf,0x87); | |
| 2060 emit_opcode(cbuf,0xD9); | |
| 2061 %} | |
| 2062 | |
| 2063 enc_class enc_cmpxchg(eSIRegP mem_ptr) %{ | |
| 2064 // [Lock] | |
| 2065 if( os::is_MP() ) | |
| 2066 emit_opcode(cbuf,0xF0); | |
| 2067 | |
| 2068 // CMPXCHG [Eptr] | |
| 2069 emit_opcode(cbuf,0x0F); | |
| 2070 emit_opcode(cbuf,0xB1); | |
| 2071 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg ); | |
| 2072 %} | |
| 2073 | |
| 2074 enc_class enc_flags_ne_to_boolean( iRegI res ) %{ | |
| 2075 int res_encoding = $res$$reg; | |
| 2076 | |
| 2077 // MOV res,0 | |
| 2078 emit_opcode( cbuf, 0xB8 + res_encoding); | |
| 2079 emit_d32( cbuf, 0 ); | |
| 2080 // JNE,s fail | |
| 2081 emit_opcode(cbuf,0x75); | |
| 2082 emit_d8(cbuf, 5 ); | |
| 2083 // MOV res,1 | |
| 2084 emit_opcode( cbuf, 0xB8 + res_encoding); | |
| 2085 emit_d32( cbuf, 1 ); | |
| 2086 // fail: | |
| 2087 %} | |
| 2088 | |
| 2089 enc_class set_instruction_start( ) %{ | |
| 1748 | 2090 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand |
| 0 | 2091 %} |
| 2092 | |
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2093 enc_class RegMem (rRegI ereg, memory mem) %{ // emit_reg_mem |
| 0 | 2094 int reg_encoding = $ereg$$reg; |
| 2095 int base = $mem$$base; | |
| 2096 int index = $mem$$index; | |
| 2097 int scale = $mem$$scale; | |
| 2098 int displace = $mem$$disp; | |
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2099 relocInfo::relocType disp_reloc = $mem->disp_reloc(); |
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2100 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc); |
| 0 | 2101 %} |
| 2102 | |
| 2103 enc_class RegMem_Hi(eRegL ereg, memory mem) %{ // emit_reg_mem | |
| 2104 int reg_encoding = HIGH_FROM_LOW($ereg$$reg); // Hi register of pair, computed from lo | |
| 2105 int base = $mem$$base; | |
| 2106 int index = $mem$$index; | |
| 2107 int scale = $mem$$scale; | |
| 2108 int displace = $mem$$disp + 4; // Offset is 4 further in memory | |
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2109 assert( $mem->disp_reloc() == relocInfo::none, "Cannot add 4 to oop" ); |
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2110 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, relocInfo::none); |
| 0 | 2111 %} |
| 2112 | |
| 2113 enc_class move_long_small_shift( eRegL dst, immI_1_31 cnt ) %{ | |
| 2114 int r1, r2; | |
| 2115 if( $tertiary == 0xA4 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); } | |
| 2116 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); } | |
| 2117 emit_opcode(cbuf,0x0F); | |
| 2118 emit_opcode(cbuf,$tertiary); | |
| 2119 emit_rm(cbuf, 0x3, r1, r2); | |
| 2120 emit_d8(cbuf,$cnt$$constant); | |
| 2121 emit_d8(cbuf,$primary); | |
| 2122 emit_rm(cbuf, 0x3, $secondary, r1); | |
| 2123 emit_d8(cbuf,$cnt$$constant); | |
| 2124 %} | |
| 2125 | |
| 2126 enc_class move_long_big_shift_sign( eRegL dst, immI_32_63 cnt ) %{ | |
| 2127 emit_opcode( cbuf, 0x8B ); // Move | |
| 2128 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg)); | |
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2129 if( $cnt$$constant > 32 ) { // Shift, if not by zero |
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2130 emit_d8(cbuf,$primary); |
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2131 emit_rm(cbuf, 0x3, $secondary, $dst$$reg); |
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2132 emit_d8(cbuf,$cnt$$constant-32); |
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2133 } |
| 0 | 2134 emit_d8(cbuf,$primary); |
| 2135 emit_rm(cbuf, 0x3, $secondary, HIGH_FROM_LOW($dst$$reg)); | |
| 2136 emit_d8(cbuf,31); | |
| 2137 %} | |
| 2138 | |
| 2139 enc_class move_long_big_shift_clr( eRegL dst, immI_32_63 cnt ) %{ | |
| 2140 int r1, r2; | |
| 2141 if( $secondary == 0x5 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); } | |
| 2142 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); } | |
| 2143 | |
| 2144 emit_opcode( cbuf, 0x8B ); // Move r1,r2 | |
| 2145 emit_rm(cbuf, 0x3, r1, r2); | |
| 2146 if( $cnt$$constant > 32 ) { // Shift, if not by zero | |
| 2147 emit_opcode(cbuf,$primary); | |
| 2148 emit_rm(cbuf, 0x3, $secondary, r1); | |
| 2149 emit_d8(cbuf,$cnt$$constant-32); | |
| 2150 } | |
| 2151 emit_opcode(cbuf,0x33); // XOR r2,r2 | |
| 2152 emit_rm(cbuf, 0x3, r2, r2); | |
| 2153 %} | |
| 2154 | |
| 2155 // Clone of RegMem but accepts an extra parameter to access each | |
| 2156 // half of a double in memory; it never needs relocation info. | |
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2157 enc_class Mov_MemD_half_to_Reg (immI opcode, memory mem, immI disp_for_half, rRegI rm_reg) %{ |
| 0 | 2158 emit_opcode(cbuf,$opcode$$constant); |
| 2159 int reg_encoding = $rm_reg$$reg; | |
| 2160 int base = $mem$$base; | |
| 2161 int index = $mem$$index; | |
| 2162 int scale = $mem$$scale; | |
| 2163 int displace = $mem$$disp + $disp_for_half$$constant; | |
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2164 relocInfo::relocType disp_reloc = relocInfo::none; |
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2165 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc); |
| 0 | 2166 %} |
| 2167 | |
| 2168 // !!!!! Special Custom Code used by MemMove, and stack access instructions !!!!! | |
| 2169 // | |
| 2170 // Clone of RegMem except the RM-byte's reg/opcode field is an ADLC-time constant | |
| 2171 // and it never needs relocation information. | |
| 2172 // Frequently used to move data between FPU's Stack Top and memory. | |
| 2173 enc_class RMopc_Mem_no_oop (immI rm_opcode, memory mem) %{ | |
| 2174 int rm_byte_opcode = $rm_opcode$$constant; | |
| 2175 int base = $mem$$base; | |
| 2176 int index = $mem$$index; | |
| 2177 int scale = $mem$$scale; | |
| 2178 int displace = $mem$$disp; | |
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2179 assert( $mem->disp_reloc() == relocInfo::none, "No oops here because no reloc info allowed" ); |
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2180 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, relocInfo::none); |
| 0 | 2181 %} |
| 2182 | |
| 2183 enc_class RMopc_Mem (immI rm_opcode, memory mem) %{ | |
| 2184 int rm_byte_opcode = $rm_opcode$$constant; | |
| 2185 int base = $mem$$base; | |
| 2186 int index = $mem$$index; | |
| 2187 int scale = $mem$$scale; | |
| 2188 int displace = $mem$$disp; | |
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2189 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals |
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2190 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc); |
| 0 | 2191 %} |
| 2192 | |
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2193 enc_class RegLea (rRegI dst, rRegI src0, immI src1 ) %{ // emit_reg_lea |
| 0 | 2194 int reg_encoding = $dst$$reg; |
| 2195 int base = $src0$$reg; // 0xFFFFFFFF indicates no base | |
| 2196 int index = 0x04; // 0x04 indicates no index | |
| 2197 int scale = 0x00; // 0x00 indicates no scale | |
| 2198 int displace = $src1$$constant; // 0x00 indicates no displacement | |
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2199 relocInfo::relocType disp_reloc = relocInfo::none; |
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2200 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc); |
| 0 | 2201 %} |
| 2202 | |
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2203 enc_class min_enc (rRegI dst, rRegI src) %{ // MIN |
| 0 | 2204 // Compare dst,src |
| 2205 emit_opcode(cbuf,0x3B); | |
| 2206 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 2207 // jmp dst < src around move | |
| 2208 emit_opcode(cbuf,0x7C); | |
| 2209 emit_d8(cbuf,2); | |
| 2210 // move dst,src | |
| 2211 emit_opcode(cbuf,0x8B); | |
| 2212 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 2213 %} | |
| 2214 | |
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2215 enc_class max_enc (rRegI dst, rRegI src) %{ // MAX |
| 0 | 2216 // Compare dst,src |
| 2217 emit_opcode(cbuf,0x3B); | |
| 2218 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 2219 // jmp dst > src around move | |
| 2220 emit_opcode(cbuf,0x7F); | |
| 2221 emit_d8(cbuf,2); | |
| 2222 // move dst,src | |
| 2223 emit_opcode(cbuf,0x8B); | |
| 2224 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 2225 %} | |
| 2226 | |
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2227 enc_class enc_FPR_store(memory mem, regDPR src) %{ |
| 0 | 2228 // If src is FPR1, we can just FST to store it. |
| 2229 // Else we need to FLD it to FPR1, then FSTP to store/pop it. | |
| 2230 int reg_encoding = 0x2; // Just store | |
| 2231 int base = $mem$$base; | |
| 2232 int index = $mem$$index; | |
| 2233 int scale = $mem$$scale; | |
| 2234 int displace = $mem$$disp; | |
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2235 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals |
| 0 | 2236 if( $src$$reg != FPR1L_enc ) { |
| 2237 reg_encoding = 0x3; // Store & pop | |
| 2238 emit_opcode( cbuf, 0xD9 ); // FLD (i.e., push it) | |
| 2239 emit_d8( cbuf, 0xC0-1+$src$$reg ); | |
| 2240 } | |
| 1748 | 2241 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand |
| 0 | 2242 emit_opcode(cbuf,$primary); |
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2243 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc); |
| 0 | 2244 %} |
| 2245 | |
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2246 enc_class neg_reg(rRegI dst) %{ |
| 0 | 2247 // NEG $dst |
| 2248 emit_opcode(cbuf,0xF7); | |
| 2249 emit_rm(cbuf, 0x3, 0x03, $dst$$reg ); | |
| 2250 %} | |
| 2251 | |
| 2252 enc_class setLT_reg(eCXRegI dst) %{ | |
| 2253 // SETLT $dst | |
| 2254 emit_opcode(cbuf,0x0F); | |
| 2255 emit_opcode(cbuf,0x9C); | |
| 2256 emit_rm( cbuf, 0x3, 0x4, $dst$$reg ); | |
| 2257 %} | |
| 2258 | |
| 2259 enc_class enc_cmpLTP(ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp) %{ // cadd_cmpLT | |
| 2260 int tmpReg = $tmp$$reg; | |
| 2261 | |
| 2262 // SUB $p,$q | |
| 2263 emit_opcode(cbuf,0x2B); | |
| 2264 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg); | |
| 2265 // SBB $tmp,$tmp | |
| 2266 emit_opcode(cbuf,0x1B); | |
| 2267 emit_rm(cbuf, 0x3, tmpReg, tmpReg); | |
| 2268 // AND $tmp,$y | |
| 2269 emit_opcode(cbuf,0x23); | |
| 2270 emit_rm(cbuf, 0x3, tmpReg, $y$$reg); | |
| 2271 // ADD $p,$tmp | |
| 2272 emit_opcode(cbuf,0x03); | |
| 2273 emit_rm(cbuf, 0x3, $p$$reg, tmpReg); | |
| 2274 %} | |
| 2275 | |
| 2276 enc_class shift_left_long( eRegL dst, eCXRegI shift ) %{ | |
| 2277 // TEST shift,32 | |
| 2278 emit_opcode(cbuf,0xF7); | |
| 2279 emit_rm(cbuf, 0x3, 0, ECX_enc); | |
| 2280 emit_d32(cbuf,0x20); | |
| 2281 // JEQ,s small | |
| 2282 emit_opcode(cbuf, 0x74); | |
| 2283 emit_d8(cbuf, 0x04); | |
| 2284 // MOV $dst.hi,$dst.lo | |
| 2285 emit_opcode( cbuf, 0x8B ); | |
| 2286 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg ); | |
| 2287 // CLR $dst.lo | |
| 2288 emit_opcode(cbuf, 0x33); | |
| 2289 emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg); | |
| 2290 // small: | |
| 2291 // SHLD $dst.hi,$dst.lo,$shift | |
| 2292 emit_opcode(cbuf,0x0F); | |
| 2293 emit_opcode(cbuf,0xA5); | |
| 2294 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg)); | |
| 2295 // SHL $dst.lo,$shift" | |
| 2296 emit_opcode(cbuf,0xD3); | |
| 2297 emit_rm(cbuf, 0x3, 0x4, $dst$$reg ); | |
| 2298 %} | |
| 2299 | |
| 2300 enc_class shift_right_long( eRegL dst, eCXRegI shift ) %{ | |
| 2301 // TEST shift,32 | |
| 2302 emit_opcode(cbuf,0xF7); | |
| 2303 emit_rm(cbuf, 0x3, 0, ECX_enc); | |
| 2304 emit_d32(cbuf,0x20); | |
| 2305 // JEQ,s small | |
| 2306 emit_opcode(cbuf, 0x74); | |
| 2307 emit_d8(cbuf, 0x04); | |
| 2308 // MOV $dst.lo,$dst.hi | |
| 2309 emit_opcode( cbuf, 0x8B ); | |
| 2310 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) ); | |
| 2311 // CLR $dst.hi | |
| 2312 emit_opcode(cbuf, 0x33); | |
| 2313 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($dst$$reg)); | |
| 2314 // small: | |
| 2315 // SHRD $dst.lo,$dst.hi,$shift | |
| 2316 emit_opcode(cbuf,0x0F); | |
| 2317 emit_opcode(cbuf,0xAD); | |
| 2318 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg); | |
| 2319 // SHR $dst.hi,$shift" | |
| 2320 emit_opcode(cbuf,0xD3); | |
| 2321 emit_rm(cbuf, 0x3, 0x5, HIGH_FROM_LOW($dst$$reg) ); | |
| 2322 %} | |
| 2323 | |
| 2324 enc_class shift_right_arith_long( eRegL dst, eCXRegI shift ) %{ | |
| 2325 // TEST shift,32 | |
| 2326 emit_opcode(cbuf,0xF7); | |
| 2327 emit_rm(cbuf, 0x3, 0, ECX_enc); | |
| 2328 emit_d32(cbuf,0x20); | |
| 2329 // JEQ,s small | |
| 2330 emit_opcode(cbuf, 0x74); | |
| 2331 emit_d8(cbuf, 0x05); | |
| 2332 // MOV $dst.lo,$dst.hi | |
| 2333 emit_opcode( cbuf, 0x8B ); | |
| 2334 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) ); | |
| 2335 // SAR $dst.hi,31 | |
| 2336 emit_opcode(cbuf, 0xC1); | |
| 2337 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW($dst$$reg) ); | |
| 2338 emit_d8(cbuf, 0x1F ); | |
| 2339 // small: | |
| 2340 // SHRD $dst.lo,$dst.hi,$shift | |
| 2341 emit_opcode(cbuf,0x0F); | |
| 2342 emit_opcode(cbuf,0xAD); | |
| 2343 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg); | |
| 2344 // SAR $dst.hi,$shift" | |
| 2345 emit_opcode(cbuf,0xD3); | |
| 2346 emit_rm(cbuf, 0x3, 0x7, HIGH_FROM_LOW($dst$$reg) ); | |
| 2347 %} | |
| 2348 | |
| 2349 | |
| 2350 // ----------------- Encodings for floating point unit ----------------- | |
| 2351 // May leave result in FPU-TOS or FPU reg depending on opcodes | |
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2352 enc_class OpcReg_FPR(regFPR src) %{ // FMUL, FDIV |
| 0 | 2353 $$$emit8$primary; |
| 2354 emit_rm(cbuf, 0x3, $secondary, $src$$reg ); | |
| 2355 %} | |
| 2356 | |
| 2357 // Pop argument in FPR0 with FSTP ST(0) | |
| 2358 enc_class PopFPU() %{ | |
| 2359 emit_opcode( cbuf, 0xDD ); | |
| 2360 emit_d8( cbuf, 0xD8 ); | |
| 2361 %} | |
| 2362 | |
| 2363 // !!!!! equivalent to Pop_Reg_F | |
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2364 enc_class Pop_Reg_DPR( regDPR dst ) %{ |
| 0 | 2365 emit_opcode( cbuf, 0xDD ); // FSTP ST(i) |
| 2366 emit_d8( cbuf, 0xD8+$dst$$reg ); | |
| 2367 %} | |
| 2368 | |
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2369 enc_class Push_Reg_DPR( regDPR dst ) %{ |
| 0 | 2370 emit_opcode( cbuf, 0xD9 ); |
| 2371 emit_d8( cbuf, 0xC0-1+$dst$$reg ); // FLD ST(i-1) | |
| 2372 %} | |
| 2373 | |
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2374 enc_class strictfp_bias1( regDPR dst ) %{ |
| 0 | 2375 emit_opcode( cbuf, 0xDB ); // FLD m80real |
| 2376 emit_opcode( cbuf, 0x2D ); | |
| 2377 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias1() ); | |
| 2378 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0 | |
| 2379 emit_opcode( cbuf, 0xC8+$dst$$reg ); | |
| 2380 %} | |
| 2381 | |
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2382 enc_class strictfp_bias2( regDPR dst ) %{ |
| 0 | 2383 emit_opcode( cbuf, 0xDB ); // FLD m80real |
| 2384 emit_opcode( cbuf, 0x2D ); | |
| 2385 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias2() ); | |
| 2386 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0 | |
| 2387 emit_opcode( cbuf, 0xC8+$dst$$reg ); | |
| 2388 %} | |
| 2389 | |
| 2390 // Special case for moving an integer register to a stack slot. | |
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2391 enc_class OpcPRegSS( stackSlotI dst, rRegI src ) %{ // RegSS |
| 0 | 2392 store_to_stackslot( cbuf, $primary, $src$$reg, $dst$$disp ); |
| 2393 %} | |
| 2394 | |
| 2395 // Special case for moving a register to a stack slot. | |
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2396 enc_class RegSS( stackSlotI dst, rRegI src ) %{ // RegSS |
| 0 | 2397 // Opcode already emitted |
| 2398 emit_rm( cbuf, 0x02, $src$$reg, ESP_enc ); // R/M byte | |
| 2399 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte | |
| 2400 emit_d32(cbuf, $dst$$disp); // Displacement | |
| 2401 %} | |
| 2402 | |
| 2403 // Push the integer in stackSlot 'src' onto FP-stack | |
| 2404 enc_class Push_Mem_I( memory src ) %{ // FILD [ESP+src] | |
| 2405 store_to_stackslot( cbuf, $primary, $secondary, $src$$disp ); | |
| 2406 %} | |
| 2407 | |
| 2408 // Push FPU's TOS float to a stack-slot, and pop FPU-stack | |
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2409 enc_class Pop_Mem_FPR( stackSlotF dst ) %{ // FSTP_S [ESP+dst] |
| 0 | 2410 store_to_stackslot( cbuf, 0xD9, 0x03, $dst$$disp ); |
| 2411 %} | |
| 2412 | |
| 2413 // Same as Pop_Mem_F except for opcode | |
| 2414 // Push FPU's TOS double to a stack-slot, and pop FPU-stack | |
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2415 enc_class Pop_Mem_DPR( stackSlotD dst ) %{ // FSTP_D [ESP+dst] |
| 0 | 2416 store_to_stackslot( cbuf, 0xDD, 0x03, $dst$$disp ); |
| 2417 %} | |
| 2418 | |
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2419 enc_class Pop_Reg_FPR( regFPR dst ) %{ |
| 0 | 2420 emit_opcode( cbuf, 0xDD ); // FSTP ST(i) |
| 2421 emit_d8( cbuf, 0xD8+$dst$$reg ); | |
| 2422 %} | |
| 2423 | |
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2424 enc_class Push_Reg_FPR( regFPR dst ) %{ |
| 0 | 2425 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1) |
| 2426 emit_d8( cbuf, 0xC0-1+$dst$$reg ); | |
| 2427 %} | |
| 2428 | |
| 2429 // Push FPU's float to a stack-slot, and pop FPU-stack | |
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2430 enc_class Pop_Mem_Reg_FPR( stackSlotF dst, regFPR src ) %{ |
| 0 | 2431 int pop = 0x02; |
| 2432 if ($src$$reg != FPR1L_enc) { | |
| 2433 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1) | |
| 2434 emit_d8( cbuf, 0xC0-1+$src$$reg ); | |
| 2435 pop = 0x03; | |
| 2436 } | |
| 2437 store_to_stackslot( cbuf, 0xD9, pop, $dst$$disp ); // FST<P>_S [ESP+dst] | |
| 2438 %} | |
| 2439 | |
| 2440 // Push FPU's double to a stack-slot, and pop FPU-stack | |
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2441 enc_class Pop_Mem_Reg_DPR( stackSlotD dst, regDPR src ) %{ |
| 0 | 2442 int pop = 0x02; |
| 2443 if ($src$$reg != FPR1L_enc) { | |
| 2444 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1) | |
| 2445 emit_d8( cbuf, 0xC0-1+$src$$reg ); | |
| 2446 pop = 0x03; | |
| 2447 } | |
| 2448 store_to_stackslot( cbuf, 0xDD, pop, $dst$$disp ); // FST<P>_D [ESP+dst] | |
| 2449 %} | |
| 2450 | |
| 2451 // Push FPU's double to a FPU-stack-slot, and pop FPU-stack | |
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2452 enc_class Pop_Reg_Reg_DPR( regDPR dst, regFPR src ) %{ |
| 0 | 2453 int pop = 0xD0 - 1; // -1 since we skip FLD |
| 2454 if ($src$$reg != FPR1L_enc) { | |
| 2455 emit_opcode( cbuf, 0xD9 ); // FLD ST(src-1) | |
| 2456 emit_d8( cbuf, 0xC0-1+$src$$reg ); | |
| 2457 pop = 0xD8; | |
| 2458 } | |
| 2459 emit_opcode( cbuf, 0xDD ); | |
| 2460 emit_d8( cbuf, pop+$dst$$reg ); // FST<P> ST(i) | |
| 2461 %} | |
| 2462 | |
| 2463 | |
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2464 enc_class Push_Reg_Mod_DPR( regDPR dst, regDPR src) %{ |
| 0 | 2465 // load dst in FPR0 |
| 2466 emit_opcode( cbuf, 0xD9 ); | |
| 2467 emit_d8( cbuf, 0xC0-1+$dst$$reg ); | |
| 2468 if ($src$$reg != FPR1L_enc) { | |
| 2469 // fincstp | |
| 2470 emit_opcode (cbuf, 0xD9); | |
| 2471 emit_opcode (cbuf, 0xF7); | |
| 2472 // swap src with FPR1: | |
| 2473 // FXCH FPR1 with src | |
| 2474 emit_opcode(cbuf, 0xD9); | |
| 2475 emit_d8(cbuf, 0xC8-1+$src$$reg ); | |
| 2476 // fdecstp | |
| 2477 emit_opcode (cbuf, 0xD9); | |
| 2478 emit_opcode (cbuf, 0xF6); | |
| 2479 } | |
| 2480 %} | |
| 2481 | |
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2482 enc_class Push_ModD_encoding(regD src0, regD src1) %{ |
| 4759 | 2483 MacroAssembler _masm(&cbuf); |
| 2484 __ subptr(rsp, 8); | |
| 2485 __ movdbl(Address(rsp, 0), $src1$$XMMRegister); | |
| 2486 __ fld_d(Address(rsp, 0)); | |
| 2487 __ movdbl(Address(rsp, 0), $src0$$XMMRegister); | |
| 2488 __ fld_d(Address(rsp, 0)); | |
| 2489 %} | |
| 2490 | |
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2491 enc_class Push_ModF_encoding(regF src0, regF src1) %{ |
| 4759 | 2492 MacroAssembler _masm(&cbuf); |
| 2493 __ subptr(rsp, 4); | |
| 2494 __ movflt(Address(rsp, 0), $src1$$XMMRegister); | |
| 2495 __ fld_s(Address(rsp, 0)); | |
| 2496 __ movflt(Address(rsp, 0), $src0$$XMMRegister); | |
| 2497 __ fld_s(Address(rsp, 0)); | |
| 0 | 2498 %} |
| 2499 | |
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2500 enc_class Push_ResultD(regD dst) %{ |
| 4759 | 2501 MacroAssembler _masm(&cbuf); |
| 2502 __ fstp_d(Address(rsp, 0)); | |
| 2503 __ movdbl($dst$$XMMRegister, Address(rsp, 0)); | |
| 2504 __ addptr(rsp, 8); | |
| 0 | 2505 %} |
| 2506 | |
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2507 enc_class Push_ResultF(regF dst, immI d8) %{ |
| 4759 | 2508 MacroAssembler _masm(&cbuf); |
| 2509 __ fstp_s(Address(rsp, 0)); | |
| 2510 __ movflt($dst$$XMMRegister, Address(rsp, 0)); | |
| 2511 __ addptr(rsp, $d8$$constant); | |
| 0 | 2512 %} |
| 2513 | |
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2514 enc_class Push_SrcD(regD src) %{ |
| 4759 | 2515 MacroAssembler _masm(&cbuf); |
| 2516 __ subptr(rsp, 8); | |
| 2517 __ movdbl(Address(rsp, 0), $src$$XMMRegister); | |
| 2518 __ fld_d(Address(rsp, 0)); | |
| 0 | 2519 %} |
| 2520 | |
| 2521 enc_class push_stack_temp_qword() %{ | |
| 4759 | 2522 MacroAssembler _masm(&cbuf); |
| 2523 __ subptr(rsp, 8); | |
| 0 | 2524 %} |
| 2525 | |
| 2526 enc_class pop_stack_temp_qword() %{ | |
| 4759 | 2527 MacroAssembler _masm(&cbuf); |
| 2528 __ addptr(rsp, 8); | |
| 2529 %} | |
| 2530 | |
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2531 enc_class push_xmm_to_fpr1(regD src) %{ |
| 4759 | 2532 MacroAssembler _masm(&cbuf); |
| 2533 __ movdbl(Address(rsp, 0), $src$$XMMRegister); | |
| 2534 __ fld_d(Address(rsp, 0)); | |
| 0 | 2535 %} |
| 2536 | |
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2537 enc_class Push_Result_Mod_DPR( regDPR src) %{ |
| 0 | 2538 if ($src$$reg != FPR1L_enc) { |
| 2539 // fincstp | |
| 2540 emit_opcode (cbuf, 0xD9); | |
| 2541 emit_opcode (cbuf, 0xF7); | |
| 2542 // FXCH FPR1 with src | |
| 2543 emit_opcode(cbuf, 0xD9); | |
| 2544 emit_d8(cbuf, 0xC8-1+$src$$reg ); | |
| 2545 // fdecstp | |
| 2546 emit_opcode (cbuf, 0xD9); | |
| 2547 emit_opcode (cbuf, 0xF6); | |
| 2548 } | |
| 2549 // // following asm replaced with Pop_Reg_F or Pop_Mem_F | |
| 2550 // // FSTP FPR$dst$$reg | |
| 2551 // emit_opcode( cbuf, 0xDD ); | |
| 2552 // emit_d8( cbuf, 0xD8+$dst$$reg ); | |
| 2553 %} | |
| 2554 | |
| 2555 enc_class fnstsw_sahf_skip_parity() %{ | |
| 2556 // fnstsw ax | |
| 2557 emit_opcode( cbuf, 0xDF ); | |
| 2558 emit_opcode( cbuf, 0xE0 ); | |
| 2559 // sahf | |
| 2560 emit_opcode( cbuf, 0x9E ); | |
| 2561 // jnp ::skip | |
| 2562 emit_opcode( cbuf, 0x7B ); | |
| 2563 emit_opcode( cbuf, 0x05 ); | |
| 2564 %} | |
| 2565 | |
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2566 enc_class emitModDPR() %{ |
| 0 | 2567 // fprem must be iterative |
| 2568 // :: loop | |
| 2569 // fprem | |
| 2570 emit_opcode( cbuf, 0xD9 ); | |
| 2571 emit_opcode( cbuf, 0xF8 ); | |
| 2572 // wait | |
| 2573 emit_opcode( cbuf, 0x9b ); | |
| 2574 // fnstsw ax | |
| 2575 emit_opcode( cbuf, 0xDF ); | |
| 2576 emit_opcode( cbuf, 0xE0 ); | |
| 2577 // sahf | |
| 2578 emit_opcode( cbuf, 0x9E ); | |
| 2579 // jp ::loop | |
| 2580 emit_opcode( cbuf, 0x0F ); | |
| 2581 emit_opcode( cbuf, 0x8A ); | |
| 2582 emit_opcode( cbuf, 0xF4 ); | |
| 2583 emit_opcode( cbuf, 0xFF ); | |
| 2584 emit_opcode( cbuf, 0xFF ); | |
| 2585 emit_opcode( cbuf, 0xFF ); | |
| 2586 %} | |
| 2587 | |
| 2588 enc_class fpu_flags() %{ | |
| 2589 // fnstsw_ax | |
| 2590 emit_opcode( cbuf, 0xDF); | |
| 2591 emit_opcode( cbuf, 0xE0); | |
| 2592 // test ax,0x0400 | |
| 2593 emit_opcode( cbuf, 0x66 ); // operand-size prefix for 16-bit immediate | |
| 2594 emit_opcode( cbuf, 0xA9 ); | |
| 2595 emit_d16 ( cbuf, 0x0400 ); | |
| 2596 // // // This sequence works, but stalls for 12-16 cycles on PPro | |
| 2597 // // test rax,0x0400 | |
| 2598 // emit_opcode( cbuf, 0xA9 ); | |
| 2599 // emit_d32 ( cbuf, 0x00000400 ); | |
| 2600 // | |
| 2601 // jz exit (no unordered comparison) | |
| 2602 emit_opcode( cbuf, 0x74 ); | |
| 2603 emit_d8 ( cbuf, 0x02 ); | |
| 2604 // mov ah,1 - treat as LT case (set carry flag) | |
| 2605 emit_opcode( cbuf, 0xB4 ); | |
| 2606 emit_d8 ( cbuf, 0x01 ); | |
| 2607 // sahf | |
| 2608 emit_opcode( cbuf, 0x9E); | |
| 2609 %} | |
| 2610 | |
| 2611 enc_class cmpF_P6_fixup() %{ | |
| 2612 // Fixup the integer flags in case comparison involved a NaN | |
| 2613 // | |
| 2614 // JNP exit (no unordered comparison, P-flag is set by NaN) | |
| 2615 emit_opcode( cbuf, 0x7B ); | |
| 2616 emit_d8 ( cbuf, 0x03 ); | |
| 2617 // MOV AH,1 - treat as LT case (set carry flag) | |
| 2618 emit_opcode( cbuf, 0xB4 ); | |
| 2619 emit_d8 ( cbuf, 0x01 ); | |
| 2620 // SAHF | |
| 2621 emit_opcode( cbuf, 0x9E); | |
| 2622 // NOP // target for branch to avoid branch to branch | |
| 2623 emit_opcode( cbuf, 0x90); | |
| 2624 %} | |
| 2625 | |
| 2626 // fnstsw_ax(); | |
| 2627 // sahf(); | |
| 2628 // movl(dst, nan_result); | |
| 2629 // jcc(Assembler::parity, exit); | |
| 2630 // movl(dst, less_result); | |
| 2631 // jcc(Assembler::below, exit); | |
| 2632 // movl(dst, equal_result); | |
| 2633 // jcc(Assembler::equal, exit); | |
| 2634 // movl(dst, greater_result); | |
| 2635 | |
| 2636 // less_result = 1; | |
| 2637 // greater_result = -1; | |
| 2638 // equal_result = 0; | |
| 2639 // nan_result = -1; | |
| 2640 | |
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2641 enc_class CmpF_Result(rRegI dst) %{ |
| 0 | 2642 // fnstsw_ax(); |
| 2643 emit_opcode( cbuf, 0xDF); | |
| 2644 emit_opcode( cbuf, 0xE0); | |
| 2645 // sahf | |
| 2646 emit_opcode( cbuf, 0x9E); | |
| 2647 // movl(dst, nan_result); | |
| 2648 emit_opcode( cbuf, 0xB8 + $dst$$reg); | |
| 2649 emit_d32( cbuf, -1 ); | |
| 2650 // jcc(Assembler::parity, exit); | |
| 2651 emit_opcode( cbuf, 0x7A ); | |
| 2652 emit_d8 ( cbuf, 0x13 ); | |
| 2653 // movl(dst, less_result); | |
| 2654 emit_opcode( cbuf, 0xB8 + $dst$$reg); | |
| 2655 emit_d32( cbuf, -1 ); | |
| 2656 // jcc(Assembler::below, exit); | |
| 2657 emit_opcode( cbuf, 0x72 ); | |
| 2658 emit_d8 ( cbuf, 0x0C ); | |
| 2659 // movl(dst, equal_result); | |
| 2660 emit_opcode( cbuf, 0xB8 + $dst$$reg); | |
| 2661 emit_d32( cbuf, 0 ); | |
| 2662 // jcc(Assembler::equal, exit); | |
| 2663 emit_opcode( cbuf, 0x74 ); | |
| 2664 emit_d8 ( cbuf, 0x05 ); | |
| 2665 // movl(dst, greater_result); | |
| 2666 emit_opcode( cbuf, 0xB8 + $dst$$reg); | |
| 2667 emit_d32( cbuf, 1 ); | |
| 2668 %} | |
| 2669 | |
| 2670 | |
| 2671 // Compare the longs and set flags | |
| 2672 // BROKEN! Do Not use as-is | |
| 2673 enc_class cmpl_test( eRegL src1, eRegL src2 ) %{ | |
| 2674 // CMP $src1.hi,$src2.hi | |
| 2675 emit_opcode( cbuf, 0x3B ); | |
| 2676 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) ); | |
| 2677 // JNE,s done | |
| 2678 emit_opcode(cbuf,0x75); | |
| 2679 emit_d8(cbuf, 2 ); | |
| 2680 // CMP $src1.lo,$src2.lo | |
| 2681 emit_opcode( cbuf, 0x3B ); | |
| 2682 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg ); | |
| 2683 // done: | |
| 2684 %} | |
| 2685 | |
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2686 enc_class convert_int_long( regL dst, rRegI src ) %{ |
| 0 | 2687 // mov $dst.lo,$src |
| 2688 int dst_encoding = $dst$$reg; | |
| 2689 int src_encoding = $src$$reg; | |
| 2690 encode_Copy( cbuf, dst_encoding , src_encoding ); | |
| 2691 // mov $dst.hi,$src | |
| 2692 encode_Copy( cbuf, HIGH_FROM_LOW(dst_encoding), src_encoding ); | |
| 2693 // sar $dst.hi,31 | |
| 2694 emit_opcode( cbuf, 0xC1 ); | |
| 2695 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW(dst_encoding) ); | |
| 2696 emit_d8(cbuf, 0x1F ); | |
| 2697 %} | |
| 2698 | |
| 2699 enc_class convert_long_double( eRegL src ) %{ | |
| 2700 // push $src.hi | |
| 2701 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg)); | |
| 2702 // push $src.lo | |
| 2703 emit_opcode(cbuf, 0x50+$src$$reg ); | |
| 2704 // fild 64-bits at [SP] | |
| 2705 emit_opcode(cbuf,0xdf); | |
| 2706 emit_d8(cbuf, 0x6C); | |
| 2707 emit_d8(cbuf, 0x24); | |
| 2708 emit_d8(cbuf, 0x00); | |
| 2709 // pop stack | |
| 2710 emit_opcode(cbuf, 0x83); // add SP, #8 | |
| 2711 emit_rm(cbuf, 0x3, 0x00, ESP_enc); | |
| 2712 emit_d8(cbuf, 0x8); | |
| 2713 %} | |
| 2714 | |
| 2715 enc_class multiply_con_and_shift_high( eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr ) %{ | |
| 2716 // IMUL EDX:EAX,$src1 | |
| 2717 emit_opcode( cbuf, 0xF7 ); | |
| 2718 emit_rm( cbuf, 0x3, 0x5, $src1$$reg ); | |
| 2719 // SAR EDX,$cnt-32 | |
| 2720 int shift_count = ((int)$cnt$$constant) - 32; | |
| 2721 if (shift_count > 0) { | |
| 2722 emit_opcode(cbuf, 0xC1); | |
| 2723 emit_rm(cbuf, 0x3, 7, $dst$$reg ); | |
| 2724 emit_d8(cbuf, shift_count); | |
| 2725 } | |
| 2726 %} | |
| 2727 | |
| 2728 // this version doesn't have add sp, 8 | |
| 2729 enc_class convert_long_double2( eRegL src ) %{ | |
| 2730 // push $src.hi | |
| 2731 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg)); | |
| 2732 // push $src.lo | |
| 2733 emit_opcode(cbuf, 0x50+$src$$reg ); | |
| 2734 // fild 64-bits at [SP] | |
| 2735 emit_opcode(cbuf,0xdf); | |
| 2736 emit_d8(cbuf, 0x6C); | |
| 2737 emit_d8(cbuf, 0x24); | |
| 2738 emit_d8(cbuf, 0x00); | |
| 2739 %} | |
| 2740 | |
| 2741 enc_class long_int_multiply( eADXRegL dst, nadxRegI src) %{ | |
| 2742 // Basic idea: long = (long)int * (long)int | |
| 2743 // IMUL EDX:EAX, src | |
| 2744 emit_opcode( cbuf, 0xF7 ); | |
| 2745 emit_rm( cbuf, 0x3, 0x5, $src$$reg); | |
| 2746 %} | |
| 2747 | |
| 2748 enc_class long_uint_multiply( eADXRegL dst, nadxRegI src) %{ | |
| 2749 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL) | |
| 2750 // MUL EDX:EAX, src | |
| 2751 emit_opcode( cbuf, 0xF7 ); | |
| 2752 emit_rm( cbuf, 0x3, 0x4, $src$$reg); | |
| 2753 %} | |
| 2754 | |
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2755 enc_class long_multiply( eADXRegL dst, eRegL src, rRegI tmp ) %{ |
| 0 | 2756 // Basic idea: lo(result) = lo(x_lo * y_lo) |
| 2757 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi) | |
| 2758 // MOV $tmp,$src.lo | |
| 2759 encode_Copy( cbuf, $tmp$$reg, $src$$reg ); | |
| 2760 // IMUL $tmp,EDX | |
| 2761 emit_opcode( cbuf, 0x0F ); | |
| 2762 emit_opcode( cbuf, 0xAF ); | |
| 2763 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) ); | |
| 2764 // MOV EDX,$src.hi | |
| 2765 encode_Copy( cbuf, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg) ); | |
| 2766 // IMUL EDX,EAX | |
| 2767 emit_opcode( cbuf, 0x0F ); | |
| 2768 emit_opcode( cbuf, 0xAF ); | |
| 2769 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg ); | |
| 2770 // ADD $tmp,EDX | |
| 2771 emit_opcode( cbuf, 0x03 ); | |
| 2772 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) ); | |
| 2773 // MUL EDX:EAX,$src.lo | |
| 2774 emit_opcode( cbuf, 0xF7 ); | |
| 2775 emit_rm( cbuf, 0x3, 0x4, $src$$reg ); | |
| 2776 // ADD EDX,ESI | |
| 2777 emit_opcode( cbuf, 0x03 ); | |
| 2778 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $tmp$$reg ); | |
| 2779 %} | |
| 2780 | |
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2781 enc_class long_multiply_con( eADXRegL dst, immL_127 src, rRegI tmp ) %{ |
| 0 | 2782 // Basic idea: lo(result) = lo(src * y_lo) |
| 2783 // hi(result) = hi(src * y_lo) + lo(src * y_hi) | |
| 2784 // IMUL $tmp,EDX,$src | |
| 2785 emit_opcode( cbuf, 0x6B ); | |
| 2786 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) ); | |
| 2787 emit_d8( cbuf, (int)$src$$constant ); | |
| 2788 // MOV EDX,$src | |
| 2789 emit_opcode(cbuf, 0xB8 + EDX_enc); | |
| 2790 emit_d32( cbuf, (int)$src$$constant ); | |
| 2791 // MUL EDX:EAX,EDX | |
| 2792 emit_opcode( cbuf, 0xF7 ); | |
| 2793 emit_rm( cbuf, 0x3, 0x4, EDX_enc ); | |
| 2794 // ADD EDX,ESI | |
| 2795 emit_opcode( cbuf, 0x03 ); | |
| 2796 emit_rm( cbuf, 0x3, EDX_enc, $tmp$$reg ); | |
| 2797 %} | |
| 2798 | |
| 2799 enc_class long_div( eRegL src1, eRegL src2 ) %{ | |
| 2800 // PUSH src1.hi | |
| 2801 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) ); | |
| 2802 // PUSH src1.lo | |
| 2803 emit_opcode(cbuf, 0x50+$src1$$reg ); | |
| 2804 // PUSH src2.hi | |
| 2805 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) ); | |
| 2806 // PUSH src2.lo | |
| 2807 emit_opcode(cbuf, 0x50+$src2$$reg ); | |
| 2808 // CALL directly to the runtime | |
| 1748 | 2809 cbuf.set_insts_mark(); |
| 0 | 2810 emit_opcode(cbuf,0xE8); // Call into runtime |
| 1748 | 2811 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::ldiv) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 0 | 2812 // Restore stack |
| 2813 emit_opcode(cbuf, 0x83); // add SP, #framesize | |
| 2814 emit_rm(cbuf, 0x3, 0x00, ESP_enc); | |
| 2815 emit_d8(cbuf, 4*4); | |
| 2816 %} | |
| 2817 | |
| 2818 enc_class long_mod( eRegL src1, eRegL src2 ) %{ | |
| 2819 // PUSH src1.hi | |
| 2820 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) ); | |
| 2821 // PUSH src1.lo | |
| 2822 emit_opcode(cbuf, 0x50+$src1$$reg ); | |
| 2823 // PUSH src2.hi | |
| 2824 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) ); | |
| 2825 // PUSH src2.lo | |
| 2826 emit_opcode(cbuf, 0x50+$src2$$reg ); | |
| 2827 // CALL directly to the runtime | |
| 1748 | 2828 cbuf.set_insts_mark(); |
| 0 | 2829 emit_opcode(cbuf,0xE8); // Call into runtime |
| 1748 | 2830 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::lrem ) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 0 | 2831 // Restore stack |
| 2832 emit_opcode(cbuf, 0x83); // add SP, #framesize | |
| 2833 emit_rm(cbuf, 0x3, 0x00, ESP_enc); | |
| 2834 emit_d8(cbuf, 4*4); | |
| 2835 %} | |
| 2836 | |
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2837 enc_class long_cmp_flags0( eRegL src, rRegI tmp ) %{ |
| 0 | 2838 // MOV $tmp,$src.lo |
| 2839 emit_opcode(cbuf, 0x8B); | |
| 2840 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg); | |
| 2841 // OR $tmp,$src.hi | |
| 2842 emit_opcode(cbuf, 0x0B); | |
| 2843 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg)); | |
| 2844 %} | |
| 2845 | |
| 2846 enc_class long_cmp_flags1( eRegL src1, eRegL src2 ) %{ | |
| 2847 // CMP $src1.lo,$src2.lo | |
| 2848 emit_opcode( cbuf, 0x3B ); | |
| 2849 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg ); | |
| 2850 // JNE,s skip | |
| 2851 emit_cc(cbuf, 0x70, 0x5); | |
| 2852 emit_d8(cbuf,2); | |
| 2853 // CMP $src1.hi,$src2.hi | |
| 2854 emit_opcode( cbuf, 0x3B ); | |
| 2855 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) ); | |
| 2856 %} | |
| 2857 | |
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2858 enc_class long_cmp_flags2( eRegL src1, eRegL src2, rRegI tmp ) %{ |
| 0 | 2859 // CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits |
| 2860 emit_opcode( cbuf, 0x3B ); | |
| 2861 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg ); | |
| 2862 // MOV $tmp,$src1.hi | |
| 2863 emit_opcode( cbuf, 0x8B ); | |
| 2864 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src1$$reg) ); | |
| 2865 // SBB $tmp,$src2.hi\t! Compute flags for long compare | |
| 2866 emit_opcode( cbuf, 0x1B ); | |
| 2867 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src2$$reg) ); | |
| 2868 %} | |
| 2869 | |
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2870 enc_class long_cmp_flags3( eRegL src, rRegI tmp ) %{ |
| 0 | 2871 // XOR $tmp,$tmp |
| 2872 emit_opcode(cbuf,0x33); // XOR | |
| 2873 emit_rm(cbuf,0x3, $tmp$$reg, $tmp$$reg); | |
| 2874 // CMP $tmp,$src.lo | |
| 2875 emit_opcode( cbuf, 0x3B ); | |
| 2876 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg ); | |
| 2877 // SBB $tmp,$src.hi | |
| 2878 emit_opcode( cbuf, 0x1B ); | |
| 2879 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg) ); | |
| 2880 %} | |
| 2881 | |
| 2882 // Sniff, sniff... smells like Gnu Superoptimizer | |
| 2883 enc_class neg_long( eRegL dst ) %{ | |
| 2884 emit_opcode(cbuf,0xF7); // NEG hi | |
| 2885 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg)); | |
| 2886 emit_opcode(cbuf,0xF7); // NEG lo | |
| 2887 emit_rm (cbuf,0x3, 0x3, $dst$$reg ); | |
| 2888 emit_opcode(cbuf,0x83); // SBB hi,0 | |
| 2889 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg)); | |
| 2890 emit_d8 (cbuf,0 ); | |
| 2891 %} | |
| 2892 | |
| 2893 enc_class enc_pop_rdx() %{ | |
| 2894 emit_opcode(cbuf,0x5A); | |
| 2895 %} | |
| 2896 | |
| 2897 enc_class enc_rethrow() %{ | |
| 1748 | 2898 cbuf.set_insts_mark(); |
| 0 | 2899 emit_opcode(cbuf, 0xE9); // jmp entry |
| 1748 | 2900 emit_d32_reloc(cbuf, (int)OptoRuntime::rethrow_stub() - ((int)cbuf.insts_end())-4, |
| 0 | 2901 runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 2902 %} | |
| 2903 | |
| 2904 | |
| 2905 // Convert a double to an int. Java semantics require we do complex | |
| 2906 // manglelations in the corner cases. So we set the rounding mode to | |
| 2907 // 'zero', store the darned double down as an int, and reset the | |
| 2908 // rounding mode to 'nearest'. The hardware throws an exception which | |
| 2909 // patches up the correct value directly to the stack. | |
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2910 enc_class DPR2I_encoding( regDPR src ) %{ |
| 0 | 2911 // Flip to round-to-zero mode. We attempted to allow invalid-op |
| 2912 // exceptions here, so that a NAN or other corner-case value will | |
| 2913 // thrown an exception (but normal values get converted at full speed). | |
| 2914 // However, I2C adapters and other float-stack manglers leave pending | |
| 2915 // invalid-op exceptions hanging. We would have to clear them before | |
| 2916 // enabling them and that is more expensive than just testing for the | |
| 2917 // invalid value Intel stores down in the corner cases. | |
| 2918 emit_opcode(cbuf,0xD9); // FLDCW trunc | |
| 2919 emit_opcode(cbuf,0x2D); | |
| 2920 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc()); | |
| 2921 // Allocate a word | |
| 2922 emit_opcode(cbuf,0x83); // SUB ESP,4 | |
| 2923 emit_opcode(cbuf,0xEC); | |
| 2924 emit_d8(cbuf,0x04); | |
| 2925 // Encoding assumes a double has been pushed into FPR0. | |
| 2926 // Store down the double as an int, popping the FPU stack | |
| 2927 emit_opcode(cbuf,0xDB); // FISTP [ESP] | |
| 2928 emit_opcode(cbuf,0x1C); | |
| 2929 emit_d8(cbuf,0x24); | |
| 2930 // Restore the rounding mode; mask the exception | |
| 2931 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode | |
| 2932 emit_opcode(cbuf,0x2D); | |
| 2933 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode() | |
| 2934 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24() | |
| 2935 : (int)StubRoutines::addr_fpu_cntrl_wrd_std()); | |
| 2936 | |
| 2937 // Load the converted int; adjust CPU stack | |
| 2938 emit_opcode(cbuf,0x58); // POP EAX | |
| 2939 emit_opcode(cbuf,0x3D); // CMP EAX,imm | |
| 2940 emit_d32 (cbuf,0x80000000); // 0x80000000 | |
| 2941 emit_opcode(cbuf,0x75); // JNE around_slow_call | |
| 2942 emit_d8 (cbuf,0x07); // Size of slow_call | |
| 2943 // Push src onto stack slow-path | |
| 2944 emit_opcode(cbuf,0xD9 ); // FLD ST(i) | |
| 2945 emit_d8 (cbuf,0xC0-1+$src$$reg ); | |
| 2946 // CALL directly to the runtime | |
| 1748 | 2947 cbuf.set_insts_mark(); |
| 0 | 2948 emit_opcode(cbuf,0xE8); // Call into runtime |
| 1748 | 2949 emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 0 | 2950 // Carry on here... |
| 2951 %} | |
| 2952 | |
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2953 enc_class DPR2L_encoding( regDPR src ) %{ |
| 0 | 2954 emit_opcode(cbuf,0xD9); // FLDCW trunc |
| 2955 emit_opcode(cbuf,0x2D); | |
| 2956 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc()); | |
| 2957 // Allocate a word | |
| 2958 emit_opcode(cbuf,0x83); // SUB ESP,8 | |
| 2959 emit_opcode(cbuf,0xEC); | |
| 2960 emit_d8(cbuf,0x08); | |
| 2961 // Encoding assumes a double has been pushed into FPR0. | |
| 2962 // Store down the double as a long, popping the FPU stack | |
| 2963 emit_opcode(cbuf,0xDF); // FISTP [ESP] | |
| 2964 emit_opcode(cbuf,0x3C); | |
| 2965 emit_d8(cbuf,0x24); | |
| 2966 // Restore the rounding mode; mask the exception | |
| 2967 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode | |
| 2968 emit_opcode(cbuf,0x2D); | |
| 2969 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode() | |
| 2970 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24() | |
| 2971 : (int)StubRoutines::addr_fpu_cntrl_wrd_std()); | |
| 2972 | |
| 2973 // Load the converted int; adjust CPU stack | |
| 2974 emit_opcode(cbuf,0x58); // POP EAX | |
| 2975 emit_opcode(cbuf,0x5A); // POP EDX | |
| 2976 emit_opcode(cbuf,0x81); // CMP EDX,imm | |
| 2977 emit_d8 (cbuf,0xFA); // rdx | |
| 2978 emit_d32 (cbuf,0x80000000); // 0x80000000 | |
| 2979 emit_opcode(cbuf,0x75); // JNE around_slow_call | |
| 2980 emit_d8 (cbuf,0x07+4); // Size of slow_call | |
| 2981 emit_opcode(cbuf,0x85); // TEST EAX,EAX | |
| 2982 emit_opcode(cbuf,0xC0); // 2/rax,/rax, | |
| 2983 emit_opcode(cbuf,0x75); // JNE around_slow_call | |
| 2984 emit_d8 (cbuf,0x07); // Size of slow_call | |
| 2985 // Push src onto stack slow-path | |
| 2986 emit_opcode(cbuf,0xD9 ); // FLD ST(i) | |
| 2987 emit_d8 (cbuf,0xC0-1+$src$$reg ); | |
| 2988 // CALL directly to the runtime | |
| 1748 | 2989 cbuf.set_insts_mark(); |
| 0 | 2990 emit_opcode(cbuf,0xE8); // Call into runtime |
| 1748 | 2991 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 0 | 2992 // Carry on here... |
| 2993 %} | |
| 2994 | |
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2995 enc_class FMul_ST_reg( eRegFPR src1 ) %{ |
| 0 | 2996 // Operand was loaded from memory into fp ST (stack top) |
| 2997 // FMUL ST,$src /* D8 C8+i */ | |
| 2998 emit_opcode(cbuf, 0xD8); | |
| 2999 emit_opcode(cbuf, 0xC8 + $src1$$reg); | |
| 3000 %} | |
| 3001 | |
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3002 enc_class FAdd_ST_reg( eRegFPR src2 ) %{ |
| 0 | 3003 // FADDP ST,src2 /* D8 C0+i */ |
| 3004 emit_opcode(cbuf, 0xD8); | |
| 3005 emit_opcode(cbuf, 0xC0 + $src2$$reg); | |
| 3006 //could use FADDP src2,fpST /* DE C0+i */ | |
| 3007 %} | |
| 3008 | |
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3009 enc_class FAddP_reg_ST( eRegFPR src2 ) %{ |
| 0 | 3010 // FADDP src2,ST /* DE C0+i */ |
| 3011 emit_opcode(cbuf, 0xDE); | |
| 3012 emit_opcode(cbuf, 0xC0 + $src2$$reg); | |
| 3013 %} | |
| 3014 | |
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3015 enc_class subFPR_divFPR_encode( eRegFPR src1, eRegFPR src2) %{ |
| 0 | 3016 // Operand has been loaded into fp ST (stack top) |
| 3017 // FSUB ST,$src1 | |
| 3018 emit_opcode(cbuf, 0xD8); | |
| 3019 emit_opcode(cbuf, 0xE0 + $src1$$reg); | |
| 3020 | |
| 3021 // FDIV | |
| 3022 emit_opcode(cbuf, 0xD8); | |
| 3023 emit_opcode(cbuf, 0xF0 + $src2$$reg); | |
| 3024 %} | |
| 3025 | |
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3026 enc_class MulFAddF (eRegFPR src1, eRegFPR src2) %{ |
| 0 | 3027 // Operand was loaded from memory into fp ST (stack top) |
| 3028 // FADD ST,$src /* D8 C0+i */ | |
| 3029 emit_opcode(cbuf, 0xD8); | |
| 3030 emit_opcode(cbuf, 0xC0 + $src1$$reg); | |
| 3031 | |
| 3032 // FMUL ST,src2 /* D8 C*+i */ | |
| 3033 emit_opcode(cbuf, 0xD8); | |
| 3034 emit_opcode(cbuf, 0xC8 + $src2$$reg); | |
| 3035 %} | |
| 3036 | |
| 3037 | |
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3038 enc_class MulFAddFreverse (eRegFPR src1, eRegFPR src2) %{ |
| 0 | 3039 // Operand was loaded from memory into fp ST (stack top) |
| 3040 // FADD ST,$src /* D8 C0+i */ | |
| 3041 emit_opcode(cbuf, 0xD8); | |
| 3042 emit_opcode(cbuf, 0xC0 + $src1$$reg); | |
| 3043 | |
| 3044 // FMULP src2,ST /* DE C8+i */ | |
| 3045 emit_opcode(cbuf, 0xDE); | |
| 3046 emit_opcode(cbuf, 0xC8 + $src2$$reg); | |
| 3047 %} | |
| 3048 | |
| 3049 // Atomically load the volatile long | |
| 3050 enc_class enc_loadL_volatile( memory mem, stackSlotL dst ) %{ | |
| 3051 emit_opcode(cbuf,0xDF); | |
| 3052 int rm_byte_opcode = 0x05; | |
| 3053 int base = $mem$$base; | |
| 3054 int index = $mem$$index; | |
| 3055 int scale = $mem$$scale; | |
| 3056 int displace = $mem$$disp; | |
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3057 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals |
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3058 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc); |
| 0 | 3059 store_to_stackslot( cbuf, 0x0DF, 0x07, $dst$$disp ); |
| 3060 %} | |
| 3061 | |
| 3062 // Volatile Store Long. Must be atomic, so move it into | |
| 3063 // the FP TOS and then do a 64-bit FIST. Has to probe the | |
| 3064 // target address before the store (for null-ptr checks) | |
| 3065 // so the memory operand is used twice in the encoding. | |
| 3066 enc_class enc_storeL_volatile( memory mem, stackSlotL src ) %{ | |
| 3067 store_to_stackslot( cbuf, 0x0DF, 0x05, $src$$disp ); | |
| 1748 | 3068 cbuf.set_insts_mark(); // Mark start of FIST in case $mem has an oop |
| 0 | 3069 emit_opcode(cbuf,0xDF); |
| 3070 int rm_byte_opcode = 0x07; | |
| 3071 int base = $mem$$base; | |
| 3072 int index = $mem$$index; | |
| 3073 int scale = $mem$$scale; | |
| 3074 int displace = $mem$$disp; | |
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3075 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals |
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3076 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc); |
| 0 | 3077 %} |
| 3078 | |
| 3079 // Safepoint Poll. This polls the safepoint page, and causes an | |
| 3080 // exception if it is not readable. Unfortunately, it kills the condition code | |
| 3081 // in the process | |
| 3082 // We current use TESTL [spp],EDI | |
| 3083 // A better choice might be TESTB [spp + pagesize() - CacheLineSize()],0 | |
| 3084 | |
| 3085 enc_class Safepoint_Poll() %{ | |
| 1748 | 3086 cbuf.relocate(cbuf.insts_mark(), relocInfo::poll_type, 0); |
| 0 | 3087 emit_opcode(cbuf,0x85); |
| 3088 emit_rm (cbuf, 0x0, 0x7, 0x5); | |
| 3089 emit_d32(cbuf, (intptr_t)os::get_polling_page()); | |
| 3090 %} | |
| 3091 %} | |
| 3092 | |
| 3093 | |
| 3094 //----------FRAME-------------------------------------------------------------- | |
| 3095 // Definition of frame structure and management information. | |
| 3096 // | |
| 3097 // S T A C K L A Y O U T Allocators stack-slot number | |
| 3098 // | (to get allocators register number | |
| 3099 // G Owned by | | v add OptoReg::stack0()) | |
| 3100 // r CALLER | | | |
| 3101 // o | +--------+ pad to even-align allocators stack-slot | |
| 3102 // w V | pad0 | numbers; owned by CALLER | |
| 3103 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned | |
| 3104 // h ^ | in | 5 | |
| 3105 // | | args | 4 Holes in incoming args owned by SELF | |
| 3106 // | | | | 3 | |
| 3107 // | | +--------+ | |
| 3108 // V | | old out| Empty on Intel, window on Sparc | |
| 3109 // | old |preserve| Must be even aligned. | |
| 3110 // | SP-+--------+----> Matcher::_old_SP, even aligned | |
| 3111 // | | in | 3 area for Intel ret address | |
| 3112 // Owned by |preserve| Empty on Sparc. | |
| 3113 // SELF +--------+ | |
| 3114 // | | pad2 | 2 pad to align old SP | |
| 3115 // | +--------+ 1 | |
| 3116 // | | locks | 0 | |
| 3117 // | +--------+----> OptoReg::stack0(), even aligned | |
| 3118 // | | pad1 | 11 pad to align new SP | |
| 3119 // | +--------+ | |
| 3120 // | | | 10 | |
| 3121 // | | spills | 9 spills | |
| 3122 // V | | 8 (pad0 slot for callee) | |
| 3123 // -----------+--------+----> Matcher::_out_arg_limit, unaligned | |
| 3124 // ^ | out | 7 | |
| 3125 // | | args | 6 Holes in outgoing args owned by CALLEE | |
| 3126 // Owned by +--------+ | |
| 3127 // CALLEE | new out| 6 Empty on Intel, window on Sparc | |
| 3128 // | new |preserve| Must be even-aligned. | |
| 3129 // | SP-+--------+----> Matcher::_new_SP, even aligned | |
| 3130 // | | | | |
| 3131 // | |
| 3132 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is | |
| 3133 // known from SELF's arguments and the Java calling convention. | |
| 3134 // Region 6-7 is determined per call site. | |
| 3135 // Note 2: If the calling convention leaves holes in the incoming argument | |
| 3136 // area, those holes are owned by SELF. Holes in the outgoing area | |
| 3137 // are owned by the CALLEE. Holes should not be nessecary in the | |
| 3138 // incoming area, as the Java calling convention is completely under | |
| 3139 // the control of the AD file. Doubles can be sorted and packed to | |
| 3140 // avoid holes. Holes in the outgoing arguments may be nessecary for | |
| 3141 // varargs C calling conventions. | |
| 3142 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is | |
| 3143 // even aligned with pad0 as needed. | |
| 3144 // Region 6 is even aligned. Region 6-7 is NOT even aligned; | |
| 3145 // region 6-11 is even aligned; it may be padded out more so that | |
| 3146 // the region from SP to FP meets the minimum stack alignment. | |
| 3147 | |
| 3148 frame %{ | |
| 3149 // What direction does stack grow in (assumed to be same for C & Java) | |
| 3150 stack_direction(TOWARDS_LOW); | |
| 3151 | |
| 3152 // These three registers define part of the calling convention | |
| 3153 // between compiled code and the interpreter. | |
| 3154 inline_cache_reg(EAX); // Inline Cache Register | |
| 3155 interpreter_method_oop_reg(EBX); // Method Oop Register when calling interpreter | |
| 3156 | |
| 3157 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset] | |
| 3158 cisc_spilling_operand_name(indOffset32); | |
| 3159 | |
| 3160 // Number of stack slots consumed by locking an object | |
| 3161 sync_stack_slots(1); | |
| 3162 | |
| 3163 // Compiled code's Frame Pointer | |
| 3164 frame_pointer(ESP); | |
| 3165 // Interpreter stores its frame pointer in a register which is | |
| 3166 // stored to the stack by I2CAdaptors. | |
| 3167 // I2CAdaptors convert from interpreted java to compiled java. | |
| 3168 interpreter_frame_pointer(EBP); | |
| 3169 | |
| 3170 // Stack alignment requirement | |
| 3171 // Alignment size in bytes (128-bit -> 16 bytes) | |
| 3172 stack_alignment(StackAlignmentInBytes); | |
| 3173 | |
| 3174 // Number of stack slots between incoming argument block and the start of | |
| 3175 // a new frame. The PROLOG must add this many slots to the stack. The | |
| 3176 // EPILOG must remove this many slots. Intel needs one slot for | |
| 3177 // return address and one for rbp, (must save rbp) | |
| 3178 in_preserve_stack_slots(2+VerifyStackAtCalls); | |
| 3179 | |
| 3180 // Number of outgoing stack slots killed above the out_preserve_stack_slots | |
| 3181 // for calls to C. Supports the var-args backing area for register parms. | |
| 3182 varargs_C_out_slots_killed(0); | |
| 3183 | |
| 3184 // The after-PROLOG location of the return address. Location of | |
| 3185 // return address specifies a type (REG or STACK) and a number | |
| 3186 // representing the register number (i.e. - use a register name) or | |
| 3187 // stack slot. | |
| 3188 // Ret Addr is on stack in slot 0 if no locks or verification or alignment. | |
| 3189 // Otherwise, it is above the locks and verification slot and alignment word | |
| 3190 return_addr(STACK - 1 + | |
| 4950 | 3191 round_to((Compile::current()->in_preserve_stack_slots() + |
| 3192 Compile::current()->fixed_slots()), | |
| 3193 stack_alignment_in_slots())); | |
| 0 | 3194 |
| 3195 // Body of function which returns an integer array locating | |
| 3196 // arguments either in registers or in stack slots. Passed an array | |
| 3197 // of ideal registers called "sig" and a "length" count. Stack-slot | |
| 3198 // offsets are based on outgoing arguments, i.e. a CALLER setting up | |
| 3199 // arguments for a CALLEE. Incoming stack arguments are | |
| 3200 // automatically biased by the preserve_stack_slots field above. | |
| 3201 calling_convention %{ | |
| 3202 // No difference between ingoing/outgoing just pass false | |
| 3203 SharedRuntime::java_calling_convention(sig_bt, regs, length, false); | |
| 3204 %} | |
| 3205 | |
| 3206 | |
| 3207 // Body of function which returns an integer array locating | |
| 3208 // arguments either in registers or in stack slots. Passed an array | |
| 3209 // of ideal registers called "sig" and a "length" count. Stack-slot | |
| 3210 // offsets are based on outgoing arguments, i.e. a CALLER setting up | |
| 3211 // arguments for a CALLEE. Incoming stack arguments are | |
| 3212 // automatically biased by the preserve_stack_slots field above. | |
| 3213 c_calling_convention %{ | |
| 3214 // This is obviously always outgoing | |
|
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3215 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length); |
| 0 | 3216 %} |
| 3217 | |
| 3218 // Location of C & interpreter return values | |
| 3219 c_return_value %{ | |
| 3220 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); | |
|
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3221 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num }; |
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3222 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num }; |
| 0 | 3223 |
| 3224 // in SSE2+ mode we want to keep the FPU stack clean so pretend | |
| 3225 // that C functions return float and double results in XMM0. | |
| 3226 if( ideal_reg == Op_RegD && UseSSE>=2 ) | |
|
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3227 return OptoRegPair(XMM0b_num,XMM0_num); |
| 0 | 3228 if( ideal_reg == Op_RegF && UseSSE>=2 ) |
|
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3229 return OptoRegPair(OptoReg::Bad,XMM0_num); |
| 0 | 3230 |
| 3231 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]); | |
| 3232 %} | |
| 3233 | |
| 3234 // Location of return values | |
| 3235 return_value %{ | |
| 3236 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); | |
|
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3237 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num }; |
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3238 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num }; |
| 0 | 3239 if( ideal_reg == Op_RegD && UseSSE>=2 ) |
|
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3240 return OptoRegPair(XMM0b_num,XMM0_num); |
| 0 | 3241 if( ideal_reg == Op_RegF && UseSSE>=1 ) |
|
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3242 return OptoRegPair(OptoReg::Bad,XMM0_num); |
| 0 | 3243 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]); |
| 3244 %} | |
| 3245 | |
| 3246 %} | |
| 3247 | |
| 3248 //----------ATTRIBUTES--------------------------------------------------------- | |
| 3249 //----------Operand Attributes------------------------------------------------- | |
| 3250 op_attrib op_cost(0); // Required cost attribute | |
| 3251 | |
| 3252 //----------Instruction Attributes--------------------------------------------- | |
| 3253 ins_attrib ins_cost(100); // Required cost attribute | |
| 3254 ins_attrib ins_size(8); // Required size attribute (in bits) | |
| 3255 ins_attrib ins_short_branch(0); // Required flag: is this instruction a | |
| 3256 // non-matching short branch variant of some | |
| 3257 // long branch? | |
| 3258 ins_attrib ins_alignment(1); // Required alignment attribute (must be a power of 2) | |
| 3259 // specifies the alignment that some part of the instruction (not | |
| 3260 // necessarily the start) requires. If > 1, a compute_padding() | |
| 3261 // function must be provided for the instruction | |
| 3262 | |
| 3263 //----------OPERANDS----------------------------------------------------------- | |
| 3264 // Operand definitions must precede instruction definitions for correct parsing | |
| 3265 // in the ADLC because operands constitute user defined types which are used in | |
| 3266 // instruction definitions. | |
| 3267 | |
| 3268 //----------Simple Operands---------------------------------------------------- | |
| 3269 // Immediate Operands | |
| 3270 // Integer Immediate | |
| 3271 operand immI() %{ | |
| 3272 match(ConI); | |
| 3273 | |
| 3274 op_cost(10); | |
| 3275 format %{ %} | |
| 3276 interface(CONST_INTER); | |
| 3277 %} | |
| 3278 | |
| 3279 // Constant for test vs zero | |
| 3280 operand immI0() %{ | |
| 3281 predicate(n->get_int() == 0); | |
| 3282 match(ConI); | |
| 3283 | |
| 3284 op_cost(0); | |
| 3285 format %{ %} | |
| 3286 interface(CONST_INTER); | |
| 3287 %} | |
| 3288 | |
| 3289 // Constant for increment | |
| 3290 operand immI1() %{ | |
| 3291 predicate(n->get_int() == 1); | |
| 3292 match(ConI); | |
| 3293 | |
| 3294 op_cost(0); | |
| 3295 format %{ %} | |
| 3296 interface(CONST_INTER); | |
| 3297 %} | |
| 3298 | |
| 3299 // Constant for decrement | |
| 3300 operand immI_M1() %{ | |
| 3301 predicate(n->get_int() == -1); | |
| 3302 match(ConI); | |
| 3303 | |
| 3304 op_cost(0); | |
| 3305 format %{ %} | |
| 3306 interface(CONST_INTER); | |
| 3307 %} | |
| 3308 | |
| 3309 // Valid scale values for addressing modes | |
| 3310 operand immI2() %{ | |
| 3311 predicate(0 <= n->get_int() && (n->get_int() <= 3)); | |
| 3312 match(ConI); | |
| 3313 | |
| 3314 format %{ %} | |
| 3315 interface(CONST_INTER); | |
| 3316 %} | |
| 3317 | |
| 3318 operand immI8() %{ | |
| 3319 predicate((-128 <= n->get_int()) && (n->get_int() <= 127)); | |
| 3320 match(ConI); | |
| 3321 | |
| 3322 op_cost(5); | |
| 3323 format %{ %} | |
| 3324 interface(CONST_INTER); | |
| 3325 %} | |
| 3326 | |
| 3327 operand immI16() %{ | |
| 3328 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767)); | |
| 3329 match(ConI); | |
| 3330 | |
| 3331 op_cost(10); | |
| 3332 format %{ %} | |
| 3333 interface(CONST_INTER); | |
| 3334 %} | |
| 3335 | |
|
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3336 // Int Immediate non-negative |
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3337 operand immU31() |
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3338 %{ |
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3339 predicate(n->get_int() >= 0); |
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3340 match(ConI); |
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3341 |
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3342 op_cost(0); |
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3343 format %{ %} |
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3344 interface(CONST_INTER); |
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3345 %} |
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|
3346 |
| 0 | 3347 // Constant for long shifts |
| 3348 operand immI_32() %{ | |
| 3349 predicate( n->get_int() == 32 ); | |
| 3350 match(ConI); | |
| 3351 | |
| 3352 op_cost(0); | |
| 3353 format %{ %} | |
| 3354 interface(CONST_INTER); | |
| 3355 %} | |
| 3356 | |
| 3357 operand immI_1_31() %{ | |
| 3358 predicate( n->get_int() >= 1 && n->get_int() <= 31 ); | |
| 3359 match(ConI); | |
| 3360 | |
| 3361 op_cost(0); | |
| 3362 format %{ %} | |
| 3363 interface(CONST_INTER); | |
| 3364 %} | |
| 3365 | |
| 3366 operand immI_32_63() %{ | |
| 3367 predicate( n->get_int() >= 32 && n->get_int() <= 63 ); | |
| 3368 match(ConI); | |
| 3369 op_cost(0); | |
| 3370 | |
| 3371 format %{ %} | |
| 3372 interface(CONST_INTER); | |
| 3373 %} | |
| 3374 | |
| 219 | 3375 operand immI_1() %{ |
| 3376 predicate( n->get_int() == 1 ); | |
| 3377 match(ConI); | |
| 3378 | |
| 3379 op_cost(0); | |
| 3380 format %{ %} | |
| 3381 interface(CONST_INTER); | |
| 3382 %} | |
| 3383 | |
| 3384 operand immI_2() %{ | |
| 3385 predicate( n->get_int() == 2 ); | |
| 3386 match(ConI); | |
| 3387 | |
| 3388 op_cost(0); | |
| 3389 format %{ %} | |
| 3390 interface(CONST_INTER); | |
| 3391 %} | |
| 3392 | |
| 3393 operand immI_3() %{ | |
| 3394 predicate( n->get_int() == 3 ); | |
| 3395 match(ConI); | |
| 3396 | |
| 3397 op_cost(0); | |
| 3398 format %{ %} | |
| 3399 interface(CONST_INTER); | |
| 3400 %} | |
| 3401 | |
| 0 | 3402 // Pointer Immediate |
| 3403 operand immP() %{ | |
| 3404 match(ConP); | |
| 3405 | |
| 3406 op_cost(10); | |
| 3407 format %{ %} | |
| 3408 interface(CONST_INTER); | |
| 3409 %} | |
| 3410 | |
| 3411 // NULL Pointer Immediate | |
| 3412 operand immP0() %{ | |
| 3413 predicate( n->get_ptr() == 0 ); | |
| 3414 match(ConP); | |
| 3415 op_cost(0); | |
| 3416 | |
| 3417 format %{ %} | |
| 3418 interface(CONST_INTER); | |
| 3419 %} | |
| 3420 | |
| 3421 // Long Immediate | |
| 3422 operand immL() %{ | |
| 3423 match(ConL); | |
| 3424 | |
| 3425 op_cost(20); | |
| 3426 format %{ %} | |
| 3427 interface(CONST_INTER); | |
| 3428 %} | |
| 3429 | |
| 3430 // Long Immediate zero | |
| 3431 operand immL0() %{ | |
| 3432 predicate( n->get_long() == 0L ); | |
| 3433 match(ConL); | |
| 3434 op_cost(0); | |
| 3435 | |
| 3436 format %{ %} | |
| 3437 interface(CONST_INTER); | |
| 3438 %} | |
| 3439 | |
| 403 | 3440 // Long Immediate zero |
| 3441 operand immL_M1() %{ | |
| 3442 predicate( n->get_long() == -1L ); | |
| 3443 match(ConL); | |
| 3444 op_cost(0); | |
| 3445 | |
| 3446 format %{ %} | |
| 3447 interface(CONST_INTER); | |
| 3448 %} | |
| 3449 | |
| 0 | 3450 // Long immediate from 0 to 127. |
| 3451 // Used for a shorter form of long mul by 10. | |
| 3452 operand immL_127() %{ | |
| 3453 predicate((0 <= n->get_long()) && (n->get_long() <= 127)); | |
| 3454 match(ConL); | |
| 3455 op_cost(0); | |
| 3456 | |
| 3457 format %{ %} | |
| 3458 interface(CONST_INTER); | |
| 3459 %} | |
| 3460 | |
| 3461 // Long Immediate: low 32-bit mask | |
| 3462 operand immL_32bits() %{ | |
| 3463 predicate(n->get_long() == 0xFFFFFFFFL); | |
| 3464 match(ConL); | |
| 3465 op_cost(0); | |
| 3466 | |
| 3467 format %{ %} | |
| 3468 interface(CONST_INTER); | |
| 3469 %} | |
| 3470 | |
| 3471 // Long Immediate: low 32-bit mask | |
| 3472 operand immL32() %{ | |
| 3473 predicate(n->get_long() == (int)(n->get_long())); | |
| 3474 match(ConL); | |
| 3475 op_cost(20); | |
| 3476 | |
| 3477 format %{ %} | |
| 3478 interface(CONST_INTER); | |
| 3479 %} | |
| 3480 | |
| 3481 //Double Immediate zero | |
|
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3482 operand immDPR0() %{ |
| 0 | 3483 // Do additional (and counter-intuitive) test against NaN to work around VC++ |
| 3484 // bug that generates code such that NaNs compare equal to 0.0 | |
| 3485 predicate( UseSSE<=1 && n->getd() == 0.0 && !g_isnan(n->getd()) ); | |
| 3486 match(ConD); | |
| 3487 | |
| 3488 op_cost(5); | |
| 3489 format %{ %} | |
| 3490 interface(CONST_INTER); | |
| 3491 %} | |
| 3492 | |
| 2008 | 3493 // Double Immediate one |
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3494 operand immDPR1() %{ |
| 0 | 3495 predicate( UseSSE<=1 && n->getd() == 1.0 ); |
| 3496 match(ConD); | |
| 3497 | |
| 3498 op_cost(5); | |
| 3499 format %{ %} | |
| 3500 interface(CONST_INTER); | |
| 3501 %} | |
| 3502 | |
| 3503 // Double Immediate | |
|
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3504 operand immDPR() %{ |
| 0 | 3505 predicate(UseSSE<=1); |
| 3506 match(ConD); | |
| 3507 | |
| 3508 op_cost(5); | |
| 3509 format %{ %} | |
| 3510 interface(CONST_INTER); | |
| 3511 %} | |
| 3512 | |
|
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3513 operand immD() %{ |
| 0 | 3514 predicate(UseSSE>=2); |
| 3515 match(ConD); | |
| 3516 | |
| 3517 op_cost(5); | |
| 3518 format %{ %} | |
| 3519 interface(CONST_INTER); | |
| 3520 %} | |
| 3521 | |
| 3522 // Double Immediate zero | |
|
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3523 operand immD0() %{ |
| 0 | 3524 // Do additional (and counter-intuitive) test against NaN to work around VC++ |
| 3525 // bug that generates code such that NaNs compare equal to 0.0 AND do not | |
| 3526 // compare equal to -0.0. | |
| 3527 predicate( UseSSE>=2 && jlong_cast(n->getd()) == 0 ); | |
| 3528 match(ConD); | |
| 3529 | |
| 3530 format %{ %} | |
| 3531 interface(CONST_INTER); | |
| 3532 %} | |
| 3533 | |
| 3534 // Float Immediate zero | |
|
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3535 operand immFPR0() %{ |
| 2008 | 3536 predicate(UseSSE == 0 && n->getf() == 0.0F); |
| 3537 match(ConF); | |
| 3538 | |
| 3539 op_cost(5); | |
| 3540 format %{ %} | |
| 3541 interface(CONST_INTER); | |
| 3542 %} | |
| 3543 | |
| 3544 // Float Immediate one | |
|
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3545 operand immFPR1() %{ |
| 2008 | 3546 predicate(UseSSE == 0 && n->getf() == 1.0F); |
| 0 | 3547 match(ConF); |
| 3548 | |
| 3549 op_cost(5); | |
| 3550 format %{ %} | |
| 3551 interface(CONST_INTER); | |
| 3552 %} | |
| 3553 | |
| 3554 // Float Immediate | |
|
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3555 operand immFPR() %{ |
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3556 predicate( UseSSE == 0 ); |
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3557 match(ConF); |
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3558 |
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3559 op_cost(5); |
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3560 format %{ %} |
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3561 interface(CONST_INTER); |
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3562 %} |
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|
3563 |
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3564 // Float Immediate |
| 0 | 3565 operand immF() %{ |
| 3566 predicate(UseSSE >= 1); | |
| 3567 match(ConF); | |
| 3568 | |
| 3569 op_cost(5); | |
| 3570 format %{ %} | |
| 3571 interface(CONST_INTER); | |
| 3572 %} | |
| 3573 | |
| 3574 // Float Immediate zero. Zero and not -0.0 | |
|
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3575 operand immF0() %{ |
| 0 | 3576 predicate( UseSSE >= 1 && jint_cast(n->getf()) == 0 ); |
| 3577 match(ConF); | |
| 3578 | |
| 3579 op_cost(5); | |
| 3580 format %{ %} | |
| 3581 interface(CONST_INTER); | |
| 3582 %} | |
| 3583 | |
| 3584 // Immediates for special shifts (sign extend) | |
| 3585 | |
| 3586 // Constants for increment | |
| 3587 operand immI_16() %{ | |
| 3588 predicate( n->get_int() == 16 ); | |
| 3589 match(ConI); | |
| 3590 | |
| 3591 format %{ %} | |
| 3592 interface(CONST_INTER); | |
| 3593 %} | |
| 3594 | |
| 3595 operand immI_24() %{ | |
| 3596 predicate( n->get_int() == 24 ); | |
| 3597 match(ConI); | |
| 3598 | |
| 3599 format %{ %} | |
| 3600 interface(CONST_INTER); | |
| 3601 %} | |
| 3602 | |
| 3603 // Constant for byte-wide masking | |
| 3604 operand immI_255() %{ | |
| 3605 predicate( n->get_int() == 255 ); | |
| 3606 match(ConI); | |
| 3607 | |
| 3608 format %{ %} | |
| 3609 interface(CONST_INTER); | |
| 3610 %} | |
| 3611 | |
| 785 | 3612 // Constant for short-wide masking |
| 3613 operand immI_65535() %{ | |
| 3614 predicate(n->get_int() == 65535); | |
| 3615 match(ConI); | |
| 3616 | |
| 3617 format %{ %} | |
| 3618 interface(CONST_INTER); | |
| 3619 %} | |
| 3620 | |
| 0 | 3621 // Register Operands |
| 3622 // Integer Register | |
|
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3623 operand rRegI() %{ |
|
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|
3624 constraint(ALLOC_IN_RC(int_reg)); |
| 0 | 3625 match(RegI); |
| 3626 match(xRegI); | |
| 3627 match(eAXRegI); | |
| 3628 match(eBXRegI); | |
| 3629 match(eCXRegI); | |
| 3630 match(eDXRegI); | |
| 3631 match(eDIRegI); | |
| 3632 match(eSIRegI); | |
| 3633 | |
| 3634 format %{ %} | |
| 3635 interface(REG_INTER); | |
| 3636 %} | |
| 3637 | |
| 3638 // Subset of Integer Register | |
|
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3639 operand xRegI(rRegI reg) %{ |
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3640 constraint(ALLOC_IN_RC(int_x_reg)); |
| 0 | 3641 match(reg); |
| 3642 match(eAXRegI); | |
| 3643 match(eBXRegI); | |
| 3644 match(eCXRegI); | |
| 3645 match(eDXRegI); | |
| 3646 | |
| 3647 format %{ %} | |
| 3648 interface(REG_INTER); | |
| 3649 %} | |
| 3650 | |
| 3651 // Special Registers | |
| 3652 operand eAXRegI(xRegI reg) %{ | |
| 3653 constraint(ALLOC_IN_RC(eax_reg)); | |
| 3654 match(reg); | |
|
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3655 match(rRegI); |
| 0 | 3656 |
| 3657 format %{ "EAX" %} | |
| 3658 interface(REG_INTER); | |
| 3659 %} | |
| 3660 | |
| 3661 // Special Registers | |
| 3662 operand eBXRegI(xRegI reg) %{ | |
| 3663 constraint(ALLOC_IN_RC(ebx_reg)); | |
| 3664 match(reg); | |
|
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|
3665 match(rRegI); |
| 0 | 3666 |
| 3667 format %{ "EBX" %} | |
| 3668 interface(REG_INTER); | |
| 3669 %} | |
| 3670 | |
| 3671 operand eCXRegI(xRegI reg) %{ | |
| 3672 constraint(ALLOC_IN_RC(ecx_reg)); | |
| 3673 match(reg); | |
|
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3674 match(rRegI); |
| 0 | 3675 |
| 3676 format %{ "ECX" %} | |
| 3677 interface(REG_INTER); | |
| 3678 %} | |
| 3679 | |
| 3680 operand eDXRegI(xRegI reg) %{ | |
| 3681 constraint(ALLOC_IN_RC(edx_reg)); | |
| 3682 match(reg); | |
|
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3683 match(rRegI); |
| 0 | 3684 |
| 3685 format %{ "EDX" %} | |
| 3686 interface(REG_INTER); | |
| 3687 %} | |
| 3688 | |
| 3689 operand eDIRegI(xRegI reg) %{ | |
| 3690 constraint(ALLOC_IN_RC(edi_reg)); | |
| 3691 match(reg); | |
|
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3692 match(rRegI); |
| 0 | 3693 |
| 3694 format %{ "EDI" %} | |
| 3695 interface(REG_INTER); | |
| 3696 %} | |
| 3697 | |
| 3698 operand naxRegI() %{ | |
| 3699 constraint(ALLOC_IN_RC(nax_reg)); | |
| 3700 match(RegI); | |
| 3701 match(eCXRegI); | |
| 3702 match(eDXRegI); | |
| 3703 match(eSIRegI); | |
| 3704 match(eDIRegI); | |
| 3705 | |
| 3706 format %{ %} | |
| 3707 interface(REG_INTER); | |
| 3708 %} | |
| 3709 | |
| 3710 operand nadxRegI() %{ | |
| 3711 constraint(ALLOC_IN_RC(nadx_reg)); | |
| 3712 match(RegI); | |
| 3713 match(eBXRegI); | |
| 3714 match(eCXRegI); | |
| 3715 match(eSIRegI); | |
| 3716 match(eDIRegI); | |
| 3717 | |
| 3718 format %{ %} | |
| 3719 interface(REG_INTER); | |
| 3720 %} | |
| 3721 | |
| 3722 operand ncxRegI() %{ | |
| 3723 constraint(ALLOC_IN_RC(ncx_reg)); | |
| 3724 match(RegI); | |
| 3725 match(eAXRegI); | |
| 3726 match(eDXRegI); | |
| 3727 match(eSIRegI); | |
| 3728 match(eDIRegI); | |
| 3729 | |
| 3730 format %{ %} | |
| 3731 interface(REG_INTER); | |
| 3732 %} | |
| 3733 | |
| 3734 // // This operand was used by cmpFastUnlock, but conflicted with 'object' reg | |
| 3735 // // | |
| 3736 operand eSIRegI(xRegI reg) %{ | |
| 3737 constraint(ALLOC_IN_RC(esi_reg)); | |
| 3738 match(reg); | |
|
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3739 match(rRegI); |
| 0 | 3740 |
| 3741 format %{ "ESI" %} | |
| 3742 interface(REG_INTER); | |
| 3743 %} | |
| 3744 | |
| 3745 // Pointer Register | |
| 3746 operand anyRegP() %{ | |
| 3747 constraint(ALLOC_IN_RC(any_reg)); | |
| 3748 match(RegP); | |
| 3749 match(eAXRegP); | |
| 3750 match(eBXRegP); | |
| 3751 match(eCXRegP); | |
| 3752 match(eDIRegP); | |
| 3753 match(eRegP); | |
| 3754 | |
| 3755 format %{ %} | |
| 3756 interface(REG_INTER); | |
| 3757 %} | |
| 3758 | |
| 3759 operand eRegP() %{ | |
|
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3760 constraint(ALLOC_IN_RC(int_reg)); |
| 0 | 3761 match(RegP); |
| 3762 match(eAXRegP); | |
| 3763 match(eBXRegP); | |
| 3764 match(eCXRegP); | |
| 3765 match(eDIRegP); | |
| 3766 | |
| 3767 format %{ %} | |
| 3768 interface(REG_INTER); | |
| 3769 %} | |
| 3770 | |
| 3771 // On windows95, EBP is not safe to use for implicit null tests. | |
| 3772 operand eRegP_no_EBP() %{ | |
|
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3773 constraint(ALLOC_IN_RC(int_reg_no_ebp)); |
| 0 | 3774 match(RegP); |
| 3775 match(eAXRegP); | |
| 3776 match(eBXRegP); | |
| 3777 match(eCXRegP); | |
| 3778 match(eDIRegP); | |
| 3779 | |
| 3780 op_cost(100); | |
| 3781 format %{ %} | |
| 3782 interface(REG_INTER); | |
| 3783 %} | |
| 3784 | |
| 3785 operand naxRegP() %{ | |
| 3786 constraint(ALLOC_IN_RC(nax_reg)); | |
| 3787 match(RegP); | |
| 3788 match(eBXRegP); | |
| 3789 match(eDXRegP); | |
| 3790 match(eCXRegP); | |
| 3791 match(eSIRegP); | |
| 3792 match(eDIRegP); | |
| 3793 | |
| 3794 format %{ %} | |
| 3795 interface(REG_INTER); | |
| 3796 %} | |
| 3797 | |
| 3798 operand nabxRegP() %{ | |
| 3799 constraint(ALLOC_IN_RC(nabx_reg)); | |
| 3800 match(RegP); | |
| 3801 match(eCXRegP); | |
| 3802 match(eDXRegP); | |
| 3803 match(eSIRegP); | |
| 3804 match(eDIRegP); | |
| 3805 | |
| 3806 format %{ %} | |
| 3807 interface(REG_INTER); | |
| 3808 %} | |
| 3809 | |
| 3810 operand pRegP() %{ | |
| 3811 constraint(ALLOC_IN_RC(p_reg)); | |
| 3812 match(RegP); | |
| 3813 match(eBXRegP); | |
| 3814 match(eDXRegP); | |
| 3815 match(eSIRegP); | |
| 3816 match(eDIRegP); | |
| 3817 | |
| 3818 format %{ %} | |
| 3819 interface(REG_INTER); | |
| 3820 %} | |
| 3821 | |
| 3822 // Special Registers | |
| 3823 // Return a pointer value | |
| 3824 operand eAXRegP(eRegP reg) %{ | |
| 3825 constraint(ALLOC_IN_RC(eax_reg)); | |
| 3826 match(reg); | |
| 3827 format %{ "EAX" %} | |
| 3828 interface(REG_INTER); | |
| 3829 %} | |
| 3830 | |
| 3831 // Used in AtomicAdd | |
| 3832 operand eBXRegP(eRegP reg) %{ | |
| 3833 constraint(ALLOC_IN_RC(ebx_reg)); | |
| 3834 match(reg); | |
| 3835 format %{ "EBX" %} | |
| 3836 interface(REG_INTER); | |
| 3837 %} | |
| 3838 | |
| 3839 // Tail-call (interprocedural jump) to interpreter | |
| 3840 operand eCXRegP(eRegP reg) %{ | |
| 3841 constraint(ALLOC_IN_RC(ecx_reg)); | |
| 3842 match(reg); | |
| 3843 format %{ "ECX" %} | |
| 3844 interface(REG_INTER); | |
| 3845 %} | |
| 3846 | |
| 3847 operand eSIRegP(eRegP reg) %{ | |
| 3848 constraint(ALLOC_IN_RC(esi_reg)); | |
| 3849 match(reg); | |
| 3850 format %{ "ESI" %} | |
| 3851 interface(REG_INTER); | |
| 3852 %} | |
| 3853 | |
| 3854 // Used in rep stosw | |
| 3855 operand eDIRegP(eRegP reg) %{ | |
| 3856 constraint(ALLOC_IN_RC(edi_reg)); | |
| 3857 match(reg); | |
| 3858 format %{ "EDI" %} | |
| 3859 interface(REG_INTER); | |
| 3860 %} | |
| 3861 | |
| 3862 operand eRegL() %{ | |
| 3863 constraint(ALLOC_IN_RC(long_reg)); | |
| 3864 match(RegL); | |
| 3865 match(eADXRegL); | |
| 3866 | |
| 3867 format %{ %} | |
| 3868 interface(REG_INTER); | |
| 3869 %} | |
| 3870 | |
| 3871 operand eADXRegL( eRegL reg ) %{ | |
| 3872 constraint(ALLOC_IN_RC(eadx_reg)); | |
| 3873 match(reg); | |
| 3874 | |
| 3875 format %{ "EDX:EAX" %} | |
| 3876 interface(REG_INTER); | |
| 3877 %} | |
| 3878 | |
| 3879 operand eBCXRegL( eRegL reg ) %{ | |
| 3880 constraint(ALLOC_IN_RC(ebcx_reg)); | |
| 3881 match(reg); | |
| 3882 | |
| 3883 format %{ "EBX:ECX" %} | |
| 3884 interface(REG_INTER); | |
| 3885 %} | |
| 3886 | |
| 3887 // Special case for integer high multiply | |
| 3888 operand eADXRegL_low_only() %{ | |
| 3889 constraint(ALLOC_IN_RC(eadx_reg)); | |
| 3890 match(RegL); | |
| 3891 | |
| 3892 format %{ "EAX" %} | |
| 3893 interface(REG_INTER); | |
| 3894 %} | |
| 3895 | |
| 3896 // Flags register, used as output of compare instructions | |
| 3897 operand eFlagsReg() %{ | |
| 3898 constraint(ALLOC_IN_RC(int_flags)); | |
| 3899 match(RegFlags); | |
| 3900 | |
| 3901 format %{ "EFLAGS" %} | |
| 3902 interface(REG_INTER); | |
| 3903 %} | |
| 3904 | |
| 3905 // Flags register, used as output of FLOATING POINT compare instructions | |
| 3906 operand eFlagsRegU() %{ | |
| 3907 constraint(ALLOC_IN_RC(int_flags)); | |
| 3908 match(RegFlags); | |
| 3909 | |
| 3910 format %{ "EFLAGS_U" %} | |
| 3911 interface(REG_INTER); | |
| 3912 %} | |
| 3913 | |
|
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3914 operand eFlagsRegUCF() %{ |
|
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|
3915 constraint(ALLOC_IN_RC(int_flags)); |
|
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|
3916 match(RegFlags); |
|
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|
3917 predicate(false); |
|
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|
3918 |
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|
3919 format %{ "EFLAGS_U_CF" %} |
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3920 interface(REG_INTER); |
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|
3921 %} |
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3922 |
| 0 | 3923 // Condition Code Register used by long compare |
| 3924 operand flagsReg_long_LTGE() %{ | |
| 3925 constraint(ALLOC_IN_RC(int_flags)); | |
| 3926 match(RegFlags); | |
| 3927 format %{ "FLAGS_LTGE" %} | |
| 3928 interface(REG_INTER); | |
| 3929 %} | |
| 3930 operand flagsReg_long_EQNE() %{ | |
| 3931 constraint(ALLOC_IN_RC(int_flags)); | |
| 3932 match(RegFlags); | |
| 3933 format %{ "FLAGS_EQNE" %} | |
| 3934 interface(REG_INTER); | |
| 3935 %} | |
| 3936 operand flagsReg_long_LEGT() %{ | |
| 3937 constraint(ALLOC_IN_RC(int_flags)); | |
| 3938 match(RegFlags); | |
| 3939 format %{ "FLAGS_LEGT" %} | |
| 3940 interface(REG_INTER); | |
| 3941 %} | |
| 3942 | |
| 3943 // Float register operands | |
|
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3944 operand regDPR() %{ |
| 0 | 3945 predicate( UseSSE < 2 ); |
|
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3946 constraint(ALLOC_IN_RC(fp_dbl_reg)); |
| 0 | 3947 match(RegD); |
| 3948 match(regDPR1); | |
| 3949 match(regDPR2); | |
| 3950 format %{ %} | |
| 3951 interface(REG_INTER); | |
| 3952 %} | |
| 3953 | |
|
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3954 operand regDPR1(regDPR reg) %{ |
| 0 | 3955 predicate( UseSSE < 2 ); |
|
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3956 constraint(ALLOC_IN_RC(fp_dbl_reg0)); |
| 0 | 3957 match(reg); |
| 3958 format %{ "FPR1" %} | |
| 3959 interface(REG_INTER); | |
| 3960 %} | |
| 3961 | |
|
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3962 operand regDPR2(regDPR reg) %{ |
| 0 | 3963 predicate( UseSSE < 2 ); |
|
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3964 constraint(ALLOC_IN_RC(fp_dbl_reg1)); |
| 0 | 3965 match(reg); |
| 3966 format %{ "FPR2" %} | |
| 3967 interface(REG_INTER); | |
| 3968 %} | |
| 3969 | |
|
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3970 operand regnotDPR1(regDPR reg) %{ |
| 0 | 3971 predicate( UseSSE < 2 ); |
|
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3972 constraint(ALLOC_IN_RC(fp_dbl_notreg0)); |
| 0 | 3973 match(reg); |
| 3974 format %{ %} | |
| 3975 interface(REG_INTER); | |
| 3976 %} | |
| 3977 | |
| 3978 // Float register operands | |
|
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3979 operand regFPR() %{ |
| 0 | 3980 predicate( UseSSE < 2 ); |
|
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3981 constraint(ALLOC_IN_RC(fp_flt_reg)); |
| 0 | 3982 match(RegF); |
| 3983 match(regFPR1); | |
| 3984 format %{ %} | |
| 3985 interface(REG_INTER); | |
| 3986 %} | |
| 3987 | |
| 3988 // Float register operands | |
|
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3989 operand regFPR1(regFPR reg) %{ |
| 0 | 3990 predicate( UseSSE < 2 ); |
|
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3991 constraint(ALLOC_IN_RC(fp_flt_reg0)); |
| 0 | 3992 match(reg); |
| 3993 format %{ "FPR1" %} | |
| 3994 interface(REG_INTER); | |
| 3995 %} | |
| 3996 | |
|
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3997 // XMM Float register operands |
|
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3998 operand regF() %{ |
| 0 | 3999 predicate( UseSSE>=1 ); |
|
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4000 constraint(ALLOC_IN_RC(float_reg)); |
| 0 | 4001 match(RegF); |
| 4002 format %{ %} | |
| 4003 interface(REG_INTER); | |
| 4004 %} | |
| 4005 | |
|
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4006 // XMM Double register operands |
|
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4007 operand regD() %{ |
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4008 predicate( UseSSE>=2 ); |
|
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4009 constraint(ALLOC_IN_RC(double_reg)); |
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4010 match(RegD); |
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|
4011 format %{ %} |
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4012 interface(REG_INTER); |
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4013 %} |
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|
4014 |
| 0 | 4015 |
| 4016 //----------Memory Operands---------------------------------------------------- | |
| 4017 // Direct Memory Operand | |
| 4018 operand direct(immP addr) %{ | |
| 4019 match(addr); | |
| 4020 | |
| 4021 format %{ "[$addr]" %} | |
| 4022 interface(MEMORY_INTER) %{ | |
| 4023 base(0xFFFFFFFF); | |
| 4024 index(0x4); | |
| 4025 scale(0x0); | |
| 4026 disp($addr); | |
| 4027 %} | |
| 4028 %} | |
| 4029 | |
| 4030 // Indirect Memory Operand | |
| 4031 operand indirect(eRegP reg) %{ | |
|
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4032 constraint(ALLOC_IN_RC(int_reg)); |
| 0 | 4033 match(reg); |
| 4034 | |
| 4035 format %{ "[$reg]" %} | |
| 4036 interface(MEMORY_INTER) %{ | |
| 4037 base($reg); | |
| 4038 index(0x4); | |
| 4039 scale(0x0); | |
| 4040 disp(0x0); | |
| 4041 %} | |
| 4042 %} | |
| 4043 | |
| 4044 // Indirect Memory Plus Short Offset Operand | |
| 4045 operand indOffset8(eRegP reg, immI8 off) %{ | |
| 4046 match(AddP reg off); | |
| 4047 | |
| 4048 format %{ "[$reg + $off]" %} | |
| 4049 interface(MEMORY_INTER) %{ | |
| 4050 base($reg); | |
| 4051 index(0x4); | |
| 4052 scale(0x0); | |
| 4053 disp($off); | |
| 4054 %} | |
| 4055 %} | |
| 4056 | |
| 4057 // Indirect Memory Plus Long Offset Operand | |
| 4058 operand indOffset32(eRegP reg, immI off) %{ | |
| 4059 match(AddP reg off); | |
| 4060 | |
| 4061 format %{ "[$reg + $off]" %} | |
| 4062 interface(MEMORY_INTER) %{ | |
| 4063 base($reg); | |
| 4064 index(0x4); | |
| 4065 scale(0x0); | |
| 4066 disp($off); | |
| 4067 %} | |
| 4068 %} | |
| 4069 | |
| 4070 // Indirect Memory Plus Long Offset Operand | |
|
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|
4071 operand indOffset32X(rRegI reg, immP off) %{ |
| 0 | 4072 match(AddP off reg); |
| 4073 | |
| 4074 format %{ "[$reg + $off]" %} | |
| 4075 interface(MEMORY_INTER) %{ | |
| 4076 base($reg); | |
| 4077 index(0x4); | |
| 4078 scale(0x0); | |
| 4079 disp($off); | |
| 4080 %} | |
| 4081 %} | |
| 4082 | |
| 4083 // Indirect Memory Plus Index Register Plus Offset Operand | |
|
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4084 operand indIndexOffset(eRegP reg, rRegI ireg, immI off) %{ |
| 0 | 4085 match(AddP (AddP reg ireg) off); |
| 4086 | |
| 4087 op_cost(10); | |
| 4088 format %{"[$reg + $off + $ireg]" %} | |
| 4089 interface(MEMORY_INTER) %{ | |
| 4090 base($reg); | |
| 4091 index($ireg); | |
| 4092 scale(0x0); | |
| 4093 disp($off); | |
| 4094 %} | |
| 4095 %} | |
| 4096 | |
| 4097 // Indirect Memory Plus Index Register Plus Offset Operand | |
|
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4098 operand indIndex(eRegP reg, rRegI ireg) %{ |
| 0 | 4099 match(AddP reg ireg); |
| 4100 | |
| 4101 op_cost(10); | |
| 4102 format %{"[$reg + $ireg]" %} | |
| 4103 interface(MEMORY_INTER) %{ | |
| 4104 base($reg); | |
| 4105 index($ireg); | |
| 4106 scale(0x0); | |
| 4107 disp(0x0); | |
| 4108 %} | |
| 4109 %} | |
| 4110 | |
| 4111 // // ------------------------------------------------------------------------- | |
| 4112 // // 486 architecture doesn't support "scale * index + offset" with out a base | |
| 4113 // // ------------------------------------------------------------------------- | |
| 4114 // // Scaled Memory Operands | |
| 4115 // // Indirect Memory Times Scale Plus Offset Operand | |
|
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4116 // operand indScaleOffset(immP off, rRegI ireg, immI2 scale) %{ |
| 0 | 4117 // match(AddP off (LShiftI ireg scale)); |
| 4118 // | |
| 4119 // op_cost(10); | |
| 4120 // format %{"[$off + $ireg << $scale]" %} | |
| 4121 // interface(MEMORY_INTER) %{ | |
| 4122 // base(0x4); | |
| 4123 // index($ireg); | |
| 4124 // scale($scale); | |
| 4125 // disp($off); | |
| 4126 // %} | |
| 4127 // %} | |
| 4128 | |
| 4129 // Indirect Memory Times Scale Plus Index Register | |
|
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4130 operand indIndexScale(eRegP reg, rRegI ireg, immI2 scale) %{ |
| 0 | 4131 match(AddP reg (LShiftI ireg scale)); |
| 4132 | |
| 4133 op_cost(10); | |
| 4134 format %{"[$reg + $ireg << $scale]" %} | |
| 4135 interface(MEMORY_INTER) %{ | |
| 4136 base($reg); | |
| 4137 index($ireg); | |
| 4138 scale($scale); | |
| 4139 disp(0x0); | |
| 4140 %} | |
| 4141 %} | |
| 4142 | |
| 4143 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand | |
|
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4144 operand indIndexScaleOffset(eRegP reg, immI off, rRegI ireg, immI2 scale) %{ |
| 0 | 4145 match(AddP (AddP reg (LShiftI ireg scale)) off); |
| 4146 | |
| 4147 op_cost(10); | |
| 4148 format %{"[$reg + $off + $ireg << $scale]" %} | |
| 4149 interface(MEMORY_INTER) %{ | |
| 4150 base($reg); | |
| 4151 index($ireg); | |
| 4152 scale($scale); | |
| 4153 disp($off); | |
| 4154 %} | |
| 4155 %} | |
| 4156 | |
| 4157 //----------Load Long Memory Operands------------------------------------------ | |
| 4158 // The load-long idiom will use it's address expression again after loading | |
| 4159 // the first word of the long. If the load-long destination overlaps with | |
| 4160 // registers used in the addressing expression, the 2nd half will be loaded | |
| 4161 // from a clobbered address. Fix this by requiring that load-long use | |
| 4162 // address registers that do not overlap with the load-long target. | |
| 4163 | |
| 4164 // load-long support | |
| 4165 operand load_long_RegP() %{ | |
| 4166 constraint(ALLOC_IN_RC(esi_reg)); | |
| 4167 match(RegP); | |
| 4168 match(eSIRegP); | |
| 4169 op_cost(100); | |
| 4170 format %{ %} | |
| 4171 interface(REG_INTER); | |
| 4172 %} | |
| 4173 | |
| 4174 // Indirect Memory Operand Long | |
| 4175 operand load_long_indirect(load_long_RegP reg) %{ | |
| 4176 constraint(ALLOC_IN_RC(esi_reg)); | |
| 4177 match(reg); | |
| 4178 | |
| 4179 format %{ "[$reg]" %} | |
| 4180 interface(MEMORY_INTER) %{ | |
| 4181 base($reg); | |
| 4182 index(0x4); | |
| 4183 scale(0x0); | |
| 4184 disp(0x0); | |
| 4185 %} | |
| 4186 %} | |
| 4187 | |
| 4188 // Indirect Memory Plus Long Offset Operand | |
| 4189 operand load_long_indOffset32(load_long_RegP reg, immI off) %{ | |
| 4190 match(AddP reg off); | |
| 4191 | |
| 4192 format %{ "[$reg + $off]" %} | |
| 4193 interface(MEMORY_INTER) %{ | |
| 4194 base($reg); | |
| 4195 index(0x4); | |
| 4196 scale(0x0); | |
| 4197 disp($off); | |
| 4198 %} | |
| 4199 %} | |
| 4200 | |
| 4201 opclass load_long_memory(load_long_indirect, load_long_indOffset32); | |
| 4202 | |
| 4203 | |
| 4204 //----------Special Memory Operands-------------------------------------------- | |
| 4205 // Stack Slot Operand - This operand is used for loading and storing temporary | |
| 4206 // values on the stack where a match requires a value to | |
| 4207 // flow through memory. | |
| 4208 operand stackSlotP(sRegP reg) %{ | |
| 4209 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4210 // No match rule because this operand is only generated in matching | |
| 4211 format %{ "[$reg]" %} | |
| 4212 interface(MEMORY_INTER) %{ | |
| 4213 base(0x4); // ESP | |
| 4214 index(0x4); // No Index | |
| 4215 scale(0x0); // No Scale | |
| 4216 disp($reg); // Stack Offset | |
| 4217 %} | |
| 4218 %} | |
| 4219 | |
| 4220 operand stackSlotI(sRegI reg) %{ | |
| 4221 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4222 // No match rule because this operand is only generated in matching | |
| 4223 format %{ "[$reg]" %} | |
| 4224 interface(MEMORY_INTER) %{ | |
| 4225 base(0x4); // ESP | |
| 4226 index(0x4); // No Index | |
| 4227 scale(0x0); // No Scale | |
| 4228 disp($reg); // Stack Offset | |
| 4229 %} | |
| 4230 %} | |
| 4231 | |
| 4232 operand stackSlotF(sRegF reg) %{ | |
| 4233 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4234 // No match rule because this operand is only generated in matching | |
| 4235 format %{ "[$reg]" %} | |
| 4236 interface(MEMORY_INTER) %{ | |
| 4237 base(0x4); // ESP | |
| 4238 index(0x4); // No Index | |
| 4239 scale(0x0); // No Scale | |
| 4240 disp($reg); // Stack Offset | |
| 4241 %} | |
| 4242 %} | |
| 4243 | |
| 4244 operand stackSlotD(sRegD reg) %{ | |
| 4245 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4246 // No match rule because this operand is only generated in matching | |
| 4247 format %{ "[$reg]" %} | |
| 4248 interface(MEMORY_INTER) %{ | |
| 4249 base(0x4); // ESP | |
| 4250 index(0x4); // No Index | |
| 4251 scale(0x0); // No Scale | |
| 4252 disp($reg); // Stack Offset | |
| 4253 %} | |
| 4254 %} | |
| 4255 | |
| 4256 operand stackSlotL(sRegL reg) %{ | |
| 4257 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4258 // No match rule because this operand is only generated in matching | |
| 4259 format %{ "[$reg]" %} | |
| 4260 interface(MEMORY_INTER) %{ | |
| 4261 base(0x4); // ESP | |
| 4262 index(0x4); // No Index | |
| 4263 scale(0x0); // No Scale | |
| 4264 disp($reg); // Stack Offset | |
| 4265 %} | |
| 4266 %} | |
| 4267 | |
| 4268 //----------Memory Operands - Win95 Implicit Null Variants---------------- | |
| 4269 // Indirect Memory Operand | |
| 4270 operand indirect_win95_safe(eRegP_no_EBP reg) | |
| 4271 %{ | |
|
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4272 constraint(ALLOC_IN_RC(int_reg)); |
| 0 | 4273 match(reg); |
| 4274 | |
| 4275 op_cost(100); | |
| 4276 format %{ "[$reg]" %} | |
| 4277 interface(MEMORY_INTER) %{ | |
| 4278 base($reg); | |
| 4279 index(0x4); | |
| 4280 scale(0x0); | |
| 4281 disp(0x0); | |
| 4282 %} | |
| 4283 %} | |
| 4284 | |
| 4285 // Indirect Memory Plus Short Offset Operand | |
| 4286 operand indOffset8_win95_safe(eRegP_no_EBP reg, immI8 off) | |
| 4287 %{ | |
| 4288 match(AddP reg off); | |
| 4289 | |
| 4290 op_cost(100); | |
| 4291 format %{ "[$reg + $off]" %} | |
| 4292 interface(MEMORY_INTER) %{ | |
| 4293 base($reg); | |
| 4294 index(0x4); | |
| 4295 scale(0x0); | |
| 4296 disp($off); | |
| 4297 %} | |
| 4298 %} | |
| 4299 | |
| 4300 // Indirect Memory Plus Long Offset Operand | |
| 4301 operand indOffset32_win95_safe(eRegP_no_EBP reg, immI off) | |
| 4302 %{ | |
| 4303 match(AddP reg off); | |
| 4304 | |
| 4305 op_cost(100); | |
| 4306 format %{ "[$reg + $off]" %} | |
| 4307 interface(MEMORY_INTER) %{ | |
| 4308 base($reg); | |
| 4309 index(0x4); | |
| 4310 scale(0x0); | |
| 4311 disp($off); | |
| 4312 %} | |
| 4313 %} | |
| 4314 | |
| 4315 // Indirect Memory Plus Index Register Plus Offset Operand | |
|
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4316 operand indIndexOffset_win95_safe(eRegP_no_EBP reg, rRegI ireg, immI off) |
| 0 | 4317 %{ |
| 4318 match(AddP (AddP reg ireg) off); | |
| 4319 | |
| 4320 op_cost(100); | |
| 4321 format %{"[$reg + $off + $ireg]" %} | |
| 4322 interface(MEMORY_INTER) %{ | |
| 4323 base($reg); | |
| 4324 index($ireg); | |
| 4325 scale(0x0); | |
| 4326 disp($off); | |
| 4327 %} | |
| 4328 %} | |
| 4329 | |
| 4330 // Indirect Memory Times Scale Plus Index Register | |
|
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4331 operand indIndexScale_win95_safe(eRegP_no_EBP reg, rRegI ireg, immI2 scale) |
| 0 | 4332 %{ |
| 4333 match(AddP reg (LShiftI ireg scale)); | |
| 4334 | |
| 4335 op_cost(100); | |
| 4336 format %{"[$reg + $ireg << $scale]" %} | |
| 4337 interface(MEMORY_INTER) %{ | |
| 4338 base($reg); | |
| 4339 index($ireg); | |
| 4340 scale($scale); | |
| 4341 disp(0x0); | |
| 4342 %} | |
| 4343 %} | |
| 4344 | |
| 4345 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand | |
|
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4346 operand indIndexScaleOffset_win95_safe(eRegP_no_EBP reg, immI off, rRegI ireg, immI2 scale) |
| 0 | 4347 %{ |
| 4348 match(AddP (AddP reg (LShiftI ireg scale)) off); | |
| 4349 | |
| 4350 op_cost(100); | |
| 4351 format %{"[$reg + $off + $ireg << $scale]" %} | |
| 4352 interface(MEMORY_INTER) %{ | |
| 4353 base($reg); | |
| 4354 index($ireg); | |
| 4355 scale($scale); | |
| 4356 disp($off); | |
| 4357 %} | |
| 4358 %} | |
| 4359 | |
| 4360 //----------Conditional Branch Operands---------------------------------------- | |
| 4361 // Comparison Op - This is the operation of the comparison, and is limited to | |
| 4362 // the following set of codes: | |
| 4363 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=) | |
| 4364 // | |
| 4365 // Other attributes of the comparison, such as unsignedness, are specified | |
| 4366 // by the comparison instruction that sets a condition code flags register. | |
| 4367 // That result is represented by a flags operand whose subtype is appropriate | |
| 4368 // to the unsignedness (etc.) of the comparison. | |
| 4369 // | |
| 4370 // Later, the instruction which matches both the Comparison Op (a Bool) and | |
| 4371 // the flags (produced by the Cmp) specifies the coding of the comparison op | |
| 4372 // by matching a specific subtype of Bool operand below, such as cmpOpU. | |
| 4373 | |
| 4374 // Comparision Code | |
| 4375 operand cmpOp() %{ | |
| 4376 match(Bool); | |
| 4377 | |
| 4378 format %{ "" %} | |
| 4379 interface(COND_INTER) %{ | |
|
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|
4380 equal(0x4, "e"); |
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4381 not_equal(0x5, "ne"); |
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4382 less(0xC, "l"); |
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4383 greater_equal(0xD, "ge"); |
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4384 less_equal(0xE, "le"); |
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|
4385 greater(0xF, "g"); |
| 12323 | 4386 overflow(0x0, "o"); |
| 4387 no_overflow(0x1, "no"); | |
| 0 | 4388 %} |
| 4389 %} | |
| 4390 | |
| 4391 // Comparison Code, unsigned compare. Used by FP also, with | |
| 4392 // C2 (unordered) turned into GT or LT already. The other bits | |
| 4393 // C0 and C3 are turned into Carry & Zero flags. | |
| 4394 operand cmpOpU() %{ | |
| 4395 match(Bool); | |
| 4396 | |
| 4397 format %{ "" %} | |
| 4398 interface(COND_INTER) %{ | |
|
415
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4399 equal(0x4, "e"); |
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|
4400 not_equal(0x5, "ne"); |
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|
4401 less(0x2, "b"); |
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|
4402 greater_equal(0x3, "nb"); |
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|
4403 less_equal(0x6, "be"); |
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|
4404 greater(0x7, "nbe"); |
| 12323 | 4405 overflow(0x0, "o"); |
| 4406 no_overflow(0x1, "no"); | |
|
415
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|
4407 %} |
|
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|
4408 %} |
|
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|
4409 |
|
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|
4410 // Floating comparisons that don't require any fixup for the unordered case |
|
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4411 operand cmpOpUCF() %{ |
|
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4412 match(Bool); |
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|
4413 predicate(n->as_Bool()->_test._test == BoolTest::lt || |
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4414 n->as_Bool()->_test._test == BoolTest::ge || |
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4415 n->as_Bool()->_test._test == BoolTest::le || |
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4416 n->as_Bool()->_test._test == BoolTest::gt); |
|
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|
4417 format %{ "" %} |
|
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|
4418 interface(COND_INTER) %{ |
|
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|
4419 equal(0x4, "e"); |
|
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|
4420 not_equal(0x5, "ne"); |
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|
4421 less(0x2, "b"); |
|
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|
4422 greater_equal(0x3, "nb"); |
|
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|
4423 less_equal(0x6, "be"); |
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|
4424 greater(0x7, "nbe"); |
| 12323 | 4425 overflow(0x0, "o"); |
| 4426 no_overflow(0x1, "no"); | |
|
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|
4427 %} |
|
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|
4428 %} |
|
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|
4429 |
|
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|
4430 |
|
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|
4431 // Floating comparisons that can be fixed up with extra conditional jumps |
|
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|
4432 operand cmpOpUCF2() %{ |
|
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|
4433 match(Bool); |
|
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|
4434 predicate(n->as_Bool()->_test._test == BoolTest::ne || |
|
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|
4435 n->as_Bool()->_test._test == BoolTest::eq); |
|
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|
4436 format %{ "" %} |
|
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|
4437 interface(COND_INTER) %{ |
|
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|
4438 equal(0x4, "e"); |
|
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|
4439 not_equal(0x5, "ne"); |
|
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|
4440 less(0x2, "b"); |
|
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|
4441 greater_equal(0x3, "nb"); |
|
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|
4442 less_equal(0x6, "be"); |
|
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|
4443 greater(0x7, "nbe"); |
| 12323 | 4444 overflow(0x0, "o"); |
| 4445 no_overflow(0x1, "no"); | |
| 0 | 4446 %} |
| 4447 %} | |
| 4448 | |
| 4449 // Comparison Code for FP conditional move | |
| 4450 operand cmpOp_fcmov() %{ | |
| 4451 match(Bool); | |
| 4452 | |
| 12323 | 4453 predicate(n->as_Bool()->_test._test != BoolTest::overflow && |
| 4454 n->as_Bool()->_test._test != BoolTest::no_overflow); | |
| 0 | 4455 format %{ "" %} |
| 4456 interface(COND_INTER) %{ | |
| 4457 equal (0x0C8); | |
| 4458 not_equal (0x1C8); | |
| 4459 less (0x0C0); | |
| 4460 greater_equal(0x1C0); | |
| 4461 less_equal (0x0D0); | |
| 4462 greater (0x1D0); | |
| 12323 | 4463 overflow(0x0, "o"); // not really supported by the instruction |
| 4464 no_overflow(0x1, "no"); // not really supported by the instruction | |
| 0 | 4465 %} |
| 4466 %} | |
| 4467 | |
| 4468 // Comparision Code used in long compares | |
| 4469 operand cmpOp_commute() %{ | |
| 4470 match(Bool); | |
| 4471 | |
| 4472 format %{ "" %} | |
| 4473 interface(COND_INTER) %{ | |
|
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|
4474 equal(0x4, "e"); |
|
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|
4475 not_equal(0x5, "ne"); |
|
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|
4476 less(0xF, "g"); |
|
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|
4477 greater_equal(0xE, "le"); |
|
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|
4478 less_equal(0xD, "ge"); |
|
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|
4479 greater(0xC, "l"); |
| 12323 | 4480 overflow(0x0, "o"); |
| 4481 no_overflow(0x1, "no"); | |
| 0 | 4482 %} |
| 4483 %} | |
| 4484 | |
| 4485 //----------OPERAND CLASSES---------------------------------------------------- | |
| 4486 // Operand Classes are groups of operands that are used as to simplify | |
| 605 | 4487 // instruction definitions by not requiring the AD writer to specify separate |
| 0 | 4488 // instructions for every form of operand when the instruction accepts |
| 4489 // multiple operand types with the same basic encoding and format. The classic | |
| 4490 // case of this is memory operands. | |
| 4491 | |
| 4492 opclass memory(direct, indirect, indOffset8, indOffset32, indOffset32X, indIndexOffset, | |
| 4493 indIndex, indIndexScale, indIndexScaleOffset); | |
| 4494 | |
| 4495 // Long memory operations are encoded in 2 instructions and a +4 offset. | |
| 4496 // This means some kind of offset is always required and you cannot use | |
| 4497 // an oop as the offset (done when working on static globals). | |
| 4498 opclass long_memory(direct, indirect, indOffset8, indOffset32, indIndexOffset, | |
| 4499 indIndex, indIndexScale, indIndexScaleOffset); | |
| 4500 | |
| 4501 | |
| 4502 //----------PIPELINE----------------------------------------------------------- | |
| 4503 // Rules which define the behavior of the target architectures pipeline. | |
| 4504 pipeline %{ | |
| 4505 | |
| 4506 //----------ATTRIBUTES--------------------------------------------------------- | |
| 4507 attributes %{ | |
| 4508 variable_size_instructions; // Fixed size instructions | |
| 4509 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle | |
| 4510 instruction_unit_size = 1; // An instruction is 1 bytes long | |
| 4511 instruction_fetch_unit_size = 16; // The processor fetches one line | |
| 4512 instruction_fetch_units = 1; // of 16 bytes | |
| 4513 | |
| 4514 // List of nop instructions | |
| 4515 nops( MachNop ); | |
| 4516 %} | |
| 4517 | |
| 4518 //----------RESOURCES---------------------------------------------------------- | |
| 4519 // Resources are the functional units available to the machine | |
| 4520 | |
| 4521 // Generic P2/P3 pipeline | |
| 4522 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of | |
| 4523 // 3 instructions decoded per cycle. | |
| 4524 // 2 load/store ops per cycle, 1 branch, 1 FPU, | |
| 4525 // 2 ALU op, only ALU0 handles mul/div instructions. | |
| 4526 resources( D0, D1, D2, DECODE = D0 | D1 | D2, | |
| 4527 MS0, MS1, MEM = MS0 | MS1, | |
| 4528 BR, FPU, | |
| 4529 ALU0, ALU1, ALU = ALU0 | ALU1 ); | |
| 4530 | |
| 4531 //----------PIPELINE DESCRIPTION----------------------------------------------- | |
| 4532 // Pipeline Description specifies the stages in the machine's pipeline | |
| 4533 | |
| 4534 // Generic P2/P3 pipeline | |
| 4535 pipe_desc(S0, S1, S2, S3, S4, S5); | |
| 4536 | |
| 4537 //----------PIPELINE CLASSES--------------------------------------------------- | |
| 4538 // Pipeline Classes describe the stages in which input and output are | |
| 4539 // referenced by the hardware pipeline. | |
| 4540 | |
| 4541 // Naming convention: ialu or fpu | |
| 4542 // Then: _reg | |
| 4543 // Then: _reg if there is a 2nd register | |
| 4544 // Then: _long if it's a pair of instructions implementing a long | |
| 4545 // Then: _fat if it requires the big decoder | |
| 4546 // Or: _mem if it requires the big decoder and a memory unit. | |
| 4547 | |
| 4548 // Integer ALU reg operation | |
|
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4549 pipe_class ialu_reg(rRegI dst) %{ |
| 0 | 4550 single_instruction; |
| 4551 dst : S4(write); | |
| 4552 dst : S3(read); | |
| 4553 DECODE : S0; // any decoder | |
| 4554 ALU : S3; // any alu | |
| 4555 %} | |
| 4556 | |
| 4557 // Long ALU reg operation | |
| 4558 pipe_class ialu_reg_long(eRegL dst) %{ | |
| 4559 instruction_count(2); | |
| 4560 dst : S4(write); | |
| 4561 dst : S3(read); | |
| 4562 DECODE : S0(2); // any 2 decoders | |
| 4563 ALU : S3(2); // both alus | |
| 4564 %} | |
| 4565 | |
| 4566 // Integer ALU reg operation using big decoder | |
|
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4567 pipe_class ialu_reg_fat(rRegI dst) %{ |
| 0 | 4568 single_instruction; |
| 4569 dst : S4(write); | |
| 4570 dst : S3(read); | |
| 4571 D0 : S0; // big decoder only | |
| 4572 ALU : S3; // any alu | |
| 4573 %} | |
| 4574 | |
| 4575 // Long ALU reg operation using big decoder | |
| 4576 pipe_class ialu_reg_long_fat(eRegL dst) %{ | |
| 4577 instruction_count(2); | |
| 4578 dst : S4(write); | |
| 4579 dst : S3(read); | |
| 4580 D0 : S0(2); // big decoder only; twice | |
| 4581 ALU : S3(2); // any 2 alus | |
| 4582 %} | |
| 4583 | |
| 4584 // Integer ALU reg-reg operation | |
|
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4585 pipe_class ialu_reg_reg(rRegI dst, rRegI src) %{ |
| 0 | 4586 single_instruction; |
| 4587 dst : S4(write); | |
| 4588 src : S3(read); | |
| 4589 DECODE : S0; // any decoder | |
| 4590 ALU : S3; // any alu | |
| 4591 %} | |
| 4592 | |
| 4593 // Long ALU reg-reg operation | |
| 4594 pipe_class ialu_reg_reg_long(eRegL dst, eRegL src) %{ | |
| 4595 instruction_count(2); | |
| 4596 dst : S4(write); | |
| 4597 src : S3(read); | |
| 4598 DECODE : S0(2); // any 2 decoders | |
| 4599 ALU : S3(2); // both alus | |
| 4600 %} | |
| 4601 | |
| 4602 // Integer ALU reg-reg operation | |
|
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|
4603 pipe_class ialu_reg_reg_fat(rRegI dst, memory src) %{ |
| 0 | 4604 single_instruction; |
| 4605 dst : S4(write); | |
| 4606 src : S3(read); | |
| 4607 D0 : S0; // big decoder only | |
| 4608 ALU : S3; // any alu | |
| 4609 %} | |
| 4610 | |
| 4611 // Long ALU reg-reg operation | |
| 4612 pipe_class ialu_reg_reg_long_fat(eRegL dst, eRegL src) %{ | |
| 4613 instruction_count(2); | |
| 4614 dst : S4(write); | |
| 4615 src : S3(read); | |
| 4616 D0 : S0(2); // big decoder only; twice | |
| 4617 ALU : S3(2); // both alus | |
| 4618 %} | |
| 4619 | |
| 4620 // Integer ALU reg-mem operation | |
|
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|
4621 pipe_class ialu_reg_mem(rRegI dst, memory mem) %{ |
| 0 | 4622 single_instruction; |
| 4623 dst : S5(write); | |
| 4624 mem : S3(read); | |
| 4625 D0 : S0; // big decoder only | |
| 4626 ALU : S4; // any alu | |
| 4627 MEM : S3; // any mem | |
| 4628 %} | |
| 4629 | |
| 4630 // Long ALU reg-mem operation | |
| 4631 pipe_class ialu_reg_long_mem(eRegL dst, load_long_memory mem) %{ | |
| 4632 instruction_count(2); | |
| 4633 dst : S5(write); | |
| 4634 mem : S3(read); | |
| 4635 D0 : S0(2); // big decoder only; twice | |
| 4636 ALU : S4(2); // any 2 alus | |
| 4637 MEM : S3(2); // both mems | |
| 4638 %} | |
| 4639 | |
| 4640 // Integer mem operation (prefetch) | |
| 4641 pipe_class ialu_mem(memory mem) | |
| 4642 %{ | |
| 4643 single_instruction; | |
| 4644 mem : S3(read); | |
| 4645 D0 : S0; // big decoder only | |
| 4646 MEM : S3; // any mem | |
| 4647 %} | |
| 4648 | |
| 4649 // Integer Store to Memory | |
|
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|
4650 pipe_class ialu_mem_reg(memory mem, rRegI src) %{ |
| 0 | 4651 single_instruction; |
| 4652 mem : S3(read); | |
| 4653 src : S5(read); | |
| 4654 D0 : S0; // big decoder only | |
| 4655 ALU : S4; // any alu | |
| 4656 MEM : S3; | |
| 4657 %} | |
| 4658 | |
| 4659 // Long Store to Memory | |
| 4660 pipe_class ialu_mem_long_reg(memory mem, eRegL src) %{ | |
| 4661 instruction_count(2); | |
| 4662 mem : S3(read); | |
| 4663 src : S5(read); | |
| 4664 D0 : S0(2); // big decoder only; twice | |
| 4665 ALU : S4(2); // any 2 alus | |
| 4666 MEM : S3(2); // Both mems | |
| 4667 %} | |
| 4668 | |
| 4669 // Integer Store to Memory | |
| 4670 pipe_class ialu_mem_imm(memory mem) %{ | |
| 4671 single_instruction; | |
| 4672 mem : S3(read); | |
| 4673 D0 : S0; // big decoder only | |
| 4674 ALU : S4; // any alu | |
| 4675 MEM : S3; | |
| 4676 %} | |
| 4677 | |
| 4678 // Integer ALU0 reg-reg operation | |
|
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|
4679 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src) %{ |
| 0 | 4680 single_instruction; |
| 4681 dst : S4(write); | |
| 4682 src : S3(read); | |
| 4683 D0 : S0; // Big decoder only | |
| 4684 ALU0 : S3; // only alu0 | |
| 4685 %} | |
| 4686 | |
| 4687 // Integer ALU0 reg-mem operation | |
|
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|
4688 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem) %{ |
| 0 | 4689 single_instruction; |
| 4690 dst : S5(write); | |
| 4691 mem : S3(read); | |
| 4692 D0 : S0; // big decoder only | |
| 4693 ALU0 : S4; // ALU0 only | |
| 4694 MEM : S3; // any mem | |
| 4695 %} | |
| 4696 | |
| 4697 // Integer ALU reg-reg operation | |
|
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|
4698 pipe_class ialu_cr_reg_reg(eFlagsReg cr, rRegI src1, rRegI src2) %{ |
| 0 | 4699 single_instruction; |
| 4700 cr : S4(write); | |
| 4701 src1 : S3(read); | |
| 4702 src2 : S3(read); | |
| 4703 DECODE : S0; // any decoder | |
| 4704 ALU : S3; // any alu | |
| 4705 %} | |
| 4706 | |
| 4707 // Integer ALU reg-imm operation | |
|
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|
4708 pipe_class ialu_cr_reg_imm(eFlagsReg cr, rRegI src1) %{ |
| 0 | 4709 single_instruction; |
| 4710 cr : S4(write); | |
| 4711 src1 : S3(read); | |
| 4712 DECODE : S0; // any decoder | |
| 4713 ALU : S3; // any alu | |
| 4714 %} | |
| 4715 | |
| 4716 // Integer ALU reg-mem operation | |
|
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|
4717 pipe_class ialu_cr_reg_mem(eFlagsReg cr, rRegI src1, memory src2) %{ |
| 0 | 4718 single_instruction; |
| 4719 cr : S4(write); | |
| 4720 src1 : S3(read); | |
| 4721 src2 : S3(read); | |
| 4722 D0 : S0; // big decoder only | |
| 4723 ALU : S4; // any alu | |
| 4724 MEM : S3; | |
| 4725 %} | |
| 4726 | |
| 4727 // Conditional move reg-reg | |
|
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|
4728 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y ) %{ |
| 0 | 4729 instruction_count(4); |
| 4730 y : S4(read); | |
| 4731 q : S3(read); | |
| 4732 p : S3(read); | |
| 4733 DECODE : S0(4); // any decoder | |
| 4734 %} | |
| 4735 | |
| 4736 // Conditional move reg-reg | |
|
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|
4737 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, eFlagsReg cr ) %{ |
| 0 | 4738 single_instruction; |
| 4739 dst : S4(write); | |
| 4740 src : S3(read); | |
| 4741 cr : S3(read); | |
| 4742 DECODE : S0; // any decoder | |
| 4743 %} | |
| 4744 | |
| 4745 // Conditional move reg-mem | |
|
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|
4746 pipe_class pipe_cmov_mem( eFlagsReg cr, rRegI dst, memory src) %{ |
| 0 | 4747 single_instruction; |
| 4748 dst : S4(write); | |
| 4749 src : S3(read); | |
| 4750 cr : S3(read); | |
| 4751 DECODE : S0; // any decoder | |
| 4752 MEM : S3; | |
| 4753 %} | |
| 4754 | |
| 4755 // Conditional move reg-reg long | |
| 4756 pipe_class pipe_cmov_reg_long( eFlagsReg cr, eRegL dst, eRegL src) %{ | |
| 4757 single_instruction; | |
| 4758 dst : S4(write); | |
| 4759 src : S3(read); | |
| 4760 cr : S3(read); | |
| 4761 DECODE : S0(2); // any 2 decoders | |
| 4762 %} | |
| 4763 | |
| 4764 // Conditional move double reg-reg | |
|
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|
4765 pipe_class pipe_cmovDPR_reg( eFlagsReg cr, regDPR1 dst, regDPR src) %{ |
| 0 | 4766 single_instruction; |
| 4767 dst : S4(write); | |
| 4768 src : S3(read); | |
| 4769 cr : S3(read); | |
| 4770 DECODE : S0; // any decoder | |
| 4771 %} | |
| 4772 | |
| 4773 // Float reg-reg operation | |
|
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|
4774 pipe_class fpu_reg(regDPR dst) %{ |
| 0 | 4775 instruction_count(2); |
| 4776 dst : S3(read); | |
| 4777 DECODE : S0(2); // any 2 decoders | |
| 4778 FPU : S3; | |
| 4779 %} | |
| 4780 | |
| 4781 // Float reg-reg operation | |
|
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|
4782 pipe_class fpu_reg_reg(regDPR dst, regDPR src) %{ |
| 0 | 4783 instruction_count(2); |
| 4784 dst : S4(write); | |
| 4785 src : S3(read); | |
| 4786 DECODE : S0(2); // any 2 decoders | |
| 4787 FPU : S3; | |
| 4788 %} | |
| 4789 | |
| 4790 // Float reg-reg operation | |
|
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4791 pipe_class fpu_reg_reg_reg(regDPR dst, regDPR src1, regDPR src2) %{ |
| 0 | 4792 instruction_count(3); |
| 4793 dst : S4(write); | |
| 4794 src1 : S3(read); | |
| 4795 src2 : S3(read); | |
| 4796 DECODE : S0(3); // any 3 decoders | |
| 4797 FPU : S3(2); | |
| 4798 %} | |
| 4799 | |
| 4800 // Float reg-reg operation | |
|
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4801 pipe_class fpu_reg_reg_reg_reg(regDPR dst, regDPR src1, regDPR src2, regDPR src3) %{ |
| 0 | 4802 instruction_count(4); |
| 4803 dst : S4(write); | |
| 4804 src1 : S3(read); | |
| 4805 src2 : S3(read); | |
| 4806 src3 : S3(read); | |
| 4807 DECODE : S0(4); // any 3 decoders | |
| 4808 FPU : S3(2); | |
| 4809 %} | |
| 4810 | |
| 4811 // Float reg-reg operation | |
|
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|
4812 pipe_class fpu_reg_mem_reg_reg(regDPR dst, memory src1, regDPR src2, regDPR src3) %{ |
| 0 | 4813 instruction_count(4); |
| 4814 dst : S4(write); | |
| 4815 src1 : S3(read); | |
| 4816 src2 : S3(read); | |
| 4817 src3 : S3(read); | |
| 4818 DECODE : S1(3); // any 3 decoders | |
| 4819 D0 : S0; // Big decoder only | |
| 4820 FPU : S3(2); | |
| 4821 MEM : S3; | |
| 4822 %} | |
| 4823 | |
| 4824 // Float reg-mem operation | |
|
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|
4825 pipe_class fpu_reg_mem(regDPR dst, memory mem) %{ |
| 0 | 4826 instruction_count(2); |
| 4827 dst : S5(write); | |
| 4828 mem : S3(read); | |
| 4829 D0 : S0; // big decoder only | |
| 4830 DECODE : S1; // any decoder for FPU POP | |
| 4831 FPU : S4; | |
| 4832 MEM : S3; // any mem | |
| 4833 %} | |
| 4834 | |
| 4835 // Float reg-mem operation | |
|
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diff
changeset
|
4836 pipe_class fpu_reg_reg_mem(regDPR dst, regDPR src1, memory mem) %{ |
| 0 | 4837 instruction_count(3); |
| 4838 dst : S5(write); | |
| 4839 src1 : S3(read); | |
| 4840 mem : S3(read); | |
| 4841 D0 : S0; // big decoder only | |
| 4842 DECODE : S1(2); // any decoder for FPU POP | |
| 4843 FPU : S4; | |
| 4844 MEM : S3; // any mem | |
| 4845 %} | |
| 4846 | |
| 4847 // Float mem-reg operation | |
|
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|
4848 pipe_class fpu_mem_reg(memory mem, regDPR src) %{ |
| 0 | 4849 instruction_count(2); |
| 4850 src : S5(read); | |
| 4851 mem : S3(read); | |
| 4852 DECODE : S0; // any decoder for FPU PUSH | |
| 4853 D0 : S1; // big decoder only | |
| 4854 FPU : S4; | |
| 4855 MEM : S3; // any mem | |
| 4856 %} | |
| 4857 | |
|
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|
4858 pipe_class fpu_mem_reg_reg(memory mem, regDPR src1, regDPR src2) %{ |
| 0 | 4859 instruction_count(3); |
| 4860 src1 : S3(read); | |
| 4861 src2 : S3(read); | |
| 4862 mem : S3(read); | |
| 4863 DECODE : S0(2); // any decoder for FPU PUSH | |
| 4864 D0 : S1; // big decoder only | |
| 4865 FPU : S4; | |
| 4866 MEM : S3; // any mem | |
| 4867 %} | |
| 4868 | |
|
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|
4869 pipe_class fpu_mem_reg_mem(memory mem, regDPR src1, memory src2) %{ |
| 0 | 4870 instruction_count(3); |
| 4871 src1 : S3(read); | |
| 4872 src2 : S3(read); | |
| 4873 mem : S4(read); | |
| 4874 DECODE : S0; // any decoder for FPU PUSH | |
| 4875 D0 : S0(2); // big decoder only | |
| 4876 FPU : S4; | |
| 4877 MEM : S3(2); // any mem | |
| 4878 %} | |
| 4879 | |
| 4880 pipe_class fpu_mem_mem(memory dst, memory src1) %{ | |
| 4881 instruction_count(2); | |
| 4882 src1 : S3(read); | |
| 4883 dst : S4(read); | |
| 4884 D0 : S0(2); // big decoder only | |
| 4885 MEM : S3(2); // any mem | |
| 4886 %} | |
| 4887 | |
| 4888 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2) %{ | |
| 4889 instruction_count(3); | |
| 4890 src1 : S3(read); | |
| 4891 src2 : S3(read); | |
| 4892 dst : S4(read); | |
| 4893 D0 : S0(3); // big decoder only | |
| 4894 FPU : S4; | |
| 4895 MEM : S3(3); // any mem | |
| 4896 %} | |
| 4897 | |
|
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|
4898 pipe_class fpu_mem_reg_con(memory mem, regDPR src1) %{ |
| 0 | 4899 instruction_count(3); |
| 4900 src1 : S4(read); | |
| 4901 mem : S4(read); | |
| 4902 DECODE : S0; // any decoder for FPU PUSH | |
| 4903 D0 : S0(2); // big decoder only | |
| 4904 FPU : S4; | |
| 4905 MEM : S3(2); // any mem | |
| 4906 %} | |
| 4907 | |
| 4908 // Float load constant | |
|
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|
4909 pipe_class fpu_reg_con(regDPR dst) %{ |
| 0 | 4910 instruction_count(2); |
| 4911 dst : S5(write); | |
| 4912 D0 : S0; // big decoder only for the load | |
| 4913 DECODE : S1; // any decoder for FPU POP | |
| 4914 FPU : S4; | |
| 4915 MEM : S3; // any mem | |
| 4916 %} | |
| 4917 | |
| 4918 // Float load constant | |
|
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|
4919 pipe_class fpu_reg_reg_con(regDPR dst, regDPR src) %{ |
| 0 | 4920 instruction_count(3); |
| 4921 dst : S5(write); | |
| 4922 src : S3(read); | |
| 4923 D0 : S0; // big decoder only for the load | |
| 4924 DECODE : S1(2); // any decoder for FPU POP | |
| 4925 FPU : S4; | |
| 4926 MEM : S3; // any mem | |
| 4927 %} | |
| 4928 | |
| 4929 // UnConditional branch | |
| 4930 pipe_class pipe_jmp( label labl ) %{ | |
| 4931 single_instruction; | |
| 4932 BR : S3; | |
| 4933 %} | |
| 4934 | |
| 4935 // Conditional branch | |
| 4936 pipe_class pipe_jcc( cmpOp cmp, eFlagsReg cr, label labl ) %{ | |
| 4937 single_instruction; | |
| 4938 cr : S1(read); | |
| 4939 BR : S3; | |
| 4940 %} | |
| 4941 | |
| 4942 // Allocation idiom | |
| 4943 pipe_class pipe_cmpxchg( eRegP dst, eRegP heap_ptr ) %{ | |
| 4944 instruction_count(1); force_serialization; | |
| 4945 fixed_latency(6); | |
| 4946 heap_ptr : S3(read); | |
| 4947 DECODE : S0(3); | |
| 4948 D0 : S2; | |
| 4949 MEM : S3; | |
| 4950 ALU : S3(2); | |
| 4951 dst : S5(write); | |
| 4952 BR : S5; | |
| 4953 %} | |
| 4954 | |
| 4955 // Generic big/slow expanded idiom | |
| 4956 pipe_class pipe_slow( ) %{ | |
| 4957 instruction_count(10); multiple_bundles; force_serialization; | |
| 4958 fixed_latency(100); | |
| 4959 D0 : S0(2); | |
| 4960 MEM : S3(2); | |
| 4961 %} | |
| 4962 | |
| 4963 // The real do-nothing guy | |
| 4964 pipe_class empty( ) %{ | |
| 4965 instruction_count(0); | |
| 4966 %} | |
| 4967 | |
| 4968 // Define the class for the Nop node | |
| 4969 define %{ | |
| 4970 MachNop = empty; | |
| 4971 %} | |
| 4972 | |
| 4973 %} | |
| 4974 | |
| 4975 //----------INSTRUCTIONS------------------------------------------------------- | |
| 4976 // | |
| 4977 // match -- States which machine-independent subtree may be replaced | |
| 4978 // by this instruction. | |
| 4979 // ins_cost -- The estimated cost of this instruction is used by instruction | |
| 4980 // selection to identify a minimum cost tree of machine | |
| 4981 // instructions that matches a tree of machine-independent | |
| 4982 // instructions. | |
| 4983 // format -- A string providing the disassembly for this instruction. | |
| 4984 // The value of an instruction's operand may be inserted | |
| 4985 // by referring to it with a '$' prefix. | |
| 4986 // opcode -- Three instruction opcodes may be provided. These are referred | |
| 4987 // to within an encode class as $primary, $secondary, and $tertiary | |
| 4988 // respectively. The primary opcode is commonly used to | |
| 4989 // indicate the type of machine instruction, while secondary | |
| 4990 // and tertiary are often used for prefix options or addressing | |
| 4991 // modes. | |
| 4992 // ins_encode -- A list of encode classes with parameters. The encode class | |
| 4993 // name must have been defined in an 'enc_class' specification | |
| 4994 // in the encode section of the architecture description. | |
| 4995 | |
| 4996 //----------BSWAP-Instruction-------------------------------------------------- | |
|
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|
4997 instruct bytes_reverse_int(rRegI dst) %{ |
| 0 | 4998 match(Set dst (ReverseBytesI dst)); |
| 4999 | |
| 5000 format %{ "BSWAP $dst" %} | |
| 5001 opcode(0x0F, 0xC8); | |
| 5002 ins_encode( OpcP, OpcSReg(dst) ); | |
| 5003 ins_pipe( ialu_reg ); | |
| 5004 %} | |
| 5005 | |
| 5006 instruct bytes_reverse_long(eRegL dst) %{ | |
| 5007 match(Set dst (ReverseBytesL dst)); | |
| 5008 | |
| 5009 format %{ "BSWAP $dst.lo\n\t" | |
| 5010 "BSWAP $dst.hi\n\t" | |
| 5011 "XCHG $dst.lo $dst.hi" %} | |
| 5012 | |
| 5013 ins_cost(125); | |
| 5014 ins_encode( bswap_long_bytes(dst) ); | |
| 5015 ins_pipe( ialu_reg_reg); | |
| 5016 %} | |
| 5017 | |
|
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|
5018 instruct bytes_reverse_unsigned_short(rRegI dst, eFlagsReg cr) %{ |
|
1396
d7f654633cfe
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|
5019 match(Set dst (ReverseBytesUS dst)); |
|
6138
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|
5020 effect(KILL cr); |
|
1396
d7f654633cfe
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1274
diff
changeset
|
5021 |
|
d7f654633cfe
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diff
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|
5022 format %{ "BSWAP $dst\n\t" |
|
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1274
diff
changeset
|
5023 "SHR $dst,16\n\t" %} |
|
d7f654633cfe
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1274
diff
changeset
|
5024 ins_encode %{ |
|
d7f654633cfe
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parents:
1274
diff
changeset
|
5025 __ bswapl($dst$$Register); |
|
d7f654633cfe
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parents:
1274
diff
changeset
|
5026 __ shrl($dst$$Register, 16); |
|
d7f654633cfe
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parents:
1274
diff
changeset
|
5027 %} |
|
d7f654633cfe
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parents:
1274
diff
changeset
|
5028 ins_pipe( ialu_reg ); |
|
d7f654633cfe
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parents:
1274
diff
changeset
|
5029 %} |
|
d7f654633cfe
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parents:
1274
diff
changeset
|
5030 |
|
6179
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|
5031 instruct bytes_reverse_short(rRegI dst, eFlagsReg cr) %{ |
|
1396
d7f654633cfe
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parents:
1274
diff
changeset
|
5032 match(Set dst (ReverseBytesS dst)); |
|
6138
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|
5033 effect(KILL cr); |
|
1396
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parents:
1274
diff
changeset
|
5034 |
|
d7f654633cfe
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diff
changeset
|
5035 format %{ "BSWAP $dst\n\t" |
|
d7f654633cfe
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parents:
1274
diff
changeset
|
5036 "SAR $dst,16\n\t" %} |
|
d7f654633cfe
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parents:
1274
diff
changeset
|
5037 ins_encode %{ |
|
d7f654633cfe
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parents:
1274
diff
changeset
|
5038 __ bswapl($dst$$Register); |
|
d7f654633cfe
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parents:
1274
diff
changeset
|
5039 __ sarl($dst$$Register, 16); |
|
d7f654633cfe
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parents:
1274
diff
changeset
|
5040 %} |
|
d7f654633cfe
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parents:
1274
diff
changeset
|
5041 ins_pipe( ialu_reg ); |
|
d7f654633cfe
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parents:
1274
diff
changeset
|
5042 %} |
|
d7f654633cfe
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parents:
1274
diff
changeset
|
5043 |
| 0 | 5044 |
|
775
93c14e5562c4
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681
diff
changeset
|
5045 //---------- Zeros Count Instructions ------------------------------------------ |
|
93c14e5562c4
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|
5046 |
|
6179
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changeset
|
5047 instruct countLeadingZerosI(rRegI dst, rRegI src, eFlagsReg cr) %{ |
|
775
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6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
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681
diff
changeset
|
5048 predicate(UseCountLeadingZerosInstruction); |
|
93c14e5562c4
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681
diff
changeset
|
5049 match(Set dst (CountLeadingZerosI src)); |
|
93c14e5562c4
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681
diff
changeset
|
5050 effect(KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
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parents:
681
diff
changeset
|
5051 |
|
93c14e5562c4
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681
diff
changeset
|
5052 format %{ "LZCNT $dst, $src\t# count leading zeros (int)" %} |
|
93c14e5562c4
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changeset
|
5053 ins_encode %{ |
|
93c14e5562c4
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diff
changeset
|
5054 __ lzcntl($dst$$Register, $src$$Register); |
|
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changeset
|
5055 %} |
|
93c14e5562c4
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changeset
|
5056 ins_pipe(ialu_reg); |
|
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changeset
|
5057 %} |
|
93c14e5562c4
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681
diff
changeset
|
5058 |
|
6179
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changeset
|
5059 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, eFlagsReg cr) %{ |
|
775
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681
diff
changeset
|
5060 predicate(!UseCountLeadingZerosInstruction); |
|
93c14e5562c4
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681
diff
changeset
|
5061 match(Set dst (CountLeadingZerosI src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5062 effect(KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5063 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
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681
diff
changeset
|
5064 format %{ "BSR $dst, $src\t# count leading zeros (int)\n\t" |
|
93c14e5562c4
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681
diff
changeset
|
5065 "JNZ skip\n\t" |
|
93c14e5562c4
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681
diff
changeset
|
5066 "MOV $dst, -1\n" |
|
93c14e5562c4
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681
diff
changeset
|
5067 "skip:\n\t" |
|
93c14e5562c4
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681
diff
changeset
|
5068 "NEG $dst\n\t" |
|
93c14e5562c4
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diff
changeset
|
5069 "ADD $dst, 31" %} |
|
93c14e5562c4
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twisti
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681
diff
changeset
|
5070 ins_encode %{ |
|
93c14e5562c4
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681
diff
changeset
|
5071 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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681
diff
changeset
|
5072 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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681
diff
changeset
|
5073 Label skip; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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681
diff
changeset
|
5074 __ bsrl(Rdst, Rsrc); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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681
diff
changeset
|
5075 __ jccb(Assembler::notZero, skip); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
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681
diff
changeset
|
5076 __ movl(Rdst, -1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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681
diff
changeset
|
5077 __ bind(skip); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
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681
diff
changeset
|
5078 __ negl(Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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681
diff
changeset
|
5079 __ addl(Rdst, BitsPerInt - 1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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681
diff
changeset
|
5080 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5081 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5082 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5083 |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5084 instruct countLeadingZerosL(rRegI dst, eRegL src, eFlagsReg cr) %{ |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5085 predicate(UseCountLeadingZerosInstruction); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5086 match(Set dst (CountLeadingZerosL src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5087 effect(TEMP dst, KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5088 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5089 format %{ "LZCNT $dst, $src.hi\t# count leading zeros (long)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5090 "JNC done\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5091 "LZCNT $dst, $src.lo\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5092 "ADD $dst, 32\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5093 "done:" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5094 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5095 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5096 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5097 Label done; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5098 __ lzcntl(Rdst, HIGH_FROM_LOW(Rsrc)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5099 __ jccb(Assembler::carryClear, done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5100 __ lzcntl(Rdst, Rsrc); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5101 __ addl(Rdst, BitsPerInt); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5102 __ bind(done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5103 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5104 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5105 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5106 |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5107 instruct countLeadingZerosL_bsr(rRegI dst, eRegL src, eFlagsReg cr) %{ |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5108 predicate(!UseCountLeadingZerosInstruction); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5109 match(Set dst (CountLeadingZerosL src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5110 effect(TEMP dst, KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5111 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5112 format %{ "BSR $dst, $src.hi\t# count leading zeros (long)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5113 "JZ msw_is_zero\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5114 "ADD $dst, 32\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5115 "JMP not_zero\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5116 "msw_is_zero:\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5117 "BSR $dst, $src.lo\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5118 "JNZ not_zero\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5119 "MOV $dst, -1\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5120 "not_zero:\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5121 "NEG $dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5122 "ADD $dst, 63\n" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5123 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5124 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5125 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5126 Label msw_is_zero; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5127 Label not_zero; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5128 __ bsrl(Rdst, HIGH_FROM_LOW(Rsrc)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5129 __ jccb(Assembler::zero, msw_is_zero); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5130 __ addl(Rdst, BitsPerInt); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5131 __ jmpb(not_zero); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5132 __ bind(msw_is_zero); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5133 __ bsrl(Rdst, Rsrc); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5134 __ jccb(Assembler::notZero, not_zero); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5135 __ movl(Rdst, -1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5136 __ bind(not_zero); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5137 __ negl(Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5138 __ addl(Rdst, BitsPerLong - 1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5139 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5140 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5141 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5142 |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5143 instruct countTrailingZerosI(rRegI dst, rRegI src, eFlagsReg cr) %{ |
|
17729
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5144 predicate(UseCountTrailingZerosInstruction); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5145 match(Set dst (CountTrailingZerosI src)); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5146 effect(KILL cr); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5147 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5148 format %{ "TZCNT $dst, $src\t# count trailing zeros (int)" %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5149 ins_encode %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5150 __ tzcntl($dst$$Register, $src$$Register); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5151 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5152 ins_pipe(ialu_reg); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5153 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5154 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5155 instruct countTrailingZerosI_bsf(rRegI dst, rRegI src, eFlagsReg cr) %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5156 predicate(!UseCountTrailingZerosInstruction); |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5157 match(Set dst (CountTrailingZerosI src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5158 effect(KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5159 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5160 format %{ "BSF $dst, $src\t# count trailing zeros (int)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5161 "JNZ done\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5162 "MOV $dst, 32\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5163 "done:" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5164 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5165 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5166 Label done; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5167 __ bsfl(Rdst, $src$$Register); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5168 __ jccb(Assembler::notZero, done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5169 __ movl(Rdst, BitsPerInt); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5170 __ bind(done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5171 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5172 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5173 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5174 |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5175 instruct countTrailingZerosL(rRegI dst, eRegL src, eFlagsReg cr) %{ |
|
17729
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5176 predicate(UseCountTrailingZerosInstruction); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5177 match(Set dst (CountTrailingZerosL src)); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5178 effect(TEMP dst, KILL cr); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5179 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5180 format %{ "TZCNT $dst, $src.lo\t# count trailing zeros (long) \n\t" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5181 "JNC done\n\t" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5182 "TZCNT $dst, $src.hi\n\t" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5183 "ADD $dst, 32\n" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5184 "done:" %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5185 ins_encode %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5186 Register Rdst = $dst$$Register; |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5187 Register Rsrc = $src$$Register; |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5188 Label done; |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5189 __ tzcntl(Rdst, Rsrc); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5190 __ jccb(Assembler::carryClear, done); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5191 __ tzcntl(Rdst, HIGH_FROM_LOW(Rsrc)); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5192 __ addl(Rdst, BitsPerInt); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5193 __ bind(done); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5194 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5195 ins_pipe(ialu_reg); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5196 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5197 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5198 instruct countTrailingZerosL_bsf(rRegI dst, eRegL src, eFlagsReg cr) %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
5199 predicate(!UseCountTrailingZerosInstruction); |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5200 match(Set dst (CountTrailingZerosL src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5201 effect(TEMP dst, KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5202 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5203 format %{ "BSF $dst, $src.lo\t# count trailing zeros (long)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5204 "JNZ done\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5205 "BSF $dst, $src.hi\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5206 "JNZ msw_not_zero\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5207 "MOV $dst, 32\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5208 "msw_not_zero:\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5209 "ADD $dst, 32\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5210 "done:" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5211 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5212 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5213 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5214 Label msw_not_zero; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5215 Label done; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5216 __ bsfl(Rdst, Rsrc); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5217 __ jccb(Assembler::notZero, done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5218 __ bsfl(Rdst, HIGH_FROM_LOW(Rsrc)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5219 __ jccb(Assembler::notZero, msw_not_zero); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5220 __ movl(Rdst, BitsPerInt); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5221 __ bind(msw_not_zero); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5222 __ addl(Rdst, BitsPerInt); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5223 __ bind(done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5224 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5225 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5226 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5227 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5228 |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5229 //---------- Population Count Instructions ------------------------------------- |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5230 |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5231 instruct popCountI(rRegI dst, rRegI src, eFlagsReg cr) %{ |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5232 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5233 match(Set dst (PopCountI src)); |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
5234 effect(KILL cr); |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5235 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5236 format %{ "POPCNT $dst, $src" %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5237 ins_encode %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5238 __ popcntl($dst$$Register, $src$$Register); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5239 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5240 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5241 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5242 |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5243 instruct popCountI_mem(rRegI dst, memory mem, eFlagsReg cr) %{ |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5244 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5245 match(Set dst (PopCountI (LoadI mem))); |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
5246 effect(KILL cr); |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5247 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5248 format %{ "POPCNT $dst, $mem" %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5249 ins_encode %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5250 __ popcntl($dst$$Register, $mem$$Address); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5251 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5252 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5253 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5254 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5255 // Note: Long.bitCount(long) returns an int. |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5256 instruct popCountL(rRegI dst, eRegL src, rRegI tmp, eFlagsReg cr) %{ |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5257 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5258 match(Set dst (PopCountL src)); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5259 effect(KILL cr, TEMP tmp, TEMP dst); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5260 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5261 format %{ "POPCNT $dst, $src.lo\n\t" |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5262 "POPCNT $tmp, $src.hi\n\t" |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5263 "ADD $dst, $tmp" %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5264 ins_encode %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5265 __ popcntl($dst$$Register, $src$$Register); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5266 __ popcntl($tmp$$Register, HIGH_FROM_LOW($src$$Register)); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5267 __ addl($dst$$Register, $tmp$$Register); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5268 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5269 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5270 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5271 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5272 // Note: Long.bitCount(long) returns an int. |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
5273 instruct popCountL_mem(rRegI dst, memory mem, rRegI tmp, eFlagsReg cr) %{ |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5274 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5275 match(Set dst (PopCountL (LoadL mem))); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5276 effect(KILL cr, TEMP tmp, TEMP dst); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5277 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5278 format %{ "POPCNT $dst, $mem\n\t" |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5279 "POPCNT $tmp, $mem+4\n\t" |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5280 "ADD $dst, $tmp" %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5281 ins_encode %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5282 //__ popcntl($dst$$Register, $mem$$Address$$first); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5283 //__ popcntl($tmp$$Register, $mem$$Address$$second); |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
5284 __ popcntl($dst$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none)); |
|
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6614
diff
changeset
|
5285 __ popcntl($tmp$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, relocInfo::none)); |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5286 __ addl($dst$$Register, $tmp$$Register); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5287 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5288 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5289 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5290 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5291 |
| 0 | 5292 //----------Load/Store/Move Instructions--------------------------------------- |
| 5293 //----------Load Instructions-------------------------------------------------- | |
| 5294 // Load Byte (8bit signed) | |
| 5295 instruct loadB(xRegI dst, memory mem) %{ | |
| 5296 match(Set dst (LoadB mem)); | |
| 5297 | |
| 5298 ins_cost(125); | |
| 624 | 5299 format %{ "MOVSX8 $dst,$mem\t# byte" %} |
| 5300 | |
| 5301 ins_encode %{ | |
| 5302 __ movsbl($dst$$Register, $mem$$Address); | |
| 5303 %} | |
| 5304 | |
| 5305 ins_pipe(ialu_reg_mem); | |
| 5306 %} | |
| 5307 | |
| 5308 // Load Byte (8bit signed) into Long Register | |
| 824 | 5309 instruct loadB2L(eRegL dst, memory mem, eFlagsReg cr) %{ |
| 624 | 5310 match(Set dst (ConvI2L (LoadB mem))); |
| 824 | 5311 effect(KILL cr); |
| 624 | 5312 |
| 5313 ins_cost(375); | |
| 5314 format %{ "MOVSX8 $dst.lo,$mem\t# byte -> long\n\t" | |
| 5315 "MOV $dst.hi,$dst.lo\n\t" | |
| 5316 "SAR $dst.hi,7" %} | |
| 5317 | |
| 5318 ins_encode %{ | |
| 5319 __ movsbl($dst$$Register, $mem$$Address); | |
| 5320 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register. | |
| 5321 __ sarl(HIGH_FROM_LOW($dst$$Register), 7); // 24+1 MSB are already signed extended. | |
| 5322 %} | |
| 5323 | |
| 5324 ins_pipe(ialu_reg_mem); | |
| 5325 %} | |
| 5326 | |
| 5327 // Load Unsigned Byte (8bit UNsigned) | |
| 5328 instruct loadUB(xRegI dst, memory mem) %{ | |
| 5329 match(Set dst (LoadUB mem)); | |
| 0 | 5330 |
| 5331 ins_cost(125); | |
| 624 | 5332 format %{ "MOVZX8 $dst,$mem\t# ubyte -> int" %} |
| 5333 | |
| 5334 ins_encode %{ | |
| 5335 __ movzbl($dst$$Register, $mem$$Address); | |
| 5336 %} | |
| 5337 | |
| 5338 ins_pipe(ialu_reg_mem); | |
| 5339 %} | |
| 5340 | |
| 5341 // Load Unsigned Byte (8 bit UNsigned) into Long Register | |
| 824 | 5342 instruct loadUB2L(eRegL dst, memory mem, eFlagsReg cr) %{ |
| 624 | 5343 match(Set dst (ConvI2L (LoadUB mem))); |
| 824 | 5344 effect(KILL cr); |
| 624 | 5345 |
| 5346 ins_cost(250); | |
| 5347 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte -> long\n\t" | |
| 5348 "XOR $dst.hi,$dst.hi" %} | |
| 5349 | |
| 5350 ins_encode %{ | |
| 824 | 5351 Register Rdst = $dst$$Register; |
| 5352 __ movzbl(Rdst, $mem$$Address); | |
| 5353 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); | |
| 5354 %} | |
| 5355 | |
| 5356 ins_pipe(ialu_reg_mem); | |
| 5357 %} | |
| 5358 | |
| 5359 // Load Unsigned Byte (8 bit UNsigned) with mask into Long Register | |
| 5360 instruct loadUB2L_immI8(eRegL dst, memory mem, immI8 mask, eFlagsReg cr) %{ | |
| 5361 match(Set dst (ConvI2L (AndI (LoadUB mem) mask))); | |
| 5362 effect(KILL cr); | |
| 5363 | |
| 5364 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte & 8-bit mask -> long\n\t" | |
| 5365 "XOR $dst.hi,$dst.hi\n\t" | |
| 5366 "AND $dst.lo,$mask" %} | |
| 5367 ins_encode %{ | |
| 5368 Register Rdst = $dst$$Register; | |
| 5369 __ movzbl(Rdst, $mem$$Address); | |
| 5370 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); | |
| 5371 __ andl(Rdst, $mask$$constant); | |
| 5372 %} | |
| 624 | 5373 ins_pipe(ialu_reg_mem); |
| 5374 %} | |
| 5375 | |
| 5376 // Load Short (16bit signed) | |
|
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5377 instruct loadS(rRegI dst, memory mem) %{ |
| 624 | 5378 match(Set dst (LoadS mem)); |
| 5379 | |
| 5380 ins_cost(125); | |
| 5381 format %{ "MOVSX $dst,$mem\t# short" %} | |
| 5382 | |
| 5383 ins_encode %{ | |
| 5384 __ movswl($dst$$Register, $mem$$Address); | |
| 5385 %} | |
| 5386 | |
| 5387 ins_pipe(ialu_reg_mem); | |
| 5388 %} | |
| 5389 | |
| 785 | 5390 // Load Short (16 bit signed) to Byte (8 bit signed) |
|
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5391 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{ |
| 785 | 5392 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour)); |
| 5393 | |
| 5394 ins_cost(125); | |
| 5395 format %{ "MOVSX $dst, $mem\t# short -> byte" %} | |
| 5396 ins_encode %{ | |
| 5397 __ movsbl($dst$$Register, $mem$$Address); | |
| 5398 %} | |
| 5399 ins_pipe(ialu_reg_mem); | |
| 5400 %} | |
| 5401 | |
| 624 | 5402 // Load Short (16bit signed) into Long Register |
| 824 | 5403 instruct loadS2L(eRegL dst, memory mem, eFlagsReg cr) %{ |
| 624 | 5404 match(Set dst (ConvI2L (LoadS mem))); |
| 824 | 5405 effect(KILL cr); |
| 624 | 5406 |
| 5407 ins_cost(375); | |
| 5408 format %{ "MOVSX $dst.lo,$mem\t# short -> long\n\t" | |
| 5409 "MOV $dst.hi,$dst.lo\n\t" | |
| 5410 "SAR $dst.hi,15" %} | |
| 5411 | |
| 5412 ins_encode %{ | |
| 5413 __ movswl($dst$$Register, $mem$$Address); | |
| 5414 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register. | |
| 5415 __ sarl(HIGH_FROM_LOW($dst$$Register), 15); // 16+1 MSB are already signed extended. | |
| 5416 %} | |
| 5417 | |
| 5418 ins_pipe(ialu_reg_mem); | |
| 0 | 5419 %} |
| 5420 | |
|
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|
5421 // Load Unsigned Short/Char (16bit unsigned) |
|
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5422 instruct loadUS(rRegI dst, memory mem) %{ |
|
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|
5423 match(Set dst (LoadUS mem)); |
| 0 | 5424 |
| 5425 ins_cost(125); | |
| 624 | 5426 format %{ "MOVZX $dst,$mem\t# ushort/char -> int" %} |
| 5427 | |
| 5428 ins_encode %{ | |
| 5429 __ movzwl($dst$$Register, $mem$$Address); | |
| 5430 %} | |
| 5431 | |
| 5432 ins_pipe(ialu_reg_mem); | |
| 5433 %} | |
| 5434 | |
| 785 | 5435 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed) |
|
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5436 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{ |
| 785 | 5437 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour)); |
| 5438 | |
| 5439 ins_cost(125); | |
| 5440 format %{ "MOVSX $dst, $mem\t# ushort -> byte" %} | |
| 5441 ins_encode %{ | |
| 5442 __ movsbl($dst$$Register, $mem$$Address); | |
| 5443 %} | |
| 5444 ins_pipe(ialu_reg_mem); | |
| 5445 %} | |
| 5446 | |
| 624 | 5447 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register |
| 824 | 5448 instruct loadUS2L(eRegL dst, memory mem, eFlagsReg cr) %{ |
| 624 | 5449 match(Set dst (ConvI2L (LoadUS mem))); |
| 824 | 5450 effect(KILL cr); |
| 624 | 5451 |
| 5452 ins_cost(250); | |
| 5453 format %{ "MOVZX $dst.lo,$mem\t# ushort/char -> long\n\t" | |
| 5454 "XOR $dst.hi,$dst.hi" %} | |
| 5455 | |
| 5456 ins_encode %{ | |
| 5457 __ movzwl($dst$$Register, $mem$$Address); | |
| 5458 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register)); | |
| 5459 %} | |
| 5460 | |
| 5461 ins_pipe(ialu_reg_mem); | |
| 0 | 5462 %} |
| 5463 | |
| 824 | 5464 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register |
| 5465 instruct loadUS2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{ | |
| 5466 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
| 5467 effect(KILL cr); | |
| 5468 | |
| 5469 format %{ "MOVZX8 $dst.lo,$mem\t# ushort/char & 0xFF -> long\n\t" | |
| 5470 "XOR $dst.hi,$dst.hi" %} | |
| 5471 ins_encode %{ | |
| 5472 Register Rdst = $dst$$Register; | |
| 5473 __ movzbl(Rdst, $mem$$Address); | |
| 5474 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); | |
| 5475 %} | |
| 5476 ins_pipe(ialu_reg_mem); | |
| 5477 %} | |
| 5478 | |
| 5479 // Load Unsigned Short/Char (16 bit UNsigned) with a 16-bit mask into Long Register | |
| 5480 instruct loadUS2L_immI16(eRegL dst, memory mem, immI16 mask, eFlagsReg cr) %{ | |
| 5481 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
| 5482 effect(KILL cr); | |
| 5483 | |
| 5484 format %{ "MOVZX $dst.lo, $mem\t# ushort/char & 16-bit mask -> long\n\t" | |
| 5485 "XOR $dst.hi,$dst.hi\n\t" | |
| 5486 "AND $dst.lo,$mask" %} | |
| 5487 ins_encode %{ | |
| 5488 Register Rdst = $dst$$Register; | |
| 5489 __ movzwl(Rdst, $mem$$Address); | |
| 5490 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); | |
| 5491 __ andl(Rdst, $mask$$constant); | |
| 5492 %} | |
| 5493 ins_pipe(ialu_reg_mem); | |
| 5494 %} | |
| 5495 | |
| 0 | 5496 // Load Integer |
|
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5497 instruct loadI(rRegI dst, memory mem) %{ |
| 0 | 5498 match(Set dst (LoadI mem)); |
| 5499 | |
| 5500 ins_cost(125); | |
| 624 | 5501 format %{ "MOV $dst,$mem\t# int" %} |
| 5502 | |
| 5503 ins_encode %{ | |
| 5504 __ movl($dst$$Register, $mem$$Address); | |
| 5505 %} | |
| 5506 | |
| 5507 ins_pipe(ialu_reg_mem); | |
| 5508 %} | |
| 5509 | |
| 785 | 5510 // Load Integer (32 bit signed) to Byte (8 bit signed) |
|
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5511 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{ |
| 785 | 5512 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour)); |
| 5513 | |
| 5514 ins_cost(125); | |
| 5515 format %{ "MOVSX $dst, $mem\t# int -> byte" %} | |
| 5516 ins_encode %{ | |
| 5517 __ movsbl($dst$$Register, $mem$$Address); | |
| 5518 %} | |
| 5519 ins_pipe(ialu_reg_mem); | |
| 5520 %} | |
| 5521 | |
| 5522 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned) | |
|
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5523 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{ |
| 785 | 5524 match(Set dst (AndI (LoadI mem) mask)); |
| 5525 | |
| 5526 ins_cost(125); | |
| 5527 format %{ "MOVZX $dst, $mem\t# int -> ubyte" %} | |
| 5528 ins_encode %{ | |
| 5529 __ movzbl($dst$$Register, $mem$$Address); | |
| 5530 %} | |
| 5531 ins_pipe(ialu_reg_mem); | |
| 5532 %} | |
| 5533 | |
| 5534 // Load Integer (32 bit signed) to Short (16 bit signed) | |
|
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5535 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{ |
| 785 | 5536 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen)); |
| 5537 | |
| 5538 ins_cost(125); | |
| 5539 format %{ "MOVSX $dst, $mem\t# int -> short" %} | |
| 5540 ins_encode %{ | |
| 5541 __ movswl($dst$$Register, $mem$$Address); | |
| 5542 %} | |
| 5543 ins_pipe(ialu_reg_mem); | |
| 5544 %} | |
| 5545 | |
| 5546 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned) | |
|
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5547 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{ |
| 785 | 5548 match(Set dst (AndI (LoadI mem) mask)); |
| 5549 | |
| 5550 ins_cost(125); | |
| 5551 format %{ "MOVZX $dst, $mem\t# int -> ushort/char" %} | |
| 5552 ins_encode %{ | |
| 5553 __ movzwl($dst$$Register, $mem$$Address); | |
| 5554 %} | |
| 5555 ins_pipe(ialu_reg_mem); | |
| 5556 %} | |
| 5557 | |
| 624 | 5558 // Load Integer into Long Register |
| 824 | 5559 instruct loadI2L(eRegL dst, memory mem, eFlagsReg cr) %{ |
| 624 | 5560 match(Set dst (ConvI2L (LoadI mem))); |
| 824 | 5561 effect(KILL cr); |
| 624 | 5562 |
| 5563 ins_cost(375); | |
| 5564 format %{ "MOV $dst.lo,$mem\t# int -> long\n\t" | |
| 5565 "MOV $dst.hi,$dst.lo\n\t" | |
| 5566 "SAR $dst.hi,31" %} | |
| 5567 | |
| 5568 ins_encode %{ | |
| 5569 __ movl($dst$$Register, $mem$$Address); | |
| 5570 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register. | |
| 5571 __ sarl(HIGH_FROM_LOW($dst$$Register), 31); | |
| 5572 %} | |
| 5573 | |
| 5574 ins_pipe(ialu_reg_mem); | |
| 5575 %} | |
| 5576 | |
| 824 | 5577 // Load Integer with mask 0xFF into Long Register |
| 5578 instruct loadI2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{ | |
| 5579 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
| 5580 effect(KILL cr); | |
| 5581 | |
| 5582 format %{ "MOVZX8 $dst.lo,$mem\t# int & 0xFF -> long\n\t" | |
| 5583 "XOR $dst.hi,$dst.hi" %} | |
| 5584 ins_encode %{ | |
| 5585 Register Rdst = $dst$$Register; | |
| 5586 __ movzbl(Rdst, $mem$$Address); | |
| 5587 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); | |
| 5588 %} | |
| 5589 ins_pipe(ialu_reg_mem); | |
| 5590 %} | |
| 5591 | |
| 5592 // Load Integer with mask 0xFFFF into Long Register | |
| 5593 instruct loadI2L_immI_65535(eRegL dst, memory mem, immI_65535 mask, eFlagsReg cr) %{ | |
| 5594 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
| 5595 effect(KILL cr); | |
| 5596 | |
| 5597 format %{ "MOVZX $dst.lo,$mem\t# int & 0xFFFF -> long\n\t" | |
| 5598 "XOR $dst.hi,$dst.hi" %} | |
| 5599 ins_encode %{ | |
| 5600 Register Rdst = $dst$$Register; | |
| 5601 __ movzwl(Rdst, $mem$$Address); | |
| 5602 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); | |
| 5603 %} | |
| 5604 ins_pipe(ialu_reg_mem); | |
| 5605 %} | |
| 5606 | |
|
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|
5607 // Load Integer with 31-bit mask into Long Register |
|
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|
5608 instruct loadI2L_immU31(eRegL dst, memory mem, immU31 mask, eFlagsReg cr) %{ |
| 824 | 5609 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); |
| 5610 effect(KILL cr); | |
| 5611 | |
|
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|
5612 format %{ "MOV $dst.lo,$mem\t# int & 31-bit mask -> long\n\t" |
| 824 | 5613 "XOR $dst.hi,$dst.hi\n\t" |
| 5614 "AND $dst.lo,$mask" %} | |
| 5615 ins_encode %{ | |
| 5616 Register Rdst = $dst$$Register; | |
| 5617 __ movl(Rdst, $mem$$Address); | |
| 5618 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); | |
| 5619 __ andl(Rdst, $mask$$constant); | |
| 5620 %} | |
| 5621 ins_pipe(ialu_reg_mem); | |
| 5622 %} | |
| 5623 | |
| 624 | 5624 // Load Unsigned Integer into Long Register |
| 6849 | 5625 instruct loadUI2L(eRegL dst, memory mem, immL_32bits mask, eFlagsReg cr) %{ |
| 5626 match(Set dst (AndL (ConvI2L (LoadI mem)) mask)); | |
| 824 | 5627 effect(KILL cr); |
| 624 | 5628 |
| 5629 ins_cost(250); | |
| 5630 format %{ "MOV $dst.lo,$mem\t# uint -> long\n\t" | |
| 5631 "XOR $dst.hi,$dst.hi" %} | |
| 5632 | |
| 5633 ins_encode %{ | |
| 5634 __ movl($dst$$Register, $mem$$Address); | |
| 5635 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register)); | |
| 5636 %} | |
| 5637 | |
| 5638 ins_pipe(ialu_reg_mem); | |
| 0 | 5639 %} |
| 5640 | |
| 5641 // Load Long. Cannot clobber address while loading, so restrict address | |
| 5642 // register to ESI | |
| 5643 instruct loadL(eRegL dst, load_long_memory mem) %{ | |
| 5644 predicate(!((LoadLNode*)n)->require_atomic_access()); | |
| 5645 match(Set dst (LoadL mem)); | |
| 5646 | |
| 5647 ins_cost(250); | |
| 624 | 5648 format %{ "MOV $dst.lo,$mem\t# long\n\t" |
| 0 | 5649 "MOV $dst.hi,$mem+4" %} |
| 624 | 5650 |
| 5651 ins_encode %{ | |
|
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5652 Address Amemlo = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none); |
|
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5653 Address Amemhi = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, relocInfo::none); |
| 624 | 5654 __ movl($dst$$Register, Amemlo); |
| 5655 __ movl(HIGH_FROM_LOW($dst$$Register), Amemhi); | |
| 5656 %} | |
| 5657 | |
| 5658 ins_pipe(ialu_reg_long_mem); | |
| 0 | 5659 %} |
| 5660 | |
| 5661 // Volatile Load Long. Must be atomic, so do 64-bit FILD | |
| 5662 // then store it down to the stack and reload on the int | |
| 5663 // side. | |
| 5664 instruct loadL_volatile(stackSlotL dst, memory mem) %{ | |
| 5665 predicate(UseSSE<=1 && ((LoadLNode*)n)->require_atomic_access()); | |
| 5666 match(Set dst (LoadL mem)); | |
| 5667 | |
| 5668 ins_cost(200); | |
| 5669 format %{ "FILD $mem\t# Atomic volatile long load\n\t" | |
| 5670 "FISTp $dst" %} | |
| 5671 ins_encode(enc_loadL_volatile(mem,dst)); | |
| 5672 ins_pipe( fpu_reg_mem ); | |
| 5673 %} | |
| 5674 | |
|
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|
5675 instruct loadLX_volatile(stackSlotL dst, memory mem, regD tmp) %{ |
| 0 | 5676 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access()); |
| 5677 match(Set dst (LoadL mem)); | |
| 5678 effect(TEMP tmp); | |
| 5679 ins_cost(180); | |
| 5680 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t" | |
| 5681 "MOVSD $dst,$tmp" %} | |
| 4759 | 5682 ins_encode %{ |
| 5683 __ movdbl($tmp$$XMMRegister, $mem$$Address); | |
| 5684 __ movdbl(Address(rsp, $dst$$disp), $tmp$$XMMRegister); | |
| 5685 %} | |
| 0 | 5686 ins_pipe( pipe_slow ); |
| 5687 %} | |
| 5688 | |
|
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|
5689 instruct loadLX_reg_volatile(eRegL dst, memory mem, regD tmp) %{ |
| 0 | 5690 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access()); |
| 5691 match(Set dst (LoadL mem)); | |
| 5692 effect(TEMP tmp); | |
| 5693 ins_cost(160); | |
| 5694 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t" | |
| 5695 "MOVD $dst.lo,$tmp\n\t" | |
| 5696 "PSRLQ $tmp,32\n\t" | |
| 5697 "MOVD $dst.hi,$tmp" %} | |
| 4759 | 5698 ins_encode %{ |
| 5699 __ movdbl($tmp$$XMMRegister, $mem$$Address); | |
| 5700 __ movdl($dst$$Register, $tmp$$XMMRegister); | |
| 5701 __ psrlq($tmp$$XMMRegister, 32); | |
| 5702 __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister); | |
| 5703 %} | |
| 0 | 5704 ins_pipe( pipe_slow ); |
| 5705 %} | |
| 5706 | |
| 5707 // Load Range | |
|
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5708 instruct loadRange(rRegI dst, memory mem) %{ |
| 0 | 5709 match(Set dst (LoadRange mem)); |
| 5710 | |
| 5711 ins_cost(125); | |
| 5712 format %{ "MOV $dst,$mem" %} | |
| 5713 opcode(0x8B); | |
| 5714 ins_encode( OpcP, RegMem(dst,mem)); | |
| 5715 ins_pipe( ialu_reg_mem ); | |
| 5716 %} | |
| 5717 | |
| 5718 | |
| 5719 // Load Pointer | |
| 5720 instruct loadP(eRegP dst, memory mem) %{ | |
| 5721 match(Set dst (LoadP mem)); | |
| 5722 | |
| 5723 ins_cost(125); | |
| 5724 format %{ "MOV $dst,$mem" %} | |
| 5725 opcode(0x8B); | |
| 5726 ins_encode( OpcP, RegMem(dst,mem)); | |
| 5727 ins_pipe( ialu_reg_mem ); | |
| 5728 %} | |
| 5729 | |
| 5730 // Load Klass Pointer | |
| 5731 instruct loadKlass(eRegP dst, memory mem) %{ | |
| 5732 match(Set dst (LoadKlass mem)); | |
| 5733 | |
| 5734 ins_cost(125); | |
| 5735 format %{ "MOV $dst,$mem" %} | |
| 5736 opcode(0x8B); | |
| 5737 ins_encode( OpcP, RegMem(dst,mem)); | |
| 5738 ins_pipe( ialu_reg_mem ); | |
| 5739 %} | |
| 5740 | |
| 5741 // Load Double | |
|
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|
5742 instruct loadDPR(regDPR dst, memory mem) %{ |
| 0 | 5743 predicate(UseSSE<=1); |
| 5744 match(Set dst (LoadD mem)); | |
| 5745 | |
| 5746 ins_cost(150); | |
| 5747 format %{ "FLD_D ST,$mem\n\t" | |
| 5748 "FSTP $dst" %} | |
| 5749 opcode(0xDD); /* DD /0 */ | |
| 5750 ins_encode( OpcP, RMopc_Mem(0x00,mem), | |
|
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|
5751 Pop_Reg_DPR(dst) ); |
| 0 | 5752 ins_pipe( fpu_reg_mem ); |
| 5753 %} | |
| 5754 | |
| 5755 // Load Double to XMM | |
|
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|
5756 instruct loadD(regD dst, memory mem) %{ |
| 0 | 5757 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper); |
| 5758 match(Set dst (LoadD mem)); | |
| 5759 ins_cost(145); | |
| 5760 format %{ "MOVSD $dst,$mem" %} | |
| 4759 | 5761 ins_encode %{ |
| 5762 __ movdbl ($dst$$XMMRegister, $mem$$Address); | |
| 5763 %} | |
| 0 | 5764 ins_pipe( pipe_slow ); |
| 5765 %} | |
| 5766 | |
|
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5767 instruct loadD_partial(regD dst, memory mem) %{ |
| 0 | 5768 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper); |
| 5769 match(Set dst (LoadD mem)); | |
| 5770 ins_cost(145); | |
| 5771 format %{ "MOVLPD $dst,$mem" %} | |
| 4759 | 5772 ins_encode %{ |
| 5773 __ movdbl ($dst$$XMMRegister, $mem$$Address); | |
| 5774 %} | |
| 0 | 5775 ins_pipe( pipe_slow ); |
| 5776 %} | |
| 5777 | |
| 5778 // Load to XMM register (single-precision floating point) | |
| 5779 // MOVSS instruction | |
|
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5780 instruct loadF(regF dst, memory mem) %{ |
| 0 | 5781 predicate(UseSSE>=1); |
| 5782 match(Set dst (LoadF mem)); | |
| 5783 ins_cost(145); | |
| 5784 format %{ "MOVSS $dst,$mem" %} | |
| 4759 | 5785 ins_encode %{ |
| 5786 __ movflt ($dst$$XMMRegister, $mem$$Address); | |
| 5787 %} | |
| 0 | 5788 ins_pipe( pipe_slow ); |
| 5789 %} | |
| 5790 | |
| 5791 // Load Float | |
|
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5792 instruct loadFPR(regFPR dst, memory mem) %{ |
| 0 | 5793 predicate(UseSSE==0); |
| 5794 match(Set dst (LoadF mem)); | |
| 5795 | |
| 5796 ins_cost(150); | |
| 5797 format %{ "FLD_S ST,$mem\n\t" | |
| 5798 "FSTP $dst" %} | |
| 5799 opcode(0xD9); /* D9 /0 */ | |
| 5800 ins_encode( OpcP, RMopc_Mem(0x00,mem), | |
|
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5801 Pop_Reg_FPR(dst) ); |
| 0 | 5802 ins_pipe( fpu_reg_mem ); |
| 5803 %} | |
| 5804 | |
| 5805 // Load Effective Address | |
| 5806 instruct leaP8(eRegP dst, indOffset8 mem) %{ | |
| 5807 match(Set dst mem); | |
| 5808 | |
| 5809 ins_cost(110); | |
| 5810 format %{ "LEA $dst,$mem" %} | |
| 5811 opcode(0x8D); | |
| 5812 ins_encode( OpcP, RegMem(dst,mem)); | |
| 5813 ins_pipe( ialu_reg_reg_fat ); | |
| 5814 %} | |
| 5815 | |
| 5816 instruct leaP32(eRegP dst, indOffset32 mem) %{ | |
| 5817 match(Set dst mem); | |
| 5818 | |
| 5819 ins_cost(110); | |
| 5820 format %{ "LEA $dst,$mem" %} | |
| 5821 opcode(0x8D); | |
| 5822 ins_encode( OpcP, RegMem(dst,mem)); | |
| 5823 ins_pipe( ialu_reg_reg_fat ); | |
| 5824 %} | |
| 5825 | |
| 5826 instruct leaPIdxOff(eRegP dst, indIndexOffset mem) %{ | |
| 5827 match(Set dst mem); | |
| 5828 | |
| 5829 ins_cost(110); | |
| 5830 format %{ "LEA $dst,$mem" %} | |
| 5831 opcode(0x8D); | |
| 5832 ins_encode( OpcP, RegMem(dst,mem)); | |
| 5833 ins_pipe( ialu_reg_reg_fat ); | |
| 5834 %} | |
| 5835 | |
| 5836 instruct leaPIdxScale(eRegP dst, indIndexScale mem) %{ | |
| 5837 match(Set dst mem); | |
| 5838 | |
| 5839 ins_cost(110); | |
| 5840 format %{ "LEA $dst,$mem" %} | |
| 5841 opcode(0x8D); | |
| 5842 ins_encode( OpcP, RegMem(dst,mem)); | |
| 5843 ins_pipe( ialu_reg_reg_fat ); | |
| 5844 %} | |
| 5845 | |
| 5846 instruct leaPIdxScaleOff(eRegP dst, indIndexScaleOffset mem) %{ | |
| 5847 match(Set dst mem); | |
| 5848 | |
| 5849 ins_cost(110); | |
| 5850 format %{ "LEA $dst,$mem" %} | |
| 5851 opcode(0x8D); | |
| 5852 ins_encode( OpcP, RegMem(dst,mem)); | |
| 5853 ins_pipe( ialu_reg_reg_fat ); | |
| 5854 %} | |
| 5855 | |
| 5856 // Load Constant | |
|
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5857 instruct loadConI(rRegI dst, immI src) %{ |
| 0 | 5858 match(Set dst src); |
| 5859 | |
| 5860 format %{ "MOV $dst,$src" %} | |
| 5861 ins_encode( LdImmI(dst, src) ); | |
| 5862 ins_pipe( ialu_reg_fat ); | |
| 5863 %} | |
| 5864 | |
| 5865 // Load Constant zero | |
|
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5866 instruct loadConI0(rRegI dst, immI0 src, eFlagsReg cr) %{ |
| 0 | 5867 match(Set dst src); |
| 5868 effect(KILL cr); | |
| 5869 | |
| 5870 ins_cost(50); | |
| 5871 format %{ "XOR $dst,$dst" %} | |
| 5872 opcode(0x33); /* + rd */ | |
| 5873 ins_encode( OpcP, RegReg( dst, dst ) ); | |
| 5874 ins_pipe( ialu_reg ); | |
| 5875 %} | |
| 5876 | |
| 5877 instruct loadConP(eRegP dst, immP src) %{ | |
| 5878 match(Set dst src); | |
| 5879 | |
| 5880 format %{ "MOV $dst,$src" %} | |
| 5881 opcode(0xB8); /* + rd */ | |
| 5882 ins_encode( LdImmP(dst, src) ); | |
| 5883 ins_pipe( ialu_reg_fat ); | |
| 5884 %} | |
| 5885 | |
| 5886 instruct loadConL(eRegL dst, immL src, eFlagsReg cr) %{ | |
| 5887 match(Set dst src); | |
| 5888 effect(KILL cr); | |
| 5889 ins_cost(200); | |
| 5890 format %{ "MOV $dst.lo,$src.lo\n\t" | |
| 5891 "MOV $dst.hi,$src.hi" %} | |
| 5892 opcode(0xB8); | |
| 5893 ins_encode( LdImmL_Lo(dst, src), LdImmL_Hi(dst, src) ); | |
| 5894 ins_pipe( ialu_reg_long_fat ); | |
| 5895 %} | |
| 5896 | |
| 5897 instruct loadConL0(eRegL dst, immL0 src, eFlagsReg cr) %{ | |
| 5898 match(Set dst src); | |
| 5899 effect(KILL cr); | |
| 5900 ins_cost(150); | |
| 5901 format %{ "XOR $dst.lo,$dst.lo\n\t" | |
| 5902 "XOR $dst.hi,$dst.hi" %} | |
| 5903 opcode(0x33,0x33); | |
| 5904 ins_encode( RegReg_Lo(dst,dst), RegReg_Hi(dst, dst) ); | |
| 5905 ins_pipe( ialu_reg_long ); | |
| 5906 %} | |
| 5907 | |
|
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5908 // The instruction usage is guarded by predicate in operand immFPR(). |
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5909 instruct loadConFPR(regFPR dst, immFPR con) %{ |
| 2008 | 5910 match(Set dst con); |
| 5911 ins_cost(125); | |
| 5912 format %{ "FLD_S ST,[$constantaddress]\t# load from constant table: float=$con\n\t" | |
| 5913 "FSTP $dst" %} | |
| 5914 ins_encode %{ | |
| 5915 __ fld_s($constantaddress($con)); | |
| 5916 __ fstp_d($dst$$reg); | |
| 5917 %} | |
| 5918 ins_pipe(fpu_reg_con); | |
| 5919 %} | |
| 5920 | |
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5921 // The instruction usage is guarded by predicate in operand immFPR0(). |
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5922 instruct loadConFPR0(regFPR dst, immFPR0 con) %{ |
| 2008 | 5923 match(Set dst con); |
| 0 | 5924 ins_cost(125); |
| 2008 | 5925 format %{ "FLDZ ST\n\t" |
| 0 | 5926 "FSTP $dst" %} |
| 2008 | 5927 ins_encode %{ |
| 5928 __ fldz(); | |
| 5929 __ fstp_d($dst$$reg); | |
| 5930 %} | |
| 5931 ins_pipe(fpu_reg_con); | |
| 5932 %} | |
| 5933 | |
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5934 // The instruction usage is guarded by predicate in operand immFPR1(). |
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5935 instruct loadConFPR1(regFPR dst, immFPR1 con) %{ |
| 2008 | 5936 match(Set dst con); |
| 5937 ins_cost(125); | |
| 5938 format %{ "FLD1 ST\n\t" | |
| 5939 "FSTP $dst" %} | |
| 5940 ins_encode %{ | |
| 5941 __ fld1(); | |
| 5942 __ fstp_d($dst$$reg); | |
| 5943 %} | |
| 5944 ins_pipe(fpu_reg_con); | |
| 0 | 5945 %} |
| 5946 | |
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5947 // The instruction usage is guarded by predicate in operand immF(). |
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5948 instruct loadConF(regF dst, immF con) %{ |
| 0 | 5949 match(Set dst con); |
| 5950 ins_cost(125); | |
| 2008 | 5951 format %{ "MOVSS $dst,[$constantaddress]\t# load from constant table: float=$con" %} |
| 5952 ins_encode %{ | |
| 5953 __ movflt($dst$$XMMRegister, $constantaddress($con)); | |
| 5954 %} | |
| 5955 ins_pipe(pipe_slow); | |
| 0 | 5956 %} |
| 5957 | |
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5958 // The instruction usage is guarded by predicate in operand immF0(). |
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5959 instruct loadConF0(regF dst, immF0 src) %{ |
| 0 | 5960 match(Set dst src); |
| 5961 ins_cost(100); | |
| 5962 format %{ "XORPS $dst,$dst\t# float 0.0" %} | |
| 2008 | 5963 ins_encode %{ |
| 5964 __ xorps($dst$$XMMRegister, $dst$$XMMRegister); | |
| 5965 %} | |
| 5966 ins_pipe(pipe_slow); | |
| 0 | 5967 %} |
| 5968 | |
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5969 // The instruction usage is guarded by predicate in operand immDPR(). |
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5970 instruct loadConDPR(regDPR dst, immDPR con) %{ |
| 2008 | 5971 match(Set dst con); |
| 5972 ins_cost(125); | |
| 5973 | |
| 5974 format %{ "FLD_D ST,[$constantaddress]\t# load from constant table: double=$con\n\t" | |
| 5975 "FSTP $dst" %} | |
| 5976 ins_encode %{ | |
| 5977 __ fld_d($constantaddress($con)); | |
| 5978 __ fstp_d($dst$$reg); | |
| 5979 %} | |
| 5980 ins_pipe(fpu_reg_con); | |
| 5981 %} | |
| 5982 | |
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5983 // The instruction usage is guarded by predicate in operand immDPR0(). |
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5984 instruct loadConDPR0(regDPR dst, immDPR0 con) %{ |
| 2008 | 5985 match(Set dst con); |
| 0 | 5986 ins_cost(125); |
| 5987 | |
| 2008 | 5988 format %{ "FLDZ ST\n\t" |
| 0 | 5989 "FSTP $dst" %} |
| 2008 | 5990 ins_encode %{ |
| 5991 __ fldz(); | |
| 5992 __ fstp_d($dst$$reg); | |
| 5993 %} | |
| 5994 ins_pipe(fpu_reg_con); | |
| 5995 %} | |
| 5996 | |
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5997 // The instruction usage is guarded by predicate in operand immDPR1(). |
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5998 instruct loadConDPR1(regDPR dst, immDPR1 con) %{ |
| 2008 | 5999 match(Set dst con); |
| 6000 ins_cost(125); | |
| 6001 | |
| 6002 format %{ "FLD1 ST\n\t" | |
| 6003 "FSTP $dst" %} | |
| 6004 ins_encode %{ | |
| 6005 __ fld1(); | |
| 6006 __ fstp_d($dst$$reg); | |
| 6007 %} | |
| 6008 ins_pipe(fpu_reg_con); | |
| 0 | 6009 %} |
| 6010 | |
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6011 // The instruction usage is guarded by predicate in operand immD(). |
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6012 instruct loadConD(regD dst, immD con) %{ |
| 0 | 6013 match(Set dst con); |
| 6014 ins_cost(125); | |
| 2008 | 6015 format %{ "MOVSD $dst,[$constantaddress]\t# load from constant table: double=$con" %} |
| 6016 ins_encode %{ | |
| 6017 __ movdbl($dst$$XMMRegister, $constantaddress($con)); | |
| 6018 %} | |
| 6019 ins_pipe(pipe_slow); | |
| 0 | 6020 %} |
| 6021 | |
|
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6022 // The instruction usage is guarded by predicate in operand immD0(). |
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6023 instruct loadConD0(regD dst, immD0 src) %{ |
| 0 | 6024 match(Set dst src); |
| 6025 ins_cost(100); | |
| 6026 format %{ "XORPD $dst,$dst\t# double 0.0" %} | |
| 4759 | 6027 ins_encode %{ |
| 6028 __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister); | |
| 6029 %} | |
| 0 | 6030 ins_pipe( pipe_slow ); |
| 6031 %} | |
| 6032 | |
| 6033 // Load Stack Slot | |
|
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6034 instruct loadSSI(rRegI dst, stackSlotI src) %{ |
| 0 | 6035 match(Set dst src); |
| 6036 ins_cost(125); | |
| 6037 | |
| 6038 format %{ "MOV $dst,$src" %} | |
| 6039 opcode(0x8B); | |
| 6040 ins_encode( OpcP, RegMem(dst,src)); | |
| 6041 ins_pipe( ialu_reg_mem ); | |
| 6042 %} | |
| 6043 | |
| 6044 instruct loadSSL(eRegL dst, stackSlotL src) %{ | |
| 6045 match(Set dst src); | |
| 6046 | |
| 6047 ins_cost(200); | |
| 6048 format %{ "MOV $dst,$src.lo\n\t" | |
| 6049 "MOV $dst+4,$src.hi" %} | |
| 6050 opcode(0x8B, 0x8B); | |
| 6051 ins_encode( OpcP, RegMem( dst, src ), OpcS, RegMem_Hi( dst, src ) ); | |
| 6052 ins_pipe( ialu_mem_long_reg ); | |
| 6053 %} | |
| 6054 | |
| 6055 // Load Stack Slot | |
| 6056 instruct loadSSP(eRegP dst, stackSlotP src) %{ | |
| 6057 match(Set dst src); | |
| 6058 ins_cost(125); | |
| 6059 | |
| 6060 format %{ "MOV $dst,$src" %} | |
| 6061 opcode(0x8B); | |
| 6062 ins_encode( OpcP, RegMem(dst,src)); | |
| 6063 ins_pipe( ialu_reg_mem ); | |
| 6064 %} | |
| 6065 | |
| 6066 // Load Stack Slot | |
|
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6067 instruct loadSSF(regFPR dst, stackSlotF src) %{ |
| 0 | 6068 match(Set dst src); |
| 6069 ins_cost(125); | |
| 6070 | |
| 6071 format %{ "FLD_S $src\n\t" | |
| 6072 "FSTP $dst" %} | |
| 6073 opcode(0xD9); /* D9 /0, FLD m32real */ | |
| 6074 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src), | |
|
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6075 Pop_Reg_FPR(dst) ); |
| 0 | 6076 ins_pipe( fpu_reg_mem ); |
| 6077 %} | |
| 6078 | |
| 6079 // Load Stack Slot | |
|
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6080 instruct loadSSD(regDPR dst, stackSlotD src) %{ |
| 0 | 6081 match(Set dst src); |
| 6082 ins_cost(125); | |
| 6083 | |
| 6084 format %{ "FLD_D $src\n\t" | |
| 6085 "FSTP $dst" %} | |
| 6086 opcode(0xDD); /* DD /0, FLD m64real */ | |
| 6087 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src), | |
|
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6088 Pop_Reg_DPR(dst) ); |
| 0 | 6089 ins_pipe( fpu_reg_mem ); |
| 6090 %} | |
| 6091 | |
| 6092 // Prefetch instructions. | |
| 6093 // Must be safe to execute with invalid address (cannot fault). | |
| 6094 | |
| 6095 instruct prefetchr0( memory mem ) %{ | |
| 2479 | 6096 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch()); |
| 0 | 6097 match(PrefetchRead mem); |
| 6098 ins_cost(0); | |
| 6099 size(0); | |
| 6100 format %{ "PREFETCHR (non-SSE is empty encoding)" %} | |
| 6101 ins_encode(); | |
| 6102 ins_pipe(empty); | |
| 6103 %} | |
| 6104 | |
| 6105 instruct prefetchr( memory mem ) %{ | |
| 2479 | 6106 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch() || ReadPrefetchInstr==3); |
| 0 | 6107 match(PrefetchRead mem); |
| 6108 ins_cost(100); | |
| 6109 | |
| 6110 format %{ "PREFETCHR $mem\t! Prefetch into level 1 cache for read" %} | |
| 3854 | 6111 ins_encode %{ |
| 6112 __ prefetchr($mem$$Address); | |
| 6113 %} | |
| 0 | 6114 ins_pipe(ialu_mem); |
| 6115 %} | |
| 6116 | |
| 6117 instruct prefetchrNTA( memory mem ) %{ | |
| 6118 predicate(UseSSE>=1 && ReadPrefetchInstr==0); | |
| 6119 match(PrefetchRead mem); | |
| 6120 ins_cost(100); | |
| 6121 | |
| 6122 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for read" %} | |
| 3854 | 6123 ins_encode %{ |
| 6124 __ prefetchnta($mem$$Address); | |
| 6125 %} | |
| 0 | 6126 ins_pipe(ialu_mem); |
| 6127 %} | |
| 6128 | |
| 6129 instruct prefetchrT0( memory mem ) %{ | |
| 6130 predicate(UseSSE>=1 && ReadPrefetchInstr==1); | |
| 6131 match(PrefetchRead mem); | |
| 6132 ins_cost(100); | |
| 6133 | |
| 6134 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for read" %} | |
| 3854 | 6135 ins_encode %{ |
| 6136 __ prefetcht0($mem$$Address); | |
| 6137 %} | |
| 0 | 6138 ins_pipe(ialu_mem); |
| 6139 %} | |
| 6140 | |
| 6141 instruct prefetchrT2( memory mem ) %{ | |
| 6142 predicate(UseSSE>=1 && ReadPrefetchInstr==2); | |
| 6143 match(PrefetchRead mem); | |
| 6144 ins_cost(100); | |
| 6145 | |
| 6146 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for read" %} | |
| 3854 | 6147 ins_encode %{ |
| 6148 __ prefetcht2($mem$$Address); | |
| 6149 %} | |
| 0 | 6150 ins_pipe(ialu_mem); |
| 6151 %} | |
| 6152 | |
| 6153 instruct prefetchw0( memory mem ) %{ | |
| 2479 | 6154 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch()); |
| 0 | 6155 match(PrefetchWrite mem); |
| 6156 ins_cost(0); | |
| 6157 size(0); | |
| 6158 format %{ "Prefetch (non-SSE is empty encoding)" %} | |
| 6159 ins_encode(); | |
| 6160 ins_pipe(empty); | |
| 6161 %} | |
| 6162 | |
| 6163 instruct prefetchw( memory mem ) %{ | |
| 3854 | 6164 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch()); |
| 0 | 6165 match( PrefetchWrite mem ); |
| 6166 ins_cost(100); | |
| 6167 | |
| 6168 format %{ "PREFETCHW $mem\t! Prefetch into L1 cache and mark modified" %} | |
| 3854 | 6169 ins_encode %{ |
| 6170 __ prefetchw($mem$$Address); | |
| 6171 %} | |
| 0 | 6172 ins_pipe(ialu_mem); |
| 6173 %} | |
| 6174 | |
| 6175 instruct prefetchwNTA( memory mem ) %{ | |
| 3854 | 6176 predicate(UseSSE>=1); |
| 0 | 6177 match(PrefetchWrite mem); |
| 6178 ins_cost(100); | |
| 6179 | |
| 6180 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for write" %} | |
| 3854 | 6181 ins_encode %{ |
| 6182 __ prefetchnta($mem$$Address); | |
| 6183 %} | |
| 0 | 6184 ins_pipe(ialu_mem); |
| 6185 %} | |
| 6186 | |
| 3854 | 6187 // Prefetch instructions for allocation. |
| 6188 | |
| 6189 instruct prefetchAlloc0( memory mem ) %{ | |
| 6190 predicate(UseSSE==0 && AllocatePrefetchInstr!=3); | |
| 6191 match(PrefetchAllocation mem); | |
| 6192 ins_cost(0); | |
| 6193 size(0); | |
| 6194 format %{ "Prefetch allocation (non-SSE is empty encoding)" %} | |
| 6195 ins_encode(); | |
| 6196 ins_pipe(empty); | |
| 6197 %} | |
| 6198 | |
| 6199 instruct prefetchAlloc( memory mem ) %{ | |
| 6200 predicate(AllocatePrefetchInstr==3); | |
| 6201 match( PrefetchAllocation mem ); | |
| 0 | 6202 ins_cost(100); |
| 6203 | |
| 3854 | 6204 format %{ "PREFETCHW $mem\t! Prefetch allocation into L1 cache and mark modified" %} |
| 6205 ins_encode %{ | |
| 6206 __ prefetchw($mem$$Address); | |
| 6207 %} | |
| 6208 ins_pipe(ialu_mem); | |
| 6209 %} | |
| 6210 | |
| 6211 instruct prefetchAllocNTA( memory mem ) %{ | |
| 6212 predicate(UseSSE>=1 && AllocatePrefetchInstr==0); | |
| 6213 match(PrefetchAllocation mem); | |
| 6214 ins_cost(100); | |
| 6215 | |
| 6216 format %{ "PREFETCHNTA $mem\t! Prefetch allocation into non-temporal cache for write" %} | |
| 6217 ins_encode %{ | |
| 6218 __ prefetchnta($mem$$Address); | |
| 6219 %} | |
| 0 | 6220 ins_pipe(ialu_mem); |
| 6221 %} | |
| 6222 | |
| 3854 | 6223 instruct prefetchAllocT0( memory mem ) %{ |
| 6224 predicate(UseSSE>=1 && AllocatePrefetchInstr==1); | |
| 6225 match(PrefetchAllocation mem); | |
| 0 | 6226 ins_cost(100); |
| 6227 | |
| 3854 | 6228 format %{ "PREFETCHT0 $mem\t! Prefetch allocation into L1 and L2 caches for write" %} |
| 6229 ins_encode %{ | |
| 6230 __ prefetcht0($mem$$Address); | |
| 6231 %} | |
| 6232 ins_pipe(ialu_mem); | |
| 6233 %} | |
| 6234 | |
| 6235 instruct prefetchAllocT2( memory mem ) %{ | |
| 6236 predicate(UseSSE>=1 && AllocatePrefetchInstr==2); | |
| 6237 match(PrefetchAllocation mem); | |
| 6238 ins_cost(100); | |
| 6239 | |
| 6240 format %{ "PREFETCHT2 $mem\t! Prefetch allocation into L2 cache for write" %} | |
| 6241 ins_encode %{ | |
| 6242 __ prefetcht2($mem$$Address); | |
| 6243 %} | |
| 0 | 6244 ins_pipe(ialu_mem); |
| 6245 %} | |
| 6246 | |
| 6247 //----------Store Instructions------------------------------------------------- | |
| 6248 | |
| 6249 // Store Byte | |
| 6250 instruct storeB(memory mem, xRegI src) %{ | |
| 6251 match(Set mem (StoreB mem src)); | |
| 6252 | |
| 6253 ins_cost(125); | |
| 6254 format %{ "MOV8 $mem,$src" %} | |
| 6255 opcode(0x88); | |
| 6256 ins_encode( OpcP, RegMem( src, mem ) ); | |
| 6257 ins_pipe( ialu_mem_reg ); | |
| 6258 %} | |
| 6259 | |
| 6260 // Store Char/Short | |
|
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6261 instruct storeC(memory mem, rRegI src) %{ |
| 0 | 6262 match(Set mem (StoreC mem src)); |
| 6263 | |
| 6264 ins_cost(125); | |
| 6265 format %{ "MOV16 $mem,$src" %} | |
| 6266 opcode(0x89, 0x66); | |
| 6267 ins_encode( OpcS, OpcP, RegMem( src, mem ) ); | |
| 6268 ins_pipe( ialu_mem_reg ); | |
| 6269 %} | |
| 6270 | |
| 6271 // Store Integer | |
|
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6272 instruct storeI(memory mem, rRegI src) %{ |
| 0 | 6273 match(Set mem (StoreI mem src)); |
| 6274 | |
| 6275 ins_cost(125); | |
| 6276 format %{ "MOV $mem,$src" %} | |
| 6277 opcode(0x89); | |
| 6278 ins_encode( OpcP, RegMem( src, mem ) ); | |
| 6279 ins_pipe( ialu_mem_reg ); | |
| 6280 %} | |
| 6281 | |
| 6282 // Store Long | |
| 6283 instruct storeL(long_memory mem, eRegL src) %{ | |
| 6284 predicate(!((StoreLNode*)n)->require_atomic_access()); | |
| 6285 match(Set mem (StoreL mem src)); | |
| 6286 | |
| 6287 ins_cost(200); | |
| 6288 format %{ "MOV $mem,$src.lo\n\t" | |
| 6289 "MOV $mem+4,$src.hi" %} | |
| 6290 opcode(0x89, 0x89); | |
| 6291 ins_encode( OpcP, RegMem( src, mem ), OpcS, RegMem_Hi( src, mem ) ); | |
| 6292 ins_pipe( ialu_mem_long_reg ); | |
| 6293 %} | |
| 6294 | |
| 824 | 6295 // Store Long to Integer |
| 6296 instruct storeL2I(memory mem, eRegL src) %{ | |
| 6297 match(Set mem (StoreI mem (ConvL2I src))); | |
| 6298 | |
| 6299 format %{ "MOV $mem,$src.lo\t# long -> int" %} | |
| 6300 ins_encode %{ | |
| 6301 __ movl($mem$$Address, $src$$Register); | |
| 6302 %} | |
| 6303 ins_pipe(ialu_mem_reg); | |
| 6304 %} | |
| 6305 | |
| 0 | 6306 // Volatile Store Long. Must be atomic, so move it into |
| 6307 // the FP TOS and then do a 64-bit FIST. Has to probe the | |
| 6308 // target address before the store (for null-ptr checks) | |
| 6309 // so the memory operand is used twice in the encoding. | |
| 6310 instruct storeL_volatile(memory mem, stackSlotL src, eFlagsReg cr ) %{ | |
| 6311 predicate(UseSSE<=1 && ((StoreLNode*)n)->require_atomic_access()); | |
| 6312 match(Set mem (StoreL mem src)); | |
| 6313 effect( KILL cr ); | |
| 6314 ins_cost(400); | |
| 6315 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t" | |
| 6316 "FILD $src\n\t" | |
| 6317 "FISTp $mem\t # 64-bit atomic volatile long store" %} | |
| 6318 opcode(0x3B); | |
| 6319 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeL_volatile(mem,src)); | |
| 6320 ins_pipe( fpu_reg_mem ); | |
| 6321 %} | |
| 6322 | |
|
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6323 instruct storeLX_volatile(memory mem, stackSlotL src, regD tmp, eFlagsReg cr) %{ |
| 0 | 6324 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access()); |
| 6325 match(Set mem (StoreL mem src)); | |
| 6326 effect( TEMP tmp, KILL cr ); | |
| 6327 ins_cost(380); | |
| 6328 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t" | |
| 6329 "MOVSD $tmp,$src\n\t" | |
| 6330 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %} | |
| 4759 | 6331 ins_encode %{ |
| 6332 __ cmpl(rax, $mem$$Address); | |
| 6333 __ movdbl($tmp$$XMMRegister, Address(rsp, $src$$disp)); | |
| 6334 __ movdbl($mem$$Address, $tmp$$XMMRegister); | |
| 6335 %} | |
| 0 | 6336 ins_pipe( pipe_slow ); |
| 6337 %} | |
| 6338 | |
|
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6339 instruct storeLX_reg_volatile(memory mem, eRegL src, regD tmp2, regD tmp, eFlagsReg cr) %{ |
| 0 | 6340 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access()); |
| 6341 match(Set mem (StoreL mem src)); | |
| 6342 effect( TEMP tmp2 , TEMP tmp, KILL cr ); | |
| 6343 ins_cost(360); | |
| 6344 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t" | |
| 6345 "MOVD $tmp,$src.lo\n\t" | |
| 6346 "MOVD $tmp2,$src.hi\n\t" | |
| 6347 "PUNPCKLDQ $tmp,$tmp2\n\t" | |
| 6348 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %} | |
| 4759 | 6349 ins_encode %{ |
| 6350 __ cmpl(rax, $mem$$Address); | |
| 6351 __ movdl($tmp$$XMMRegister, $src$$Register); | |
| 6352 __ movdl($tmp2$$XMMRegister, HIGH_FROM_LOW($src$$Register)); | |
| 6353 __ punpckldq($tmp$$XMMRegister, $tmp2$$XMMRegister); | |
| 6354 __ movdbl($mem$$Address, $tmp$$XMMRegister); | |
| 6355 %} | |
| 0 | 6356 ins_pipe( pipe_slow ); |
| 6357 %} | |
| 6358 | |
| 6359 // Store Pointer; for storing unknown oops and raw pointers | |
| 6360 instruct storeP(memory mem, anyRegP src) %{ | |
| 6361 match(Set mem (StoreP mem src)); | |
| 6362 | |
| 6363 ins_cost(125); | |
| 6364 format %{ "MOV $mem,$src" %} | |
| 6365 opcode(0x89); | |
| 6366 ins_encode( OpcP, RegMem( src, mem ) ); | |
| 6367 ins_pipe( ialu_mem_reg ); | |
| 6368 %} | |
| 6369 | |
| 6370 // Store Integer Immediate | |
| 6371 instruct storeImmI(memory mem, immI src) %{ | |
| 6372 match(Set mem (StoreI mem src)); | |
| 6373 | |
| 6374 ins_cost(150); | |
| 6375 format %{ "MOV $mem,$src" %} | |
| 6376 opcode(0xC7); /* C7 /0 */ | |
| 6377 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src )); | |
| 6378 ins_pipe( ialu_mem_imm ); | |
| 6379 %} | |
| 6380 | |
| 6381 // Store Short/Char Immediate | |
| 6382 instruct storeImmI16(memory mem, immI16 src) %{ | |
| 6383 predicate(UseStoreImmI16); | |
| 6384 match(Set mem (StoreC mem src)); | |
| 6385 | |
| 6386 ins_cost(150); | |
| 6387 format %{ "MOV16 $mem,$src" %} | |
| 6388 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */ | |
| 6389 ins_encode( SizePrefix, OpcP, RMopc_Mem(0x00,mem), Con16( src )); | |
| 6390 ins_pipe( ialu_mem_imm ); | |
| 6391 %} | |
| 6392 | |
| 6393 // Store Pointer Immediate; null pointers or constant oops that do not | |
| 6394 // need card-mark barriers. | |
| 6395 instruct storeImmP(memory mem, immP src) %{ | |
| 6396 match(Set mem (StoreP mem src)); | |
| 6397 | |
| 6398 ins_cost(150); | |
| 6399 format %{ "MOV $mem,$src" %} | |
| 6400 opcode(0xC7); /* C7 /0 */ | |
| 6401 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src )); | |
| 6402 ins_pipe( ialu_mem_imm ); | |
| 6403 %} | |
| 6404 | |
| 6405 // Store Byte Immediate | |
| 6406 instruct storeImmB(memory mem, immI8 src) %{ | |
| 6407 match(Set mem (StoreB mem src)); | |
| 6408 | |
| 6409 ins_cost(150); | |
| 6410 format %{ "MOV8 $mem,$src" %} | |
| 6411 opcode(0xC6); /* C6 /0 */ | |
| 6412 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src )); | |
| 6413 ins_pipe( ialu_mem_imm ); | |
| 6414 %} | |
| 6415 | |
| 6416 // Store CMS card-mark Immediate | |
| 6417 instruct storeImmCM(memory mem, immI8 src) %{ | |
| 6418 match(Set mem (StoreCM mem src)); | |
| 6419 | |
| 6420 ins_cost(150); | |
| 6421 format %{ "MOV8 $mem,$src\t! CMS card-mark imm0" %} | |
| 6422 opcode(0xC6); /* C6 /0 */ | |
| 6423 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src )); | |
| 6424 ins_pipe( ialu_mem_imm ); | |
| 6425 %} | |
| 6426 | |
| 6427 // Store Double | |
|
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|
6428 instruct storeDPR( memory mem, regDPR1 src) %{ |
| 0 | 6429 predicate(UseSSE<=1); |
| 6430 match(Set mem (StoreD mem src)); | |
| 6431 | |
| 6432 ins_cost(100); | |
| 6433 format %{ "FST_D $mem,$src" %} | |
| 6434 opcode(0xDD); /* DD /2 */ | |
|
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6435 ins_encode( enc_FPR_store(mem,src) ); |
| 0 | 6436 ins_pipe( fpu_mem_reg ); |
| 6437 %} | |
| 6438 | |
| 6439 // Store double does rounding on x86 | |
|
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6440 instruct storeDPR_rounded( memory mem, regDPR1 src) %{ |
| 0 | 6441 predicate(UseSSE<=1); |
| 6442 match(Set mem (StoreD mem (RoundDouble src))); | |
| 6443 | |
| 6444 ins_cost(100); | |
| 6445 format %{ "FST_D $mem,$src\t# round" %} | |
| 6446 opcode(0xDD); /* DD /2 */ | |
|
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6447 ins_encode( enc_FPR_store(mem,src) ); |
| 0 | 6448 ins_pipe( fpu_mem_reg ); |
| 6449 %} | |
| 6450 | |
| 6451 // Store XMM register to memory (double-precision floating points) | |
| 6452 // MOVSD instruction | |
|
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6453 instruct storeD(memory mem, regD src) %{ |
| 0 | 6454 predicate(UseSSE>=2); |
| 6455 match(Set mem (StoreD mem src)); | |
| 6456 ins_cost(95); | |
| 6457 format %{ "MOVSD $mem,$src" %} | |
| 4759 | 6458 ins_encode %{ |
| 6459 __ movdbl($mem$$Address, $src$$XMMRegister); | |
| 6460 %} | |
| 0 | 6461 ins_pipe( pipe_slow ); |
| 6462 %} | |
| 6463 | |
| 6464 // Store XMM register to memory (single-precision floating point) | |
| 6465 // MOVSS instruction | |
|
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6466 instruct storeF(memory mem, regF src) %{ |
| 0 | 6467 predicate(UseSSE>=1); |
| 6468 match(Set mem (StoreF mem src)); | |
| 6469 ins_cost(95); | |
| 6470 format %{ "MOVSS $mem,$src" %} | |
| 4759 | 6471 ins_encode %{ |
| 6472 __ movflt($mem$$Address, $src$$XMMRegister); | |
| 6473 %} | |
| 0 | 6474 ins_pipe( pipe_slow ); |
| 6475 %} | |
| 6476 | |
| 6477 // Store Float | |
|
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6478 instruct storeFPR( memory mem, regFPR1 src) %{ |
| 0 | 6479 predicate(UseSSE==0); |
| 6480 match(Set mem (StoreF mem src)); | |
| 6481 | |
| 6482 ins_cost(100); | |
| 6483 format %{ "FST_S $mem,$src" %} | |
| 6484 opcode(0xD9); /* D9 /2 */ | |
|
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6485 ins_encode( enc_FPR_store(mem,src) ); |
| 0 | 6486 ins_pipe( fpu_mem_reg ); |
| 6487 %} | |
| 6488 | |
| 6489 // Store Float does rounding on x86 | |
|
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6490 instruct storeFPR_rounded( memory mem, regFPR1 src) %{ |
| 0 | 6491 predicate(UseSSE==0); |
| 6492 match(Set mem (StoreF mem (RoundFloat src))); | |
| 6493 | |
| 6494 ins_cost(100); | |
| 6495 format %{ "FST_S $mem,$src\t# round" %} | |
| 6496 opcode(0xD9); /* D9 /2 */ | |
|
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6497 ins_encode( enc_FPR_store(mem,src) ); |
| 0 | 6498 ins_pipe( fpu_mem_reg ); |
| 6499 %} | |
| 6500 | |
| 6501 // Store Float does rounding on x86 | |
|
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6502 instruct storeFPR_Drounded( memory mem, regDPR1 src) %{ |
| 0 | 6503 predicate(UseSSE<=1); |
| 6504 match(Set mem (StoreF mem (ConvD2F src))); | |
| 6505 | |
| 6506 ins_cost(100); | |
| 6507 format %{ "FST_S $mem,$src\t# D-round" %} | |
| 6508 opcode(0xD9); /* D9 /2 */ | |
|
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6509 ins_encode( enc_FPR_store(mem,src) ); |
| 0 | 6510 ins_pipe( fpu_mem_reg ); |
| 6511 %} | |
| 6512 | |
| 6513 // Store immediate Float value (it is faster than store from FPU register) | |
|
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6514 // The instruction usage is guarded by predicate in operand immFPR(). |
|
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6515 instruct storeFPR_imm( memory mem, immFPR src) %{ |
|
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6516 match(Set mem (StoreF mem src)); |
|
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6517 |
|
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6518 ins_cost(50); |
|
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6519 format %{ "MOV $mem,$src\t# store float" %} |
|
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6520 opcode(0xC7); /* C7 /0 */ |
|
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6521 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32FPR_as_bits( src )); |
|
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6522 ins_pipe( ialu_mem_imm ); |
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6523 %} |
|
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6524 |
|
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6525 // Store immediate Float value (it is faster than store from XMM register) |
| 0 | 6526 // The instruction usage is guarded by predicate in operand immF(). |
| 6527 instruct storeF_imm( memory mem, immF src) %{ | |
| 6528 match(Set mem (StoreF mem src)); | |
| 6529 | |
| 6530 ins_cost(50); | |
| 6531 format %{ "MOV $mem,$src\t# store float" %} | |
| 6532 opcode(0xC7); /* C7 /0 */ | |
| 6533 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32F_as_bits( src )); | |
| 6534 ins_pipe( ialu_mem_imm ); | |
| 6535 %} | |
| 6536 | |
| 6537 // Store Integer to stack slot | |
|
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6538 instruct storeSSI(stackSlotI dst, rRegI src) %{ |
| 0 | 6539 match(Set dst src); |
| 6540 | |
| 6541 ins_cost(100); | |
| 6542 format %{ "MOV $dst,$src" %} | |
| 6543 opcode(0x89); | |
| 6544 ins_encode( OpcPRegSS( dst, src ) ); | |
| 6545 ins_pipe( ialu_mem_reg ); | |
| 6546 %} | |
| 6547 | |
| 6548 // Store Integer to stack slot | |
| 6549 instruct storeSSP(stackSlotP dst, eRegP src) %{ | |
| 6550 match(Set dst src); | |
| 6551 | |
| 6552 ins_cost(100); | |
| 6553 format %{ "MOV $dst,$src" %} | |
| 6554 opcode(0x89); | |
| 6555 ins_encode( OpcPRegSS( dst, src ) ); | |
| 6556 ins_pipe( ialu_mem_reg ); | |
| 6557 %} | |
| 6558 | |
| 6559 // Store Long to stack slot | |
| 6560 instruct storeSSL(stackSlotL dst, eRegL src) %{ | |
| 6561 match(Set dst src); | |
| 6562 | |
| 6563 ins_cost(200); | |
| 6564 format %{ "MOV $dst,$src.lo\n\t" | |
| 6565 "MOV $dst+4,$src.hi" %} | |
| 6566 opcode(0x89, 0x89); | |
| 6567 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) ); | |
| 6568 ins_pipe( ialu_mem_long_reg ); | |
| 6569 %} | |
| 6570 | |
| 6571 //----------MemBar Instructions----------------------------------------------- | |
| 6572 // Memory barrier flavors | |
| 6573 | |
| 6574 instruct membar_acquire() %{ | |
| 6575 match(MemBarAcquire); | |
|
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6576 match(LoadFence); |
| 0 | 6577 ins_cost(400); |
| 6578 | |
| 6579 size(0); | |
|
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6580 format %{ "MEMBAR-acquire ! (empty encoding)" %} |
|
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|
6581 ins_encode(); |
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|
6582 ins_pipe(empty); |
| 0 | 6583 %} |
| 6584 | |
| 6585 instruct membar_acquire_lock() %{ | |
|
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7074017: Introduce MemBarAcquireLock/MemBarReleaseLock nodes for monitor enter/exit code paths
roland
parents:
3842
diff
changeset
|
6586 match(MemBarAcquireLock); |
| 0 | 6587 ins_cost(0); |
| 6588 | |
| 6589 size(0); | |
| 6590 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %} | |
| 6591 ins_encode( ); | |
| 6592 ins_pipe(empty); | |
| 6593 %} | |
| 6594 | |
| 6595 instruct membar_release() %{ | |
| 6596 match(MemBarRelease); | |
|
14439
50fdb38839eb
8028515: PPPC64 (part 113.2): opto: Introduce LoadFence/StoreFence.
goetz
parents:
14428
diff
changeset
|
6597 match(StoreFence); |
| 0 | 6598 ins_cost(400); |
| 6599 | |
| 6600 size(0); | |
|
671
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6601 format %{ "MEMBAR-release ! (empty encoding)" %} |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6602 ins_encode( ); |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6603 ins_pipe(empty); |
| 0 | 6604 %} |
| 6605 | |
| 6606 instruct membar_release_lock() %{ | |
|
3849
f1c12354c3f7
7074017: Introduce MemBarAcquireLock/MemBarReleaseLock nodes for monitor enter/exit code paths
roland
parents:
3842
diff
changeset
|
6607 match(MemBarReleaseLock); |
| 0 | 6608 ins_cost(0); |
| 6609 | |
| 6610 size(0); | |
| 6611 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %} | |
| 6612 ins_encode( ); | |
| 6613 ins_pipe(empty); | |
| 6614 %} | |
| 6615 | |
|
671
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6616 instruct membar_volatile(eFlagsReg cr) %{ |
| 0 | 6617 match(MemBarVolatile); |
|
671
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6618 effect(KILL cr); |
| 0 | 6619 ins_cost(400); |
| 6620 | |
|
671
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6621 format %{ |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6622 $$template |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6623 if (os::is_MP()) { |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6624 $$emit$$"LOCK ADDL [ESP + #0], 0\t! membar_volatile" |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6625 } else { |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6626 $$emit$$"MEMBAR-volatile ! (empty encoding)" |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6627 } |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6628 %} |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6629 ins_encode %{ |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6630 __ membar(Assembler::StoreLoad); |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
6631 %} |
| 0 | 6632 ins_pipe(pipe_slow); |
| 6633 %} | |
| 6634 | |
| 6635 instruct unnecessary_membar_volatile() %{ | |
| 6636 match(MemBarVolatile); | |
| 6637 predicate(Matcher::post_store_load_barrier(n)); | |
| 6638 ins_cost(0); | |
| 6639 | |
| 6640 size(0); | |
| 6641 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %} | |
| 6642 ins_encode( ); | |
| 6643 ins_pipe(empty); | |
| 6644 %} | |
| 6645 | |
|
4763
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4761
diff
changeset
|
6646 instruct membar_storestore() %{ |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4761
diff
changeset
|
6647 match(MemBarStoreStore); |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4761
diff
changeset
|
6648 ins_cost(0); |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4761
diff
changeset
|
6649 |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4761
diff
changeset
|
6650 size(0); |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4761
diff
changeset
|
6651 format %{ "MEMBAR-storestore (empty encoding)" %} |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4761
diff
changeset
|
6652 ins_encode( ); |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4761
diff
changeset
|
6653 ins_pipe(empty); |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4761
diff
changeset
|
6654 %} |
|
1dc233a8c7fe
7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents:
4761
diff
changeset
|
6655 |
| 0 | 6656 //----------Move Instructions-------------------------------------------------- |
| 6657 instruct castX2P(eAXRegP dst, eAXRegI src) %{ | |
| 6658 match(Set dst (CastX2P src)); | |
| 6659 format %{ "# X2P $dst, $src" %} | |
| 6660 ins_encode( /*empty encoding*/ ); | |
| 6661 ins_cost(0); | |
| 6662 ins_pipe(empty); | |
| 6663 %} | |
| 6664 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
6665 instruct castP2X(rRegI dst, eRegP src ) %{ |
| 0 | 6666 match(Set dst (CastP2X src)); |
| 6667 ins_cost(50); | |
| 6668 format %{ "MOV $dst, $src\t# CastP2X" %} | |
| 6669 ins_encode( enc_Copy( dst, src) ); | |
| 6670 ins_pipe( ialu_reg_reg ); | |
| 6671 %} | |
| 6672 | |
| 6673 //----------Conditional Move--------------------------------------------------- | |
| 6674 // Conditional move | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
6675 instruct jmovI_reg(cmpOp cop, eFlagsReg cr, rRegI dst, rRegI src) %{ |
| 4047 | 6676 predicate(!VM_Version::supports_cmov() ); |
| 6677 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); | |
| 6678 ins_cost(200); | |
| 6679 format %{ "J$cop,us skip\t# signed cmove\n\t" | |
| 6680 "MOV $dst,$src\n" | |
| 6681 "skip:" %} | |
| 6682 ins_encode %{ | |
| 6683 Label Lskip; | |
| 6684 // Invert sense of branch from sense of CMOV | |
| 6685 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip); | |
| 6686 __ movl($dst$$Register, $src$$Register); | |
| 6687 __ bind(Lskip); | |
| 6688 %} | |
| 6689 ins_pipe( pipe_cmov_reg ); | |
| 6690 %} | |
| 6691 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
6692 instruct jmovI_regU(cmpOpU cop, eFlagsRegU cr, rRegI dst, rRegI src) %{ |
| 4047 | 6693 predicate(!VM_Version::supports_cmov() ); |
| 6694 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); | |
| 6695 ins_cost(200); | |
| 6696 format %{ "J$cop,us skip\t# unsigned cmove\n\t" | |
| 6697 "MOV $dst,$src\n" | |
| 6698 "skip:" %} | |
| 6699 ins_encode %{ | |
| 6700 Label Lskip; | |
| 6701 // Invert sense of branch from sense of CMOV | |
| 6702 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip); | |
| 6703 __ movl($dst$$Register, $src$$Register); | |
| 6704 __ bind(Lskip); | |
| 6705 %} | |
| 6706 ins_pipe( pipe_cmov_reg ); | |
| 6707 %} | |
| 6708 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
6709 instruct cmovI_reg(rRegI dst, rRegI src, eFlagsReg cr, cmpOp cop ) %{ |
| 0 | 6710 predicate(VM_Version::supports_cmov() ); |
| 6711 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); | |
| 6712 ins_cost(200); | |
| 6713 format %{ "CMOV$cop $dst,$src" %} | |
| 6714 opcode(0x0F,0x40); | |
| 6715 ins_encode( enc_cmov(cop), RegReg( dst, src ) ); | |
| 6716 ins_pipe( pipe_cmov_reg ); | |
| 6717 %} | |
| 6718 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
6719 instruct cmovI_regU( cmpOpU cop, eFlagsRegU cr, rRegI dst, rRegI src ) %{ |
| 0 | 6720 predicate(VM_Version::supports_cmov() ); |
| 6721 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); | |
| 6722 ins_cost(200); | |
| 6723 format %{ "CMOV$cop $dst,$src" %} | |
| 6724 opcode(0x0F,0x40); | |
| 6725 ins_encode( enc_cmov(cop), RegReg( dst, src ) ); | |
| 6726 ins_pipe( pipe_cmov_reg ); | |
| 6727 %} | |
| 6728 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
6729 instruct cmovI_regUCF( cmpOpUCF cop, eFlagsRegUCF cr, rRegI dst, rRegI src ) %{ |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6730 predicate(VM_Version::supports_cmov() ); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6731 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6732 ins_cost(200); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6733 expand %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6734 cmovI_regU(cop, cr, dst, src); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6735 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6736 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6737 |
| 0 | 6738 // Conditional move |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
6739 instruct cmovI_mem(cmpOp cop, eFlagsReg cr, rRegI dst, memory src) %{ |
| 0 | 6740 predicate(VM_Version::supports_cmov() ); |
| 6741 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); | |
| 6742 ins_cost(250); | |
| 6743 format %{ "CMOV$cop $dst,$src" %} | |
| 6744 opcode(0x0F,0x40); | |
| 6745 ins_encode( enc_cmov(cop), RegMem( dst, src ) ); | |
| 6746 ins_pipe( pipe_cmov_mem ); | |
| 6747 %} | |
| 6748 | |
| 6749 // Conditional move | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
6750 instruct cmovI_memU(cmpOpU cop, eFlagsRegU cr, rRegI dst, memory src) %{ |
| 0 | 6751 predicate(VM_Version::supports_cmov() ); |
| 6752 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); | |
| 6753 ins_cost(250); | |
| 6754 format %{ "CMOV$cop $dst,$src" %} | |
| 6755 opcode(0x0F,0x40); | |
| 6756 ins_encode( enc_cmov(cop), RegMem( dst, src ) ); | |
| 6757 ins_pipe( pipe_cmov_mem ); | |
| 6758 %} | |
| 6759 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
6760 instruct cmovI_memUCF(cmpOpUCF cop, eFlagsRegUCF cr, rRegI dst, memory src) %{ |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6761 predicate(VM_Version::supports_cmov() ); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6762 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6763 ins_cost(250); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6764 expand %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6765 cmovI_memU(cop, cr, dst, src); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6766 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6767 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6768 |
| 0 | 6769 // Conditional move |
| 6770 instruct cmovP_reg(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{ | |
| 6771 predicate(VM_Version::supports_cmov() ); | |
| 6772 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); | |
| 6773 ins_cost(200); | |
| 6774 format %{ "CMOV$cop $dst,$src\t# ptr" %} | |
| 6775 opcode(0x0F,0x40); | |
| 6776 ins_encode( enc_cmov(cop), RegReg( dst, src ) ); | |
| 6777 ins_pipe( pipe_cmov_reg ); | |
| 6778 %} | |
| 6779 | |
| 6780 // Conditional move (non-P6 version) | |
| 6781 // Note: a CMoveP is generated for stubs and native wrappers | |
| 6782 // regardless of whether we are on a P6, so we | |
| 6783 // emulate a cmov here | |
| 6784 instruct cmovP_reg_nonP6(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{ | |
| 6785 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); | |
| 6786 ins_cost(300); | |
| 6787 format %{ "Jn$cop skip\n\t" | |
| 6788 "MOV $dst,$src\t# pointer\n" | |
| 6789 "skip:" %} | |
| 6790 opcode(0x8b); | |
| 6791 ins_encode( enc_cmov_branch(cop, 0x2), OpcP, RegReg(dst, src)); | |
| 6792 ins_pipe( pipe_cmov_reg ); | |
| 6793 %} | |
| 6794 | |
| 6795 // Conditional move | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6796 instruct cmovP_regU(cmpOpU cop, eFlagsRegU cr, eRegP dst, eRegP src ) %{ |
| 0 | 6797 predicate(VM_Version::supports_cmov() ); |
| 6798 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); | |
| 6799 ins_cost(200); | |
| 6800 format %{ "CMOV$cop $dst,$src\t# ptr" %} | |
| 6801 opcode(0x0F,0x40); | |
| 6802 ins_encode( enc_cmov(cop), RegReg( dst, src ) ); | |
| 6803 ins_pipe( pipe_cmov_reg ); | |
| 6804 %} | |
| 6805 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6806 instruct cmovP_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegP dst, eRegP src ) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6807 predicate(VM_Version::supports_cmov() ); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6808 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6809 ins_cost(200); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6810 expand %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6811 cmovP_regU(cop, cr, dst, src); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6812 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6813 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
6814 |
| 0 | 6815 // DISABLED: Requires the ADLC to emit a bottom_type call that |
| 6816 // correctly meets the two pointer arguments; one is an incoming | |
| 6817 // register but the other is a memory operand. ALSO appears to | |
| 6818 // be buggy with implicit null checks. | |
| 6819 // | |
| 6820 //// Conditional move | |
| 6821 //instruct cmovP_mem(cmpOp cop, eFlagsReg cr, eRegP dst, memory src) %{ | |
| 6822 // predicate(VM_Version::supports_cmov() ); | |
| 6823 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src)))); | |
| 6824 // ins_cost(250); | |
| 6825 // format %{ "CMOV$cop $dst,$src\t# ptr" %} | |
| 6826 // opcode(0x0F,0x40); | |
| 6827 // ins_encode( enc_cmov(cop), RegMem( dst, src ) ); | |
| 6828 // ins_pipe( pipe_cmov_mem ); | |
| 6829 //%} | |
| 6830 // | |
| 6831 //// Conditional move | |
| 6832 //instruct cmovP_memU(cmpOpU cop, eFlagsRegU cr, eRegP dst, memory src) %{ | |
| 6833 // predicate(VM_Version::supports_cmov() ); | |
| 6834 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src)))); | |
| 6835 // ins_cost(250); | |
| 6836 // format %{ "CMOV$cop $dst,$src\t# ptr" %} | |
| 6837 // opcode(0x0F,0x40); | |
| 6838 // ins_encode( enc_cmov(cop), RegMem( dst, src ) ); | |
| 6839 // ins_pipe( pipe_cmov_mem ); | |
| 6840 //%} | |
| 6841 | |
| 6842 // Conditional move | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6843 instruct fcmovDPR_regU(cmpOp_fcmov cop, eFlagsRegU cr, regDPR1 dst, regDPR src) %{ |
| 0 | 6844 predicate(UseSSE<=1); |
| 6845 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); | |
| 6846 ins_cost(200); | |
| 6847 format %{ "FCMOV$cop $dst,$src\t# double" %} | |
| 6848 opcode(0xDA); | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6849 ins_encode( enc_cmov_dpr(cop,src) ); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6850 ins_pipe( pipe_cmovDPR_reg ); |
| 0 | 6851 %} |
| 6852 | |
| 6853 // Conditional move | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
6854 instruct fcmovFPR_regU(cmpOp_fcmov cop, eFlagsRegU cr, regFPR1 dst, regFPR src) %{ |
| 0 | 6855 predicate(UseSSE==0); |
| 6856 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); | |
| 6857 ins_cost(200); | |
| 6858 format %{ "FCMOV$cop $dst,$src\t# float" %} | |
| 6859 opcode(0xDA); | |
|
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|
6860 ins_encode( enc_cmov_dpr(cop,src) ); |
|
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|
6861 ins_pipe( pipe_cmovDPR_reg ); |
| 0 | 6862 %} |
| 6863 | |
| 6864 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned. | |
|
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|
6865 instruct fcmovDPR_regS(cmpOp cop, eFlagsReg cr, regDPR dst, regDPR src) %{ |
| 0 | 6866 predicate(UseSSE<=1); |
| 6867 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); | |
| 6868 ins_cost(200); | |
| 6869 format %{ "Jn$cop skip\n\t" | |
| 6870 "MOV $dst,$src\t# double\n" | |
| 6871 "skip:" %} | |
| 6872 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */ | |
|
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|
6873 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_DPR(src), OpcP, RegOpc(dst) ); |
|
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|
6874 ins_pipe( pipe_cmovDPR_reg ); |
| 0 | 6875 %} |
| 6876 | |
| 6877 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned. | |
|
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|
6878 instruct fcmovFPR_regS(cmpOp cop, eFlagsReg cr, regFPR dst, regFPR src) %{ |
| 0 | 6879 predicate(UseSSE==0); |
| 6880 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); | |
| 6881 ins_cost(200); | |
| 6882 format %{ "Jn$cop skip\n\t" | |
| 6883 "MOV $dst,$src\t# float\n" | |
| 6884 "skip:" %} | |
| 6885 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */ | |
|
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|
6886 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_FPR(src), OpcP, RegOpc(dst) ); |
|
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|
6887 ins_pipe( pipe_cmovDPR_reg ); |
| 0 | 6888 %} |
| 6889 | |
| 6890 // No CMOVE with SSE/SSE2 | |
|
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|
6891 instruct fcmovF_regS(cmpOp cop, eFlagsReg cr, regF dst, regF src) %{ |
| 0 | 6892 predicate (UseSSE>=1); |
| 6893 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); | |
| 6894 ins_cost(200); | |
| 6895 format %{ "Jn$cop skip\n\t" | |
| 6896 "MOVSS $dst,$src\t# float\n" | |
| 6897 "skip:" %} | |
| 6898 ins_encode %{ | |
| 6899 Label skip; | |
| 6900 // Invert sense of branch from sense of CMOV | |
| 6901 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip); | |
| 6902 __ movflt($dst$$XMMRegister, $src$$XMMRegister); | |
| 6903 __ bind(skip); | |
| 6904 %} | |
| 6905 ins_pipe( pipe_slow ); | |
| 6906 %} | |
| 6907 | |
| 6908 // No CMOVE with SSE/SSE2 | |
|
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|
6909 instruct fcmovD_regS(cmpOp cop, eFlagsReg cr, regD dst, regD src) %{ |
| 0 | 6910 predicate (UseSSE>=2); |
| 6911 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); | |
| 6912 ins_cost(200); | |
| 6913 format %{ "Jn$cop skip\n\t" | |
| 6914 "MOVSD $dst,$src\t# float\n" | |
| 6915 "skip:" %} | |
| 6916 ins_encode %{ | |
| 6917 Label skip; | |
| 6918 // Invert sense of branch from sense of CMOV | |
| 6919 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip); | |
| 6920 __ movdbl($dst$$XMMRegister, $src$$XMMRegister); | |
| 6921 __ bind(skip); | |
| 6922 %} | |
| 6923 ins_pipe( pipe_slow ); | |
| 6924 %} | |
| 6925 | |
| 6926 // unsigned version | |
|
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|
6927 instruct fcmovF_regU(cmpOpU cop, eFlagsRegU cr, regF dst, regF src) %{ |
| 0 | 6928 predicate (UseSSE>=1); |
| 6929 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); | |
| 6930 ins_cost(200); | |
| 6931 format %{ "Jn$cop skip\n\t" | |
| 6932 "MOVSS $dst,$src\t# float\n" | |
| 6933 "skip:" %} | |
| 6934 ins_encode %{ | |
| 6935 Label skip; | |
| 6936 // Invert sense of branch from sense of CMOV | |
| 6937 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip); | |
| 6938 __ movflt($dst$$XMMRegister, $src$$XMMRegister); | |
| 6939 __ bind(skip); | |
| 6940 %} | |
| 6941 ins_pipe( pipe_slow ); | |
| 6942 %} | |
| 6943 | |
|
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|
6944 instruct fcmovF_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regF dst, regF src) %{ |
|
415
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changeset
|
6945 predicate (UseSSE>=1); |
|
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|
6946 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); |
|
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|
6947 ins_cost(200); |
|
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diff
changeset
|
6948 expand %{ |
|
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changeset
|
6949 fcmovF_regU(cop, cr, dst, src); |
|
415
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changeset
|
6950 %} |
|
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changeset
|
6951 %} |
|
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diff
changeset
|
6952 |
| 0 | 6953 // unsigned version |
|
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|
6954 instruct fcmovD_regU(cmpOpU cop, eFlagsRegU cr, regD dst, regD src) %{ |
| 0 | 6955 predicate (UseSSE>=2); |
| 6956 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); | |
| 6957 ins_cost(200); | |
| 6958 format %{ "Jn$cop skip\n\t" | |
| 6959 "MOVSD $dst,$src\t# float\n" | |
| 6960 "skip:" %} | |
| 6961 ins_encode %{ | |
| 6962 Label skip; | |
| 6963 // Invert sense of branch from sense of CMOV | |
| 6964 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip); | |
| 6965 __ movdbl($dst$$XMMRegister, $src$$XMMRegister); | |
| 6966 __ bind(skip); | |
| 6967 %} | |
| 6968 ins_pipe( pipe_slow ); | |
| 6969 %} | |
| 6970 | |
|
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|
6971 instruct fcmovD_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regD dst, regD src) %{ |
|
415
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changeset
|
6972 predicate (UseSSE>=2); |
|
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|
6973 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); |
|
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changeset
|
6974 ins_cost(200); |
|
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diff
changeset
|
6975 expand %{ |
|
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changeset
|
6976 fcmovD_regU(cop, cr, dst, src); |
|
415
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diff
changeset
|
6977 %} |
|
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diff
changeset
|
6978 %} |
|
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diff
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|
6979 |
| 0 | 6980 instruct cmovL_reg(cmpOp cop, eFlagsReg cr, eRegL dst, eRegL src) %{ |
| 6981 predicate(VM_Version::supports_cmov() ); | |
| 6982 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); | |
| 6983 ins_cost(200); | |
| 6984 format %{ "CMOV$cop $dst.lo,$src.lo\n\t" | |
| 6985 "CMOV$cop $dst.hi,$src.hi" %} | |
| 6986 opcode(0x0F,0x40); | |
| 6987 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) ); | |
| 6988 ins_pipe( pipe_cmov_reg_long ); | |
| 6989 %} | |
| 6990 | |
| 6991 instruct cmovL_regU(cmpOpU cop, eFlagsRegU cr, eRegL dst, eRegL src) %{ | |
| 6992 predicate(VM_Version::supports_cmov() ); | |
| 6993 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); | |
| 6994 ins_cost(200); | |
| 6995 format %{ "CMOV$cop $dst.lo,$src.lo\n\t" | |
| 6996 "CMOV$cop $dst.hi,$src.hi" %} | |
| 6997 opcode(0x0F,0x40); | |
| 6998 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) ); | |
| 6999 ins_pipe( pipe_cmov_reg_long ); | |
| 7000 %} | |
| 7001 | |
|
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changeset
|
7002 instruct cmovL_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegL dst, eRegL src) %{ |
|
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diff
changeset
|
7003 predicate(VM_Version::supports_cmov() ); |
|
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diff
changeset
|
7004 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); |
|
4d9884b01ba6
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diff
changeset
|
7005 ins_cost(200); |
|
4d9884b01ba6
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never
parents:
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diff
changeset
|
7006 expand %{ |
|
4d9884b01ba6
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diff
changeset
|
7007 cmovL_regU(cop, cr, dst, src); |
|
4d9884b01ba6
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parents:
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diff
changeset
|
7008 %} |
|
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never
parents:
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diff
changeset
|
7009 %} |
|
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diff
changeset
|
7010 |
| 0 | 7011 //----------Arithmetic Instructions-------------------------------------------- |
| 7012 //----------Addition Instructions---------------------------------------------- | |
| 12323 | 7013 |
| 0 | 7014 // Integer Addition Instructions |
|
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|
7015 instruct addI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 7016 match(Set dst (AddI dst src)); |
| 7017 effect(KILL cr); | |
| 7018 | |
| 7019 size(2); | |
| 7020 format %{ "ADD $dst,$src" %} | |
| 7021 opcode(0x03); | |
| 7022 ins_encode( OpcP, RegReg( dst, src) ); | |
| 7023 ins_pipe( ialu_reg_reg ); | |
| 7024 %} | |
| 7025 | |
|
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|
7026 instruct addI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{ |
| 0 | 7027 match(Set dst (AddI dst src)); |
| 7028 effect(KILL cr); | |
| 7029 | |
| 7030 format %{ "ADD $dst,$src" %} | |
| 7031 opcode(0x81, 0x00); /* /0 id */ | |
| 7032 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); | |
| 7033 ins_pipe( ialu_reg ); | |
| 7034 %} | |
| 7035 | |
|
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|
7036 instruct incI_eReg(rRegI dst, immI1 src, eFlagsReg cr) %{ |
| 0 | 7037 predicate(UseIncDec); |
| 7038 match(Set dst (AddI dst src)); | |
| 7039 effect(KILL cr); | |
| 7040 | |
| 7041 size(1); | |
| 7042 format %{ "INC $dst" %} | |
| 7043 opcode(0x40); /* */ | |
| 7044 ins_encode( Opc_plus( primary, dst ) ); | |
| 7045 ins_pipe( ialu_reg ); | |
| 7046 %} | |
| 7047 | |
|
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|
7048 instruct leaI_eReg_immI(rRegI dst, rRegI src0, immI src1) %{ |
| 0 | 7049 match(Set dst (AddI src0 src1)); |
| 7050 ins_cost(110); | |
| 7051 | |
| 7052 format %{ "LEA $dst,[$src0 + $src1]" %} | |
| 7053 opcode(0x8D); /* 0x8D /r */ | |
| 7054 ins_encode( OpcP, RegLea( dst, src0, src1 ) ); | |
| 7055 ins_pipe( ialu_reg_reg ); | |
| 7056 %} | |
| 7057 | |
| 7058 instruct leaP_eReg_immI(eRegP dst, eRegP src0, immI src1) %{ | |
| 7059 match(Set dst (AddP src0 src1)); | |
| 7060 ins_cost(110); | |
| 7061 | |
| 7062 format %{ "LEA $dst,[$src0 + $src1]\t# ptr" %} | |
| 7063 opcode(0x8D); /* 0x8D /r */ | |
| 7064 ins_encode( OpcP, RegLea( dst, src0, src1 ) ); | |
| 7065 ins_pipe( ialu_reg_reg ); | |
| 7066 %} | |
| 7067 | |
|
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|
7068 instruct decI_eReg(rRegI dst, immI_M1 src, eFlagsReg cr) %{ |
| 0 | 7069 predicate(UseIncDec); |
| 7070 match(Set dst (AddI dst src)); | |
| 7071 effect(KILL cr); | |
| 7072 | |
| 7073 size(1); | |
| 7074 format %{ "DEC $dst" %} | |
| 7075 opcode(0x48); /* */ | |
| 7076 ins_encode( Opc_plus( primary, dst ) ); | |
| 7077 ins_pipe( ialu_reg ); | |
| 7078 %} | |
| 7079 | |
|
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|
7080 instruct addP_eReg(eRegP dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 7081 match(Set dst (AddP dst src)); |
| 7082 effect(KILL cr); | |
| 7083 | |
| 7084 size(2); | |
| 7085 format %{ "ADD $dst,$src" %} | |
| 7086 opcode(0x03); | |
| 7087 ins_encode( OpcP, RegReg( dst, src) ); | |
| 7088 ins_pipe( ialu_reg_reg ); | |
| 7089 %} | |
| 7090 | |
| 7091 instruct addP_eReg_imm(eRegP dst, immI src, eFlagsReg cr) %{ | |
| 7092 match(Set dst (AddP dst src)); | |
| 7093 effect(KILL cr); | |
| 7094 | |
| 7095 format %{ "ADD $dst,$src" %} | |
| 7096 opcode(0x81,0x00); /* Opcode 81 /0 id */ | |
| 7097 // ins_encode( RegImm( dst, src) ); | |
| 7098 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); | |
| 7099 ins_pipe( ialu_reg ); | |
| 7100 %} | |
| 7101 | |
|
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|
7102 instruct addI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{ |
| 0 | 7103 match(Set dst (AddI dst (LoadI src))); |
| 7104 effect(KILL cr); | |
| 7105 | |
| 7106 ins_cost(125); | |
| 7107 format %{ "ADD $dst,$src" %} | |
| 7108 opcode(0x03); | |
| 7109 ins_encode( OpcP, RegMem( dst, src) ); | |
| 7110 ins_pipe( ialu_reg_mem ); | |
| 7111 %} | |
| 7112 | |
|
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|
7113 instruct addI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 7114 match(Set dst (StoreI dst (AddI (LoadI dst) src))); |
| 7115 effect(KILL cr); | |
| 7116 | |
| 7117 ins_cost(150); | |
| 7118 format %{ "ADD $dst,$src" %} | |
| 7119 opcode(0x01); /* Opcode 01 /r */ | |
| 7120 ins_encode( OpcP, RegMem( src, dst ) ); | |
| 7121 ins_pipe( ialu_mem_reg ); | |
| 7122 %} | |
| 7123 | |
| 7124 // Add Memory with Immediate | |
| 7125 instruct addI_mem_imm(memory dst, immI src, eFlagsReg cr) %{ | |
| 7126 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 7127 effect(KILL cr); | |
| 7128 | |
| 7129 ins_cost(125); | |
| 7130 format %{ "ADD $dst,$src" %} | |
| 7131 opcode(0x81); /* Opcode 81 /0 id */ | |
| 7132 ins_encode( OpcSE( src ), RMopc_Mem(0x00,dst), Con8or32( src ) ); | |
| 7133 ins_pipe( ialu_mem_imm ); | |
| 7134 %} | |
| 7135 | |
| 7136 instruct incI_mem(memory dst, immI1 src, eFlagsReg cr) %{ | |
| 7137 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 7138 effect(KILL cr); | |
| 7139 | |
| 7140 ins_cost(125); | |
| 7141 format %{ "INC $dst" %} | |
| 7142 opcode(0xFF); /* Opcode FF /0 */ | |
| 7143 ins_encode( OpcP, RMopc_Mem(0x00,dst)); | |
| 7144 ins_pipe( ialu_mem_imm ); | |
| 7145 %} | |
| 7146 | |
| 7147 instruct decI_mem(memory dst, immI_M1 src, eFlagsReg cr) %{ | |
| 7148 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 7149 effect(KILL cr); | |
| 7150 | |
| 7151 ins_cost(125); | |
| 7152 format %{ "DEC $dst" %} | |
| 7153 opcode(0xFF); /* Opcode FF /1 */ | |
| 7154 ins_encode( OpcP, RMopc_Mem(0x01,dst)); | |
| 7155 ins_pipe( ialu_mem_imm ); | |
| 7156 %} | |
| 7157 | |
| 7158 | |
| 7159 instruct checkCastPP( eRegP dst ) %{ | |
| 7160 match(Set dst (CheckCastPP dst)); | |
| 7161 | |
| 7162 size(0); | |
| 7163 format %{ "#checkcastPP of $dst" %} | |
| 7164 ins_encode( /*empty encoding*/ ); | |
| 7165 ins_pipe( empty ); | |
| 7166 %} | |
| 7167 | |
| 7168 instruct castPP( eRegP dst ) %{ | |
| 7169 match(Set dst (CastPP dst)); | |
| 7170 format %{ "#castPP of $dst" %} | |
| 7171 ins_encode( /*empty encoding*/ ); | |
| 7172 ins_pipe( empty ); | |
| 7173 %} | |
| 7174 | |
|
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|
7175 instruct castII( rRegI dst ) %{ |
| 0 | 7176 match(Set dst (CastII dst)); |
| 7177 format %{ "#castII of $dst" %} | |
| 7178 ins_encode( /*empty encoding*/ ); | |
| 7179 ins_cost(0); | |
| 7180 ins_pipe( empty ); | |
| 7181 %} | |
| 7182 | |
| 7183 | |
| 7184 // Load-locked - same as a regular pointer load when used with compare-swap | |
| 7185 instruct loadPLocked(eRegP dst, memory mem) %{ | |
| 7186 match(Set dst (LoadPLocked mem)); | |
| 7187 | |
| 7188 ins_cost(125); | |
| 7189 format %{ "MOV $dst,$mem\t# Load ptr. locked" %} | |
| 7190 opcode(0x8B); | |
| 7191 ins_encode( OpcP, RegMem(dst,mem)); | |
| 7192 ins_pipe( ialu_reg_mem ); | |
| 7193 %} | |
| 7194 | |
| 7195 // Conditional-store of the updated heap-top. | |
| 7196 // Used during allocation of the shared heap. | |
| 7197 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel. | |
| 7198 instruct storePConditional( memory heap_top_ptr, eAXRegP oldval, eRegP newval, eFlagsReg cr ) %{ | |
| 7199 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval))); | |
| 7200 // EAX is killed if there is contention, but then it's also unused. | |
| 7201 // In the common case of no contention, EAX holds the new oop address. | |
| 7202 format %{ "CMPXCHG $heap_top_ptr,$newval\t# If EAX==$heap_top_ptr Then store $newval into $heap_top_ptr" %} | |
| 7203 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval,heap_top_ptr) ); | |
| 7204 ins_pipe( pipe_cmpxchg ); | |
| 7205 %} | |
| 7206 | |
|
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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parents:
415
diff
changeset
|
7207 // Conditional-store of an int value. |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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parents:
415
diff
changeset
|
7208 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG on Intel. |
|
6179
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7119644: Increase superword's vector size up to 256 bits
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diff
changeset
|
7209 instruct storeIConditional( memory mem, eAXRegI oldval, rRegI newval, eFlagsReg cr ) %{ |
|
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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parents:
415
diff
changeset
|
7210 match(Set cr (StoreIConditional mem (Binary oldval newval))); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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parents:
415
diff
changeset
|
7211 effect(KILL oldval); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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415
diff
changeset
|
7212 format %{ "CMPXCHG $mem,$newval\t# If EAX==$mem Then store $newval into $mem" %} |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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parents:
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diff
changeset
|
7213 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval, mem) ); |
| 0 | 7214 ins_pipe( pipe_cmpxchg ); |
| 7215 %} | |
| 7216 | |
|
420
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6462850: generate biased locking code in C2 ideal graph
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parents:
415
diff
changeset
|
7217 // Conditional-store of a long value. |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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parents:
415
diff
changeset
|
7218 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG8 on Intel. |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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415
diff
changeset
|
7219 instruct storeLConditional( memory mem, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{ |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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parents:
415
diff
changeset
|
7220 match(Set cr (StoreLConditional mem (Binary oldval newval))); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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parents:
415
diff
changeset
|
7221 effect(KILL oldval); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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parents:
415
diff
changeset
|
7222 format %{ "XCHG EBX,ECX\t# correct order for CMPXCHG8 instruction\n\t" |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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parents:
415
diff
changeset
|
7223 "CMPXCHG8 $mem,ECX:EBX\t# If EDX:EAX==$mem Then store ECX:EBX into $mem\n\t" |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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parents:
415
diff
changeset
|
7224 "XCHG EBX,ECX" |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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parents:
415
diff
changeset
|
7225 %} |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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diff
changeset
|
7226 ins_encode %{ |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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parents:
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diff
changeset
|
7227 // Note: we need to swap rbx, and rcx before and after the |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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parents:
415
diff
changeset
|
7228 // cmpxchg8 instruction because the instruction uses |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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parents:
415
diff
changeset
|
7229 // rcx as the high order word of the new value to store but |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7230 // our register encoding uses rbx. |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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parents:
415
diff
changeset
|
7231 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc)); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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parents:
415
diff
changeset
|
7232 if( os::is_MP() ) |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
7233 __ lock(); |
| 624 | 7234 __ cmpxchg8($mem$$Address); |
|
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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parents:
415
diff
changeset
|
7235 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc)); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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parents:
415
diff
changeset
|
7236 %} |
| 0 | 7237 ins_pipe( pipe_cmpxchg ); |
| 7238 %} | |
| 7239 | |
| 7240 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them | |
| 7241 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
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parents:
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diff
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|
7242 instruct compareAndSwapL( rRegI res, eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{ |
|
6795
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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6725
diff
changeset
|
7243 predicate(VM_Version::supports_cx8()); |
| 0 | 7244 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval))); |
| 7245 effect(KILL cr, KILL oldval); | |
| 7246 format %{ "CMPXCHG8 [$mem_ptr],$newval\t# If EDX:EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t" | |
| 7247 "MOV $res,0\n\t" | |
| 7248 "JNE,s fail\n\t" | |
| 7249 "MOV $res,1\n" | |
| 7250 "fail:" %} | |
| 7251 ins_encode( enc_cmpxchg8(mem_ptr), | |
| 7252 enc_flags_ne_to_boolean(res) ); | |
| 7253 ins_pipe( pipe_cmpxchg ); | |
| 7254 %} | |
| 7255 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
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diff
changeset
|
7256 instruct compareAndSwapP( rRegI res, pRegP mem_ptr, eAXRegP oldval, eCXRegP newval, eFlagsReg cr) %{ |
| 0 | 7257 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval))); |
| 7258 effect(KILL cr, KILL oldval); | |
| 7259 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t" | |
| 7260 "MOV $res,0\n\t" | |
| 7261 "JNE,s fail\n\t" | |
| 7262 "MOV $res,1\n" | |
| 7263 "fail:" %} | |
| 7264 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) ); | |
| 7265 ins_pipe( pipe_cmpxchg ); | |
| 7266 %} | |
| 7267 | |
|
6179
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7119644: Increase superword's vector size up to 256 bits
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parents:
6143
diff
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|
7268 instruct compareAndSwapI( rRegI res, pRegP mem_ptr, eAXRegI oldval, eCXRegI newval, eFlagsReg cr) %{ |
| 0 | 7269 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval))); |
| 7270 effect(KILL cr, KILL oldval); | |
| 7271 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t" | |
| 7272 "MOV $res,0\n\t" | |
| 7273 "JNE,s fail\n\t" | |
| 7274 "MOV $res,1\n" | |
| 7275 "fail:" %} | |
| 7276 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) ); | |
| 7277 ins_pipe( pipe_cmpxchg ); | |
| 7278 %} | |
| 7279 | |
|
6795
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7280 instruct xaddI_no_res( memory mem, Universe dummy, immI add, eFlagsReg cr) %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
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6725
diff
changeset
|
7281 predicate(n->as_LoadStore()->result_not_used()); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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parents:
6725
diff
changeset
|
7282 match(Set dummy (GetAndAddI mem add)); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7283 effect(KILL cr); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7284 format %{ "ADDL [$mem],$add" %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7285 ins_encode %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7286 if (os::is_MP()) { __ lock(); } |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7287 __ addl($mem$$Address, $add$$constant); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7288 %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7289 ins_pipe( pipe_cmpxchg ); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7290 %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7291 |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7292 instruct xaddI( memory mem, rRegI newval, eFlagsReg cr) %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7293 match(Set newval (GetAndAddI mem newval)); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7294 effect(KILL cr); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7295 format %{ "XADDL [$mem],$newval" %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7296 ins_encode %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7297 if (os::is_MP()) { __ lock(); } |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7298 __ xaddl($mem$$Address, $newval$$Register); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7299 %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7300 ins_pipe( pipe_cmpxchg ); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7301 %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7302 |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7303 instruct xchgI( memory mem, rRegI newval) %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7304 match(Set newval (GetAndSetI mem newval)); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7305 format %{ "XCHGL $newval,[$mem]" %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7306 ins_encode %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7307 __ xchgl($newval$$Register, $mem$$Address); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7308 %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7309 ins_pipe( pipe_cmpxchg ); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7310 %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7311 |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7312 instruct xchgP( memory mem, pRegP newval) %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7313 match(Set newval (GetAndSetP mem newval)); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7314 format %{ "XCHGL $newval,[$mem]" %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7315 ins_encode %{ |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7316 __ xchgl($newval$$Register, $mem$$Address); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7317 %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
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6725
diff
changeset
|
7318 ins_pipe( pipe_cmpxchg ); |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
7319 %} |
|
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
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6725
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changeset
|
7320 |
| 0 | 7321 //----------Subtraction Instructions------------------------------------------- |
|
12972
59e8ad757e19
8026844: Various Math functions needs intrinsification
rbackman
parents:
12334
diff
changeset
|
7322 |
| 0 | 7323 // Integer Subtraction Instructions |
|
6179
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7119644: Increase superword's vector size up to 256 bits
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diff
changeset
|
7324 instruct subI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 7325 match(Set dst (SubI dst src)); |
| 7326 effect(KILL cr); | |
| 7327 | |
| 7328 size(2); | |
| 7329 format %{ "SUB $dst,$src" %} | |
| 7330 opcode(0x2B); | |
| 7331 ins_encode( OpcP, RegReg( dst, src) ); | |
| 7332 ins_pipe( ialu_reg_reg ); | |
| 7333 %} | |
| 7334 | |
|
6179
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7119644: Increase superword's vector size up to 256 bits
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6143
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changeset
|
7335 instruct subI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{ |
| 0 | 7336 match(Set dst (SubI dst src)); |
| 7337 effect(KILL cr); | |
| 7338 | |
| 7339 format %{ "SUB $dst,$src" %} | |
| 7340 opcode(0x81,0x05); /* Opcode 81 /5 */ | |
| 7341 // ins_encode( RegImm( dst, src) ); | |
| 7342 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); | |
| 7343 ins_pipe( ialu_reg ); | |
| 7344 %} | |
| 7345 | |
|
6179
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7119644: Increase superword's vector size up to 256 bits
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6143
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changeset
|
7346 instruct subI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{ |
| 0 | 7347 match(Set dst (SubI dst (LoadI src))); |
| 7348 effect(KILL cr); | |
| 7349 | |
| 7350 ins_cost(125); | |
| 7351 format %{ "SUB $dst,$src" %} | |
| 7352 opcode(0x2B); | |
| 7353 ins_encode( OpcP, RegMem( dst, src) ); | |
| 7354 ins_pipe( ialu_reg_mem ); | |
| 7355 %} | |
| 7356 | |
|
6179
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7119644: Increase superword's vector size up to 256 bits
kvn
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6143
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changeset
|
7357 instruct subI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 7358 match(Set dst (StoreI dst (SubI (LoadI dst) src))); |
| 7359 effect(KILL cr); | |
| 7360 | |
| 7361 ins_cost(150); | |
| 7362 format %{ "SUB $dst,$src" %} | |
| 7363 opcode(0x29); /* Opcode 29 /r */ | |
| 7364 ins_encode( OpcP, RegMem( src, dst ) ); | |
| 7365 ins_pipe( ialu_mem_reg ); | |
| 7366 %} | |
| 7367 | |
| 7368 // Subtract from a pointer | |
|
6179
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7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
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changeset
|
7369 instruct subP_eReg(eRegP dst, rRegI src, immI0 zero, eFlagsReg cr) %{ |
| 0 | 7370 match(Set dst (AddP dst (SubI zero src))); |
| 7371 effect(KILL cr); | |
| 7372 | |
| 7373 size(2); | |
| 7374 format %{ "SUB $dst,$src" %} | |
| 7375 opcode(0x2B); | |
| 7376 ins_encode( OpcP, RegReg( dst, src) ); | |
| 7377 ins_pipe( ialu_reg_reg ); | |
| 7378 %} | |
| 7379 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7380 instruct negI_eReg(rRegI dst, immI0 zero, eFlagsReg cr) %{ |
| 0 | 7381 match(Set dst (SubI zero dst)); |
| 7382 effect(KILL cr); | |
| 7383 | |
| 7384 size(2); | |
| 7385 format %{ "NEG $dst" %} | |
| 7386 opcode(0xF7,0x03); // Opcode F7 /3 | |
| 7387 ins_encode( OpcP, RegOpc( dst ) ); | |
| 7388 ins_pipe( ialu_reg ); | |
| 7389 %} | |
| 7390 | |
| 7391 //----------Multiplication/Division Instructions------------------------------- | |
| 7392 // Integer Multiplication Instructions | |
| 7393 // Multiply Register | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6143
diff
changeset
|
7394 instruct mulI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 7395 match(Set dst (MulI dst src)); |
| 7396 effect(KILL cr); | |
| 7397 | |
| 7398 size(3); | |
| 7399 ins_cost(300); | |
| 7400 format %{ "IMUL $dst,$src" %} | |
| 7401 opcode(0xAF, 0x0F); | |
| 7402 ins_encode( OpcS, OpcP, RegReg( dst, src) ); | |
| 7403 ins_pipe( ialu_reg_reg_alu0 ); | |
| 7404 %} | |
| 7405 | |
| 7406 // Multiply 32-bit Immediate | |
|
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|
7407 instruct mulI_eReg_imm(rRegI dst, rRegI src, immI imm, eFlagsReg cr) %{ |
| 0 | 7408 match(Set dst (MulI src imm)); |
| 7409 effect(KILL cr); | |
| 7410 | |
| 7411 ins_cost(300); | |
| 7412 format %{ "IMUL $dst,$src,$imm" %} | |
| 7413 opcode(0x69); /* 69 /r id */ | |
| 7414 ins_encode( OpcSE(imm), RegReg( dst, src ), Con8or32( imm ) ); | |
| 7415 ins_pipe( ialu_reg_reg_alu0 ); | |
| 7416 %} | |
| 7417 | |
| 7418 instruct loadConL_low_only(eADXRegL_low_only dst, immL32 src, eFlagsReg cr) %{ | |
| 7419 match(Set dst src); | |
| 7420 effect(KILL cr); | |
| 7421 | |
| 7422 // Note that this is artificially increased to make it more expensive than loadConL | |
| 7423 ins_cost(250); | |
| 7424 format %{ "MOV EAX,$src\t// low word only" %} | |
| 7425 opcode(0xB8); | |
| 7426 ins_encode( LdImmL_Lo(dst, src) ); | |
| 7427 ins_pipe( ialu_reg_fat ); | |
| 7428 %} | |
| 7429 | |
| 7430 // Multiply by 32-bit Immediate, taking the shifted high order results | |
| 7431 // (special case for shift by 32) | |
| 7432 instruct mulI_imm_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32 cnt, eFlagsReg cr) %{ | |
| 7433 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt))); | |
| 7434 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL && | |
| 7435 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint && | |
| 7436 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint ); | |
| 7437 effect(USE src1, KILL cr); | |
| 7438 | |
| 7439 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only | |
| 7440 ins_cost(0*100 + 1*400 - 150); | |
| 7441 format %{ "IMUL EDX:EAX,$src1" %} | |
| 7442 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) ); | |
| 7443 ins_pipe( pipe_slow ); | |
| 7444 %} | |
| 7445 | |
| 7446 // Multiply by 32-bit Immediate, taking the shifted high order results | |
| 7447 instruct mulI_imm_RShift_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr) %{ | |
| 7448 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt))); | |
| 7449 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL && | |
| 7450 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint && | |
| 7451 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint ); | |
| 7452 effect(USE src1, KILL cr); | |
| 7453 | |
| 7454 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only | |
| 7455 ins_cost(1*100 + 1*400 - 150); | |
| 7456 format %{ "IMUL EDX:EAX,$src1\n\t" | |
| 7457 "SAR EDX,$cnt-32" %} | |
| 7458 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) ); | |
| 7459 ins_pipe( pipe_slow ); | |
| 7460 %} | |
| 7461 | |
| 7462 // Multiply Memory 32-bit Immediate | |
|
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|
7463 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, eFlagsReg cr) %{ |
| 0 | 7464 match(Set dst (MulI (LoadI src) imm)); |
| 7465 effect(KILL cr); | |
| 7466 | |
| 7467 ins_cost(300); | |
| 7468 format %{ "IMUL $dst,$src,$imm" %} | |
| 7469 opcode(0x69); /* 69 /r id */ | |
| 7470 ins_encode( OpcSE(imm), RegMem( dst, src ), Con8or32( imm ) ); | |
| 7471 ins_pipe( ialu_reg_mem_alu0 ); | |
| 7472 %} | |
| 7473 | |
| 7474 // Multiply Memory | |
|
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|
7475 instruct mulI(rRegI dst, memory src, eFlagsReg cr) %{ |
| 0 | 7476 match(Set dst (MulI dst (LoadI src))); |
| 7477 effect(KILL cr); | |
| 7478 | |
| 7479 ins_cost(350); | |
| 7480 format %{ "IMUL $dst,$src" %} | |
| 7481 opcode(0xAF, 0x0F); | |
| 7482 ins_encode( OpcS, OpcP, RegMem( dst, src) ); | |
| 7483 ins_pipe( ialu_reg_mem_alu0 ); | |
| 7484 %} | |
| 7485 | |
| 7486 // Multiply Register Int to Long | |
| 7487 instruct mulI2L(eADXRegL dst, eAXRegI src, nadxRegI src1, eFlagsReg flags) %{ | |
| 7488 // Basic Idea: long = (long)int * (long)int | |
| 7489 match(Set dst (MulL (ConvI2L src) (ConvI2L src1))); | |
| 7490 effect(DEF dst, USE src, USE src1, KILL flags); | |
| 7491 | |
| 7492 ins_cost(300); | |
| 7493 format %{ "IMUL $dst,$src1" %} | |
| 7494 | |
| 7495 ins_encode( long_int_multiply( dst, src1 ) ); | |
| 7496 ins_pipe( ialu_reg_reg_alu0 ); | |
| 7497 %} | |
| 7498 | |
| 7499 instruct mulIS_eReg(eADXRegL dst, immL_32bits mask, eFlagsReg flags, eAXRegI src, nadxRegI src1) %{ | |
| 7500 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL) | |
| 7501 match(Set dst (MulL (AndL (ConvI2L src) mask) (AndL (ConvI2L src1) mask))); | |
| 7502 effect(KILL flags); | |
| 7503 | |
| 7504 ins_cost(300); | |
| 7505 format %{ "MUL $dst,$src1" %} | |
| 7506 | |
| 7507 ins_encode( long_uint_multiply(dst, src1) ); | |
| 7508 ins_pipe( ialu_reg_reg_alu0 ); | |
| 7509 %} | |
| 7510 | |
| 7511 // Multiply Register Long | |
|
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|
7512 instruct mulL_eReg(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{ |
| 0 | 7513 match(Set dst (MulL dst src)); |
| 7514 effect(KILL cr, TEMP tmp); | |
| 7515 ins_cost(4*100+3*400); | |
| 7516 // Basic idea: lo(result) = lo(x_lo * y_lo) | |
| 7517 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi) | |
| 7518 format %{ "MOV $tmp,$src.lo\n\t" | |
| 7519 "IMUL $tmp,EDX\n\t" | |
| 7520 "MOV EDX,$src.hi\n\t" | |
| 7521 "IMUL EDX,EAX\n\t" | |
| 7522 "ADD $tmp,EDX\n\t" | |
| 7523 "MUL EDX:EAX,$src.lo\n\t" | |
| 7524 "ADD EDX,$tmp" %} | |
| 7525 ins_encode( long_multiply( dst, src, tmp ) ); | |
| 7526 ins_pipe( pipe_slow ); | |
| 7527 %} | |
| 7528 | |
|
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|
7529 // Multiply Register Long where the left operand's high 32 bits are zero |
|
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|
7530 instruct mulL_eReg_lhi0(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{ |
|
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|
7531 predicate(is_operand_hi32_zero(n->in(1))); |
|
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|
7532 match(Set dst (MulL dst src)); |
|
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|
7533 effect(KILL cr, TEMP tmp); |
|
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|
7534 ins_cost(2*100+2*400); |
|
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|
7535 // Basic idea: lo(result) = lo(x_lo * y_lo) |
|
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7536 // hi(result) = hi(x_lo * y_lo) + lo(x_lo * y_hi) where lo(x_hi * y_lo) = 0 because x_hi = 0 |
|
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|
7537 format %{ "MOV $tmp,$src.hi\n\t" |
|
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|
7538 "IMUL $tmp,EAX\n\t" |
|
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|
7539 "MUL EDX:EAX,$src.lo\n\t" |
|
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|
7540 "ADD EDX,$tmp" %} |
|
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|
7541 ins_encode %{ |
|
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|
7542 __ movl($tmp$$Register, HIGH_FROM_LOW($src$$Register)); |
|
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|
7543 __ imull($tmp$$Register, rax); |
|
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|
7544 __ mull($src$$Register); |
|
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|
7545 __ addl(rdx, $tmp$$Register); |
|
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|
7546 %} |
|
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changeset
|
7547 ins_pipe( pipe_slow ); |
|
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|
7548 %} |
|
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|
7549 |
|
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|
7550 // Multiply Register Long where the right operand's high 32 bits are zero |
|
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|
7551 instruct mulL_eReg_rhi0(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{ |
|
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|
7552 predicate(is_operand_hi32_zero(n->in(2))); |
|
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|
7553 match(Set dst (MulL dst src)); |
|
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|
7554 effect(KILL cr, TEMP tmp); |
|
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|
7555 ins_cost(2*100+2*400); |
|
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|
7556 // Basic idea: lo(result) = lo(x_lo * y_lo) |
|
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7557 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) where lo(x_lo * y_hi) = 0 because y_hi = 0 |
|
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|
7558 format %{ "MOV $tmp,$src.lo\n\t" |
|
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|
7559 "IMUL $tmp,EDX\n\t" |
|
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|
7560 "MUL EDX:EAX,$src.lo\n\t" |
|
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|
7561 "ADD EDX,$tmp" %} |
|
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|
7562 ins_encode %{ |
|
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|
7563 __ movl($tmp$$Register, $src$$Register); |
|
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|
7564 __ imull($tmp$$Register, rdx); |
|
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|
7565 __ mull($src$$Register); |
|
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|
7566 __ addl(rdx, $tmp$$Register); |
|
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|
7567 %} |
|
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changeset
|
7568 ins_pipe( pipe_slow ); |
|
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changeset
|
7569 %} |
|
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diff
changeset
|
7570 |
|
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|
7571 // Multiply Register Long where the left and the right operands' high 32 bits are zero |
|
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1137
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|
7572 instruct mulL_eReg_hi0(eADXRegL dst, eRegL src, eFlagsReg cr) %{ |
|
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|
7573 predicate(is_operand_hi32_zero(n->in(1)) && is_operand_hi32_zero(n->in(2))); |
|
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|
7574 match(Set dst (MulL dst src)); |
|
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changeset
|
7575 effect(KILL cr); |
|
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|
7576 ins_cost(1*400); |
|
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changeset
|
7577 // Basic idea: lo(result) = lo(x_lo * y_lo) |
|
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changeset
|
7578 // hi(result) = hi(x_lo * y_lo) where lo(x_hi * y_lo) = 0 and lo(x_lo * y_hi) = 0 because x_hi = 0 and y_hi = 0 |
|
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changeset
|
7579 format %{ "MUL EDX:EAX,$src.lo\n\t" %} |
|
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changeset
|
7580 ins_encode %{ |
|
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|
7581 __ mull($src$$Register); |
|
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|
7582 %} |
|
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changeset
|
7583 ins_pipe( pipe_slow ); |
|
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|
7584 %} |
|
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|
7585 |
| 0 | 7586 // Multiply Register Long by small constant |
|
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|
7587 instruct mulL_eReg_con(eADXRegL dst, immL_127 src, rRegI tmp, eFlagsReg cr) %{ |
| 0 | 7588 match(Set dst (MulL dst src)); |
| 7589 effect(KILL cr, TEMP tmp); | |
| 7590 ins_cost(2*100+2*400); | |
| 7591 size(12); | |
| 7592 // Basic idea: lo(result) = lo(src * EAX) | |
| 7593 // hi(result) = hi(src * EAX) + lo(src * EDX) | |
| 7594 format %{ "IMUL $tmp,EDX,$src\n\t" | |
| 7595 "MOV EDX,$src\n\t" | |
| 7596 "MUL EDX\t# EDX*EAX -> EDX:EAX\n\t" | |
| 7597 "ADD EDX,$tmp" %} | |
| 7598 ins_encode( long_multiply_con( dst, src, tmp ) ); | |
| 7599 ins_pipe( pipe_slow ); | |
| 7600 %} | |
| 7601 | |
| 7602 // Integer DIV with Register | |
| 7603 instruct divI_eReg(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{ | |
| 7604 match(Set rax (DivI rax div)); | |
| 7605 effect(KILL rdx, KILL cr); | |
| 7606 size(26); | |
| 7607 ins_cost(30*100+10*100); | |
| 7608 format %{ "CMP EAX,0x80000000\n\t" | |
| 7609 "JNE,s normal\n\t" | |
| 7610 "XOR EDX,EDX\n\t" | |
| 7611 "CMP ECX,-1\n\t" | |
| 7612 "JE,s done\n" | |
| 7613 "normal: CDQ\n\t" | |
| 7614 "IDIV $div\n\t" | |
| 7615 "done:" %} | |
| 7616 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 7617 ins_encode( cdq_enc, OpcP, RegOpc(div) ); | |
| 7618 ins_pipe( ialu_reg_reg_alu0 ); | |
| 7619 %} | |
| 7620 | |
| 7621 // Divide Register Long | |
| 7622 instruct divL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{ | |
| 7623 match(Set dst (DivL src1 src2)); | |
| 7624 effect( KILL cr, KILL cx, KILL bx ); | |
| 7625 ins_cost(10000); | |
| 7626 format %{ "PUSH $src1.hi\n\t" | |
| 7627 "PUSH $src1.lo\n\t" | |
| 7628 "PUSH $src2.hi\n\t" | |
| 7629 "PUSH $src2.lo\n\t" | |
| 7630 "CALL SharedRuntime::ldiv\n\t" | |
| 7631 "ADD ESP,16" %} | |
| 7632 ins_encode( long_div(src1,src2) ); | |
| 7633 ins_pipe( pipe_slow ); | |
| 7634 %} | |
| 7635 | |
| 7636 // Integer DIVMOD with Register, both quotient and mod results | |
| 7637 instruct divModI_eReg_divmod(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{ | |
| 7638 match(DivModI rax div); | |
| 7639 effect(KILL cr); | |
| 7640 size(26); | |
| 7641 ins_cost(30*100+10*100); | |
| 7642 format %{ "CMP EAX,0x80000000\n\t" | |
| 7643 "JNE,s normal\n\t" | |
| 7644 "XOR EDX,EDX\n\t" | |
| 7645 "CMP ECX,-1\n\t" | |
| 7646 "JE,s done\n" | |
| 7647 "normal: CDQ\n\t" | |
| 7648 "IDIV $div\n\t" | |
| 7649 "done:" %} | |
| 7650 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 7651 ins_encode( cdq_enc, OpcP, RegOpc(div) ); | |
| 7652 ins_pipe( pipe_slow ); | |
| 7653 %} | |
| 7654 | |
| 7655 // Integer MOD with Register | |
| 7656 instruct modI_eReg(eDXRegI rdx, eAXRegI rax, eCXRegI div, eFlagsReg cr) %{ | |
| 7657 match(Set rdx (ModI rax div)); | |
| 7658 effect(KILL rax, KILL cr); | |
| 7659 | |
| 7660 size(26); | |
| 7661 ins_cost(300); | |
| 7662 format %{ "CDQ\n\t" | |
| 7663 "IDIV $div" %} | |
| 7664 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 7665 ins_encode( cdq_enc, OpcP, RegOpc(div) ); | |
| 7666 ins_pipe( ialu_reg_reg_alu0 ); | |
| 7667 %} | |
| 7668 | |
| 7669 // Remainder Register Long | |
| 7670 instruct modL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{ | |
| 7671 match(Set dst (ModL src1 src2)); | |
| 7672 effect( KILL cr, KILL cx, KILL bx ); | |
| 7673 ins_cost(10000); | |
| 7674 format %{ "PUSH $src1.hi\n\t" | |
| 7675 "PUSH $src1.lo\n\t" | |
| 7676 "PUSH $src2.hi\n\t" | |
| 7677 "PUSH $src2.lo\n\t" | |
| 7678 "CALL SharedRuntime::lrem\n\t" | |
| 7679 "ADD ESP,16" %} | |
| 7680 ins_encode( long_mod(src1,src2) ); | |
| 7681 ins_pipe( pipe_slow ); | |
| 7682 %} | |
| 7683 | |
|
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|
7684 // Divide Register Long (no special case since divisor != -1) |
|
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|
7685 instruct divL_eReg_imm32( eADXRegL dst, immL32 imm, rRegI tmp, rRegI tmp2, eFlagsReg cr ) %{ |
|
1914
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|
7686 match(Set dst (DivL dst imm)); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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diff
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|
7687 effect( TEMP tmp, TEMP tmp2, KILL cr ); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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|
7688 ins_cost(1000); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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|
7689 format %{ "MOV $tmp,abs($imm) # ldiv EDX:EAX,$imm\n\t" |
| 1920 | 7690 "XOR $tmp2,$tmp2\n\t" |
|
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|
7691 "CMP $tmp,EDX\n\t" |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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|
7692 "JA,s fast\n\t" |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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|
7693 "MOV $tmp2,EAX\n\t" |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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|
7694 "MOV EAX,EDX\n\t" |
| 1920 | 7695 "MOV EDX,0\n\t" |
| 7696 "JLE,s pos\n\t" | |
| 7697 "LNEG EAX : $tmp2\n\t" | |
| 7698 "DIV $tmp # unsigned division\n\t" | |
| 7699 "XCHG EAX,$tmp2\n\t" | |
| 7700 "DIV $tmp\n\t" | |
| 7701 "LNEG $tmp2 : EAX\n\t" | |
|
1914
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|
7702 "JMP,s done\n" |
| 1920 | 7703 "pos:\n\t" |
| 7704 "DIV $tmp\n\t" | |
| 7705 "XCHG EAX,$tmp2\n" | |
|
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diff
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|
7706 "fast:\n\t" |
| 1920 | 7707 "DIV $tmp\n" |
|
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|
7708 "done:\n\t" |
| 1920 | 7709 "MOV EDX,$tmp2\n\t" |
|
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|
7710 "NEG EDX:EAX # if $imm < 0" %} |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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|
7711 ins_encode %{ |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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|
7712 int con = (int)$imm$$constant; |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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|
7713 assert(con != 0 && con != -1 && con != min_jint, "wrong divisor"); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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|
7714 int pcon = (con > 0) ? con : -con; |
| 1920 | 7715 Label Lfast, Lpos, Ldone; |
|
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|
7716 |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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|
7717 __ movl($tmp$$Register, pcon); |
| 1920 | 7718 __ xorl($tmp2$$Register,$tmp2$$Register); |
|
1914
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kvn
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|
7719 __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register)); |
| 1920 | 7720 __ jccb(Assembler::above, Lfast); // result fits into 32 bit |
|
1914
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kvn
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|
7721 |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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|
7722 __ movl($tmp2$$Register, $dst$$Register); // save |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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|
7723 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register)); |
| 1920 | 7724 __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags |
| 7725 __ jccb(Assembler::lessEqual, Lpos); // result is positive | |
| 7726 | |
| 7727 // Negative dividend. | |
| 7728 // convert value to positive to use unsigned division | |
| 7729 __ lneg($dst$$Register, $tmp2$$Register); | |
| 7730 __ divl($tmp$$Register); | |
|
1914
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|
7731 __ xchgl($dst$$Register, $tmp2$$Register); |
| 1920 | 7732 __ divl($tmp$$Register); |
| 7733 // revert result back to negative | |
| 7734 __ lneg($tmp2$$Register, $dst$$Register); | |
|
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|
7735 __ jmpb(Ldone); |
|
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6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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|
7736 |
| 1920 | 7737 __ bind(Lpos); |
| 7738 __ divl($tmp$$Register); // Use unsigned division | |
| 7739 __ xchgl($dst$$Register, $tmp2$$Register); | |
| 7740 // Fallthrow for final divide, tmp2 has 32 bit hi result | |
| 7741 | |
|
1914
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kvn
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|
7742 __ bind(Lfast); |
| 1920 | 7743 // fast path: src is positive |
| 7744 __ divl($tmp$$Register); // Use unsigned division | |
|
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kvn
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|
7745 |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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diff
changeset
|
7746 __ bind(Ldone); |
| 1920 | 7747 __ movl(HIGH_FROM_LOW($dst$$Register),$tmp2$$Register); |
|
1914
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kvn
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|
7748 if (con < 0) { |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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diff
changeset
|
7749 __ lneg(HIGH_FROM_LOW($dst$$Register), $dst$$Register); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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1748
diff
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|
7750 } |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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1748
diff
changeset
|
7751 %} |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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1748
diff
changeset
|
7752 ins_pipe( pipe_slow ); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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1748
diff
changeset
|
7753 %} |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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1748
diff
changeset
|
7754 |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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1748
diff
changeset
|
7755 // Remainder Register Long (remainder fit into 32 bits) |
|
6179
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|
7756 instruct modL_eReg_imm32( eADXRegL dst, immL32 imm, rRegI tmp, rRegI tmp2, eFlagsReg cr ) %{ |
|
1914
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6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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|
7757 match(Set dst (ModL dst imm)); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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1748
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|
7758 effect( TEMP tmp, TEMP tmp2, KILL cr ); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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1748
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|
7759 ins_cost(1000); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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1748
diff
changeset
|
7760 format %{ "MOV $tmp,abs($imm) # lrem EDX:EAX,$imm\n\t" |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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1748
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|
7761 "CMP $tmp,EDX\n\t" |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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1748
diff
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|
7762 "JA,s fast\n\t" |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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1748
diff
changeset
|
7763 "MOV $tmp2,EAX\n\t" |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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1748
diff
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|
7764 "MOV EAX,EDX\n\t" |
| 1920 | 7765 "MOV EDX,0\n\t" |
| 7766 "JLE,s pos\n\t" | |
| 7767 "LNEG EAX : $tmp2\n\t" | |
| 7768 "DIV $tmp # unsigned division\n\t" | |
| 7769 "MOV EAX,$tmp2\n\t" | |
| 7770 "DIV $tmp\n\t" | |
| 7771 "NEG EDX\n\t" | |
| 7772 "JMP,s done\n" | |
| 7773 "pos:\n\t" | |
| 7774 "DIV $tmp\n\t" | |
|
1914
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6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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1748
diff
changeset
|
7775 "MOV EAX,$tmp2\n" |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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1748
diff
changeset
|
7776 "fast:\n\t" |
| 1920 | 7777 "DIV $tmp\n" |
| 7778 "done:\n\t" | |
|
1914
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6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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1748
diff
changeset
|
7779 "MOV EAX,EDX\n\t" |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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1748
diff
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|
7780 "SAR EDX,31\n\t" %} |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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diff
changeset
|
7781 ins_encode %{ |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7782 int con = (int)$imm$$constant; |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7783 assert(con != 0 && con != -1 && con != min_jint, "wrong divisor"); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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1748
diff
changeset
|
7784 int pcon = (con > 0) ? con : -con; |
| 1920 | 7785 Label Lfast, Lpos, Ldone; |
|
1914
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kvn
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1748
diff
changeset
|
7786 |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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1748
diff
changeset
|
7787 __ movl($tmp$$Register, pcon); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7788 __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register)); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
7789 __ jccb(Assembler::above, Lfast); // src is positive and result fits into 32 bit |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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1748
diff
changeset
|
7790 |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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diff
changeset
|
7791 __ movl($tmp2$$Register, $dst$$Register); // save |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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changeset
|
7792 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register)); |
| 1920 | 7793 __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags |
| 7794 __ jccb(Assembler::lessEqual, Lpos); // result is positive | |
| 7795 | |
| 7796 // Negative dividend. | |
| 7797 // convert value to positive to use unsigned division | |
| 7798 __ lneg($dst$$Register, $tmp2$$Register); | |
| 7799 __ divl($tmp$$Register); | |
| 7800 __ movl($dst$$Register, $tmp2$$Register); | |
| 7801 __ divl($tmp$$Register); | |
| 7802 // revert remainder back to negative | |
| 7803 __ negl(HIGH_FROM_LOW($dst$$Register)); | |
| 7804 __ jmpb(Ldone); | |
| 7805 | |
| 7806 __ bind(Lpos); | |
| 7807 __ divl($tmp$$Register); | |
|
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|
7808 __ movl($dst$$Register, $tmp2$$Register); |
|
ae065c367d93
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kvn
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changeset
|
7809 |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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diff
changeset
|
7810 __ bind(Lfast); |
| 1920 | 7811 // fast path: src is positive |
| 7812 __ divl($tmp$$Register); | |
| 7813 | |
| 7814 __ bind(Ldone); | |
|
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|
7815 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register)); |
|
ae065c367d93
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changeset
|
7816 __ sarl(HIGH_FROM_LOW($dst$$Register), 31); // result sign |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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changeset
|
7817 |
|
ae065c367d93
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kvn
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diff
changeset
|
7818 %} |
|
ae065c367d93
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diff
changeset
|
7819 ins_pipe( pipe_slow ); |
|
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|
7820 %} |
|
ae065c367d93
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|
7821 |
| 0 | 7822 // Integer Shift Instructions |
| 7823 // Shift Left by one | |
|
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|
7824 instruct shlI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{ |
| 0 | 7825 match(Set dst (LShiftI dst shift)); |
| 7826 effect(KILL cr); | |
| 7827 | |
| 7828 size(2); | |
| 7829 format %{ "SHL $dst,$shift" %} | |
| 7830 opcode(0xD1, 0x4); /* D1 /4 */ | |
| 7831 ins_encode( OpcP, RegOpc( dst ) ); | |
| 7832 ins_pipe( ialu_reg ); | |
| 7833 %} | |
| 7834 | |
| 7835 // Shift Left by 8-bit immediate | |
|
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|
7836 instruct salI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{ |
| 0 | 7837 match(Set dst (LShiftI dst shift)); |
| 7838 effect(KILL cr); | |
| 7839 | |
| 7840 size(3); | |
| 7841 format %{ "SHL $dst,$shift" %} | |
| 7842 opcode(0xC1, 0x4); /* C1 /4 ib */ | |
| 7843 ins_encode( RegOpcImm( dst, shift) ); | |
| 7844 ins_pipe( ialu_reg ); | |
| 7845 %} | |
| 7846 | |
| 7847 // Shift Left by variable | |
|
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|
7848 instruct salI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{ |
| 0 | 7849 match(Set dst (LShiftI dst shift)); |
| 7850 effect(KILL cr); | |
| 7851 | |
| 7852 size(2); | |
| 7853 format %{ "SHL $dst,$shift" %} | |
| 7854 opcode(0xD3, 0x4); /* D3 /4 */ | |
| 7855 ins_encode( OpcP, RegOpc( dst ) ); | |
| 7856 ins_pipe( ialu_reg_reg ); | |
| 7857 %} | |
| 7858 | |
| 7859 // Arithmetic shift right by one | |
|
6179
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changeset
|
7860 instruct sarI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{ |
| 0 | 7861 match(Set dst (RShiftI dst shift)); |
| 7862 effect(KILL cr); | |
| 7863 | |
| 7864 size(2); | |
| 7865 format %{ "SAR $dst,$shift" %} | |
| 7866 opcode(0xD1, 0x7); /* D1 /7 */ | |
| 7867 ins_encode( OpcP, RegOpc( dst ) ); | |
| 7868 ins_pipe( ialu_reg ); | |
| 7869 %} | |
| 7870 | |
| 7871 // Arithmetic shift right by one | |
| 7872 instruct sarI_mem_1(memory dst, immI1 shift, eFlagsReg cr) %{ | |
| 7873 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift))); | |
| 7874 effect(KILL cr); | |
| 7875 format %{ "SAR $dst,$shift" %} | |
| 7876 opcode(0xD1, 0x7); /* D1 /7 */ | |
| 7877 ins_encode( OpcP, RMopc_Mem(secondary,dst) ); | |
| 7878 ins_pipe( ialu_mem_imm ); | |
| 7879 %} | |
| 7880 | |
| 7881 // Arithmetic Shift Right by 8-bit immediate | |
|
6179
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changeset
|
7882 instruct sarI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{ |
| 0 | 7883 match(Set dst (RShiftI dst shift)); |
| 7884 effect(KILL cr); | |
| 7885 | |
| 7886 size(3); | |
| 7887 format %{ "SAR $dst,$shift" %} | |
| 7888 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 7889 ins_encode( RegOpcImm( dst, shift ) ); | |
| 7890 ins_pipe( ialu_mem_imm ); | |
| 7891 %} | |
| 7892 | |
| 7893 // Arithmetic Shift Right by 8-bit immediate | |
| 7894 instruct sarI_mem_imm(memory dst, immI8 shift, eFlagsReg cr) %{ | |
| 7895 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift))); | |
| 7896 effect(KILL cr); | |
| 7897 | |
| 7898 format %{ "SAR $dst,$shift" %} | |
| 7899 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 7900 ins_encode( OpcP, RMopc_Mem(secondary, dst ), Con8or32( shift ) ); | |
| 7901 ins_pipe( ialu_mem_imm ); | |
| 7902 %} | |
| 7903 | |
| 7904 // Arithmetic Shift Right by variable | |
|
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|
7905 instruct sarI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{ |
| 0 | 7906 match(Set dst (RShiftI dst shift)); |
| 7907 effect(KILL cr); | |
| 7908 | |
| 7909 size(2); | |
| 7910 format %{ "SAR $dst,$shift" %} | |
| 7911 opcode(0xD3, 0x7); /* D3 /7 */ | |
| 7912 ins_encode( OpcP, RegOpc( dst ) ); | |
| 7913 ins_pipe( ialu_reg_reg ); | |
| 7914 %} | |
| 7915 | |
| 7916 // Logical shift right by one | |
|
6179
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|
7917 instruct shrI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{ |
| 0 | 7918 match(Set dst (URShiftI dst shift)); |
| 7919 effect(KILL cr); | |
| 7920 | |
| 7921 size(2); | |
| 7922 format %{ "SHR $dst,$shift" %} | |
| 7923 opcode(0xD1, 0x5); /* D1 /5 */ | |
| 7924 ins_encode( OpcP, RegOpc( dst ) ); | |
| 7925 ins_pipe( ialu_reg ); | |
| 7926 %} | |
| 7927 | |
| 7928 // Logical Shift Right by 8-bit immediate | |
|
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diff
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|
7929 instruct shrI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{ |
| 0 | 7930 match(Set dst (URShiftI dst shift)); |
| 7931 effect(KILL cr); | |
| 7932 | |
| 7933 size(3); | |
| 7934 format %{ "SHR $dst,$shift" %} | |
| 7935 opcode(0xC1, 0x5); /* C1 /5 ib */ | |
| 7936 ins_encode( RegOpcImm( dst, shift) ); | |
| 7937 ins_pipe( ialu_reg ); | |
| 7938 %} | |
| 7939 | |
|
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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415
diff
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|
7940 |
| 0 | 7941 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24. |
| 7942 // This idiom is used by the compiler for the i2b bytecode. | |
|
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|
7943 instruct i2b(rRegI dst, xRegI src, immI_24 twentyfour) %{ |
| 0 | 7944 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour)); |
| 7945 | |
| 7946 size(3); | |
| 7947 format %{ "MOVSX $dst,$src :8" %} | |
| 785 | 7948 ins_encode %{ |
| 7949 __ movsbl($dst$$Register, $src$$Register); | |
| 7950 %} | |
| 7951 ins_pipe(ialu_reg_reg); | |
| 0 | 7952 %} |
| 7953 | |
| 7954 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16. | |
| 7955 // This idiom is used by the compiler the i2s bytecode. | |
|
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|
7956 instruct i2s(rRegI dst, xRegI src, immI_16 sixteen) %{ |
| 0 | 7957 match(Set dst (RShiftI (LShiftI src sixteen) sixteen)); |
| 7958 | |
| 7959 size(3); | |
| 7960 format %{ "MOVSX $dst,$src :16" %} | |
| 785 | 7961 ins_encode %{ |
| 7962 __ movswl($dst$$Register, $src$$Register); | |
| 7963 %} | |
| 7964 ins_pipe(ialu_reg_reg); | |
| 0 | 7965 %} |
| 7966 | |
| 7967 | |
| 7968 // Logical Shift Right by variable | |
|
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|
7969 instruct shrI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{ |
| 0 | 7970 match(Set dst (URShiftI dst shift)); |
| 7971 effect(KILL cr); | |
| 7972 | |
| 7973 size(2); | |
| 7974 format %{ "SHR $dst,$shift" %} | |
| 7975 opcode(0xD3, 0x5); /* D3 /5 */ | |
| 7976 ins_encode( OpcP, RegOpc( dst ) ); | |
| 7977 ins_pipe( ialu_reg_reg ); | |
| 7978 %} | |
| 7979 | |
| 7980 | |
| 7981 //----------Logical Instructions----------------------------------------------- | |
| 7982 //----------Integer Logical Instructions--------------------------------------- | |
| 7983 // And Instructions | |
| 7984 // And Register with Register | |
|
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diff
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|
7985 instruct andI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 7986 match(Set dst (AndI dst src)); |
| 7987 effect(KILL cr); | |
| 7988 | |
| 7989 size(2); | |
| 7990 format %{ "AND $dst,$src" %} | |
| 7991 opcode(0x23); | |
| 7992 ins_encode( OpcP, RegReg( dst, src) ); | |
| 7993 ins_pipe( ialu_reg_reg ); | |
| 7994 %} | |
| 7995 | |
| 7996 // And Register with Immediate | |
|
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|
7997 instruct andI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{ |
| 0 | 7998 match(Set dst (AndI dst src)); |
| 7999 effect(KILL cr); | |
| 8000 | |
| 8001 format %{ "AND $dst,$src" %} | |
| 8002 opcode(0x81,0x04); /* Opcode 81 /4 */ | |
| 8003 // ins_encode( RegImm( dst, src) ); | |
| 8004 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); | |
| 8005 ins_pipe( ialu_reg ); | |
| 8006 %} | |
| 8007 | |
| 8008 // And Register with Memory | |
|
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|
8009 instruct andI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{ |
| 0 | 8010 match(Set dst (AndI dst (LoadI src))); |
| 8011 effect(KILL cr); | |
| 8012 | |
| 8013 ins_cost(125); | |
| 8014 format %{ "AND $dst,$src" %} | |
| 8015 opcode(0x23); | |
| 8016 ins_encode( OpcP, RegMem( dst, src) ); | |
| 8017 ins_pipe( ialu_reg_mem ); | |
| 8018 %} | |
| 8019 | |
| 8020 // And Memory with Register | |
|
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|
8021 instruct andI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 8022 match(Set dst (StoreI dst (AndI (LoadI dst) src))); |
| 8023 effect(KILL cr); | |
| 8024 | |
| 8025 ins_cost(150); | |
| 8026 format %{ "AND $dst,$src" %} | |
| 8027 opcode(0x21); /* Opcode 21 /r */ | |
| 8028 ins_encode( OpcP, RegMem( src, dst ) ); | |
| 8029 ins_pipe( ialu_mem_reg ); | |
| 8030 %} | |
| 8031 | |
| 8032 // And Memory with Immediate | |
| 8033 instruct andI_mem_imm(memory dst, immI src, eFlagsReg cr) %{ | |
| 8034 match(Set dst (StoreI dst (AndI (LoadI dst) src))); | |
| 8035 effect(KILL cr); | |
| 8036 | |
| 8037 ins_cost(125); | |
| 8038 format %{ "AND $dst,$src" %} | |
| 8039 opcode(0x81, 0x4); /* Opcode 81 /4 id */ | |
| 8040 // ins_encode( MemImm( dst, src) ); | |
| 8041 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) ); | |
| 8042 ins_pipe( ialu_mem_imm ); | |
| 8043 %} | |
| 8044 | |
|
17729
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|
8045 // BMI1 instructions |
|
8a8ff6b577ed
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|
8046 instruct andnI_rReg_rReg_rReg(rRegI dst, rRegI src1, rRegI src2, immI_M1 minus_1, eFlagsReg cr) %{ |
|
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|
8047 match(Set dst (AndI (XorI src1 minus_1) src2)); |
|
8a8ff6b577ed
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diff
changeset
|
8048 predicate(UseBMI1Instructions); |
|
8a8ff6b577ed
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diff
changeset
|
8049 effect(KILL cr); |
|
8a8ff6b577ed
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diff
changeset
|
8050 |
|
8a8ff6b577ed
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|
8051 format %{ "ANDNL $dst, $src1, $src2" %} |
|
8a8ff6b577ed
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diff
changeset
|
8052 |
|
8a8ff6b577ed
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changeset
|
8053 ins_encode %{ |
|
8a8ff6b577ed
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changeset
|
8054 __ andnl($dst$$Register, $src1$$Register, $src2$$Register); |
|
8a8ff6b577ed
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diff
changeset
|
8055 %} |
|
8a8ff6b577ed
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changeset
|
8056 ins_pipe(ialu_reg); |
|
8a8ff6b577ed
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|
8057 %} |
|
8a8ff6b577ed
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diff
changeset
|
8058 |
|
8a8ff6b577ed
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changeset
|
8059 instruct andnI_rReg_rReg_mem(rRegI dst, rRegI src1, memory src2, immI_M1 minus_1, eFlagsReg cr) %{ |
|
8a8ff6b577ed
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changeset
|
8060 match(Set dst (AndI (XorI src1 minus_1) (LoadI src2) )); |
|
8a8ff6b577ed
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diff
changeset
|
8061 predicate(UseBMI1Instructions); |
|
8a8ff6b577ed
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diff
changeset
|
8062 effect(KILL cr); |
|
8a8ff6b577ed
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diff
changeset
|
8063 |
|
8a8ff6b577ed
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changeset
|
8064 ins_cost(125); |
|
8a8ff6b577ed
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changeset
|
8065 format %{ "ANDNL $dst, $src1, $src2" %} |
|
8a8ff6b577ed
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changeset
|
8066 |
|
8a8ff6b577ed
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changeset
|
8067 ins_encode %{ |
|
8a8ff6b577ed
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changeset
|
8068 __ andnl($dst$$Register, $src1$$Register, $src2$$Address); |
|
8a8ff6b577ed
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diff
changeset
|
8069 %} |
|
8a8ff6b577ed
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diff
changeset
|
8070 ins_pipe(ialu_reg_mem); |
|
8a8ff6b577ed
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diff
changeset
|
8071 %} |
|
8a8ff6b577ed
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diff
changeset
|
8072 |
|
8a8ff6b577ed
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changeset
|
8073 instruct blsiI_rReg_rReg(rRegI dst, rRegI src, immI0 imm_zero, eFlagsReg cr) %{ |
|
8a8ff6b577ed
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|
8074 match(Set dst (AndI (SubI imm_zero src) src)); |
|
8a8ff6b577ed
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diff
changeset
|
8075 predicate(UseBMI1Instructions); |
|
8a8ff6b577ed
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diff
changeset
|
8076 effect(KILL cr); |
|
8a8ff6b577ed
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diff
changeset
|
8077 |
|
8a8ff6b577ed
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changeset
|
8078 format %{ "BLSIL $dst, $src" %} |
|
8a8ff6b577ed
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diff
changeset
|
8079 |
|
8a8ff6b577ed
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changeset
|
8080 ins_encode %{ |
|
8a8ff6b577ed
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changeset
|
8081 __ blsil($dst$$Register, $src$$Register); |
|
8a8ff6b577ed
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diff
changeset
|
8082 %} |
|
8a8ff6b577ed
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changeset
|
8083 ins_pipe(ialu_reg); |
|
8a8ff6b577ed
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changeset
|
8084 %} |
|
8a8ff6b577ed
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changeset
|
8085 |
|
8a8ff6b577ed
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changeset
|
8086 instruct blsiI_rReg_mem(rRegI dst, memory src, immI0 imm_zero, eFlagsReg cr) %{ |
|
8a8ff6b577ed
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|
8087 match(Set dst (AndI (SubI imm_zero (LoadI src) ) (LoadI src) )); |
|
8a8ff6b577ed
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diff
changeset
|
8088 predicate(UseBMI1Instructions); |
|
8a8ff6b577ed
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diff
changeset
|
8089 effect(KILL cr); |
|
8a8ff6b577ed
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changeset
|
8090 |
|
8a8ff6b577ed
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changeset
|
8091 ins_cost(125); |
|
8a8ff6b577ed
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changeset
|
8092 format %{ "BLSIL $dst, $src" %} |
|
8a8ff6b577ed
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changeset
|
8093 |
|
8a8ff6b577ed
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changeset
|
8094 ins_encode %{ |
|
8a8ff6b577ed
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changeset
|
8095 __ blsil($dst$$Register, $src$$Address); |
|
8a8ff6b577ed
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changeset
|
8096 %} |
|
8a8ff6b577ed
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changeset
|
8097 ins_pipe(ialu_reg_mem); |
|
8a8ff6b577ed
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changeset
|
8098 %} |
|
8a8ff6b577ed
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changeset
|
8099 |
|
8a8ff6b577ed
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changeset
|
8100 instruct blsmskI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, eFlagsReg cr) |
|
8a8ff6b577ed
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|
8101 %{ |
|
8a8ff6b577ed
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|
8102 match(Set dst (XorI (AddI src minus_1) src)); |
|
8a8ff6b577ed
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changeset
|
8103 predicate(UseBMI1Instructions); |
|
8a8ff6b577ed
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changeset
|
8104 effect(KILL cr); |
|
8a8ff6b577ed
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changeset
|
8105 |
|
8a8ff6b577ed
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changeset
|
8106 format %{ "BLSMSKL $dst, $src" %} |
|
8a8ff6b577ed
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iveresov
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diff
changeset
|
8107 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
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diff
changeset
|
8108 ins_encode %{ |
|
8a8ff6b577ed
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changeset
|
8109 __ blsmskl($dst$$Register, $src$$Register); |
|
8a8ff6b577ed
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diff
changeset
|
8110 %} |
|
8a8ff6b577ed
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iveresov
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changeset
|
8111 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
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diff
changeset
|
8112 ins_pipe(ialu_reg); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
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diff
changeset
|
8113 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
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changeset
|
8114 |
|
8a8ff6b577ed
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changeset
|
8115 instruct blsmskI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, eFlagsReg cr) |
|
8a8ff6b577ed
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changeset
|
8116 %{ |
|
8a8ff6b577ed
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changeset
|
8117 match(Set dst (XorI (AddI (LoadI src) minus_1) (LoadI src) )); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8118 predicate(UseBMI1Instructions); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
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diff
changeset
|
8119 effect(KILL cr); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
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diff
changeset
|
8120 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
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diff
changeset
|
8121 ins_cost(125); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
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diff
changeset
|
8122 format %{ "BLSMSKL $dst, $src" %} |
|
8a8ff6b577ed
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parents:
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diff
changeset
|
8123 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
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changeset
|
8124 ins_encode %{ |
|
8a8ff6b577ed
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iveresov
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changeset
|
8125 __ blsmskl($dst$$Register, $src$$Address); |
|
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|
8126 %} |
|
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|
8127 |
|
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|
8128 ins_pipe(ialu_reg_mem); |
|
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|
8129 %} |
|
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|
8130 |
|
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|
8131 instruct blsrI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, eFlagsReg cr) |
|
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|
8132 %{ |
|
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|
8133 match(Set dst (AndI (AddI src minus_1) src) ); |
|
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|
8134 predicate(UseBMI1Instructions); |
|
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|
8135 effect(KILL cr); |
|
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|
8136 |
|
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|
8137 format %{ "BLSRL $dst, $src" %} |
|
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|
8138 |
|
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|
8139 ins_encode %{ |
|
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|
8140 __ blsrl($dst$$Register, $src$$Register); |
|
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|
8141 %} |
|
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|
8142 |
|
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|
8143 ins_pipe(ialu_reg); |
|
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|
8144 %} |
|
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|
8145 |
|
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|
8146 instruct blsrI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, eFlagsReg cr) |
|
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|
8147 %{ |
|
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|
8148 match(Set dst (AndI (AddI (LoadI src) minus_1) (LoadI src) )); |
|
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|
8149 predicate(UseBMI1Instructions); |
|
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|
8150 effect(KILL cr); |
|
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|
8151 |
|
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|
8152 ins_cost(125); |
|
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|
8153 format %{ "BLSRL $dst, $src" %} |
|
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|
8154 |
|
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|
8155 ins_encode %{ |
|
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|
8156 __ blsrl($dst$$Register, $src$$Address); |
|
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|
8157 %} |
|
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|
8158 |
|
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|
8159 ins_pipe(ialu_reg_mem); |
|
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|
8160 %} |
|
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|
8161 |
| 0 | 8162 // Or Instructions |
| 8163 // Or Register with Register | |
|
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|
8164 instruct orI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 8165 match(Set dst (OrI dst src)); |
| 8166 effect(KILL cr); | |
| 8167 | |
| 8168 size(2); | |
| 8169 format %{ "OR $dst,$src" %} | |
| 8170 opcode(0x0B); | |
| 8171 ins_encode( OpcP, RegReg( dst, src) ); | |
| 8172 ins_pipe( ialu_reg_reg ); | |
| 8173 %} | |
| 8174 | |
|
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|
8175 instruct orI_eReg_castP2X(rRegI dst, eRegP src, eFlagsReg cr) %{ |
|
420
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|
8176 match(Set dst (OrI dst (CastP2X src))); |
|
a1980da045cc
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diff
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|
8177 effect(KILL cr); |
|
a1980da045cc
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415
diff
changeset
|
8178 |
|
a1980da045cc
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415
diff
changeset
|
8179 size(2); |
|
a1980da045cc
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415
diff
changeset
|
8180 format %{ "OR $dst,$src" %} |
|
a1980da045cc
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415
diff
changeset
|
8181 opcode(0x0B); |
|
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415
diff
changeset
|
8182 ins_encode( OpcP, RegReg( dst, src) ); |
|
a1980da045cc
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diff
changeset
|
8183 ins_pipe( ialu_reg_reg ); |
|
a1980da045cc
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415
diff
changeset
|
8184 %} |
|
a1980da045cc
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415
diff
changeset
|
8185 |
|
a1980da045cc
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diff
changeset
|
8186 |
| 0 | 8187 // Or Register with Immediate |
|
6179
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|
8188 instruct orI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{ |
| 0 | 8189 match(Set dst (OrI dst src)); |
| 8190 effect(KILL cr); | |
| 8191 | |
| 8192 format %{ "OR $dst,$src" %} | |
| 8193 opcode(0x81,0x01); /* Opcode 81 /1 id */ | |
| 8194 // ins_encode( RegImm( dst, src) ); | |
| 8195 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); | |
| 8196 ins_pipe( ialu_reg ); | |
| 8197 %} | |
| 8198 | |
| 8199 // Or Register with Memory | |
|
6179
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|
8200 instruct orI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{ |
| 0 | 8201 match(Set dst (OrI dst (LoadI src))); |
| 8202 effect(KILL cr); | |
| 8203 | |
| 8204 ins_cost(125); | |
| 8205 format %{ "OR $dst,$src" %} | |
| 8206 opcode(0x0B); | |
| 8207 ins_encode( OpcP, RegMem( dst, src) ); | |
| 8208 ins_pipe( ialu_reg_mem ); | |
| 8209 %} | |
| 8210 | |
| 8211 // Or Memory with Register | |
|
6179
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|
8212 instruct orI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 8213 match(Set dst (StoreI dst (OrI (LoadI dst) src))); |
| 8214 effect(KILL cr); | |
| 8215 | |
| 8216 ins_cost(150); | |
| 8217 format %{ "OR $dst,$src" %} | |
| 8218 opcode(0x09); /* Opcode 09 /r */ | |
| 8219 ins_encode( OpcP, RegMem( src, dst ) ); | |
| 8220 ins_pipe( ialu_mem_reg ); | |
| 8221 %} | |
| 8222 | |
| 8223 // Or Memory with Immediate | |
| 8224 instruct orI_mem_imm(memory dst, immI src, eFlagsReg cr) %{ | |
| 8225 match(Set dst (StoreI dst (OrI (LoadI dst) src))); | |
| 8226 effect(KILL cr); | |
| 8227 | |
| 8228 ins_cost(125); | |
| 8229 format %{ "OR $dst,$src" %} | |
| 8230 opcode(0x81,0x1); /* Opcode 81 /1 id */ | |
| 8231 // ins_encode( MemImm( dst, src) ); | |
| 8232 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) ); | |
| 8233 ins_pipe( ialu_mem_imm ); | |
| 8234 %} | |
| 8235 | |
| 8236 // ROL/ROR | |
| 8237 // ROL expand | |
|
6179
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|
8238 instruct rolI_eReg_imm1(rRegI dst, immI1 shift, eFlagsReg cr) %{ |
| 0 | 8239 effect(USE_DEF dst, USE shift, KILL cr); |
| 8240 | |
| 8241 format %{ "ROL $dst, $shift" %} | |
| 8242 opcode(0xD1, 0x0); /* Opcode D1 /0 */ | |
| 8243 ins_encode( OpcP, RegOpc( dst )); | |
| 8244 ins_pipe( ialu_reg ); | |
| 8245 %} | |
| 8246 | |
|
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|
8247 instruct rolI_eReg_imm8(rRegI dst, immI8 shift, eFlagsReg cr) %{ |
| 0 | 8248 effect(USE_DEF dst, USE shift, KILL cr); |
| 8249 | |
| 8250 format %{ "ROL $dst, $shift" %} | |
| 8251 opcode(0xC1, 0x0); /*Opcode /C1 /0 */ | |
| 8252 ins_encode( RegOpcImm(dst, shift) ); | |
| 8253 ins_pipe(ialu_reg); | |
| 8254 %} | |
| 8255 | |
| 8256 instruct rolI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr) %{ | |
| 8257 effect(USE_DEF dst, USE shift, KILL cr); | |
| 8258 | |
| 8259 format %{ "ROL $dst, $shift" %} | |
| 8260 opcode(0xD3, 0x0); /* Opcode D3 /0 */ | |
| 8261 ins_encode(OpcP, RegOpc(dst)); | |
| 8262 ins_pipe( ialu_reg_reg ); | |
| 8263 %} | |
| 8264 // end of ROL expand | |
| 8265 | |
| 8266 // ROL 32bit by one once | |
|
6179
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|
8267 instruct rolI_eReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, eFlagsReg cr) %{ |
| 0 | 8268 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift))); |
| 8269 | |
| 8270 expand %{ | |
| 8271 rolI_eReg_imm1(dst, lshift, cr); | |
| 8272 %} | |
| 8273 %} | |
| 8274 | |
| 8275 // ROL 32bit var by imm8 once | |
|
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|
8276 instruct rolI_eReg_i8(rRegI dst, immI8 lshift, immI8 rshift, eFlagsReg cr) %{ |
| 0 | 8277 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); |
| 8278 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift))); | |
| 8279 | |
| 8280 expand %{ | |
| 8281 rolI_eReg_imm8(dst, lshift, cr); | |
| 8282 %} | |
| 8283 %} | |
| 8284 | |
| 8285 // ROL 32bit var by var once | |
| 8286 instruct rolI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{ | |
| 8287 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift)))); | |
| 8288 | |
| 8289 expand %{ | |
| 8290 rolI_eReg_CL(dst, shift, cr); | |
| 8291 %} | |
| 8292 %} | |
| 8293 | |
| 8294 // ROL 32bit var by var once | |
| 8295 instruct rolI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{ | |
| 8296 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift)))); | |
| 8297 | |
| 8298 expand %{ | |
| 8299 rolI_eReg_CL(dst, shift, cr); | |
| 8300 %} | |
| 8301 %} | |
| 8302 | |
| 8303 // ROR expand | |
|
6179
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changeset
|
8304 instruct rorI_eReg_imm1(rRegI dst, immI1 shift, eFlagsReg cr) %{ |
| 0 | 8305 effect(USE_DEF dst, USE shift, KILL cr); |
| 8306 | |
| 8307 format %{ "ROR $dst, $shift" %} | |
| 8308 opcode(0xD1,0x1); /* Opcode D1 /1 */ | |
| 8309 ins_encode( OpcP, RegOpc( dst ) ); | |
| 8310 ins_pipe( ialu_reg ); | |
| 8311 %} | |
| 8312 | |
|
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changeset
|
8313 instruct rorI_eReg_imm8(rRegI dst, immI8 shift, eFlagsReg cr) %{ |
| 0 | 8314 effect (USE_DEF dst, USE shift, KILL cr); |
| 8315 | |
| 8316 format %{ "ROR $dst, $shift" %} | |
| 8317 opcode(0xC1, 0x1); /* Opcode /C1 /1 ib */ | |
| 8318 ins_encode( RegOpcImm(dst, shift) ); | |
| 8319 ins_pipe( ialu_reg ); | |
| 8320 %} | |
| 8321 | |
| 8322 instruct rorI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr)%{ | |
| 8323 effect(USE_DEF dst, USE shift, KILL cr); | |
| 8324 | |
| 8325 format %{ "ROR $dst, $shift" %} | |
| 8326 opcode(0xD3, 0x1); /* Opcode D3 /1 */ | |
| 8327 ins_encode(OpcP, RegOpc(dst)); | |
| 8328 ins_pipe( ialu_reg_reg ); | |
| 8329 %} | |
| 8330 // end of ROR expand | |
| 8331 | |
| 8332 // ROR right once | |
|
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changeset
|
8333 instruct rorI_eReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, eFlagsReg cr) %{ |
| 0 | 8334 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift))); |
| 8335 | |
| 8336 expand %{ | |
| 8337 rorI_eReg_imm1(dst, rshift, cr); | |
| 8338 %} | |
| 8339 %} | |
| 8340 | |
| 8341 // ROR 32bit by immI8 once | |
|
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changeset
|
8342 instruct rorI_eReg_i8(rRegI dst, immI8 rshift, immI8 lshift, eFlagsReg cr) %{ |
| 0 | 8343 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); |
| 8344 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift))); | |
| 8345 | |
| 8346 expand %{ | |
| 8347 rorI_eReg_imm8(dst, rshift, cr); | |
| 8348 %} | |
| 8349 %} | |
| 8350 | |
| 8351 // ROR 32bit var by var once | |
| 8352 instruct rorI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{ | |
| 8353 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift)))); | |
| 8354 | |
| 8355 expand %{ | |
| 8356 rorI_eReg_CL(dst, shift, cr); | |
| 8357 %} | |
| 8358 %} | |
| 8359 | |
| 8360 // ROR 32bit var by var once | |
| 8361 instruct rorI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{ | |
| 8362 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift)))); | |
| 8363 | |
| 8364 expand %{ | |
| 8365 rorI_eReg_CL(dst, shift, cr); | |
| 8366 %} | |
| 8367 %} | |
| 8368 | |
| 8369 // Xor Instructions | |
| 8370 // Xor Register with Register | |
|
6179
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|
8371 instruct xorI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 8372 match(Set dst (XorI dst src)); |
| 8373 effect(KILL cr); | |
| 8374 | |
| 8375 size(2); | |
| 8376 format %{ "XOR $dst,$src" %} | |
| 8377 opcode(0x33); | |
| 8378 ins_encode( OpcP, RegReg( dst, src) ); | |
| 8379 ins_pipe( ialu_reg_reg ); | |
| 8380 %} | |
| 8381 | |
| 403 | 8382 // Xor Register with Immediate -1 |
|
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|
8383 instruct xorI_eReg_im1(rRegI dst, immI_M1 imm) %{ |
| 403 | 8384 match(Set dst (XorI dst imm)); |
| 8385 | |
| 8386 size(2); | |
| 8387 format %{ "NOT $dst" %} | |
| 8388 ins_encode %{ | |
| 8389 __ notl($dst$$Register); | |
| 8390 %} | |
| 8391 ins_pipe( ialu_reg ); | |
| 8392 %} | |
| 8393 | |
| 0 | 8394 // Xor Register with Immediate |
|
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changeset
|
8395 instruct xorI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{ |
| 0 | 8396 match(Set dst (XorI dst src)); |
| 8397 effect(KILL cr); | |
| 8398 | |
| 8399 format %{ "XOR $dst,$src" %} | |
| 8400 opcode(0x81,0x06); /* Opcode 81 /6 id */ | |
| 8401 // ins_encode( RegImm( dst, src) ); | |
| 8402 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); | |
| 8403 ins_pipe( ialu_reg ); | |
| 8404 %} | |
| 8405 | |
| 8406 // Xor Register with Memory | |
|
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changeset
|
8407 instruct xorI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{ |
| 0 | 8408 match(Set dst (XorI dst (LoadI src))); |
| 8409 effect(KILL cr); | |
| 8410 | |
| 8411 ins_cost(125); | |
| 8412 format %{ "XOR $dst,$src" %} | |
| 8413 opcode(0x33); | |
| 8414 ins_encode( OpcP, RegMem(dst, src) ); | |
| 8415 ins_pipe( ialu_reg_mem ); | |
| 8416 %} | |
| 8417 | |
| 8418 // Xor Memory with Register | |
|
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8419 instruct xorI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 8420 match(Set dst (StoreI dst (XorI (LoadI dst) src))); |
| 8421 effect(KILL cr); | |
| 8422 | |
| 8423 ins_cost(150); | |
| 8424 format %{ "XOR $dst,$src" %} | |
| 8425 opcode(0x31); /* Opcode 31 /r */ | |
| 8426 ins_encode( OpcP, RegMem( src, dst ) ); | |
| 8427 ins_pipe( ialu_mem_reg ); | |
| 8428 %} | |
| 8429 | |
| 8430 // Xor Memory with Immediate | |
| 8431 instruct xorI_mem_imm(memory dst, immI src, eFlagsReg cr) %{ | |
| 8432 match(Set dst (StoreI dst (XorI (LoadI dst) src))); | |
| 8433 effect(KILL cr); | |
| 8434 | |
| 8435 ins_cost(125); | |
| 8436 format %{ "XOR $dst,$src" %} | |
| 8437 opcode(0x81,0x6); /* Opcode 81 /6 id */ | |
| 8438 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) ); | |
| 8439 ins_pipe( ialu_mem_imm ); | |
| 8440 %} | |
| 8441 | |
| 8442 //----------Convert Int to Boolean--------------------------------------------- | |
| 8443 | |
|
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|
8444 instruct movI_nocopy(rRegI dst, rRegI src) %{ |
| 0 | 8445 effect( DEF dst, USE src ); |
| 8446 format %{ "MOV $dst,$src" %} | |
| 8447 ins_encode( enc_Copy( dst, src) ); | |
| 8448 ins_pipe( ialu_reg_reg ); | |
| 8449 %} | |
| 8450 | |
|
6179
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|
8451 instruct ci2b( rRegI dst, rRegI src, eFlagsReg cr ) %{ |
| 0 | 8452 effect( USE_DEF dst, USE src, KILL cr ); |
| 8453 | |
| 8454 size(4); | |
| 8455 format %{ "NEG $dst\n\t" | |
| 8456 "ADC $dst,$src" %} | |
| 8457 ins_encode( neg_reg(dst), | |
| 8458 OpcRegReg(0x13,dst,src) ); | |
| 8459 ins_pipe( ialu_reg_reg_long ); | |
| 8460 %} | |
| 8461 | |
|
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|
8462 instruct convI2B( rRegI dst, rRegI src, eFlagsReg cr ) %{ |
| 0 | 8463 match(Set dst (Conv2B src)); |
| 8464 | |
| 8465 expand %{ | |
| 8466 movI_nocopy(dst,src); | |
| 8467 ci2b(dst,src,cr); | |
| 8468 %} | |
| 8469 %} | |
| 8470 | |
|
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|
8471 instruct movP_nocopy(rRegI dst, eRegP src) %{ |
| 0 | 8472 effect( DEF dst, USE src ); |
| 8473 format %{ "MOV $dst,$src" %} | |
| 8474 ins_encode( enc_Copy( dst, src) ); | |
| 8475 ins_pipe( ialu_reg_reg ); | |
| 8476 %} | |
| 8477 | |
|
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|
8478 instruct cp2b( rRegI dst, eRegP src, eFlagsReg cr ) %{ |
| 0 | 8479 effect( USE_DEF dst, USE src, KILL cr ); |
| 8480 format %{ "NEG $dst\n\t" | |
| 8481 "ADC $dst,$src" %} | |
| 8482 ins_encode( neg_reg(dst), | |
| 8483 OpcRegReg(0x13,dst,src) ); | |
| 8484 ins_pipe( ialu_reg_reg_long ); | |
| 8485 %} | |
| 8486 | |
|
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|
8487 instruct convP2B( rRegI dst, eRegP src, eFlagsReg cr ) %{ |
| 0 | 8488 match(Set dst (Conv2B src)); |
| 8489 | |
| 8490 expand %{ | |
| 8491 movP_nocopy(dst,src); | |
| 8492 cp2b(dst,src,cr); | |
| 8493 %} | |
| 8494 %} | |
| 8495 | |
| 9154 | 8496 instruct cmpLTMask(eCXRegI dst, ncxRegI p, ncxRegI q, eFlagsReg cr) %{ |
| 0 | 8497 match(Set dst (CmpLTMask p q)); |
| 9154 | 8498 effect(KILL cr); |
| 0 | 8499 ins_cost(400); |
| 8500 | |
| 8501 // SETlt can only use low byte of EAX,EBX, ECX, or EDX as destination | |
| 8502 format %{ "XOR $dst,$dst\n\t" | |
| 8503 "CMP $p,$q\n\t" | |
| 8504 "SETlt $dst\n\t" | |
| 8505 "NEG $dst" %} | |
| 9154 | 8506 ins_encode %{ |
| 8507 Register Rp = $p$$Register; | |
| 8508 Register Rq = $q$$Register; | |
| 8509 Register Rd = $dst$$Register; | |
| 8510 Label done; | |
| 8511 __ xorl(Rd, Rd); | |
| 8512 __ cmpl(Rp, Rq); | |
| 8513 __ setb(Assembler::less, Rd); | |
| 8514 __ negl(Rd); | |
| 8515 %} | |
| 8516 | |
| 8517 ins_pipe(pipe_slow); | |
| 8518 %} | |
| 8519 | |
| 8520 instruct cmpLTMask0(rRegI dst, immI0 zero, eFlagsReg cr) %{ | |
| 0 | 8521 match(Set dst (CmpLTMask dst zero)); |
| 9154 | 8522 effect(DEF dst, KILL cr); |
| 0 | 8523 ins_cost(100); |
| 8524 | |
| 9154 | 8525 format %{ "SAR $dst,31\t# cmpLTMask0" %} |
| 8526 ins_encode %{ | |
| 8527 __ sarl($dst$$Register, 31); | |
| 8528 %} | |
| 8529 ins_pipe(ialu_reg); | |
| 8530 %} | |
| 8531 | |
| 8532 /* better to save a register than avoid a branch */ | |
| 8533 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y, eFlagsReg cr) %{ | |
| 0 | 8534 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))); |
| 9154 | 8535 effect(KILL cr); |
| 0 | 8536 ins_cost(400); |
| 9154 | 8537 format %{ "SUB $p,$q\t# cadd_cmpLTMask\n\t" |
| 8538 "JGE done\n\t" | |
| 8539 "ADD $p,$y\n" | |
| 8540 "done: " %} | |
| 8541 ins_encode %{ | |
| 8542 Register Rp = $p$$Register; | |
| 8543 Register Rq = $q$$Register; | |
| 8544 Register Ry = $y$$Register; | |
| 8545 Label done; | |
| 8546 __ subl(Rp, Rq); | |
| 8547 __ jccb(Assembler::greaterEqual, done); | |
| 8548 __ addl(Rp, Ry); | |
| 8549 __ bind(done); | |
| 8550 %} | |
| 8551 | |
| 8552 ins_pipe(pipe_cmplt); | |
| 8553 %} | |
| 8554 | |
| 8555 /* better to save a register than avoid a branch */ | |
| 8556 instruct and_cmpLTMask(rRegI p, rRegI q, rRegI y, eFlagsReg cr) %{ | |
| 8557 match(Set y (AndI (CmpLTMask p q) y)); | |
| 8558 effect(KILL cr); | |
| 8559 | |
| 8560 ins_cost(300); | |
| 8561 | |
| 8562 format %{ "CMPL $p, $q\t# and_cmpLTMask\n\t" | |
| 8563 "JLT done\n\t" | |
| 8564 "XORL $y, $y\n" | |
| 8565 "done: " %} | |
| 8566 ins_encode %{ | |
| 8567 Register Rp = $p$$Register; | |
| 8568 Register Rq = $q$$Register; | |
| 8569 Register Ry = $y$$Register; | |
| 8570 Label done; | |
| 8571 __ cmpl(Rp, Rq); | |
| 8572 __ jccb(Assembler::less, done); | |
| 8573 __ xorl(Ry, Ry); | |
| 8574 __ bind(done); | |
| 8575 %} | |
| 8576 | |
| 8577 ins_pipe(pipe_cmplt); | |
| 0 | 8578 %} |
| 8579 | |
| 8580 /* If I enable this, I encourage spilling in the inner loop of compress. | |
| 9154 | 8581 instruct cadd_cmpLTMask_mem(ncxRegI p, ncxRegI q, memory y, eCXRegI tmp, eFlagsReg cr) %{ |
| 0 | 8582 match(Set p (AddI (AndI (CmpLTMask p q) (LoadI y)) (SubI p q))); |
| 8583 */ | |
|
17726
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8584 //----------Overflow Math Instructions----------------------------------------- |
|
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|
8585 |
|
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|
8586 instruct overflowAddI_eReg(eFlagsReg cr, eAXRegI op1, rRegI op2) |
|
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|
8587 %{ |
|
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|
8588 match(Set cr (OverflowAddI op1 op2)); |
|
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8589 effect(DEF cr, USE_KILL op1, USE op2); |
|
085b304a1cc5
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|
8590 |
|
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|
8591 format %{ "ADD $op1, $op2\t# overflow check int" %} |
|
085b304a1cc5
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|
8592 |
|
085b304a1cc5
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|
8593 ins_encode %{ |
|
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|
8594 __ addl($op1$$Register, $op2$$Register); |
|
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|
8595 %} |
|
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|
8596 ins_pipe(ialu_reg_reg); |
|
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|
8597 %} |
|
085b304a1cc5
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|
8598 |
|
085b304a1cc5
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|
8599 instruct overflowAddI_rReg_imm(eFlagsReg cr, eAXRegI op1, immI op2) |
|
085b304a1cc5
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|
8600 %{ |
|
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|
8601 match(Set cr (OverflowAddI op1 op2)); |
|
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8602 effect(DEF cr, USE_KILL op1, USE op2); |
|
085b304a1cc5
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|
8603 |
|
085b304a1cc5
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|
8604 format %{ "ADD $op1, $op2\t# overflow check int" %} |
|
085b304a1cc5
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|
8605 |
|
085b304a1cc5
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|
8606 ins_encode %{ |
|
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|
8607 __ addl($op1$$Register, $op2$$constant); |
|
085b304a1cc5
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|
8608 %} |
|
085b304a1cc5
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|
8609 ins_pipe(ialu_reg_reg); |
|
085b304a1cc5
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|
8610 %} |
|
085b304a1cc5
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|
8611 |
|
085b304a1cc5
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|
8612 instruct overflowSubI_rReg(eFlagsReg cr, rRegI op1, rRegI op2) |
|
085b304a1cc5
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|
8613 %{ |
|
085b304a1cc5
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|
8614 match(Set cr (OverflowSubI op1 op2)); |
|
085b304a1cc5
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|
8615 |
|
085b304a1cc5
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|
8616 format %{ "CMP $op1, $op2\t# overflow check int" %} |
|
085b304a1cc5
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|
8617 ins_encode %{ |
|
085b304a1cc5
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|
8618 __ cmpl($op1$$Register, $op2$$Register); |
|
085b304a1cc5
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|
8619 %} |
|
085b304a1cc5
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|
8620 ins_pipe(ialu_reg_reg); |
|
085b304a1cc5
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|
8621 %} |
|
085b304a1cc5
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changeset
|
8622 |
|
085b304a1cc5
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|
8623 instruct overflowSubI_rReg_imm(eFlagsReg cr, rRegI op1, immI op2) |
|
085b304a1cc5
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|
8624 %{ |
|
085b304a1cc5
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|
8625 match(Set cr (OverflowSubI op1 op2)); |
|
085b304a1cc5
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|
8626 |
|
085b304a1cc5
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|
8627 format %{ "CMP $op1, $op2\t# overflow check int" %} |
|
085b304a1cc5
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|
8628 ins_encode %{ |
|
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|
8629 __ cmpl($op1$$Register, $op2$$constant); |
|
085b304a1cc5
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|
8630 %} |
|
085b304a1cc5
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|
8631 ins_pipe(ialu_reg_reg); |
|
085b304a1cc5
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|
8632 %} |
|
085b304a1cc5
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changeset
|
8633 |
|
085b304a1cc5
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|
8634 instruct overflowNegI_rReg(eFlagsReg cr, immI0 zero, eAXRegI op2) |
|
085b304a1cc5
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|
8635 %{ |
|
085b304a1cc5
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|
8636 match(Set cr (OverflowSubI zero op2)); |
|
085b304a1cc5
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|
8637 effect(DEF cr, USE_KILL op2); |
|
085b304a1cc5
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|
8638 |
|
085b304a1cc5
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|
8639 format %{ "NEG $op2\t# overflow check int" %} |
|
085b304a1cc5
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|
8640 ins_encode %{ |
|
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|
8641 __ negl($op2$$Register); |
|
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|
8642 %} |
|
085b304a1cc5
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|
8643 ins_pipe(ialu_reg_reg); |
|
085b304a1cc5
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|
8644 %} |
|
085b304a1cc5
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changeset
|
8645 |
|
085b304a1cc5
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|
8646 instruct overflowMulI_rReg(eFlagsReg cr, eAXRegI op1, rRegI op2) |
|
085b304a1cc5
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|
8647 %{ |
|
085b304a1cc5
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|
8648 match(Set cr (OverflowMulI op1 op2)); |
|
085b304a1cc5
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|
8649 effect(DEF cr, USE_KILL op1, USE op2); |
|
085b304a1cc5
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|
8650 |
|
085b304a1cc5
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|
8651 format %{ "IMUL $op1, $op2\t# overflow check int" %} |
|
085b304a1cc5
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|
8652 ins_encode %{ |
|
085b304a1cc5
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|
8653 __ imull($op1$$Register, $op2$$Register); |
|
085b304a1cc5
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|
8654 %} |
|
085b304a1cc5
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|
8655 ins_pipe(ialu_reg_reg_alu0); |
|
085b304a1cc5
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|
8656 %} |
|
085b304a1cc5
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changeset
|
8657 |
|
085b304a1cc5
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|
8658 instruct overflowMulI_rReg_imm(eFlagsReg cr, rRegI op1, immI op2, rRegI tmp) |
|
085b304a1cc5
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|
8659 %{ |
|
085b304a1cc5
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|
8660 match(Set cr (OverflowMulI op1 op2)); |
|
085b304a1cc5
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|
8661 effect(DEF cr, TEMP tmp, USE op1, USE op2); |
|
085b304a1cc5
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|
8662 |
|
085b304a1cc5
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|
8663 format %{ "IMUL $tmp, $op1, $op2\t# overflow check int" %} |
|
085b304a1cc5
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|
8664 ins_encode %{ |
|
085b304a1cc5
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|
8665 __ imull($tmp$$Register, $op1$$Register, $op2$$constant); |
|
085b304a1cc5
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rbackman
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diff
changeset
|
8666 %} |
|
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|
8667 ins_pipe(ialu_reg_reg_alu0); |
|
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|
8668 %} |
| 0 | 8669 |
| 8670 //----------Long Instructions------------------------------------------------ | |
| 8671 // Add Long Register with Register | |
| 8672 instruct addL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ | |
| 8673 match(Set dst (AddL dst src)); | |
| 8674 effect(KILL cr); | |
| 8675 ins_cost(200); | |
| 8676 format %{ "ADD $dst.lo,$src.lo\n\t" | |
| 8677 "ADC $dst.hi,$src.hi" %} | |
| 8678 opcode(0x03, 0x13); | |
| 8679 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) ); | |
| 8680 ins_pipe( ialu_reg_reg_long ); | |
| 8681 %} | |
| 8682 | |
| 8683 // Add Long Register with Immediate | |
| 8684 instruct addL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ | |
| 8685 match(Set dst (AddL dst src)); | |
| 8686 effect(KILL cr); | |
| 8687 format %{ "ADD $dst.lo,$src.lo\n\t" | |
| 8688 "ADC $dst.hi,$src.hi" %} | |
| 8689 opcode(0x81,0x00,0x02); /* Opcode 81 /0, 81 /2 */ | |
| 8690 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); | |
| 8691 ins_pipe( ialu_reg_long ); | |
| 8692 %} | |
| 8693 | |
| 8694 // Add Long Register with Memory | |
| 8695 instruct addL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ | |
| 8696 match(Set dst (AddL dst (LoadL mem))); | |
| 8697 effect(KILL cr); | |
| 8698 ins_cost(125); | |
| 8699 format %{ "ADD $dst.lo,$mem\n\t" | |
| 8700 "ADC $dst.hi,$mem+4" %} | |
| 8701 opcode(0x03, 0x13); | |
| 8702 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); | |
| 8703 ins_pipe( ialu_reg_long_mem ); | |
| 8704 %} | |
| 8705 | |
| 8706 // Subtract Long Register with Register. | |
| 8707 instruct subL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ | |
| 8708 match(Set dst (SubL dst src)); | |
| 8709 effect(KILL cr); | |
| 8710 ins_cost(200); | |
| 8711 format %{ "SUB $dst.lo,$src.lo\n\t" | |
| 8712 "SBB $dst.hi,$src.hi" %} | |
| 8713 opcode(0x2B, 0x1B); | |
| 8714 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) ); | |
| 8715 ins_pipe( ialu_reg_reg_long ); | |
| 8716 %} | |
| 8717 | |
| 8718 // Subtract Long Register with Immediate | |
| 8719 instruct subL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ | |
| 8720 match(Set dst (SubL dst src)); | |
| 8721 effect(KILL cr); | |
| 8722 format %{ "SUB $dst.lo,$src.lo\n\t" | |
| 8723 "SBB $dst.hi,$src.hi" %} | |
| 8724 opcode(0x81,0x05,0x03); /* Opcode 81 /5, 81 /3 */ | |
| 8725 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); | |
| 8726 ins_pipe( ialu_reg_long ); | |
| 8727 %} | |
| 8728 | |
| 8729 // Subtract Long Register with Memory | |
| 8730 instruct subL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ | |
| 8731 match(Set dst (SubL dst (LoadL mem))); | |
| 8732 effect(KILL cr); | |
| 8733 ins_cost(125); | |
| 8734 format %{ "SUB $dst.lo,$mem\n\t" | |
| 8735 "SBB $dst.hi,$mem+4" %} | |
| 8736 opcode(0x2B, 0x1B); | |
| 8737 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); | |
| 8738 ins_pipe( ialu_reg_long_mem ); | |
| 8739 %} | |
| 8740 | |
| 8741 instruct negL_eReg(eRegL dst, immL0 zero, eFlagsReg cr) %{ | |
| 8742 match(Set dst (SubL zero dst)); | |
| 8743 effect(KILL cr); | |
| 8744 ins_cost(300); | |
| 8745 format %{ "NEG $dst.hi\n\tNEG $dst.lo\n\tSBB $dst.hi,0" %} | |
| 8746 ins_encode( neg_long(dst) ); | |
| 8747 ins_pipe( ialu_reg_reg_long ); | |
| 8748 %} | |
| 8749 | |
| 8750 // And Long Register with Register | |
| 8751 instruct andL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ | |
| 8752 match(Set dst (AndL dst src)); | |
| 8753 effect(KILL cr); | |
| 8754 format %{ "AND $dst.lo,$src.lo\n\t" | |
| 8755 "AND $dst.hi,$src.hi" %} | |
| 8756 opcode(0x23,0x23); | |
| 8757 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) ); | |
| 8758 ins_pipe( ialu_reg_reg_long ); | |
| 8759 %} | |
| 8760 | |
| 8761 // And Long Register with Immediate | |
| 8762 instruct andL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ | |
| 8763 match(Set dst (AndL dst src)); | |
| 8764 effect(KILL cr); | |
| 8765 format %{ "AND $dst.lo,$src.lo\n\t" | |
| 8766 "AND $dst.hi,$src.hi" %} | |
| 8767 opcode(0x81,0x04,0x04); /* Opcode 81 /4, 81 /4 */ | |
| 8768 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); | |
| 8769 ins_pipe( ialu_reg_long ); | |
| 8770 %} | |
| 8771 | |
| 8772 // And Long Register with Memory | |
| 8773 instruct andL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ | |
| 8774 match(Set dst (AndL dst (LoadL mem))); | |
| 8775 effect(KILL cr); | |
| 8776 ins_cost(125); | |
| 8777 format %{ "AND $dst.lo,$mem\n\t" | |
| 8778 "AND $dst.hi,$mem+4" %} | |
| 8779 opcode(0x23, 0x23); | |
| 8780 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); | |
| 8781 ins_pipe( ialu_reg_long_mem ); | |
| 8782 %} | |
| 8783 | |
|
17729
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|
8784 // BMI1 instructions |
|
8a8ff6b577ed
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|
8785 instruct andnL_eReg_eReg_eReg(eRegL dst, eRegL src1, eRegL src2, immL_M1 minus_1, eFlagsReg cr) %{ |
|
8a8ff6b577ed
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|
8786 match(Set dst (AndL (XorL src1 minus_1) src2)); |
|
8a8ff6b577ed
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|
8787 predicate(UseBMI1Instructions); |
|
8a8ff6b577ed
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|
8788 effect(KILL cr, TEMP dst); |
|
8a8ff6b577ed
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|
8789 |
|
8a8ff6b577ed
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|
8790 format %{ "ANDNL $dst.lo, $src1.lo, $src2.lo\n\t" |
|
8a8ff6b577ed
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|
8791 "ANDNL $dst.hi, $src1.hi, $src2.hi" |
|
8a8ff6b577ed
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|
8792 %} |
|
8a8ff6b577ed
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changeset
|
8793 |
|
8a8ff6b577ed
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changeset
|
8794 ins_encode %{ |
|
8a8ff6b577ed
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|
8795 Register Rdst = $dst$$Register; |
|
8a8ff6b577ed
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|
8796 Register Rsrc1 = $src1$$Register; |
|
8a8ff6b577ed
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changeset
|
8797 Register Rsrc2 = $src2$$Register; |
|
8a8ff6b577ed
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|
8798 __ andnl(Rdst, Rsrc1, Rsrc2); |
|
8a8ff6b577ed
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|
8799 __ andnl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rsrc1), HIGH_FROM_LOW(Rsrc2)); |
|
8a8ff6b577ed
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|
8800 %} |
|
8a8ff6b577ed
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|
8801 ins_pipe(ialu_reg_reg_long); |
|
8a8ff6b577ed
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|
8802 %} |
|
8a8ff6b577ed
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diff
changeset
|
8803 |
|
8a8ff6b577ed
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diff
changeset
|
8804 instruct andnL_eReg_eReg_mem(eRegL dst, eRegL src1, memory src2, immL_M1 minus_1, eFlagsReg cr) %{ |
|
8a8ff6b577ed
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|
8805 match(Set dst (AndL (XorL src1 minus_1) (LoadL src2) )); |
|
8a8ff6b577ed
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17726
diff
changeset
|
8806 predicate(UseBMI1Instructions); |
|
8a8ff6b577ed
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diff
changeset
|
8807 effect(KILL cr, TEMP dst); |
|
8a8ff6b577ed
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17726
diff
changeset
|
8808 |
|
8a8ff6b577ed
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diff
changeset
|
8809 ins_cost(125); |
|
8a8ff6b577ed
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|
8810 format %{ "ANDNL $dst.lo, $src1.lo, $src2\n\t" |
|
8a8ff6b577ed
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|
8811 "ANDNL $dst.hi, $src1.hi, $src2+4" |
|
8a8ff6b577ed
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|
8812 %} |
|
8a8ff6b577ed
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diff
changeset
|
8813 |
|
8a8ff6b577ed
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diff
changeset
|
8814 ins_encode %{ |
|
8a8ff6b577ed
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changeset
|
8815 Register Rdst = $dst$$Register; |
|
8a8ff6b577ed
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changeset
|
8816 Register Rsrc1 = $src1$$Register; |
|
8a8ff6b577ed
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|
8817 Address src2_hi = Address::make_raw($src2$$base, $src2$$index, $src2$$scale, $src2$$disp + 4, relocInfo::none); |
|
8a8ff6b577ed
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|
8818 |
|
8a8ff6b577ed
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diff
changeset
|
8819 __ andnl(Rdst, Rsrc1, $src2$$Address); |
|
8a8ff6b577ed
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|
8820 __ andnl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rsrc1), src2_hi); |
|
8a8ff6b577ed
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diff
changeset
|
8821 %} |
|
8a8ff6b577ed
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diff
changeset
|
8822 ins_pipe(ialu_reg_mem); |
|
8a8ff6b577ed
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diff
changeset
|
8823 %} |
|
8a8ff6b577ed
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diff
changeset
|
8824 |
|
8a8ff6b577ed
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|
8825 instruct blsiL_eReg_eReg(eRegL dst, eRegL src, immL0 imm_zero, eFlagsReg cr) %{ |
|
8a8ff6b577ed
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|
8826 match(Set dst (AndL (SubL imm_zero src) src)); |
|
8a8ff6b577ed
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diff
changeset
|
8827 predicate(UseBMI1Instructions); |
|
8a8ff6b577ed
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diff
changeset
|
8828 effect(KILL cr, TEMP dst); |
|
8a8ff6b577ed
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diff
changeset
|
8829 |
|
8a8ff6b577ed
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diff
changeset
|
8830 format %{ "MOVL $dst.hi, 0\n\t" |
|
8a8ff6b577ed
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diff
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|
8831 "BLSIL $dst.lo, $src.lo\n\t" |
|
8a8ff6b577ed
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|
8832 "JNZ done\n\t" |
|
8a8ff6b577ed
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|
8833 "BLSIL $dst.hi, $src.hi\n" |
|
8a8ff6b577ed
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diff
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|
8834 "done:" |
|
8a8ff6b577ed
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diff
changeset
|
8835 %} |
|
8a8ff6b577ed
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diff
changeset
|
8836 |
|
8a8ff6b577ed
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diff
changeset
|
8837 ins_encode %{ |
|
8a8ff6b577ed
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diff
changeset
|
8838 Label done; |
|
8a8ff6b577ed
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diff
changeset
|
8839 Register Rdst = $dst$$Register; |
|
8a8ff6b577ed
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parents:
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diff
changeset
|
8840 Register Rsrc = $src$$Register; |
|
8a8ff6b577ed
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|
8841 __ movl(HIGH_FROM_LOW(Rdst), 0); |
|
8a8ff6b577ed
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diff
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|
8842 __ blsil(Rdst, Rsrc); |
|
8a8ff6b577ed
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|
8843 __ jccb(Assembler::notZero, done); |
|
8a8ff6b577ed
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diff
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|
8844 __ blsil(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rsrc)); |
|
8a8ff6b577ed
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|
8845 __ bind(done); |
|
8a8ff6b577ed
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diff
changeset
|
8846 %} |
|
8a8ff6b577ed
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parents:
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diff
changeset
|
8847 ins_pipe(ialu_reg); |
|
8a8ff6b577ed
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diff
changeset
|
8848 %} |
|
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diff
changeset
|
8849 |
|
8a8ff6b577ed
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|
8850 instruct blsiL_eReg_mem(eRegL dst, memory src, immL0 imm_zero, eFlagsReg cr) %{ |
|
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|
8851 match(Set dst (AndL (SubL imm_zero (LoadL src) ) (LoadL src) )); |
|
8a8ff6b577ed
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diff
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|
8852 predicate(UseBMI1Instructions); |
|
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|
8853 effect(KILL cr, TEMP dst); |
|
8a8ff6b577ed
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|
8854 |
|
8a8ff6b577ed
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diff
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|
8855 ins_cost(125); |
|
8a8ff6b577ed
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|
8856 format %{ "MOVL $dst.hi, 0\n\t" |
|
8a8ff6b577ed
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diff
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|
8857 "BLSIL $dst.lo, $src\n\t" |
|
8a8ff6b577ed
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diff
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|
8858 "JNZ done\n\t" |
|
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|
8859 "BLSIL $dst.hi, $src+4\n" |
|
8a8ff6b577ed
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diff
changeset
|
8860 "done:" |
|
8a8ff6b577ed
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diff
changeset
|
8861 %} |
|
8a8ff6b577ed
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diff
changeset
|
8862 |
|
8a8ff6b577ed
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changeset
|
8863 ins_encode %{ |
|
8a8ff6b577ed
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diff
changeset
|
8864 Label done; |
|
8a8ff6b577ed
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changeset
|
8865 Register Rdst = $dst$$Register; |
|
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|
8866 Address src_hi = Address::make_raw($src$$base, $src$$index, $src$$scale, $src$$disp + 4, relocInfo::none); |
|
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diff
changeset
|
8867 |
|
8a8ff6b577ed
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diff
changeset
|
8868 __ movl(HIGH_FROM_LOW(Rdst), 0); |
|
8a8ff6b577ed
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diff
changeset
|
8869 __ blsil(Rdst, $src$$Address); |
|
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diff
changeset
|
8870 __ jccb(Assembler::notZero, done); |
|
8a8ff6b577ed
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diff
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|
8871 __ blsil(HIGH_FROM_LOW(Rdst), src_hi); |
|
8a8ff6b577ed
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diff
changeset
|
8872 __ bind(done); |
|
8a8ff6b577ed
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iveresov
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diff
changeset
|
8873 %} |
|
8a8ff6b577ed
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diff
changeset
|
8874 ins_pipe(ialu_reg_mem); |
|
8a8ff6b577ed
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diff
changeset
|
8875 %} |
|
8a8ff6b577ed
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diff
changeset
|
8876 |
|
8a8ff6b577ed
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diff
changeset
|
8877 instruct blsmskL_eReg_eReg(eRegL dst, eRegL src, immL_M1 minus_1, eFlagsReg cr) |
|
8a8ff6b577ed
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diff
changeset
|
8878 %{ |
|
8a8ff6b577ed
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diff
changeset
|
8879 match(Set dst (XorL (AddL src minus_1) src)); |
|
8a8ff6b577ed
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parents:
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diff
changeset
|
8880 predicate(UseBMI1Instructions); |
|
8a8ff6b577ed
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iveresov
parents:
17726
diff
changeset
|
8881 effect(KILL cr, TEMP dst); |
|
8a8ff6b577ed
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iveresov
parents:
17726
diff
changeset
|
8882 |
|
8a8ff6b577ed
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parents:
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diff
changeset
|
8883 format %{ "MOVL $dst.hi, 0\n\t" |
|
8a8ff6b577ed
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parents:
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diff
changeset
|
8884 "BLSMSKL $dst.lo, $src.lo\n\t" |
|
8a8ff6b577ed
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diff
changeset
|
8885 "JNC done\n\t" |
|
8a8ff6b577ed
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diff
changeset
|
8886 "BLSMSKL $dst.hi, $src.hi\n" |
|
8a8ff6b577ed
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parents:
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diff
changeset
|
8887 "done:" |
|
8a8ff6b577ed
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parents:
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diff
changeset
|
8888 %} |
|
8a8ff6b577ed
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parents:
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diff
changeset
|
8889 |
|
8a8ff6b577ed
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parents:
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diff
changeset
|
8890 ins_encode %{ |
|
8a8ff6b577ed
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parents:
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diff
changeset
|
8891 Label done; |
|
8a8ff6b577ed
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diff
changeset
|
8892 Register Rdst = $dst$$Register; |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
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17726
diff
changeset
|
8893 Register Rsrc = $src$$Register; |
|
8a8ff6b577ed
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diff
changeset
|
8894 __ movl(HIGH_FROM_LOW(Rdst), 0); |
|
8a8ff6b577ed
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diff
changeset
|
8895 __ blsmskl(Rdst, Rsrc); |
|
8a8ff6b577ed
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diff
changeset
|
8896 __ jccb(Assembler::carryClear, done); |
|
8a8ff6b577ed
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diff
changeset
|
8897 __ blsmskl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rsrc)); |
|
8a8ff6b577ed
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diff
changeset
|
8898 __ bind(done); |
|
8a8ff6b577ed
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diff
changeset
|
8899 %} |
|
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parents:
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diff
changeset
|
8900 |
|
8a8ff6b577ed
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iveresov
parents:
17726
diff
changeset
|
8901 ins_pipe(ialu_reg); |
|
8a8ff6b577ed
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parents:
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diff
changeset
|
8902 %} |
|
8a8ff6b577ed
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iveresov
parents:
17726
diff
changeset
|
8903 |
|
8a8ff6b577ed
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iveresov
parents:
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diff
changeset
|
8904 instruct blsmskL_eReg_mem(eRegL dst, memory src, immL_M1 minus_1, eFlagsReg cr) |
|
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diff
changeset
|
8905 %{ |
|
8a8ff6b577ed
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diff
changeset
|
8906 match(Set dst (XorL (AddL (LoadL src) minus_1) (LoadL src) )); |
|
8a8ff6b577ed
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parents:
17726
diff
changeset
|
8907 predicate(UseBMI1Instructions); |
|
8a8ff6b577ed
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parents:
17726
diff
changeset
|
8908 effect(KILL cr, TEMP dst); |
|
8a8ff6b577ed
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iveresov
parents:
17726
diff
changeset
|
8909 |
|
8a8ff6b577ed
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iveresov
parents:
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diff
changeset
|
8910 ins_cost(125); |
|
8a8ff6b577ed
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diff
changeset
|
8911 format %{ "MOVL $dst.hi, 0\n\t" |
|
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parents:
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diff
changeset
|
8912 "BLSMSKL $dst.lo, $src\n\t" |
|
8a8ff6b577ed
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diff
changeset
|
8913 "JNC done\n\t" |
|
8a8ff6b577ed
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diff
changeset
|
8914 "BLSMSKL $dst.hi, $src+4\n" |
|
8a8ff6b577ed
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parents:
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diff
changeset
|
8915 "done:" |
|
8a8ff6b577ed
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parents:
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diff
changeset
|
8916 %} |
|
8a8ff6b577ed
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parents:
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diff
changeset
|
8917 |
|
8a8ff6b577ed
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iveresov
parents:
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diff
changeset
|
8918 ins_encode %{ |
|
8a8ff6b577ed
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parents:
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diff
changeset
|
8919 Label done; |
|
8a8ff6b577ed
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parents:
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diff
changeset
|
8920 Register Rdst = $dst$$Register; |
|
8a8ff6b577ed
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diff
changeset
|
8921 Address src_hi = Address::make_raw($src$$base, $src$$index, $src$$scale, $src$$disp + 4, relocInfo::none); |
|
8a8ff6b577ed
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parents:
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diff
changeset
|
8922 |
|
8a8ff6b577ed
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parents:
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diff
changeset
|
8923 __ movl(HIGH_FROM_LOW(Rdst), 0); |
|
8a8ff6b577ed
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diff
changeset
|
8924 __ blsmskl(Rdst, $src$$Address); |
|
8a8ff6b577ed
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diff
changeset
|
8925 __ jccb(Assembler::carryClear, done); |
|
8a8ff6b577ed
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parents:
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diff
changeset
|
8926 __ blsmskl(HIGH_FROM_LOW(Rdst), src_hi); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
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parents:
17726
diff
changeset
|
8927 __ bind(done); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
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parents:
17726
diff
changeset
|
8928 %} |
|
8a8ff6b577ed
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iveresov
parents:
17726
diff
changeset
|
8929 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8930 ins_pipe(ialu_reg_mem); |
|
8a8ff6b577ed
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iveresov
parents:
17726
diff
changeset
|
8931 %} |
|
8a8ff6b577ed
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iveresov
parents:
17726
diff
changeset
|
8932 |
|
8a8ff6b577ed
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iveresov
parents:
17726
diff
changeset
|
8933 instruct blsrL_eReg_eReg(eRegL dst, eRegL src, immL_M1 minus_1, eFlagsReg cr) |
|
8a8ff6b577ed
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iveresov
parents:
17726
diff
changeset
|
8934 %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
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diff
changeset
|
8935 match(Set dst (AndL (AddL src minus_1) src) ); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8936 predicate(UseBMI1Instructions); |
|
8a8ff6b577ed
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iveresov
parents:
17726
diff
changeset
|
8937 effect(KILL cr, TEMP dst); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8938 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8939 format %{ "MOVL $dst.hi, $src.hi\n\t" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8940 "BLSRL $dst.lo, $src.lo\n\t" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8941 "JNC done\n\t" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8942 "BLSRL $dst.hi, $src.hi\n" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8943 "done:" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8944 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8945 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8946 ins_encode %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8947 Label done; |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8948 Register Rdst = $dst$$Register; |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8949 Register Rsrc = $src$$Register; |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8950 __ movl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rsrc)); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8951 __ blsrl(Rdst, Rsrc); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8952 __ jccb(Assembler::carryClear, done); |
|
8a8ff6b577ed
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parents:
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diff
changeset
|
8953 __ blsrl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rsrc)); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8954 __ bind(done); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8955 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8956 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8957 ins_pipe(ialu_reg); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8958 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8959 |
|
8a8ff6b577ed
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iveresov
parents:
17726
diff
changeset
|
8960 instruct blsrL_eReg_mem(eRegL dst, memory src, immL_M1 minus_1, eFlagsReg cr) |
|
8a8ff6b577ed
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iveresov
parents:
17726
diff
changeset
|
8961 %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8962 match(Set dst (AndL (AddL (LoadL src) minus_1) (LoadL src) )); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8963 predicate(UseBMI1Instructions); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8964 effect(KILL cr, TEMP dst); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8965 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8966 ins_cost(125); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8967 format %{ "MOVL $dst.hi, $src+4\n\t" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8968 "BLSRL $dst.lo, $src\n\t" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8969 "JNC done\n\t" |
|
8a8ff6b577ed
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iveresov
parents:
17726
diff
changeset
|
8970 "BLSRL $dst.hi, $src+4\n" |
|
8a8ff6b577ed
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iveresov
parents:
17726
diff
changeset
|
8971 "done:" |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8972 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8973 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8974 ins_encode %{ |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8975 Label done; |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8976 Register Rdst = $dst$$Register; |
|
8a8ff6b577ed
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iveresov
parents:
17726
diff
changeset
|
8977 Address src_hi = Address::make_raw($src$$base, $src$$index, $src$$scale, $src$$disp + 4, relocInfo::none); |
|
8a8ff6b577ed
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parents:
17726
diff
changeset
|
8978 __ movl(HIGH_FROM_LOW(Rdst), src_hi); |
|
8a8ff6b577ed
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iveresov
parents:
17726
diff
changeset
|
8979 __ blsrl(Rdst, $src$$Address); |
|
8a8ff6b577ed
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parents:
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diff
changeset
|
8980 __ jccb(Assembler::carryClear, done); |
|
8a8ff6b577ed
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parents:
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diff
changeset
|
8981 __ blsrl(HIGH_FROM_LOW(Rdst), src_hi); |
|
8a8ff6b577ed
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iveresov
parents:
17726
diff
changeset
|
8982 __ bind(done); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8983 %} |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8984 |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8985 ins_pipe(ialu_reg_mem); |
|
8a8ff6b577ed
8031321: Support Intel bit manipulation instructions
iveresov
parents:
17726
diff
changeset
|
8986 %} |
|
8a8ff6b577ed
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diff
changeset
|
8987 |
| 0 | 8988 // Or Long Register with Register |
| 8989 instruct orl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ | |
| 8990 match(Set dst (OrL dst src)); | |
| 8991 effect(KILL cr); | |
| 8992 format %{ "OR $dst.lo,$src.lo\n\t" | |
| 8993 "OR $dst.hi,$src.hi" %} | |
| 8994 opcode(0x0B,0x0B); | |
| 8995 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) ); | |
| 8996 ins_pipe( ialu_reg_reg_long ); | |
| 8997 %} | |
| 8998 | |
| 8999 // Or Long Register with Immediate | |
| 9000 instruct orl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ | |
| 9001 match(Set dst (OrL dst src)); | |
| 9002 effect(KILL cr); | |
| 9003 format %{ "OR $dst.lo,$src.lo\n\t" | |
| 9004 "OR $dst.hi,$src.hi" %} | |
| 9005 opcode(0x81,0x01,0x01); /* Opcode 81 /1, 81 /1 */ | |
| 9006 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); | |
| 9007 ins_pipe( ialu_reg_long ); | |
| 9008 %} | |
| 9009 | |
| 9010 // Or Long Register with Memory | |
| 9011 instruct orl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ | |
| 9012 match(Set dst (OrL dst (LoadL mem))); | |
| 9013 effect(KILL cr); | |
| 9014 ins_cost(125); | |
| 9015 format %{ "OR $dst.lo,$mem\n\t" | |
| 9016 "OR $dst.hi,$mem+4" %} | |
| 9017 opcode(0x0B,0x0B); | |
| 9018 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); | |
| 9019 ins_pipe( ialu_reg_long_mem ); | |
| 9020 %} | |
| 9021 | |
| 9022 // Xor Long Register with Register | |
| 9023 instruct xorl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ | |
| 9024 match(Set dst (XorL dst src)); | |
| 9025 effect(KILL cr); | |
| 9026 format %{ "XOR $dst.lo,$src.lo\n\t" | |
| 9027 "XOR $dst.hi,$src.hi" %} | |
| 9028 opcode(0x33,0x33); | |
| 9029 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) ); | |
| 9030 ins_pipe( ialu_reg_reg_long ); | |
| 9031 %} | |
| 9032 | |
| 403 | 9033 // Xor Long Register with Immediate -1 |
| 9034 instruct xorl_eReg_im1(eRegL dst, immL_M1 imm) %{ | |
| 9035 match(Set dst (XorL dst imm)); | |
| 9036 format %{ "NOT $dst.lo\n\t" | |
| 9037 "NOT $dst.hi" %} | |
| 9038 ins_encode %{ | |
| 9039 __ notl($dst$$Register); | |
| 9040 __ notl(HIGH_FROM_LOW($dst$$Register)); | |
| 9041 %} | |
| 9042 ins_pipe( ialu_reg_long ); | |
| 9043 %} | |
| 9044 | |
| 0 | 9045 // Xor Long Register with Immediate |
| 9046 instruct xorl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ | |
| 9047 match(Set dst (XorL dst src)); | |
| 9048 effect(KILL cr); | |
| 9049 format %{ "XOR $dst.lo,$src.lo\n\t" | |
| 9050 "XOR $dst.hi,$src.hi" %} | |
| 9051 opcode(0x81,0x06,0x06); /* Opcode 81 /6, 81 /6 */ | |
| 9052 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); | |
| 9053 ins_pipe( ialu_reg_long ); | |
| 9054 %} | |
| 9055 | |
| 9056 // Xor Long Register with Memory | |
| 9057 instruct xorl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ | |
| 9058 match(Set dst (XorL dst (LoadL mem))); | |
| 9059 effect(KILL cr); | |
| 9060 ins_cost(125); | |
| 9061 format %{ "XOR $dst.lo,$mem\n\t" | |
| 9062 "XOR $dst.hi,$mem+4" %} | |
| 9063 opcode(0x33,0x33); | |
| 9064 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); | |
| 9065 ins_pipe( ialu_reg_long_mem ); | |
| 9066 %} | |
| 9067 | |
| 219 | 9068 // Shift Left Long by 1 |
| 9069 instruct shlL_eReg_1(eRegL dst, immI_1 cnt, eFlagsReg cr) %{ | |
| 9070 predicate(UseNewLongLShift); | |
| 9071 match(Set dst (LShiftL dst cnt)); | |
| 9072 effect(KILL cr); | |
| 9073 ins_cost(100); | |
| 9074 format %{ "ADD $dst.lo,$dst.lo\n\t" | |
| 9075 "ADC $dst.hi,$dst.hi" %} | |
| 9076 ins_encode %{ | |
| 9077 __ addl($dst$$Register,$dst$$Register); | |
| 9078 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); | |
| 9079 %} | |
| 9080 ins_pipe( ialu_reg_long ); | |
| 9081 %} | |
| 9082 | |
| 9083 // Shift Left Long by 2 | |
| 9084 instruct shlL_eReg_2(eRegL dst, immI_2 cnt, eFlagsReg cr) %{ | |
| 9085 predicate(UseNewLongLShift); | |
| 9086 match(Set dst (LShiftL dst cnt)); | |
| 9087 effect(KILL cr); | |
| 9088 ins_cost(100); | |
| 9089 format %{ "ADD $dst.lo,$dst.lo\n\t" | |
| 9090 "ADC $dst.hi,$dst.hi\n\t" | |
| 9091 "ADD $dst.lo,$dst.lo\n\t" | |
| 9092 "ADC $dst.hi,$dst.hi" %} | |
| 9093 ins_encode %{ | |
| 9094 __ addl($dst$$Register,$dst$$Register); | |
| 9095 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); | |
| 9096 __ addl($dst$$Register,$dst$$Register); | |
| 9097 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); | |
| 9098 %} | |
| 9099 ins_pipe( ialu_reg_long ); | |
| 9100 %} | |
| 9101 | |
| 9102 // Shift Left Long by 3 | |
| 9103 instruct shlL_eReg_3(eRegL dst, immI_3 cnt, eFlagsReg cr) %{ | |
| 9104 predicate(UseNewLongLShift); | |
| 9105 match(Set dst (LShiftL dst cnt)); | |
| 9106 effect(KILL cr); | |
| 9107 ins_cost(100); | |
| 9108 format %{ "ADD $dst.lo,$dst.lo\n\t" | |
| 9109 "ADC $dst.hi,$dst.hi\n\t" | |
| 9110 "ADD $dst.lo,$dst.lo\n\t" | |
| 9111 "ADC $dst.hi,$dst.hi\n\t" | |
| 9112 "ADD $dst.lo,$dst.lo\n\t" | |
| 9113 "ADC $dst.hi,$dst.hi" %} | |
| 9114 ins_encode %{ | |
| 9115 __ addl($dst$$Register,$dst$$Register); | |
| 9116 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); | |
| 9117 __ addl($dst$$Register,$dst$$Register); | |
| 9118 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); | |
| 9119 __ addl($dst$$Register,$dst$$Register); | |
| 9120 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); | |
| 9121 %} | |
| 9122 ins_pipe( ialu_reg_long ); | |
| 9123 %} | |
| 9124 | |
| 0 | 9125 // Shift Left Long by 1-31 |
| 9126 instruct shlL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{ | |
| 9127 match(Set dst (LShiftL dst cnt)); | |
| 9128 effect(KILL cr); | |
| 9129 ins_cost(200); | |
| 9130 format %{ "SHLD $dst.hi,$dst.lo,$cnt\n\t" | |
| 9131 "SHL $dst.lo,$cnt" %} | |
| 9132 opcode(0xC1, 0x4, 0xA4); /* 0F/A4, then C1 /4 ib */ | |
| 9133 ins_encode( move_long_small_shift(dst,cnt) ); | |
| 9134 ins_pipe( ialu_reg_long ); | |
| 9135 %} | |
| 9136 | |
| 9137 // Shift Left Long by 32-63 | |
| 9138 instruct shlL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{ | |
| 9139 match(Set dst (LShiftL dst cnt)); | |
| 9140 effect(KILL cr); | |
| 9141 ins_cost(300); | |
| 9142 format %{ "MOV $dst.hi,$dst.lo\n" | |
| 9143 "\tSHL $dst.hi,$cnt-32\n" | |
| 9144 "\tXOR $dst.lo,$dst.lo" %} | |
| 9145 opcode(0xC1, 0x4); /* C1 /4 ib */ | |
| 9146 ins_encode( move_long_big_shift_clr(dst,cnt) ); | |
| 9147 ins_pipe( ialu_reg_long ); | |
| 9148 %} | |
| 9149 | |
| 9150 // Shift Left Long by variable | |
| 9151 instruct salL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{ | |
| 9152 match(Set dst (LShiftL dst shift)); | |
| 9153 effect(KILL cr); | |
| 9154 ins_cost(500+200); | |
| 9155 size(17); | |
| 9156 format %{ "TEST $shift,32\n\t" | |
| 9157 "JEQ,s small\n\t" | |
| 9158 "MOV $dst.hi,$dst.lo\n\t" | |
| 9159 "XOR $dst.lo,$dst.lo\n" | |
| 9160 "small:\tSHLD $dst.hi,$dst.lo,$shift\n\t" | |
| 9161 "SHL $dst.lo,$shift" %} | |
| 9162 ins_encode( shift_left_long( dst, shift ) ); | |
| 9163 ins_pipe( pipe_slow ); | |
| 9164 %} | |
| 9165 | |
| 9166 // Shift Right Long by 1-31 | |
| 9167 instruct shrL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{ | |
| 9168 match(Set dst (URShiftL dst cnt)); | |
| 9169 effect(KILL cr); | |
| 9170 ins_cost(200); | |
| 9171 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t" | |
| 9172 "SHR $dst.hi,$cnt" %} | |
| 9173 opcode(0xC1, 0x5, 0xAC); /* 0F/AC, then C1 /5 ib */ | |
| 9174 ins_encode( move_long_small_shift(dst,cnt) ); | |
| 9175 ins_pipe( ialu_reg_long ); | |
| 9176 %} | |
| 9177 | |
| 9178 // Shift Right Long by 32-63 | |
| 9179 instruct shrL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{ | |
| 9180 match(Set dst (URShiftL dst cnt)); | |
| 9181 effect(KILL cr); | |
| 9182 ins_cost(300); | |
| 9183 format %{ "MOV $dst.lo,$dst.hi\n" | |
| 9184 "\tSHR $dst.lo,$cnt-32\n" | |
| 9185 "\tXOR $dst.hi,$dst.hi" %} | |
| 9186 opcode(0xC1, 0x5); /* C1 /5 ib */ | |
| 9187 ins_encode( move_long_big_shift_clr(dst,cnt) ); | |
| 9188 ins_pipe( ialu_reg_long ); | |
| 9189 %} | |
| 9190 | |
| 9191 // Shift Right Long by variable | |
| 9192 instruct shrL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{ | |
| 9193 match(Set dst (URShiftL dst shift)); | |
| 9194 effect(KILL cr); | |
| 9195 ins_cost(600); | |
| 9196 size(17); | |
| 9197 format %{ "TEST $shift,32\n\t" | |
| 9198 "JEQ,s small\n\t" | |
| 9199 "MOV $dst.lo,$dst.hi\n\t" | |
| 9200 "XOR $dst.hi,$dst.hi\n" | |
| 9201 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t" | |
| 9202 "SHR $dst.hi,$shift" %} | |
| 9203 ins_encode( shift_right_long( dst, shift ) ); | |
| 9204 ins_pipe( pipe_slow ); | |
| 9205 %} | |
| 9206 | |
| 9207 // Shift Right Long by 1-31 | |
| 9208 instruct sarL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{ | |
| 9209 match(Set dst (RShiftL dst cnt)); | |
| 9210 effect(KILL cr); | |
| 9211 ins_cost(200); | |
| 9212 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t" | |
| 9213 "SAR $dst.hi,$cnt" %} | |
| 9214 opcode(0xC1, 0x7, 0xAC); /* 0F/AC, then C1 /7 ib */ | |
| 9215 ins_encode( move_long_small_shift(dst,cnt) ); | |
| 9216 ins_pipe( ialu_reg_long ); | |
| 9217 %} | |
| 9218 | |
| 9219 // Shift Right Long by 32-63 | |
| 9220 instruct sarL_eReg_32_63( eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{ | |
| 9221 match(Set dst (RShiftL dst cnt)); | |
| 9222 effect(KILL cr); | |
| 9223 ins_cost(300); | |
| 9224 format %{ "MOV $dst.lo,$dst.hi\n" | |
| 9225 "\tSAR $dst.lo,$cnt-32\n" | |
| 9226 "\tSAR $dst.hi,31" %} | |
| 9227 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 9228 ins_encode( move_long_big_shift_sign(dst,cnt) ); | |
| 9229 ins_pipe( ialu_reg_long ); | |
| 9230 %} | |
| 9231 | |
| 9232 // Shift Right arithmetic Long by variable | |
| 9233 instruct sarL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{ | |
| 9234 match(Set dst (RShiftL dst shift)); | |
| 9235 effect(KILL cr); | |
| 9236 ins_cost(600); | |
| 9237 size(18); | |
| 9238 format %{ "TEST $shift,32\n\t" | |
| 9239 "JEQ,s small\n\t" | |
| 9240 "MOV $dst.lo,$dst.hi\n\t" | |
| 9241 "SAR $dst.hi,31\n" | |
| 9242 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t" | |
| 9243 "SAR $dst.hi,$shift" %} | |
| 9244 ins_encode( shift_right_arith_long( dst, shift ) ); | |
| 9245 ins_pipe( pipe_slow ); | |
| 9246 %} | |
| 9247 | |
| 9248 | |
| 9249 //----------Double Instructions------------------------------------------------ | |
| 9250 // Double Math | |
| 9251 | |
| 9252 // Compare & branch | |
| 9253 | |
| 9254 // P6 version of float compare, sets condition codes in EFLAGS | |
|
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9255 instruct cmpDPR_cc_P6(eFlagsRegU cr, regDPR src1, regDPR src2, eAXRegI rax) %{ |
| 0 | 9256 predicate(VM_Version::supports_cmov() && UseSSE <=1); |
| 9257 match(Set cr (CmpD src1 src2)); | |
| 9258 effect(KILL rax); | |
| 9259 ins_cost(150); | |
| 9260 format %{ "FLD $src1\n\t" | |
| 9261 "FUCOMIP ST,$src2 // P6 instruction\n\t" | |
| 9262 "JNP exit\n\t" | |
| 9263 "MOV ah,1 // saw a NaN, set CF\n\t" | |
| 9264 "SAHF\n" | |
| 9265 "exit:\tNOP // avoid branch to branch" %} | |
| 9266 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */ | |
|
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9267 ins_encode( Push_Reg_DPR(src1), |
| 0 | 9268 OpcP, RegOpc(src2), |
| 9269 cmpF_P6_fixup ); | |
| 9270 ins_pipe( pipe_slow ); | |
| 9271 %} | |
| 9272 | |
|
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9273 instruct cmpDPR_cc_P6CF(eFlagsRegUCF cr, regDPR src1, regDPR src2) %{ |
|
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9274 predicate(VM_Version::supports_cmov() && UseSSE <=1); |
|
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9275 match(Set cr (CmpD src1 src2)); |
|
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9276 ins_cost(150); |
|
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9277 format %{ "FLD $src1\n\t" |
|
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9278 "FUCOMIP ST,$src2 // P6 instruction" %} |
|
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|
9279 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */ |
|
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9280 ins_encode( Push_Reg_DPR(src1), |
|
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|
9281 OpcP, RegOpc(src2)); |
|
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|
9282 ins_pipe( pipe_slow ); |
|
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|
9283 %} |
|
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|
9284 |
| 0 | 9285 // Compare & branch |
|
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9286 instruct cmpDPR_cc(eFlagsRegU cr, regDPR src1, regDPR src2, eAXRegI rax) %{ |
| 0 | 9287 predicate(UseSSE<=1); |
| 9288 match(Set cr (CmpD src1 src2)); | |
| 9289 effect(KILL rax); | |
| 9290 ins_cost(200); | |
| 9291 format %{ "FLD $src1\n\t" | |
| 9292 "FCOMp $src2\n\t" | |
| 9293 "FNSTSW AX\n\t" | |
| 9294 "TEST AX,0x400\n\t" | |
| 9295 "JZ,s flags\n\t" | |
| 9296 "MOV AH,1\t# unordered treat as LT\n" | |
| 9297 "flags:\tSAHF" %} | |
| 9298 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */ | |
|
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9299 ins_encode( Push_Reg_DPR(src1), |
| 0 | 9300 OpcP, RegOpc(src2), |
| 9301 fpu_flags); | |
| 9302 ins_pipe( pipe_slow ); | |
| 9303 %} | |
| 9304 | |
| 9305 // Compare vs zero into -1,0,1 | |
|
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9306 instruct cmpDPR_0(rRegI dst, regDPR src1, immDPR0 zero, eAXRegI rax, eFlagsReg cr) %{ |
| 0 | 9307 predicate(UseSSE<=1); |
| 9308 match(Set dst (CmpD3 src1 zero)); | |
| 9309 effect(KILL cr, KILL rax); | |
| 9310 ins_cost(280); | |
| 9311 format %{ "FTSTD $dst,$src1" %} | |
| 9312 opcode(0xE4, 0xD9); | |
|
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9313 ins_encode( Push_Reg_DPR(src1), |
| 0 | 9314 OpcS, OpcP, PopFPU, |
| 9315 CmpF_Result(dst)); | |
| 9316 ins_pipe( pipe_slow ); | |
| 9317 %} | |
| 9318 | |
| 9319 // Compare into -1,0,1 | |
|
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9320 instruct cmpDPR_reg(rRegI dst, regDPR src1, regDPR src2, eAXRegI rax, eFlagsReg cr) %{ |
| 0 | 9321 predicate(UseSSE<=1); |
| 9322 match(Set dst (CmpD3 src1 src2)); | |
| 9323 effect(KILL cr, KILL rax); | |
| 9324 ins_cost(300); | |
| 9325 format %{ "FCMPD $dst,$src1,$src2" %} | |
| 9326 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */ | |
|
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9327 ins_encode( Push_Reg_DPR(src1), |
| 0 | 9328 OpcP, RegOpc(src2), |
| 9329 CmpF_Result(dst)); | |
| 9330 ins_pipe( pipe_slow ); | |
| 9331 %} | |
| 9332 | |
| 9333 // float compare and set condition codes in EFLAGS by XMM regs | |
|
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9334 instruct cmpD_cc(eFlagsRegU cr, regD src1, regD src2) %{ |
| 0 | 9335 predicate(UseSSE>=2); |
| 4759 | 9336 match(Set cr (CmpD src1 src2)); |
| 9337 ins_cost(145); | |
| 9338 format %{ "UCOMISD $src1,$src2\n\t" | |
| 9339 "JNP,s exit\n\t" | |
| 9340 "PUSHF\t# saw NaN, set CF\n\t" | |
| 9341 "AND [rsp], #0xffffff2b\n\t" | |
| 9342 "POPF\n" | |
| 9343 "exit:" %} | |
| 9344 ins_encode %{ | |
| 9345 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister); | |
| 9346 emit_cmpfp_fixup(_masm); | |
| 9347 %} | |
| 9348 ins_pipe( pipe_slow ); | |
| 9349 %} | |
| 9350 | |
|
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9351 instruct cmpD_ccCF(eFlagsRegUCF cr, regD src1, regD src2) %{ |
|
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|
9352 predicate(UseSSE>=2); |
| 4759 | 9353 match(Set cr (CmpD src1 src2)); |
|
415
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|
9354 ins_cost(100); |
| 4759 | 9355 format %{ "UCOMISD $src1,$src2" %} |
| 9356 ins_encode %{ | |
| 9357 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister); | |
| 9358 %} | |
|
415
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|
9359 ins_pipe( pipe_slow ); |
|
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|
9360 %} |
|
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|
9361 |
| 0 | 9362 // float compare and set condition codes in EFLAGS by XMM regs |
|
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9363 instruct cmpD_ccmem(eFlagsRegU cr, regD src1, memory src2) %{ |
| 0 | 9364 predicate(UseSSE>=2); |
| 4759 | 9365 match(Set cr (CmpD src1 (LoadD src2))); |
| 0 | 9366 ins_cost(145); |
| 4759 | 9367 format %{ "UCOMISD $src1,$src2\n\t" |
| 9368 "JNP,s exit\n\t" | |
| 9369 "PUSHF\t# saw NaN, set CF\n\t" | |
| 9370 "AND [rsp], #0xffffff2b\n\t" | |
| 9371 "POPF\n" | |
| 9372 "exit:" %} | |
| 9373 ins_encode %{ | |
| 9374 __ ucomisd($src1$$XMMRegister, $src2$$Address); | |
| 9375 emit_cmpfp_fixup(_masm); | |
| 9376 %} | |
| 9377 ins_pipe( pipe_slow ); | |
| 9378 %} | |
| 9379 | |
|
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9380 instruct cmpD_ccmemCF(eFlagsRegUCF cr, regD src1, memory src2) %{ |
|
415
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|
9381 predicate(UseSSE>=2); |
| 4759 | 9382 match(Set cr (CmpD src1 (LoadD src2))); |
|
415
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|
9383 ins_cost(100); |
| 4759 | 9384 format %{ "UCOMISD $src1,$src2" %} |
| 9385 ins_encode %{ | |
| 9386 __ ucomisd($src1$$XMMRegister, $src2$$Address); | |
| 9387 %} | |
|
415
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|
9388 ins_pipe( pipe_slow ); |
|
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|
9389 %} |
|
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|
9390 |
| 0 | 9391 // Compare into -1,0,1 in XMM |
|
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9392 instruct cmpD_reg(xRegI dst, regD src1, regD src2, eFlagsReg cr) %{ |
| 0 | 9393 predicate(UseSSE>=2); |
| 9394 match(Set dst (CmpD3 src1 src2)); | |
| 9395 effect(KILL cr); | |
| 9396 ins_cost(255); | |
| 4759 | 9397 format %{ "UCOMISD $src1, $src2\n\t" |
| 9398 "MOV $dst, #-1\n\t" | |
| 9399 "JP,s done\n\t" | |
| 9400 "JB,s done\n\t" | |
| 9401 "SETNE $dst\n\t" | |
| 9402 "MOVZB $dst, $dst\n" | |
| 9403 "done:" %} | |
| 9404 ins_encode %{ | |
| 9405 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister); | |
| 9406 emit_cmpfp3(_masm, $dst$$Register); | |
| 9407 %} | |
| 0 | 9408 ins_pipe( pipe_slow ); |
| 9409 %} | |
| 9410 | |
| 9411 // Compare into -1,0,1 in XMM and memory | |
|
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9412 instruct cmpD_regmem(xRegI dst, regD src1, memory src2, eFlagsReg cr) %{ |
| 0 | 9413 predicate(UseSSE>=2); |
| 4759 | 9414 match(Set dst (CmpD3 src1 (LoadD src2))); |
| 0 | 9415 effect(KILL cr); |
| 9416 ins_cost(275); | |
| 4759 | 9417 format %{ "UCOMISD $src1, $src2\n\t" |
| 9418 "MOV $dst, #-1\n\t" | |
| 9419 "JP,s done\n\t" | |
| 9420 "JB,s done\n\t" | |
| 9421 "SETNE $dst\n\t" | |
| 9422 "MOVZB $dst, $dst\n" | |
| 9423 "done:" %} | |
| 9424 ins_encode %{ | |
| 9425 __ ucomisd($src1$$XMMRegister, $src2$$Address); | |
| 9426 emit_cmpfp3(_masm, $dst$$Register); | |
| 9427 %} | |
| 0 | 9428 ins_pipe( pipe_slow ); |
| 9429 %} | |
| 9430 | |
| 9431 | |
|
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9432 instruct subDPR_reg(regDPR dst, regDPR src) %{ |
| 0 | 9433 predicate (UseSSE <=1); |
| 9434 match(Set dst (SubD dst src)); | |
| 9435 | |
| 9436 format %{ "FLD $src\n\t" | |
| 9437 "DSUBp $dst,ST" %} | |
| 9438 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */ | |
| 9439 ins_cost(150); | |
|
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9440 ins_encode( Push_Reg_DPR(src), |
| 0 | 9441 OpcP, RegOpc(dst) ); |
| 9442 ins_pipe( fpu_reg_reg ); | |
| 9443 %} | |
| 9444 | |
|
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9445 instruct subDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{ |
| 0 | 9446 predicate (UseSSE <=1); |
| 9447 match(Set dst (RoundDouble (SubD src1 src2))); | |
| 9448 ins_cost(250); | |
| 9449 | |
| 9450 format %{ "FLD $src2\n\t" | |
| 9451 "DSUB ST,$src1\n\t" | |
| 9452 "FSTP_D $dst\t# D-round" %} | |
| 9453 opcode(0xD8, 0x5); | |
|
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9454 ins_encode( Push_Reg_DPR(src2), |
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9455 OpcP, RegOpc(src1), Pop_Mem_DPR(dst) ); |
| 0 | 9456 ins_pipe( fpu_mem_reg_reg ); |
| 9457 %} | |
| 9458 | |
| 9459 | |
|
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9460 instruct subDPR_reg_mem(regDPR dst, memory src) %{ |
| 0 | 9461 predicate (UseSSE <=1); |
| 9462 match(Set dst (SubD dst (LoadD src))); | |
| 9463 ins_cost(150); | |
| 9464 | |
| 9465 format %{ "FLD $src\n\t" | |
| 9466 "DSUBp $dst,ST" %} | |
| 9467 opcode(0xDE, 0x5, 0xDD); /* DE C0+i */ /* LoadD DD /0 */ | |
| 9468 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src), | |
| 9469 OpcP, RegOpc(dst) ); | |
| 9470 ins_pipe( fpu_reg_mem ); | |
| 9471 %} | |
| 9472 | |
|
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9473 instruct absDPR_reg(regDPR1 dst, regDPR1 src) %{ |
| 0 | 9474 predicate (UseSSE<=1); |
| 9475 match(Set dst (AbsD src)); | |
| 9476 ins_cost(100); | |
| 9477 format %{ "FABS" %} | |
| 9478 opcode(0xE1, 0xD9); | |
| 9479 ins_encode( OpcS, OpcP ); | |
| 9480 ins_pipe( fpu_reg_reg ); | |
| 9481 %} | |
| 9482 | |
|
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9483 instruct negDPR_reg(regDPR1 dst, regDPR1 src) %{ |
| 0 | 9484 predicate(UseSSE<=1); |
| 9485 match(Set dst (NegD src)); | |
| 9486 ins_cost(100); | |
| 9487 format %{ "FCHS" %} | |
| 9488 opcode(0xE0, 0xD9); | |
| 9489 ins_encode( OpcS, OpcP ); | |
| 9490 ins_pipe( fpu_reg_reg ); | |
| 9491 %} | |
| 9492 | |
|
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9493 instruct addDPR_reg(regDPR dst, regDPR src) %{ |
| 0 | 9494 predicate(UseSSE<=1); |
| 9495 match(Set dst (AddD dst src)); | |
| 9496 format %{ "FLD $src\n\t" | |
| 9497 "DADD $dst,ST" %} | |
| 9498 size(4); | |
| 9499 ins_cost(150); | |
| 9500 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/ | |
|
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9501 ins_encode( Push_Reg_DPR(src), |
| 0 | 9502 OpcP, RegOpc(dst) ); |
| 9503 ins_pipe( fpu_reg_reg ); | |
| 9504 %} | |
| 9505 | |
| 9506 | |
|
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9507 instruct addDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{ |
| 0 | 9508 predicate(UseSSE<=1); |
| 9509 match(Set dst (RoundDouble (AddD src1 src2))); | |
| 9510 ins_cost(250); | |
| 9511 | |
| 9512 format %{ "FLD $src2\n\t" | |
| 9513 "DADD ST,$src1\n\t" | |
| 9514 "FSTP_D $dst\t# D-round" %} | |
| 9515 opcode(0xD8, 0x0); /* D8 C0+i or D8 /0*/ | |
|
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9516 ins_encode( Push_Reg_DPR(src2), |
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9517 OpcP, RegOpc(src1), Pop_Mem_DPR(dst) ); |
| 0 | 9518 ins_pipe( fpu_mem_reg_reg ); |
| 9519 %} | |
| 9520 | |
| 9521 | |
|
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9522 instruct addDPR_reg_mem(regDPR dst, memory src) %{ |
| 0 | 9523 predicate(UseSSE<=1); |
| 9524 match(Set dst (AddD dst (LoadD src))); | |
| 9525 ins_cost(150); | |
| 9526 | |
| 9527 format %{ "FLD $src\n\t" | |
| 9528 "DADDp $dst,ST" %} | |
| 9529 opcode(0xDE, 0x0, 0xDD); /* DE C0+i */ /* LoadD DD /0 */ | |
| 9530 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src), | |
| 9531 OpcP, RegOpc(dst) ); | |
| 9532 ins_pipe( fpu_reg_mem ); | |
| 9533 %} | |
| 9534 | |
| 9535 // add-to-memory | |
|
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9536 instruct addDPR_mem_reg(memory dst, regDPR src) %{ |
| 0 | 9537 predicate(UseSSE<=1); |
| 9538 match(Set dst (StoreD dst (RoundDouble (AddD (LoadD dst) src)))); | |
| 9539 ins_cost(150); | |
| 9540 | |
| 9541 format %{ "FLD_D $dst\n\t" | |
| 9542 "DADD ST,$src\n\t" | |
| 9543 "FST_D $dst" %} | |
| 9544 opcode(0xDD, 0x0); | |
| 9545 ins_encode( Opcode(0xDD), RMopc_Mem(0x00,dst), | |
| 9546 Opcode(0xD8), RegOpc(src), | |
| 9547 set_instruction_start, | |
| 9548 Opcode(0xDD), RMopc_Mem(0x03,dst) ); | |
| 9549 ins_pipe( fpu_reg_mem ); | |
| 9550 %} | |
| 9551 | |
|
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9552 instruct addDPR_reg_imm1(regDPR dst, immDPR1 con) %{ |
| 0 | 9553 predicate(UseSSE<=1); |
| 2008 | 9554 match(Set dst (AddD dst con)); |
| 0 | 9555 ins_cost(125); |
| 9556 format %{ "FLD1\n\t" | |
| 9557 "DADDp $dst,ST" %} | |
| 2008 | 9558 ins_encode %{ |
| 9559 __ fld1(); | |
| 9560 __ faddp($dst$$reg); | |
| 9561 %} | |
| 9562 ins_pipe(fpu_reg); | |
| 9563 %} | |
| 9564 | |
|
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9565 instruct addDPR_reg_imm(regDPR dst, immDPR con) %{ |
| 0 | 9566 predicate(UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 ); |
| 2008 | 9567 match(Set dst (AddD dst con)); |
| 0 | 9568 ins_cost(200); |
| 2008 | 9569 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t" |
| 0 | 9570 "DADDp $dst,ST" %} |
| 2008 | 9571 ins_encode %{ |
| 9572 __ fld_d($constantaddress($con)); | |
| 9573 __ faddp($dst$$reg); | |
| 9574 %} | |
| 9575 ins_pipe(fpu_reg_mem); | |
| 0 | 9576 %} |
| 9577 | |
|
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9578 instruct addDPR_reg_imm_round(stackSlotD dst, regDPR src, immDPR con) %{ |
| 0 | 9579 predicate(UseSSE<=1 && _kids[0]->_kids[1]->_leaf->getd() != 0.0 && _kids[0]->_kids[1]->_leaf->getd() != 1.0 ); |
| 9580 match(Set dst (RoundDouble (AddD src con))); | |
| 9581 ins_cost(200); | |
| 2008 | 9582 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t" |
| 0 | 9583 "DADD ST,$src\n\t" |
| 9584 "FSTP_D $dst\t# D-round" %} | |
| 2008 | 9585 ins_encode %{ |
| 9586 __ fld_d($constantaddress($con)); | |
| 9587 __ fadd($src$$reg); | |
| 9588 __ fstp_d(Address(rsp, $dst$$disp)); | |
| 9589 %} | |
| 9590 ins_pipe(fpu_mem_reg_con); | |
| 0 | 9591 %} |
| 9592 | |
|
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9593 instruct mulDPR_reg(regDPR dst, regDPR src) %{ |
| 0 | 9594 predicate(UseSSE<=1); |
| 9595 match(Set dst (MulD dst src)); | |
| 9596 format %{ "FLD $src\n\t" | |
| 9597 "DMULp $dst,ST" %} | |
| 9598 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/ | |
| 9599 ins_cost(150); | |
|
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9600 ins_encode( Push_Reg_DPR(src), |
| 0 | 9601 OpcP, RegOpc(dst) ); |
| 9602 ins_pipe( fpu_reg_reg ); | |
| 9603 %} | |
| 9604 | |
| 9605 // Strict FP instruction biases argument before multiply then | |
| 9606 // biases result to avoid double rounding of subnormals. | |
| 9607 // | |
| 9608 // scale arg1 by multiplying arg1 by 2^(-15360) | |
| 9609 // load arg2 | |
| 9610 // multiply scaled arg1 by arg2 | |
| 9611 // rescale product by 2^(15360) | |
| 9612 // | |
|
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9613 instruct strictfp_mulDPR_reg(regDPR1 dst, regnotDPR1 src) %{ |
| 0 | 9614 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() ); |
| 9615 match(Set dst (MulD dst src)); | |
| 9616 ins_cost(1); // Select this instruction for all strict FP double multiplies | |
| 9617 | |
| 9618 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t" | |
| 9619 "DMULp $dst,ST\n\t" | |
| 9620 "FLD $src\n\t" | |
| 9621 "DMULp $dst,ST\n\t" | |
| 9622 "FLD StubRoutines::_fpu_subnormal_bias2\n\t" | |
| 9623 "DMULp $dst,ST\n\t" %} | |
| 9624 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/ | |
| 9625 ins_encode( strictfp_bias1(dst), | |
|
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9626 Push_Reg_DPR(src), |
| 0 | 9627 OpcP, RegOpc(dst), |
| 9628 strictfp_bias2(dst) ); | |
| 9629 ins_pipe( fpu_reg_reg ); | |
| 9630 %} | |
| 9631 | |
|
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9632 instruct mulDPR_reg_imm(regDPR dst, immDPR con) %{ |
| 0 | 9633 predicate( UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 ); |
| 2008 | 9634 match(Set dst (MulD dst con)); |
| 0 | 9635 ins_cost(200); |
| 2008 | 9636 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t" |
| 0 | 9637 "DMULp $dst,ST" %} |
| 2008 | 9638 ins_encode %{ |
| 9639 __ fld_d($constantaddress($con)); | |
| 9640 __ fmulp($dst$$reg); | |
| 9641 %} | |
| 9642 ins_pipe(fpu_reg_mem); | |
| 0 | 9643 %} |
| 9644 | |
| 9645 | |
|
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9646 instruct mulDPR_reg_mem(regDPR dst, memory src) %{ |
| 0 | 9647 predicate( UseSSE<=1 ); |
| 9648 match(Set dst (MulD dst (LoadD src))); | |
| 9649 ins_cost(200); | |
| 9650 format %{ "FLD_D $src\n\t" | |
| 9651 "DMULp $dst,ST" %} | |
| 9652 opcode(0xDE, 0x1, 0xDD); /* DE C8+i or DE /1*/ /* LoadD DD /0 */ | |
| 9653 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src), | |
| 9654 OpcP, RegOpc(dst) ); | |
| 9655 ins_pipe( fpu_reg_mem ); | |
| 9656 %} | |
| 9657 | |
| 9658 // | |
| 9659 // Cisc-alternate to reg-reg multiply | |
|
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9660 instruct mulDPR_reg_mem_cisc(regDPR dst, regDPR src, memory mem) %{ |
| 0 | 9661 predicate( UseSSE<=1 ); |
| 9662 match(Set dst (MulD src (LoadD mem))); | |
| 9663 ins_cost(250); | |
| 9664 format %{ "FLD_D $mem\n\t" | |
| 9665 "DMUL ST,$src\n\t" | |
| 9666 "FSTP_D $dst" %} | |
| 9667 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadD D9 /0 */ | |
| 9668 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem), | |
|
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9669 OpcReg_FPR(src), |
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9670 Pop_Reg_DPR(dst) ); |
| 0 | 9671 ins_pipe( fpu_reg_reg_mem ); |
| 9672 %} | |
| 9673 | |
| 9674 | |
|
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9675 // MACRO3 -- addDPR a mulDPR |
| 0 | 9676 // This instruction is a '2-address' instruction in that the result goes |
| 9677 // back to src2. This eliminates a move from the macro; possibly the | |
| 9678 // register allocator will have to add it back (and maybe not). | |
|
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9679 instruct addDPR_mulDPR_reg(regDPR src2, regDPR src1, regDPR src0) %{ |
| 0 | 9680 predicate( UseSSE<=1 ); |
| 9681 match(Set src2 (AddD (MulD src0 src1) src2)); | |
| 9682 format %{ "FLD $src0\t# ===MACRO3d===\n\t" | |
| 9683 "DMUL ST,$src1\n\t" | |
| 9684 "DADDp $src2,ST" %} | |
| 9685 ins_cost(250); | |
| 9686 opcode(0xDD); /* LoadD DD /0 */ | |
|
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9687 ins_encode( Push_Reg_FPR(src0), |
| 0 | 9688 FMul_ST_reg(src1), |
| 9689 FAddP_reg_ST(src2) ); | |
| 9690 ins_pipe( fpu_reg_reg_reg ); | |
| 9691 %} | |
| 9692 | |
| 9693 | |
|
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9694 // MACRO3 -- subDPR a mulDPR |
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9695 instruct subDPR_mulDPR_reg(regDPR src2, regDPR src1, regDPR src0) %{ |
| 0 | 9696 predicate( UseSSE<=1 ); |
| 9697 match(Set src2 (SubD (MulD src0 src1) src2)); | |
| 9698 format %{ "FLD $src0\t# ===MACRO3d===\n\t" | |
| 9699 "DMUL ST,$src1\n\t" | |
| 9700 "DSUBRp $src2,ST" %} | |
| 9701 ins_cost(250); | |
|
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9702 ins_encode( Push_Reg_FPR(src0), |
| 0 | 9703 FMul_ST_reg(src1), |
| 9704 Opcode(0xDE), Opc_plus(0xE0,src2)); | |
| 9705 ins_pipe( fpu_reg_reg_reg ); | |
| 9706 %} | |
| 9707 | |
| 9708 | |
|
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9709 instruct divDPR_reg(regDPR dst, regDPR src) %{ |
| 0 | 9710 predicate( UseSSE<=1 ); |
| 9711 match(Set dst (DivD dst src)); | |
| 9712 | |
| 9713 format %{ "FLD $src\n\t" | |
| 9714 "FDIVp $dst,ST" %} | |
| 9715 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/ | |
| 9716 ins_cost(150); | |
|
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9717 ins_encode( Push_Reg_DPR(src), |
| 0 | 9718 OpcP, RegOpc(dst) ); |
| 9719 ins_pipe( fpu_reg_reg ); | |
| 9720 %} | |
| 9721 | |
| 9722 // Strict FP instruction biases argument before division then | |
| 9723 // biases result, to avoid double rounding of subnormals. | |
| 9724 // | |
| 9725 // scale dividend by multiplying dividend by 2^(-15360) | |
| 9726 // load divisor | |
| 9727 // divide scaled dividend by divisor | |
| 9728 // rescale quotient by 2^(15360) | |
| 9729 // | |
|
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9730 instruct strictfp_divDPR_reg(regDPR1 dst, regnotDPR1 src) %{ |
| 0 | 9731 predicate (UseSSE<=1); |
| 9732 match(Set dst (DivD dst src)); | |
| 9733 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() ); | |
| 9734 ins_cost(01); | |
| 9735 | |
| 9736 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t" | |
| 9737 "DMULp $dst,ST\n\t" | |
| 9738 "FLD $src\n\t" | |
| 9739 "FDIVp $dst,ST\n\t" | |
| 9740 "FLD StubRoutines::_fpu_subnormal_bias2\n\t" | |
| 9741 "DMULp $dst,ST\n\t" %} | |
| 9742 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/ | |
| 9743 ins_encode( strictfp_bias1(dst), | |
|
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changeset
|
9744 Push_Reg_DPR(src), |
| 0 | 9745 OpcP, RegOpc(dst), |
| 9746 strictfp_bias2(dst) ); | |
| 9747 ins_pipe( fpu_reg_reg ); | |
| 9748 %} | |
| 9749 | |
|
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|
9750 instruct divDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{ |
| 0 | 9751 predicate( UseSSE<=1 && !(Compile::current()->has_method() && Compile::current()->method()->is_strict()) ); |
| 9752 match(Set dst (RoundDouble (DivD src1 src2))); | |
| 9753 | |
| 9754 format %{ "FLD $src1\n\t" | |
| 9755 "FDIV ST,$src2\n\t" | |
| 9756 "FSTP_D $dst\t# D-round" %} | |
| 9757 opcode(0xD8, 0x6); /* D8 F0+i or D8 /6 */ | |
|
4761
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changeset
|
9758 ins_encode( Push_Reg_DPR(src1), |
|
65149e74c706
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changeset
|
9759 OpcP, RegOpc(src2), Pop_Mem_DPR(dst) ); |
| 0 | 9760 ins_pipe( fpu_mem_reg_reg ); |
| 9761 %} | |
| 9762 | |
| 9763 | |
|
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|
9764 instruct modDPR_reg(regDPR dst, regDPR src, eAXRegI rax, eFlagsReg cr) %{ |
| 0 | 9765 predicate(UseSSE<=1); |
| 9766 match(Set dst (ModD dst src)); | |
|
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changeset
|
9767 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS |
| 0 | 9768 |
| 9769 format %{ "DMOD $dst,$src" %} | |
| 9770 ins_cost(250); | |
|
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changeset
|
9771 ins_encode(Push_Reg_Mod_DPR(dst, src), |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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diff
changeset
|
9772 emitModDPR(), |
|
65149e74c706
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diff
changeset
|
9773 Push_Result_Mod_DPR(src), |
|
65149e74c706
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changeset
|
9774 Pop_Reg_DPR(dst)); |
|
65149e74c706
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changeset
|
9775 ins_pipe( pipe_slow ); |
|
65149e74c706
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changeset
|
9776 %} |
|
65149e74c706
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changeset
|
9777 |
|
65149e74c706
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changeset
|
9778 instruct modD_reg(regD dst, regD src0, regD src1, eAXRegI rax, eFlagsReg cr) %{ |
| 0 | 9779 predicate(UseSSE>=2); |
| 9780 match(Set dst (ModD src0 src1)); | |
| 9781 effect(KILL rax, KILL cr); | |
| 9782 | |
| 9783 format %{ "SUB ESP,8\t # DMOD\n" | |
| 9784 "\tMOVSD [ESP+0],$src1\n" | |
| 9785 "\tFLD_D [ESP+0]\n" | |
| 9786 "\tMOVSD [ESP+0],$src0\n" | |
| 9787 "\tFLD_D [ESP+0]\n" | |
| 9788 "loop:\tFPREM\n" | |
| 9789 "\tFWAIT\n" | |
| 9790 "\tFNSTSW AX\n" | |
| 9791 "\tSAHF\n" | |
| 9792 "\tJP loop\n" | |
| 9793 "\tFSTP_D [ESP+0]\n" | |
| 9794 "\tMOVSD $dst,[ESP+0]\n" | |
| 9795 "\tADD ESP,8\n" | |
| 9796 "\tFSTP ST0\t # Restore FPU Stack" | |
| 9797 %} | |
| 9798 ins_cost(250); | |
|
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|
9799 ins_encode( Push_ModD_encoding(src0, src1), emitModDPR(), Push_ResultD(dst), PopFPU); |
|
65149e74c706
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|
9800 ins_pipe( pipe_slow ); |
|
65149e74c706
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diff
changeset
|
9801 %} |
|
65149e74c706
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diff
changeset
|
9802 |
|
65149e74c706
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changeset
|
9803 instruct sinDPR_reg(regDPR1 dst, regDPR1 src) %{ |
| 0 | 9804 predicate (UseSSE<=1); |
| 9805 match(Set dst (SinD src)); | |
| 9806 ins_cost(1800); | |
| 9807 format %{ "DSIN $dst" %} | |
| 9808 opcode(0xD9, 0xFE); | |
| 9809 ins_encode( OpcP, OpcS ); | |
| 9810 ins_pipe( pipe_slow ); | |
| 9811 %} | |
| 9812 | |
|
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changeset
|
9813 instruct sinD_reg(regD dst, eFlagsReg cr) %{ |
| 0 | 9814 predicate (UseSSE>=2); |
| 9815 match(Set dst (SinD dst)); | |
|
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|
9816 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8" |
| 0 | 9817 ins_cost(1800); |
| 9818 format %{ "DSIN $dst" %} | |
| 9819 opcode(0xD9, 0xFE); | |
|
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changeset
|
9820 ins_encode( Push_SrcD(dst), OpcP, OpcS, Push_ResultD(dst) ); |
|
65149e74c706
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changeset
|
9821 ins_pipe( pipe_slow ); |
|
65149e74c706
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kvn
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diff
changeset
|
9822 %} |
|
65149e74c706
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diff
changeset
|
9823 |
|
65149e74c706
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diff
changeset
|
9824 instruct cosDPR_reg(regDPR1 dst, regDPR1 src) %{ |
| 0 | 9825 predicate (UseSSE<=1); |
| 9826 match(Set dst (CosD src)); | |
| 9827 ins_cost(1800); | |
| 9828 format %{ "DCOS $dst" %} | |
| 9829 opcode(0xD9, 0xFF); | |
| 9830 ins_encode( OpcP, OpcS ); | |
| 9831 ins_pipe( pipe_slow ); | |
| 9832 %} | |
| 9833 | |
|
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changeset
|
9834 instruct cosD_reg(regD dst, eFlagsReg cr) %{ |
| 0 | 9835 predicate (UseSSE>=2); |
| 9836 match(Set dst (CosD dst)); | |
|
4761
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changeset
|
9837 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8" |
| 0 | 9838 ins_cost(1800); |
| 9839 format %{ "DCOS $dst" %} | |
| 9840 opcode(0xD9, 0xFF); | |
|
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diff
changeset
|
9841 ins_encode( Push_SrcD(dst), OpcP, OpcS, Push_ResultD(dst) ); |
|
65149e74c706
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diff
changeset
|
9842 ins_pipe( pipe_slow ); |
|
65149e74c706
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diff
changeset
|
9843 %} |
|
65149e74c706
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diff
changeset
|
9844 |
|
65149e74c706
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diff
changeset
|
9845 instruct tanDPR_reg(regDPR1 dst, regDPR1 src) %{ |
| 0 | 9846 predicate (UseSSE<=1); |
| 9847 match(Set dst(TanD src)); | |
| 9848 format %{ "DTAN $dst" %} | |
| 9849 ins_encode( Opcode(0xD9), Opcode(0xF2), // fptan | |
| 9850 Opcode(0xDD), Opcode(0xD8)); // fstp st | |
| 9851 ins_pipe( pipe_slow ); | |
| 9852 %} | |
| 9853 | |
|
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changeset
|
9854 instruct tanD_reg(regD dst, eFlagsReg cr) %{ |
| 0 | 9855 predicate (UseSSE>=2); |
| 9856 match(Set dst(TanD dst)); | |
|
4761
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changeset
|
9857 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8" |
| 0 | 9858 format %{ "DTAN $dst" %} |
|
4761
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changeset
|
9859 ins_encode( Push_SrcD(dst), |
| 0 | 9860 Opcode(0xD9), Opcode(0xF2), // fptan |
| 9861 Opcode(0xDD), Opcode(0xD8), // fstp st | |
|
4761
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changeset
|
9862 Push_ResultD(dst) ); |
|
65149e74c706
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kvn
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changeset
|
9863 ins_pipe( pipe_slow ); |
|
65149e74c706
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kvn
parents:
4759
diff
changeset
|
9864 %} |
|
65149e74c706
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kvn
parents:
4759
diff
changeset
|
9865 |
|
65149e74c706
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diff
changeset
|
9866 instruct atanDPR_reg(regDPR dst, regDPR src) %{ |
| 0 | 9867 predicate (UseSSE<=1); |
| 9868 match(Set dst(AtanD dst src)); | |
| 9869 format %{ "DATA $dst,$src" %} | |
| 9870 opcode(0xD9, 0xF3); | |
|
4761
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diff
changeset
|
9871 ins_encode( Push_Reg_DPR(src), |
| 0 | 9872 OpcP, OpcS, RegOpc(dst) ); |
| 9873 ins_pipe( pipe_slow ); | |
| 9874 %} | |
| 9875 | |
|
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changeset
|
9876 instruct atanD_reg(regD dst, regD src, eFlagsReg cr) %{ |
| 0 | 9877 predicate (UseSSE>=2); |
| 9878 match(Set dst(AtanD dst src)); | |
|
4761
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4759
diff
changeset
|
9879 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8" |
| 0 | 9880 format %{ "DATA $dst,$src" %} |
| 9881 opcode(0xD9, 0xF3); | |
|
4761
65149e74c706
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diff
changeset
|
9882 ins_encode( Push_SrcD(src), |
|
65149e74c706
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4759
diff
changeset
|
9883 OpcP, OpcS, Push_ResultD(dst) ); |
|
65149e74c706
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4759
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changeset
|
9884 ins_pipe( pipe_slow ); |
|
65149e74c706
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kvn
parents:
4759
diff
changeset
|
9885 %} |
|
65149e74c706
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kvn
parents:
4759
diff
changeset
|
9886 |
|
65149e74c706
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parents:
4759
diff
changeset
|
9887 instruct sqrtDPR_reg(regDPR dst, regDPR src) %{ |
| 0 | 9888 predicate (UseSSE<=1); |
| 9889 match(Set dst (SqrtD src)); | |
| 9890 format %{ "DSQRT $dst,$src" %} | |
| 9891 opcode(0xFA, 0xD9); | |
|
4761
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4759
diff
changeset
|
9892 ins_encode( Push_Reg_DPR(src), |
|
65149e74c706
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changeset
|
9893 OpcS, OpcP, Pop_Reg_DPR(dst) ); |
|
65149e74c706
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kvn
parents:
4759
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changeset
|
9894 ins_pipe( pipe_slow ); |
|
65149e74c706
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kvn
parents:
4759
diff
changeset
|
9895 %} |
|
65149e74c706
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kvn
parents:
4759
diff
changeset
|
9896 |
|
6084
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9897 instruct powDPR_reg(regDPR X, regDPR1 Y, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{ |
| 0 | 9898 predicate (UseSSE<=1); |
| 9899 match(Set Y (PowD X Y)); // Raise X to the Yth power | |
|
6084
6759698e3140
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roland
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5934
diff
changeset
|
9900 effect(KILL rax, KILL rdx, KILL rcx, KILL cr); |
|
6759698e3140
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roland
parents:
5934
diff
changeset
|
9901 format %{ "fast_pow $X $Y -> $Y // KILL $rax, $rcx, $rdx" %} |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9902 ins_encode %{ |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9903 __ subptr(rsp, 8); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
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5934
diff
changeset
|
9904 __ fld_s($X$$reg - 1); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9905 __ fast_pow(); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9906 __ addptr(rsp, 8); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9907 %} |
|
6759698e3140
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roland
parents:
5934
diff
changeset
|
9908 ins_pipe( pipe_slow ); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9909 %} |
|
6759698e3140
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roland
parents:
5934
diff
changeset
|
9910 |
|
6759698e3140
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roland
parents:
5934
diff
changeset
|
9911 instruct powD_reg(regD dst, regD src0, regD src1, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{ |
| 0 | 9912 predicate (UseSSE>=2); |
| 9913 match(Set dst (PowD src0 src1)); // Raise src0 to the src1'th power | |
|
6084
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roland
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diff
changeset
|
9914 effect(KILL rax, KILL rdx, KILL rcx, KILL cr); |
|
6759698e3140
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roland
parents:
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diff
changeset
|
9915 format %{ "fast_pow $src0 $src1 -> $dst // KILL $rax, $rcx, $rdx" %} |
|
6759698e3140
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roland
parents:
5934
diff
changeset
|
9916 ins_encode %{ |
|
6759698e3140
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roland
parents:
5934
diff
changeset
|
9917 __ subptr(rsp, 8); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9918 __ movdbl(Address(rsp, 0), $src1$$XMMRegister); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
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5934
diff
changeset
|
9919 __ fld_d(Address(rsp, 0)); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
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5934
diff
changeset
|
9920 __ movdbl(Address(rsp, 0), $src0$$XMMRegister); |
|
6759698e3140
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roland
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5934
diff
changeset
|
9921 __ fld_d(Address(rsp, 0)); |
|
6759698e3140
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roland
parents:
5934
diff
changeset
|
9922 __ fast_pow(); |
|
6759698e3140
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parents:
5934
diff
changeset
|
9923 __ fstp_d(Address(rsp, 0)); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
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diff
changeset
|
9924 __ movdbl($dst$$XMMRegister, Address(rsp, 0)); |
|
6759698e3140
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roland
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5934
diff
changeset
|
9925 __ addptr(rsp, 8); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9926 %} |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9927 ins_pipe( pipe_slow ); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9928 %} |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9929 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9930 |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9931 instruct expDPR_reg(regDPR1 dpr1, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{ |
| 0 | 9932 predicate (UseSSE<=1); |
| 9933 match(Set dpr1 (ExpD dpr1)); | |
|
6084
6759698e3140
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roland
parents:
5934
diff
changeset
|
9934 effect(KILL rax, KILL rcx, KILL rdx, KILL cr); |
|
6759698e3140
7133857: exp() and pow() should use the x87 ISA on x86
roland
parents:
5934
diff
changeset
|
9935 format %{ "fast_exp $dpr1 -> $dpr1 // KILL $rax, $rcx, $rdx" %} |
|
6759698e3140
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5934
diff
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|
9936 ins_encode %{ |
|
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5934
diff
changeset
|
9937 __ fast_exp(); |
|
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5934
diff
changeset
|
9938 %} |
|
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5934
diff
changeset
|
9939 ins_pipe( pipe_slow ); |
|
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roland
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5934
diff
changeset
|
9940 %} |
|
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diff
changeset
|
9941 |
|
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diff
changeset
|
9942 instruct expD_reg(regD dst, regD src, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{ |
| 0 | 9943 predicate (UseSSE>=2); |
| 9944 match(Set dst (ExpD src)); | |
|
6084
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diff
changeset
|
9945 effect(KILL rax, KILL rcx, KILL rdx, KILL cr); |
|
6759698e3140
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roland
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changeset
|
9946 format %{ "fast_exp $dst -> $src // KILL $rax, $rcx, $rdx" %} |
|
6759698e3140
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roland
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5934
diff
changeset
|
9947 ins_encode %{ |
|
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diff
changeset
|
9948 __ subptr(rsp, 8); |
|
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diff
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|
9949 __ movdbl(Address(rsp, 0), $src$$XMMRegister); |
|
6759698e3140
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diff
changeset
|
9950 __ fld_d(Address(rsp, 0)); |
|
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5934
diff
changeset
|
9951 __ fast_exp(); |
|
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5934
diff
changeset
|
9952 __ fstp_d(Address(rsp, 0)); |
|
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diff
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|
9953 __ movdbl($dst$$XMMRegister, Address(rsp, 0)); |
|
6759698e3140
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|
9954 __ addptr(rsp, 8); |
|
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diff
changeset
|
9955 %} |
|
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changeset
|
9956 ins_pipe( pipe_slow ); |
|
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diff
changeset
|
9957 %} |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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diff
changeset
|
9958 |
|
65149e74c706
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changeset
|
9959 instruct log10DPR_reg(regDPR1 dst, regDPR1 src) %{ |
| 0 | 9960 predicate (UseSSE<=1); |
| 9961 // The source Double operand on FPU stack | |
| 9962 match(Set dst (Log10D src)); | |
| 9963 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number | |
| 9964 // fxch ; swap ST(0) with ST(1) | |
| 9965 // fyl2x ; compute log_10(2) * log_2(x) | |
| 9966 format %{ "FLDLG2 \t\t\t#Log10\n\t" | |
| 9967 "FXCH \n\t" | |
| 9968 "FYL2X \t\t\t# Q=Log10*Log_2(x)" | |
| 9969 %} | |
| 9970 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2 | |
| 9971 Opcode(0xD9), Opcode(0xC9), // fxch | |
| 9972 Opcode(0xD9), Opcode(0xF1)); // fyl2x | |
| 9973 | |
| 9974 ins_pipe( pipe_slow ); | |
| 9975 %} | |
| 9976 | |
|
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changeset
|
9977 instruct log10D_reg(regD dst, regD src, eFlagsReg cr) %{ |
| 0 | 9978 predicate (UseSSE>=2); |
| 9979 effect(KILL cr); | |
| 9980 match(Set dst (Log10D src)); | |
| 9981 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number | |
| 9982 // fyl2x ; compute log_10(2) * log_2(x) | |
| 9983 format %{ "FLDLG2 \t\t\t#Log10\n\t" | |
| 9984 "FYL2X \t\t\t# Q=Log10*Log_2(x)" | |
| 9985 %} | |
| 9986 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2 | |
|
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changeset
|
9987 Push_SrcD(src), |
| 0 | 9988 Opcode(0xD9), Opcode(0xF1), // fyl2x |
|
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|
9989 Push_ResultD(dst)); |
|
65149e74c706
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diff
changeset
|
9990 |
|
65149e74c706
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diff
changeset
|
9991 ins_pipe( pipe_slow ); |
|
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diff
changeset
|
9992 %} |
|
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diff
changeset
|
9993 |
|
65149e74c706
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changeset
|
9994 instruct logDPR_reg(regDPR1 dst, regDPR1 src) %{ |
| 0 | 9995 predicate (UseSSE<=1); |
| 9996 // The source Double operand on FPU stack | |
| 9997 match(Set dst (LogD src)); | |
| 9998 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number | |
| 9999 // fxch ; swap ST(0) with ST(1) | |
| 10000 // fyl2x ; compute log_e(2) * log_2(x) | |
| 10001 format %{ "FLDLN2 \t\t\t#Log_e\n\t" | |
| 10002 "FXCH \n\t" | |
| 10003 "FYL2X \t\t\t# Q=Log_e*Log_2(x)" | |
| 10004 %} | |
| 10005 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2 | |
| 10006 Opcode(0xD9), Opcode(0xC9), // fxch | |
| 10007 Opcode(0xD9), Opcode(0xF1)); // fyl2x | |
| 10008 | |
| 10009 ins_pipe( pipe_slow ); | |
| 10010 %} | |
| 10011 | |
|
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|
10012 instruct logD_reg(regD dst, regD src, eFlagsReg cr) %{ |
| 0 | 10013 predicate (UseSSE>=2); |
| 10014 effect(KILL cr); | |
| 10015 // The source and result Double operands in XMM registers | |
| 10016 match(Set dst (LogD src)); | |
| 10017 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number | |
| 10018 // fyl2x ; compute log_e(2) * log_2(x) | |
| 10019 format %{ "FLDLN2 \t\t\t#Log_e\n\t" | |
| 10020 "FYL2X \t\t\t# Q=Log_e*Log_2(x)" | |
| 10021 %} | |
| 10022 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2 | |
|
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|
10023 Push_SrcD(src), |
| 0 | 10024 Opcode(0xD9), Opcode(0xF1), // fyl2x |
|
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|
10025 Push_ResultD(dst)); |
| 0 | 10026 ins_pipe( pipe_slow ); |
| 10027 %} | |
| 10028 | |
| 10029 //-------------Float Instructions------------------------------- | |
| 10030 // Float Math | |
| 10031 | |
| 10032 // Code for float compare: | |
| 10033 // fcompp(); | |
| 10034 // fwait(); fnstsw_ax(); | |
| 10035 // sahf(); | |
| 10036 // movl(dst, unordered_result); | |
| 10037 // jcc(Assembler::parity, exit); | |
| 10038 // movl(dst, less_result); | |
| 10039 // jcc(Assembler::below, exit); | |
| 10040 // movl(dst, equal_result); | |
| 10041 // jcc(Assembler::equal, exit); | |
| 10042 // movl(dst, greater_result); | |
| 10043 // exit: | |
| 10044 | |
| 10045 // P6 version of float compare, sets condition codes in EFLAGS | |
|
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|
10046 instruct cmpFPR_cc_P6(eFlagsRegU cr, regFPR src1, regFPR src2, eAXRegI rax) %{ |
| 0 | 10047 predicate(VM_Version::supports_cmov() && UseSSE == 0); |
| 10048 match(Set cr (CmpF src1 src2)); | |
| 10049 effect(KILL rax); | |
| 10050 ins_cost(150); | |
| 10051 format %{ "FLD $src1\n\t" | |
| 10052 "FUCOMIP ST,$src2 // P6 instruction\n\t" | |
| 10053 "JNP exit\n\t" | |
| 10054 "MOV ah,1 // saw a NaN, set CF (treat as LT)\n\t" | |
| 10055 "SAHF\n" | |
| 10056 "exit:\tNOP // avoid branch to branch" %} | |
| 10057 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */ | |
|
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diff
changeset
|
10058 ins_encode( Push_Reg_DPR(src1), |
| 0 | 10059 OpcP, RegOpc(src2), |
| 10060 cmpF_P6_fixup ); | |
| 10061 ins_pipe( pipe_slow ); | |
| 10062 %} | |
| 10063 | |
|
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|
10064 instruct cmpFPR_cc_P6CF(eFlagsRegUCF cr, regFPR src1, regFPR src2) %{ |
|
415
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changeset
|
10065 predicate(VM_Version::supports_cmov() && UseSSE == 0); |
|
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changeset
|
10066 match(Set cr (CmpF src1 src2)); |
|
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parents:
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diff
changeset
|
10067 ins_cost(100); |
|
4d9884b01ba6
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diff
changeset
|
10068 format %{ "FLD $src1\n\t" |
|
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diff
changeset
|
10069 "FUCOMIP ST,$src2 // P6 instruction" %} |
|
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parents:
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diff
changeset
|
10070 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */ |
|
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|
10071 ins_encode( Push_Reg_DPR(src1), |
|
415
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changeset
|
10072 OpcP, RegOpc(src2)); |
|
4d9884b01ba6
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parents:
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diff
changeset
|
10073 ins_pipe( pipe_slow ); |
|
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parents:
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diff
changeset
|
10074 %} |
|
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diff
changeset
|
10075 |
| 0 | 10076 |
| 10077 // Compare & branch | |
|
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|
10078 instruct cmpFPR_cc(eFlagsRegU cr, regFPR src1, regFPR src2, eAXRegI rax) %{ |
| 0 | 10079 predicate(UseSSE == 0); |
| 10080 match(Set cr (CmpF src1 src2)); | |
| 10081 effect(KILL rax); | |
| 10082 ins_cost(200); | |
| 10083 format %{ "FLD $src1\n\t" | |
| 10084 "FCOMp $src2\n\t" | |
| 10085 "FNSTSW AX\n\t" | |
| 10086 "TEST AX,0x400\n\t" | |
| 10087 "JZ,s flags\n\t" | |
| 10088 "MOV AH,1\t# unordered treat as LT\n" | |
| 10089 "flags:\tSAHF" %} | |
| 10090 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */ | |
|
4761
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7121648: Use 3-operands SIMD instructions on x86 with AVX
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changeset
|
10091 ins_encode( Push_Reg_DPR(src1), |
| 0 | 10092 OpcP, RegOpc(src2), |
| 10093 fpu_flags); | |
| 10094 ins_pipe( pipe_slow ); | |
| 10095 %} | |
| 10096 | |
| 10097 // Compare vs zero into -1,0,1 | |
|
6179
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changeset
|
10098 instruct cmpFPR_0(rRegI dst, regFPR src1, immFPR0 zero, eAXRegI rax, eFlagsReg cr) %{ |
| 0 | 10099 predicate(UseSSE == 0); |
| 10100 match(Set dst (CmpF3 src1 zero)); | |
| 10101 effect(KILL cr, KILL rax); | |
| 10102 ins_cost(280); | |
| 10103 format %{ "FTSTF $dst,$src1" %} | |
| 10104 opcode(0xE4, 0xD9); | |
|
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changeset
|
10105 ins_encode( Push_Reg_DPR(src1), |
| 0 | 10106 OpcS, OpcP, PopFPU, |
| 10107 CmpF_Result(dst)); | |
| 10108 ins_pipe( pipe_slow ); | |
| 10109 %} | |
| 10110 | |
| 10111 // Compare into -1,0,1 | |
|
6179
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|
10112 instruct cmpFPR_reg(rRegI dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{ |
| 0 | 10113 predicate(UseSSE == 0); |
| 10114 match(Set dst (CmpF3 src1 src2)); | |
| 10115 effect(KILL cr, KILL rax); | |
| 10116 ins_cost(300); | |
| 10117 format %{ "FCMPF $dst,$src1,$src2" %} | |
| 10118 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */ | |
|
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changeset
|
10119 ins_encode( Push_Reg_DPR(src1), |
| 0 | 10120 OpcP, RegOpc(src2), |
| 10121 CmpF_Result(dst)); | |
| 10122 ins_pipe( pipe_slow ); | |
| 10123 %} | |
| 10124 | |
| 10125 // float compare and set condition codes in EFLAGS by XMM regs | |
|
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|
10126 instruct cmpF_cc(eFlagsRegU cr, regF src1, regF src2) %{ |
| 0 | 10127 predicate(UseSSE>=1); |
| 4759 | 10128 match(Set cr (CmpF src1 src2)); |
| 0 | 10129 ins_cost(145); |
| 4759 | 10130 format %{ "UCOMISS $src1,$src2\n\t" |
| 10131 "JNP,s exit\n\t" | |
| 10132 "PUSHF\t# saw NaN, set CF\n\t" | |
| 10133 "AND [rsp], #0xffffff2b\n\t" | |
| 10134 "POPF\n" | |
| 10135 "exit:" %} | |
| 10136 ins_encode %{ | |
| 10137 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister); | |
| 10138 emit_cmpfp_fixup(_masm); | |
| 10139 %} | |
| 10140 ins_pipe( pipe_slow ); | |
| 10141 %} | |
| 10142 | |
|
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|
10143 instruct cmpF_ccCF(eFlagsRegUCF cr, regF src1, regF src2) %{ |
|
415
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diff
changeset
|
10144 predicate(UseSSE>=1); |
| 4759 | 10145 match(Set cr (CmpF src1 src2)); |
|
415
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parents:
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diff
changeset
|
10146 ins_cost(100); |
| 4759 | 10147 format %{ "UCOMISS $src1,$src2" %} |
| 10148 ins_encode %{ | |
| 10149 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister); | |
| 10150 %} | |
|
415
4d9884b01ba6
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parents:
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diff
changeset
|
10151 ins_pipe( pipe_slow ); |
|
4d9884b01ba6
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parents:
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diff
changeset
|
10152 %} |
|
4d9884b01ba6
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parents:
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diff
changeset
|
10153 |
| 0 | 10154 // float compare and set condition codes in EFLAGS by XMM regs |
|
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|
10155 instruct cmpF_ccmem(eFlagsRegU cr, regF src1, memory src2) %{ |
| 0 | 10156 predicate(UseSSE>=1); |
| 4759 | 10157 match(Set cr (CmpF src1 (LoadF src2))); |
| 0 | 10158 ins_cost(165); |
| 4759 | 10159 format %{ "UCOMISS $src1,$src2\n\t" |
| 10160 "JNP,s exit\n\t" | |
| 10161 "PUSHF\t# saw NaN, set CF\n\t" | |
| 10162 "AND [rsp], #0xffffff2b\n\t" | |
| 10163 "POPF\n" | |
| 10164 "exit:" %} | |
| 10165 ins_encode %{ | |
| 10166 __ ucomiss($src1$$XMMRegister, $src2$$Address); | |
| 10167 emit_cmpfp_fixup(_masm); | |
| 10168 %} | |
| 10169 ins_pipe( pipe_slow ); | |
| 10170 %} | |
| 10171 | |
|
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changeset
|
10172 instruct cmpF_ccmemCF(eFlagsRegUCF cr, regF src1, memory src2) %{ |
|
415
4d9884b01ba6
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never
parents:
403
diff
changeset
|
10173 predicate(UseSSE>=1); |
| 4759 | 10174 match(Set cr (CmpF src1 (LoadF src2))); |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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parents:
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diff
changeset
|
10175 ins_cost(100); |
| 4759 | 10176 format %{ "UCOMISS $src1,$src2" %} |
| 10177 ins_encode %{ | |
| 10178 __ ucomiss($src1$$XMMRegister, $src2$$Address); | |
| 10179 %} | |
|
415
4d9884b01ba6
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parents:
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diff
changeset
|
10180 ins_pipe( pipe_slow ); |
|
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parents:
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diff
changeset
|
10181 %} |
|
4d9884b01ba6
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parents:
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diff
changeset
|
10182 |
| 0 | 10183 // Compare into -1,0,1 in XMM |
|
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10184 instruct cmpF_reg(xRegI dst, regF src1, regF src2, eFlagsReg cr) %{ |
| 0 | 10185 predicate(UseSSE>=1); |
| 10186 match(Set dst (CmpF3 src1 src2)); | |
| 10187 effect(KILL cr); | |
| 10188 ins_cost(255); | |
| 4759 | 10189 format %{ "UCOMISS $src1, $src2\n\t" |
| 10190 "MOV $dst, #-1\n\t" | |
| 10191 "JP,s done\n\t" | |
| 10192 "JB,s done\n\t" | |
| 10193 "SETNE $dst\n\t" | |
| 10194 "MOVZB $dst, $dst\n" | |
| 10195 "done:" %} | |
| 10196 ins_encode %{ | |
| 10197 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister); | |
| 10198 emit_cmpfp3(_masm, $dst$$Register); | |
| 10199 %} | |
| 0 | 10200 ins_pipe( pipe_slow ); |
| 10201 %} | |
| 10202 | |
| 10203 // Compare into -1,0,1 in XMM and memory | |
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10204 instruct cmpF_regmem(xRegI dst, regF src1, memory src2, eFlagsReg cr) %{ |
| 0 | 10205 predicate(UseSSE>=1); |
| 4759 | 10206 match(Set dst (CmpF3 src1 (LoadF src2))); |
| 0 | 10207 effect(KILL cr); |
| 10208 ins_cost(275); | |
| 4759 | 10209 format %{ "UCOMISS $src1, $src2\n\t" |
| 10210 "MOV $dst, #-1\n\t" | |
| 10211 "JP,s done\n\t" | |
| 10212 "JB,s done\n\t" | |
| 10213 "SETNE $dst\n\t" | |
| 10214 "MOVZB $dst, $dst\n" | |
| 10215 "done:" %} | |
| 10216 ins_encode %{ | |
| 10217 __ ucomiss($src1$$XMMRegister, $src2$$Address); | |
| 10218 emit_cmpfp3(_masm, $dst$$Register); | |
| 10219 %} | |
| 0 | 10220 ins_pipe( pipe_slow ); |
| 10221 %} | |
| 10222 | |
| 10223 // Spill to obtain 24-bit precision | |
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10224 instruct subFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{ |
| 0 | 10225 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10226 match(Set dst (SubF src1 src2)); | |
| 10227 | |
| 10228 format %{ "FSUB $dst,$src1 - $src2" %} | |
| 10229 opcode(0xD8, 0x4); /* D8 E0+i or D8 /4 mod==0x3 ;; result in TOS */ | |
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10230 ins_encode( Push_Reg_FPR(src1), |
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10231 OpcReg_FPR(src2), |
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10232 Pop_Mem_FPR(dst) ); |
| 0 | 10233 ins_pipe( fpu_mem_reg_reg ); |
| 10234 %} | |
| 10235 // | |
| 10236 // This instruction does not round to 24-bits | |
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10237 instruct subFPR_reg(regFPR dst, regFPR src) %{ |
| 0 | 10238 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10239 match(Set dst (SubF dst src)); | |
| 10240 | |
| 10241 format %{ "FSUB $dst,$src" %} | |
| 10242 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */ | |
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10243 ins_encode( Push_Reg_FPR(src), |
| 0 | 10244 OpcP, RegOpc(dst) ); |
| 10245 ins_pipe( fpu_reg_reg ); | |
| 10246 %} | |
| 10247 | |
| 10248 // Spill to obtain 24-bit precision | |
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10249 instruct addFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{ |
| 0 | 10250 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10251 match(Set dst (AddF src1 src2)); | |
| 10252 | |
| 10253 format %{ "FADD $dst,$src1,$src2" %} | |
| 10254 opcode(0xD8, 0x0); /* D8 C0+i */ | |
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10255 ins_encode( Push_Reg_FPR(src2), |
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10256 OpcReg_FPR(src1), |
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10257 Pop_Mem_FPR(dst) ); |
| 0 | 10258 ins_pipe( fpu_mem_reg_reg ); |
| 10259 %} | |
| 10260 // | |
| 10261 // This instruction does not round to 24-bits | |
|
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10262 instruct addFPR_reg(regFPR dst, regFPR src) %{ |
| 0 | 10263 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10264 match(Set dst (AddF dst src)); | |
| 10265 | |
| 10266 format %{ "FLD $src\n\t" | |
| 10267 "FADDp $dst,ST" %} | |
| 10268 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/ | |
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10269 ins_encode( Push_Reg_FPR(src), |
| 0 | 10270 OpcP, RegOpc(dst) ); |
| 10271 ins_pipe( fpu_reg_reg ); | |
| 10272 %} | |
| 10273 | |
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10274 instruct absFPR_reg(regFPR1 dst, regFPR1 src) %{ |
| 0 | 10275 predicate(UseSSE==0); |
| 10276 match(Set dst (AbsF src)); | |
| 10277 ins_cost(100); | |
| 10278 format %{ "FABS" %} | |
| 10279 opcode(0xE1, 0xD9); | |
| 10280 ins_encode( OpcS, OpcP ); | |
| 10281 ins_pipe( fpu_reg_reg ); | |
| 10282 %} | |
| 10283 | |
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10284 instruct negFPR_reg(regFPR1 dst, regFPR1 src) %{ |
| 0 | 10285 predicate(UseSSE==0); |
| 10286 match(Set dst (NegF src)); | |
| 10287 ins_cost(100); | |
| 10288 format %{ "FCHS" %} | |
| 10289 opcode(0xE0, 0xD9); | |
| 10290 ins_encode( OpcS, OpcP ); | |
| 10291 ins_pipe( fpu_reg_reg ); | |
| 10292 %} | |
| 10293 | |
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10294 // Cisc-alternate to addFPR_reg |
| 0 | 10295 // Spill to obtain 24-bit precision |
|
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10296 instruct addFPR24_reg_mem(stackSlotF dst, regFPR src1, memory src2) %{ |
| 0 | 10297 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10298 match(Set dst (AddF src1 (LoadF src2))); | |
| 10299 | |
| 10300 format %{ "FLD $src2\n\t" | |
| 10301 "FADD ST,$src1\n\t" | |
| 10302 "FSTP_S $dst" %} | |
| 10303 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */ | |
| 10304 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), | |
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10305 OpcReg_FPR(src1), |
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10306 Pop_Mem_FPR(dst) ); |
| 0 | 10307 ins_pipe( fpu_mem_reg_mem ); |
| 10308 %} | |
| 10309 // | |
|
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10310 // Cisc-alternate to addFPR_reg |
| 0 | 10311 // This instruction does not round to 24-bits |
|
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10312 instruct addFPR_reg_mem(regFPR dst, memory src) %{ |
| 0 | 10313 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10314 match(Set dst (AddF dst (LoadF src))); | |
| 10315 | |
| 10316 format %{ "FADD $dst,$src" %} | |
| 10317 opcode(0xDE, 0x0, 0xD9); /* DE C0+i or DE /0*/ /* LoadF D9 /0 */ | |
| 10318 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src), | |
| 10319 OpcP, RegOpc(dst) ); | |
| 10320 ins_pipe( fpu_reg_mem ); | |
| 10321 %} | |
| 10322 | |
| 10323 // // Following two instructions for _222_mpegaudio | |
| 10324 // Spill to obtain 24-bit precision | |
|
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10325 instruct addFPR24_mem_reg(stackSlotF dst, regFPR src2, memory src1 ) %{ |
| 0 | 10326 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10327 match(Set dst (AddF src1 src2)); | |
| 10328 | |
| 10329 format %{ "FADD $dst,$src1,$src2" %} | |
| 10330 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */ | |
| 10331 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src1), | |
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10332 OpcReg_FPR(src2), |
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10333 Pop_Mem_FPR(dst) ); |
| 0 | 10334 ins_pipe( fpu_mem_reg_mem ); |
| 10335 %} | |
| 10336 | |
| 10337 // Cisc-spill variant | |
| 10338 // Spill to obtain 24-bit precision | |
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10339 instruct addFPR24_mem_cisc(stackSlotF dst, memory src1, memory src2) %{ |
| 0 | 10340 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10341 match(Set dst (AddF src1 (LoadF src2))); | |
| 10342 | |
| 10343 format %{ "FADD $dst,$src1,$src2 cisc" %} | |
| 10344 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */ | |
| 10345 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), | |
| 10346 set_instruction_start, | |
| 10347 OpcP, RMopc_Mem(secondary,src1), | |
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10348 Pop_Mem_FPR(dst) ); |
| 0 | 10349 ins_pipe( fpu_mem_mem_mem ); |
| 10350 %} | |
| 10351 | |
| 10352 // Spill to obtain 24-bit precision | |
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10353 instruct addFPR24_mem_mem(stackSlotF dst, memory src1, memory src2) %{ |
| 0 | 10354 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10355 match(Set dst (AddF src1 src2)); | |
| 10356 | |
| 10357 format %{ "FADD $dst,$src1,$src2" %} | |
| 10358 opcode(0xD8, 0x0, 0xD9); /* D8 /0 */ /* LoadF D9 /0 */ | |
| 10359 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), | |
| 10360 set_instruction_start, | |
| 10361 OpcP, RMopc_Mem(secondary,src1), | |
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10362 Pop_Mem_FPR(dst) ); |
| 0 | 10363 ins_pipe( fpu_mem_mem_mem ); |
| 10364 %} | |
| 10365 | |
| 10366 | |
| 10367 // Spill to obtain 24-bit precision | |
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10368 instruct addFPR24_reg_imm(stackSlotF dst, regFPR src, immFPR con) %{ |
| 0 | 10369 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 2008 | 10370 match(Set dst (AddF src con)); |
| 10371 format %{ "FLD $src\n\t" | |
| 10372 "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t" | |
| 0 | 10373 "FSTP_S $dst" %} |
| 2008 | 10374 ins_encode %{ |
| 10375 __ fld_s($src$$reg - 1); // FLD ST(i-1) | |
| 10376 __ fadd_s($constantaddress($con)); | |
| 10377 __ fstp_s(Address(rsp, $dst$$disp)); | |
| 10378 %} | |
| 10379 ins_pipe(fpu_mem_reg_con); | |
| 0 | 10380 %} |
| 10381 // | |
| 10382 // This instruction does not round to 24-bits | |
|
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10383 instruct addFPR_reg_imm(regFPR dst, regFPR src, immFPR con) %{ |
| 0 | 10384 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 2008 | 10385 match(Set dst (AddF src con)); |
| 10386 format %{ "FLD $src\n\t" | |
| 10387 "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t" | |
| 10388 "FSTP $dst" %} | |
| 10389 ins_encode %{ | |
| 10390 __ fld_s($src$$reg - 1); // FLD ST(i-1) | |
| 10391 __ fadd_s($constantaddress($con)); | |
| 10392 __ fstp_d($dst$$reg); | |
| 10393 %} | |
| 10394 ins_pipe(fpu_reg_reg_con); | |
| 0 | 10395 %} |
| 10396 | |
| 10397 // Spill to obtain 24-bit precision | |
|
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10398 instruct mulFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{ |
| 0 | 10399 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10400 match(Set dst (MulF src1 src2)); | |
| 10401 | |
| 10402 format %{ "FLD $src1\n\t" | |
| 10403 "FMUL $src2\n\t" | |
| 10404 "FSTP_S $dst" %} | |
| 10405 opcode(0xD8, 0x1); /* D8 C8+i or D8 /1 ;; result in TOS */ | |
|
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10406 ins_encode( Push_Reg_FPR(src1), |
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10407 OpcReg_FPR(src2), |
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10408 Pop_Mem_FPR(dst) ); |
| 0 | 10409 ins_pipe( fpu_mem_reg_reg ); |
| 10410 %} | |
| 10411 // | |
| 10412 // This instruction does not round to 24-bits | |
|
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10413 instruct mulFPR_reg(regFPR dst, regFPR src1, regFPR src2) %{ |
| 0 | 10414 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10415 match(Set dst (MulF src1 src2)); | |
| 10416 | |
| 10417 format %{ "FLD $src1\n\t" | |
| 10418 "FMUL $src2\n\t" | |
| 10419 "FSTP_S $dst" %} | |
| 10420 opcode(0xD8, 0x1); /* D8 C8+i */ | |
|
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10421 ins_encode( Push_Reg_FPR(src2), |
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10422 OpcReg_FPR(src1), |
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10423 Pop_Reg_FPR(dst) ); |
| 0 | 10424 ins_pipe( fpu_reg_reg_reg ); |
| 10425 %} | |
| 10426 | |
| 10427 | |
| 10428 // Spill to obtain 24-bit precision | |
| 10429 // Cisc-alternate to reg-reg multiply | |
|
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10430 instruct mulFPR24_reg_mem(stackSlotF dst, regFPR src1, memory src2) %{ |
| 0 | 10431 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10432 match(Set dst (MulF src1 (LoadF src2))); | |
| 10433 | |
| 10434 format %{ "FLD_S $src2\n\t" | |
| 10435 "FMUL $src1\n\t" | |
| 10436 "FSTP_S $dst" %} | |
| 10437 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or DE /1*/ /* LoadF D9 /0 */ | |
| 10438 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), | |
|
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10439 OpcReg_FPR(src1), |
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10440 Pop_Mem_FPR(dst) ); |
| 0 | 10441 ins_pipe( fpu_mem_reg_mem ); |
| 10442 %} | |
| 10443 // | |
| 10444 // This instruction does not round to 24-bits | |
| 10445 // Cisc-alternate to reg-reg multiply | |
|
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10446 instruct mulFPR_reg_mem(regFPR dst, regFPR src1, memory src2) %{ |
| 0 | 10447 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10448 match(Set dst (MulF src1 (LoadF src2))); | |
| 10449 | |
| 10450 format %{ "FMUL $dst,$src1,$src2" %} | |
| 10451 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadF D9 /0 */ | |
| 10452 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), | |
|
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10453 OpcReg_FPR(src1), |
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10454 Pop_Reg_FPR(dst) ); |
| 0 | 10455 ins_pipe( fpu_reg_reg_mem ); |
| 10456 %} | |
| 10457 | |
| 10458 // Spill to obtain 24-bit precision | |
|
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10459 instruct mulFPR24_mem_mem(stackSlotF dst, memory src1, memory src2) %{ |
| 0 | 10460 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10461 match(Set dst (MulF src1 src2)); | |
| 10462 | |
| 10463 format %{ "FMUL $dst,$src1,$src2" %} | |
| 10464 opcode(0xD8, 0x1, 0xD9); /* D8 /1 */ /* LoadF D9 /0 */ | |
| 10465 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), | |
| 10466 set_instruction_start, | |
| 10467 OpcP, RMopc_Mem(secondary,src1), | |
|
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10468 Pop_Mem_FPR(dst) ); |
| 0 | 10469 ins_pipe( fpu_mem_mem_mem ); |
| 10470 %} | |
| 10471 | |
| 10472 // Spill to obtain 24-bit precision | |
|
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10473 instruct mulFPR24_reg_imm(stackSlotF dst, regFPR src, immFPR con) %{ |
| 0 | 10474 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 2008 | 10475 match(Set dst (MulF src con)); |
| 10476 | |
| 10477 format %{ "FLD $src\n\t" | |
| 10478 "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t" | |
| 10479 "FSTP_S $dst" %} | |
| 10480 ins_encode %{ | |
| 10481 __ fld_s($src$$reg - 1); // FLD ST(i-1) | |
| 10482 __ fmul_s($constantaddress($con)); | |
| 10483 __ fstp_s(Address(rsp, $dst$$disp)); | |
| 10484 %} | |
| 10485 ins_pipe(fpu_mem_reg_con); | |
| 0 | 10486 %} |
| 10487 // | |
| 10488 // This instruction does not round to 24-bits | |
|
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10489 instruct mulFPR_reg_imm(regFPR dst, regFPR src, immFPR con) %{ |
| 0 | 10490 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 2008 | 10491 match(Set dst (MulF src con)); |
| 10492 | |
| 10493 format %{ "FLD $src\n\t" | |
| 10494 "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t" | |
| 10495 "FSTP $dst" %} | |
| 10496 ins_encode %{ | |
| 10497 __ fld_s($src$$reg - 1); // FLD ST(i-1) | |
| 10498 __ fmul_s($constantaddress($con)); | |
| 10499 __ fstp_d($dst$$reg); | |
| 10500 %} | |
| 10501 ins_pipe(fpu_reg_reg_con); | |
| 0 | 10502 %} |
| 10503 | |
| 10504 | |
| 10505 // | |
|
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10506 // MACRO1 -- subsume unshared load into mulFPR |
| 0 | 10507 // This instruction does not round to 24-bits |
|
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10508 instruct mulFPR_reg_load1(regFPR dst, regFPR src, memory mem1 ) %{ |
| 0 | 10509 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10510 match(Set dst (MulF (LoadF mem1) src)); | |
| 10511 | |
| 10512 format %{ "FLD $mem1 ===MACRO1===\n\t" | |
| 10513 "FMUL ST,$src\n\t" | |
| 10514 "FSTP $dst" %} | |
| 10515 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or D8 /1 */ /* LoadF D9 /0 */ | |
| 10516 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem1), | |
|
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10517 OpcReg_FPR(src), |
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10518 Pop_Reg_FPR(dst) ); |
| 0 | 10519 ins_pipe( fpu_reg_reg_mem ); |
| 10520 %} | |
| 10521 // | |
|
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10522 // MACRO2 -- addFPR a mulFPR which subsumed an unshared load |
| 0 | 10523 // This instruction does not round to 24-bits |
|
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10524 instruct addFPR_mulFPR_reg_load1(regFPR dst, memory mem1, regFPR src1, regFPR src2) %{ |
| 0 | 10525 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10526 match(Set dst (AddF (MulF (LoadF mem1) src1) src2)); | |
| 10527 ins_cost(95); | |
| 10528 | |
| 10529 format %{ "FLD $mem1 ===MACRO2===\n\t" | |
|
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10530 "FMUL ST,$src1 subsume mulFPR left load\n\t" |
| 0 | 10531 "FADD ST,$src2\n\t" |
| 10532 "FSTP $dst" %} | |
| 10533 opcode(0xD9); /* LoadF D9 /0 */ | |
| 10534 ins_encode( OpcP, RMopc_Mem(0x00,mem1), | |
| 10535 FMul_ST_reg(src1), | |
| 10536 FAdd_ST_reg(src2), | |
|
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10537 Pop_Reg_FPR(dst) ); |
| 0 | 10538 ins_pipe( fpu_reg_mem_reg_reg ); |
| 10539 %} | |
| 10540 | |
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10541 // MACRO3 -- addFPR a mulFPR |
| 0 | 10542 // This instruction does not round to 24-bits. It is a '2-address' |
| 10543 // instruction in that the result goes back to src2. This eliminates | |
| 10544 // a move from the macro; possibly the register allocator will have | |
| 10545 // to add it back (and maybe not). | |
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10546 instruct addFPR_mulFPR_reg(regFPR src2, regFPR src1, regFPR src0) %{ |
| 0 | 10547 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10548 match(Set src2 (AddF (MulF src0 src1) src2)); | |
| 10549 | |
| 10550 format %{ "FLD $src0 ===MACRO3===\n\t" | |
| 10551 "FMUL ST,$src1\n\t" | |
| 10552 "FADDP $src2,ST" %} | |
| 10553 opcode(0xD9); /* LoadF D9 /0 */ | |
|
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10554 ins_encode( Push_Reg_FPR(src0), |
| 0 | 10555 FMul_ST_reg(src1), |
| 10556 FAddP_reg_ST(src2) ); | |
| 10557 ins_pipe( fpu_reg_reg_reg ); | |
| 10558 %} | |
| 10559 | |
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10560 // MACRO4 -- divFPR subFPR |
| 0 | 10561 // This instruction does not round to 24-bits |
|
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10562 instruct subFPR_divFPR_reg(regFPR dst, regFPR src1, regFPR src2, regFPR src3) %{ |
| 0 | 10563 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10564 match(Set dst (DivF (SubF src2 src1) src3)); | |
| 10565 | |
| 10566 format %{ "FLD $src2 ===MACRO4===\n\t" | |
| 10567 "FSUB ST,$src1\n\t" | |
| 10568 "FDIV ST,$src3\n\t" | |
| 10569 "FSTP $dst" %} | |
| 10570 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/ | |
|
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10571 ins_encode( Push_Reg_FPR(src2), |
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10572 subFPR_divFPR_encode(src1,src3), |
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10573 Pop_Reg_FPR(dst) ); |
| 0 | 10574 ins_pipe( fpu_reg_reg_reg_reg ); |
| 10575 %} | |
| 10576 | |
| 10577 // Spill to obtain 24-bit precision | |
|
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10578 instruct divFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{ |
| 0 | 10579 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10580 match(Set dst (DivF src1 src2)); | |
| 10581 | |
| 10582 format %{ "FDIV $dst,$src1,$src2" %} | |
| 10583 opcode(0xD8, 0x6); /* D8 F0+i or DE /6*/ | |
|
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10584 ins_encode( Push_Reg_FPR(src1), |
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10585 OpcReg_FPR(src2), |
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10586 Pop_Mem_FPR(dst) ); |
| 0 | 10587 ins_pipe( fpu_mem_reg_reg ); |
| 10588 %} | |
| 10589 // | |
| 10590 // This instruction does not round to 24-bits | |
|
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10591 instruct divFPR_reg(regFPR dst, regFPR src) %{ |
| 0 | 10592 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10593 match(Set dst (DivF dst src)); | |
| 10594 | |
| 10595 format %{ "FDIV $dst,$src" %} | |
| 10596 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/ | |
|
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10597 ins_encode( Push_Reg_FPR(src), |
| 0 | 10598 OpcP, RegOpc(dst) ); |
| 10599 ins_pipe( fpu_reg_reg ); | |
| 10600 %} | |
| 10601 | |
| 10602 | |
| 10603 // Spill to obtain 24-bit precision | |
|
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10604 instruct modFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{ |
| 0 | 10605 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10606 match(Set dst (ModF src1 src2)); | |
|
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10607 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS |
| 0 | 10608 |
| 10609 format %{ "FMOD $dst,$src1,$src2" %} | |
|
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10610 ins_encode( Push_Reg_Mod_DPR(src1, src2), |
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10611 emitModDPR(), |
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10612 Push_Result_Mod_DPR(src2), |
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10613 Pop_Mem_FPR(dst)); |
| 0 | 10614 ins_pipe( pipe_slow ); |
| 10615 %} | |
| 10616 // | |
| 10617 // This instruction does not round to 24-bits | |
|
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10618 instruct modFPR_reg(regFPR dst, regFPR src, eAXRegI rax, eFlagsReg cr) %{ |
| 0 | 10619 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10620 match(Set dst (ModF dst src)); | |
|
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10621 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS |
| 0 | 10622 |
| 10623 format %{ "FMOD $dst,$src" %} | |
|
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10624 ins_encode(Push_Reg_Mod_DPR(dst, src), |
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10625 emitModDPR(), |
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10626 Push_Result_Mod_DPR(src), |
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10627 Pop_Reg_FPR(dst)); |
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10628 ins_pipe( pipe_slow ); |
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10629 %} |
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10630 |
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10631 instruct modF_reg(regF dst, regF src0, regF src1, eAXRegI rax, eFlagsReg cr) %{ |
| 0 | 10632 predicate(UseSSE>=1); |
| 10633 match(Set dst (ModF src0 src1)); | |
| 10634 effect(KILL rax, KILL cr); | |
| 10635 format %{ "SUB ESP,4\t # FMOD\n" | |
| 10636 "\tMOVSS [ESP+0],$src1\n" | |
| 10637 "\tFLD_S [ESP+0]\n" | |
| 10638 "\tMOVSS [ESP+0],$src0\n" | |
| 10639 "\tFLD_S [ESP+0]\n" | |
| 10640 "loop:\tFPREM\n" | |
| 10641 "\tFWAIT\n" | |
| 10642 "\tFNSTSW AX\n" | |
| 10643 "\tSAHF\n" | |
| 10644 "\tJP loop\n" | |
| 10645 "\tFSTP_S [ESP+0]\n" | |
| 10646 "\tMOVSS $dst,[ESP+0]\n" | |
| 10647 "\tADD ESP,4\n" | |
| 10648 "\tFSTP ST0\t # Restore FPU Stack" | |
| 10649 %} | |
| 10650 ins_cost(250); | |
|
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10651 ins_encode( Push_ModF_encoding(src0, src1), emitModDPR(), Push_ResultF(dst,0x4), PopFPU); |
| 0 | 10652 ins_pipe( pipe_slow ); |
| 10653 %} | |
| 10654 | |
| 10655 | |
| 10656 //----------Arithmetic Conversion Instructions--------------------------------- | |
| 10657 // The conversions operations are all Alpha sorted. Please keep it that way! | |
| 10658 | |
|
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10659 instruct roundFloat_mem_reg(stackSlotF dst, regFPR src) %{ |
| 0 | 10660 predicate(UseSSE==0); |
| 10661 match(Set dst (RoundFloat src)); | |
| 10662 ins_cost(125); | |
| 10663 format %{ "FST_S $dst,$src\t# F-round" %} | |
|
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10664 ins_encode( Pop_Mem_Reg_FPR(dst, src) ); |
| 0 | 10665 ins_pipe( fpu_mem_reg ); |
| 10666 %} | |
| 10667 | |
|
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10668 instruct roundDouble_mem_reg(stackSlotD dst, regDPR src) %{ |
| 0 | 10669 predicate(UseSSE<=1); |
| 10670 match(Set dst (RoundDouble src)); | |
| 10671 ins_cost(125); | |
| 10672 format %{ "FST_D $dst,$src\t# D-round" %} | |
|
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10673 ins_encode( Pop_Mem_Reg_DPR(dst, src) ); |
| 0 | 10674 ins_pipe( fpu_mem_reg ); |
| 10675 %} | |
| 10676 | |
| 10677 // Force rounding to 24-bit precision and 6-bit exponent | |
|
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10678 instruct convDPR2FPR_reg(stackSlotF dst, regDPR src) %{ |
| 0 | 10679 predicate(UseSSE==0); |
| 10680 match(Set dst (ConvD2F src)); | |
| 10681 format %{ "FST_S $dst,$src\t# F-round" %} | |
| 10682 expand %{ | |
| 10683 roundFloat_mem_reg(dst,src); | |
| 10684 %} | |
| 10685 %} | |
| 10686 | |
| 10687 // Force rounding to 24-bit precision and 6-bit exponent | |
|
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10688 instruct convDPR2F_reg(regF dst, regDPR src, eFlagsReg cr) %{ |
| 0 | 10689 predicate(UseSSE==1); |
| 10690 match(Set dst (ConvD2F src)); | |
| 10691 effect( KILL cr ); | |
| 10692 format %{ "SUB ESP,4\n\t" | |
| 10693 "FST_S [ESP],$src\t# F-round\n\t" | |
| 10694 "MOVSS $dst,[ESP]\n\t" | |
| 10695 "ADD ESP,4" %} | |
| 4759 | 10696 ins_encode %{ |
| 10697 __ subptr(rsp, 4); | |
| 10698 if ($src$$reg != FPR1L_enc) { | |
| 10699 __ fld_s($src$$reg-1); | |
| 10700 __ fstp_s(Address(rsp, 0)); | |
| 10701 } else { | |
| 10702 __ fst_s(Address(rsp, 0)); | |
| 10703 } | |
| 10704 __ movflt($dst$$XMMRegister, Address(rsp, 0)); | |
| 10705 __ addptr(rsp, 4); | |
| 10706 %} | |
| 0 | 10707 ins_pipe( pipe_slow ); |
| 10708 %} | |
| 10709 | |
| 10710 // Force rounding double precision to single precision | |
|
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10711 instruct convD2F_reg(regF dst, regD src) %{ |
| 0 | 10712 predicate(UseSSE>=2); |
| 10713 match(Set dst (ConvD2F src)); | |
| 10714 format %{ "CVTSD2SS $dst,$src\t# F-round" %} | |
| 4759 | 10715 ins_encode %{ |
| 10716 __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister); | |
| 10717 %} | |
| 0 | 10718 ins_pipe( pipe_slow ); |
| 10719 %} | |
| 10720 | |
|
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10721 instruct convFPR2DPR_reg_reg(regDPR dst, regFPR src) %{ |
| 0 | 10722 predicate(UseSSE==0); |
| 10723 match(Set dst (ConvF2D src)); | |
| 10724 format %{ "FST_S $dst,$src\t# D-round" %} | |
|
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10725 ins_encode( Pop_Reg_Reg_DPR(dst, src)); |
| 0 | 10726 ins_pipe( fpu_reg_reg ); |
| 10727 %} | |
| 10728 | |
|
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10729 instruct convFPR2D_reg(stackSlotD dst, regFPR src) %{ |
| 0 | 10730 predicate(UseSSE==1); |
| 10731 match(Set dst (ConvF2D src)); | |
| 10732 format %{ "FST_D $dst,$src\t# D-round" %} | |
| 10733 expand %{ | |
| 10734 roundDouble_mem_reg(dst,src); | |
| 10735 %} | |
| 10736 %} | |
| 10737 | |
|
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10738 instruct convF2DPR_reg(regDPR dst, regF src, eFlagsReg cr) %{ |
| 0 | 10739 predicate(UseSSE==1); |
| 10740 match(Set dst (ConvF2D src)); | |
| 10741 effect( KILL cr ); | |
| 10742 format %{ "SUB ESP,4\n\t" | |
| 10743 "MOVSS [ESP] $src\n\t" | |
| 10744 "FLD_S [ESP]\n\t" | |
| 10745 "ADD ESP,4\n\t" | |
| 10746 "FSTP $dst\t# D-round" %} | |
| 4759 | 10747 ins_encode %{ |
| 10748 __ subptr(rsp, 4); | |
| 10749 __ movflt(Address(rsp, 0), $src$$XMMRegister); | |
| 10750 __ fld_s(Address(rsp, 0)); | |
| 10751 __ addptr(rsp, 4); | |
| 10752 __ fstp_d($dst$$reg); | |
| 10753 %} | |
| 0 | 10754 ins_pipe( pipe_slow ); |
| 10755 %} | |
| 10756 | |
|
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10757 instruct convF2D_reg(regD dst, regF src) %{ |
| 0 | 10758 predicate(UseSSE>=2); |
| 10759 match(Set dst (ConvF2D src)); | |
| 10760 format %{ "CVTSS2SD $dst,$src\t# D-round" %} | |
| 4759 | 10761 ins_encode %{ |
| 10762 __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister); | |
| 10763 %} | |
| 0 | 10764 ins_pipe( pipe_slow ); |
| 10765 %} | |
| 10766 | |
| 10767 // Convert a double to an int. If the double is a NAN, stuff a zero in instead. | |
|
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10768 instruct convDPR2I_reg_reg( eAXRegI dst, eDXRegI tmp, regDPR src, eFlagsReg cr ) %{ |
| 0 | 10769 predicate(UseSSE<=1); |
| 10770 match(Set dst (ConvD2I src)); | |
| 10771 effect( KILL tmp, KILL cr ); | |
| 10772 format %{ "FLD $src\t# Convert double to int \n\t" | |
| 10773 "FLDCW trunc mode\n\t" | |
| 10774 "SUB ESP,4\n\t" | |
| 10775 "FISTp [ESP + #0]\n\t" | |
| 10776 "FLDCW std/24-bit mode\n\t" | |
| 10777 "POP EAX\n\t" | |
| 10778 "CMP EAX,0x80000000\n\t" | |
| 10779 "JNE,s fast\n\t" | |
| 10780 "FLD_D $src\n\t" | |
| 10781 "CALL d2i_wrapper\n" | |
| 10782 "fast:" %} | |
|
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10783 ins_encode( Push_Reg_DPR(src), DPR2I_encoding(src) ); |
| 0 | 10784 ins_pipe( pipe_slow ); |
| 10785 %} | |
| 10786 | |
| 10787 // Convert a double to an int. If the double is a NAN, stuff a zero in instead. | |
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10788 instruct convD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regD src, eFlagsReg cr ) %{ |
| 0 | 10789 predicate(UseSSE>=2); |
| 10790 match(Set dst (ConvD2I src)); | |
| 10791 effect( KILL tmp, KILL cr ); | |
| 10792 format %{ "CVTTSD2SI $dst, $src\n\t" | |
| 10793 "CMP $dst,0x80000000\n\t" | |
| 10794 "JNE,s fast\n\t" | |
| 10795 "SUB ESP, 8\n\t" | |
| 10796 "MOVSD [ESP], $src\n\t" | |
| 10797 "FLD_D [ESP]\n\t" | |
| 10798 "ADD ESP, 8\n\t" | |
| 10799 "CALL d2i_wrapper\n" | |
| 10800 "fast:" %} | |
| 4759 | 10801 ins_encode %{ |
| 10802 Label fast; | |
| 10803 __ cvttsd2sil($dst$$Register, $src$$XMMRegister); | |
| 10804 __ cmpl($dst$$Register, 0x80000000); | |
| 10805 __ jccb(Assembler::notEqual, fast); | |
| 10806 __ subptr(rsp, 8); | |
| 10807 __ movdbl(Address(rsp, 0), $src$$XMMRegister); | |
| 10808 __ fld_d(Address(rsp, 0)); | |
| 10809 __ addptr(rsp, 8); | |
| 10810 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2i_wrapper()))); | |
| 10811 __ bind(fast); | |
| 10812 %} | |
| 0 | 10813 ins_pipe( pipe_slow ); |
| 10814 %} | |
| 10815 | |
|
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10816 instruct convDPR2L_reg_reg( eADXRegL dst, regDPR src, eFlagsReg cr ) %{ |
| 0 | 10817 predicate(UseSSE<=1); |
| 10818 match(Set dst (ConvD2L src)); | |
| 10819 effect( KILL cr ); | |
| 10820 format %{ "FLD $src\t# Convert double to long\n\t" | |
| 10821 "FLDCW trunc mode\n\t" | |
| 10822 "SUB ESP,8\n\t" | |
| 10823 "FISTp [ESP + #0]\n\t" | |
| 10824 "FLDCW std/24-bit mode\n\t" | |
| 10825 "POP EAX\n\t" | |
| 10826 "POP EDX\n\t" | |
| 10827 "CMP EDX,0x80000000\n\t" | |
| 10828 "JNE,s fast\n\t" | |
| 10829 "TEST EAX,EAX\n\t" | |
| 10830 "JNE,s fast\n\t" | |
| 10831 "FLD $src\n\t" | |
| 10832 "CALL d2l_wrapper\n" | |
| 10833 "fast:" %} | |
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10834 ins_encode( Push_Reg_DPR(src), DPR2L_encoding(src) ); |
| 0 | 10835 ins_pipe( pipe_slow ); |
| 10836 %} | |
| 10837 | |
| 10838 // XMM lacks a float/double->long conversion, so use the old FPU stack. | |
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10839 instruct convD2L_reg_reg( eADXRegL dst, regD src, eFlagsReg cr ) %{ |
| 0 | 10840 predicate (UseSSE>=2); |
| 10841 match(Set dst (ConvD2L src)); | |
| 10842 effect( KILL cr ); | |
| 10843 format %{ "SUB ESP,8\t# Convert double to long\n\t" | |
| 10844 "MOVSD [ESP],$src\n\t" | |
| 10845 "FLD_D [ESP]\n\t" | |
| 10846 "FLDCW trunc mode\n\t" | |
| 10847 "FISTp [ESP + #0]\n\t" | |
| 10848 "FLDCW std/24-bit mode\n\t" | |
| 10849 "POP EAX\n\t" | |
| 10850 "POP EDX\n\t" | |
| 10851 "CMP EDX,0x80000000\n\t" | |
| 10852 "JNE,s fast\n\t" | |
| 10853 "TEST EAX,EAX\n\t" | |
| 10854 "JNE,s fast\n\t" | |
| 10855 "SUB ESP,8\n\t" | |
| 10856 "MOVSD [ESP],$src\n\t" | |
| 10857 "FLD_D [ESP]\n\t" | |
| 4759 | 10858 "ADD ESP,8\n\t" |
| 0 | 10859 "CALL d2l_wrapper\n" |
| 10860 "fast:" %} | |
| 4759 | 10861 ins_encode %{ |
| 10862 Label fast; | |
| 10863 __ subptr(rsp, 8); | |
| 10864 __ movdbl(Address(rsp, 0), $src$$XMMRegister); | |
| 10865 __ fld_d(Address(rsp, 0)); | |
| 10866 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc())); | |
| 10867 __ fistp_d(Address(rsp, 0)); | |
| 10868 // Restore the rounding mode, mask the exception | |
| 10869 if (Compile::current()->in_24_bit_fp_mode()) { | |
| 10870 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); | |
| 10871 } else { | |
| 10872 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); | |
| 10873 } | |
| 10874 // Load the converted long, adjust CPU stack | |
| 10875 __ pop(rax); | |
| 10876 __ pop(rdx); | |
| 10877 __ cmpl(rdx, 0x80000000); | |
| 10878 __ jccb(Assembler::notEqual, fast); | |
| 10879 __ testl(rax, rax); | |
| 10880 __ jccb(Assembler::notEqual, fast); | |
| 10881 __ subptr(rsp, 8); | |
| 10882 __ movdbl(Address(rsp, 0), $src$$XMMRegister); | |
| 10883 __ fld_d(Address(rsp, 0)); | |
| 10884 __ addptr(rsp, 8); | |
| 10885 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2l_wrapper()))); | |
| 10886 __ bind(fast); | |
| 10887 %} | |
| 0 | 10888 ins_pipe( pipe_slow ); |
| 10889 %} | |
| 10890 | |
| 10891 // Convert a double to an int. Java semantics require we do complex | |
| 10892 // manglations in the corner cases. So we set the rounding mode to | |
| 10893 // 'zero', store the darned double down as an int, and reset the | |
| 10894 // rounding mode to 'nearest'. The hardware stores a flag value down | |
| 10895 // if we would overflow or converted a NAN; we check for this and | |
| 10896 // and go the slow path if needed. | |
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10897 instruct convFPR2I_reg_reg(eAXRegI dst, eDXRegI tmp, regFPR src, eFlagsReg cr ) %{ |
| 0 | 10898 predicate(UseSSE==0); |
| 10899 match(Set dst (ConvF2I src)); | |
| 10900 effect( KILL tmp, KILL cr ); | |
| 10901 format %{ "FLD $src\t# Convert float to int \n\t" | |
| 10902 "FLDCW trunc mode\n\t" | |
| 10903 "SUB ESP,4\n\t" | |
| 10904 "FISTp [ESP + #0]\n\t" | |
| 10905 "FLDCW std/24-bit mode\n\t" | |
| 10906 "POP EAX\n\t" | |
| 10907 "CMP EAX,0x80000000\n\t" | |
| 10908 "JNE,s fast\n\t" | |
| 10909 "FLD $src\n\t" | |
| 10910 "CALL d2i_wrapper\n" | |
| 10911 "fast:" %} | |
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10912 // DPR2I_encoding works for FPR2I |
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10913 ins_encode( Push_Reg_FPR(src), DPR2I_encoding(src) ); |
| 0 | 10914 ins_pipe( pipe_slow ); |
| 10915 %} | |
| 10916 | |
| 10917 // Convert a float in xmm to an int reg. | |
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10918 instruct convF2I_reg(eAXRegI dst, eDXRegI tmp, regF src, eFlagsReg cr ) %{ |
| 0 | 10919 predicate(UseSSE>=1); |
| 10920 match(Set dst (ConvF2I src)); | |
| 10921 effect( KILL tmp, KILL cr ); | |
| 10922 format %{ "CVTTSS2SI $dst, $src\n\t" | |
| 10923 "CMP $dst,0x80000000\n\t" | |
| 10924 "JNE,s fast\n\t" | |
| 10925 "SUB ESP, 4\n\t" | |
| 10926 "MOVSS [ESP], $src\n\t" | |
| 10927 "FLD [ESP]\n\t" | |
| 10928 "ADD ESP, 4\n\t" | |
| 10929 "CALL d2i_wrapper\n" | |
| 10930 "fast:" %} | |
| 4759 | 10931 ins_encode %{ |
| 10932 Label fast; | |
| 10933 __ cvttss2sil($dst$$Register, $src$$XMMRegister); | |
| 10934 __ cmpl($dst$$Register, 0x80000000); | |
| 10935 __ jccb(Assembler::notEqual, fast); | |
| 10936 __ subptr(rsp, 4); | |
| 10937 __ movflt(Address(rsp, 0), $src$$XMMRegister); | |
| 10938 __ fld_s(Address(rsp, 0)); | |
| 10939 __ addptr(rsp, 4); | |
| 10940 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2i_wrapper()))); | |
| 10941 __ bind(fast); | |
| 10942 %} | |
| 0 | 10943 ins_pipe( pipe_slow ); |
| 10944 %} | |
| 10945 | |
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10946 instruct convFPR2L_reg_reg( eADXRegL dst, regFPR src, eFlagsReg cr ) %{ |
| 0 | 10947 predicate(UseSSE==0); |
| 10948 match(Set dst (ConvF2L src)); | |
| 10949 effect( KILL cr ); | |
| 10950 format %{ "FLD $src\t# Convert float to long\n\t" | |
| 10951 "FLDCW trunc mode\n\t" | |
| 10952 "SUB ESP,8\n\t" | |
| 10953 "FISTp [ESP + #0]\n\t" | |
| 10954 "FLDCW std/24-bit mode\n\t" | |
| 10955 "POP EAX\n\t" | |
| 10956 "POP EDX\n\t" | |
| 10957 "CMP EDX,0x80000000\n\t" | |
| 10958 "JNE,s fast\n\t" | |
| 10959 "TEST EAX,EAX\n\t" | |
| 10960 "JNE,s fast\n\t" | |
| 10961 "FLD $src\n\t" | |
| 10962 "CALL d2l_wrapper\n" | |
| 10963 "fast:" %} | |
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10964 // DPR2L_encoding works for FPR2L |
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10965 ins_encode( Push_Reg_FPR(src), DPR2L_encoding(src) ); |
| 0 | 10966 ins_pipe( pipe_slow ); |
| 10967 %} | |
| 10968 | |
| 10969 // XMM lacks a float/double->long conversion, so use the old FPU stack. | |
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10970 instruct convF2L_reg_reg( eADXRegL dst, regF src, eFlagsReg cr ) %{ |
| 0 | 10971 predicate (UseSSE>=1); |
| 10972 match(Set dst (ConvF2L src)); | |
| 10973 effect( KILL cr ); | |
| 10974 format %{ "SUB ESP,8\t# Convert float to long\n\t" | |
| 10975 "MOVSS [ESP],$src\n\t" | |
| 10976 "FLD_S [ESP]\n\t" | |
| 10977 "FLDCW trunc mode\n\t" | |
| 10978 "FISTp [ESP + #0]\n\t" | |
| 10979 "FLDCW std/24-bit mode\n\t" | |
| 10980 "POP EAX\n\t" | |
| 10981 "POP EDX\n\t" | |
| 10982 "CMP EDX,0x80000000\n\t" | |
| 10983 "JNE,s fast\n\t" | |
| 10984 "TEST EAX,EAX\n\t" | |
| 10985 "JNE,s fast\n\t" | |
| 10986 "SUB ESP,4\t# Convert float to long\n\t" | |
| 10987 "MOVSS [ESP],$src\n\t" | |
| 10988 "FLD_S [ESP]\n\t" | |
| 10989 "ADD ESP,4\n\t" | |
| 10990 "CALL d2l_wrapper\n" | |
| 10991 "fast:" %} | |
| 4759 | 10992 ins_encode %{ |
| 10993 Label fast; | |
| 10994 __ subptr(rsp, 8); | |
| 10995 __ movflt(Address(rsp, 0), $src$$XMMRegister); | |
| 10996 __ fld_s(Address(rsp, 0)); | |
| 10997 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc())); | |
| 10998 __ fistp_d(Address(rsp, 0)); | |
| 10999 // Restore the rounding mode, mask the exception | |
| 11000 if (Compile::current()->in_24_bit_fp_mode()) { | |
| 11001 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); | |
| 11002 } else { | |
| 11003 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); | |
| 11004 } | |
| 11005 // Load the converted long, adjust CPU stack | |
| 11006 __ pop(rax); | |
| 11007 __ pop(rdx); | |
| 11008 __ cmpl(rdx, 0x80000000); | |
| 11009 __ jccb(Assembler::notEqual, fast); | |
| 11010 __ testl(rax, rax); | |
| 11011 __ jccb(Assembler::notEqual, fast); | |
| 11012 __ subptr(rsp, 4); | |
| 11013 __ movflt(Address(rsp, 0), $src$$XMMRegister); | |
| 11014 __ fld_s(Address(rsp, 0)); | |
| 11015 __ addptr(rsp, 4); | |
| 11016 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2l_wrapper()))); | |
| 11017 __ bind(fast); | |
| 11018 %} | |
| 0 | 11019 ins_pipe( pipe_slow ); |
| 11020 %} | |
| 11021 | |
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11022 instruct convI2DPR_reg(regDPR dst, stackSlotI src) %{ |
| 0 | 11023 predicate( UseSSE<=1 ); |
| 11024 match(Set dst (ConvI2D src)); | |
| 11025 format %{ "FILD $src\n\t" | |
| 11026 "FSTP $dst" %} | |
| 11027 opcode(0xDB, 0x0); /* DB /0 */ | |
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11028 ins_encode(Push_Mem_I(src), Pop_Reg_DPR(dst)); |
| 0 | 11029 ins_pipe( fpu_reg_mem ); |
| 11030 %} | |
| 11031 | |
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11032 instruct convI2D_reg(regD dst, rRegI src) %{ |
| 71 | 11033 predicate( UseSSE>=2 && !UseXmmI2D ); |
| 0 | 11034 match(Set dst (ConvI2D src)); |
| 11035 format %{ "CVTSI2SD $dst,$src" %} | |
| 4759 | 11036 ins_encode %{ |
| 11037 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register); | |
| 11038 %} | |
| 0 | 11039 ins_pipe( pipe_slow ); |
| 11040 %} | |
| 11041 | |
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11042 instruct convI2D_mem(regD dst, memory mem) %{ |
| 0 | 11043 predicate( UseSSE>=2 ); |
| 11044 match(Set dst (ConvI2D (LoadI mem))); | |
| 11045 format %{ "CVTSI2SD $dst,$mem" %} | |
| 4759 | 11046 ins_encode %{ |
| 11047 __ cvtsi2sdl ($dst$$XMMRegister, $mem$$Address); | |
| 11048 %} | |
| 0 | 11049 ins_pipe( pipe_slow ); |
| 11050 %} | |
| 11051 | |
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11052 instruct convXI2D_reg(regD dst, rRegI src) |
| 71 | 11053 %{ |
| 11054 predicate( UseSSE>=2 && UseXmmI2D ); | |
| 11055 match(Set dst (ConvI2D src)); | |
| 11056 | |
| 11057 format %{ "MOVD $dst,$src\n\t" | |
| 11058 "CVTDQ2PD $dst,$dst\t# i2d" %} | |
| 11059 ins_encode %{ | |
| 304 | 11060 __ movdl($dst$$XMMRegister, $src$$Register); |
| 71 | 11061 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister); |
| 11062 %} | |
| 11063 ins_pipe(pipe_slow); // XXX | |
| 11064 %} | |
| 11065 | |
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11066 instruct convI2DPR_mem(regDPR dst, memory mem) %{ |
| 0 | 11067 predicate( UseSSE<=1 && !Compile::current()->select_24_bit_instr()); |
| 11068 match(Set dst (ConvI2D (LoadI mem))); | |
| 11069 format %{ "FILD $mem\n\t" | |
| 11070 "FSTP $dst" %} | |
| 11071 opcode(0xDB); /* DB /0 */ | |
| 11072 ins_encode( OpcP, RMopc_Mem(0x00,mem), | |
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11073 Pop_Reg_DPR(dst)); |
| 0 | 11074 ins_pipe( fpu_reg_mem ); |
| 11075 %} | |
| 11076 | |
| 11077 // Convert a byte to a float; no rounding step needed. | |
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11078 instruct conv24I2FPR_reg(regFPR dst, stackSlotI src) %{ |
| 0 | 11079 predicate( UseSSE==0 && n->in(1)->Opcode() == Op_AndI && n->in(1)->in(2)->is_Con() && n->in(1)->in(2)->get_int() == 255 ); |
| 11080 match(Set dst (ConvI2F src)); | |
| 11081 format %{ "FILD $src\n\t" | |
| 11082 "FSTP $dst" %} | |
| 11083 | |
| 11084 opcode(0xDB, 0x0); /* DB /0 */ | |
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11085 ins_encode(Push_Mem_I(src), Pop_Reg_FPR(dst)); |
| 0 | 11086 ins_pipe( fpu_reg_mem ); |
| 11087 %} | |
| 11088 | |
| 11089 // In 24-bit mode, force exponent rounding by storing back out | |
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11090 instruct convI2FPR_SSF(stackSlotF dst, stackSlotI src) %{ |
| 0 | 11091 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 11092 match(Set dst (ConvI2F src)); | |
| 11093 ins_cost(200); | |
| 11094 format %{ "FILD $src\n\t" | |
| 11095 "FSTP_S $dst" %} | |
| 11096 opcode(0xDB, 0x0); /* DB /0 */ | |
| 11097 ins_encode( Push_Mem_I(src), | |
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11098 Pop_Mem_FPR(dst)); |
| 0 | 11099 ins_pipe( fpu_mem_mem ); |
| 11100 %} | |
| 11101 | |
| 11102 // In 24-bit mode, force exponent rounding by storing back out | |
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11103 instruct convI2FPR_SSF_mem(stackSlotF dst, memory mem) %{ |
| 0 | 11104 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 11105 match(Set dst (ConvI2F (LoadI mem))); | |
| 11106 ins_cost(200); | |
| 11107 format %{ "FILD $mem\n\t" | |
| 11108 "FSTP_S $dst" %} | |
| 11109 opcode(0xDB); /* DB /0 */ | |
| 11110 ins_encode( OpcP, RMopc_Mem(0x00,mem), | |
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11111 Pop_Mem_FPR(dst)); |
| 0 | 11112 ins_pipe( fpu_mem_mem ); |
| 11113 %} | |
| 11114 | |
| 11115 // This instruction does not round to 24-bits | |
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11116 instruct convI2FPR_reg(regFPR dst, stackSlotI src) %{ |
| 0 | 11117 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 11118 match(Set dst (ConvI2F src)); | |
| 11119 format %{ "FILD $src\n\t" | |
| 11120 "FSTP $dst" %} | |
| 11121 opcode(0xDB, 0x0); /* DB /0 */ | |
| 11122 ins_encode( Push_Mem_I(src), | |
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11123 Pop_Reg_FPR(dst)); |
| 0 | 11124 ins_pipe( fpu_reg_mem ); |
| 11125 %} | |
| 11126 | |
| 11127 // This instruction does not round to 24-bits | |
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11128 instruct convI2FPR_mem(regFPR dst, memory mem) %{ |
| 0 | 11129 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 11130 match(Set dst (ConvI2F (LoadI mem))); | |
| 11131 format %{ "FILD $mem\n\t" | |
| 11132 "FSTP $dst" %} | |
| 11133 opcode(0xDB); /* DB /0 */ | |
| 11134 ins_encode( OpcP, RMopc_Mem(0x00,mem), | |
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11135 Pop_Reg_FPR(dst)); |
| 0 | 11136 ins_pipe( fpu_reg_mem ); |
| 11137 %} | |
| 11138 | |
| 11139 // Convert an int to a float in xmm; no rounding step needed. | |
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11140 instruct convI2F_reg(regF dst, rRegI src) %{ |
| 71 | 11141 predicate( UseSSE==1 || UseSSE>=2 && !UseXmmI2F ); |
| 0 | 11142 match(Set dst (ConvI2F src)); |
| 11143 format %{ "CVTSI2SS $dst, $src" %} | |
| 4759 | 11144 ins_encode %{ |
| 11145 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register); | |
| 11146 %} | |
| 0 | 11147 ins_pipe( pipe_slow ); |
| 11148 %} | |
| 11149 | |
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11150 instruct convXI2F_reg(regF dst, rRegI src) |
| 71 | 11151 %{ |
| 11152 predicate( UseSSE>=2 && UseXmmI2F ); | |
| 11153 match(Set dst (ConvI2F src)); | |
| 11154 | |
| 11155 format %{ "MOVD $dst,$src\n\t" | |
| 11156 "CVTDQ2PS $dst,$dst\t# i2f" %} | |
| 11157 ins_encode %{ | |
| 304 | 11158 __ movdl($dst$$XMMRegister, $src$$Register); |
| 71 | 11159 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister); |
| 11160 %} | |
| 11161 ins_pipe(pipe_slow); // XXX | |
| 11162 %} | |
| 11163 | |
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11164 instruct convI2L_reg( eRegL dst, rRegI src, eFlagsReg cr) %{ |
| 0 | 11165 match(Set dst (ConvI2L src)); |
| 11166 effect(KILL cr); | |
| 624 | 11167 ins_cost(375); |
| 0 | 11168 format %{ "MOV $dst.lo,$src\n\t" |
| 11169 "MOV $dst.hi,$src\n\t" | |
| 11170 "SAR $dst.hi,31" %} | |
| 11171 ins_encode(convert_int_long(dst,src)); | |
| 11172 ins_pipe( ialu_reg_reg_long ); | |
| 11173 %} | |
| 11174 | |
| 11175 // Zero-extend convert int to long | |
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11176 instruct convI2L_reg_zex(eRegL dst, rRegI src, immL_32bits mask, eFlagsReg flags ) %{ |
| 0 | 11177 match(Set dst (AndL (ConvI2L src) mask) ); |
| 11178 effect( KILL flags ); | |
| 624 | 11179 ins_cost(250); |
| 0 | 11180 format %{ "MOV $dst.lo,$src\n\t" |
| 11181 "XOR $dst.hi,$dst.hi" %} | |
| 11182 opcode(0x33); // XOR | |
| 11183 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) ); | |
| 11184 ins_pipe( ialu_reg_reg_long ); | |
| 11185 %} | |
| 11186 | |
| 11187 // Zero-extend long | |
| 11188 instruct zerox_long(eRegL dst, eRegL src, immL_32bits mask, eFlagsReg flags ) %{ | |
| 11189 match(Set dst (AndL src mask) ); | |
| 11190 effect( KILL flags ); | |
| 624 | 11191 ins_cost(250); |
| 0 | 11192 format %{ "MOV $dst.lo,$src.lo\n\t" |
| 11193 "XOR $dst.hi,$dst.hi\n\t" %} | |
| 11194 opcode(0x33); // XOR | |
| 11195 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) ); | |
| 11196 ins_pipe( ialu_reg_reg_long ); | |
| 11197 %} | |
| 11198 | |
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11199 instruct convL2DPR_reg( stackSlotD dst, eRegL src, eFlagsReg cr) %{ |
| 0 | 11200 predicate (UseSSE<=1); |
| 11201 match(Set dst (ConvL2D src)); | |
| 11202 effect( KILL cr ); | |
| 11203 format %{ "PUSH $src.hi\t# Convert long to double\n\t" | |
| 11204 "PUSH $src.lo\n\t" | |
| 11205 "FILD ST,[ESP + #0]\n\t" | |
| 11206 "ADD ESP,8\n\t" | |
| 11207 "FSTP_D $dst\t# D-round" %} | |
| 11208 opcode(0xDF, 0x5); /* DF /5 */ | |
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11209 ins_encode(convert_long_double(src), Pop_Mem_DPR(dst)); |
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11210 ins_pipe( pipe_slow ); |
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11211 %} |
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11212 |
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11213 instruct convL2D_reg( regD dst, eRegL src, eFlagsReg cr) %{ |
| 0 | 11214 predicate (UseSSE>=2); |
| 11215 match(Set dst (ConvL2D src)); | |
| 11216 effect( KILL cr ); | |
| 11217 format %{ "PUSH $src.hi\t# Convert long to double\n\t" | |
| 11218 "PUSH $src.lo\n\t" | |
| 11219 "FILD_D [ESP]\n\t" | |
| 11220 "FSTP_D [ESP]\n\t" | |
| 11221 "MOVSD $dst,[ESP]\n\t" | |
| 11222 "ADD ESP,8" %} | |
| 11223 opcode(0xDF, 0x5); /* DF /5 */ | |
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11224 ins_encode(convert_long_double2(src), Push_ResultD(dst)); |
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11225 ins_pipe( pipe_slow ); |
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11226 %} |
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11227 |
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11228 instruct convL2F_reg( regF dst, eRegL src, eFlagsReg cr) %{ |
| 0 | 11229 predicate (UseSSE>=1); |
| 11230 match(Set dst (ConvL2F src)); | |
| 11231 effect( KILL cr ); | |
| 11232 format %{ "PUSH $src.hi\t# Convert long to single float\n\t" | |
| 11233 "PUSH $src.lo\n\t" | |
| 11234 "FILD_D [ESP]\n\t" | |
| 11235 "FSTP_S [ESP]\n\t" | |
| 11236 "MOVSS $dst,[ESP]\n\t" | |
| 11237 "ADD ESP,8" %} | |
| 11238 opcode(0xDF, 0x5); /* DF /5 */ | |
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11239 ins_encode(convert_long_double2(src), Push_ResultF(dst,0x8)); |
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11240 ins_pipe( pipe_slow ); |
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11241 %} |
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11242 |
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11243 instruct convL2FPR_reg( stackSlotF dst, eRegL src, eFlagsReg cr) %{ |
| 0 | 11244 match(Set dst (ConvL2F src)); |
| 11245 effect( KILL cr ); | |
| 11246 format %{ "PUSH $src.hi\t# Convert long to single float\n\t" | |
| 11247 "PUSH $src.lo\n\t" | |
| 11248 "FILD ST,[ESP + #0]\n\t" | |
| 11249 "ADD ESP,8\n\t" | |
| 11250 "FSTP_S $dst\t# F-round" %} | |
| 11251 opcode(0xDF, 0x5); /* DF /5 */ | |
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11252 ins_encode(convert_long_double(src), Pop_Mem_FPR(dst)); |
| 0 | 11253 ins_pipe( pipe_slow ); |
| 11254 %} | |
| 11255 | |
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11256 instruct convL2I_reg( rRegI dst, eRegL src ) %{ |
| 0 | 11257 match(Set dst (ConvL2I src)); |
| 11258 effect( DEF dst, USE src ); | |
| 11259 format %{ "MOV $dst,$src.lo" %} | |
| 11260 ins_encode(enc_CopyL_Lo(dst,src)); | |
| 11261 ins_pipe( ialu_reg_reg ); | |
| 11262 %} | |
| 11263 | |
| 11264 | |
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11265 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{ |
| 0 | 11266 match(Set dst (MoveF2I src)); |
| 11267 effect( DEF dst, USE src ); | |
| 11268 ins_cost(100); | |
| 11269 format %{ "MOV $dst,$src\t# MoveF2I_stack_reg" %} | |
| 4759 | 11270 ins_encode %{ |
| 11271 __ movl($dst$$Register, Address(rsp, $src$$disp)); | |
| 11272 %} | |
| 0 | 11273 ins_pipe( ialu_reg_mem ); |
| 11274 %} | |
| 11275 | |
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11276 instruct MoveFPR2I_reg_stack(stackSlotI dst, regFPR src) %{ |
| 0 | 11277 predicate(UseSSE==0); |
| 11278 match(Set dst (MoveF2I src)); | |
| 11279 effect( DEF dst, USE src ); | |
| 11280 | |
| 11281 ins_cost(125); | |
| 11282 format %{ "FST_S $dst,$src\t# MoveF2I_reg_stack" %} | |
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11283 ins_encode( Pop_Mem_Reg_FPR(dst, src) ); |
| 0 | 11284 ins_pipe( fpu_mem_reg ); |
| 11285 %} | |
| 11286 | |
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11287 instruct MoveF2I_reg_stack_sse(stackSlotI dst, regF src) %{ |
| 0 | 11288 predicate(UseSSE>=1); |
| 11289 match(Set dst (MoveF2I src)); | |
| 11290 effect( DEF dst, USE src ); | |
| 11291 | |
| 11292 ins_cost(95); | |
| 11293 format %{ "MOVSS $dst,$src\t# MoveF2I_reg_stack_sse" %} | |
| 4759 | 11294 ins_encode %{ |
| 11295 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister); | |
| 11296 %} | |
| 0 | 11297 ins_pipe( pipe_slow ); |
| 11298 %} | |
| 11299 | |
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11300 instruct MoveF2I_reg_reg_sse(rRegI dst, regF src) %{ |
| 0 | 11301 predicate(UseSSE>=2); |
| 11302 match(Set dst (MoveF2I src)); | |
| 11303 effect( DEF dst, USE src ); | |
| 11304 ins_cost(85); | |
| 11305 format %{ "MOVD $dst,$src\t# MoveF2I_reg_reg_sse" %} | |
| 4759 | 11306 ins_encode %{ |
| 11307 __ movdl($dst$$Register, $src$$XMMRegister); | |
| 11308 %} | |
| 0 | 11309 ins_pipe( pipe_slow ); |
| 11310 %} | |
| 11311 | |
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11312 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{ |
| 0 | 11313 match(Set dst (MoveI2F src)); |
| 11314 effect( DEF dst, USE src ); | |
| 11315 | |
| 11316 ins_cost(100); | |
| 11317 format %{ "MOV $dst,$src\t# MoveI2F_reg_stack" %} | |
| 4759 | 11318 ins_encode %{ |
| 11319 __ movl(Address(rsp, $dst$$disp), $src$$Register); | |
| 11320 %} | |
| 0 | 11321 ins_pipe( ialu_mem_reg ); |
| 11322 %} | |
| 11323 | |
| 11324 | |
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11325 instruct MoveI2FPR_stack_reg(regFPR dst, stackSlotI src) %{ |
| 0 | 11326 predicate(UseSSE==0); |
| 11327 match(Set dst (MoveI2F src)); | |
| 11328 effect(DEF dst, USE src); | |
| 11329 | |
| 11330 ins_cost(125); | |
| 11331 format %{ "FLD_S $src\n\t" | |
| 11332 "FSTP $dst\t# MoveI2F_stack_reg" %} | |
| 11333 opcode(0xD9); /* D9 /0, FLD m32real */ | |
| 11334 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src), | |
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11335 Pop_Reg_FPR(dst) ); |
| 0 | 11336 ins_pipe( fpu_reg_mem ); |
| 11337 %} | |
| 11338 | |
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11339 instruct MoveI2F_stack_reg_sse(regF dst, stackSlotI src) %{ |
| 0 | 11340 predicate(UseSSE>=1); |
| 11341 match(Set dst (MoveI2F src)); | |
| 11342 effect( DEF dst, USE src ); | |
| 11343 | |
| 11344 ins_cost(95); | |
| 11345 format %{ "MOVSS $dst,$src\t# MoveI2F_stack_reg_sse" %} | |
| 4759 | 11346 ins_encode %{ |
| 11347 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp)); | |
| 11348 %} | |
| 0 | 11349 ins_pipe( pipe_slow ); |
| 11350 %} | |
| 11351 | |
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11352 instruct MoveI2F_reg_reg_sse(regF dst, rRegI src) %{ |
| 0 | 11353 predicate(UseSSE>=2); |
| 11354 match(Set dst (MoveI2F src)); | |
| 11355 effect( DEF dst, USE src ); | |
| 11356 | |
| 11357 ins_cost(85); | |
| 11358 format %{ "MOVD $dst,$src\t# MoveI2F_reg_reg_sse" %} | |
| 4759 | 11359 ins_encode %{ |
| 11360 __ movdl($dst$$XMMRegister, $src$$Register); | |
| 11361 %} | |
| 0 | 11362 ins_pipe( pipe_slow ); |
| 11363 %} | |
| 11364 | |
| 11365 instruct MoveD2L_stack_reg(eRegL dst, stackSlotD src) %{ | |
| 11366 match(Set dst (MoveD2L src)); | |
| 11367 effect(DEF dst, USE src); | |
| 11368 | |
| 11369 ins_cost(250); | |
| 11370 format %{ "MOV $dst.lo,$src\n\t" | |
| 11371 "MOV $dst.hi,$src+4\t# MoveD2L_stack_reg" %} | |
| 11372 opcode(0x8B, 0x8B); | |
| 11373 ins_encode( OpcP, RegMem(dst,src), OpcS, RegMem_Hi(dst,src)); | |
| 11374 ins_pipe( ialu_mem_long_reg ); | |
| 11375 %} | |
| 11376 | |
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11377 instruct MoveDPR2L_reg_stack(stackSlotL dst, regDPR src) %{ |
| 0 | 11378 predicate(UseSSE<=1); |
| 11379 match(Set dst (MoveD2L src)); | |
| 11380 effect(DEF dst, USE src); | |
| 11381 | |
| 11382 ins_cost(125); | |
| 11383 format %{ "FST_D $dst,$src\t# MoveD2L_reg_stack" %} | |
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11384 ins_encode( Pop_Mem_Reg_DPR(dst, src) ); |
| 0 | 11385 ins_pipe( fpu_mem_reg ); |
| 11386 %} | |
| 11387 | |
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11388 instruct MoveD2L_reg_stack_sse(stackSlotL dst, regD src) %{ |
| 0 | 11389 predicate(UseSSE>=2); |
| 11390 match(Set dst (MoveD2L src)); | |
| 11391 effect(DEF dst, USE src); | |
| 11392 ins_cost(95); | |
| 11393 format %{ "MOVSD $dst,$src\t# MoveD2L_reg_stack_sse" %} | |
| 4759 | 11394 ins_encode %{ |
| 11395 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister); | |
| 11396 %} | |
| 0 | 11397 ins_pipe( pipe_slow ); |
| 11398 %} | |
| 11399 | |
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11400 instruct MoveD2L_reg_reg_sse(eRegL dst, regD src, regD tmp) %{ |
| 0 | 11401 predicate(UseSSE>=2); |
| 11402 match(Set dst (MoveD2L src)); | |
| 11403 effect(DEF dst, USE src, TEMP tmp); | |
| 11404 ins_cost(85); | |
| 11405 format %{ "MOVD $dst.lo,$src\n\t" | |
| 11406 "PSHUFLW $tmp,$src,0x4E\n\t" | |
| 11407 "MOVD $dst.hi,$tmp\t# MoveD2L_reg_reg_sse" %} | |
| 4759 | 11408 ins_encode %{ |
| 11409 __ movdl($dst$$Register, $src$$XMMRegister); | |
| 11410 __ pshuflw($tmp$$XMMRegister, $src$$XMMRegister, 0x4e); | |
| 11411 __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister); | |
| 11412 %} | |
| 0 | 11413 ins_pipe( pipe_slow ); |
| 11414 %} | |
| 11415 | |
| 11416 instruct MoveL2D_reg_stack(stackSlotD dst, eRegL src) %{ | |
| 11417 match(Set dst (MoveL2D src)); | |
| 11418 effect(DEF dst, USE src); | |
| 11419 | |
| 11420 ins_cost(200); | |
| 11421 format %{ "MOV $dst,$src.lo\n\t" | |
| 11422 "MOV $dst+4,$src.hi\t# MoveL2D_reg_stack" %} | |
| 11423 opcode(0x89, 0x89); | |
| 11424 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) ); | |
| 11425 ins_pipe( ialu_mem_long_reg ); | |
| 11426 %} | |
| 11427 | |
| 11428 | |
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11429 instruct MoveL2DPR_stack_reg(regDPR dst, stackSlotL src) %{ |
| 0 | 11430 predicate(UseSSE<=1); |
| 11431 match(Set dst (MoveL2D src)); | |
| 11432 effect(DEF dst, USE src); | |
| 11433 ins_cost(125); | |
| 11434 | |
| 11435 format %{ "FLD_D $src\n\t" | |
| 11436 "FSTP $dst\t# MoveL2D_stack_reg" %} | |
| 11437 opcode(0xDD); /* DD /0, FLD m64real */ | |
| 11438 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src), | |
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11439 Pop_Reg_DPR(dst) ); |
| 0 | 11440 ins_pipe( fpu_reg_mem ); |
| 11441 %} | |
| 11442 | |
| 11443 | |
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11444 instruct MoveL2D_stack_reg_sse(regD dst, stackSlotL src) %{ |
| 0 | 11445 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper); |
| 11446 match(Set dst (MoveL2D src)); | |
| 11447 effect(DEF dst, USE src); | |
| 11448 | |
| 11449 ins_cost(95); | |
| 11450 format %{ "MOVSD $dst,$src\t# MoveL2D_stack_reg_sse" %} | |
| 4759 | 11451 ins_encode %{ |
| 11452 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp)); | |
| 11453 %} | |
| 0 | 11454 ins_pipe( pipe_slow ); |
| 11455 %} | |
| 11456 | |
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11457 instruct MoveL2D_stack_reg_sse_partial(regD dst, stackSlotL src) %{ |
| 0 | 11458 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper); |
| 11459 match(Set dst (MoveL2D src)); | |
| 11460 effect(DEF dst, USE src); | |
| 11461 | |
| 11462 ins_cost(95); | |
| 11463 format %{ "MOVLPD $dst,$src\t# MoveL2D_stack_reg_sse" %} | |
| 4759 | 11464 ins_encode %{ |
| 11465 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp)); | |
| 11466 %} | |
| 0 | 11467 ins_pipe( pipe_slow ); |
| 11468 %} | |
| 11469 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11470 instruct MoveL2D_reg_reg_sse(regD dst, eRegL src, regD tmp) %{ |
| 0 | 11471 predicate(UseSSE>=2); |
| 11472 match(Set dst (MoveL2D src)); | |
| 11473 effect(TEMP dst, USE src, TEMP tmp); | |
| 11474 ins_cost(85); | |
| 11475 format %{ "MOVD $dst,$src.lo\n\t" | |
| 11476 "MOVD $tmp,$src.hi\n\t" | |
| 11477 "PUNPCKLDQ $dst,$tmp\t# MoveL2D_reg_reg_sse" %} | |
| 4759 | 11478 ins_encode %{ |
| 11479 __ movdl($dst$$XMMRegister, $src$$Register); | |
| 11480 __ movdl($tmp$$XMMRegister, HIGH_FROM_LOW($src$$Register)); | |
| 11481 __ punpckldq($dst$$XMMRegister, $tmp$$XMMRegister); | |
| 11482 %} | |
| 0 | 11483 ins_pipe( pipe_slow ); |
| 11484 %} | |
| 11485 | |
| 11486 | |
| 11487 // ======================================================================= | |
| 11488 // fast clearing of an array | |
| 11489 instruct rep_stos(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{ | |
|
7474
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6853
diff
changeset
|
11490 predicate(!UseFastStosb); |
| 0 | 11491 match(Set dummy (ClearArray cnt base)); |
| 11492 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr); | |
|
7474
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6853
diff
changeset
|
11493 format %{ "XOR EAX,EAX\t# ClearArray:\n\t" |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6853
diff
changeset
|
11494 "SHL ECX,1\t# Convert doublewords to words\n\t" |
| 0 | 11495 "REP STOS\t# store EAX into [EDI++] while ECX--" %} |
|
7474
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6853
diff
changeset
|
11496 ins_encode %{ |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6853
diff
changeset
|
11497 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register); |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6853
diff
changeset
|
11498 %} |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6853
diff
changeset
|
11499 ins_pipe( pipe_slow ); |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6853
diff
changeset
|
11500 %} |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6853
diff
changeset
|
11501 |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6853
diff
changeset
|
11502 instruct rep_fast_stosb(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{ |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6853
diff
changeset
|
11503 predicate(UseFastStosb); |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6853
diff
changeset
|
11504 match(Set dummy (ClearArray cnt base)); |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6853
diff
changeset
|
11505 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr); |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6853
diff
changeset
|
11506 format %{ "XOR EAX,EAX\t# ClearArray:\n\t" |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6853
diff
changeset
|
11507 "SHL ECX,3\t# Convert doublewords to bytes\n\t" |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6853
diff
changeset
|
11508 "REP STOSB\t# store EAX into [EDI++] while ECX--" %} |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6853
diff
changeset
|
11509 ins_encode %{ |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6853
diff
changeset
|
11510 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register); |
|
00af3a3a8df4
8005522: use fast-string instructions on x86 for zeroing
kvn
parents:
6853
diff
changeset
|
11511 %} |
| 0 | 11512 ins_pipe( pipe_slow ); |
| 11513 %} | |
| 11514 | |
| 2262 | 11515 instruct string_compare(eDIRegP str1, eCXRegI cnt1, eSIRegP str2, eDXRegI cnt2, |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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4759
diff
changeset
|
11516 eAXRegI result, regD tmp1, eFlagsReg cr) %{ |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11517 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); |
| 2262 | 11518 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr); |
| 11519 | |
| 11520 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %} | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11521 ins_encode %{ |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11522 __ string_compare($str1$$Register, $str2$$Register, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11523 $cnt1$$Register, $cnt2$$Register, $result$$Register, |
| 2262 | 11524 $tmp1$$XMMRegister); |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11525 %} |
| 681 | 11526 ins_pipe( pipe_slow ); |
| 11527 %} | |
| 11528 | |
| 11529 // fast string equals | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11530 instruct string_equals(eDIRegP str1, eSIRegP str2, eCXRegI cnt, eAXRegI result, |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11531 regD tmp1, regD tmp2, eBXRegI tmp3, eFlagsReg cr) %{ |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11532 match(Set result (StrEquals (Binary str1 str2) cnt)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11533 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11534 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11535 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %} |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11536 ins_encode %{ |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11537 __ char_arrays_equals(false, $str1$$Register, $str2$$Register, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11538 $cnt$$Register, $result$$Register, $tmp3$$Register, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11539 $tmp1$$XMMRegister, $tmp2$$XMMRegister); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11540 %} |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11541 ins_pipe( pipe_slow ); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11542 %} |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11543 |
|
2320
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11544 // fast search of substring with known size. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11545 instruct string_indexof_con(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, immI int_cnt2, |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11546 eBXRegI result, regD vec, eAXRegI cnt2, eCXRegI tmp, eFlagsReg cr) %{ |
|
2320
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11547 predicate(UseSSE42Intrinsics); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11548 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2))); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11549 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11550 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11551 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %} |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11552 ins_encode %{ |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11553 int icnt2 = (int)$int_cnt2$$constant; |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11554 if (icnt2 >= 8) { |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11555 // IndexOf for constant substrings with size >= 8 elements |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11556 // which don't need to be loaded through stack. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11557 __ string_indexofC8($str1$$Register, $str2$$Register, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11558 $cnt1$$Register, $cnt2$$Register, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11559 icnt2, $result$$Register, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11560 $vec$$XMMRegister, $tmp$$Register); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11561 } else { |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11562 // Small strings are loaded through stack if they cross page boundary. |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11563 __ string_indexof($str1$$Register, $str2$$Register, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11564 $cnt1$$Register, $cnt2$$Register, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11565 icnt2, $result$$Register, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11566 $vec$$XMMRegister, $tmp$$Register); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11567 } |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11568 %} |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11569 ins_pipe( pipe_slow ); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11570 %} |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11571 |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11572 instruct string_indexof(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, eAXRegI cnt2, |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11573 eBXRegI result, regD vec, eCXRegI tmp, eFlagsReg cr) %{ |
| 681 | 11574 predicate(UseSSE42Intrinsics); |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11575 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2))); |
|
2320
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11576 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr); |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11577 |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11578 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %} |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11579 ins_encode %{ |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11580 __ string_indexof($str1$$Register, $str2$$Register, |
|
2320
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11581 $cnt1$$Register, $cnt2$$Register, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11582 (-1), $result$$Register, |
|
41d4973cf100
6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents:
2262
diff
changeset
|
11583 $vec$$XMMRegister, $tmp$$Register); |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11584 %} |
| 0 | 11585 ins_pipe( pipe_slow ); |
| 11586 %} | |
| 11587 | |
|
169
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
11588 // fast array equals |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11589 instruct array_equals(eDIRegP ary1, eSIRegP ary2, eAXRegI result, |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
11590 regD tmp1, regD tmp2, eCXRegI tmp3, eBXRegI tmp4, eFlagsReg cr) |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11591 %{ |
|
169
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
11592 match(Set result (AryEq ary1 ary2)); |
| 681 | 11593 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr); |
|
169
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
11594 //ins_cost(300); |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
11595 |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11596 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %} |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11597 ins_encode %{ |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11598 __ char_arrays_equals(true, $ary1$$Register, $ary2$$Register, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11599 $tmp3$$Register, $result$$Register, $tmp4$$Register, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11600 $tmp1$$XMMRegister, $tmp2$$XMMRegister); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
824
diff
changeset
|
11601 %} |
|
169
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
11602 ins_pipe( pipe_slow ); |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
11603 %} |
|
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
113
diff
changeset
|
11604 |
|
7637
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
11605 // encode char[] to byte[] in ISO_8859_1 |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
11606 instruct encode_iso_array(eSIRegP src, eDIRegP dst, eDXRegI len, |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
11607 regD tmp1, regD tmp2, regD tmp3, regD tmp4, |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
11608 eCXRegI tmp5, eAXRegI result, eFlagsReg cr) %{ |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7474
diff
changeset
|
11609 match(Set result (EncodeISOArray src (Binary dst len))); |
|
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11610 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr); |
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11611 |
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11612 format %{ "Encode array $src,$dst,$len -> $result // KILL ECX, EDX, $tmp1, $tmp2, $tmp3, $tmp4, ESI, EDI " %} |
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11613 ins_encode %{ |
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11614 __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register, |
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11615 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister, |
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11616 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register); |
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11617 %} |
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11618 ins_pipe( pipe_slow ); |
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11619 %} |
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11620 |
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11621 |
| 0 | 11622 //----------Control Flow Instructions------------------------------------------ |
| 11623 // Signed compare Instructions | |
|
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11624 instruct compI_eReg(eFlagsReg cr, rRegI op1, rRegI op2) %{ |
| 0 | 11625 match(Set cr (CmpI op1 op2)); |
| 11626 effect( DEF cr, USE op1, USE op2 ); | |
| 11627 format %{ "CMP $op1,$op2" %} | |
| 11628 opcode(0x3B); /* Opcode 3B /r */ | |
| 11629 ins_encode( OpcP, RegReg( op1, op2) ); | |
| 11630 ins_pipe( ialu_cr_reg_reg ); | |
| 11631 %} | |
| 11632 | |
|
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11633 instruct compI_eReg_imm(eFlagsReg cr, rRegI op1, immI op2) %{ |
| 0 | 11634 match(Set cr (CmpI op1 op2)); |
| 11635 effect( DEF cr, USE op1 ); | |
| 11636 format %{ "CMP $op1,$op2" %} | |
| 11637 opcode(0x81,0x07); /* Opcode 81 /7 */ | |
| 11638 // ins_encode( RegImm( op1, op2) ); /* Was CmpImm */ | |
| 11639 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) ); | |
| 11640 ins_pipe( ialu_cr_reg_imm ); | |
| 11641 %} | |
| 11642 | |
| 11643 // Cisc-spilled version of cmpI_eReg | |
|
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11644 instruct compI_eReg_mem(eFlagsReg cr, rRegI op1, memory op2) %{ |
| 0 | 11645 match(Set cr (CmpI op1 (LoadI op2))); |
| 11646 | |
| 11647 format %{ "CMP $op1,$op2" %} | |
| 11648 ins_cost(500); | |
| 11649 opcode(0x3B); /* Opcode 3B /r */ | |
| 11650 ins_encode( OpcP, RegMem( op1, op2) ); | |
| 11651 ins_pipe( ialu_cr_reg_mem ); | |
| 11652 %} | |
| 11653 | |
|
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11654 instruct testI_reg( eFlagsReg cr, rRegI src, immI0 zero ) %{ |
| 0 | 11655 match(Set cr (CmpI src zero)); |
| 11656 effect( DEF cr, USE src ); | |
| 11657 | |
| 11658 format %{ "TEST $src,$src" %} | |
| 11659 opcode(0x85); | |
| 11660 ins_encode( OpcP, RegReg( src, src ) ); | |
| 11661 ins_pipe( ialu_cr_reg_imm ); | |
| 11662 %} | |
| 11663 | |
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11664 instruct testI_reg_imm( eFlagsReg cr, rRegI src, immI con, immI0 zero ) %{ |
| 0 | 11665 match(Set cr (CmpI (AndI src con) zero)); |
| 11666 | |
| 11667 format %{ "TEST $src,$con" %} | |
| 11668 opcode(0xF7,0x00); | |
| 11669 ins_encode( OpcP, RegOpc(src), Con32(con) ); | |
| 11670 ins_pipe( ialu_cr_reg_imm ); | |
| 11671 %} | |
| 11672 | |
|
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11673 instruct testI_reg_mem( eFlagsReg cr, rRegI src, memory mem, immI0 zero ) %{ |
| 0 | 11674 match(Set cr (CmpI (AndI src mem) zero)); |
| 11675 | |
| 11676 format %{ "TEST $src,$mem" %} | |
| 11677 opcode(0x85); | |
| 11678 ins_encode( OpcP, RegMem( src, mem ) ); | |
| 11679 ins_pipe( ialu_cr_reg_mem ); | |
| 11680 %} | |
| 11681 | |
| 11682 // Unsigned compare Instructions; really, same as signed except they | |
| 11683 // produce an eFlagsRegU instead of eFlagsReg. | |
|
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11684 instruct compU_eReg(eFlagsRegU cr, rRegI op1, rRegI op2) %{ |
| 0 | 11685 match(Set cr (CmpU op1 op2)); |
| 11686 | |
| 11687 format %{ "CMPu $op1,$op2" %} | |
| 11688 opcode(0x3B); /* Opcode 3B /r */ | |
| 11689 ins_encode( OpcP, RegReg( op1, op2) ); | |
| 11690 ins_pipe( ialu_cr_reg_reg ); | |
| 11691 %} | |
| 11692 | |
|
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11693 instruct compU_eReg_imm(eFlagsRegU cr, rRegI op1, immI op2) %{ |
| 0 | 11694 match(Set cr (CmpU op1 op2)); |
| 11695 | |
| 11696 format %{ "CMPu $op1,$op2" %} | |
| 11697 opcode(0x81,0x07); /* Opcode 81 /7 */ | |
| 11698 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) ); | |
| 11699 ins_pipe( ialu_cr_reg_imm ); | |
| 11700 %} | |
| 11701 | |
| 11702 // // Cisc-spilled version of cmpU_eReg | |
|
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11703 instruct compU_eReg_mem(eFlagsRegU cr, rRegI op1, memory op2) %{ |
| 0 | 11704 match(Set cr (CmpU op1 (LoadI op2))); |
| 11705 | |
| 11706 format %{ "CMPu $op1,$op2" %} | |
| 11707 ins_cost(500); | |
| 11708 opcode(0x3B); /* Opcode 3B /r */ | |
| 11709 ins_encode( OpcP, RegMem( op1, op2) ); | |
| 11710 ins_pipe( ialu_cr_reg_mem ); | |
| 11711 %} | |
| 11712 | |
| 11713 // // Cisc-spilled version of cmpU_eReg | |
|
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11714 //instruct compU_mem_eReg(eFlagsRegU cr, memory op1, rRegI op2) %{ |
| 0 | 11715 // match(Set cr (CmpU (LoadI op1) op2)); |
| 11716 // | |
| 11717 // format %{ "CMPu $op1,$op2" %} | |
| 11718 // ins_cost(500); | |
| 11719 // opcode(0x39); /* Opcode 39 /r */ | |
| 11720 // ins_encode( OpcP, RegMem( op1, op2) ); | |
| 11721 //%} | |
| 11722 | |
|
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11723 instruct testU_reg( eFlagsRegU cr, rRegI src, immI0 zero ) %{ |
| 0 | 11724 match(Set cr (CmpU src zero)); |
| 11725 | |
| 11726 format %{ "TESTu $src,$src" %} | |
| 11727 opcode(0x85); | |
| 11728 ins_encode( OpcP, RegReg( src, src ) ); | |
| 11729 ins_pipe( ialu_cr_reg_imm ); | |
| 11730 %} | |
| 11731 | |
| 11732 // Unsigned pointer compare Instructions | |
| 11733 instruct compP_eReg(eFlagsRegU cr, eRegP op1, eRegP op2) %{ | |
| 11734 match(Set cr (CmpP op1 op2)); | |
| 11735 | |
| 11736 format %{ "CMPu $op1,$op2" %} | |
| 11737 opcode(0x3B); /* Opcode 3B /r */ | |
| 11738 ins_encode( OpcP, RegReg( op1, op2) ); | |
| 11739 ins_pipe( ialu_cr_reg_reg ); | |
| 11740 %} | |
| 11741 | |
| 11742 instruct compP_eReg_imm(eFlagsRegU cr, eRegP op1, immP op2) %{ | |
| 11743 match(Set cr (CmpP op1 op2)); | |
| 11744 | |
| 11745 format %{ "CMPu $op1,$op2" %} | |
| 11746 opcode(0x81,0x07); /* Opcode 81 /7 */ | |
| 11747 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) ); | |
| 11748 ins_pipe( ialu_cr_reg_imm ); | |
| 11749 %} | |
| 11750 | |
| 11751 // // Cisc-spilled version of cmpP_eReg | |
| 11752 instruct compP_eReg_mem(eFlagsRegU cr, eRegP op1, memory op2) %{ | |
| 11753 match(Set cr (CmpP op1 (LoadP op2))); | |
| 11754 | |
| 11755 format %{ "CMPu $op1,$op2" %} | |
| 11756 ins_cost(500); | |
| 11757 opcode(0x3B); /* Opcode 3B /r */ | |
| 11758 ins_encode( OpcP, RegMem( op1, op2) ); | |
| 11759 ins_pipe( ialu_cr_reg_mem ); | |
| 11760 %} | |
| 11761 | |
| 11762 // // Cisc-spilled version of cmpP_eReg | |
| 11763 //instruct compP_mem_eReg(eFlagsRegU cr, memory op1, eRegP op2) %{ | |
| 11764 // match(Set cr (CmpP (LoadP op1) op2)); | |
| 11765 // | |
| 11766 // format %{ "CMPu $op1,$op2" %} | |
| 11767 // ins_cost(500); | |
| 11768 // opcode(0x39); /* Opcode 39 /r */ | |
| 11769 // ins_encode( OpcP, RegMem( op1, op2) ); | |
| 11770 //%} | |
| 11771 | |
| 11772 // Compare raw pointer (used in out-of-heap check). | |
| 11773 // Only works because non-oop pointers must be raw pointers | |
| 11774 // and raw pointers have no anti-dependencies. | |
| 11775 instruct compP_mem_eReg( eFlagsRegU cr, eRegP op1, memory op2 ) %{ | |
|
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11776 predicate( n->in(2)->in(2)->bottom_type()->reloc() == relocInfo::none ); |
| 0 | 11777 match(Set cr (CmpP op1 (LoadP op2))); |
| 11778 | |
| 11779 format %{ "CMPu $op1,$op2" %} | |
| 11780 opcode(0x3B); /* Opcode 3B /r */ | |
| 11781 ins_encode( OpcP, RegMem( op1, op2) ); | |
| 11782 ins_pipe( ialu_cr_reg_mem ); | |
| 11783 %} | |
| 11784 | |
| 11785 // | |
| 11786 // This will generate a signed flags result. This should be ok | |
| 11787 // since any compare to a zero should be eq/neq. | |
| 11788 instruct testP_reg( eFlagsReg cr, eRegP src, immP0 zero ) %{ | |
| 11789 match(Set cr (CmpP src zero)); | |
| 11790 | |
| 11791 format %{ "TEST $src,$src" %} | |
| 11792 opcode(0x85); | |
| 11793 ins_encode( OpcP, RegReg( src, src ) ); | |
| 11794 ins_pipe( ialu_cr_reg_imm ); | |
| 11795 %} | |
| 11796 | |
| 11797 // Cisc-spilled version of testP_reg | |
| 11798 // This will generate a signed flags result. This should be ok | |
| 11799 // since any compare to a zero should be eq/neq. | |
| 11800 instruct testP_Reg_mem( eFlagsReg cr, memory op, immI0 zero ) %{ | |
| 11801 match(Set cr (CmpP (LoadP op) zero)); | |
| 11802 | |
| 11803 format %{ "TEST $op,0xFFFFFFFF" %} | |
| 11804 ins_cost(500); | |
| 11805 opcode(0xF7); /* Opcode F7 /0 */ | |
| 11806 ins_encode( OpcP, RMopc_Mem(0x00,op), Con_d32(0xFFFFFFFF) ); | |
| 11807 ins_pipe( ialu_cr_reg_imm ); | |
| 11808 %} | |
| 11809 | |
| 11810 // Yanked all unsigned pointer compare operations. | |
| 11811 // Pointer compares are done with CmpP which is already unsigned. | |
| 11812 | |
| 11813 //----------Max and Min-------------------------------------------------------- | |
| 11814 // Min Instructions | |
| 11815 //// | |
| 11816 // *** Min and Max using the conditional move are slower than the | |
| 11817 // *** branch version on a Pentium III. | |
| 11818 // // Conditional move for min | |
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11819 //instruct cmovI_reg_lt( rRegI op2, rRegI op1, eFlagsReg cr ) %{ |
| 0 | 11820 // effect( USE_DEF op2, USE op1, USE cr ); |
| 11821 // format %{ "CMOVlt $op2,$op1\t! min" %} | |
| 11822 // opcode(0x4C,0x0F); | |
| 11823 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) ); | |
| 11824 // ins_pipe( pipe_cmov_reg ); | |
| 11825 //%} | |
| 11826 // | |
| 11827 //// Min Register with Register (P6 version) | |
|
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11828 //instruct minI_eReg_p6( rRegI op1, rRegI op2 ) %{ |
| 0 | 11829 // predicate(VM_Version::supports_cmov() ); |
| 11830 // match(Set op2 (MinI op1 op2)); | |
| 11831 // ins_cost(200); | |
| 11832 // expand %{ | |
| 11833 // eFlagsReg cr; | |
| 11834 // compI_eReg(cr,op1,op2); | |
| 11835 // cmovI_reg_lt(op2,op1,cr); | |
| 11836 // %} | |
| 11837 //%} | |
| 11838 | |
| 11839 // Min Register with Register (generic version) | |
|
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11840 instruct minI_eReg(rRegI dst, rRegI src, eFlagsReg flags) %{ |
| 0 | 11841 match(Set dst (MinI dst src)); |
| 11842 effect(KILL flags); | |
| 11843 ins_cost(300); | |
| 11844 | |
| 11845 format %{ "MIN $dst,$src" %} | |
| 11846 opcode(0xCC); | |
| 11847 ins_encode( min_enc(dst,src) ); | |
| 11848 ins_pipe( pipe_slow ); | |
| 11849 %} | |
| 11850 | |
| 11851 // Max Register with Register | |
| 11852 // *** Min and Max using the conditional move are slower than the | |
| 11853 // *** branch version on a Pentium III. | |
| 11854 // // Conditional move for max | |
|
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11855 //instruct cmovI_reg_gt( rRegI op2, rRegI op1, eFlagsReg cr ) %{ |
| 0 | 11856 // effect( USE_DEF op2, USE op1, USE cr ); |
| 11857 // format %{ "CMOVgt $op2,$op1\t! max" %} | |
| 11858 // opcode(0x4F,0x0F); | |
| 11859 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) ); | |
| 11860 // ins_pipe( pipe_cmov_reg ); | |
| 11861 //%} | |
| 11862 // | |
| 11863 // // Max Register with Register (P6 version) | |
|
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11864 //instruct maxI_eReg_p6( rRegI op1, rRegI op2 ) %{ |
| 0 | 11865 // predicate(VM_Version::supports_cmov() ); |
| 11866 // match(Set op2 (MaxI op1 op2)); | |
| 11867 // ins_cost(200); | |
| 11868 // expand %{ | |
| 11869 // eFlagsReg cr; | |
| 11870 // compI_eReg(cr,op1,op2); | |
| 11871 // cmovI_reg_gt(op2,op1,cr); | |
| 11872 // %} | |
| 11873 //%} | |
| 11874 | |
| 11875 // Max Register with Register (generic version) | |
|
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11876 instruct maxI_eReg(rRegI dst, rRegI src, eFlagsReg flags) %{ |
| 0 | 11877 match(Set dst (MaxI dst src)); |
| 11878 effect(KILL flags); | |
| 11879 ins_cost(300); | |
| 11880 | |
| 11881 format %{ "MAX $dst,$src" %} | |
| 11882 opcode(0xCC); | |
| 11883 ins_encode( max_enc(dst,src) ); | |
| 11884 ins_pipe( pipe_slow ); | |
| 11885 %} | |
| 11886 | |
| 11887 // ============================================================================ | |
| 3345 | 11888 // Counted Loop limit node which represents exact final iterator value. |
| 11889 // Note: the resulting value should fit into integer range since | |
| 11890 // counted loops have limit check on overflow. | |
| 11891 instruct loopLimit_eReg(eAXRegI limit, nadxRegI init, immI stride, eDXRegI limit_hi, nadxRegI tmp, eFlagsReg flags) %{ | |
| 11892 match(Set limit (LoopLimit (Binary init limit) stride)); | |
| 11893 effect(TEMP limit_hi, TEMP tmp, KILL flags); | |
| 11894 ins_cost(300); | |
| 11895 | |
| 11896 format %{ "loopLimit $init,$limit,$stride # $limit = $init + $stride *( $limit - $init + $stride -1)/ $stride, kills $limit_hi" %} | |
| 11897 ins_encode %{ | |
| 11898 int strd = (int)$stride$$constant; | |
| 11899 assert(strd != 1 && strd != -1, "sanity"); | |
| 11900 int m1 = (strd > 0) ? 1 : -1; | |
| 11901 // Convert limit to long (EAX:EDX) | |
| 11902 __ cdql(); | |
| 11903 // Convert init to long (init:tmp) | |
| 11904 __ movl($tmp$$Register, $init$$Register); | |
| 11905 __ sarl($tmp$$Register, 31); | |
| 11906 // $limit - $init | |
| 11907 __ subl($limit$$Register, $init$$Register); | |
| 11908 __ sbbl($limit_hi$$Register, $tmp$$Register); | |
| 11909 // + ($stride - 1) | |
| 11910 if (strd > 0) { | |
| 11911 __ addl($limit$$Register, (strd - 1)); | |
| 11912 __ adcl($limit_hi$$Register, 0); | |
| 11913 __ movl($tmp$$Register, strd); | |
| 11914 } else { | |
| 11915 __ addl($limit$$Register, (strd + 1)); | |
| 11916 __ adcl($limit_hi$$Register, -1); | |
| 11917 __ lneg($limit_hi$$Register, $limit$$Register); | |
| 11918 __ movl($tmp$$Register, -strd); | |
| 11919 } | |
| 11920 // signed devision: (EAX:EDX) / pos_stride | |
| 11921 __ idivl($tmp$$Register); | |
| 11922 if (strd < 0) { | |
| 11923 // restore sign | |
| 11924 __ negl($tmp$$Register); | |
| 11925 } | |
| 11926 // (EAX) * stride | |
| 11927 __ mull($tmp$$Register); | |
| 11928 // + init (ignore upper bits) | |
| 11929 __ addl($limit$$Register, $init$$Register); | |
| 11930 %} | |
| 11931 ins_pipe( pipe_slow ); | |
| 11932 %} | |
| 11933 | |
| 11934 // ============================================================================ | |
| 0 | 11935 // Branch Instructions |
| 11936 // Jump Table | |
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11937 instruct jumpXtnd(rRegI switch_val) %{ |
| 0 | 11938 match(Jump switch_val); |
| 11939 ins_cost(350); | |
| 2008 | 11940 format %{ "JMP [$constantaddress](,$switch_val,1)\n\t" %} |
| 11941 ins_encode %{ | |
| 0 | 11942 // Jump to Address(table_base + switch_reg) |
| 11943 Address index(noreg, $switch_val$$Register, Address::times_1); | |
| 2008 | 11944 __ jump(ArrayAddress($constantaddress, index)); |
| 0 | 11945 %} |
| 11946 ins_pipe(pipe_jmp); | |
| 11947 %} | |
| 11948 | |
| 11949 // Jump Direct - Label defines a relative address from JMP+1 | |
| 11950 instruct jmpDir(label labl) %{ | |
| 11951 match(Goto); | |
| 11952 effect(USE labl); | |
| 11953 | |
| 11954 ins_cost(300); | |
| 11955 format %{ "JMP $labl" %} | |
| 11956 size(5); | |
| 3851 | 11957 ins_encode %{ |
| 11958 Label* L = $labl$$label; | |
| 11959 __ jmp(*L, false); // Always long jump | |
| 11960 %} | |
| 0 | 11961 ins_pipe( pipe_jmp ); |
| 11962 %} | |
| 11963 | |
| 11964 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 11965 instruct jmpCon(cmpOp cop, eFlagsReg cr, label labl) %{ | |
| 11966 match(If cop cr); | |
| 11967 effect(USE labl); | |
| 11968 | |
| 11969 ins_cost(300); | |
| 11970 format %{ "J$cop $labl" %} | |
| 11971 size(6); | |
| 3851 | 11972 ins_encode %{ |
| 11973 Label* L = $labl$$label; | |
| 11974 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 11975 %} | |
| 0 | 11976 ins_pipe( pipe_jcc ); |
| 11977 %} | |
| 11978 | |
| 11979 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 11980 instruct jmpLoopEnd(cmpOp cop, eFlagsReg cr, label labl) %{ | |
| 11981 match(CountedLoopEnd cop cr); | |
| 11982 effect(USE labl); | |
| 11983 | |
| 11984 ins_cost(300); | |
| 11985 format %{ "J$cop $labl\t# Loop end" %} | |
| 11986 size(6); | |
| 3851 | 11987 ins_encode %{ |
| 11988 Label* L = $labl$$label; | |
| 11989 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 11990 %} | |
| 0 | 11991 ins_pipe( pipe_jcc ); |
| 11992 %} | |
| 11993 | |
| 11994 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 11995 instruct jmpLoopEndU(cmpOpU cop, eFlagsRegU cmp, label labl) %{ | |
| 11996 match(CountedLoopEnd cop cmp); | |
| 11997 effect(USE labl); | |
| 11998 | |
| 11999 ins_cost(300); | |
| 12000 format %{ "J$cop,u $labl\t# Loop end" %} | |
| 12001 size(6); | |
| 3851 | 12002 ins_encode %{ |
| 12003 Label* L = $labl$$label; | |
| 12004 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 12005 %} | |
| 0 | 12006 ins_pipe( pipe_jcc ); |
| 12007 %} | |
| 12008 | |
|
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|
12009 instruct jmpLoopEndUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{ |
|
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|
12010 match(CountedLoopEnd cop cmp); |
|
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|
12011 effect(USE labl); |
|
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|
12012 |
|
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|
12013 ins_cost(200); |
|
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|
12014 format %{ "J$cop,u $labl\t# Loop end" %} |
|
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|
12015 size(6); |
| 3851 | 12016 ins_encode %{ |
| 12017 Label* L = $labl$$label; | |
| 12018 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 12019 %} | |
|
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|
12020 ins_pipe( pipe_jcc ); |
|
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|
12021 %} |
|
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|
12022 |
| 0 | 12023 // Jump Direct Conditional - using unsigned comparison |
| 12024 instruct jmpConU(cmpOpU cop, eFlagsRegU cmp, label labl) %{ | |
| 12025 match(If cop cmp); | |
| 12026 effect(USE labl); | |
| 12027 | |
| 12028 ins_cost(300); | |
| 12029 format %{ "J$cop,u $labl" %} | |
| 12030 size(6); | |
| 3851 | 12031 ins_encode %{ |
| 12032 Label* L = $labl$$label; | |
| 12033 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 12034 %} | |
|
415
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|
12035 ins_pipe(pipe_jcc); |
|
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|
12036 %} |
|
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|
12037 |
|
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|
12038 instruct jmpConUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{ |
|
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|
12039 match(If cop cmp); |
|
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diff
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|
12040 effect(USE labl); |
|
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|
12041 |
|
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|
12042 ins_cost(200); |
|
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|
12043 format %{ "J$cop,u $labl" %} |
|
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|
12044 size(6); |
| 3851 | 12045 ins_encode %{ |
| 12046 Label* L = $labl$$label; | |
| 12047 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 12048 %} | |
|
415
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|
12049 ins_pipe(pipe_jcc); |
|
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|
12050 %} |
|
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changeset
|
12051 |
|
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diff
changeset
|
12052 instruct jmpConUCF2(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{ |
|
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changeset
|
12053 match(If cop cmp); |
|
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diff
changeset
|
12054 effect(USE labl); |
|
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|
12055 |
|
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changeset
|
12056 ins_cost(200); |
|
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diff
changeset
|
12057 format %{ $$template |
|
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|
12058 if ($cop$$cmpcode == Assembler::notEqual) { |
|
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|
12059 $$emit$$"JP,u $labl\n\t" |
|
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|
12060 $$emit$$"J$cop,u $labl" |
|
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|
12061 } else { |
|
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changeset
|
12062 $$emit$$"JP,u done\n\t" |
|
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|
12063 $$emit$$"J$cop,u $labl\n\t" |
|
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|
12064 $$emit$$"done:" |
|
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|
12065 } |
|
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changeset
|
12066 %} |
|
4d9884b01ba6
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changeset
|
12067 ins_encode %{ |
|
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changeset
|
12068 Label* l = $labl$$label; |
|
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|
12069 if ($cop$$cmpcode == Assembler::notEqual) { |
| 3851 | 12070 __ jcc(Assembler::parity, *l, false); |
| 12071 __ jcc(Assembler::notEqual, *l, false); | |
|
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|
12072 } else if ($cop$$cmpcode == Assembler::equal) { |
| 3851 | 12073 Label done; |
| 12074 __ jccb(Assembler::parity, done); | |
| 12075 __ jcc(Assembler::equal, *l, false); | |
| 12076 __ bind(done); | |
|
415
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|
12077 } else { |
|
4d9884b01ba6
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changeset
|
12078 ShouldNotReachHere(); |
|
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changeset
|
12079 } |
|
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changeset
|
12080 %} |
|
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changeset
|
12081 ins_pipe(pipe_jcc); |
| 0 | 12082 %} |
| 12083 | |
| 12084 // ============================================================================ | |
| 12085 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass | |
| 12086 // array for an instance of the superklass. Set a hidden internal cache on a | |
| 12087 // hit (cache is checked with exposed code in gen_subtype_check()). Return | |
| 12088 // NZ for a miss or zero for a hit. The encoding ALSO sets flags. | |
| 12089 instruct partialSubtypeCheck( eDIRegP result, eSIRegP sub, eAXRegP super, eCXRegI rcx, eFlagsReg cr ) %{ | |
| 12090 match(Set result (PartialSubtypeCheck sub super)); | |
| 12091 effect( KILL rcx, KILL cr ); | |
| 12092 | |
| 12093 ins_cost(1100); // slightly larger than the next version | |
|
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
12094 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t" |
|
6831
d8ce2825b193
8000213: NPG: Should have renamed arrayKlass and typeArrayKlass
coleenp
parents:
6795
diff
changeset
|
12095 "MOV ECX,[EDI+ArrayKlass::length]\t# length to scan\n\t" |
|
d8ce2825b193
8000213: NPG: Should have renamed arrayKlass and typeArrayKlass
coleenp
parents:
6795
diff
changeset
|
12096 "ADD EDI,ArrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t" |
| 0 | 12097 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t" |
| 12098 "JNE,s miss\t\t# Missed: EDI not-zero\n\t" | |
| 12099 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache\n\t" | |
| 12100 "XOR $result,$result\t\t Hit: EDI zero\n\t" | |
| 12101 "miss:\t" %} | |
| 12102 | |
| 12103 opcode(0x1); // Force a XOR of EDI | |
| 12104 ins_encode( enc_PartialSubtypeCheck() ); | |
| 12105 ins_pipe( pipe_slow ); | |
| 12106 %} | |
| 12107 | |
| 12108 instruct partialSubtypeCheck_vs_Zero( eFlagsReg cr, eSIRegP sub, eAXRegP super, eCXRegI rcx, eDIRegP result, immP0 zero ) %{ | |
| 12109 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero)); | |
| 12110 effect( KILL rcx, KILL result ); | |
| 12111 | |
| 12112 ins_cost(1000); | |
|
644
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
12113 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t" |
|
6831
d8ce2825b193
8000213: NPG: Should have renamed arrayKlass and typeArrayKlass
coleenp
parents:
6795
diff
changeset
|
12114 "MOV ECX,[EDI+ArrayKlass::length]\t# length to scan\n\t" |
|
d8ce2825b193
8000213: NPG: Should have renamed arrayKlass and typeArrayKlass
coleenp
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6795
diff
changeset
|
12115 "ADD EDI,ArrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t" |
| 0 | 12116 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t" |
| 12117 "JNE,s miss\t\t# Missed: flags NZ\n\t" | |
| 12118 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache, flags Z\n\t" | |
| 12119 "miss:\t" %} | |
| 12120 | |
| 12121 opcode(0x0); // No need to XOR EDI | |
| 12122 ins_encode( enc_PartialSubtypeCheck() ); | |
| 12123 ins_pipe( pipe_slow ); | |
| 12124 %} | |
| 12125 | |
| 12126 // ============================================================================ | |
| 12127 // Branch Instructions -- short offset versions | |
| 12128 // | |
| 12129 // These instructions are used to replace jumps of a long offset (the default | |
| 12130 // match) with jumps of a shorter offset. These instructions are all tagged | |
| 12131 // with the ins_short_branch attribute, which causes the ADLC to suppress the | |
| 12132 // match rules in general matching. Instead, the ADLC generates a conversion | |
| 12133 // method in the MachNode which can be used to do in-place replacement of the | |
| 12134 // long variant with the shorter variant. The compiler will determine if a | |
| 12135 // branch can be taken by the is_short_branch_offset() predicate in the machine | |
| 12136 // specific code section of the file. | |
| 12137 | |
| 12138 // Jump Direct - Label defines a relative address from JMP+1 | |
| 12139 instruct jmpDir_short(label labl) %{ | |
| 12140 match(Goto); | |
| 12141 effect(USE labl); | |
| 12142 | |
| 12143 ins_cost(300); | |
| 12144 format %{ "JMP,s $labl" %} | |
| 12145 size(2); | |
| 3851 | 12146 ins_encode %{ |
| 12147 Label* L = $labl$$label; | |
| 12148 __ jmpb(*L); | |
| 12149 %} | |
| 0 | 12150 ins_pipe( pipe_jmp ); |
| 12151 ins_short_branch(1); | |
| 12152 %} | |
| 12153 | |
| 12154 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 12155 instruct jmpCon_short(cmpOp cop, eFlagsReg cr, label labl) %{ | |
| 12156 match(If cop cr); | |
| 12157 effect(USE labl); | |
| 12158 | |
| 12159 ins_cost(300); | |
| 12160 format %{ "J$cop,s $labl" %} | |
| 12161 size(2); | |
| 3851 | 12162 ins_encode %{ |
| 12163 Label* L = $labl$$label; | |
| 12164 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 12165 %} | |
| 0 | 12166 ins_pipe( pipe_jcc ); |
| 12167 ins_short_branch(1); | |
| 12168 %} | |
| 12169 | |
| 12170 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 12171 instruct jmpLoopEnd_short(cmpOp cop, eFlagsReg cr, label labl) %{ | |
| 12172 match(CountedLoopEnd cop cr); | |
| 12173 effect(USE labl); | |
| 12174 | |
| 12175 ins_cost(300); | |
|
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|
12176 format %{ "J$cop,s $labl\t# Loop end" %} |
| 0 | 12177 size(2); |
| 3851 | 12178 ins_encode %{ |
| 12179 Label* L = $labl$$label; | |
| 12180 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 12181 %} | |
| 0 | 12182 ins_pipe( pipe_jcc ); |
| 12183 ins_short_branch(1); | |
| 12184 %} | |
| 12185 | |
| 12186 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 12187 instruct jmpLoopEndU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{ | |
| 12188 match(CountedLoopEnd cop cmp); | |
| 12189 effect(USE labl); | |
| 12190 | |
| 12191 ins_cost(300); | |
|
415
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diff
changeset
|
12192 format %{ "J$cop,us $labl\t# Loop end" %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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|
12193 size(2); |
| 3851 | 12194 ins_encode %{ |
| 12195 Label* L = $labl$$label; | |
| 12196 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 12197 %} | |
|
415
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changeset
|
12198 ins_pipe( pipe_jcc ); |
|
4d9884b01ba6
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parents:
403
diff
changeset
|
12199 ins_short_branch(1); |
|
4d9884b01ba6
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diff
changeset
|
12200 %} |
|
4d9884b01ba6
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403
diff
changeset
|
12201 |
|
4d9884b01ba6
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diff
changeset
|
12202 instruct jmpLoopEndUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{ |
|
4d9884b01ba6
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diff
changeset
|
12203 match(CountedLoopEnd cop cmp); |
|
4d9884b01ba6
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403
diff
changeset
|
12204 effect(USE labl); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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diff
changeset
|
12205 |
|
4d9884b01ba6
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diff
changeset
|
12206 ins_cost(300); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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parents:
403
diff
changeset
|
12207 format %{ "J$cop,us $labl\t# Loop end" %} |
| 0 | 12208 size(2); |
| 3851 | 12209 ins_encode %{ |
| 12210 Label* L = $labl$$label; | |
| 12211 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 12212 %} | |
| 0 | 12213 ins_pipe( pipe_jcc ); |
| 12214 ins_short_branch(1); | |
| 12215 %} | |
| 12216 | |
| 12217 // Jump Direct Conditional - using unsigned comparison | |
| 12218 instruct jmpConU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{ | |
| 12219 match(If cop cmp); | |
| 12220 effect(USE labl); | |
| 12221 | |
| 12222 ins_cost(300); | |
| 12223 format %{ "J$cop,us $labl" %} | |
| 12224 size(2); | |
| 3851 | 12225 ins_encode %{ |
| 12226 Label* L = $labl$$label; | |
| 12227 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 12228 %} | |
| 0 | 12229 ins_pipe( pipe_jcc ); |
| 12230 ins_short_branch(1); | |
| 12231 %} | |
| 12232 | |
|
415
4d9884b01ba6
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changeset
|
12233 instruct jmpConUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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parents:
403
diff
changeset
|
12234 match(If cop cmp); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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parents:
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diff
changeset
|
12235 effect(USE labl); |
|
4d9884b01ba6
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|
12236 |
|
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|
12237 ins_cost(300); |
|
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|
12238 format %{ "J$cop,us $labl" %} |
|
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|
12239 size(2); |
| 3851 | 12240 ins_encode %{ |
| 12241 Label* L = $labl$$label; | |
| 12242 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 12243 %} | |
|
415
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|
12244 ins_pipe( pipe_jcc ); |
|
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|
12245 ins_short_branch(1); |
|
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changeset
|
12246 %} |
|
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diff
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|
12247 |
|
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diff
changeset
|
12248 instruct jmpConUCF2_short(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{ |
|
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|
12249 match(If cop cmp); |
|
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|
12250 effect(USE labl); |
|
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|
12251 |
|
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|
12252 ins_cost(300); |
|
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|
12253 format %{ $$template |
|
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|
12254 if ($cop$$cmpcode == Assembler::notEqual) { |
|
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|
12255 $$emit$$"JP,u,s $labl\n\t" |
|
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|
12256 $$emit$$"J$cop,u,s $labl" |
|
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|
12257 } else { |
|
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changeset
|
12258 $$emit$$"JP,u,s done\n\t" |
|
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|
12259 $$emit$$"J$cop,u,s $labl\n\t" |
|
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|
12260 $$emit$$"done:" |
|
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changeset
|
12261 } |
|
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never
parents:
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diff
changeset
|
12262 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12263 size(4); |
|
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never
parents:
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diff
changeset
|
12264 ins_encode %{ |
|
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never
parents:
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diff
changeset
|
12265 Label* l = $labl$$label; |
|
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diff
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|
12266 if ($cop$$cmpcode == Assembler::notEqual) { |
| 3851 | 12267 __ jccb(Assembler::parity, *l); |
| 12268 __ jccb(Assembler::notEqual, *l); | |
|
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|
12269 } else if ($cop$$cmpcode == Assembler::equal) { |
| 3851 | 12270 Label done; |
| 12271 __ jccb(Assembler::parity, done); | |
| 12272 __ jccb(Assembler::equal, *l); | |
| 12273 __ bind(done); | |
|
415
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|
12274 } else { |
| 3851 | 12275 ShouldNotReachHere(); |
| 12276 } | |
|
415
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changeset
|
12277 %} |
|
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diff
changeset
|
12278 ins_pipe(pipe_jcc); |
|
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|
12279 ins_short_branch(1); |
|
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never
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diff
changeset
|
12280 %} |
|
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|
12281 |
| 0 | 12282 // ============================================================================ |
| 12283 // Long Compare | |
| 12284 // | |
| 12285 // Currently we hold longs in 2 registers. Comparing such values efficiently | |
| 12286 // is tricky. The flavor of compare used depends on whether we are testing | |
| 12287 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit. | |
| 12288 // The GE test is the negated LT test. The LE test can be had by commuting | |
| 12289 // the operands (yielding a GE test) and then negating; negate again for the | |
| 12290 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the | |
| 12291 // NE test is negated from that. | |
| 12292 | |
| 12293 // Due to a shortcoming in the ADLC, it mixes up expressions like: | |
| 12294 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the | |
| 12295 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections | |
| 12296 // are collapsed internally in the ADLC's dfa-gen code. The match for | |
| 12297 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the | |
| 12298 // foo match ends up with the wrong leaf. One fix is to not match both | |
| 12299 // reg-reg and reg-zero forms of long-compare. This is unfortunate because | |
| 12300 // both forms beat the trinary form of long-compare and both are very useful | |
| 12301 // on Intel which has so few registers. | |
| 12302 | |
| 12303 // Manifest a CmpL result in an integer register. Very painful. | |
| 12304 // This is the test to avoid. | |
| 12305 instruct cmpL3_reg_reg(eSIRegI dst, eRegL src1, eRegL src2, eFlagsReg flags ) %{ | |
| 12306 match(Set dst (CmpL3 src1 src2)); | |
| 12307 effect( KILL flags ); | |
| 12308 ins_cost(1000); | |
| 12309 format %{ "XOR $dst,$dst\n\t" | |
| 12310 "CMP $src1.hi,$src2.hi\n\t" | |
| 12311 "JLT,s m_one\n\t" | |
| 12312 "JGT,s p_one\n\t" | |
| 12313 "CMP $src1.lo,$src2.lo\n\t" | |
| 12314 "JB,s m_one\n\t" | |
| 12315 "JEQ,s done\n" | |
| 12316 "p_one:\tINC $dst\n\t" | |
| 12317 "JMP,s done\n" | |
| 12318 "m_one:\tDEC $dst\n" | |
| 12319 "done:" %} | |
| 12320 ins_encode %{ | |
| 12321 Label p_one, m_one, done; | |
| 304 | 12322 __ xorptr($dst$$Register, $dst$$Register); |
| 0 | 12323 __ cmpl(HIGH_FROM_LOW($src1$$Register), HIGH_FROM_LOW($src2$$Register)); |
| 12324 __ jccb(Assembler::less, m_one); | |
| 12325 __ jccb(Assembler::greater, p_one); | |
| 12326 __ cmpl($src1$$Register, $src2$$Register); | |
| 12327 __ jccb(Assembler::below, m_one); | |
| 12328 __ jccb(Assembler::equal, done); | |
| 12329 __ bind(p_one); | |
| 304 | 12330 __ incrementl($dst$$Register); |
| 0 | 12331 __ jmpb(done); |
| 12332 __ bind(m_one); | |
| 304 | 12333 __ decrementl($dst$$Register); |
| 0 | 12334 __ bind(done); |
| 12335 %} | |
| 12336 ins_pipe( pipe_slow ); | |
| 12337 %} | |
| 12338 | |
| 12339 //====== | |
| 12340 // Manifest a CmpL result in the normal flags. Only good for LT or GE | |
| 12341 // compares. Can be used for LE or GT compares by reversing arguments. | |
| 12342 // NOT GOOD FOR EQ/NE tests. | |
| 12343 instruct cmpL_zero_flags_LTGE( flagsReg_long_LTGE flags, eRegL src, immL0 zero ) %{ | |
| 12344 match( Set flags (CmpL src zero )); | |
| 12345 ins_cost(100); | |
| 12346 format %{ "TEST $src.hi,$src.hi" %} | |
| 12347 opcode(0x85); | |
| 12348 ins_encode( OpcP, RegReg_Hi2( src, src ) ); | |
| 12349 ins_pipe( ialu_cr_reg_reg ); | |
| 12350 %} | |
| 12351 | |
| 12352 // Manifest a CmpL result in the normal flags. Only good for LT or GE | |
| 12353 // compares. Can be used for LE or GT compares by reversing arguments. | |
| 12354 // NOT GOOD FOR EQ/NE tests. | |
|
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|
12355 instruct cmpL_reg_flags_LTGE( flagsReg_long_LTGE flags, eRegL src1, eRegL src2, rRegI tmp ) %{ |
| 0 | 12356 match( Set flags (CmpL src1 src2 )); |
| 12357 effect( TEMP tmp ); | |
| 12358 ins_cost(300); | |
| 12359 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t" | |
| 12360 "MOV $tmp,$src1.hi\n\t" | |
| 12361 "SBB $tmp,$src2.hi\t! Compute flags for long compare" %} | |
| 12362 ins_encode( long_cmp_flags2( src1, src2, tmp ) ); | |
| 12363 ins_pipe( ialu_cr_reg_reg ); | |
| 12364 %} | |
| 12365 | |
| 12366 // Long compares reg < zero/req OR reg >= zero/req. | |
| 12367 // Just a wrapper for a normal branch, plus the predicate test. | |
| 12368 instruct cmpL_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, label labl) %{ | |
| 12369 match(If cmp flags); | |
| 12370 effect(USE labl); | |
| 12371 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); | |
| 12372 expand %{ | |
| 12373 jmpCon(cmp,flags,labl); // JLT or JGE... | |
| 12374 %} | |
| 12375 %} | |
| 12376 | |
| 12377 // Compare 2 longs and CMOVE longs. | |
| 12378 instruct cmovLL_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, eRegL src) %{ | |
| 12379 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src))); | |
| 12380 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); | |
| 12381 ins_cost(400); | |
| 12382 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" | |
| 12383 "CMOV$cmp $dst.hi,$src.hi" %} | |
| 12384 opcode(0x0F,0x40); | |
| 12385 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) ); | |
| 12386 ins_pipe( pipe_cmov_reg_long ); | |
| 12387 %} | |
| 12388 | |
| 12389 instruct cmovLL_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, load_long_memory src) %{ | |
| 12390 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src)))); | |
| 12391 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); | |
| 12392 ins_cost(500); | |
| 12393 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" | |
| 12394 "CMOV$cmp $dst.hi,$src.hi" %} | |
| 12395 opcode(0x0F,0x40); | |
| 12396 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) ); | |
| 12397 ins_pipe( pipe_cmov_reg_long ); | |
| 12398 %} | |
| 12399 | |
| 12400 // Compare 2 longs and CMOVE ints. | |
|
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|
12401 instruct cmovII_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, rRegI dst, rRegI src) %{ |
| 0 | 12402 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); |
| 12403 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src))); | |
| 12404 ins_cost(200); | |
| 12405 format %{ "CMOV$cmp $dst,$src" %} | |
| 12406 opcode(0x0F,0x40); | |
| 12407 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); | |
| 12408 ins_pipe( pipe_cmov_reg ); | |
| 12409 %} | |
| 12410 | |
|
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|
12411 instruct cmovII_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, rRegI dst, memory src) %{ |
| 0 | 12412 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); |
| 12413 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src)))); | |
| 12414 ins_cost(250); | |
| 12415 format %{ "CMOV$cmp $dst,$src" %} | |
| 12416 opcode(0x0F,0x40); | |
| 12417 ins_encode( enc_cmov(cmp), RegMem( dst, src ) ); | |
| 12418 ins_pipe( pipe_cmov_mem ); | |
| 12419 %} | |
| 12420 | |
| 12421 // Compare 2 longs and CMOVE ints. | |
| 12422 instruct cmovPP_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegP dst, eRegP src) %{ | |
| 12423 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); | |
| 12424 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src))); | |
| 12425 ins_cost(200); | |
| 12426 format %{ "CMOV$cmp $dst,$src" %} | |
| 12427 opcode(0x0F,0x40); | |
| 12428 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); | |
| 12429 ins_pipe( pipe_cmov_reg ); | |
| 12430 %} | |
| 12431 | |
| 12432 // Compare 2 longs and CMOVE doubles | |
|
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|
12433 instruct cmovDDPR_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regDPR dst, regDPR src) %{ |
| 0 | 12434 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); |
| 12435 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); | |
| 12436 ins_cost(200); | |
| 12437 expand %{ | |
|
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|
12438 fcmovDPR_regS(cmp,flags,dst,src); |
| 0 | 12439 %} |
| 12440 %} | |
| 12441 | |
| 12442 // Compare 2 longs and CMOVE doubles | |
|
4761
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|
12443 instruct cmovDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regD dst, regD src) %{ |
| 0 | 12444 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); |
| 12445 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); | |
| 12446 ins_cost(200); | |
| 12447 expand %{ | |
|
4761
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|
12448 fcmovD_regS(cmp,flags,dst,src); |
|
65149e74c706
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|
12449 %} |
|
65149e74c706
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|
12450 %} |
|
65149e74c706
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|
12451 |
|
65149e74c706
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|
12452 instruct cmovFFPR_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regFPR dst, regFPR src) %{ |
|
65149e74c706
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|
12453 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); |
|
65149e74c706
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|
12454 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); |
|
65149e74c706
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|
12455 ins_cost(200); |
|
65149e74c706
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changeset
|
12456 expand %{ |
|
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|
12457 fcmovFPR_regS(cmp,flags,dst,src); |
| 0 | 12458 %} |
| 12459 %} | |
| 12460 | |
| 12461 instruct cmovFF_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regF dst, regF src) %{ | |
|
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|
12462 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); |
| 0 | 12463 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); |
| 12464 ins_cost(200); | |
| 12465 expand %{ | |
| 12466 fcmovF_regS(cmp,flags,dst,src); | |
| 12467 %} | |
| 12468 %} | |
| 12469 | |
| 12470 //====== | |
| 12471 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares. | |
|
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12472 instruct cmpL_zero_flags_EQNE( flagsReg_long_EQNE flags, eRegL src, immL0 zero, rRegI tmp ) %{ |
| 0 | 12473 match( Set flags (CmpL src zero )); |
| 12474 effect(TEMP tmp); | |
| 12475 ins_cost(200); | |
| 12476 format %{ "MOV $tmp,$src.lo\n\t" | |
| 12477 "OR $tmp,$src.hi\t! Long is EQ/NE 0?" %} | |
| 12478 ins_encode( long_cmp_flags0( src, tmp ) ); | |
| 12479 ins_pipe( ialu_reg_reg_long ); | |
| 12480 %} | |
| 12481 | |
| 12482 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares. | |
| 12483 instruct cmpL_reg_flags_EQNE( flagsReg_long_EQNE flags, eRegL src1, eRegL src2 ) %{ | |
| 12484 match( Set flags (CmpL src1 src2 )); | |
| 12485 ins_cost(200+300); | |
| 12486 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t" | |
| 12487 "JNE,s skip\n\t" | |
| 12488 "CMP $src1.hi,$src2.hi\n\t" | |
| 12489 "skip:\t" %} | |
| 12490 ins_encode( long_cmp_flags1( src1, src2 ) ); | |
| 12491 ins_pipe( ialu_cr_reg_reg ); | |
| 12492 %} | |
| 12493 | |
| 12494 // Long compare reg == zero/reg OR reg != zero/reg | |
| 12495 // Just a wrapper for a normal branch, plus the predicate test. | |
| 12496 instruct cmpL_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, label labl) %{ | |
| 12497 match(If cmp flags); | |
| 12498 effect(USE labl); | |
| 12499 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); | |
| 12500 expand %{ | |
| 12501 jmpCon(cmp,flags,labl); // JEQ or JNE... | |
| 12502 %} | |
| 12503 %} | |
| 12504 | |
| 12505 // Compare 2 longs and CMOVE longs. | |
| 12506 instruct cmovLL_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, eRegL src) %{ | |
| 12507 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src))); | |
| 12508 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); | |
| 12509 ins_cost(400); | |
| 12510 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" | |
| 12511 "CMOV$cmp $dst.hi,$src.hi" %} | |
| 12512 opcode(0x0F,0x40); | |
| 12513 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) ); | |
| 12514 ins_pipe( pipe_cmov_reg_long ); | |
| 12515 %} | |
| 12516 | |
| 12517 instruct cmovLL_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, load_long_memory src) %{ | |
| 12518 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src)))); | |
| 12519 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); | |
| 12520 ins_cost(500); | |
| 12521 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" | |
| 12522 "CMOV$cmp $dst.hi,$src.hi" %} | |
| 12523 opcode(0x0F,0x40); | |
| 12524 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) ); | |
| 12525 ins_pipe( pipe_cmov_reg_long ); | |
| 12526 %} | |
| 12527 | |
| 12528 // Compare 2 longs and CMOVE ints. | |
|
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12529 instruct cmovII_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, rRegI dst, rRegI src) %{ |
| 0 | 12530 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); |
| 12531 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src))); | |
| 12532 ins_cost(200); | |
| 12533 format %{ "CMOV$cmp $dst,$src" %} | |
| 12534 opcode(0x0F,0x40); | |
| 12535 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); | |
| 12536 ins_pipe( pipe_cmov_reg ); | |
| 12537 %} | |
| 12538 | |
|
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12539 instruct cmovII_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, rRegI dst, memory src) %{ |
| 0 | 12540 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); |
| 12541 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src)))); | |
| 12542 ins_cost(250); | |
| 12543 format %{ "CMOV$cmp $dst,$src" %} | |
| 12544 opcode(0x0F,0x40); | |
| 12545 ins_encode( enc_cmov(cmp), RegMem( dst, src ) ); | |
| 12546 ins_pipe( pipe_cmov_mem ); | |
| 12547 %} | |
| 12548 | |
| 12549 // Compare 2 longs and CMOVE ints. | |
| 12550 instruct cmovPP_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegP dst, eRegP src) %{ | |
| 12551 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); | |
| 12552 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src))); | |
| 12553 ins_cost(200); | |
| 12554 format %{ "CMOV$cmp $dst,$src" %} | |
| 12555 opcode(0x0F,0x40); | |
| 12556 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); | |
| 12557 ins_pipe( pipe_cmov_reg ); | |
| 12558 %} | |
| 12559 | |
| 12560 // Compare 2 longs and CMOVE doubles | |
|
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12561 instruct cmovDDPR_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regDPR dst, regDPR src) %{ |
| 0 | 12562 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); |
| 12563 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); | |
| 12564 ins_cost(200); | |
| 12565 expand %{ | |
|
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12566 fcmovDPR_regS(cmp,flags,dst,src); |
| 0 | 12567 %} |
| 12568 %} | |
| 12569 | |
| 12570 // Compare 2 longs and CMOVE doubles | |
|
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12571 instruct cmovDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regD dst, regD src) %{ |
| 0 | 12572 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); |
| 12573 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); | |
| 12574 ins_cost(200); | |
| 12575 expand %{ | |
|
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12576 fcmovD_regS(cmp,flags,dst,src); |
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12577 %} |
|
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12578 %} |
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12579 |
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12580 instruct cmovFFPR_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regFPR dst, regFPR src) %{ |
|
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12581 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); |
|
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12582 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); |
|
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12583 ins_cost(200); |
|
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12584 expand %{ |
|
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12585 fcmovFPR_regS(cmp,flags,dst,src); |
| 0 | 12586 %} |
| 12587 %} | |
| 12588 | |
| 12589 instruct cmovFF_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regF dst, regF src) %{ | |
|
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12590 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); |
| 0 | 12591 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); |
| 12592 ins_cost(200); | |
| 12593 expand %{ | |
| 12594 fcmovF_regS(cmp,flags,dst,src); | |
| 12595 %} | |
| 12596 %} | |
| 12597 | |
| 12598 //====== | |
| 12599 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares. | |
| 12600 // Same as cmpL_reg_flags_LEGT except must negate src | |
|
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12601 instruct cmpL_zero_flags_LEGT( flagsReg_long_LEGT flags, eRegL src, immL0 zero, rRegI tmp ) %{ |
| 0 | 12602 match( Set flags (CmpL src zero )); |
| 12603 effect( TEMP tmp ); | |
| 12604 ins_cost(300); | |
| 12605 format %{ "XOR $tmp,$tmp\t# Long compare for -$src < 0, use commuted test\n\t" | |
| 12606 "CMP $tmp,$src.lo\n\t" | |
| 12607 "SBB $tmp,$src.hi\n\t" %} | |
| 12608 ins_encode( long_cmp_flags3(src, tmp) ); | |
| 12609 ins_pipe( ialu_reg_reg_long ); | |
| 12610 %} | |
| 12611 | |
| 12612 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares. | |
| 12613 // Same as cmpL_reg_flags_LTGE except operands swapped. Swapping operands | |
| 12614 // requires a commuted test to get the same result. | |
|
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12615 instruct cmpL_reg_flags_LEGT( flagsReg_long_LEGT flags, eRegL src1, eRegL src2, rRegI tmp ) %{ |
| 0 | 12616 match( Set flags (CmpL src1 src2 )); |
| 12617 effect( TEMP tmp ); | |
| 12618 ins_cost(300); | |
| 12619 format %{ "CMP $src2.lo,$src1.lo\t! Long compare, swapped operands, use with commuted test\n\t" | |
| 12620 "MOV $tmp,$src2.hi\n\t" | |
| 12621 "SBB $tmp,$src1.hi\t! Compute flags for long compare" %} | |
| 12622 ins_encode( long_cmp_flags2( src2, src1, tmp ) ); | |
| 12623 ins_pipe( ialu_cr_reg_reg ); | |
| 12624 %} | |
| 12625 | |
| 12626 // Long compares reg < zero/req OR reg >= zero/req. | |
| 12627 // Just a wrapper for a normal branch, plus the predicate test | |
| 12628 instruct cmpL_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, label labl) %{ | |
| 12629 match(If cmp flags); | |
| 12630 effect(USE labl); | |
| 12631 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le ); | |
| 12632 ins_cost(300); | |
| 12633 expand %{ | |
| 12634 jmpCon(cmp,flags,labl); // JGT or JLE... | |
| 12635 %} | |
| 12636 %} | |
| 12637 | |
| 12638 // Compare 2 longs and CMOVE longs. | |
| 12639 instruct cmovLL_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, eRegL src) %{ | |
| 12640 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src))); | |
| 12641 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); | |
| 12642 ins_cost(400); | |
| 12643 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" | |
| 12644 "CMOV$cmp $dst.hi,$src.hi" %} | |
| 12645 opcode(0x0F,0x40); | |
| 12646 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) ); | |
| 12647 ins_pipe( pipe_cmov_reg_long ); | |
| 12648 %} | |
| 12649 | |
| 12650 instruct cmovLL_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, load_long_memory src) %{ | |
| 12651 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src)))); | |
| 12652 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); | |
| 12653 ins_cost(500); | |
| 12654 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" | |
| 12655 "CMOV$cmp $dst.hi,$src.hi+4" %} | |
| 12656 opcode(0x0F,0x40); | |
| 12657 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) ); | |
| 12658 ins_pipe( pipe_cmov_reg_long ); | |
| 12659 %} | |
| 12660 | |
| 12661 // Compare 2 longs and CMOVE ints. | |
|
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12662 instruct cmovII_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, rRegI dst, rRegI src) %{ |
| 0 | 12663 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); |
| 12664 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src))); | |
| 12665 ins_cost(200); | |
| 12666 format %{ "CMOV$cmp $dst,$src" %} | |
| 12667 opcode(0x0F,0x40); | |
| 12668 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); | |
| 12669 ins_pipe( pipe_cmov_reg ); | |
| 12670 %} | |
| 12671 | |
|
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12672 instruct cmovII_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, rRegI dst, memory src) %{ |
| 0 | 12673 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); |
| 12674 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src)))); | |
| 12675 ins_cost(250); | |
| 12676 format %{ "CMOV$cmp $dst,$src" %} | |
| 12677 opcode(0x0F,0x40); | |
| 12678 ins_encode( enc_cmov(cmp), RegMem( dst, src ) ); | |
| 12679 ins_pipe( pipe_cmov_mem ); | |
| 12680 %} | |
| 12681 | |
| 12682 // Compare 2 longs and CMOVE ptrs. | |
| 12683 instruct cmovPP_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegP dst, eRegP src) %{ | |
| 12684 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); | |
| 12685 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src))); | |
| 12686 ins_cost(200); | |
| 12687 format %{ "CMOV$cmp $dst,$src" %} | |
| 12688 opcode(0x0F,0x40); | |
| 12689 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); | |
| 12690 ins_pipe( pipe_cmov_reg ); | |
| 12691 %} | |
| 12692 | |
| 12693 // Compare 2 longs and CMOVE doubles | |
|
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12694 instruct cmovDDPR_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regDPR dst, regDPR src) %{ |
| 0 | 12695 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ); |
| 12696 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); | |
| 12697 ins_cost(200); | |
| 12698 expand %{ | |
|
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12699 fcmovDPR_regS(cmp,flags,dst,src); |
| 0 | 12700 %} |
| 12701 %} | |
| 12702 | |
| 12703 // Compare 2 longs and CMOVE doubles | |
|
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12704 instruct cmovDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regD dst, regD src) %{ |
| 0 | 12705 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ); |
| 12706 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); | |
| 12707 ins_cost(200); | |
| 12708 expand %{ | |
|
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12709 fcmovD_regS(cmp,flags,dst,src); |
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12710 %} |
|
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|
12711 %} |
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12712 |
|
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12713 instruct cmovFFPR_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regFPR dst, regFPR src) %{ |
|
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12714 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ); |
|
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12715 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); |
|
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12716 ins_cost(200); |
|
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12717 expand %{ |
|
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12718 fcmovFPR_regS(cmp,flags,dst,src); |
|
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12719 %} |
|
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|
12720 %} |
|
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12721 |
| 0 | 12722 |
| 12723 instruct cmovFF_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regF dst, regF src) %{ | |
|
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12724 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ); |
| 0 | 12725 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); |
| 12726 ins_cost(200); | |
| 12727 expand %{ | |
| 12728 fcmovF_regS(cmp,flags,dst,src); | |
| 12729 %} | |
| 12730 %} | |
| 12731 | |
| 12732 | |
| 12733 // ============================================================================ | |
| 12734 // Procedure Call/Return Instructions | |
| 12735 // Call Java Static Instruction | |
| 12736 // Note: If this code changes, the corresponding ret_addr_offset() and | |
| 12737 // compute_padding() functions will have to be adjusted. | |
| 12738 instruct CallStaticJavaDirect(method meth) %{ | |
| 12739 match(CallStaticJava); | |
| 12740 effect(USE meth); | |
| 12741 | |
| 12742 ins_cost(300); | |
| 12743 format %{ "CALL,static " %} | |
| 12744 opcode(0xE8); /* E8 cd */ | |
|
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|
12745 ins_encode( pre_call_resets, |
| 0 | 12746 Java_Static_Call( meth ), |
| 12747 call_epilog, | |
| 12748 post_call_FPU ); | |
| 12749 ins_pipe( pipe_slow ); | |
| 12750 ins_alignment(4); | |
| 12751 %} | |
| 12752 | |
| 12753 // Call Java Dynamic Instruction | |
| 12754 // Note: If this code changes, the corresponding ret_addr_offset() and | |
| 12755 // compute_padding() functions will have to be adjusted. | |
| 12756 instruct CallDynamicJavaDirect(method meth) %{ | |
| 12757 match(CallDynamicJava); | |
| 12758 effect(USE meth); | |
| 12759 | |
| 12760 ins_cost(300); | |
| 12761 format %{ "MOV EAX,(oop)-1\n\t" | |
| 12762 "CALL,dynamic" %} | |
| 12763 opcode(0xE8); /* E8 cd */ | |
|
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|
12764 ins_encode( pre_call_resets, |
| 0 | 12765 Java_Dynamic_Call( meth ), |
| 12766 call_epilog, | |
| 12767 post_call_FPU ); | |
| 12768 ins_pipe( pipe_slow ); | |
| 12769 ins_alignment(4); | |
| 12770 %} | |
| 12771 | |
| 12772 // Call Runtime Instruction | |
| 12773 instruct CallRuntimeDirect(method meth) %{ | |
| 12774 match(CallRuntime ); | |
| 12775 effect(USE meth); | |
| 12776 | |
| 12777 ins_cost(300); | |
| 12778 format %{ "CALL,runtime " %} | |
| 12779 opcode(0xE8); /* E8 cd */ | |
| 12780 // Use FFREEs to clear entries in float stack | |
|
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12781 ins_encode( pre_call_resets, |
| 0 | 12782 FFree_Float_Stack_All, |
| 12783 Java_To_Runtime( meth ), | |
| 12784 post_call_FPU ); | |
| 12785 ins_pipe( pipe_slow ); | |
| 12786 %} | |
| 12787 | |
| 12788 // Call runtime without safepoint | |
| 12789 instruct CallLeafDirect(method meth) %{ | |
| 12790 match(CallLeaf); | |
| 12791 effect(USE meth); | |
| 12792 | |
| 12793 ins_cost(300); | |
| 12794 format %{ "CALL_LEAF,runtime " %} | |
| 12795 opcode(0xE8); /* E8 cd */ | |
|
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12796 ins_encode( pre_call_resets, |
| 0 | 12797 FFree_Float_Stack_All, |
| 12798 Java_To_Runtime( meth ), | |
| 12799 Verify_FPU_For_Leaf, post_call_FPU ); | |
| 12800 ins_pipe( pipe_slow ); | |
| 12801 %} | |
| 12802 | |
| 12803 instruct CallLeafNoFPDirect(method meth) %{ | |
| 12804 match(CallLeafNoFP); | |
| 12805 effect(USE meth); | |
| 12806 | |
| 12807 ins_cost(300); | |
| 12808 format %{ "CALL_LEAF_NOFP,runtime " %} | |
| 12809 opcode(0xE8); /* E8 cd */ | |
| 12810 ins_encode(Java_To_Runtime(meth)); | |
| 12811 ins_pipe( pipe_slow ); | |
| 12812 %} | |
| 12813 | |
| 12814 | |
| 12815 // Return Instruction | |
| 12816 // Remove the return address & jump to it. | |
| 12817 instruct Ret() %{ | |
| 12818 match(Return); | |
| 12819 format %{ "RET" %} | |
| 12820 opcode(0xC3); | |
| 12821 ins_encode(OpcP); | |
| 12822 ins_pipe( pipe_jmp ); | |
| 12823 %} | |
| 12824 | |
| 12825 // Tail Call; Jump from runtime stub to Java code. | |
| 12826 // Also known as an 'interprocedural jump'. | |
| 12827 // Target of jump will eventually return to caller. | |
| 12828 // TailJump below removes the return address. | |
| 12829 instruct TailCalljmpInd(eRegP_no_EBP jump_target, eBXRegP method_oop) %{ | |
| 12830 match(TailCall jump_target method_oop ); | |
| 12831 ins_cost(300); | |
| 12832 format %{ "JMP $jump_target \t# EBX holds method oop" %} | |
| 12833 opcode(0xFF, 0x4); /* Opcode FF /4 */ | |
| 12834 ins_encode( OpcP, RegOpc(jump_target) ); | |
| 12835 ins_pipe( pipe_jmp ); | |
| 12836 %} | |
| 12837 | |
| 12838 | |
| 12839 // Tail Jump; remove the return address; jump to target. | |
| 12840 // TailCall above leaves the return address around. | |
| 12841 instruct tailjmpInd(eRegP_no_EBP jump_target, eAXRegP ex_oop) %{ | |
| 12842 match( TailJump jump_target ex_oop ); | |
| 12843 ins_cost(300); | |
| 12844 format %{ "POP EDX\t# pop return address into dummy\n\t" | |
| 12845 "JMP $jump_target " %} | |
| 12846 opcode(0xFF, 0x4); /* Opcode FF /4 */ | |
| 12847 ins_encode( enc_pop_rdx, | |
| 12848 OpcP, RegOpc(jump_target) ); | |
| 12849 ins_pipe( pipe_jmp ); | |
| 12850 %} | |
| 12851 | |
| 12852 // Create exception oop: created by stack-crawling runtime code. | |
| 12853 // Created exception is now available to this handler, and is setup | |
| 12854 // just prior to jumping to this handler. No code emitted. | |
| 12855 instruct CreateException( eAXRegP ex_oop ) | |
| 12856 %{ | |
| 12857 match(Set ex_oop (CreateEx)); | |
| 12858 | |
| 12859 size(0); | |
| 12860 // use the following format syntax | |
| 12861 format %{ "# exception oop is in EAX; no code emitted" %} | |
| 12862 ins_encode(); | |
| 12863 ins_pipe( empty ); | |
| 12864 %} | |
| 12865 | |
| 12866 | |
| 12867 // Rethrow exception: | |
| 12868 // The exception oop will come in the first argument position. | |
| 12869 // Then JUMP (not call) to the rethrow stub code. | |
| 12870 instruct RethrowException() | |
| 12871 %{ | |
| 12872 match(Rethrow); | |
| 12873 | |
| 12874 // use the following format syntax | |
| 12875 format %{ "JMP rethrow_stub" %} | |
| 12876 ins_encode(enc_rethrow); | |
| 12877 ins_pipe( pipe_jmp ); | |
| 12878 %} | |
| 12879 | |
| 12880 // inlined locking and unlocking | |
| 12881 | |
| 17780 | 12882 instruct cmpFastLockRTM(eFlagsReg cr, eRegP object, eBXRegP box, eAXRegI tmp, eDXRegI scr, rRegI cx1, rRegI cx2) %{ |
| 12883 predicate(Compile::current()->use_rtm()); | |
| 12884 match(Set cr (FastLock object box)); | |
| 12885 effect(TEMP tmp, TEMP scr, TEMP cx1, TEMP cx2, USE_KILL box); | |
| 12886 ins_cost(300); | |
| 12887 format %{ "FASTLOCK $object,$box\t! kills $box,$tmp,$scr,$cx1,$cx2" %} | |
| 12888 ins_encode %{ | |
| 12889 __ fast_lock($object$$Register, $box$$Register, $tmp$$Register, | |
| 12890 $scr$$Register, $cx1$$Register, $cx2$$Register, | |
| 12891 _counters, _rtm_counters, _stack_rtm_counters, | |
| 12892 ((Method*)(ra_->C->method()->constant_encoding()))->method_data(), | |
| 12893 true, ra_->C->profile_rtm()); | |
| 12894 %} | |
| 12895 ins_pipe(pipe_slow); | |
| 12896 %} | |
| 12897 | |
|
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12898 instruct cmpFastLock(eFlagsReg cr, eRegP object, eBXRegP box, eAXRegI tmp, eRegP scr) %{ |
| 17780 | 12899 predicate(!Compile::current()->use_rtm()); |
|
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12900 match(Set cr (FastLock object box)); |
|
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12901 effect(TEMP tmp, TEMP scr, USE_KILL box); |
| 0 | 12902 ins_cost(300); |
| 4777 | 12903 format %{ "FASTLOCK $object,$box\t! kills $box,$tmp,$scr" %} |
|
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12904 ins_encode %{ |
| 17780 | 12905 __ fast_lock($object$$Register, $box$$Register, $tmp$$Register, |
| 12906 $scr$$Register, noreg, noreg, _counters, NULL, NULL, NULL, false, false); | |
|
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12907 %} |
|
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12908 ins_pipe(pipe_slow); |
|
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12909 %} |
|
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12910 |
|
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12911 instruct cmpFastUnlock(eFlagsReg cr, eRegP object, eAXRegP box, eRegP tmp ) %{ |
|
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12912 match(Set cr (FastUnlock object box)); |
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12913 effect(TEMP tmp, USE_KILL box); |
| 0 | 12914 ins_cost(300); |
| 4777 | 12915 format %{ "FASTUNLOCK $object,$box\t! kills $box,$tmp" %} |
|
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12916 ins_encode %{ |
| 17780 | 12917 __ fast_unlock($object$$Register, $box$$Register, $tmp$$Register, ra_->C->use_rtm()); |
|
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12918 %} |
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12919 ins_pipe(pipe_slow); |
| 0 | 12920 %} |
| 12921 | |
| 12922 | |
| 12923 | |
| 12924 // ============================================================================ | |
| 12925 // Safepoint Instruction | |
| 12926 instruct safePoint_poll(eFlagsReg cr) %{ | |
| 12927 match(SafePoint); | |
| 12928 effect(KILL cr); | |
| 12929 | |
| 12930 // TODO-FIXME: we currently poll at offset 0 of the safepoint polling page. | |
| 12931 // On SPARC that might be acceptable as we can generate the address with | |
| 12932 // just a sethi, saving an or. By polling at offset 0 we can end up | |
| 12933 // putting additional pressure on the index-0 in the D$. Because of | |
| 12934 // alignment (just like the situation at hand) the lower indices tend | |
| 12935 // to see more traffic. It'd be better to change the polling address | |
| 12936 // to offset 0 of the last $line in the polling page. | |
| 12937 | |
| 12938 format %{ "TSTL #polladdr,EAX\t! Safepoint: poll for GC" %} | |
| 12939 ins_cost(125); | |
| 12940 size(6) ; | |
| 12941 ins_encode( Safepoint_Poll() ); | |
| 12942 ins_pipe( ialu_reg_mem ); | |
| 12943 %} | |
| 12944 | |
| 4950 | 12945 |
| 12946 // ============================================================================ | |
| 12947 // This name is KNOWN by the ADLC and cannot be changed. | |
| 12948 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type | |
| 12949 // for this guy. | |
| 12950 instruct tlsLoadP(eRegP dst, eFlagsReg cr) %{ | |
| 12951 match(Set dst (ThreadLocal)); | |
| 12952 effect(DEF dst, KILL cr); | |
| 12953 | |
| 12954 format %{ "MOV $dst, Thread::current()" %} | |
| 12955 ins_encode %{ | |
| 12956 Register dstReg = as_Register($dst$$reg); | |
| 12957 __ get_thread(dstReg); | |
| 12958 %} | |
| 12959 ins_pipe( ialu_reg_fat ); | |
| 12960 %} | |
| 12961 | |
| 12962 | |
| 12963 | |
| 0 | 12964 //----------PEEPHOLE RULES----------------------------------------------------- |
| 12965 // These must follow all instruction definitions as they use the names | |
| 12966 // defined in the instructions definitions. | |
| 12967 // | |
| 605 | 12968 // peepmatch ( root_instr_name [preceding_instruction]* ); |
| 0 | 12969 // |
| 12970 // peepconstraint %{ | |
| 12971 // (instruction_number.operand_name relational_op instruction_number.operand_name | |
| 12972 // [, ...] ); | |
| 12973 // // instruction numbers are zero-based using left to right order in peepmatch | |
| 12974 // | |
| 12975 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) ); | |
| 12976 // // provide an instruction_number.operand_name for each operand that appears | |
| 12977 // // in the replacement instruction's match rule | |
| 12978 // | |
| 12979 // ---------VM FLAGS--------------------------------------------------------- | |
| 12980 // | |
| 12981 // All peephole optimizations can be turned off using -XX:-OptoPeephole | |
| 12982 // | |
| 12983 // Each peephole rule is given an identifying number starting with zero and | |
| 12984 // increasing by one in the order seen by the parser. An individual peephole | |
| 12985 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=# | |
| 12986 // on the command-line. | |
| 12987 // | |
| 12988 // ---------CURRENT LIMITATIONS---------------------------------------------- | |
| 12989 // | |
| 12990 // Only match adjacent instructions in same basic block | |
| 12991 // Only equality constraints | |
| 12992 // Only constraints between operands, not (0.dest_reg == EAX_enc) | |
| 12993 // Only one replacement instruction | |
| 12994 // | |
| 12995 // ---------EXAMPLE---------------------------------------------------------- | |
| 12996 // | |
| 12997 // // pertinent parts of existing instructions in architecture description | |
|
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12998 // instruct movI(rRegI dst, rRegI src) %{ |
| 0 | 12999 // match(Set dst (CopyI src)); |
| 13000 // %} | |
| 13001 // | |
|
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13002 // instruct incI_eReg(rRegI dst, immI1 src, eFlagsReg cr) %{ |
| 0 | 13003 // match(Set dst (AddI dst src)); |
| 13004 // effect(KILL cr); | |
| 13005 // %} | |
| 13006 // | |
| 13007 // // Change (inc mov) to lea | |
| 13008 // peephole %{ | |
| 13009 // // increment preceeded by register-register move | |
| 13010 // peepmatch ( incI_eReg movI ); | |
| 13011 // // require that the destination register of the increment | |
| 13012 // // match the destination register of the move | |
| 13013 // peepconstraint ( 0.dst == 1.dst ); | |
| 13014 // // construct a replacement instruction that sets | |
| 13015 // // the destination to ( move's source register + one ) | |
| 13016 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); | |
| 13017 // %} | |
| 13018 // | |
| 13019 // Implementation no longer uses movX instructions since | |
| 13020 // machine-independent system no longer uses CopyX nodes. | |
| 13021 // | |
| 13022 // peephole %{ | |
| 13023 // peepmatch ( incI_eReg movI ); | |
| 13024 // peepconstraint ( 0.dst == 1.dst ); | |
| 13025 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); | |
| 13026 // %} | |
| 13027 // | |
| 13028 // peephole %{ | |
| 13029 // peepmatch ( decI_eReg movI ); | |
| 13030 // peepconstraint ( 0.dst == 1.dst ); | |
| 13031 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); | |
| 13032 // %} | |
| 13033 // | |
| 13034 // peephole %{ | |
| 13035 // peepmatch ( addI_eReg_imm movI ); | |
| 13036 // peepconstraint ( 0.dst == 1.dst ); | |
| 13037 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); | |
| 13038 // %} | |
| 13039 // | |
| 13040 // peephole %{ | |
| 13041 // peepmatch ( addP_eReg_imm movP ); | |
| 13042 // peepconstraint ( 0.dst == 1.dst ); | |
| 13043 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) ); | |
| 13044 // %} | |
| 13045 | |
| 13046 // // Change load of spilled value to only a spill | |
|
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13047 // instruct storeI(memory mem, rRegI src) %{ |
| 0 | 13048 // match(Set mem (StoreI mem src)); |
| 13049 // %} | |
| 13050 // | |
|
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13051 // instruct loadI(rRegI dst, memory mem) %{ |
| 0 | 13052 // match(Set dst (LoadI mem)); |
| 13053 // %} | |
| 13054 // | |
| 13055 peephole %{ | |
| 13056 peepmatch ( loadI storeI ); | |
| 13057 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem ); | |
| 13058 peepreplace ( storeI( 1.mem 1.mem 1.src ) ); | |
| 13059 %} | |
| 13060 | |
| 13061 //----------SMARTSPILL RULES--------------------------------------------------- | |
| 13062 // These must follow all instruction definitions as they use the names | |
| 13063 // defined in the instructions definitions. |