Mercurial > hg > graal-jvmci-8
annotate src/cpu/x86/vm/assembler_x86.cpp @ 671:d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
Reviewed-by: kvn, phh
author | never |
---|---|
date | Thu, 26 Mar 2009 14:31:45 -0700 |
parents | c89f86385056 |
children | fbde8ec322d0 |
rev | line source |
---|---|
0 | 1 /* |
624 | 2 * Copyright 1997-2009 Sun Microsystems, Inc. All Rights Reserved. |
0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
4 * | |
5 * This code is free software; you can redistribute it and/or modify it | |
6 * under the terms of the GNU General Public License version 2 only, as | |
7 * published by the Free Software Foundation. | |
8 * | |
9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 * version 2 for more details (a copy is included in the LICENSE file that | |
13 * accompanied this code). | |
14 * | |
15 * You should have received a copy of the GNU General Public License version | |
16 * 2 along with this work; if not, write to the Free Software Foundation, | |
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
18 * | |
19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
20 * CA 95054 USA or visit www.sun.com if you need additional information or | |
21 * have any questions. | |
22 * | |
23 */ | |
24 | |
25 #include "incls/_precompiled.incl" | |
304 | 26 #include "incls/_assembler_x86.cpp.incl" |
0 | 27 |
28 // Implementation of AddressLiteral | |
29 | |
30 AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) { | |
31 _is_lval = false; | |
32 _target = target; | |
33 switch (rtype) { | |
34 case relocInfo::oop_type: | |
35 // Oops are a special case. Normally they would be their own section | |
36 // but in cases like icBuffer they are literals in the code stream that | |
37 // we don't have a section for. We use none so that we get a literal address | |
38 // which is always patchable. | |
39 break; | |
40 case relocInfo::external_word_type: | |
41 _rspec = external_word_Relocation::spec(target); | |
42 break; | |
43 case relocInfo::internal_word_type: | |
44 _rspec = internal_word_Relocation::spec(target); | |
45 break; | |
46 case relocInfo::opt_virtual_call_type: | |
47 _rspec = opt_virtual_call_Relocation::spec(); | |
48 break; | |
49 case relocInfo::static_call_type: | |
50 _rspec = static_call_Relocation::spec(); | |
51 break; | |
52 case relocInfo::runtime_call_type: | |
53 _rspec = runtime_call_Relocation::spec(); | |
54 break; | |
55 case relocInfo::poll_type: | |
56 case relocInfo::poll_return_type: | |
57 _rspec = Relocation::spec_simple(rtype); | |
58 break; | |
59 case relocInfo::none: | |
60 break; | |
61 default: | |
62 ShouldNotReachHere(); | |
63 break; | |
64 } | |
65 } | |
66 | |
67 // Implementation of Address | |
68 | |
304 | 69 #ifdef _LP64 |
70 | |
0 | 71 Address Address::make_array(ArrayAddress adr) { |
72 // Not implementable on 64bit machines | |
73 // Should have been handled higher up the call chain. | |
74 ShouldNotReachHere(); | |
304 | 75 return Address(); |
76 } | |
77 | |
78 // exceedingly dangerous constructor | |
79 Address::Address(int disp, address loc, relocInfo::relocType rtype) { | |
80 _base = noreg; | |
81 _index = noreg; | |
82 _scale = no_scale; | |
83 _disp = disp; | |
84 switch (rtype) { | |
85 case relocInfo::external_word_type: | |
86 _rspec = external_word_Relocation::spec(loc); | |
87 break; | |
88 case relocInfo::internal_word_type: | |
89 _rspec = internal_word_Relocation::spec(loc); | |
90 break; | |
91 case relocInfo::runtime_call_type: | |
92 // HMM | |
93 _rspec = runtime_call_Relocation::spec(); | |
94 break; | |
95 case relocInfo::poll_type: | |
96 case relocInfo::poll_return_type: | |
97 _rspec = Relocation::spec_simple(rtype); | |
98 break; | |
99 case relocInfo::none: | |
100 break; | |
101 default: | |
102 ShouldNotReachHere(); | |
103 } | |
104 } | |
105 #else // LP64 | |
106 | |
107 Address Address::make_array(ArrayAddress adr) { | |
0 | 108 AddressLiteral base = adr.base(); |
109 Address index = adr.index(); | |
110 assert(index._disp == 0, "must not have disp"); // maybe it can? | |
111 Address array(index._base, index._index, index._scale, (intptr_t) base.target()); | |
112 array._rspec = base._rspec; | |
113 return array; | |
304 | 114 } |
0 | 115 |
116 // exceedingly dangerous constructor | |
117 Address::Address(address loc, RelocationHolder spec) { | |
118 _base = noreg; | |
119 _index = noreg; | |
120 _scale = no_scale; | |
121 _disp = (intptr_t) loc; | |
122 _rspec = spec; | |
123 } | |
304 | 124 |
0 | 125 #endif // _LP64 |
126 | |
304 | 127 |
128 | |
0 | 129 // Convert the raw encoding form into the form expected by the constructor for |
130 // Address. An index of 4 (rsp) corresponds to having no index, so convert | |
131 // that to noreg for the Address constructor. | |
624 | 132 Address Address::make_raw(int base, int index, int scale, int disp, bool disp_is_oop) { |
133 RelocationHolder rspec; | |
134 if (disp_is_oop) { | |
135 rspec = Relocation::spec_simple(relocInfo::oop_type); | |
136 } | |
0 | 137 bool valid_index = index != rsp->encoding(); |
138 if (valid_index) { | |
139 Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp)); | |
624 | 140 madr._rspec = rspec; |
0 | 141 return madr; |
142 } else { | |
143 Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp)); | |
624 | 144 madr._rspec = rspec; |
0 | 145 return madr; |
146 } | |
147 } | |
148 | |
149 // Implementation of Assembler | |
150 | |
151 int AbstractAssembler::code_fill_byte() { | |
152 return (u_char)'\xF4'; // hlt | |
153 } | |
154 | |
155 // make this go away someday | |
156 void Assembler::emit_data(jint data, relocInfo::relocType rtype, int format) { | |
157 if (rtype == relocInfo::none) | |
158 emit_long(data); | |
159 else emit_data(data, Relocation::spec_simple(rtype), format); | |
160 } | |
161 | |
162 void Assembler::emit_data(jint data, RelocationHolder const& rspec, int format) { | |
304 | 163 assert(imm_operand == 0, "default format must be immediate in this file"); |
0 | 164 assert(inst_mark() != NULL, "must be inside InstructionMark"); |
165 if (rspec.type() != relocInfo::none) { | |
166 #ifdef ASSERT | |
167 check_relocation(rspec, format); | |
168 #endif | |
169 // Do not use AbstractAssembler::relocate, which is not intended for | |
170 // embedded words. Instead, relocate to the enclosing instruction. | |
171 | |
172 // hack. call32 is too wide for mask so use disp32 | |
173 if (format == call32_operand) | |
174 code_section()->relocate(inst_mark(), rspec, disp32_operand); | |
175 else | |
176 code_section()->relocate(inst_mark(), rspec, format); | |
177 } | |
178 emit_long(data); | |
179 } | |
180 | |
304 | 181 static int encode(Register r) { |
182 int enc = r->encoding(); | |
183 if (enc >= 8) { | |
184 enc -= 8; | |
185 } | |
186 return enc; | |
187 } | |
188 | |
189 static int encode(XMMRegister r) { | |
190 int enc = r->encoding(); | |
191 if (enc >= 8) { | |
192 enc -= 8; | |
193 } | |
194 return enc; | |
195 } | |
0 | 196 |
197 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) { | |
198 assert(dst->has_byte_register(), "must have byte register"); | |
199 assert(isByte(op1) && isByte(op2), "wrong opcode"); | |
200 assert(isByte(imm8), "not a byte"); | |
201 assert((op1 & 0x01) == 0, "should be 8bit operation"); | |
202 emit_byte(op1); | |
304 | 203 emit_byte(op2 | encode(dst)); |
0 | 204 emit_byte(imm8); |
205 } | |
206 | |
207 | |
304 | 208 void Assembler::emit_arith(int op1, int op2, Register dst, int32_t imm32) { |
0 | 209 assert(isByte(op1) && isByte(op2), "wrong opcode"); |
210 assert((op1 & 0x01) == 1, "should be 32bit operation"); | |
211 assert((op1 & 0x02) == 0, "sign-extension bit should not be set"); | |
212 if (is8bit(imm32)) { | |
213 emit_byte(op1 | 0x02); // set sign bit | |
304 | 214 emit_byte(op2 | encode(dst)); |
0 | 215 emit_byte(imm32 & 0xFF); |
216 } else { | |
217 emit_byte(op1); | |
304 | 218 emit_byte(op2 | encode(dst)); |
0 | 219 emit_long(imm32); |
220 } | |
221 } | |
222 | |
223 // immediate-to-memory forms | |
304 | 224 void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32) { |
0 | 225 assert((op1 & 0x01) == 1, "should be 32bit operation"); |
226 assert((op1 & 0x02) == 0, "sign-extension bit should not be set"); | |
227 if (is8bit(imm32)) { | |
228 emit_byte(op1 | 0x02); // set sign bit | |
304 | 229 emit_operand(rm, adr, 1); |
0 | 230 emit_byte(imm32 & 0xFF); |
231 } else { | |
232 emit_byte(op1); | |
304 | 233 emit_operand(rm, adr, 4); |
0 | 234 emit_long(imm32); |
235 } | |
236 } | |
237 | |
238 void Assembler::emit_arith(int op1, int op2, Register dst, jobject obj) { | |
304 | 239 LP64_ONLY(ShouldNotReachHere()); |
0 | 240 assert(isByte(op1) && isByte(op2), "wrong opcode"); |
241 assert((op1 & 0x01) == 1, "should be 32bit operation"); | |
242 assert((op1 & 0x02) == 0, "sign-extension bit should not be set"); | |
243 InstructionMark im(this); | |
244 emit_byte(op1); | |
304 | 245 emit_byte(op2 | encode(dst)); |
246 emit_data((intptr_t)obj, relocInfo::oop_type, 0); | |
0 | 247 } |
248 | |
249 | |
250 void Assembler::emit_arith(int op1, int op2, Register dst, Register src) { | |
251 assert(isByte(op1) && isByte(op2), "wrong opcode"); | |
252 emit_byte(op1); | |
304 | 253 emit_byte(op2 | encode(dst) << 3 | encode(src)); |
254 } | |
255 | |
256 | |
257 void Assembler::emit_operand(Register reg, Register base, Register index, | |
258 Address::ScaleFactor scale, int disp, | |
259 RelocationHolder const& rspec, | |
260 int rip_relative_correction) { | |
0 | 261 relocInfo::relocType rtype = (relocInfo::relocType) rspec.type(); |
304 | 262 |
263 // Encode the registers as needed in the fields they are used in | |
264 | |
265 int regenc = encode(reg) << 3; | |
266 int indexenc = index->is_valid() ? encode(index) << 3 : 0; | |
267 int baseenc = base->is_valid() ? encode(base) : 0; | |
268 | |
0 | 269 if (base->is_valid()) { |
270 if (index->is_valid()) { | |
271 assert(scale != Address::no_scale, "inconsistent address"); | |
272 // [base + index*scale + disp] | |
304 | 273 if (disp == 0 && rtype == relocInfo::none && |
274 base != rbp LP64_ONLY(&& base != r13)) { | |
0 | 275 // [base + index*scale] |
276 // [00 reg 100][ss index base] | |
277 assert(index != rsp, "illegal addressing mode"); | |
304 | 278 emit_byte(0x04 | regenc); |
279 emit_byte(scale << 6 | indexenc | baseenc); | |
0 | 280 } else if (is8bit(disp) && rtype == relocInfo::none) { |
281 // [base + index*scale + imm8] | |
282 // [01 reg 100][ss index base] imm8 | |
283 assert(index != rsp, "illegal addressing mode"); | |
304 | 284 emit_byte(0x44 | regenc); |
285 emit_byte(scale << 6 | indexenc | baseenc); | |
0 | 286 emit_byte(disp & 0xFF); |
287 } else { | |
304 | 288 // [base + index*scale + disp32] |
289 // [10 reg 100][ss index base] disp32 | |
0 | 290 assert(index != rsp, "illegal addressing mode"); |
304 | 291 emit_byte(0x84 | regenc); |
292 emit_byte(scale << 6 | indexenc | baseenc); | |
0 | 293 emit_data(disp, rspec, disp32_operand); |
294 } | |
304 | 295 } else if (base == rsp LP64_ONLY(|| base == r12)) { |
296 // [rsp + disp] | |
0 | 297 if (disp == 0 && rtype == relocInfo::none) { |
304 | 298 // [rsp] |
0 | 299 // [00 reg 100][00 100 100] |
304 | 300 emit_byte(0x04 | regenc); |
0 | 301 emit_byte(0x24); |
302 } else if (is8bit(disp) && rtype == relocInfo::none) { | |
304 | 303 // [rsp + imm8] |
304 // [01 reg 100][00 100 100] disp8 | |
305 emit_byte(0x44 | regenc); | |
0 | 306 emit_byte(0x24); |
307 emit_byte(disp & 0xFF); | |
308 } else { | |
304 | 309 // [rsp + imm32] |
310 // [10 reg 100][00 100 100] disp32 | |
311 emit_byte(0x84 | regenc); | |
0 | 312 emit_byte(0x24); |
313 emit_data(disp, rspec, disp32_operand); | |
314 } | |
315 } else { | |
316 // [base + disp] | |
304 | 317 assert(base != rsp LP64_ONLY(&& base != r12), "illegal addressing mode"); |
318 if (disp == 0 && rtype == relocInfo::none && | |
319 base != rbp LP64_ONLY(&& base != r13)) { | |
0 | 320 // [base] |
321 // [00 reg base] | |
304 | 322 emit_byte(0x00 | regenc | baseenc); |
0 | 323 } else if (is8bit(disp) && rtype == relocInfo::none) { |
304 | 324 // [base + disp8] |
325 // [01 reg base] disp8 | |
326 emit_byte(0x40 | regenc | baseenc); | |
0 | 327 emit_byte(disp & 0xFF); |
328 } else { | |
304 | 329 // [base + disp32] |
330 // [10 reg base] disp32 | |
331 emit_byte(0x80 | regenc | baseenc); | |
0 | 332 emit_data(disp, rspec, disp32_operand); |
333 } | |
334 } | |
335 } else { | |
336 if (index->is_valid()) { | |
337 assert(scale != Address::no_scale, "inconsistent address"); | |
338 // [index*scale + disp] | |
304 | 339 // [00 reg 100][ss index 101] disp32 |
0 | 340 assert(index != rsp, "illegal addressing mode"); |
304 | 341 emit_byte(0x04 | regenc); |
342 emit_byte(scale << 6 | indexenc | 0x05); | |
0 | 343 emit_data(disp, rspec, disp32_operand); |
304 | 344 } else if (rtype != relocInfo::none ) { |
345 // [disp] (64bit) RIP-RELATIVE (32bit) abs | |
346 // [00 000 101] disp32 | |
347 | |
348 emit_byte(0x05 | regenc); | |
349 // Note that the RIP-rel. correction applies to the generated | |
350 // disp field, but _not_ to the target address in the rspec. | |
351 | |
352 // disp was created by converting the target address minus the pc | |
353 // at the start of the instruction. That needs more correction here. | |
354 // intptr_t disp = target - next_ip; | |
355 assert(inst_mark() != NULL, "must be inside InstructionMark"); | |
356 address next_ip = pc() + sizeof(int32_t) + rip_relative_correction; | |
357 int64_t adjusted = disp; | |
358 // Do rip-rel adjustment for 64bit | |
359 LP64_ONLY(adjusted -= (next_ip - inst_mark())); | |
360 assert(is_simm32(adjusted), | |
361 "must be 32bit offset (RIP relative address)"); | |
362 emit_data((int32_t) adjusted, rspec, disp32_operand); | |
363 | |
0 | 364 } else { |
304 | 365 // 32bit never did this, did everything as the rip-rel/disp code above |
366 // [disp] ABSOLUTE | |
367 // [00 reg 100][00 100 101] disp32 | |
368 emit_byte(0x04 | regenc); | |
369 emit_byte(0x25); | |
0 | 370 emit_data(disp, rspec, disp32_operand); |
371 } | |
372 } | |
373 } | |
374 | |
304 | 375 void Assembler::emit_operand(XMMRegister reg, Register base, Register index, |
376 Address::ScaleFactor scale, int disp, | |
377 RelocationHolder const& rspec) { | |
378 emit_operand((Register)reg, base, index, scale, disp, rspec); | |
379 } | |
380 | |
0 | 381 // Secret local extension to Assembler::WhichOperand: |
382 #define end_pc_operand (_WhichOperand_limit) | |
383 | |
384 address Assembler::locate_operand(address inst, WhichOperand which) { | |
385 // Decode the given instruction, and return the address of | |
386 // an embedded 32-bit operand word. | |
387 | |
388 // If "which" is disp32_operand, selects the displacement portion | |
389 // of an effective address specifier. | |
304 | 390 // If "which" is imm64_operand, selects the trailing immediate constant. |
0 | 391 // If "which" is call32_operand, selects the displacement of a call or jump. |
392 // Caller is responsible for ensuring that there is such an operand, | |
304 | 393 // and that it is 32/64 bits wide. |
0 | 394 |
395 // If "which" is end_pc_operand, find the end of the instruction. | |
396 | |
397 address ip = inst; | |
304 | 398 bool is_64bit = false; |
399 | |
400 debug_only(bool has_disp32 = false); | |
401 int tail_size = 0; // other random bytes (#32, #16, etc.) at end of insn | |
402 | |
403 again_after_prefix: | |
0 | 404 switch (0xFF & *ip++) { |
405 | |
406 // These convenience macros generate groups of "case" labels for the switch. | |
304 | 407 #define REP4(x) (x)+0: case (x)+1: case (x)+2: case (x)+3 |
408 #define REP8(x) (x)+0: case (x)+1: case (x)+2: case (x)+3: \ | |
0 | 409 case (x)+4: case (x)+5: case (x)+6: case (x)+7 |
304 | 410 #define REP16(x) REP8((x)+0): \ |
0 | 411 case REP8((x)+8) |
412 | |
413 case CS_segment: | |
414 case SS_segment: | |
415 case DS_segment: | |
416 case ES_segment: | |
417 case FS_segment: | |
418 case GS_segment: | |
304 | 419 // Seems dubious |
420 LP64_ONLY(assert(false, "shouldn't have that prefix")); | |
0 | 421 assert(ip == inst+1, "only one prefix allowed"); |
422 goto again_after_prefix; | |
423 | |
304 | 424 case 0x67: |
425 case REX: | |
426 case REX_B: | |
427 case REX_X: | |
428 case REX_XB: | |
429 case REX_R: | |
430 case REX_RB: | |
431 case REX_RX: | |
432 case REX_RXB: | |
433 NOT_LP64(assert(false, "64bit prefixes")); | |
434 goto again_after_prefix; | |
435 | |
436 case REX_W: | |
437 case REX_WB: | |
438 case REX_WX: | |
439 case REX_WXB: | |
440 case REX_WR: | |
441 case REX_WRB: | |
442 case REX_WRX: | |
443 case REX_WRXB: | |
444 NOT_LP64(assert(false, "64bit prefixes")); | |
445 is_64bit = true; | |
446 goto again_after_prefix; | |
447 | |
448 case 0xFF: // pushq a; decl a; incl a; call a; jmp a | |
0 | 449 case 0x88: // movb a, r |
450 case 0x89: // movl a, r | |
451 case 0x8A: // movb r, a | |
452 case 0x8B: // movl r, a | |
453 case 0x8F: // popl a | |
304 | 454 debug_only(has_disp32 = true); |
0 | 455 break; |
456 | |
304 | 457 case 0x68: // pushq #32 |
458 if (which == end_pc_operand) { | |
459 return ip + 4; | |
460 } | |
461 assert(which == imm_operand && !is_64bit, "pushl has no disp32 or 64bit immediate"); | |
0 | 462 return ip; // not produced by emit_operand |
463 | |
464 case 0x66: // movw ... (size prefix) | |
304 | 465 again_after_size_prefix2: |
0 | 466 switch (0xFF & *ip++) { |
304 | 467 case REX: |
468 case REX_B: | |
469 case REX_X: | |
470 case REX_XB: | |
471 case REX_R: | |
472 case REX_RB: | |
473 case REX_RX: | |
474 case REX_RXB: | |
475 case REX_W: | |
476 case REX_WB: | |
477 case REX_WX: | |
478 case REX_WXB: | |
479 case REX_WR: | |
480 case REX_WRB: | |
481 case REX_WRX: | |
482 case REX_WRXB: | |
483 NOT_LP64(assert(false, "64bit prefix found")); | |
484 goto again_after_size_prefix2; | |
0 | 485 case 0x8B: // movw r, a |
486 case 0x89: // movw a, r | |
304 | 487 debug_only(has_disp32 = true); |
0 | 488 break; |
489 case 0xC7: // movw a, #16 | |
304 | 490 debug_only(has_disp32 = true); |
0 | 491 tail_size = 2; // the imm16 |
492 break; | |
493 case 0x0F: // several SSE/SSE2 variants | |
494 ip--; // reparse the 0x0F | |
495 goto again_after_prefix; | |
496 default: | |
497 ShouldNotReachHere(); | |
498 } | |
499 break; | |
500 | |
304 | 501 case REP8(0xB8): // movl/q r, #32/#64(oop?) |
502 if (which == end_pc_operand) return ip + (is_64bit ? 8 : 4); | |
503 // these asserts are somewhat nonsensical | |
504 #ifndef _LP64 | |
505 assert(which == imm_operand || which == disp32_operand, ""); | |
506 #else | |
507 assert((which == call32_operand || which == imm_operand) && is_64bit || | |
508 which == narrow_oop_operand && !is_64bit, ""); | |
509 #endif // _LP64 | |
0 | 510 return ip; |
511 | |
512 case 0x69: // imul r, a, #32 | |
513 case 0xC7: // movl a, #32(oop?) | |
514 tail_size = 4; | |
304 | 515 debug_only(has_disp32 = true); // has both kinds of operands! |
0 | 516 break; |
517 | |
518 case 0x0F: // movx..., etc. | |
519 switch (0xFF & *ip++) { | |
520 case 0x12: // movlps | |
521 case 0x28: // movaps | |
522 case 0x2E: // ucomiss | |
523 case 0x2F: // comiss | |
524 case 0x54: // andps | |
525 case 0x55: // andnps | |
526 case 0x56: // orps | |
527 case 0x57: // xorps | |
528 case 0x6E: // movd | |
529 case 0x7E: // movd | |
530 case 0xAE: // ldmxcsr a | |
304 | 531 // 64bit side says it these have both operands but that doesn't |
532 // appear to be true | |
533 debug_only(has_disp32 = true); | |
0 | 534 break; |
535 | |
536 case 0xAD: // shrd r, a, %cl | |
537 case 0xAF: // imul r, a | |
304 | 538 case 0xBE: // movsbl r, a (movsxb) |
539 case 0xBF: // movswl r, a (movsxw) | |
540 case 0xB6: // movzbl r, a (movzxb) | |
541 case 0xB7: // movzwl r, a (movzxw) | |
0 | 542 case REP16(0x40): // cmovl cc, r, a |
543 case 0xB0: // cmpxchgb | |
544 case 0xB1: // cmpxchg | |
545 case 0xC1: // xaddl | |
546 case 0xC7: // cmpxchg8 | |
547 case REP16(0x90): // setcc a | |
304 | 548 debug_only(has_disp32 = true); |
0 | 549 // fall out of the switch to decode the address |
550 break; | |
304 | 551 |
0 | 552 case 0xAC: // shrd r, a, #8 |
304 | 553 debug_only(has_disp32 = true); |
0 | 554 tail_size = 1; // the imm8 |
555 break; | |
304 | 556 |
0 | 557 case REP16(0x80): // jcc rdisp32 |
558 if (which == end_pc_operand) return ip + 4; | |
304 | 559 assert(which == call32_operand, "jcc has no disp32 or imm"); |
0 | 560 return ip; |
561 default: | |
562 ShouldNotReachHere(); | |
563 } | |
564 break; | |
565 | |
566 case 0x81: // addl a, #32; addl r, #32 | |
567 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl | |
304 | 568 // on 32bit in the case of cmpl, the imm might be an oop |
0 | 569 tail_size = 4; |
304 | 570 debug_only(has_disp32 = true); // has both kinds of operands! |
0 | 571 break; |
572 | |
573 case 0x83: // addl a, #8; addl r, #8 | |
574 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl | |
304 | 575 debug_only(has_disp32 = true); // has both kinds of operands! |
0 | 576 tail_size = 1; |
577 break; | |
578 | |
579 case 0x9B: | |
580 switch (0xFF & *ip++) { | |
581 case 0xD9: // fnstcw a | |
304 | 582 debug_only(has_disp32 = true); |
0 | 583 break; |
584 default: | |
585 ShouldNotReachHere(); | |
586 } | |
587 break; | |
588 | |
589 case REP4(0x00): // addb a, r; addl a, r; addb r, a; addl r, a | |
590 case REP4(0x10): // adc... | |
591 case REP4(0x20): // and... | |
592 case REP4(0x30): // xor... | |
593 case REP4(0x08): // or... | |
594 case REP4(0x18): // sbb... | |
595 case REP4(0x28): // sub... | |
304 | 596 case 0xF7: // mull a |
597 case 0x8D: // lea r, a | |
598 case 0x87: // xchg r, a | |
0 | 599 case REP4(0x38): // cmp... |
304 | 600 case 0x85: // test r, a |
601 debug_only(has_disp32 = true); // has both kinds of operands! | |
0 | 602 break; |
603 | |
604 case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8 | |
605 case 0xC6: // movb a, #8 | |
606 case 0x80: // cmpb a, #8 | |
607 case 0x6B: // imul r, a, #8 | |
304 | 608 debug_only(has_disp32 = true); // has both kinds of operands! |
0 | 609 tail_size = 1; // the imm8 |
610 break; | |
611 | |
612 case 0xE8: // call rdisp32 | |
613 case 0xE9: // jmp rdisp32 | |
614 if (which == end_pc_operand) return ip + 4; | |
304 | 615 assert(which == call32_operand, "call has no disp32 or imm"); |
0 | 616 return ip; |
617 | |
618 case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1 | |
619 case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl | |
620 case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a | |
621 case 0xDD: // fld_d a; fst_d a; fstp_d a | |
622 case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a | |
623 case 0xDF: // fild_d a; fistp_d a | |
624 case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a | |
625 case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a | |
626 case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a | |
304 | 627 debug_only(has_disp32 = true); |
0 | 628 break; |
629 | |
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
405
diff
changeset
|
630 case 0xF0: // Lock |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
405
diff
changeset
|
631 assert(os::is_MP(), "only on MP"); |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
405
diff
changeset
|
632 goto again_after_prefix; |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
405
diff
changeset
|
633 |
0 | 634 case 0xF3: // For SSE |
635 case 0xF2: // For SSE2 | |
304 | 636 switch (0xFF & *ip++) { |
637 case REX: | |
638 case REX_B: | |
639 case REX_X: | |
640 case REX_XB: | |
641 case REX_R: | |
642 case REX_RB: | |
643 case REX_RX: | |
644 case REX_RXB: | |
645 case REX_W: | |
646 case REX_WB: | |
647 case REX_WX: | |
648 case REX_WXB: | |
649 case REX_WR: | |
650 case REX_WRB: | |
651 case REX_WRX: | |
652 case REX_WRXB: | |
653 NOT_LP64(assert(false, "found 64bit prefix")); | |
654 ip++; | |
655 default: | |
656 ip++; | |
657 } | |
658 debug_only(has_disp32 = true); // has both kinds of operands! | |
0 | 659 break; |
660 | |
661 default: | |
662 ShouldNotReachHere(); | |
663 | |
304 | 664 #undef REP8 |
665 #undef REP16 | |
0 | 666 } |
667 | |
668 assert(which != call32_operand, "instruction is not a call, jmp, or jcc"); | |
304 | 669 #ifdef _LP64 |
670 assert(which != imm_operand, "instruction is not a movq reg, imm64"); | |
671 #else | |
672 // assert(which != imm_operand || has_imm32, "instruction has no imm32 field"); | |
673 assert(which != imm_operand || has_disp32, "instruction has no imm32 field"); | |
674 #endif // LP64 | |
675 assert(which != disp32_operand || has_disp32, "instruction has no disp32 field"); | |
0 | 676 |
677 // parse the output of emit_operand | |
678 int op2 = 0xFF & *ip++; | |
679 int base = op2 & 0x07; | |
680 int op3 = -1; | |
681 const int b100 = 4; | |
682 const int b101 = 5; | |
683 if (base == b100 && (op2 >> 6) != 3) { | |
684 op3 = 0xFF & *ip++; | |
685 base = op3 & 0x07; // refetch the base | |
686 } | |
687 // now ip points at the disp (if any) | |
688 | |
689 switch (op2 >> 6) { | |
690 case 0: | |
691 // [00 reg 100][ss index base] | |
304 | 692 // [00 reg 100][00 100 esp] |
0 | 693 // [00 reg base] |
694 // [00 reg 100][ss index 101][disp32] | |
695 // [00 reg 101] [disp32] | |
696 | |
697 if (base == b101) { | |
698 if (which == disp32_operand) | |
699 return ip; // caller wants the disp32 | |
700 ip += 4; // skip the disp32 | |
701 } | |
702 break; | |
703 | |
704 case 1: | |
705 // [01 reg 100][ss index base][disp8] | |
304 | 706 // [01 reg 100][00 100 esp][disp8] |
0 | 707 // [01 reg base] [disp8] |
708 ip += 1; // skip the disp8 | |
709 break; | |
710 | |
711 case 2: | |
712 // [10 reg 100][ss index base][disp32] | |
304 | 713 // [10 reg 100][00 100 esp][disp32] |
0 | 714 // [10 reg base] [disp32] |
715 if (which == disp32_operand) | |
716 return ip; // caller wants the disp32 | |
717 ip += 4; // skip the disp32 | |
718 break; | |
719 | |
720 case 3: | |
721 // [11 reg base] (not a memory addressing mode) | |
722 break; | |
723 } | |
724 | |
725 if (which == end_pc_operand) { | |
726 return ip + tail_size; | |
727 } | |
728 | |
304 | 729 #ifdef _LP64 |
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
730 assert(which == narrow_oop_operand && !is_64bit, "instruction is not a movl adr, imm32"); |
304 | 731 #else |
732 assert(which == imm_operand, "instruction has only an imm field"); | |
733 #endif // LP64 | |
0 | 734 return ip; |
735 } | |
736 | |
737 address Assembler::locate_next_instruction(address inst) { | |
738 // Secretly share code with locate_operand: | |
739 return locate_operand(inst, end_pc_operand); | |
740 } | |
741 | |
742 | |
743 #ifdef ASSERT | |
744 void Assembler::check_relocation(RelocationHolder const& rspec, int format) { | |
745 address inst = inst_mark(); | |
746 assert(inst != NULL && inst < pc(), "must point to beginning of instruction"); | |
747 address opnd; | |
748 | |
749 Relocation* r = rspec.reloc(); | |
750 if (r->type() == relocInfo::none) { | |
751 return; | |
752 } else if (r->is_call() || format == call32_operand) { | |
753 // assert(format == imm32_operand, "cannot specify a nonzero format"); | |
754 opnd = locate_operand(inst, call32_operand); | |
755 } else if (r->is_data()) { | |
304 | 756 assert(format == imm_operand || format == disp32_operand |
757 LP64_ONLY(|| format == narrow_oop_operand), "format ok"); | |
0 | 758 opnd = locate_operand(inst, (WhichOperand)format); |
759 } else { | |
304 | 760 assert(format == imm_operand, "cannot specify a format"); |
0 | 761 return; |
762 } | |
763 assert(opnd == pc(), "must put operand where relocs can find it"); | |
764 } | |
304 | 765 #endif // ASSERT |
766 | |
767 void Assembler::emit_operand32(Register reg, Address adr) { | |
768 assert(reg->encoding() < 8, "no extended registers"); | |
769 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers"); | |
770 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, | |
771 adr._rspec); | |
772 } | |
773 | |
774 void Assembler::emit_operand(Register reg, Address adr, | |
775 int rip_relative_correction) { | |
776 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, | |
777 adr._rspec, | |
778 rip_relative_correction); | |
779 } | |
780 | |
781 void Assembler::emit_operand(XMMRegister reg, Address adr) { | |
782 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, | |
783 adr._rspec); | |
784 } | |
785 | |
786 // MMX operations | |
787 void Assembler::emit_operand(MMXRegister reg, Address adr) { | |
788 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers"); | |
789 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec); | |
790 } | |
791 | |
792 // work around gcc (3.2.1-7a) bug | |
793 void Assembler::emit_operand(Address adr, MMXRegister reg) { | |
794 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers"); | |
795 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec); | |
0 | 796 } |
797 | |
798 | |
799 void Assembler::emit_farith(int b1, int b2, int i) { | |
800 assert(isByte(b1) && isByte(b2), "wrong opcode"); | |
801 assert(0 <= i && i < 8, "illegal stack offset"); | |
802 emit_byte(b1); | |
803 emit_byte(b2 + i); | |
804 } | |
805 | |
806 | |
304 | 807 // Now the Assembler instruction (identical for 32/64 bits) |
808 | |
809 void Assembler::adcl(Register dst, int32_t imm32) { | |
810 prefix(dst); | |
0 | 811 emit_arith(0x81, 0xD0, dst, imm32); |
812 } | |
813 | |
814 void Assembler::adcl(Register dst, Address src) { | |
815 InstructionMark im(this); | |
304 | 816 prefix(src, dst); |
0 | 817 emit_byte(0x13); |
818 emit_operand(dst, src); | |
819 } | |
820 | |
821 void Assembler::adcl(Register dst, Register src) { | |
304 | 822 (void) prefix_and_encode(dst->encoding(), src->encoding()); |
0 | 823 emit_arith(0x13, 0xC0, dst, src); |
824 } | |
825 | |
304 | 826 void Assembler::addl(Address dst, int32_t imm32) { |
827 InstructionMark im(this); | |
828 prefix(dst); | |
829 emit_arith_operand(0x81, rax, dst, imm32); | |
830 } | |
0 | 831 |
832 void Assembler::addl(Address dst, Register src) { | |
833 InstructionMark im(this); | |
304 | 834 prefix(dst, src); |
0 | 835 emit_byte(0x01); |
836 emit_operand(src, dst); | |
837 } | |
838 | |
304 | 839 void Assembler::addl(Register dst, int32_t imm32) { |
840 prefix(dst); | |
0 | 841 emit_arith(0x81, 0xC0, dst, imm32); |
842 } | |
843 | |
844 void Assembler::addl(Register dst, Address src) { | |
845 InstructionMark im(this); | |
304 | 846 prefix(src, dst); |
0 | 847 emit_byte(0x03); |
848 emit_operand(dst, src); | |
849 } | |
850 | |
851 void Assembler::addl(Register dst, Register src) { | |
304 | 852 (void) prefix_and_encode(dst->encoding(), src->encoding()); |
0 | 853 emit_arith(0x03, 0xC0, dst, src); |
854 } | |
855 | |
856 void Assembler::addr_nop_4() { | |
857 // 4 bytes: NOP DWORD PTR [EAX+0] | |
858 emit_byte(0x0F); | |
859 emit_byte(0x1F); | |
860 emit_byte(0x40); // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc); | |
861 emit_byte(0); // 8-bits offset (1 byte) | |
862 } | |
863 | |
864 void Assembler::addr_nop_5() { | |
865 // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset | |
866 emit_byte(0x0F); | |
867 emit_byte(0x1F); | |
868 emit_byte(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4); | |
869 emit_byte(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc); | |
870 emit_byte(0); // 8-bits offset (1 byte) | |
871 } | |
872 | |
873 void Assembler::addr_nop_7() { | |
874 // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset | |
875 emit_byte(0x0F); | |
876 emit_byte(0x1F); | |
877 emit_byte(0x80); // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc); | |
878 emit_long(0); // 32-bits offset (4 bytes) | |
879 } | |
880 | |
881 void Assembler::addr_nop_8() { | |
882 // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset | |
883 emit_byte(0x0F); | |
884 emit_byte(0x1F); | |
885 emit_byte(0x84); // emit_rm(cbuf, 0x2, EAX_enc, 0x4); | |
886 emit_byte(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc); | |
887 emit_long(0); // 32-bits offset (4 bytes) | |
888 } | |
889 | |
304 | 890 void Assembler::addsd(XMMRegister dst, XMMRegister src) { |
891 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
892 emit_byte(0xF2); | |
893 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
894 emit_byte(0x0F); | |
895 emit_byte(0x58); | |
896 emit_byte(0xC0 | encode); | |
897 } | |
898 | |
899 void Assembler::addsd(XMMRegister dst, Address src) { | |
900 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
901 InstructionMark im(this); | |
902 emit_byte(0xF2); | |
903 prefix(src, dst); | |
904 emit_byte(0x0F); | |
905 emit_byte(0x58); | |
906 emit_operand(dst, src); | |
907 } | |
908 | |
909 void Assembler::addss(XMMRegister dst, XMMRegister src) { | |
910 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
911 emit_byte(0xF3); | |
912 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
913 emit_byte(0x0F); | |
914 emit_byte(0x58); | |
915 emit_byte(0xC0 | encode); | |
916 } | |
917 | |
918 void Assembler::addss(XMMRegister dst, Address src) { | |
919 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
920 InstructionMark im(this); | |
921 emit_byte(0xF3); | |
922 prefix(src, dst); | |
923 emit_byte(0x0F); | |
924 emit_byte(0x58); | |
925 emit_operand(dst, src); | |
926 } | |
927 | |
928 void Assembler::andl(Register dst, int32_t imm32) { | |
929 prefix(dst); | |
930 emit_arith(0x81, 0xE0, dst, imm32); | |
931 } | |
932 | |
933 void Assembler::andl(Register dst, Address src) { | |
934 InstructionMark im(this); | |
935 prefix(src, dst); | |
936 emit_byte(0x23); | |
937 emit_operand(dst, src); | |
938 } | |
939 | |
940 void Assembler::andl(Register dst, Register src) { | |
941 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
942 emit_arith(0x23, 0xC0, dst, src); | |
943 } | |
944 | |
945 void Assembler::andpd(XMMRegister dst, Address src) { | |
946 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
947 InstructionMark im(this); | |
948 emit_byte(0x66); | |
949 prefix(src, dst); | |
950 emit_byte(0x0F); | |
951 emit_byte(0x54); | |
952 emit_operand(dst, src); | |
953 } | |
954 | |
955 void Assembler::bswapl(Register reg) { // bswap | |
956 int encode = prefix_and_encode(reg->encoding()); | |
957 emit_byte(0x0F); | |
958 emit_byte(0xC8 | encode); | |
959 } | |
960 | |
961 void Assembler::call(Label& L, relocInfo::relocType rtype) { | |
962 // suspect disp32 is always good | |
963 int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand); | |
964 | |
965 if (L.is_bound()) { | |
966 const int long_size = 5; | |
967 int offs = (int)( target(L) - pc() ); | |
968 assert(offs <= 0, "assembler error"); | |
969 InstructionMark im(this); | |
970 // 1110 1000 #32-bit disp | |
971 emit_byte(0xE8); | |
972 emit_data(offs - long_size, rtype, operand); | |
973 } else { | |
974 InstructionMark im(this); | |
975 // 1110 1000 #32-bit disp | |
976 L.add_patch_at(code(), locator()); | |
977 | |
978 emit_byte(0xE8); | |
979 emit_data(int(0), rtype, operand); | |
980 } | |
981 } | |
982 | |
983 void Assembler::call(Register dst) { | |
984 // This was originally using a 32bit register encoding | |
985 // and surely we want 64bit! | |
986 // this is a 32bit encoding but in 64bit mode the default | |
987 // operand size is 64bit so there is no need for the | |
988 // wide prefix. So prefix only happens if we use the | |
989 // new registers. Much like push/pop. | |
990 int x = offset(); | |
991 // this may be true but dbx disassembles it as if it | |
992 // were 32bits... | |
993 // int encode = prefix_and_encode(dst->encoding()); | |
994 // if (offset() != x) assert(dst->encoding() >= 8, "what?"); | |
995 int encode = prefixq_and_encode(dst->encoding()); | |
996 | |
997 emit_byte(0xFF); | |
998 emit_byte(0xD0 | encode); | |
999 } | |
1000 | |
1001 | |
1002 void Assembler::call(Address adr) { | |
1003 InstructionMark im(this); | |
1004 prefix(adr); | |
1005 emit_byte(0xFF); | |
1006 emit_operand(rdx, adr); | |
1007 } | |
1008 | |
1009 void Assembler::call_literal(address entry, RelocationHolder const& rspec) { | |
1010 assert(entry != NULL, "call most probably wrong"); | |
1011 InstructionMark im(this); | |
1012 emit_byte(0xE8); | |
1013 intptr_t disp = entry - (_code_pos + sizeof(int32_t)); | |
1014 assert(is_simm32(disp), "must be 32bit offset (call2)"); | |
1015 // Technically, should use call32_operand, but this format is | |
1016 // implied by the fact that we're emitting a call instruction. | |
1017 | |
1018 int operand = LP64_ONLY(disp32_operand) NOT_LP64(call32_operand); | |
1019 emit_data((int) disp, rspec, operand); | |
1020 } | |
1021 | |
1022 void Assembler::cdql() { | |
1023 emit_byte(0x99); | |
1024 } | |
1025 | |
1026 void Assembler::cmovl(Condition cc, Register dst, Register src) { | |
1027 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction")); | |
1028 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1029 emit_byte(0x0F); | |
1030 emit_byte(0x40 | cc); | |
1031 emit_byte(0xC0 | encode); | |
1032 } | |
1033 | |
1034 | |
1035 void Assembler::cmovl(Condition cc, Register dst, Address src) { | |
1036 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction")); | |
1037 prefix(src, dst); | |
1038 emit_byte(0x0F); | |
1039 emit_byte(0x40 | cc); | |
1040 emit_operand(dst, src); | |
1041 } | |
1042 | |
1043 void Assembler::cmpb(Address dst, int imm8) { | |
1044 InstructionMark im(this); | |
1045 prefix(dst); | |
1046 emit_byte(0x80); | |
1047 emit_operand(rdi, dst, 1); | |
1048 emit_byte(imm8); | |
1049 } | |
1050 | |
1051 void Assembler::cmpl(Address dst, int32_t imm32) { | |
1052 InstructionMark im(this); | |
1053 prefix(dst); | |
1054 emit_byte(0x81); | |
1055 emit_operand(rdi, dst, 4); | |
1056 emit_long(imm32); | |
1057 } | |
1058 | |
1059 void Assembler::cmpl(Register dst, int32_t imm32) { | |
1060 prefix(dst); | |
1061 emit_arith(0x81, 0xF8, dst, imm32); | |
1062 } | |
1063 | |
1064 void Assembler::cmpl(Register dst, Register src) { | |
1065 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
1066 emit_arith(0x3B, 0xC0, dst, src); | |
1067 } | |
1068 | |
1069 | |
1070 void Assembler::cmpl(Register dst, Address src) { | |
1071 InstructionMark im(this); | |
1072 prefix(src, dst); | |
1073 emit_byte(0x3B); | |
1074 emit_operand(dst, src); | |
1075 } | |
1076 | |
1077 void Assembler::cmpw(Address dst, int imm16) { | |
1078 InstructionMark im(this); | |
1079 assert(!dst.base_needs_rex() && !dst.index_needs_rex(), "no extended registers"); | |
1080 emit_byte(0x66); | |
1081 emit_byte(0x81); | |
1082 emit_operand(rdi, dst, 2); | |
1083 emit_word(imm16); | |
1084 } | |
1085 | |
1086 // The 32-bit cmpxchg compares the value at adr with the contents of rax, | |
1087 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,. | |
1088 // The ZF is set if the compared values were equal, and cleared otherwise. | |
1089 void Assembler::cmpxchgl(Register reg, Address adr) { // cmpxchg | |
1090 if (Atomics & 2) { | |
1091 // caveat: no instructionmark, so this isn't relocatable. | |
1092 // Emit a synthetic, non-atomic, CAS equivalent. | |
1093 // Beware. The synthetic form sets all ICCs, not just ZF. | |
1094 // cmpxchg r,[m] is equivalent to rax, = CAS (m, rax, r) | |
1095 cmpl(rax, adr); | |
1096 movl(rax, adr); | |
1097 if (reg != rax) { | |
1098 Label L ; | |
1099 jcc(Assembler::notEqual, L); | |
1100 movl(adr, reg); | |
1101 bind(L); | |
1102 } | |
1103 } else { | |
1104 InstructionMark im(this); | |
1105 prefix(adr, reg); | |
1106 emit_byte(0x0F); | |
1107 emit_byte(0xB1); | |
1108 emit_operand(reg, adr); | |
1109 } | |
1110 } | |
1111 | |
1112 void Assembler::comisd(XMMRegister dst, Address src) { | |
1113 // NOTE: dbx seems to decode this as comiss even though the | |
1114 // 0x66 is there. Strangly ucomisd comes out correct | |
1115 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1116 emit_byte(0x66); | |
1117 comiss(dst, src); | |
1118 } | |
1119 | |
1120 void Assembler::comiss(XMMRegister dst, Address src) { | |
1121 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
1122 | |
1123 InstructionMark im(this); | |
1124 prefix(src, dst); | |
1125 emit_byte(0x0F); | |
1126 emit_byte(0x2F); | |
1127 emit_operand(dst, src); | |
1128 } | |
1129 | |
1130 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) { | |
1131 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1132 emit_byte(0xF3); | |
1133 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1134 emit_byte(0x0F); | |
1135 emit_byte(0xE6); | |
1136 emit_byte(0xC0 | encode); | |
1137 } | |
1138 | |
1139 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) { | |
1140 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1141 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1142 emit_byte(0x0F); | |
1143 emit_byte(0x5B); | |
1144 emit_byte(0xC0 | encode); | |
1145 } | |
1146 | |
1147 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) { | |
1148 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1149 emit_byte(0xF2); | |
1150 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1151 emit_byte(0x0F); | |
1152 emit_byte(0x5A); | |
1153 emit_byte(0xC0 | encode); | |
1154 } | |
1155 | |
1156 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) { | |
1157 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1158 emit_byte(0xF2); | |
1159 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1160 emit_byte(0x0F); | |
1161 emit_byte(0x2A); | |
1162 emit_byte(0xC0 | encode); | |
1163 } | |
1164 | |
1165 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) { | |
1166 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
1167 emit_byte(0xF3); | |
1168 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1169 emit_byte(0x0F); | |
1170 emit_byte(0x2A); | |
1171 emit_byte(0xC0 | encode); | |
1172 } | |
1173 | |
1174 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) { | |
1175 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1176 emit_byte(0xF3); | |
1177 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1178 emit_byte(0x0F); | |
1179 emit_byte(0x5A); | |
1180 emit_byte(0xC0 | encode); | |
1181 } | |
1182 | |
1183 void Assembler::cvttsd2sil(Register dst, XMMRegister src) { | |
1184 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1185 emit_byte(0xF2); | |
1186 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1187 emit_byte(0x0F); | |
1188 emit_byte(0x2C); | |
1189 emit_byte(0xC0 | encode); | |
1190 } | |
1191 | |
1192 void Assembler::cvttss2sil(Register dst, XMMRegister src) { | |
1193 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
1194 emit_byte(0xF3); | |
1195 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1196 emit_byte(0x0F); | |
1197 emit_byte(0x2C); | |
1198 emit_byte(0xC0 | encode); | |
1199 } | |
1200 | |
1201 void Assembler::decl(Address dst) { | |
1202 // Don't use it directly. Use MacroAssembler::decrement() instead. | |
1203 InstructionMark im(this); | |
1204 prefix(dst); | |
1205 emit_byte(0xFF); | |
1206 emit_operand(rcx, dst); | |
1207 } | |
1208 | |
1209 void Assembler::divsd(XMMRegister dst, Address src) { | |
1210 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1211 InstructionMark im(this); | |
1212 emit_byte(0xF2); | |
1213 prefix(src, dst); | |
1214 emit_byte(0x0F); | |
1215 emit_byte(0x5E); | |
1216 emit_operand(dst, src); | |
1217 } | |
1218 | |
1219 void Assembler::divsd(XMMRegister dst, XMMRegister src) { | |
1220 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1221 emit_byte(0xF2); | |
1222 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1223 emit_byte(0x0F); | |
1224 emit_byte(0x5E); | |
1225 emit_byte(0xC0 | encode); | |
1226 } | |
1227 | |
1228 void Assembler::divss(XMMRegister dst, Address src) { | |
1229 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
1230 InstructionMark im(this); | |
1231 emit_byte(0xF3); | |
1232 prefix(src, dst); | |
1233 emit_byte(0x0F); | |
1234 emit_byte(0x5E); | |
1235 emit_operand(dst, src); | |
1236 } | |
1237 | |
1238 void Assembler::divss(XMMRegister dst, XMMRegister src) { | |
1239 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
1240 emit_byte(0xF3); | |
1241 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1242 emit_byte(0x0F); | |
1243 emit_byte(0x5E); | |
1244 emit_byte(0xC0 | encode); | |
1245 } | |
1246 | |
1247 void Assembler::emms() { | |
1248 NOT_LP64(assert(VM_Version::supports_mmx(), "")); | |
1249 emit_byte(0x0F); | |
1250 emit_byte(0x77); | |
1251 } | |
1252 | |
1253 void Assembler::hlt() { | |
1254 emit_byte(0xF4); | |
1255 } | |
1256 | |
1257 void Assembler::idivl(Register src) { | |
1258 int encode = prefix_and_encode(src->encoding()); | |
1259 emit_byte(0xF7); | |
1260 emit_byte(0xF8 | encode); | |
1261 } | |
1262 | |
1263 void Assembler::imull(Register dst, Register src) { | |
1264 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1265 emit_byte(0x0F); | |
1266 emit_byte(0xAF); | |
1267 emit_byte(0xC0 | encode); | |
1268 } | |
1269 | |
1270 | |
1271 void Assembler::imull(Register dst, Register src, int value) { | |
1272 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1273 if (is8bit(value)) { | |
1274 emit_byte(0x6B); | |
1275 emit_byte(0xC0 | encode); | |
1276 emit_byte(value); | |
1277 } else { | |
1278 emit_byte(0x69); | |
1279 emit_byte(0xC0 | encode); | |
1280 emit_long(value); | |
1281 } | |
1282 } | |
1283 | |
1284 void Assembler::incl(Address dst) { | |
1285 // Don't use it directly. Use MacroAssembler::increment() instead. | |
1286 InstructionMark im(this); | |
1287 prefix(dst); | |
1288 emit_byte(0xFF); | |
1289 emit_operand(rax, dst); | |
1290 } | |
1291 | |
1292 void Assembler::jcc(Condition cc, Label& L, relocInfo::relocType rtype) { | |
1293 InstructionMark im(this); | |
1294 relocate(rtype); | |
1295 assert((0 <= cc) && (cc < 16), "illegal cc"); | |
1296 if (L.is_bound()) { | |
1297 address dst = target(L); | |
1298 assert(dst != NULL, "jcc most probably wrong"); | |
1299 | |
1300 const int short_size = 2; | |
1301 const int long_size = 6; | |
1302 intptr_t offs = (intptr_t)dst - (intptr_t)_code_pos; | |
1303 if (rtype == relocInfo::none && is8bit(offs - short_size)) { | |
1304 // 0111 tttn #8-bit disp | |
1305 emit_byte(0x70 | cc); | |
1306 emit_byte((offs - short_size) & 0xFF); | |
1307 } else { | |
1308 // 0000 1111 1000 tttn #32-bit disp | |
1309 assert(is_simm32(offs - long_size), | |
1310 "must be 32bit offset (call4)"); | |
1311 emit_byte(0x0F); | |
1312 emit_byte(0x80 | cc); | |
1313 emit_long(offs - long_size); | |
1314 } | |
1315 } else { | |
1316 // Note: could eliminate cond. jumps to this jump if condition | |
1317 // is the same however, seems to be rather unlikely case. | |
1318 // Note: use jccb() if label to be bound is very close to get | |
1319 // an 8-bit displacement | |
1320 L.add_patch_at(code(), locator()); | |
1321 emit_byte(0x0F); | |
1322 emit_byte(0x80 | cc); | |
1323 emit_long(0); | |
1324 } | |
1325 } | |
1326 | |
1327 void Assembler::jccb(Condition cc, Label& L) { | |
1328 if (L.is_bound()) { | |
1329 const int short_size = 2; | |
1330 address entry = target(L); | |
1331 assert(is8bit((intptr_t)entry - ((intptr_t)_code_pos + short_size)), | |
1332 "Dispacement too large for a short jmp"); | |
1333 intptr_t offs = (intptr_t)entry - (intptr_t)_code_pos; | |
1334 // 0111 tttn #8-bit disp | |
1335 emit_byte(0x70 | cc); | |
1336 emit_byte((offs - short_size) & 0xFF); | |
1337 } else { | |
1338 InstructionMark im(this); | |
1339 L.add_patch_at(code(), locator()); | |
1340 emit_byte(0x70 | cc); | |
1341 emit_byte(0); | |
1342 } | |
1343 } | |
1344 | |
1345 void Assembler::jmp(Address adr) { | |
1346 InstructionMark im(this); | |
1347 prefix(adr); | |
1348 emit_byte(0xFF); | |
1349 emit_operand(rsp, adr); | |
1350 } | |
1351 | |
1352 void Assembler::jmp(Label& L, relocInfo::relocType rtype) { | |
1353 if (L.is_bound()) { | |
1354 address entry = target(L); | |
1355 assert(entry != NULL, "jmp most probably wrong"); | |
1356 InstructionMark im(this); | |
1357 const int short_size = 2; | |
1358 const int long_size = 5; | |
1359 intptr_t offs = entry - _code_pos; | |
1360 if (rtype == relocInfo::none && is8bit(offs - short_size)) { | |
1361 emit_byte(0xEB); | |
1362 emit_byte((offs - short_size) & 0xFF); | |
1363 } else { | |
1364 emit_byte(0xE9); | |
1365 emit_long(offs - long_size); | |
1366 } | |
1367 } else { | |
1368 // By default, forward jumps are always 32-bit displacements, since | |
1369 // we can't yet know where the label will be bound. If you're sure that | |
1370 // the forward jump will not run beyond 256 bytes, use jmpb to | |
1371 // force an 8-bit displacement. | |
1372 InstructionMark im(this); | |
1373 relocate(rtype); | |
1374 L.add_patch_at(code(), locator()); | |
1375 emit_byte(0xE9); | |
1376 emit_long(0); | |
1377 } | |
1378 } | |
1379 | |
1380 void Assembler::jmp(Register entry) { | |
1381 int encode = prefix_and_encode(entry->encoding()); | |
1382 emit_byte(0xFF); | |
1383 emit_byte(0xE0 | encode); | |
1384 } | |
1385 | |
1386 void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) { | |
1387 InstructionMark im(this); | |
1388 emit_byte(0xE9); | |
1389 assert(dest != NULL, "must have a target"); | |
1390 intptr_t disp = dest - (_code_pos + sizeof(int32_t)); | |
1391 assert(is_simm32(disp), "must be 32bit offset (jmp)"); | |
1392 emit_data(disp, rspec.reloc(), call32_operand); | |
1393 } | |
1394 | |
1395 void Assembler::jmpb(Label& L) { | |
1396 if (L.is_bound()) { | |
1397 const int short_size = 2; | |
1398 address entry = target(L); | |
1399 assert(is8bit((entry - _code_pos) + short_size), | |
1400 "Dispacement too large for a short jmp"); | |
1401 assert(entry != NULL, "jmp most probably wrong"); | |
1402 intptr_t offs = entry - _code_pos; | |
1403 emit_byte(0xEB); | |
1404 emit_byte((offs - short_size) & 0xFF); | |
1405 } else { | |
1406 InstructionMark im(this); | |
1407 L.add_patch_at(code(), locator()); | |
1408 emit_byte(0xEB); | |
1409 emit_byte(0); | |
1410 } | |
1411 } | |
1412 | |
1413 void Assembler::ldmxcsr( Address src) { | |
1414 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
1415 InstructionMark im(this); | |
1416 prefix(src); | |
1417 emit_byte(0x0F); | |
1418 emit_byte(0xAE); | |
1419 emit_operand(as_Register(2), src); | |
1420 } | |
1421 | |
1422 void Assembler::leal(Register dst, Address src) { | |
1423 InstructionMark im(this); | |
1424 #ifdef _LP64 | |
1425 emit_byte(0x67); // addr32 | |
1426 prefix(src, dst); | |
1427 #endif // LP64 | |
1428 emit_byte(0x8D); | |
1429 emit_operand(dst, src); | |
1430 } | |
1431 | |
1432 void Assembler::lock() { | |
1433 if (Atomics & 1) { | |
1434 // Emit either nothing, a NOP, or a NOP: prefix | |
1435 emit_byte(0x90) ; | |
1436 } else { | |
1437 emit_byte(0xF0); | |
1438 } | |
1439 } | |
1440 | |
671
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
665
diff
changeset
|
1441 // Emit mfence instruction |
304 | 1442 void Assembler::mfence() { |
671
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
665
diff
changeset
|
1443 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");) |
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
665
diff
changeset
|
1444 emit_byte( 0x0F ); |
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
665
diff
changeset
|
1445 emit_byte( 0xAE ); |
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
665
diff
changeset
|
1446 emit_byte( 0xF0 ); |
304 | 1447 } |
1448 | |
1449 void Assembler::mov(Register dst, Register src) { | |
1450 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); | |
1451 } | |
1452 | |
1453 void Assembler::movapd(XMMRegister dst, XMMRegister src) { | |
1454 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1455 int dstenc = dst->encoding(); | |
1456 int srcenc = src->encoding(); | |
1457 emit_byte(0x66); | |
1458 if (dstenc < 8) { | |
1459 if (srcenc >= 8) { | |
1460 prefix(REX_B); | |
1461 srcenc -= 8; | |
1462 } | |
1463 } else { | |
1464 if (srcenc < 8) { | |
1465 prefix(REX_R); | |
1466 } else { | |
1467 prefix(REX_RB); | |
1468 srcenc -= 8; | |
1469 } | |
1470 dstenc -= 8; | |
1471 } | |
1472 emit_byte(0x0F); | |
1473 emit_byte(0x28); | |
1474 emit_byte(0xC0 | dstenc << 3 | srcenc); | |
1475 } | |
1476 | |
1477 void Assembler::movaps(XMMRegister dst, XMMRegister src) { | |
1478 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
1479 int dstenc = dst->encoding(); | |
1480 int srcenc = src->encoding(); | |
1481 if (dstenc < 8) { | |
1482 if (srcenc >= 8) { | |
1483 prefix(REX_B); | |
1484 srcenc -= 8; | |
1485 } | |
1486 } else { | |
1487 if (srcenc < 8) { | |
1488 prefix(REX_R); | |
1489 } else { | |
1490 prefix(REX_RB); | |
1491 srcenc -= 8; | |
1492 } | |
1493 dstenc -= 8; | |
1494 } | |
1495 emit_byte(0x0F); | |
1496 emit_byte(0x28); | |
1497 emit_byte(0xC0 | dstenc << 3 | srcenc); | |
1498 } | |
1499 | |
1500 void Assembler::movb(Register dst, Address src) { | |
1501 NOT_LP64(assert(dst->has_byte_register(), "must have byte register")); | |
1502 InstructionMark im(this); | |
1503 prefix(src, dst, true); | |
1504 emit_byte(0x8A); | |
1505 emit_operand(dst, src); | |
1506 } | |
1507 | |
1508 | |
1509 void Assembler::movb(Address dst, int imm8) { | |
1510 InstructionMark im(this); | |
1511 prefix(dst); | |
1512 emit_byte(0xC6); | |
1513 emit_operand(rax, dst, 1); | |
1514 emit_byte(imm8); | |
1515 } | |
1516 | |
1517 | |
1518 void Assembler::movb(Address dst, Register src) { | |
1519 assert(src->has_byte_register(), "must have byte register"); | |
1520 InstructionMark im(this); | |
1521 prefix(dst, src, true); | |
1522 emit_byte(0x88); | |
1523 emit_operand(src, dst); | |
1524 } | |
1525 | |
1526 void Assembler::movdl(XMMRegister dst, Register src) { | |
1527 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1528 emit_byte(0x66); | |
1529 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1530 emit_byte(0x0F); | |
1531 emit_byte(0x6E); | |
1532 emit_byte(0xC0 | encode); | |
1533 } | |
1534 | |
1535 void Assembler::movdl(Register dst, XMMRegister src) { | |
1536 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1537 emit_byte(0x66); | |
1538 // swap src/dst to get correct prefix | |
1539 int encode = prefix_and_encode(src->encoding(), dst->encoding()); | |
1540 emit_byte(0x0F); | |
1541 emit_byte(0x7E); | |
1542 emit_byte(0xC0 | encode); | |
1543 } | |
1544 | |
1545 void Assembler::movdqa(XMMRegister dst, Address src) { | |
1546 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1547 InstructionMark im(this); | |
1548 emit_byte(0x66); | |
1549 prefix(src, dst); | |
1550 emit_byte(0x0F); | |
1551 emit_byte(0x6F); | |
1552 emit_operand(dst, src); | |
1553 } | |
1554 | |
1555 void Assembler::movdqa(XMMRegister dst, XMMRegister src) { | |
1556 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1557 emit_byte(0x66); | |
1558 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
1559 emit_byte(0x0F); | |
1560 emit_byte(0x6F); | |
1561 emit_byte(0xC0 | encode); | |
1562 } | |
1563 | |
1564 void Assembler::movdqa(Address dst, XMMRegister src) { | |
1565 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1566 InstructionMark im(this); | |
1567 emit_byte(0x66); | |
1568 prefix(dst, src); | |
1569 emit_byte(0x0F); | |
1570 emit_byte(0x7F); | |
1571 emit_operand(src, dst); | |
1572 } | |
1573 | |
405 | 1574 void Assembler::movdqu(XMMRegister dst, Address src) { |
1575 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1576 InstructionMark im(this); | |
1577 emit_byte(0xF3); | |
1578 prefix(src, dst); | |
1579 emit_byte(0x0F); | |
1580 emit_byte(0x6F); | |
1581 emit_operand(dst, src); | |
1582 } | |
1583 | |
1584 void Assembler::movdqu(XMMRegister dst, XMMRegister src) { | |
1585 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1586 emit_byte(0xF3); | |
1587 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
1588 emit_byte(0x0F); | |
1589 emit_byte(0x6F); | |
1590 emit_byte(0xC0 | encode); | |
1591 } | |
1592 | |
1593 void Assembler::movdqu(Address dst, XMMRegister src) { | |
1594 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1595 InstructionMark im(this); | |
1596 emit_byte(0xF3); | |
1597 prefix(dst, src); | |
1598 emit_byte(0x0F); | |
1599 emit_byte(0x7F); | |
1600 emit_operand(src, dst); | |
1601 } | |
1602 | |
304 | 1603 // Uses zero extension on 64bit |
1604 | |
1605 void Assembler::movl(Register dst, int32_t imm32) { | |
1606 int encode = prefix_and_encode(dst->encoding()); | |
1607 emit_byte(0xB8 | encode); | |
1608 emit_long(imm32); | |
1609 } | |
1610 | |
1611 void Assembler::movl(Register dst, Register src) { | |
1612 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1613 emit_byte(0x8B); | |
1614 emit_byte(0xC0 | encode); | |
1615 } | |
1616 | |
1617 void Assembler::movl(Register dst, Address src) { | |
1618 InstructionMark im(this); | |
1619 prefix(src, dst); | |
1620 emit_byte(0x8B); | |
1621 emit_operand(dst, src); | |
1622 } | |
1623 | |
1624 void Assembler::movl(Address dst, int32_t imm32) { | |
1625 InstructionMark im(this); | |
1626 prefix(dst); | |
1627 emit_byte(0xC7); | |
1628 emit_operand(rax, dst, 4); | |
1629 emit_long(imm32); | |
1630 } | |
1631 | |
1632 void Assembler::movl(Address dst, Register src) { | |
1633 InstructionMark im(this); | |
1634 prefix(dst, src); | |
1635 emit_byte(0x89); | |
1636 emit_operand(src, dst); | |
1637 } | |
1638 | |
1639 // New cpus require to use movsd and movss to avoid partial register stall | |
1640 // when loading from memory. But for old Opteron use movlpd instead of movsd. | |
1641 // The selection is done in MacroAssembler::movdbl() and movflt(). | |
1642 void Assembler::movlpd(XMMRegister dst, Address src) { | |
1643 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1644 InstructionMark im(this); | |
1645 emit_byte(0x66); | |
1646 prefix(src, dst); | |
1647 emit_byte(0x0F); | |
1648 emit_byte(0x12); | |
1649 emit_operand(dst, src); | |
1650 } | |
1651 | |
1652 void Assembler::movq( MMXRegister dst, Address src ) { | |
1653 assert( VM_Version::supports_mmx(), "" ); | |
1654 emit_byte(0x0F); | |
1655 emit_byte(0x6F); | |
1656 emit_operand(dst, src); | |
1657 } | |
1658 | |
1659 void Assembler::movq( Address dst, MMXRegister src ) { | |
1660 assert( VM_Version::supports_mmx(), "" ); | |
1661 emit_byte(0x0F); | |
1662 emit_byte(0x7F); | |
1663 // workaround gcc (3.2.1-7a) bug | |
1664 // In that version of gcc with only an emit_operand(MMX, Address) | |
1665 // gcc will tail jump and try and reverse the parameters completely | |
1666 // obliterating dst in the process. By having a version available | |
1667 // that doesn't need to swap the args at the tail jump the bug is | |
1668 // avoided. | |
1669 emit_operand(dst, src); | |
1670 } | |
1671 | |
1672 void Assembler::movq(XMMRegister dst, Address src) { | |
1673 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1674 InstructionMark im(this); | |
1675 emit_byte(0xF3); | |
1676 prefix(src, dst); | |
1677 emit_byte(0x0F); | |
1678 emit_byte(0x7E); | |
1679 emit_operand(dst, src); | |
1680 } | |
1681 | |
1682 void Assembler::movq(Address dst, XMMRegister src) { | |
1683 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1684 InstructionMark im(this); | |
1685 emit_byte(0x66); | |
1686 prefix(dst, src); | |
1687 emit_byte(0x0F); | |
1688 emit_byte(0xD6); | |
1689 emit_operand(src, dst); | |
1690 } | |
1691 | |
1692 void Assembler::movsbl(Register dst, Address src) { // movsxb | |
1693 InstructionMark im(this); | |
1694 prefix(src, dst); | |
1695 emit_byte(0x0F); | |
1696 emit_byte(0xBE); | |
1697 emit_operand(dst, src); | |
1698 } | |
1699 | |
1700 void Assembler::movsbl(Register dst, Register src) { // movsxb | |
1701 NOT_LP64(assert(src->has_byte_register(), "must have byte register")); | |
1702 int encode = prefix_and_encode(dst->encoding(), src->encoding(), true); | |
1703 emit_byte(0x0F); | |
1704 emit_byte(0xBE); | |
1705 emit_byte(0xC0 | encode); | |
1706 } | |
1707 | |
1708 void Assembler::movsd(XMMRegister dst, XMMRegister src) { | |
1709 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1710 emit_byte(0xF2); | |
1711 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1712 emit_byte(0x0F); | |
1713 emit_byte(0x10); | |
1714 emit_byte(0xC0 | encode); | |
1715 } | |
1716 | |
1717 void Assembler::movsd(XMMRegister dst, Address src) { | |
1718 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1719 InstructionMark im(this); | |
1720 emit_byte(0xF2); | |
1721 prefix(src, dst); | |
1722 emit_byte(0x0F); | |
1723 emit_byte(0x10); | |
1724 emit_operand(dst, src); | |
1725 } | |
1726 | |
1727 void Assembler::movsd(Address dst, XMMRegister src) { | |
1728 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1729 InstructionMark im(this); | |
1730 emit_byte(0xF2); | |
1731 prefix(dst, src); | |
1732 emit_byte(0x0F); | |
1733 emit_byte(0x11); | |
1734 emit_operand(src, dst); | |
1735 } | |
1736 | |
1737 void Assembler::movss(XMMRegister dst, XMMRegister src) { | |
1738 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
1739 emit_byte(0xF3); | |
1740 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1741 emit_byte(0x0F); | |
1742 emit_byte(0x10); | |
1743 emit_byte(0xC0 | encode); | |
1744 } | |
1745 | |
1746 void Assembler::movss(XMMRegister dst, Address src) { | |
1747 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
1748 InstructionMark im(this); | |
1749 emit_byte(0xF3); | |
1750 prefix(src, dst); | |
1751 emit_byte(0x0F); | |
1752 emit_byte(0x10); | |
1753 emit_operand(dst, src); | |
1754 } | |
1755 | |
1756 void Assembler::movss(Address dst, XMMRegister src) { | |
1757 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
1758 InstructionMark im(this); | |
1759 emit_byte(0xF3); | |
1760 prefix(dst, src); | |
1761 emit_byte(0x0F); | |
1762 emit_byte(0x11); | |
1763 emit_operand(src, dst); | |
1764 } | |
1765 | |
1766 void Assembler::movswl(Register dst, Address src) { // movsxw | |
1767 InstructionMark im(this); | |
1768 prefix(src, dst); | |
1769 emit_byte(0x0F); | |
1770 emit_byte(0xBF); | |
1771 emit_operand(dst, src); | |
1772 } | |
1773 | |
1774 void Assembler::movswl(Register dst, Register src) { // movsxw | |
1775 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1776 emit_byte(0x0F); | |
1777 emit_byte(0xBF); | |
1778 emit_byte(0xC0 | encode); | |
1779 } | |
1780 | |
1781 void Assembler::movw(Address dst, int imm16) { | |
1782 InstructionMark im(this); | |
1783 | |
1784 emit_byte(0x66); // switch to 16-bit mode | |
1785 prefix(dst); | |
1786 emit_byte(0xC7); | |
1787 emit_operand(rax, dst, 2); | |
1788 emit_word(imm16); | |
1789 } | |
1790 | |
1791 void Assembler::movw(Register dst, Address src) { | |
1792 InstructionMark im(this); | |
1793 emit_byte(0x66); | |
1794 prefix(src, dst); | |
1795 emit_byte(0x8B); | |
1796 emit_operand(dst, src); | |
1797 } | |
1798 | |
1799 void Assembler::movw(Address dst, Register src) { | |
1800 InstructionMark im(this); | |
1801 emit_byte(0x66); | |
1802 prefix(dst, src); | |
1803 emit_byte(0x89); | |
1804 emit_operand(src, dst); | |
1805 } | |
1806 | |
1807 void Assembler::movzbl(Register dst, Address src) { // movzxb | |
1808 InstructionMark im(this); | |
1809 prefix(src, dst); | |
1810 emit_byte(0x0F); | |
1811 emit_byte(0xB6); | |
1812 emit_operand(dst, src); | |
1813 } | |
1814 | |
1815 void Assembler::movzbl(Register dst, Register src) { // movzxb | |
1816 NOT_LP64(assert(src->has_byte_register(), "must have byte register")); | |
1817 int encode = prefix_and_encode(dst->encoding(), src->encoding(), true); | |
1818 emit_byte(0x0F); | |
1819 emit_byte(0xB6); | |
1820 emit_byte(0xC0 | encode); | |
1821 } | |
1822 | |
1823 void Assembler::movzwl(Register dst, Address src) { // movzxw | |
1824 InstructionMark im(this); | |
1825 prefix(src, dst); | |
1826 emit_byte(0x0F); | |
1827 emit_byte(0xB7); | |
1828 emit_operand(dst, src); | |
1829 } | |
1830 | |
1831 void Assembler::movzwl(Register dst, Register src) { // movzxw | |
1832 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1833 emit_byte(0x0F); | |
1834 emit_byte(0xB7); | |
1835 emit_byte(0xC0 | encode); | |
1836 } | |
1837 | |
1838 void Assembler::mull(Address src) { | |
1839 InstructionMark im(this); | |
1840 prefix(src); | |
1841 emit_byte(0xF7); | |
1842 emit_operand(rsp, src); | |
1843 } | |
1844 | |
1845 void Assembler::mull(Register src) { | |
1846 int encode = prefix_and_encode(src->encoding()); | |
1847 emit_byte(0xF7); | |
1848 emit_byte(0xE0 | encode); | |
1849 } | |
1850 | |
1851 void Assembler::mulsd(XMMRegister dst, Address src) { | |
1852 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1853 InstructionMark im(this); | |
1854 emit_byte(0xF2); | |
1855 prefix(src, dst); | |
1856 emit_byte(0x0F); | |
1857 emit_byte(0x59); | |
1858 emit_operand(dst, src); | |
1859 } | |
1860 | |
1861 void Assembler::mulsd(XMMRegister dst, XMMRegister src) { | |
1862 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1863 emit_byte(0xF2); | |
1864 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1865 emit_byte(0x0F); | |
1866 emit_byte(0x59); | |
1867 emit_byte(0xC0 | encode); | |
1868 } | |
1869 | |
1870 void Assembler::mulss(XMMRegister dst, Address src) { | |
1871 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
1872 InstructionMark im(this); | |
1873 emit_byte(0xF3); | |
1874 prefix(src, dst); | |
1875 emit_byte(0x0F); | |
1876 emit_byte(0x59); | |
1877 emit_operand(dst, src); | |
1878 } | |
1879 | |
1880 void Assembler::mulss(XMMRegister dst, XMMRegister src) { | |
1881 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
1882 emit_byte(0xF3); | |
1883 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1884 emit_byte(0x0F); | |
1885 emit_byte(0x59); | |
1886 emit_byte(0xC0 | encode); | |
1887 } | |
1888 | |
1889 void Assembler::negl(Register dst) { | |
1890 int encode = prefix_and_encode(dst->encoding()); | |
1891 emit_byte(0xF7); | |
1892 emit_byte(0xD8 | encode); | |
1893 } | |
1894 | |
0 | 1895 void Assembler::nop(int i) { |
304 | 1896 #ifdef ASSERT |
0 | 1897 assert(i > 0, " "); |
304 | 1898 // The fancy nops aren't currently recognized by debuggers making it a |
1899 // pain to disassemble code while debugging. If asserts are on clearly | |
1900 // speed is not an issue so simply use the single byte traditional nop | |
1901 // to do alignment. | |
1902 | |
1903 for (; i > 0 ; i--) emit_byte(0x90); | |
1904 return; | |
1905 | |
1906 #endif // ASSERT | |
1907 | |
0 | 1908 if (UseAddressNop && VM_Version::is_intel()) { |
1909 // | |
1910 // Using multi-bytes nops "0x0F 0x1F [address]" for Intel | |
1911 // 1: 0x90 | |
1912 // 2: 0x66 0x90 | |
1913 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding) | |
1914 // 4: 0x0F 0x1F 0x40 0x00 | |
1915 // 5: 0x0F 0x1F 0x44 0x00 0x00 | |
1916 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00 | |
1917 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 | |
1918 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
1919 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
1920 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
1921 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
1922 | |
1923 // The rest coding is Intel specific - don't use consecutive address nops | |
1924 | |
1925 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 | |
1926 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 | |
1927 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 | |
1928 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 | |
1929 | |
1930 while(i >= 15) { | |
1931 // For Intel don't generate consecutive addess nops (mix with regular nops) | |
1932 i -= 15; | |
1933 emit_byte(0x66); // size prefix | |
1934 emit_byte(0x66); // size prefix | |
1935 emit_byte(0x66); // size prefix | |
1936 addr_nop_8(); | |
1937 emit_byte(0x66); // size prefix | |
1938 emit_byte(0x66); // size prefix | |
1939 emit_byte(0x66); // size prefix | |
1940 emit_byte(0x90); // nop | |
1941 } | |
1942 switch (i) { | |
1943 case 14: | |
1944 emit_byte(0x66); // size prefix | |
1945 case 13: | |
1946 emit_byte(0x66); // size prefix | |
1947 case 12: | |
1948 addr_nop_8(); | |
1949 emit_byte(0x66); // size prefix | |
1950 emit_byte(0x66); // size prefix | |
1951 emit_byte(0x66); // size prefix | |
1952 emit_byte(0x90); // nop | |
1953 break; | |
1954 case 11: | |
1955 emit_byte(0x66); // size prefix | |
1956 case 10: | |
1957 emit_byte(0x66); // size prefix | |
1958 case 9: | |
1959 emit_byte(0x66); // size prefix | |
1960 case 8: | |
1961 addr_nop_8(); | |
1962 break; | |
1963 case 7: | |
1964 addr_nop_7(); | |
1965 break; | |
1966 case 6: | |
1967 emit_byte(0x66); // size prefix | |
1968 case 5: | |
1969 addr_nop_5(); | |
1970 break; | |
1971 case 4: | |
1972 addr_nop_4(); | |
1973 break; | |
1974 case 3: | |
1975 // Don't use "0x0F 0x1F 0x00" - need patching safe padding | |
1976 emit_byte(0x66); // size prefix | |
1977 case 2: | |
1978 emit_byte(0x66); // size prefix | |
1979 case 1: | |
1980 emit_byte(0x90); // nop | |
1981 break; | |
1982 default: | |
1983 assert(i == 0, " "); | |
1984 } | |
1985 return; | |
1986 } | |
1987 if (UseAddressNop && VM_Version::is_amd()) { | |
1988 // | |
1989 // Using multi-bytes nops "0x0F 0x1F [address]" for AMD. | |
1990 // 1: 0x90 | |
1991 // 2: 0x66 0x90 | |
1992 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding) | |
1993 // 4: 0x0F 0x1F 0x40 0x00 | |
1994 // 5: 0x0F 0x1F 0x44 0x00 0x00 | |
1995 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00 | |
1996 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 | |
1997 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
1998 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
1999 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
2000 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
2001 | |
2002 // The rest coding is AMD specific - use consecutive address nops | |
2003 | |
2004 // 12: 0x66 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00 | |
2005 // 13: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00 | |
2006 // 14: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 | |
2007 // 15: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 | |
2008 // 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
2009 // Size prefixes (0x66) are added for larger sizes | |
2010 | |
2011 while(i >= 22) { | |
2012 i -= 11; | |
2013 emit_byte(0x66); // size prefix | |
2014 emit_byte(0x66); // size prefix | |
2015 emit_byte(0x66); // size prefix | |
2016 addr_nop_8(); | |
2017 } | |
2018 // Generate first nop for size between 21-12 | |
2019 switch (i) { | |
2020 case 21: | |
2021 i -= 1; | |
2022 emit_byte(0x66); // size prefix | |
2023 case 20: | |
2024 case 19: | |
2025 i -= 1; | |
2026 emit_byte(0x66); // size prefix | |
2027 case 18: | |
2028 case 17: | |
2029 i -= 1; | |
2030 emit_byte(0x66); // size prefix | |
2031 case 16: | |
2032 case 15: | |
2033 i -= 8; | |
2034 addr_nop_8(); | |
2035 break; | |
2036 case 14: | |
2037 case 13: | |
2038 i -= 7; | |
2039 addr_nop_7(); | |
2040 break; | |
2041 case 12: | |
2042 i -= 6; | |
2043 emit_byte(0x66); // size prefix | |
2044 addr_nop_5(); | |
2045 break; | |
2046 default: | |
2047 assert(i < 12, " "); | |
2048 } | |
2049 | |
2050 // Generate second nop for size between 11-1 | |
2051 switch (i) { | |
2052 case 11: | |
2053 emit_byte(0x66); // size prefix | |
2054 case 10: | |
2055 emit_byte(0x66); // size prefix | |
2056 case 9: | |
2057 emit_byte(0x66); // size prefix | |
2058 case 8: | |
2059 addr_nop_8(); | |
2060 break; | |
2061 case 7: | |
2062 addr_nop_7(); | |
2063 break; | |
2064 case 6: | |
2065 emit_byte(0x66); // size prefix | |
2066 case 5: | |
2067 addr_nop_5(); | |
2068 break; | |
2069 case 4: | |
2070 addr_nop_4(); | |
2071 break; | |
2072 case 3: | |
2073 // Don't use "0x0F 0x1F 0x00" - need patching safe padding | |
2074 emit_byte(0x66); // size prefix | |
2075 case 2: | |
2076 emit_byte(0x66); // size prefix | |
2077 case 1: | |
2078 emit_byte(0x90); // nop | |
2079 break; | |
2080 default: | |
2081 assert(i == 0, " "); | |
2082 } | |
2083 return; | |
2084 } | |
2085 | |
2086 // Using nops with size prefixes "0x66 0x90". | |
2087 // From AMD Optimization Guide: | |
2088 // 1: 0x90 | |
2089 // 2: 0x66 0x90 | |
2090 // 3: 0x66 0x66 0x90 | |
2091 // 4: 0x66 0x66 0x66 0x90 | |
2092 // 5: 0x66 0x66 0x90 0x66 0x90 | |
2093 // 6: 0x66 0x66 0x90 0x66 0x66 0x90 | |
2094 // 7: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 | |
2095 // 8: 0x66 0x66 0x66 0x90 0x66 0x66 0x66 0x90 | |
2096 // 9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90 | |
2097 // 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90 | |
2098 // | |
2099 while(i > 12) { | |
2100 i -= 4; | |
2101 emit_byte(0x66); // size prefix | |
2102 emit_byte(0x66); | |
2103 emit_byte(0x66); | |
2104 emit_byte(0x90); // nop | |
2105 } | |
2106 // 1 - 12 nops | |
2107 if(i > 8) { | |
2108 if(i > 9) { | |
2109 i -= 1; | |
2110 emit_byte(0x66); | |
2111 } | |
2112 i -= 3; | |
2113 emit_byte(0x66); | |
2114 emit_byte(0x66); | |
2115 emit_byte(0x90); | |
2116 } | |
2117 // 1 - 8 nops | |
2118 if(i > 4) { | |
2119 if(i > 6) { | |
2120 i -= 1; | |
2121 emit_byte(0x66); | |
2122 } | |
2123 i -= 3; | |
2124 emit_byte(0x66); | |
2125 emit_byte(0x66); | |
2126 emit_byte(0x90); | |
2127 } | |
2128 switch (i) { | |
2129 case 4: | |
2130 emit_byte(0x66); | |
2131 case 3: | |
2132 emit_byte(0x66); | |
2133 case 2: | |
2134 emit_byte(0x66); | |
2135 case 1: | |
2136 emit_byte(0x90); | |
2137 break; | |
2138 default: | |
2139 assert(i == 0, " "); | |
2140 } | |
2141 } | |
2142 | |
304 | 2143 void Assembler::notl(Register dst) { |
2144 int encode = prefix_and_encode(dst->encoding()); | |
2145 emit_byte(0xF7); | |
2146 emit_byte(0xD0 | encode ); | |
2147 } | |
2148 | |
2149 void Assembler::orl(Address dst, int32_t imm32) { | |
2150 InstructionMark im(this); | |
2151 prefix(dst); | |
2152 emit_byte(0x81); | |
2153 emit_operand(rcx, dst, 4); | |
2154 emit_long(imm32); | |
2155 } | |
2156 | |
2157 void Assembler::orl(Register dst, int32_t imm32) { | |
2158 prefix(dst); | |
2159 emit_arith(0x81, 0xC8, dst, imm32); | |
2160 } | |
2161 | |
2162 | |
2163 void Assembler::orl(Register dst, Address src) { | |
2164 InstructionMark im(this); | |
2165 prefix(src, dst); | |
2166 emit_byte(0x0B); | |
2167 emit_operand(dst, src); | |
2168 } | |
2169 | |
2170 | |
2171 void Assembler::orl(Register dst, Register src) { | |
2172 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
2173 emit_arith(0x0B, 0xC0, dst, src); | |
2174 } | |
2175 | |
2176 // generic | |
2177 void Assembler::pop(Register dst) { | |
2178 int encode = prefix_and_encode(dst->encoding()); | |
2179 emit_byte(0x58 | encode); | |
2180 } | |
2181 | |
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
2182 void Assembler::popcntl(Register dst, Address src) { |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
2183 assert(VM_Version::supports_popcnt(), "must support"); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
2184 InstructionMark im(this); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
2185 emit_byte(0xF3); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
2186 prefix(src, dst); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
2187 emit_byte(0x0F); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
2188 emit_byte(0xB8); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
2189 emit_operand(dst, src); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
2190 } |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
2191 |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
2192 void Assembler::popcntl(Register dst, Register src) { |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
2193 assert(VM_Version::supports_popcnt(), "must support"); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
2194 emit_byte(0xF3); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
2195 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
2196 emit_byte(0x0F); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
2197 emit_byte(0xB8); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
2198 emit_byte(0xC0 | encode); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
2199 } |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
2200 |
304 | 2201 void Assembler::popf() { |
2202 emit_byte(0x9D); | |
2203 } | |
2204 | |
2205 void Assembler::popl(Address dst) { | |
2206 // NOTE: this will adjust stack by 8byte on 64bits | |
2207 InstructionMark im(this); | |
2208 prefix(dst); | |
2209 emit_byte(0x8F); | |
2210 emit_operand(rax, dst); | |
2211 } | |
2212 | |
2213 void Assembler::prefetch_prefix(Address src) { | |
2214 prefix(src); | |
2215 emit_byte(0x0F); | |
2216 } | |
2217 | |
2218 void Assembler::prefetchnta(Address src) { | |
2219 NOT_LP64(assert(VM_Version::supports_sse2(), "must support")); | |
2220 InstructionMark im(this); | |
2221 prefetch_prefix(src); | |
2222 emit_byte(0x18); | |
2223 emit_operand(rax, src); // 0, src | |
2224 } | |
2225 | |
2226 void Assembler::prefetchr(Address src) { | |
2227 NOT_LP64(assert(VM_Version::supports_3dnow(), "must support")); | |
2228 InstructionMark im(this); | |
2229 prefetch_prefix(src); | |
2230 emit_byte(0x0D); | |
2231 emit_operand(rax, src); // 0, src | |
2232 } | |
2233 | |
2234 void Assembler::prefetcht0(Address src) { | |
2235 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); | |
2236 InstructionMark im(this); | |
2237 prefetch_prefix(src); | |
2238 emit_byte(0x18); | |
2239 emit_operand(rcx, src); // 1, src | |
2240 } | |
2241 | |
2242 void Assembler::prefetcht1(Address src) { | |
2243 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); | |
2244 InstructionMark im(this); | |
2245 prefetch_prefix(src); | |
2246 emit_byte(0x18); | |
2247 emit_operand(rdx, src); // 2, src | |
2248 } | |
2249 | |
2250 void Assembler::prefetcht2(Address src) { | |
2251 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); | |
2252 InstructionMark im(this); | |
2253 prefetch_prefix(src); | |
2254 emit_byte(0x18); | |
2255 emit_operand(rbx, src); // 3, src | |
2256 } | |
2257 | |
2258 void Assembler::prefetchw(Address src) { | |
2259 NOT_LP64(assert(VM_Version::supports_3dnow(), "must support")); | |
2260 InstructionMark im(this); | |
2261 prefetch_prefix(src); | |
2262 emit_byte(0x0D); | |
2263 emit_operand(rcx, src); // 1, src | |
2264 } | |
2265 | |
2266 void Assembler::prefix(Prefix p) { | |
2267 a_byte(p); | |
2268 } | |
2269 | |
2270 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) { | |
2271 assert(isByte(mode), "invalid value"); | |
2272 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
2273 | |
2274 emit_byte(0x66); | |
2275 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
2276 emit_byte(0x0F); | |
2277 emit_byte(0x70); | |
2278 emit_byte(0xC0 | encode); | |
2279 emit_byte(mode & 0xFF); | |
2280 | |
2281 } | |
2282 | |
2283 void Assembler::pshufd(XMMRegister dst, Address src, int mode) { | |
2284 assert(isByte(mode), "invalid value"); | |
2285 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
2286 | |
2287 InstructionMark im(this); | |
2288 emit_byte(0x66); | |
2289 prefix(src, dst); | |
2290 emit_byte(0x0F); | |
2291 emit_byte(0x70); | |
2292 emit_operand(dst, src); | |
2293 emit_byte(mode & 0xFF); | |
2294 } | |
2295 | |
2296 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) { | |
2297 assert(isByte(mode), "invalid value"); | |
2298 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
2299 | |
2300 emit_byte(0xF2); | |
2301 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
2302 emit_byte(0x0F); | |
2303 emit_byte(0x70); | |
2304 emit_byte(0xC0 | encode); | |
2305 emit_byte(mode & 0xFF); | |
2306 } | |
2307 | |
2308 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) { | |
2309 assert(isByte(mode), "invalid value"); | |
2310 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
2311 | |
2312 InstructionMark im(this); | |
2313 emit_byte(0xF2); | |
2314 prefix(src, dst); // QQ new | |
2315 emit_byte(0x0F); | |
2316 emit_byte(0x70); | |
2317 emit_operand(dst, src); | |
2318 emit_byte(mode & 0xFF); | |
2319 } | |
2320 | |
2321 void Assembler::psrlq(XMMRegister dst, int shift) { | |
2322 // HMM Table D-1 says sse2 or mmx | |
2323 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
2324 | |
2325 int encode = prefixq_and_encode(xmm2->encoding(), dst->encoding()); | |
2326 emit_byte(0x66); | |
2327 emit_byte(0x0F); | |
2328 emit_byte(0x73); | |
2329 emit_byte(0xC0 | encode); | |
2330 emit_byte(shift); | |
2331 } | |
2332 | |
2333 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) { | |
2334 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
2335 emit_byte(0x66); | |
2336 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
2337 emit_byte(0x0F); | |
2338 emit_byte(0x60); | |
2339 emit_byte(0xC0 | encode); | |
2340 } | |
2341 | |
2342 void Assembler::push(int32_t imm32) { | |
2343 // in 64bits we push 64bits onto the stack but only | |
2344 // take a 32bit immediate | |
2345 emit_byte(0x68); | |
2346 emit_long(imm32); | |
2347 } | |
2348 | |
2349 void Assembler::push(Register src) { | |
2350 int encode = prefix_and_encode(src->encoding()); | |
2351 | |
2352 emit_byte(0x50 | encode); | |
2353 } | |
2354 | |
2355 void Assembler::pushf() { | |
2356 emit_byte(0x9C); | |
2357 } | |
2358 | |
2359 void Assembler::pushl(Address src) { | |
2360 // Note this will push 64bit on 64bit | |
2361 InstructionMark im(this); | |
2362 prefix(src); | |
2363 emit_byte(0xFF); | |
2364 emit_operand(rsi, src); | |
2365 } | |
2366 | |
2367 void Assembler::pxor(XMMRegister dst, Address src) { | |
2368 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
2369 InstructionMark im(this); | |
2370 emit_byte(0x66); | |
2371 prefix(src, dst); | |
2372 emit_byte(0x0F); | |
2373 emit_byte(0xEF); | |
2374 emit_operand(dst, src); | |
2375 } | |
2376 | |
2377 void Assembler::pxor(XMMRegister dst, XMMRegister src) { | |
2378 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
2379 InstructionMark im(this); | |
2380 emit_byte(0x66); | |
2381 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
2382 emit_byte(0x0F); | |
2383 emit_byte(0xEF); | |
2384 emit_byte(0xC0 | encode); | |
2385 } | |
2386 | |
2387 void Assembler::rcll(Register dst, int imm8) { | |
2388 assert(isShiftCount(imm8), "illegal shift count"); | |
2389 int encode = prefix_and_encode(dst->encoding()); | |
2390 if (imm8 == 1) { | |
2391 emit_byte(0xD1); | |
2392 emit_byte(0xD0 | encode); | |
2393 } else { | |
2394 emit_byte(0xC1); | |
2395 emit_byte(0xD0 | encode); | |
2396 emit_byte(imm8); | |
2397 } | |
2398 } | |
2399 | |
2400 // copies data from [esi] to [edi] using rcx pointer sized words | |
2401 // generic | |
2402 void Assembler::rep_mov() { | |
2403 emit_byte(0xF3); | |
2404 // MOVSQ | |
2405 LP64_ONLY(prefix(REX_W)); | |
2406 emit_byte(0xA5); | |
2407 } | |
2408 | |
2409 // sets rcx pointer sized words with rax, value at [edi] | |
2410 // generic | |
2411 void Assembler::rep_set() { // rep_set | |
2412 emit_byte(0xF3); | |
2413 // STOSQ | |
2414 LP64_ONLY(prefix(REX_W)); | |
2415 emit_byte(0xAB); | |
2416 } | |
2417 | |
2418 // scans rcx pointer sized words at [edi] for occurance of rax, | |
2419 // generic | |
2420 void Assembler::repne_scan() { // repne_scan | |
2421 emit_byte(0xF2); | |
2422 // SCASQ | |
2423 LP64_ONLY(prefix(REX_W)); | |
2424 emit_byte(0xAF); | |
2425 } | |
2426 | |
2427 #ifdef _LP64 | |
2428 // scans rcx 4 byte words at [edi] for occurance of rax, | |
2429 // generic | |
2430 void Assembler::repne_scanl() { // repne_scan | |
2431 emit_byte(0xF2); | |
2432 // SCASL | |
2433 emit_byte(0xAF); | |
2434 } | |
2435 #endif | |
2436 | |
0 | 2437 void Assembler::ret(int imm16) { |
2438 if (imm16 == 0) { | |
2439 emit_byte(0xC3); | |
2440 } else { | |
2441 emit_byte(0xC2); | |
2442 emit_word(imm16); | |
2443 } | |
2444 } | |
2445 | |
304 | 2446 void Assembler::sahf() { |
2447 #ifdef _LP64 | |
2448 // Not supported in 64bit mode | |
2449 ShouldNotReachHere(); | |
2450 #endif | |
2451 emit_byte(0x9E); | |
2452 } | |
2453 | |
2454 void Assembler::sarl(Register dst, int imm8) { | |
2455 int encode = prefix_and_encode(dst->encoding()); | |
2456 assert(isShiftCount(imm8), "illegal shift count"); | |
2457 if (imm8 == 1) { | |
2458 emit_byte(0xD1); | |
2459 emit_byte(0xF8 | encode); | |
2460 } else { | |
2461 emit_byte(0xC1); | |
2462 emit_byte(0xF8 | encode); | |
2463 emit_byte(imm8); | |
2464 } | |
2465 } | |
2466 | |
2467 void Assembler::sarl(Register dst) { | |
2468 int encode = prefix_and_encode(dst->encoding()); | |
2469 emit_byte(0xD3); | |
2470 emit_byte(0xF8 | encode); | |
2471 } | |
2472 | |
2473 void Assembler::sbbl(Address dst, int32_t imm32) { | |
2474 InstructionMark im(this); | |
2475 prefix(dst); | |
2476 emit_arith_operand(0x81, rbx, dst, imm32); | |
2477 } | |
2478 | |
2479 void Assembler::sbbl(Register dst, int32_t imm32) { | |
2480 prefix(dst); | |
2481 emit_arith(0x81, 0xD8, dst, imm32); | |
2482 } | |
2483 | |
2484 | |
2485 void Assembler::sbbl(Register dst, Address src) { | |
2486 InstructionMark im(this); | |
2487 prefix(src, dst); | |
2488 emit_byte(0x1B); | |
2489 emit_operand(dst, src); | |
2490 } | |
2491 | |
2492 void Assembler::sbbl(Register dst, Register src) { | |
2493 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
2494 emit_arith(0x1B, 0xC0, dst, src); | |
2495 } | |
2496 | |
2497 void Assembler::setb(Condition cc, Register dst) { | |
2498 assert(0 <= cc && cc < 16, "illegal cc"); | |
2499 int encode = prefix_and_encode(dst->encoding(), true); | |
0 | 2500 emit_byte(0x0F); |
304 | 2501 emit_byte(0x90 | cc); |
2502 emit_byte(0xC0 | encode); | |
2503 } | |
2504 | |
2505 void Assembler::shll(Register dst, int imm8) { | |
2506 assert(isShiftCount(imm8), "illegal shift count"); | |
2507 int encode = prefix_and_encode(dst->encoding()); | |
2508 if (imm8 == 1 ) { | |
2509 emit_byte(0xD1); | |
2510 emit_byte(0xE0 | encode); | |
2511 } else { | |
2512 emit_byte(0xC1); | |
2513 emit_byte(0xE0 | encode); | |
2514 emit_byte(imm8); | |
2515 } | |
2516 } | |
2517 | |
2518 void Assembler::shll(Register dst) { | |
2519 int encode = prefix_and_encode(dst->encoding()); | |
2520 emit_byte(0xD3); | |
2521 emit_byte(0xE0 | encode); | |
2522 } | |
2523 | |
2524 void Assembler::shrl(Register dst, int imm8) { | |
2525 assert(isShiftCount(imm8), "illegal shift count"); | |
2526 int encode = prefix_and_encode(dst->encoding()); | |
2527 emit_byte(0xC1); | |
2528 emit_byte(0xE8 | encode); | |
2529 emit_byte(imm8); | |
2530 } | |
2531 | |
2532 void Assembler::shrl(Register dst) { | |
2533 int encode = prefix_and_encode(dst->encoding()); | |
2534 emit_byte(0xD3); | |
2535 emit_byte(0xE8 | encode); | |
2536 } | |
0 | 2537 |
2538 // copies a single word from [esi] to [edi] | |
2539 void Assembler::smovl() { | |
2540 emit_byte(0xA5); | |
2541 } | |
2542 | |
304 | 2543 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) { |
2544 // HMM Table D-1 says sse2 | |
2545 // NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
2546 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
2547 emit_byte(0xF2); | |
2548 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
2549 emit_byte(0x0F); | |
2550 emit_byte(0x51); | |
2551 emit_byte(0xC0 | encode); | |
2552 } | |
2553 | |
2554 void Assembler::stmxcsr( Address dst) { | |
2555 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
2556 InstructionMark im(this); | |
2557 prefix(dst); | |
2558 emit_byte(0x0F); | |
2559 emit_byte(0xAE); | |
2560 emit_operand(as_Register(3), dst); | |
2561 } | |
2562 | |
2563 void Assembler::subl(Address dst, int32_t imm32) { | |
2564 InstructionMark im(this); | |
2565 prefix(dst); | |
2566 if (is8bit(imm32)) { | |
2567 emit_byte(0x83); | |
2568 emit_operand(rbp, dst, 1); | |
2569 emit_byte(imm32 & 0xFF); | |
2570 } else { | |
2571 emit_byte(0x81); | |
2572 emit_operand(rbp, dst, 4); | |
2573 emit_long(imm32); | |
2574 } | |
2575 } | |
2576 | |
2577 void Assembler::subl(Register dst, int32_t imm32) { | |
2578 prefix(dst); | |
2579 emit_arith(0x81, 0xE8, dst, imm32); | |
2580 } | |
2581 | |
2582 void Assembler::subl(Address dst, Register src) { | |
2583 InstructionMark im(this); | |
2584 prefix(dst, src); | |
2585 emit_byte(0x29); | |
2586 emit_operand(src, dst); | |
2587 } | |
2588 | |
2589 void Assembler::subl(Register dst, Address src) { | |
2590 InstructionMark im(this); | |
2591 prefix(src, dst); | |
2592 emit_byte(0x2B); | |
2593 emit_operand(dst, src); | |
2594 } | |
2595 | |
2596 void Assembler::subl(Register dst, Register src) { | |
2597 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
2598 emit_arith(0x2B, 0xC0, dst, src); | |
2599 } | |
2600 | |
2601 void Assembler::subsd(XMMRegister dst, XMMRegister src) { | |
2602 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
2603 emit_byte(0xF2); | |
2604 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
2605 emit_byte(0x0F); | |
2606 emit_byte(0x5C); | |
2607 emit_byte(0xC0 | encode); | |
2608 } | |
2609 | |
2610 void Assembler::subsd(XMMRegister dst, Address src) { | |
2611 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
2612 InstructionMark im(this); | |
2613 emit_byte(0xF2); | |
2614 prefix(src, dst); | |
2615 emit_byte(0x0F); | |
2616 emit_byte(0x5C); | |
2617 emit_operand(dst, src); | |
2618 } | |
2619 | |
2620 void Assembler::subss(XMMRegister dst, XMMRegister src) { | |
2621 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
0 | 2622 emit_byte(0xF3); |
304 | 2623 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
2624 emit_byte(0x0F); | |
2625 emit_byte(0x5C); | |
2626 emit_byte(0xC0 | encode); | |
2627 } | |
2628 | |
2629 void Assembler::subss(XMMRegister dst, Address src) { | |
2630 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
2631 InstructionMark im(this); | |
2632 emit_byte(0xF3); | |
2633 prefix(src, dst); | |
2634 emit_byte(0x0F); | |
2635 emit_byte(0x5C); | |
2636 emit_operand(dst, src); | |
2637 } | |
2638 | |
2639 void Assembler::testb(Register dst, int imm8) { | |
2640 NOT_LP64(assert(dst->has_byte_register(), "must have byte register")); | |
2641 (void) prefix_and_encode(dst->encoding(), true); | |
2642 emit_arith_b(0xF6, 0xC0, dst, imm8); | |
2643 } | |
2644 | |
2645 void Assembler::testl(Register dst, int32_t imm32) { | |
2646 // not using emit_arith because test | |
2647 // doesn't support sign-extension of | |
2648 // 8bit operands | |
2649 int encode = dst->encoding(); | |
2650 if (encode == 0) { | |
2651 emit_byte(0xA9); | |
2652 } else { | |
2653 encode = prefix_and_encode(encode); | |
2654 emit_byte(0xF7); | |
2655 emit_byte(0xC0 | encode); | |
2656 } | |
2657 emit_long(imm32); | |
2658 } | |
2659 | |
2660 void Assembler::testl(Register dst, Register src) { | |
2661 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
2662 emit_arith(0x85, 0xC0, dst, src); | |
2663 } | |
2664 | |
2665 void Assembler::testl(Register dst, Address src) { | |
2666 InstructionMark im(this); | |
2667 prefix(src, dst); | |
2668 emit_byte(0x85); | |
2669 emit_operand(dst, src); | |
2670 } | |
2671 | |
2672 void Assembler::ucomisd(XMMRegister dst, Address src) { | |
2673 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
2674 emit_byte(0x66); | |
2675 ucomiss(dst, src); | |
2676 } | |
2677 | |
2678 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) { | |
2679 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
2680 emit_byte(0x66); | |
2681 ucomiss(dst, src); | |
2682 } | |
2683 | |
2684 void Assembler::ucomiss(XMMRegister dst, Address src) { | |
2685 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
2686 | |
2687 InstructionMark im(this); | |
2688 prefix(src, dst); | |
2689 emit_byte(0x0F); | |
2690 emit_byte(0x2E); | |
2691 emit_operand(dst, src); | |
2692 } | |
2693 | |
2694 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) { | |
2695 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
2696 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
2697 emit_byte(0x0F); | |
2698 emit_byte(0x2E); | |
2699 emit_byte(0xC0 | encode); | |
2700 } | |
2701 | |
2702 | |
2703 void Assembler::xaddl(Address dst, Register src) { | |
2704 InstructionMark im(this); | |
2705 prefix(dst, src); | |
0 | 2706 emit_byte(0x0F); |
304 | 2707 emit_byte(0xC1); |
2708 emit_operand(src, dst); | |
2709 } | |
2710 | |
2711 void Assembler::xchgl(Register dst, Address src) { // xchg | |
2712 InstructionMark im(this); | |
2713 prefix(src, dst); | |
2714 emit_byte(0x87); | |
2715 emit_operand(dst, src); | |
2716 } | |
2717 | |
2718 void Assembler::xchgl(Register dst, Register src) { | |
2719 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
2720 emit_byte(0x87); | |
2721 emit_byte(0xc0 | encode); | |
2722 } | |
2723 | |
2724 void Assembler::xorl(Register dst, int32_t imm32) { | |
2725 prefix(dst); | |
2726 emit_arith(0x81, 0xF0, dst, imm32); | |
2727 } | |
2728 | |
2729 void Assembler::xorl(Register dst, Address src) { | |
2730 InstructionMark im(this); | |
2731 prefix(src, dst); | |
2732 emit_byte(0x33); | |
2733 emit_operand(dst, src); | |
2734 } | |
2735 | |
2736 void Assembler::xorl(Register dst, Register src) { | |
2737 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
2738 emit_arith(0x33, 0xC0, dst, src); | |
2739 } | |
2740 | |
2741 void Assembler::xorpd(XMMRegister dst, XMMRegister src) { | |
2742 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
2743 emit_byte(0x66); | |
2744 xorps(dst, src); | |
2745 } | |
2746 | |
2747 void Assembler::xorpd(XMMRegister dst, Address src) { | |
2748 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
2749 InstructionMark im(this); | |
2750 emit_byte(0x66); | |
2751 prefix(src, dst); | |
2752 emit_byte(0x0F); | |
2753 emit_byte(0x57); | |
2754 emit_operand(dst, src); | |
2755 } | |
2756 | |
2757 | |
2758 void Assembler::xorps(XMMRegister dst, XMMRegister src) { | |
2759 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
2760 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
2761 emit_byte(0x0F); | |
2762 emit_byte(0x57); | |
2763 emit_byte(0xC0 | encode); | |
2764 } | |
2765 | |
2766 void Assembler::xorps(XMMRegister dst, Address src) { | |
2767 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
2768 InstructionMark im(this); | |
2769 prefix(src, dst); | |
2770 emit_byte(0x0F); | |
2771 emit_byte(0x57); | |
2772 emit_operand(dst, src); | |
2773 } | |
2774 | |
2775 #ifndef _LP64 | |
2776 // 32bit only pieces of the assembler | |
2777 | |
2778 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) { | |
2779 // NO PREFIX AS NEVER 64BIT | |
2780 InstructionMark im(this); | |
2781 emit_byte(0x81); | |
2782 emit_byte(0xF8 | src1->encoding()); | |
2783 emit_data(imm32, rspec, 0); | |
2784 } | |
2785 | |
2786 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) { | |
2787 // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs | |
2788 InstructionMark im(this); | |
2789 emit_byte(0x81); | |
2790 emit_operand(rdi, src1); | |
2791 emit_data(imm32, rspec, 0); | |
2792 } | |
2793 | |
2794 // The 64-bit (32bit platform) cmpxchg compares the value at adr with the contents of rdx:rax, | |
2795 // and stores rcx:rbx into adr if so; otherwise, the value at adr is loaded | |
2796 // into rdx:rax. The ZF is set if the compared values were equal, and cleared otherwise. | |
2797 void Assembler::cmpxchg8(Address adr) { | |
2798 InstructionMark im(this); | |
2799 emit_byte(0x0F); | |
2800 emit_byte(0xc7); | |
2801 emit_operand(rcx, adr); | |
2802 } | |
2803 | |
2804 void Assembler::decl(Register dst) { | |
2805 // Don't use it directly. Use MacroAssembler::decrementl() instead. | |
2806 emit_byte(0x48 | dst->encoding()); | |
2807 } | |
2808 | |
2809 #endif // _LP64 | |
2810 | |
2811 // 64bit typically doesn't use the x87 but needs to for the trig funcs | |
2812 | |
2813 void Assembler::fabs() { | |
2814 emit_byte(0xD9); | |
2815 emit_byte(0xE1); | |
2816 } | |
2817 | |
2818 void Assembler::fadd(int i) { | |
2819 emit_farith(0xD8, 0xC0, i); | |
2820 } | |
2821 | |
2822 void Assembler::fadd_d(Address src) { | |
2823 InstructionMark im(this); | |
2824 emit_byte(0xDC); | |
2825 emit_operand32(rax, src); | |
2826 } | |
2827 | |
2828 void Assembler::fadd_s(Address src) { | |
2829 InstructionMark im(this); | |
2830 emit_byte(0xD8); | |
2831 emit_operand32(rax, src); | |
2832 } | |
2833 | |
2834 void Assembler::fadda(int i) { | |
2835 emit_farith(0xDC, 0xC0, i); | |
2836 } | |
2837 | |
2838 void Assembler::faddp(int i) { | |
2839 emit_farith(0xDE, 0xC0, i); | |
2840 } | |
2841 | |
2842 void Assembler::fchs() { | |
2843 emit_byte(0xD9); | |
2844 emit_byte(0xE0); | |
2845 } | |
2846 | |
2847 void Assembler::fcom(int i) { | |
2848 emit_farith(0xD8, 0xD0, i); | |
2849 } | |
2850 | |
2851 void Assembler::fcomp(int i) { | |
2852 emit_farith(0xD8, 0xD8, i); | |
2853 } | |
2854 | |
2855 void Assembler::fcomp_d(Address src) { | |
2856 InstructionMark im(this); | |
2857 emit_byte(0xDC); | |
2858 emit_operand32(rbx, src); | |
2859 } | |
2860 | |
2861 void Assembler::fcomp_s(Address src) { | |
2862 InstructionMark im(this); | |
2863 emit_byte(0xD8); | |
2864 emit_operand32(rbx, src); | |
2865 } | |
2866 | |
2867 void Assembler::fcompp() { | |
2868 emit_byte(0xDE); | |
2869 emit_byte(0xD9); | |
2870 } | |
2871 | |
2872 void Assembler::fcos() { | |
2873 emit_byte(0xD9); | |
0 | 2874 emit_byte(0xFF); |
304 | 2875 } |
2876 | |
2877 void Assembler::fdecstp() { | |
2878 emit_byte(0xD9); | |
2879 emit_byte(0xF6); | |
2880 } | |
2881 | |
2882 void Assembler::fdiv(int i) { | |
2883 emit_farith(0xD8, 0xF0, i); | |
2884 } | |
2885 | |
2886 void Assembler::fdiv_d(Address src) { | |
2887 InstructionMark im(this); | |
2888 emit_byte(0xDC); | |
2889 emit_operand32(rsi, src); | |
2890 } | |
2891 | |
2892 void Assembler::fdiv_s(Address src) { | |
2893 InstructionMark im(this); | |
2894 emit_byte(0xD8); | |
2895 emit_operand32(rsi, src); | |
2896 } | |
2897 | |
2898 void Assembler::fdiva(int i) { | |
2899 emit_farith(0xDC, 0xF8, i); | |
2900 } | |
2901 | |
2902 // Note: The Intel manual (Pentium Processor User's Manual, Vol.3, 1994) | |
2903 // is erroneous for some of the floating-point instructions below. | |
2904 | |
2905 void Assembler::fdivp(int i) { | |
2906 emit_farith(0xDE, 0xF8, i); // ST(0) <- ST(0) / ST(1) and pop (Intel manual wrong) | |
2907 } | |
2908 | |
2909 void Assembler::fdivr(int i) { | |
2910 emit_farith(0xD8, 0xF8, i); | |
2911 } | |
2912 | |
2913 void Assembler::fdivr_d(Address src) { | |
2914 InstructionMark im(this); | |
2915 emit_byte(0xDC); | |
2916 emit_operand32(rdi, src); | |
2917 } | |
2918 | |
2919 void Assembler::fdivr_s(Address src) { | |
2920 InstructionMark im(this); | |
2921 emit_byte(0xD8); | |
2922 emit_operand32(rdi, src); | |
2923 } | |
2924 | |
2925 void Assembler::fdivra(int i) { | |
2926 emit_farith(0xDC, 0xF0, i); | |
2927 } | |
2928 | |
2929 void Assembler::fdivrp(int i) { | |
2930 emit_farith(0xDE, 0xF0, i); // ST(0) <- ST(1) / ST(0) and pop (Intel manual wrong) | |
2931 } | |
2932 | |
2933 void Assembler::ffree(int i) { | |
2934 emit_farith(0xDD, 0xC0, i); | |
2935 } | |
2936 | |
2937 void Assembler::fild_d(Address adr) { | |
2938 InstructionMark im(this); | |
2939 emit_byte(0xDF); | |
2940 emit_operand32(rbp, adr); | |
2941 } | |
2942 | |
2943 void Assembler::fild_s(Address adr) { | |
2944 InstructionMark im(this); | |
2945 emit_byte(0xDB); | |
2946 emit_operand32(rax, adr); | |
2947 } | |
2948 | |
2949 void Assembler::fincstp() { | |
2950 emit_byte(0xD9); | |
2951 emit_byte(0xF7); | |
2952 } | |
2953 | |
2954 void Assembler::finit() { | |
2955 emit_byte(0x9B); | |
2956 emit_byte(0xDB); | |
2957 emit_byte(0xE3); | |
2958 } | |
2959 | |
2960 void Assembler::fist_s(Address adr) { | |
2961 InstructionMark im(this); | |
2962 emit_byte(0xDB); | |
2963 emit_operand32(rdx, adr); | |
2964 } | |
2965 | |
2966 void Assembler::fistp_d(Address adr) { | |
2967 InstructionMark im(this); | |
2968 emit_byte(0xDF); | |
2969 emit_operand32(rdi, adr); | |
2970 } | |
2971 | |
2972 void Assembler::fistp_s(Address adr) { | |
2973 InstructionMark im(this); | |
2974 emit_byte(0xDB); | |
2975 emit_operand32(rbx, adr); | |
2976 } | |
0 | 2977 |
2978 void Assembler::fld1() { | |
2979 emit_byte(0xD9); | |
2980 emit_byte(0xE8); | |
2981 } | |
2982 | |
304 | 2983 void Assembler::fld_d(Address adr) { |
2984 InstructionMark im(this); | |
2985 emit_byte(0xDD); | |
2986 emit_operand32(rax, adr); | |
2987 } | |
0 | 2988 |
2989 void Assembler::fld_s(Address adr) { | |
2990 InstructionMark im(this); | |
2991 emit_byte(0xD9); | |
304 | 2992 emit_operand32(rax, adr); |
2993 } | |
2994 | |
2995 | |
2996 void Assembler::fld_s(int index) { | |
0 | 2997 emit_farith(0xD9, 0xC0, index); |
2998 } | |
2999 | |
3000 void Assembler::fld_x(Address adr) { | |
3001 InstructionMark im(this); | |
3002 emit_byte(0xDB); | |
304 | 3003 emit_operand32(rbp, adr); |
3004 } | |
3005 | |
3006 void Assembler::fldcw(Address src) { | |
3007 InstructionMark im(this); | |
3008 emit_byte(0xd9); | |
3009 emit_operand32(rbp, src); | |
3010 } | |
3011 | |
3012 void Assembler::fldenv(Address src) { | |
0 | 3013 InstructionMark im(this); |
3014 emit_byte(0xD9); | |
304 | 3015 emit_operand32(rsp, src); |
3016 } | |
3017 | |
3018 void Assembler::fldlg2() { | |
0 | 3019 emit_byte(0xD9); |
304 | 3020 emit_byte(0xEC); |
3021 } | |
0 | 3022 |
3023 void Assembler::fldln2() { | |
3024 emit_byte(0xD9); | |
3025 emit_byte(0xED); | |
3026 } | |
3027 | |
304 | 3028 void Assembler::fldz() { |
0 | 3029 emit_byte(0xD9); |
304 | 3030 emit_byte(0xEE); |
3031 } | |
0 | 3032 |
3033 void Assembler::flog() { | |
3034 fldln2(); | |
3035 fxch(); | |
3036 fyl2x(); | |
3037 } | |
3038 | |
3039 void Assembler::flog10() { | |
3040 fldlg2(); | |
3041 fxch(); | |
3042 fyl2x(); | |
3043 } | |
3044 | |
304 | 3045 void Assembler::fmul(int i) { |
3046 emit_farith(0xD8, 0xC8, i); | |
3047 } | |
3048 | |
3049 void Assembler::fmul_d(Address src) { | |
3050 InstructionMark im(this); | |
3051 emit_byte(0xDC); | |
3052 emit_operand32(rcx, src); | |
3053 } | |
3054 | |
3055 void Assembler::fmul_s(Address src) { | |
3056 InstructionMark im(this); | |
3057 emit_byte(0xD8); | |
3058 emit_operand32(rcx, src); | |
3059 } | |
3060 | |
3061 void Assembler::fmula(int i) { | |
3062 emit_farith(0xDC, 0xC8, i); | |
3063 } | |
3064 | |
3065 void Assembler::fmulp(int i) { | |
3066 emit_farith(0xDE, 0xC8, i); | |
3067 } | |
3068 | |
3069 void Assembler::fnsave(Address dst) { | |
3070 InstructionMark im(this); | |
3071 emit_byte(0xDD); | |
3072 emit_operand32(rsi, dst); | |
3073 } | |
3074 | |
3075 void Assembler::fnstcw(Address src) { | |
3076 InstructionMark im(this); | |
3077 emit_byte(0x9B); | |
3078 emit_byte(0xD9); | |
3079 emit_operand32(rdi, src); | |
3080 } | |
3081 | |
3082 void Assembler::fnstsw_ax() { | |
3083 emit_byte(0xdF); | |
3084 emit_byte(0xE0); | |
3085 } | |
3086 | |
3087 void Assembler::fprem() { | |
3088 emit_byte(0xD9); | |
3089 emit_byte(0xF8); | |
3090 } | |
3091 | |
3092 void Assembler::fprem1() { | |
3093 emit_byte(0xD9); | |
3094 emit_byte(0xF5); | |
3095 } | |
3096 | |
3097 void Assembler::frstor(Address src) { | |
3098 InstructionMark im(this); | |
3099 emit_byte(0xDD); | |
3100 emit_operand32(rsp, src); | |
3101 } | |
0 | 3102 |
3103 void Assembler::fsin() { | |
3104 emit_byte(0xD9); | |
3105 emit_byte(0xFE); | |
3106 } | |
3107 | |
304 | 3108 void Assembler::fsqrt() { |
3109 emit_byte(0xD9); | |
3110 emit_byte(0xFA); | |
3111 } | |
3112 | |
3113 void Assembler::fst_d(Address adr) { | |
3114 InstructionMark im(this); | |
3115 emit_byte(0xDD); | |
3116 emit_operand32(rdx, adr); | |
3117 } | |
3118 | |
3119 void Assembler::fst_s(Address adr) { | |
3120 InstructionMark im(this); | |
3121 emit_byte(0xD9); | |
3122 emit_operand32(rdx, adr); | |
3123 } | |
3124 | |
3125 void Assembler::fstp_d(Address adr) { | |
3126 InstructionMark im(this); | |
3127 emit_byte(0xDD); | |
3128 emit_operand32(rbx, adr); | |
3129 } | |
3130 | |
3131 void Assembler::fstp_d(int index) { | |
3132 emit_farith(0xDD, 0xD8, index); | |
3133 } | |
3134 | |
3135 void Assembler::fstp_s(Address adr) { | |
3136 InstructionMark im(this); | |
0 | 3137 emit_byte(0xD9); |
304 | 3138 emit_operand32(rbx, adr); |
3139 } | |
3140 | |
3141 void Assembler::fstp_x(Address adr) { | |
3142 InstructionMark im(this); | |
3143 emit_byte(0xDB); | |
3144 emit_operand32(rdi, adr); | |
3145 } | |
3146 | |
3147 void Assembler::fsub(int i) { | |
3148 emit_farith(0xD8, 0xE0, i); | |
3149 } | |
3150 | |
3151 void Assembler::fsub_d(Address src) { | |
3152 InstructionMark im(this); | |
3153 emit_byte(0xDC); | |
3154 emit_operand32(rsp, src); | |
3155 } | |
3156 | |
3157 void Assembler::fsub_s(Address src) { | |
3158 InstructionMark im(this); | |
3159 emit_byte(0xD8); | |
3160 emit_operand32(rsp, src); | |
3161 } | |
3162 | |
3163 void Assembler::fsuba(int i) { | |
3164 emit_farith(0xDC, 0xE8, i); | |
3165 } | |
3166 | |
3167 void Assembler::fsubp(int i) { | |
3168 emit_farith(0xDE, 0xE8, i); // ST(0) <- ST(0) - ST(1) and pop (Intel manual wrong) | |
3169 } | |
3170 | |
3171 void Assembler::fsubr(int i) { | |
3172 emit_farith(0xD8, 0xE8, i); | |
3173 } | |
3174 | |
3175 void Assembler::fsubr_d(Address src) { | |
3176 InstructionMark im(this); | |
3177 emit_byte(0xDC); | |
3178 emit_operand32(rbp, src); | |
3179 } | |
3180 | |
3181 void Assembler::fsubr_s(Address src) { | |
3182 InstructionMark im(this); | |
3183 emit_byte(0xD8); | |
3184 emit_operand32(rbp, src); | |
3185 } | |
3186 | |
3187 void Assembler::fsubra(int i) { | |
3188 emit_farith(0xDC, 0xE0, i); | |
3189 } | |
3190 | |
3191 void Assembler::fsubrp(int i) { | |
3192 emit_farith(0xDE, 0xE0, i); // ST(0) <- ST(1) - ST(0) and pop (Intel manual wrong) | |
0 | 3193 } |
3194 | |
3195 void Assembler::ftan() { | |
3196 emit_byte(0xD9); | |
3197 emit_byte(0xF2); | |
3198 emit_byte(0xDD); | |
3199 emit_byte(0xD8); | |
3200 } | |
3201 | |
304 | 3202 void Assembler::ftst() { |
0 | 3203 emit_byte(0xD9); |
304 | 3204 emit_byte(0xE4); |
3205 } | |
0 | 3206 |
3207 void Assembler::fucomi(int i) { | |
3208 // make sure the instruction is supported (introduced for P6, together with cmov) | |
3209 guarantee(VM_Version::supports_cmov(), "illegal instruction"); | |
3210 emit_farith(0xDB, 0xE8, i); | |
3211 } | |
3212 | |
3213 void Assembler::fucomip(int i) { | |
3214 // make sure the instruction is supported (introduced for P6, together with cmov) | |
3215 guarantee(VM_Version::supports_cmov(), "illegal instruction"); | |
3216 emit_farith(0xDF, 0xE8, i); | |
3217 } | |
3218 | |
3219 void Assembler::fwait() { | |
3220 emit_byte(0x9B); | |
3221 } | |
3222 | |
304 | 3223 void Assembler::fxch(int i) { |
3224 emit_farith(0xD9, 0xC8, i); | |
3225 } | |
3226 | |
3227 void Assembler::fyl2x() { | |
0 | 3228 emit_byte(0xD9); |
304 | 3229 emit_byte(0xF1); |
3230 } | |
3231 | |
3232 | |
3233 #ifndef _LP64 | |
3234 | |
3235 void Assembler::incl(Register dst) { | |
3236 // Don't use it directly. Use MacroAssembler::incrementl() instead. | |
3237 emit_byte(0x40 | dst->encoding()); | |
3238 } | |
3239 | |
3240 void Assembler::lea(Register dst, Address src) { | |
3241 leal(dst, src); | |
3242 } | |
3243 | |
3244 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) { | |
3245 InstructionMark im(this); | |
3246 emit_byte(0xC7); | |
3247 emit_operand(rax, dst); | |
3248 emit_data((int)imm32, rspec, 0); | |
3249 } | |
3250 | |
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3251 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) { |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3252 InstructionMark im(this); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3253 int encode = prefix_and_encode(dst->encoding()); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3254 emit_byte(0xB8 | encode); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3255 emit_data((int)imm32, rspec, 0); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3256 } |
304 | 3257 |
3258 void Assembler::popa() { // 32bit | |
3259 emit_byte(0x61); | |
3260 } | |
3261 | |
3262 void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) { | |
3263 InstructionMark im(this); | |
3264 emit_byte(0x68); | |
3265 emit_data(imm32, rspec, 0); | |
3266 } | |
3267 | |
3268 void Assembler::pusha() { // 32bit | |
3269 emit_byte(0x60); | |
3270 } | |
3271 | |
3272 void Assembler::set_byte_if_not_zero(Register dst) { | |
0 | 3273 emit_byte(0x0F); |
304 | 3274 emit_byte(0x95); |
3275 emit_byte(0xE0 | dst->encoding()); | |
3276 } | |
3277 | |
3278 void Assembler::shldl(Register dst, Register src) { | |
0 | 3279 emit_byte(0x0F); |
304 | 3280 emit_byte(0xA5); |
3281 emit_byte(0xC0 | src->encoding() << 3 | dst->encoding()); | |
3282 } | |
3283 | |
3284 void Assembler::shrdl(Register dst, Register src) { | |
0 | 3285 emit_byte(0x0F); |
304 | 3286 emit_byte(0xAD); |
3287 emit_byte(0xC0 | src->encoding() << 3 | dst->encoding()); | |
3288 } | |
3289 | |
3290 #else // LP64 | |
3291 | |
3292 // 64bit only pieces of the assembler | |
3293 // This should only be used by 64bit instructions that can use rip-relative | |
3294 // it cannot be used by instructions that want an immediate value. | |
3295 | |
3296 bool Assembler::reachable(AddressLiteral adr) { | |
3297 int64_t disp; | |
3298 // None will force a 64bit literal to the code stream. Likely a placeholder | |
3299 // for something that will be patched later and we need to certain it will | |
3300 // always be reachable. | |
3301 if (adr.reloc() == relocInfo::none) { | |
3302 return false; | |
3303 } | |
3304 if (adr.reloc() == relocInfo::internal_word_type) { | |
3305 // This should be rip relative and easily reachable. | |
3306 return true; | |
3307 } | |
3308 if (adr.reloc() == relocInfo::virtual_call_type || | |
3309 adr.reloc() == relocInfo::opt_virtual_call_type || | |
3310 adr.reloc() == relocInfo::static_call_type || | |
3311 adr.reloc() == relocInfo::static_stub_type ) { | |
3312 // This should be rip relative within the code cache and easily | |
3313 // reachable until we get huge code caches. (At which point | |
3314 // ic code is going to have issues). | |
3315 return true; | |
3316 } | |
3317 if (adr.reloc() != relocInfo::external_word_type && | |
3318 adr.reloc() != relocInfo::poll_return_type && // these are really external_word but need special | |
3319 adr.reloc() != relocInfo::poll_type && // relocs to identify them | |
3320 adr.reloc() != relocInfo::runtime_call_type ) { | |
3321 return false; | |
3322 } | |
3323 | |
3324 // Stress the correction code | |
3325 if (ForceUnreachable) { | |
3326 // Must be runtimecall reloc, see if it is in the codecache | |
3327 // Flipping stuff in the codecache to be unreachable causes issues | |
3328 // with things like inline caches where the additional instructions | |
3329 // are not handled. | |
3330 if (CodeCache::find_blob(adr._target) == NULL) { | |
3331 return false; | |
3332 } | |
3333 } | |
3334 // For external_word_type/runtime_call_type if it is reachable from where we | |
3335 // are now (possibly a temp buffer) and where we might end up | |
3336 // anywhere in the codeCache then we are always reachable. | |
3337 // This would have to change if we ever save/restore shared code | |
3338 // to be more pessimistic. | |
3339 | |
3340 disp = (int64_t)adr._target - ((int64_t)CodeCache::low_bound() + sizeof(int)); | |
3341 if (!is_simm32(disp)) return false; | |
3342 disp = (int64_t)adr._target - ((int64_t)CodeCache::high_bound() + sizeof(int)); | |
3343 if (!is_simm32(disp)) return false; | |
3344 | |
3345 disp = (int64_t)adr._target - ((int64_t)_code_pos + sizeof(int)); | |
3346 | |
3347 // Because rip relative is a disp + address_of_next_instruction and we | |
3348 // don't know the value of address_of_next_instruction we apply a fudge factor | |
3349 // to make sure we will be ok no matter the size of the instruction we get placed into. | |
3350 // We don't have to fudge the checks above here because they are already worst case. | |
3351 | |
3352 // 12 == override/rex byte, opcode byte, rm byte, sib byte, a 4-byte disp , 4-byte literal | |
3353 // + 4 because better safe than sorry. | |
3354 const int fudge = 12 + 4; | |
3355 if (disp < 0) { | |
3356 disp -= fudge; | |
3357 } else { | |
3358 disp += fudge; | |
3359 } | |
3360 return is_simm32(disp); | |
3361 } | |
3362 | |
3363 void Assembler::emit_data64(jlong data, | |
3364 relocInfo::relocType rtype, | |
3365 int format) { | |
3366 if (rtype == relocInfo::none) { | |
3367 emit_long64(data); | |
3368 } else { | |
3369 emit_data64(data, Relocation::spec_simple(rtype), format); | |
3370 } | |
3371 } | |
3372 | |
3373 void Assembler::emit_data64(jlong data, | |
3374 RelocationHolder const& rspec, | |
3375 int format) { | |
3376 assert(imm_operand == 0, "default format must be immediate in this file"); | |
3377 assert(imm_operand == format, "must be immediate"); | |
3378 assert(inst_mark() != NULL, "must be inside InstructionMark"); | |
3379 // Do not use AbstractAssembler::relocate, which is not intended for | |
3380 // embedded words. Instead, relocate to the enclosing instruction. | |
3381 code_section()->relocate(inst_mark(), rspec, format); | |
3382 #ifdef ASSERT | |
3383 check_relocation(rspec, format); | |
3384 #endif | |
3385 emit_long64(data); | |
3386 } | |
3387 | |
3388 int Assembler::prefix_and_encode(int reg_enc, bool byteinst) { | |
3389 if (reg_enc >= 8) { | |
3390 prefix(REX_B); | |
3391 reg_enc -= 8; | |
3392 } else if (byteinst && reg_enc >= 4) { | |
3393 prefix(REX); | |
3394 } | |
3395 return reg_enc; | |
3396 } | |
3397 | |
3398 int Assembler::prefixq_and_encode(int reg_enc) { | |
3399 if (reg_enc < 8) { | |
3400 prefix(REX_W); | |
3401 } else { | |
3402 prefix(REX_WB); | |
3403 reg_enc -= 8; | |
3404 } | |
3405 return reg_enc; | |
3406 } | |
3407 | |
3408 int Assembler::prefix_and_encode(int dst_enc, int src_enc, bool byteinst) { | |
3409 if (dst_enc < 8) { | |
3410 if (src_enc >= 8) { | |
3411 prefix(REX_B); | |
3412 src_enc -= 8; | |
3413 } else if (byteinst && src_enc >= 4) { | |
3414 prefix(REX); | |
3415 } | |
3416 } else { | |
3417 if (src_enc < 8) { | |
3418 prefix(REX_R); | |
3419 } else { | |
3420 prefix(REX_RB); | |
3421 src_enc -= 8; | |
3422 } | |
3423 dst_enc -= 8; | |
3424 } | |
3425 return dst_enc << 3 | src_enc; | |
3426 } | |
3427 | |
3428 int Assembler::prefixq_and_encode(int dst_enc, int src_enc) { | |
3429 if (dst_enc < 8) { | |
3430 if (src_enc < 8) { | |
3431 prefix(REX_W); | |
3432 } else { | |
3433 prefix(REX_WB); | |
3434 src_enc -= 8; | |
3435 } | |
3436 } else { | |
3437 if (src_enc < 8) { | |
3438 prefix(REX_WR); | |
3439 } else { | |
3440 prefix(REX_WRB); | |
3441 src_enc -= 8; | |
3442 } | |
3443 dst_enc -= 8; | |
3444 } | |
3445 return dst_enc << 3 | src_enc; | |
3446 } | |
3447 | |
3448 void Assembler::prefix(Register reg) { | |
3449 if (reg->encoding() >= 8) { | |
3450 prefix(REX_B); | |
3451 } | |
3452 } | |
3453 | |
3454 void Assembler::prefix(Address adr) { | |
3455 if (adr.base_needs_rex()) { | |
3456 if (adr.index_needs_rex()) { | |
3457 prefix(REX_XB); | |
3458 } else { | |
3459 prefix(REX_B); | |
3460 } | |
3461 } else { | |
3462 if (adr.index_needs_rex()) { | |
3463 prefix(REX_X); | |
3464 } | |
3465 } | |
3466 } | |
3467 | |
3468 void Assembler::prefixq(Address adr) { | |
3469 if (adr.base_needs_rex()) { | |
3470 if (adr.index_needs_rex()) { | |
3471 prefix(REX_WXB); | |
3472 } else { | |
3473 prefix(REX_WB); | |
3474 } | |
3475 } else { | |
3476 if (adr.index_needs_rex()) { | |
3477 prefix(REX_WX); | |
3478 } else { | |
3479 prefix(REX_W); | |
3480 } | |
3481 } | |
3482 } | |
3483 | |
3484 | |
3485 void Assembler::prefix(Address adr, Register reg, bool byteinst) { | |
3486 if (reg->encoding() < 8) { | |
3487 if (adr.base_needs_rex()) { | |
3488 if (adr.index_needs_rex()) { | |
3489 prefix(REX_XB); | |
3490 } else { | |
3491 prefix(REX_B); | |
3492 } | |
3493 } else { | |
3494 if (adr.index_needs_rex()) { | |
3495 prefix(REX_X); | |
3496 } else if (reg->encoding() >= 4 ) { | |
3497 prefix(REX); | |
3498 } | |
3499 } | |
3500 } else { | |
3501 if (adr.base_needs_rex()) { | |
3502 if (adr.index_needs_rex()) { | |
3503 prefix(REX_RXB); | |
3504 } else { | |
3505 prefix(REX_RB); | |
3506 } | |
3507 } else { | |
3508 if (adr.index_needs_rex()) { | |
3509 prefix(REX_RX); | |
3510 } else { | |
3511 prefix(REX_R); | |
3512 } | |
3513 } | |
3514 } | |
3515 } | |
3516 | |
3517 void Assembler::prefixq(Address adr, Register src) { | |
3518 if (src->encoding() < 8) { | |
3519 if (adr.base_needs_rex()) { | |
3520 if (adr.index_needs_rex()) { | |
3521 prefix(REX_WXB); | |
3522 } else { | |
3523 prefix(REX_WB); | |
3524 } | |
3525 } else { | |
3526 if (adr.index_needs_rex()) { | |
3527 prefix(REX_WX); | |
3528 } else { | |
3529 prefix(REX_W); | |
3530 } | |
3531 } | |
3532 } else { | |
3533 if (adr.base_needs_rex()) { | |
3534 if (adr.index_needs_rex()) { | |
3535 prefix(REX_WRXB); | |
3536 } else { | |
3537 prefix(REX_WRB); | |
3538 } | |
3539 } else { | |
3540 if (adr.index_needs_rex()) { | |
3541 prefix(REX_WRX); | |
3542 } else { | |
3543 prefix(REX_WR); | |
3544 } | |
3545 } | |
3546 } | |
3547 } | |
3548 | |
3549 void Assembler::prefix(Address adr, XMMRegister reg) { | |
3550 if (reg->encoding() < 8) { | |
3551 if (adr.base_needs_rex()) { | |
3552 if (adr.index_needs_rex()) { | |
3553 prefix(REX_XB); | |
3554 } else { | |
3555 prefix(REX_B); | |
3556 } | |
3557 } else { | |
3558 if (adr.index_needs_rex()) { | |
3559 prefix(REX_X); | |
3560 } | |
3561 } | |
3562 } else { | |
3563 if (adr.base_needs_rex()) { | |
3564 if (adr.index_needs_rex()) { | |
3565 prefix(REX_RXB); | |
3566 } else { | |
3567 prefix(REX_RB); | |
3568 } | |
3569 } else { | |
3570 if (adr.index_needs_rex()) { | |
3571 prefix(REX_RX); | |
3572 } else { | |
3573 prefix(REX_R); | |
3574 } | |
3575 } | |
3576 } | |
3577 } | |
3578 | |
3579 void Assembler::adcq(Register dst, int32_t imm32) { | |
3580 (void) prefixq_and_encode(dst->encoding()); | |
3581 emit_arith(0x81, 0xD0, dst, imm32); | |
3582 } | |
3583 | |
3584 void Assembler::adcq(Register dst, Address src) { | |
3585 InstructionMark im(this); | |
3586 prefixq(src, dst); | |
3587 emit_byte(0x13); | |
3588 emit_operand(dst, src); | |
3589 } | |
3590 | |
3591 void Assembler::adcq(Register dst, Register src) { | |
3592 (int) prefixq_and_encode(dst->encoding(), src->encoding()); | |
3593 emit_arith(0x13, 0xC0, dst, src); | |
3594 } | |
3595 | |
3596 void Assembler::addq(Address dst, int32_t imm32) { | |
3597 InstructionMark im(this); | |
3598 prefixq(dst); | |
3599 emit_arith_operand(0x81, rax, dst,imm32); | |
3600 } | |
3601 | |
3602 void Assembler::addq(Address dst, Register src) { | |
3603 InstructionMark im(this); | |
3604 prefixq(dst, src); | |
3605 emit_byte(0x01); | |
3606 emit_operand(src, dst); | |
3607 } | |
3608 | |
3609 void Assembler::addq(Register dst, int32_t imm32) { | |
3610 (void) prefixq_and_encode(dst->encoding()); | |
3611 emit_arith(0x81, 0xC0, dst, imm32); | |
3612 } | |
3613 | |
3614 void Assembler::addq(Register dst, Address src) { | |
3615 InstructionMark im(this); | |
3616 prefixq(src, dst); | |
3617 emit_byte(0x03); | |
3618 emit_operand(dst, src); | |
3619 } | |
3620 | |
3621 void Assembler::addq(Register dst, Register src) { | |
3622 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
3623 emit_arith(0x03, 0xC0, dst, src); | |
3624 } | |
3625 | |
3626 void Assembler::andq(Register dst, int32_t imm32) { | |
3627 (void) prefixq_and_encode(dst->encoding()); | |
3628 emit_arith(0x81, 0xE0, dst, imm32); | |
3629 } | |
3630 | |
3631 void Assembler::andq(Register dst, Address src) { | |
3632 InstructionMark im(this); | |
3633 prefixq(src, dst); | |
3634 emit_byte(0x23); | |
3635 emit_operand(dst, src); | |
3636 } | |
3637 | |
3638 void Assembler::andq(Register dst, Register src) { | |
3639 (int) prefixq_and_encode(dst->encoding(), src->encoding()); | |
3640 emit_arith(0x23, 0xC0, dst, src); | |
3641 } | |
3642 | |
3643 void Assembler::bswapq(Register reg) { | |
3644 int encode = prefixq_and_encode(reg->encoding()); | |
3645 emit_byte(0x0F); | |
3646 emit_byte(0xC8 | encode); | |
3647 } | |
3648 | |
3649 void Assembler::cdqq() { | |
3650 prefix(REX_W); | |
3651 emit_byte(0x99); | |
3652 } | |
3653 | |
3654 void Assembler::clflush(Address adr) { | |
3655 prefix(adr); | |
3656 emit_byte(0x0F); | |
3657 emit_byte(0xAE); | |
3658 emit_operand(rdi, adr); | |
3659 } | |
3660 | |
3661 void Assembler::cmovq(Condition cc, Register dst, Register src) { | |
3662 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
3663 emit_byte(0x0F); | |
3664 emit_byte(0x40 | cc); | |
3665 emit_byte(0xC0 | encode); | |
3666 } | |
3667 | |
3668 void Assembler::cmovq(Condition cc, Register dst, Address src) { | |
3669 InstructionMark im(this); | |
3670 prefixq(src, dst); | |
3671 emit_byte(0x0F); | |
3672 emit_byte(0x40 | cc); | |
3673 emit_operand(dst, src); | |
3674 } | |
3675 | |
3676 void Assembler::cmpq(Address dst, int32_t imm32) { | |
3677 InstructionMark im(this); | |
3678 prefixq(dst); | |
3679 emit_byte(0x81); | |
3680 emit_operand(rdi, dst, 4); | |
3681 emit_long(imm32); | |
3682 } | |
3683 | |
3684 void Assembler::cmpq(Register dst, int32_t imm32) { | |
3685 (void) prefixq_and_encode(dst->encoding()); | |
3686 emit_arith(0x81, 0xF8, dst, imm32); | |
3687 } | |
3688 | |
3689 void Assembler::cmpq(Address dst, Register src) { | |
3690 InstructionMark im(this); | |
3691 prefixq(dst, src); | |
3692 emit_byte(0x3B); | |
3693 emit_operand(src, dst); | |
3694 } | |
3695 | |
3696 void Assembler::cmpq(Register dst, Register src) { | |
3697 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
3698 emit_arith(0x3B, 0xC0, dst, src); | |
3699 } | |
3700 | |
3701 void Assembler::cmpq(Register dst, Address src) { | |
3702 InstructionMark im(this); | |
3703 prefixq(src, dst); | |
3704 emit_byte(0x3B); | |
3705 emit_operand(dst, src); | |
3706 } | |
3707 | |
3708 void Assembler::cmpxchgq(Register reg, Address adr) { | |
3709 InstructionMark im(this); | |
3710 prefixq(adr, reg); | |
3711 emit_byte(0x0F); | |
3712 emit_byte(0xB1); | |
3713 emit_operand(reg, adr); | |
3714 } | |
3715 | |
3716 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) { | |
3717 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
3718 emit_byte(0xF2); | |
3719 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
3720 emit_byte(0x0F); | |
3721 emit_byte(0x2A); | |
3722 emit_byte(0xC0 | encode); | |
3723 } | |
3724 | |
3725 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) { | |
3726 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
3727 emit_byte(0xF3); | |
3728 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
3729 emit_byte(0x0F); | |
3730 emit_byte(0x2A); | |
3731 emit_byte(0xC0 | encode); | |
3732 } | |
3733 | |
3734 void Assembler::cvttsd2siq(Register dst, XMMRegister src) { | |
3735 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
3736 emit_byte(0xF2); | |
3737 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
3738 emit_byte(0x0F); | |
3739 emit_byte(0x2C); | |
3740 emit_byte(0xC0 | encode); | |
3741 } | |
3742 | |
3743 void Assembler::cvttss2siq(Register dst, XMMRegister src) { | |
3744 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
3745 emit_byte(0xF3); | |
3746 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
3747 emit_byte(0x0F); | |
3748 emit_byte(0x2C); | |
3749 emit_byte(0xC0 | encode); | |
3750 } | |
3751 | |
3752 void Assembler::decl(Register dst) { | |
3753 // Don't use it directly. Use MacroAssembler::decrementl() instead. | |
3754 // Use two-byte form (one-byte form is a REX prefix in 64-bit mode) | |
3755 int encode = prefix_and_encode(dst->encoding()); | |
3756 emit_byte(0xFF); | |
3757 emit_byte(0xC8 | encode); | |
3758 } | |
3759 | |
3760 void Assembler::decq(Register dst) { | |
3761 // Don't use it directly. Use MacroAssembler::decrementq() instead. | |
3762 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode) | |
3763 int encode = prefixq_and_encode(dst->encoding()); | |
3764 emit_byte(0xFF); | |
3765 emit_byte(0xC8 | encode); | |
3766 } | |
3767 | |
3768 void Assembler::decq(Address dst) { | |
3769 // Don't use it directly. Use MacroAssembler::decrementq() instead. | |
3770 InstructionMark im(this); | |
3771 prefixq(dst); | |
3772 emit_byte(0xFF); | |
3773 emit_operand(rcx, dst); | |
3774 } | |
3775 | |
3776 void Assembler::fxrstor(Address src) { | |
3777 prefixq(src); | |
3778 emit_byte(0x0F); | |
3779 emit_byte(0xAE); | |
3780 emit_operand(as_Register(1), src); | |
3781 } | |
3782 | |
3783 void Assembler::fxsave(Address dst) { | |
3784 prefixq(dst); | |
3785 emit_byte(0x0F); | |
3786 emit_byte(0xAE); | |
3787 emit_operand(as_Register(0), dst); | |
3788 } | |
3789 | |
3790 void Assembler::idivq(Register src) { | |
3791 int encode = prefixq_and_encode(src->encoding()); | |
3792 emit_byte(0xF7); | |
3793 emit_byte(0xF8 | encode); | |
3794 } | |
3795 | |
3796 void Assembler::imulq(Register dst, Register src) { | |
3797 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
3798 emit_byte(0x0F); | |
3799 emit_byte(0xAF); | |
3800 emit_byte(0xC0 | encode); | |
3801 } | |
3802 | |
3803 void Assembler::imulq(Register dst, Register src, int value) { | |
3804 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
3805 if (is8bit(value)) { | |
3806 emit_byte(0x6B); | |
3807 emit_byte(0xC0 | encode); | |
3808 emit_byte(value); | |
3809 } else { | |
3810 emit_byte(0x69); | |
3811 emit_byte(0xC0 | encode); | |
3812 emit_long(value); | |
3813 } | |
3814 } | |
3815 | |
3816 void Assembler::incl(Register dst) { | |
3817 // Don't use it directly. Use MacroAssembler::incrementl() instead. | |
3818 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode) | |
3819 int encode = prefix_and_encode(dst->encoding()); | |
3820 emit_byte(0xFF); | |
3821 emit_byte(0xC0 | encode); | |
3822 } | |
3823 | |
3824 void Assembler::incq(Register dst) { | |
3825 // Don't use it directly. Use MacroAssembler::incrementq() instead. | |
3826 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode) | |
3827 int encode = prefixq_and_encode(dst->encoding()); | |
3828 emit_byte(0xFF); | |
3829 emit_byte(0xC0 | encode); | |
3830 } | |
3831 | |
3832 void Assembler::incq(Address dst) { | |
3833 // Don't use it directly. Use MacroAssembler::incrementq() instead. | |
3834 InstructionMark im(this); | |
3835 prefixq(dst); | |
3836 emit_byte(0xFF); | |
3837 emit_operand(rax, dst); | |
3838 } | |
3839 | |
3840 void Assembler::lea(Register dst, Address src) { | |
3841 leaq(dst, src); | |
3842 } | |
3843 | |
3844 void Assembler::leaq(Register dst, Address src) { | |
3845 InstructionMark im(this); | |
3846 prefixq(src, dst); | |
3847 emit_byte(0x8D); | |
3848 emit_operand(dst, src); | |
3849 } | |
3850 | |
3851 void Assembler::mov64(Register dst, int64_t imm64) { | |
3852 InstructionMark im(this); | |
3853 int encode = prefixq_and_encode(dst->encoding()); | |
3854 emit_byte(0xB8 | encode); | |
3855 emit_long64(imm64); | |
3856 } | |
3857 | |
3858 void Assembler::mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec) { | |
3859 InstructionMark im(this); | |
3860 int encode = prefixq_and_encode(dst->encoding()); | |
3861 emit_byte(0xB8 | encode); | |
3862 emit_data64(imm64, rspec); | |
3863 } | |
3864 | |
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3865 void Assembler::mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec) { |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3866 InstructionMark im(this); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3867 int encode = prefix_and_encode(dst->encoding()); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3868 emit_byte(0xB8 | encode); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3869 emit_data((int)imm32, rspec, narrow_oop_operand); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3870 } |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3871 |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3872 void Assembler::mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec) { |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3873 InstructionMark im(this); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3874 prefix(dst); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3875 emit_byte(0xC7); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3876 emit_operand(rax, dst, 4); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3877 emit_data((int)imm32, rspec, narrow_oop_operand); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3878 } |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3879 |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3880 void Assembler::cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec) { |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3881 InstructionMark im(this); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3882 int encode = prefix_and_encode(src1->encoding()); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3883 emit_byte(0x81); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3884 emit_byte(0xF8 | encode); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3885 emit_data((int)imm32, rspec, narrow_oop_operand); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3886 } |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3887 |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3888 void Assembler::cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec) { |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3889 InstructionMark im(this); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3890 prefix(src1); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3891 emit_byte(0x81); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3892 emit_operand(rax, src1, 4); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3893 emit_data((int)imm32, rspec, narrow_oop_operand); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3894 } |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3895 |
304 | 3896 void Assembler::movdq(XMMRegister dst, Register src) { |
3897 // table D-1 says MMX/SSE2 | |
3898 NOT_LP64(assert(VM_Version::supports_sse2() || VM_Version::supports_mmx(), "")); | |
0 | 3899 emit_byte(0x66); |
304 | 3900 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
0 | 3901 emit_byte(0x0F); |
304 | 3902 emit_byte(0x6E); |
3903 emit_byte(0xC0 | encode); | |
3904 } | |
3905 | |
3906 void Assembler::movdq(Register dst, XMMRegister src) { | |
3907 // table D-1 says MMX/SSE2 | |
3908 NOT_LP64(assert(VM_Version::supports_sse2() || VM_Version::supports_mmx(), "")); | |
0 | 3909 emit_byte(0x66); |
304 | 3910 // swap src/dst to get correct prefix |
3911 int encode = prefixq_and_encode(src->encoding(), dst->encoding()); | |
0 | 3912 emit_byte(0x0F); |
3913 emit_byte(0x7E); | |
304 | 3914 emit_byte(0xC0 | encode); |
3915 } | |
3916 | |
3917 void Assembler::movq(Register dst, Register src) { | |
3918 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
3919 emit_byte(0x8B); | |
3920 emit_byte(0xC0 | encode); | |
3921 } | |
3922 | |
3923 void Assembler::movq(Register dst, Address src) { | |
3924 InstructionMark im(this); | |
3925 prefixq(src, dst); | |
3926 emit_byte(0x8B); | |
3927 emit_operand(dst, src); | |
3928 } | |
3929 | |
3930 void Assembler::movq(Address dst, Register src) { | |
3931 InstructionMark im(this); | |
3932 prefixq(dst, src); | |
3933 emit_byte(0x89); | |
3934 emit_operand(src, dst); | |
3935 } | |
3936 | |
624 | 3937 void Assembler::movsbq(Register dst, Address src) { |
3938 InstructionMark im(this); | |
3939 prefixq(src, dst); | |
3940 emit_byte(0x0F); | |
3941 emit_byte(0xBE); | |
3942 emit_operand(dst, src); | |
3943 } | |
3944 | |
3945 void Assembler::movsbq(Register dst, Register src) { | |
3946 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
3947 emit_byte(0x0F); | |
3948 emit_byte(0xBE); | |
3949 emit_byte(0xC0 | encode); | |
3950 } | |
3951 | |
304 | 3952 void Assembler::movslq(Register dst, int32_t imm32) { |
3953 // dbx shows movslq(rcx, 3) as movq $0x0000000049000000,(%rbx) | |
3954 // and movslq(r8, 3); as movl $0x0000000048000000,(%rbx) | |
3955 // as a result we shouldn't use until tested at runtime... | |
3956 ShouldNotReachHere(); | |
3957 InstructionMark im(this); | |
3958 int encode = prefixq_and_encode(dst->encoding()); | |
3959 emit_byte(0xC7 | encode); | |
3960 emit_long(imm32); | |
3961 } | |
3962 | |
3963 void Assembler::movslq(Address dst, int32_t imm32) { | |
3964 assert(is_simm32(imm32), "lost bits"); | |
3965 InstructionMark im(this); | |
3966 prefixq(dst); | |
3967 emit_byte(0xC7); | |
3968 emit_operand(rax, dst, 4); | |
3969 emit_long(imm32); | |
3970 } | |
3971 | |
3972 void Assembler::movslq(Register dst, Address src) { | |
3973 InstructionMark im(this); | |
3974 prefixq(src, dst); | |
3975 emit_byte(0x63); | |
3976 emit_operand(dst, src); | |
3977 } | |
3978 | |
3979 void Assembler::movslq(Register dst, Register src) { | |
3980 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
3981 emit_byte(0x63); | |
3982 emit_byte(0xC0 | encode); | |
3983 } | |
3984 | |
624 | 3985 void Assembler::movswq(Register dst, Address src) { |
3986 InstructionMark im(this); | |
3987 prefixq(src, dst); | |
3988 emit_byte(0x0F); | |
3989 emit_byte(0xBF); | |
3990 emit_operand(dst, src); | |
3991 } | |
3992 | |
3993 void Assembler::movswq(Register dst, Register src) { | |
3994 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
3995 emit_byte(0x0F); | |
3996 emit_byte(0xBF); | |
3997 emit_byte(0xC0 | encode); | |
3998 } | |
3999 | |
4000 void Assembler::movzbq(Register dst, Address src) { | |
4001 InstructionMark im(this); | |
4002 prefixq(src, dst); | |
4003 emit_byte(0x0F); | |
4004 emit_byte(0xB6); | |
4005 emit_operand(dst, src); | |
4006 } | |
4007 | |
4008 void Assembler::movzbq(Register dst, Register src) { | |
4009 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
4010 emit_byte(0x0F); | |
4011 emit_byte(0xB6); | |
4012 emit_byte(0xC0 | encode); | |
4013 } | |
4014 | |
4015 void Assembler::movzwq(Register dst, Address src) { | |
4016 InstructionMark im(this); | |
4017 prefixq(src, dst); | |
4018 emit_byte(0x0F); | |
4019 emit_byte(0xB7); | |
4020 emit_operand(dst, src); | |
4021 } | |
4022 | |
4023 void Assembler::movzwq(Register dst, Register src) { | |
4024 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
4025 emit_byte(0x0F); | |
4026 emit_byte(0xB7); | |
4027 emit_byte(0xC0 | encode); | |
4028 } | |
4029 | |
304 | 4030 void Assembler::negq(Register dst) { |
4031 int encode = prefixq_and_encode(dst->encoding()); | |
4032 emit_byte(0xF7); | |
4033 emit_byte(0xD8 | encode); | |
4034 } | |
4035 | |
4036 void Assembler::notq(Register dst) { | |
4037 int encode = prefixq_and_encode(dst->encoding()); | |
4038 emit_byte(0xF7); | |
4039 emit_byte(0xD0 | encode); | |
4040 } | |
4041 | |
4042 void Assembler::orq(Address dst, int32_t imm32) { | |
4043 InstructionMark im(this); | |
4044 prefixq(dst); | |
4045 emit_byte(0x81); | |
4046 emit_operand(rcx, dst, 4); | |
4047 emit_long(imm32); | |
4048 } | |
4049 | |
4050 void Assembler::orq(Register dst, int32_t imm32) { | |
4051 (void) prefixq_and_encode(dst->encoding()); | |
4052 emit_arith(0x81, 0xC8, dst, imm32); | |
4053 } | |
4054 | |
4055 void Assembler::orq(Register dst, Address src) { | |
4056 InstructionMark im(this); | |
4057 prefixq(src, dst); | |
4058 emit_byte(0x0B); | |
4059 emit_operand(dst, src); | |
4060 } | |
4061 | |
4062 void Assembler::orq(Register dst, Register src) { | |
4063 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
4064 emit_arith(0x0B, 0xC0, dst, src); | |
4065 } | |
4066 | |
4067 void Assembler::popa() { // 64bit | |
4068 movq(r15, Address(rsp, 0)); | |
4069 movq(r14, Address(rsp, wordSize)); | |
4070 movq(r13, Address(rsp, 2 * wordSize)); | |
4071 movq(r12, Address(rsp, 3 * wordSize)); | |
4072 movq(r11, Address(rsp, 4 * wordSize)); | |
4073 movq(r10, Address(rsp, 5 * wordSize)); | |
4074 movq(r9, Address(rsp, 6 * wordSize)); | |
4075 movq(r8, Address(rsp, 7 * wordSize)); | |
4076 movq(rdi, Address(rsp, 8 * wordSize)); | |
4077 movq(rsi, Address(rsp, 9 * wordSize)); | |
4078 movq(rbp, Address(rsp, 10 * wordSize)); | |
4079 // skip rsp | |
4080 movq(rbx, Address(rsp, 12 * wordSize)); | |
4081 movq(rdx, Address(rsp, 13 * wordSize)); | |
4082 movq(rcx, Address(rsp, 14 * wordSize)); | |
4083 movq(rax, Address(rsp, 15 * wordSize)); | |
4084 | |
4085 addq(rsp, 16 * wordSize); | |
4086 } | |
4087 | |
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
4088 void Assembler::popcntq(Register dst, Address src) { |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
4089 assert(VM_Version::supports_popcnt(), "must support"); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
4090 InstructionMark im(this); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
4091 emit_byte(0xF3); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
4092 prefixq(src, dst); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
4093 emit_byte(0x0F); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
4094 emit_byte(0xB8); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
4095 emit_operand(dst, src); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
4096 } |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
4097 |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
4098 void Assembler::popcntq(Register dst, Register src) { |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
4099 assert(VM_Version::supports_popcnt(), "must support"); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
4100 emit_byte(0xF3); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
4101 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
4102 emit_byte(0x0F); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
4103 emit_byte(0xB8); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
4104 emit_byte(0xC0 | encode); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
4105 } |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
4106 |
304 | 4107 void Assembler::popq(Address dst) { |
4108 InstructionMark im(this); | |
4109 prefixq(dst); | |
4110 emit_byte(0x8F); | |
4111 emit_operand(rax, dst); | |
4112 } | |
4113 | |
4114 void Assembler::pusha() { // 64bit | |
4115 // we have to store original rsp. ABI says that 128 bytes | |
4116 // below rsp are local scratch. | |
4117 movq(Address(rsp, -5 * wordSize), rsp); | |
4118 | |
4119 subq(rsp, 16 * wordSize); | |
4120 | |
4121 movq(Address(rsp, 15 * wordSize), rax); | |
4122 movq(Address(rsp, 14 * wordSize), rcx); | |
4123 movq(Address(rsp, 13 * wordSize), rdx); | |
4124 movq(Address(rsp, 12 * wordSize), rbx); | |
4125 // skip rsp | |
4126 movq(Address(rsp, 10 * wordSize), rbp); | |
4127 movq(Address(rsp, 9 * wordSize), rsi); | |
4128 movq(Address(rsp, 8 * wordSize), rdi); | |
4129 movq(Address(rsp, 7 * wordSize), r8); | |
4130 movq(Address(rsp, 6 * wordSize), r9); | |
4131 movq(Address(rsp, 5 * wordSize), r10); | |
4132 movq(Address(rsp, 4 * wordSize), r11); | |
4133 movq(Address(rsp, 3 * wordSize), r12); | |
4134 movq(Address(rsp, 2 * wordSize), r13); | |
4135 movq(Address(rsp, wordSize), r14); | |
4136 movq(Address(rsp, 0), r15); | |
4137 } | |
4138 | |
4139 void Assembler::pushq(Address src) { | |
4140 InstructionMark im(this); | |
4141 prefixq(src); | |
4142 emit_byte(0xFF); | |
4143 emit_operand(rsi, src); | |
4144 } | |
4145 | |
4146 void Assembler::rclq(Register dst, int imm8) { | |
4147 assert(isShiftCount(imm8 >> 1), "illegal shift count"); | |
4148 int encode = prefixq_and_encode(dst->encoding()); | |
4149 if (imm8 == 1) { | |
4150 emit_byte(0xD1); | |
4151 emit_byte(0xD0 | encode); | |
4152 } else { | |
4153 emit_byte(0xC1); | |
4154 emit_byte(0xD0 | encode); | |
4155 emit_byte(imm8); | |
4156 } | |
4157 } | |
4158 void Assembler::sarq(Register dst, int imm8) { | |
4159 assert(isShiftCount(imm8 >> 1), "illegal shift count"); | |
4160 int encode = prefixq_and_encode(dst->encoding()); | |
4161 if (imm8 == 1) { | |
4162 emit_byte(0xD1); | |
4163 emit_byte(0xF8 | encode); | |
4164 } else { | |
4165 emit_byte(0xC1); | |
4166 emit_byte(0xF8 | encode); | |
4167 emit_byte(imm8); | |
4168 } | |
4169 } | |
4170 | |
4171 void Assembler::sarq(Register dst) { | |
4172 int encode = prefixq_and_encode(dst->encoding()); | |
4173 emit_byte(0xD3); | |
4174 emit_byte(0xF8 | encode); | |
4175 } | |
4176 void Assembler::sbbq(Address dst, int32_t imm32) { | |
4177 InstructionMark im(this); | |
4178 prefixq(dst); | |
4179 emit_arith_operand(0x81, rbx, dst, imm32); | |
4180 } | |
4181 | |
4182 void Assembler::sbbq(Register dst, int32_t imm32) { | |
4183 (void) prefixq_and_encode(dst->encoding()); | |
4184 emit_arith(0x81, 0xD8, dst, imm32); | |
4185 } | |
4186 | |
4187 void Assembler::sbbq(Register dst, Address src) { | |
4188 InstructionMark im(this); | |
4189 prefixq(src, dst); | |
4190 emit_byte(0x1B); | |
4191 emit_operand(dst, src); | |
4192 } | |
4193 | |
4194 void Assembler::sbbq(Register dst, Register src) { | |
4195 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
4196 emit_arith(0x1B, 0xC0, dst, src); | |
4197 } | |
4198 | |
4199 void Assembler::shlq(Register dst, int imm8) { | |
4200 assert(isShiftCount(imm8 >> 1), "illegal shift count"); | |
4201 int encode = prefixq_and_encode(dst->encoding()); | |
4202 if (imm8 == 1) { | |
4203 emit_byte(0xD1); | |
4204 emit_byte(0xE0 | encode); | |
4205 } else { | |
4206 emit_byte(0xC1); | |
4207 emit_byte(0xE0 | encode); | |
4208 emit_byte(imm8); | |
4209 } | |
4210 } | |
4211 | |
4212 void Assembler::shlq(Register dst) { | |
4213 int encode = prefixq_and_encode(dst->encoding()); | |
4214 emit_byte(0xD3); | |
4215 emit_byte(0xE0 | encode); | |
4216 } | |
4217 | |
4218 void Assembler::shrq(Register dst, int imm8) { | |
4219 assert(isShiftCount(imm8 >> 1), "illegal shift count"); | |
4220 int encode = prefixq_and_encode(dst->encoding()); | |
4221 emit_byte(0xC1); | |
4222 emit_byte(0xE8 | encode); | |
4223 emit_byte(imm8); | |
4224 } | |
4225 | |
4226 void Assembler::shrq(Register dst) { | |
4227 int encode = prefixq_and_encode(dst->encoding()); | |
4228 emit_byte(0xD3); | |
4229 emit_byte(0xE8 | encode); | |
4230 } | |
4231 | |
4232 void Assembler::sqrtsd(XMMRegister dst, Address src) { | |
4233 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
0 | 4234 InstructionMark im(this); |
4235 emit_byte(0xF2); | |
304 | 4236 prefix(src, dst); |
0 | 4237 emit_byte(0x0F); |
304 | 4238 emit_byte(0x51); |
4239 emit_operand(dst, src); | |
4240 } | |
4241 | |
4242 void Assembler::subq(Address dst, int32_t imm32) { | |
4243 InstructionMark im(this); | |
4244 prefixq(dst); | |
4245 if (is8bit(imm32)) { | |
4246 emit_byte(0x83); | |
4247 emit_operand(rbp, dst, 1); | |
4248 emit_byte(imm32 & 0xFF); | |
4249 } else { | |
4250 emit_byte(0x81); | |
4251 emit_operand(rbp, dst, 4); | |
4252 emit_long(imm32); | |
4253 } | |
4254 } | |
4255 | |
4256 void Assembler::subq(Register dst, int32_t imm32) { | |
4257 (void) prefixq_and_encode(dst->encoding()); | |
4258 emit_arith(0x81, 0xE8, dst, imm32); | |
4259 } | |
4260 | |
4261 void Assembler::subq(Address dst, Register src) { | |
4262 InstructionMark im(this); | |
4263 prefixq(dst, src); | |
4264 emit_byte(0x29); | |
4265 emit_operand(src, dst); | |
4266 } | |
4267 | |
4268 void Assembler::subq(Register dst, Address src) { | |
4269 InstructionMark im(this); | |
4270 prefixq(src, dst); | |
4271 emit_byte(0x2B); | |
4272 emit_operand(dst, src); | |
4273 } | |
4274 | |
4275 void Assembler::subq(Register dst, Register src) { | |
4276 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
4277 emit_arith(0x2B, 0xC0, dst, src); | |
4278 } | |
4279 | |
4280 void Assembler::testq(Register dst, int32_t imm32) { | |
4281 // not using emit_arith because test | |
4282 // doesn't support sign-extension of | |
4283 // 8bit operands | |
4284 int encode = dst->encoding(); | |
4285 if (encode == 0) { | |
4286 prefix(REX_W); | |
4287 emit_byte(0xA9); | |
4288 } else { | |
4289 encode = prefixq_and_encode(encode); | |
4290 emit_byte(0xF7); | |
4291 emit_byte(0xC0 | encode); | |
4292 } | |
4293 emit_long(imm32); | |
4294 } | |
4295 | |
4296 void Assembler::testq(Register dst, Register src) { | |
4297 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
4298 emit_arith(0x85, 0xC0, dst, src); | |
4299 } | |
4300 | |
4301 void Assembler::xaddq(Address dst, Register src) { | |
4302 InstructionMark im(this); | |
4303 prefixq(dst, src); | |
71 | 4304 emit_byte(0x0F); |
304 | 4305 emit_byte(0xC1); |
4306 emit_operand(src, dst); | |
4307 } | |
4308 | |
4309 void Assembler::xchgq(Register dst, Address src) { | |
4310 InstructionMark im(this); | |
4311 prefixq(src, dst); | |
4312 emit_byte(0x87); | |
4313 emit_operand(dst, src); | |
4314 } | |
4315 | |
4316 void Assembler::xchgq(Register dst, Register src) { | |
4317 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
4318 emit_byte(0x87); | |
4319 emit_byte(0xc0 | encode); | |
4320 } | |
4321 | |
4322 void Assembler::xorq(Register dst, Register src) { | |
4323 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
4324 emit_arith(0x33, 0xC0, dst, src); | |
4325 } | |
4326 | |
4327 void Assembler::xorq(Register dst, Address src) { | |
4328 InstructionMark im(this); | |
4329 prefixq(src, dst); | |
4330 emit_byte(0x33); | |
4331 emit_operand(dst, src); | |
4332 } | |
4333 | |
4334 #endif // !LP64 | |
4335 | |
4336 static Assembler::Condition reverse[] = { | |
4337 Assembler::noOverflow /* overflow = 0x0 */ , | |
4338 Assembler::overflow /* noOverflow = 0x1 */ , | |
4339 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ , | |
4340 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ , | |
4341 Assembler::notZero /* zero = 0x4, equal = 0x4 */ , | |
4342 Assembler::zero /* notZero = 0x5, notEqual = 0x5 */ , | |
4343 Assembler::above /* belowEqual = 0x6 */ , | |
4344 Assembler::belowEqual /* above = 0x7 */ , | |
4345 Assembler::positive /* negative = 0x8 */ , | |
4346 Assembler::negative /* positive = 0x9 */ , | |
4347 Assembler::noParity /* parity = 0xa */ , | |
4348 Assembler::parity /* noParity = 0xb */ , | |
4349 Assembler::greaterEqual /* less = 0xc */ , | |
4350 Assembler::less /* greaterEqual = 0xd */ , | |
4351 Assembler::greater /* lessEqual = 0xe */ , | |
4352 Assembler::lessEqual /* greater = 0xf, */ | |
4353 | |
4354 }; | |
4355 | |
0 | 4356 |
4357 // Implementation of MacroAssembler | |
4358 | |
304 | 4359 // First all the versions that have distinct versions depending on 32/64 bit |
4360 // Unless the difference is trivial (1 line or so). | |
4361 | |
4362 #ifndef _LP64 | |
4363 | |
4364 // 32bit versions | |
4365 | |
0 | 4366 Address MacroAssembler::as_Address(AddressLiteral adr) { |
4367 return Address(adr.target(), adr.rspec()); | |
4368 } | |
4369 | |
4370 Address MacroAssembler::as_Address(ArrayAddress adr) { | |
4371 return Address::make_array(adr); | |
4372 } | |
4373 | |
304 | 4374 int MacroAssembler::biased_locking_enter(Register lock_reg, |
4375 Register obj_reg, | |
4376 Register swap_reg, | |
4377 Register tmp_reg, | |
4378 bool swap_reg_contains_mark, | |
4379 Label& done, | |
4380 Label* slow_case, | |
4381 BiasedLockingCounters* counters) { | |
4382 assert(UseBiasedLocking, "why call this otherwise?"); | |
4383 assert(swap_reg == rax, "swap_reg must be rax, for cmpxchg"); | |
4384 assert_different_registers(lock_reg, obj_reg, swap_reg); | |
4385 | |
4386 if (PrintBiasedLockingStatistics && counters == NULL) | |
4387 counters = BiasedLocking::counters(); | |
4388 | |
4389 bool need_tmp_reg = false; | |
4390 if (tmp_reg == noreg) { | |
4391 need_tmp_reg = true; | |
4392 tmp_reg = lock_reg; | |
4393 } else { | |
4394 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg); | |
4395 } | |
4396 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout"); | |
4397 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes()); | |
4398 Address klass_addr (obj_reg, oopDesc::klass_offset_in_bytes()); | |
4399 Address saved_mark_addr(lock_reg, 0); | |
4400 | |
4401 // Biased locking | |
4402 // See whether the lock is currently biased toward our thread and | |
4403 // whether the epoch is still valid | |
4404 // Note that the runtime guarantees sufficient alignment of JavaThread | |
4405 // pointers to allow age to be placed into low bits | |
4406 // First check to see whether biasing is even enabled for this object | |
4407 Label cas_label; | |
4408 int null_check_offset = -1; | |
4409 if (!swap_reg_contains_mark) { | |
4410 null_check_offset = offset(); | |
4411 movl(swap_reg, mark_addr); | |
4412 } | |
4413 if (need_tmp_reg) { | |
4414 push(tmp_reg); | |
4415 } | |
4416 movl(tmp_reg, swap_reg); | |
4417 andl(tmp_reg, markOopDesc::biased_lock_mask_in_place); | |
4418 cmpl(tmp_reg, markOopDesc::biased_lock_pattern); | |
4419 if (need_tmp_reg) { | |
4420 pop(tmp_reg); | |
4421 } | |
4422 jcc(Assembler::notEqual, cas_label); | |
4423 // The bias pattern is present in the object's header. Need to check | |
4424 // whether the bias owner and the epoch are both still current. | |
4425 // Note that because there is no current thread register on x86 we | |
4426 // need to store off the mark word we read out of the object to | |
4427 // avoid reloading it and needing to recheck invariants below. This | |
4428 // store is unfortunate but it makes the overall code shorter and | |
4429 // simpler. | |
4430 movl(saved_mark_addr, swap_reg); | |
4431 if (need_tmp_reg) { | |
4432 push(tmp_reg); | |
4433 } | |
4434 get_thread(tmp_reg); | |
4435 xorl(swap_reg, tmp_reg); | |
4436 if (swap_reg_contains_mark) { | |
4437 null_check_offset = offset(); | |
4438 } | |
4439 movl(tmp_reg, klass_addr); | |
4440 xorl(swap_reg, Address(tmp_reg, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes())); | |
4441 andl(swap_reg, ~((int) markOopDesc::age_mask_in_place)); | |
4442 if (need_tmp_reg) { | |
4443 pop(tmp_reg); | |
4444 } | |
4445 if (counters != NULL) { | |
4446 cond_inc32(Assembler::zero, | |
4447 ExternalAddress((address)counters->biased_lock_entry_count_addr())); | |
4448 } | |
4449 jcc(Assembler::equal, done); | |
4450 | |
4451 Label try_revoke_bias; | |
4452 Label try_rebias; | |
4453 | |
4454 // At this point we know that the header has the bias pattern and | |
4455 // that we are not the bias owner in the current epoch. We need to | |
4456 // figure out more details about the state of the header in order to | |
4457 // know what operations can be legally performed on the object's | |
4458 // header. | |
4459 | |
4460 // If the low three bits in the xor result aren't clear, that means | |
4461 // the prototype header is no longer biased and we have to revoke | |
4462 // the bias on this object. | |
4463 testl(swap_reg, markOopDesc::biased_lock_mask_in_place); | |
4464 jcc(Assembler::notZero, try_revoke_bias); | |
4465 | |
4466 // Biasing is still enabled for this data type. See whether the | |
4467 // epoch of the current bias is still valid, meaning that the epoch | |
4468 // bits of the mark word are equal to the epoch bits of the | |
4469 // prototype header. (Note that the prototype header's epoch bits | |
4470 // only change at a safepoint.) If not, attempt to rebias the object | |
4471 // toward the current thread. Note that we must be absolutely sure | |
4472 // that the current epoch is invalid in order to do this because | |
4473 // otherwise the manipulations it performs on the mark word are | |
4474 // illegal. | |
4475 testl(swap_reg, markOopDesc::epoch_mask_in_place); | |
4476 jcc(Assembler::notZero, try_rebias); | |
4477 | |
4478 // The epoch of the current bias is still valid but we know nothing | |
4479 // about the owner; it might be set or it might be clear. Try to | |
4480 // acquire the bias of the object using an atomic operation. If this | |
4481 // fails we will go in to the runtime to revoke the object's bias. | |
4482 // Note that we first construct the presumed unbiased header so we | |
4483 // don't accidentally blow away another thread's valid bias. | |
4484 movl(swap_reg, saved_mark_addr); | |
4485 andl(swap_reg, | |
4486 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place); | |
4487 if (need_tmp_reg) { | |
4488 push(tmp_reg); | |
4489 } | |
4490 get_thread(tmp_reg); | |
4491 orl(tmp_reg, swap_reg); | |
4492 if (os::is_MP()) { | |
4493 lock(); | |
4494 } | |
4495 cmpxchgptr(tmp_reg, Address(obj_reg, 0)); | |
4496 if (need_tmp_reg) { | |
4497 pop(tmp_reg); | |
4498 } | |
4499 // If the biasing toward our thread failed, this means that | |
4500 // another thread succeeded in biasing it toward itself and we | |
4501 // need to revoke that bias. The revocation will occur in the | |
4502 // interpreter runtime in the slow case. | |
4503 if (counters != NULL) { | |
4504 cond_inc32(Assembler::zero, | |
4505 ExternalAddress((address)counters->anonymously_biased_lock_entry_count_addr())); | |
4506 } | |
4507 if (slow_case != NULL) { | |
4508 jcc(Assembler::notZero, *slow_case); | |
4509 } | |
4510 jmp(done); | |
4511 | |
4512 bind(try_rebias); | |
4513 // At this point we know the epoch has expired, meaning that the | |
4514 // current "bias owner", if any, is actually invalid. Under these | |
4515 // circumstances _only_, we are allowed to use the current header's | |
4516 // value as the comparison value when doing the cas to acquire the | |
4517 // bias in the current epoch. In other words, we allow transfer of | |
4518 // the bias from one thread to another directly in this situation. | |
4519 // | |
4520 // FIXME: due to a lack of registers we currently blow away the age | |
4521 // bits in this situation. Should attempt to preserve them. | |
4522 if (need_tmp_reg) { | |
4523 push(tmp_reg); | |
4524 } | |
4525 get_thread(tmp_reg); | |
4526 movl(swap_reg, klass_addr); | |
4527 orl(tmp_reg, Address(swap_reg, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes())); | |
4528 movl(swap_reg, saved_mark_addr); | |
4529 if (os::is_MP()) { | |
4530 lock(); | |
4531 } | |
4532 cmpxchgptr(tmp_reg, Address(obj_reg, 0)); | |
4533 if (need_tmp_reg) { | |
4534 pop(tmp_reg); | |
4535 } | |
4536 // If the biasing toward our thread failed, then another thread | |
4537 // succeeded in biasing it toward itself and we need to revoke that | |
4538 // bias. The revocation will occur in the runtime in the slow case. | |
4539 if (counters != NULL) { | |
4540 cond_inc32(Assembler::zero, | |
4541 ExternalAddress((address)counters->rebiased_lock_entry_count_addr())); | |
4542 } | |
4543 if (slow_case != NULL) { | |
4544 jcc(Assembler::notZero, *slow_case); | |
4545 } | |
4546 jmp(done); | |
4547 | |
4548 bind(try_revoke_bias); | |
4549 // The prototype mark in the klass doesn't have the bias bit set any | |
4550 // more, indicating that objects of this data type are not supposed | |
4551 // to be biased any more. We are going to try to reset the mark of | |
4552 // this object to the prototype value and fall through to the | |
4553 // CAS-based locking scheme. Note that if our CAS fails, it means | |
4554 // that another thread raced us for the privilege of revoking the | |
4555 // bias of this particular object, so it's okay to continue in the | |
4556 // normal locking code. | |
4557 // | |
4558 // FIXME: due to a lack of registers we currently blow away the age | |
4559 // bits in this situation. Should attempt to preserve them. | |
4560 movl(swap_reg, saved_mark_addr); | |
4561 if (need_tmp_reg) { | |
4562 push(tmp_reg); | |
4563 } | |
4564 movl(tmp_reg, klass_addr); | |
4565 movl(tmp_reg, Address(tmp_reg, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes())); | |
4566 if (os::is_MP()) { | |
4567 lock(); | |
4568 } | |
4569 cmpxchgptr(tmp_reg, Address(obj_reg, 0)); | |
4570 if (need_tmp_reg) { | |
4571 pop(tmp_reg); | |
4572 } | |
4573 // Fall through to the normal CAS-based lock, because no matter what | |
4574 // the result of the above CAS, some thread must have succeeded in | |
4575 // removing the bias bit from the object's header. | |
4576 if (counters != NULL) { | |
4577 cond_inc32(Assembler::zero, | |
4578 ExternalAddress((address)counters->revoked_lock_entry_count_addr())); | |
4579 } | |
4580 | |
4581 bind(cas_label); | |
4582 | |
4583 return null_check_offset; | |
4584 } | |
4585 void MacroAssembler::call_VM_leaf_base(address entry_point, | |
4586 int number_of_arguments) { | |
4587 call(RuntimeAddress(entry_point)); | |
4588 increment(rsp, number_of_arguments * wordSize); | |
4589 } | |
4590 | |
4591 void MacroAssembler::cmpoop(Address src1, jobject obj) { | |
4592 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate()); | |
4593 } | |
4594 | |
4595 void MacroAssembler::cmpoop(Register src1, jobject obj) { | |
4596 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate()); | |
4597 } | |
4598 | |
4599 void MacroAssembler::extend_sign(Register hi, Register lo) { | |
4600 // According to Intel Doc. AP-526, "Integer Divide", p.18. | |
4601 if (VM_Version::is_P6() && hi == rdx && lo == rax) { | |
4602 cdql(); | |
4603 } else { | |
4604 movl(hi, lo); | |
4605 sarl(hi, 31); | |
4606 } | |
4607 } | |
4608 | |
0 | 4609 void MacroAssembler::fat_nop() { |
4610 // A 5 byte nop that is safe for patching (see patch_verified_entry) | |
4611 emit_byte(0x26); // es: | |
4612 emit_byte(0x2e); // cs: | |
4613 emit_byte(0x64); // fs: | |
4614 emit_byte(0x65); // gs: | |
4615 emit_byte(0x90); | |
4616 } | |
4617 | |
304 | 4618 void MacroAssembler::jC2(Register tmp, Label& L) { |
4619 // set parity bit if FPU flag C2 is set (via rax) | |
4620 save_rax(tmp); | |
4621 fwait(); fnstsw_ax(); | |
4622 sahf(); | |
4623 restore_rax(tmp); | |
4624 // branch | |
4625 jcc(Assembler::parity, L); | |
4626 } | |
4627 | |
4628 void MacroAssembler::jnC2(Register tmp, Label& L) { | |
4629 // set parity bit if FPU flag C2 is set (via rax) | |
4630 save_rax(tmp); | |
4631 fwait(); fnstsw_ax(); | |
4632 sahf(); | |
4633 restore_rax(tmp); | |
4634 // branch | |
4635 jcc(Assembler::noParity, L); | |
4636 } | |
4637 | |
0 | 4638 // 32bit can do a case table jump in one instruction but we no longer allow the base |
4639 // to be installed in the Address class | |
4640 void MacroAssembler::jump(ArrayAddress entry) { | |
4641 jmp(as_Address(entry)); | |
4642 } | |
4643 | |
304 | 4644 // Note: y_lo will be destroyed |
4645 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) { | |
4646 // Long compare for Java (semantics as described in JVM spec.) | |
4647 Label high, low, done; | |
4648 | |
4649 cmpl(x_hi, y_hi); | |
4650 jcc(Assembler::less, low); | |
4651 jcc(Assembler::greater, high); | |
4652 // x_hi is the return register | |
4653 xorl(x_hi, x_hi); | |
4654 cmpl(x_lo, y_lo); | |
4655 jcc(Assembler::below, low); | |
4656 jcc(Assembler::equal, done); | |
4657 | |
4658 bind(high); | |
4659 xorl(x_hi, x_hi); | |
4660 increment(x_hi); | |
4661 jmp(done); | |
4662 | |
4663 bind(low); | |
4664 xorl(x_hi, x_hi); | |
4665 decrementl(x_hi); | |
4666 | |
4667 bind(done); | |
4668 } | |
4669 | |
4670 void MacroAssembler::lea(Register dst, AddressLiteral src) { | |
4671 mov_literal32(dst, (int32_t)src.target(), src.rspec()); | |
0 | 4672 } |
4673 | |
4674 void MacroAssembler::lea(Address dst, AddressLiteral adr) { | |
4675 // leal(dst, as_Address(adr)); | |
304 | 4676 // see note in movl as to why we must use a move |
0 | 4677 mov_literal32(dst, (int32_t) adr.target(), adr.rspec()); |
4678 } | |
4679 | |
4680 void MacroAssembler::leave() { | |
304 | 4681 mov(rsp, rbp); |
4682 pop(rbp); | |
4683 } | |
0 | 4684 |
4685 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) { | |
4686 // Multiplication of two Java long values stored on the stack | |
4687 // as illustrated below. Result is in rdx:rax. | |
4688 // | |
4689 // rsp ---> [ ?? ] \ \ | |
4690 // .... | y_rsp_offset | | |
4691 // [ y_lo ] / (in bytes) | x_rsp_offset | |
4692 // [ y_hi ] | (in bytes) | |
4693 // .... | | |
4694 // [ x_lo ] / | |
4695 // [ x_hi ] | |
4696 // .... | |
4697 // | |
4698 // Basic idea: lo(result) = lo(x_lo * y_lo) | |
4699 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi) | |
4700 Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset); | |
4701 Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset); | |
4702 Label quick; | |
4703 // load x_hi, y_hi and check if quick | |
4704 // multiplication is possible | |
4705 movl(rbx, x_hi); | |
4706 movl(rcx, y_hi); | |
4707 movl(rax, rbx); | |
4708 orl(rbx, rcx); // rbx, = 0 <=> x_hi = 0 and y_hi = 0 | |
4709 jcc(Assembler::zero, quick); // if rbx, = 0 do quick multiply | |
4710 // do full multiplication | |
4711 // 1st step | |
4712 mull(y_lo); // x_hi * y_lo | |
4713 movl(rbx, rax); // save lo(x_hi * y_lo) in rbx, | |
4714 // 2nd step | |
4715 movl(rax, x_lo); | |
4716 mull(rcx); // x_lo * y_hi | |
4717 addl(rbx, rax); // add lo(x_lo * y_hi) to rbx, | |
4718 // 3rd step | |
4719 bind(quick); // note: rbx, = 0 if quick multiply! | |
4720 movl(rax, x_lo); | |
4721 mull(y_lo); // x_lo * y_lo | |
4722 addl(rdx, rbx); // correct hi(x_lo * y_lo) | |
4723 } | |
4724 | |
304 | 4725 void MacroAssembler::lneg(Register hi, Register lo) { |
4726 negl(lo); | |
4727 adcl(hi, 0); | |
4728 negl(hi); | |
4729 } | |
0 | 4730 |
4731 void MacroAssembler::lshl(Register hi, Register lo) { | |
4732 // Java shift left long support (semantics as described in JVM spec., p.305) | |
4733 // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n)) | |
4734 // shift value is in rcx ! | |
4735 assert(hi != rcx, "must not use rcx"); | |
4736 assert(lo != rcx, "must not use rcx"); | |
4737 const Register s = rcx; // shift count | |
4738 const int n = BitsPerWord; | |
4739 Label L; | |
4740 andl(s, 0x3f); // s := s & 0x3f (s < 0x40) | |
4741 cmpl(s, n); // if (s < n) | |
4742 jcc(Assembler::less, L); // else (s >= n) | |
4743 movl(hi, lo); // x := x << n | |
4744 xorl(lo, lo); | |
4745 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n! | |
4746 bind(L); // s (mod n) < n | |
4747 shldl(hi, lo); // x := x << s | |
4748 shll(lo); | |
4749 } | |
4750 | |
4751 | |
4752 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) { | |
4753 // Java shift right long support (semantics as described in JVM spec., p.306 & p.310) | |
4754 // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n)) | |
4755 assert(hi != rcx, "must not use rcx"); | |
4756 assert(lo != rcx, "must not use rcx"); | |
4757 const Register s = rcx; // shift count | |
4758 const int n = BitsPerWord; | |
4759 Label L; | |
4760 andl(s, 0x3f); // s := s & 0x3f (s < 0x40) | |
4761 cmpl(s, n); // if (s < n) | |
4762 jcc(Assembler::less, L); // else (s >= n) | |
4763 movl(lo, hi); // x := x >> n | |
4764 if (sign_extension) sarl(hi, 31); | |
4765 else xorl(hi, hi); | |
4766 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n! | |
4767 bind(L); // s (mod n) < n | |
4768 shrdl(lo, hi); // x := x >> s | |
4769 if (sign_extension) sarl(hi); | |
4770 else shrl(hi); | |
4771 } | |
4772 | |
304 | 4773 void MacroAssembler::movoop(Register dst, jobject obj) { |
4774 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate()); | |
4775 } | |
4776 | |
4777 void MacroAssembler::movoop(Address dst, jobject obj) { | |
4778 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate()); | |
4779 } | |
4780 | |
4781 void MacroAssembler::movptr(Register dst, AddressLiteral src) { | |
4782 if (src.is_lval()) { | |
4783 mov_literal32(dst, (intptr_t)src.target(), src.rspec()); | |
4784 } else { | |
4785 movl(dst, as_Address(src)); | |
4786 } | |
4787 } | |
4788 | |
4789 void MacroAssembler::movptr(ArrayAddress dst, Register src) { | |
4790 movl(as_Address(dst), src); | |
4791 } | |
4792 | |
4793 void MacroAssembler::movptr(Register dst, ArrayAddress src) { | |
4794 movl(dst, as_Address(src)); | |
4795 } | |
4796 | |
4797 // src should NEVER be a real pointer. Use AddressLiteral for true pointers | |
4798 void MacroAssembler::movptr(Address dst, intptr_t src) { | |
4799 movl(dst, src); | |
4800 } | |
4801 | |
4802 | |
4803 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src) { | |
4804 movsd(dst, as_Address(src)); | |
4805 } | |
4806 | |
4807 void MacroAssembler::pop_callee_saved_registers() { | |
4808 pop(rcx); | |
4809 pop(rdx); | |
4810 pop(rdi); | |
4811 pop(rsi); | |
4812 } | |
4813 | |
4814 void MacroAssembler::pop_fTOS() { | |
4815 fld_d(Address(rsp, 0)); | |
4816 addl(rsp, 2 * wordSize); | |
4817 } | |
4818 | |
4819 void MacroAssembler::push_callee_saved_registers() { | |
4820 push(rsi); | |
4821 push(rdi); | |
4822 push(rdx); | |
4823 push(rcx); | |
4824 } | |
4825 | |
4826 void MacroAssembler::push_fTOS() { | |
4827 subl(rsp, 2 * wordSize); | |
4828 fstp_d(Address(rsp, 0)); | |
4829 } | |
4830 | |
4831 | |
4832 void MacroAssembler::pushoop(jobject obj) { | |
4833 push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate()); | |
4834 } | |
4835 | |
4836 | |
4837 void MacroAssembler::pushptr(AddressLiteral src) { | |
4838 if (src.is_lval()) { | |
4839 push_literal32((int32_t)src.target(), src.rspec()); | |
4840 } else { | |
4841 pushl(as_Address(src)); | |
4842 } | |
4843 } | |
4844 | |
4845 void MacroAssembler::set_word_if_not_zero(Register dst) { | |
4846 xorl(dst, dst); | |
4847 set_byte_if_not_zero(dst); | |
4848 } | |
4849 | |
4850 static void pass_arg0(MacroAssembler* masm, Register arg) { | |
4851 masm->push(arg); | |
4852 } | |
4853 | |
4854 static void pass_arg1(MacroAssembler* masm, Register arg) { | |
4855 masm->push(arg); | |
4856 } | |
4857 | |
4858 static void pass_arg2(MacroAssembler* masm, Register arg) { | |
4859 masm->push(arg); | |
4860 } | |
4861 | |
4862 static void pass_arg3(MacroAssembler* masm, Register arg) { | |
4863 masm->push(arg); | |
4864 } | |
4865 | |
4866 #ifndef PRODUCT | |
4867 extern "C" void findpc(intptr_t x); | |
4868 #endif | |
4869 | |
4870 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) { | |
4871 // In order to get locks to work, we need to fake a in_VM state | |
4872 JavaThread* thread = JavaThread::current(); | |
4873 JavaThreadState saved_state = thread->thread_state(); | |
4874 thread->set_thread_state(_thread_in_vm); | |
4875 if (ShowMessageBoxOnError) { | |
4876 JavaThread* thread = JavaThread::current(); | |
4877 JavaThreadState saved_state = thread->thread_state(); | |
4878 thread->set_thread_state(_thread_in_vm); | |
4879 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) { | |
4880 ttyLocker ttyl; | |
4881 BytecodeCounter::print(); | |
4882 } | |
4883 // To see where a verify_oop failed, get $ebx+40/X for this frame. | |
4884 // This is the value of eip which points to where verify_oop will return. | |
4885 if (os::message_box(msg, "Execution stopped, print registers?")) { | |
4886 ttyLocker ttyl; | |
4887 tty->print_cr("eip = 0x%08x", eip); | |
4888 #ifndef PRODUCT | |
4889 tty->cr(); | |
4890 findpc(eip); | |
4891 tty->cr(); | |
4892 #endif | |
4893 tty->print_cr("rax, = 0x%08x", rax); | |
4894 tty->print_cr("rbx, = 0x%08x", rbx); | |
4895 tty->print_cr("rcx = 0x%08x", rcx); | |
4896 tty->print_cr("rdx = 0x%08x", rdx); | |
4897 tty->print_cr("rdi = 0x%08x", rdi); | |
4898 tty->print_cr("rsi = 0x%08x", rsi); | |
4899 tty->print_cr("rbp, = 0x%08x", rbp); | |
4900 tty->print_cr("rsp = 0x%08x", rsp); | |
4901 BREAKPOINT; | |
4902 } | |
4903 } else { | |
4904 ttyLocker ttyl; | |
4905 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg); | |
4906 assert(false, "DEBUG MESSAGE"); | |
4907 } | |
4908 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state); | |
4909 } | |
4910 | |
4911 void MacroAssembler::stop(const char* msg) { | |
4912 ExternalAddress message((address)msg); | |
4913 // push address of message | |
4914 pushptr(message.addr()); | |
4915 { Label L; call(L, relocInfo::none); bind(L); } // push eip | |
4916 pusha(); // push registers | |
4917 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32))); | |
4918 hlt(); | |
4919 } | |
4920 | |
4921 void MacroAssembler::warn(const char* msg) { | |
4922 push_CPU_state(); | |
4923 | |
4924 ExternalAddress message((address) msg); | |
4925 // push address of message | |
4926 pushptr(message.addr()); | |
4927 | |
4928 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning))); | |
4929 addl(rsp, wordSize); // discard argument | |
4930 pop_CPU_state(); | |
4931 } | |
4932 | |
4933 #else // _LP64 | |
4934 | |
4935 // 64 bit versions | |
4936 | |
4937 Address MacroAssembler::as_Address(AddressLiteral adr) { | |
4938 // amd64 always does this as a pc-rel | |
4939 // we can be absolute or disp based on the instruction type | |
4940 // jmp/call are displacements others are absolute | |
4941 assert(!adr.is_lval(), "must be rval"); | |
4942 assert(reachable(adr), "must be"); | |
4943 return Address((int32_t)(intptr_t)(adr.target() - pc()), adr.target(), adr.reloc()); | |
4944 | |
4945 } | |
4946 | |
4947 Address MacroAssembler::as_Address(ArrayAddress adr) { | |
4948 AddressLiteral base = adr.base(); | |
4949 lea(rscratch1, base); | |
4950 Address index = adr.index(); | |
4951 assert(index._disp == 0, "must not have disp"); // maybe it can? | |
4952 Address array(rscratch1, index._index, index._scale, index._disp); | |
4953 return array; | |
4954 } | |
4955 | |
4956 int MacroAssembler::biased_locking_enter(Register lock_reg, | |
4957 Register obj_reg, | |
4958 Register swap_reg, | |
4959 Register tmp_reg, | |
4960 bool swap_reg_contains_mark, | |
4961 Label& done, | |
4962 Label* slow_case, | |
4963 BiasedLockingCounters* counters) { | |
4964 assert(UseBiasedLocking, "why call this otherwise?"); | |
4965 assert(swap_reg == rax, "swap_reg must be rax for cmpxchgq"); | |
4966 assert(tmp_reg != noreg, "tmp_reg must be supplied"); | |
4967 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg); | |
4968 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout"); | |
4969 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes()); | |
4970 Address saved_mark_addr(lock_reg, 0); | |
4971 | |
4972 if (PrintBiasedLockingStatistics && counters == NULL) | |
4973 counters = BiasedLocking::counters(); | |
4974 | |
4975 // Biased locking | |
4976 // See whether the lock is currently biased toward our thread and | |
4977 // whether the epoch is still valid | |
4978 // Note that the runtime guarantees sufficient alignment of JavaThread | |
4979 // pointers to allow age to be placed into low bits | |
4980 // First check to see whether biasing is even enabled for this object | |
4981 Label cas_label; | |
4982 int null_check_offset = -1; | |
4983 if (!swap_reg_contains_mark) { | |
4984 null_check_offset = offset(); | |
4985 movq(swap_reg, mark_addr); | |
4986 } | |
4987 movq(tmp_reg, swap_reg); | |
4988 andq(tmp_reg, markOopDesc::biased_lock_mask_in_place); | |
4989 cmpq(tmp_reg, markOopDesc::biased_lock_pattern); | |
4990 jcc(Assembler::notEqual, cas_label); | |
4991 // The bias pattern is present in the object's header. Need to check | |
4992 // whether the bias owner and the epoch are both still current. | |
4993 load_prototype_header(tmp_reg, obj_reg); | |
4994 orq(tmp_reg, r15_thread); | |
4995 xorq(tmp_reg, swap_reg); | |
4996 andq(tmp_reg, ~((int) markOopDesc::age_mask_in_place)); | |
4997 if (counters != NULL) { | |
4998 cond_inc32(Assembler::zero, | |
4999 ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr())); | |
5000 } | |
0 | 5001 jcc(Assembler::equal, done); |
5002 | |
304 | 5003 Label try_revoke_bias; |
5004 Label try_rebias; | |
5005 | |
5006 // At this point we know that the header has the bias pattern and | |
5007 // that we are not the bias owner in the current epoch. We need to | |
5008 // figure out more details about the state of the header in order to | |
5009 // know what operations can be legally performed on the object's | |
5010 // header. | |
5011 | |
5012 // If the low three bits in the xor result aren't clear, that means | |
5013 // the prototype header is no longer biased and we have to revoke | |
5014 // the bias on this object. | |
5015 testq(tmp_reg, markOopDesc::biased_lock_mask_in_place); | |
5016 jcc(Assembler::notZero, try_revoke_bias); | |
5017 | |
5018 // Biasing is still enabled for this data type. See whether the | |
5019 // epoch of the current bias is still valid, meaning that the epoch | |
5020 // bits of the mark word are equal to the epoch bits of the | |
5021 // prototype header. (Note that the prototype header's epoch bits | |
5022 // only change at a safepoint.) If not, attempt to rebias the object | |
5023 // toward the current thread. Note that we must be absolutely sure | |
5024 // that the current epoch is invalid in order to do this because | |
5025 // otherwise the manipulations it performs on the mark word are | |
5026 // illegal. | |
5027 testq(tmp_reg, markOopDesc::epoch_mask_in_place); | |
5028 jcc(Assembler::notZero, try_rebias); | |
5029 | |
5030 // The epoch of the current bias is still valid but we know nothing | |
5031 // about the owner; it might be set or it might be clear. Try to | |
5032 // acquire the bias of the object using an atomic operation. If this | |
5033 // fails we will go in to the runtime to revoke the object's bias. | |
5034 // Note that we first construct the presumed unbiased header so we | |
5035 // don't accidentally blow away another thread's valid bias. | |
5036 andq(swap_reg, | |
5037 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place); | |
5038 movq(tmp_reg, swap_reg); | |
5039 orq(tmp_reg, r15_thread); | |
5040 if (os::is_MP()) { | |
5041 lock(); | |
5042 } | |
5043 cmpxchgq(tmp_reg, Address(obj_reg, 0)); | |
5044 // If the biasing toward our thread failed, this means that | |
5045 // another thread succeeded in biasing it toward itself and we | |
5046 // need to revoke that bias. The revocation will occur in the | |
5047 // interpreter runtime in the slow case. | |
5048 if (counters != NULL) { | |
5049 cond_inc32(Assembler::zero, | |
5050 ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr())); | |
5051 } | |
5052 if (slow_case != NULL) { | |
5053 jcc(Assembler::notZero, *slow_case); | |
5054 } | |
0 | 5055 jmp(done); |
5056 | |
304 | 5057 bind(try_rebias); |
5058 // At this point we know the epoch has expired, meaning that the | |
5059 // current "bias owner", if any, is actually invalid. Under these | |
5060 // circumstances _only_, we are allowed to use the current header's | |
5061 // value as the comparison value when doing the cas to acquire the | |
5062 // bias in the current epoch. In other words, we allow transfer of | |
5063 // the bias from one thread to another directly in this situation. | |
5064 // | |
5065 // FIXME: due to a lack of registers we currently blow away the age | |
5066 // bits in this situation. Should attempt to preserve them. | |
5067 load_prototype_header(tmp_reg, obj_reg); | |
5068 orq(tmp_reg, r15_thread); | |
5069 if (os::is_MP()) { | |
5070 lock(); | |
5071 } | |
5072 cmpxchgq(tmp_reg, Address(obj_reg, 0)); | |
5073 // If the biasing toward our thread failed, then another thread | |
5074 // succeeded in biasing it toward itself and we need to revoke that | |
5075 // bias. The revocation will occur in the runtime in the slow case. | |
5076 if (counters != NULL) { | |
5077 cond_inc32(Assembler::zero, | |
5078 ExternalAddress((address) counters->rebiased_lock_entry_count_addr())); | |
5079 } | |
5080 if (slow_case != NULL) { | |
5081 jcc(Assembler::notZero, *slow_case); | |
0 | 5082 } |
5083 jmp(done); | |
5084 | |
304 | 5085 bind(try_revoke_bias); |
5086 // The prototype mark in the klass doesn't have the bias bit set any | |
5087 // more, indicating that objects of this data type are not supposed | |
5088 // to be biased any more. We are going to try to reset the mark of | |
5089 // this object to the prototype value and fall through to the | |
5090 // CAS-based locking scheme. Note that if our CAS fails, it means | |
5091 // that another thread raced us for the privilege of revoking the | |
5092 // bias of this particular object, so it's okay to continue in the | |
5093 // normal locking code. | |
5094 // | |
5095 // FIXME: due to a lack of registers we currently blow away the age | |
5096 // bits in this situation. Should attempt to preserve them. | |
5097 load_prototype_header(tmp_reg, obj_reg); | |
5098 if (os::is_MP()) { | |
5099 lock(); | |
5100 } | |
5101 cmpxchgq(tmp_reg, Address(obj_reg, 0)); | |
5102 // Fall through to the normal CAS-based lock, because no matter what | |
5103 // the result of the above CAS, some thread must have succeeded in | |
5104 // removing the bias bit from the object's header. | |
5105 if (counters != NULL) { | |
5106 cond_inc32(Assembler::zero, | |
5107 ExternalAddress((address) counters->revoked_lock_entry_count_addr())); | |
5108 } | |
5109 | |
5110 bind(cas_label); | |
5111 | |
5112 return null_check_offset; | |
5113 } | |
5114 | |
5115 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) { | |
5116 Label L, E; | |
5117 | |
5118 #ifdef _WIN64 | |
5119 // Windows always allocates space for it's register args | |
5120 assert(num_args <= 4, "only register arguments supported"); | |
5121 subq(rsp, frame::arg_reg_save_area_bytes); | |
5122 #endif | |
5123 | |
5124 // Align stack if necessary | |
5125 testl(rsp, 15); | |
5126 jcc(Assembler::zero, L); | |
5127 | |
5128 subq(rsp, 8); | |
5129 { | |
5130 call(RuntimeAddress(entry_point)); | |
5131 } | |
5132 addq(rsp, 8); | |
5133 jmp(E); | |
5134 | |
5135 bind(L); | |
5136 { | |
5137 call(RuntimeAddress(entry_point)); | |
5138 } | |
5139 | |
5140 bind(E); | |
5141 | |
5142 #ifdef _WIN64 | |
5143 // restore stack pointer | |
5144 addq(rsp, frame::arg_reg_save_area_bytes); | |
5145 #endif | |
5146 | |
5147 } | |
5148 | |
5149 void MacroAssembler::cmp64(Register src1, AddressLiteral src2) { | |
5150 assert(!src2.is_lval(), "should use cmpptr"); | |
5151 | |
5152 if (reachable(src2)) { | |
5153 cmpq(src1, as_Address(src2)); | |
5154 } else { | |
5155 lea(rscratch1, src2); | |
5156 Assembler::cmpq(src1, Address(rscratch1, 0)); | |
5157 } | |
5158 } | |
5159 | |
5160 int MacroAssembler::corrected_idivq(Register reg) { | |
5161 // Full implementation of Java ldiv and lrem; checks for special | |
5162 // case as described in JVM spec., p.243 & p.271. The function | |
5163 // returns the (pc) offset of the idivl instruction - may be needed | |
5164 // for implicit exceptions. | |
5165 // | |
5166 // normal case special case | |
5167 // | |
5168 // input : rax: dividend min_long | |
5169 // reg: divisor (may not be eax/edx) -1 | |
5170 // | |
5171 // output: rax: quotient (= rax idiv reg) min_long | |
5172 // rdx: remainder (= rax irem reg) 0 | |
5173 assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register"); | |
5174 static const int64_t min_long = 0x8000000000000000; | |
5175 Label normal_case, special_case; | |
5176 | |
5177 // check for special case | |
5178 cmp64(rax, ExternalAddress((address) &min_long)); | |
5179 jcc(Assembler::notEqual, normal_case); | |
5180 xorl(rdx, rdx); // prepare rdx for possible special case (where | |
5181 // remainder = 0) | |
5182 cmpq(reg, -1); | |
5183 jcc(Assembler::equal, special_case); | |
5184 | |
5185 // handle normal case | |
5186 bind(normal_case); | |
5187 cdqq(); | |
5188 int idivq_offset = offset(); | |
5189 idivq(reg); | |
5190 | |
5191 // normal and special case exit | |
5192 bind(special_case); | |
5193 | |
5194 return idivq_offset; | |
5195 } | |
5196 | |
5197 void MacroAssembler::decrementq(Register reg, int value) { | |
5198 if (value == min_jint) { subq(reg, value); return; } | |
5199 if (value < 0) { incrementq(reg, -value); return; } | |
5200 if (value == 0) { ; return; } | |
5201 if (value == 1 && UseIncDec) { decq(reg) ; return; } | |
5202 /* else */ { subq(reg, value) ; return; } | |
5203 } | |
5204 | |
5205 void MacroAssembler::decrementq(Address dst, int value) { | |
5206 if (value == min_jint) { subq(dst, value); return; } | |
5207 if (value < 0) { incrementq(dst, -value); return; } | |
5208 if (value == 0) { ; return; } | |
5209 if (value == 1 && UseIncDec) { decq(dst) ; return; } | |
5210 /* else */ { subq(dst, value) ; return; } | |
5211 } | |
5212 | |
5213 void MacroAssembler::fat_nop() { | |
5214 // A 5 byte nop that is safe for patching (see patch_verified_entry) | |
5215 // Recommened sequence from 'Software Optimization Guide for the AMD | |
5216 // Hammer Processor' | |
5217 emit_byte(0x66); | |
5218 emit_byte(0x66); | |
5219 emit_byte(0x90); | |
5220 emit_byte(0x66); | |
5221 emit_byte(0x90); | |
5222 } | |
5223 | |
5224 void MacroAssembler::incrementq(Register reg, int value) { | |
5225 if (value == min_jint) { addq(reg, value); return; } | |
5226 if (value < 0) { decrementq(reg, -value); return; } | |
5227 if (value == 0) { ; return; } | |
5228 if (value == 1 && UseIncDec) { incq(reg) ; return; } | |
5229 /* else */ { addq(reg, value) ; return; } | |
5230 } | |
5231 | |
5232 void MacroAssembler::incrementq(Address dst, int value) { | |
5233 if (value == min_jint) { addq(dst, value); return; } | |
5234 if (value < 0) { decrementq(dst, -value); return; } | |
5235 if (value == 0) { ; return; } | |
5236 if (value == 1 && UseIncDec) { incq(dst) ; return; } | |
5237 /* else */ { addq(dst, value) ; return; } | |
5238 } | |
5239 | |
5240 // 32bit can do a case table jump in one instruction but we no longer allow the base | |
5241 // to be installed in the Address class | |
5242 void MacroAssembler::jump(ArrayAddress entry) { | |
5243 lea(rscratch1, entry.base()); | |
5244 Address dispatch = entry.index(); | |
5245 assert(dispatch._base == noreg, "must be"); | |
5246 dispatch._base = rscratch1; | |
5247 jmp(dispatch); | |
5248 } | |
5249 | |
5250 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) { | |
5251 ShouldNotReachHere(); // 64bit doesn't use two regs | |
5252 cmpq(x_lo, y_lo); | |
5253 } | |
5254 | |
5255 void MacroAssembler::lea(Register dst, AddressLiteral src) { | |
5256 mov_literal64(dst, (intptr_t)src.target(), src.rspec()); | |
5257 } | |
5258 | |
5259 void MacroAssembler::lea(Address dst, AddressLiteral adr) { | |
5260 mov_literal64(rscratch1, (intptr_t)adr.target(), adr.rspec()); | |
5261 movptr(dst, rscratch1); | |
5262 } | |
5263 | |
5264 void MacroAssembler::leave() { | |
5265 // %%% is this really better? Why not on 32bit too? | |
5266 emit_byte(0xC9); // LEAVE | |
5267 } | |
5268 | |
5269 void MacroAssembler::lneg(Register hi, Register lo) { | |
5270 ShouldNotReachHere(); // 64bit doesn't use two regs | |
5271 negq(lo); | |
5272 } | |
5273 | |
5274 void MacroAssembler::movoop(Register dst, jobject obj) { | |
5275 mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate()); | |
5276 } | |
5277 | |
5278 void MacroAssembler::movoop(Address dst, jobject obj) { | |
5279 mov_literal64(rscratch1, (intptr_t)obj, oop_Relocation::spec_for_immediate()); | |
5280 movq(dst, rscratch1); | |
5281 } | |
5282 | |
5283 void MacroAssembler::movptr(Register dst, AddressLiteral src) { | |
5284 if (src.is_lval()) { | |
5285 mov_literal64(dst, (intptr_t)src.target(), src.rspec()); | |
5286 } else { | |
5287 if (reachable(src)) { | |
5288 movq(dst, as_Address(src)); | |
5289 } else { | |
5290 lea(rscratch1, src); | |
5291 movq(dst, Address(rscratch1,0)); | |
0 | 5292 } |
304 | 5293 } |
5294 } | |
5295 | |
5296 void MacroAssembler::movptr(ArrayAddress dst, Register src) { | |
5297 movq(as_Address(dst), src); | |
5298 } | |
5299 | |
5300 void MacroAssembler::movptr(Register dst, ArrayAddress src) { | |
5301 movq(dst, as_Address(src)); | |
5302 } | |
5303 | |
5304 // src should NEVER be a real pointer. Use AddressLiteral for true pointers | |
5305 void MacroAssembler::movptr(Address dst, intptr_t src) { | |
5306 mov64(rscratch1, src); | |
5307 movq(dst, rscratch1); | |
5308 } | |
5309 | |
5310 // These are mostly for initializing NULL | |
5311 void MacroAssembler::movptr(Address dst, int32_t src) { | |
5312 movslq(dst, src); | |
5313 } | |
5314 | |
5315 void MacroAssembler::movptr(Register dst, int32_t src) { | |
5316 mov64(dst, (intptr_t)src); | |
5317 } | |
5318 | |
5319 void MacroAssembler::pushoop(jobject obj) { | |
5320 movoop(rscratch1, obj); | |
5321 push(rscratch1); | |
5322 } | |
5323 | |
5324 void MacroAssembler::pushptr(AddressLiteral src) { | |
5325 lea(rscratch1, src); | |
5326 if (src.is_lval()) { | |
5327 push(rscratch1); | |
5328 } else { | |
5329 pushq(Address(rscratch1, 0)); | |
5330 } | |
5331 } | |
5332 | |
5333 void MacroAssembler::reset_last_Java_frame(bool clear_fp, | |
5334 bool clear_pc) { | |
5335 // we must set sp to zero to clear frame | |
512
db4caa99ef11
6787106: Hotspot 32 bit build fails on platforms having different definitions for intptr_t & int32_t
xlu
parents:
420
diff
changeset
|
5336 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), NULL_WORD); |
304 | 5337 // must clear fp, so that compiled frames are not confused; it is |
5338 // possible that we need it only for debugging | |
5339 if (clear_fp) { | |
512
db4caa99ef11
6787106: Hotspot 32 bit build fails on platforms having different definitions for intptr_t & int32_t
xlu
parents:
420
diff
changeset
|
5340 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), NULL_WORD); |
304 | 5341 } |
5342 | |
5343 if (clear_pc) { | |
512
db4caa99ef11
6787106: Hotspot 32 bit build fails on platforms having different definitions for intptr_t & int32_t
xlu
parents:
420
diff
changeset
|
5344 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), NULL_WORD); |
304 | 5345 } |
5346 } | |
5347 | |
5348 void MacroAssembler::set_last_Java_frame(Register last_java_sp, | |
5349 Register last_java_fp, | |
5350 address last_java_pc) { | |
5351 // determine last_java_sp register | |
5352 if (!last_java_sp->is_valid()) { | |
5353 last_java_sp = rsp; | |
5354 } | |
5355 | |
5356 // last_java_fp is optional | |
5357 if (last_java_fp->is_valid()) { | |
5358 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), | |
5359 last_java_fp); | |
5360 } | |
5361 | |
5362 // last_java_pc is optional | |
5363 if (last_java_pc != NULL) { | |
5364 Address java_pc(r15_thread, | |
5365 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()); | |
5366 lea(rscratch1, InternalAddress(last_java_pc)); | |
5367 movptr(java_pc, rscratch1); | |
5368 } | |
5369 | |
5370 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp); | |
5371 } | |
5372 | |
5373 static void pass_arg0(MacroAssembler* masm, Register arg) { | |
5374 if (c_rarg0 != arg ) { | |
5375 masm->mov(c_rarg0, arg); | |
5376 } | |
5377 } | |
5378 | |
5379 static void pass_arg1(MacroAssembler* masm, Register arg) { | |
5380 if (c_rarg1 != arg ) { | |
5381 masm->mov(c_rarg1, arg); | |
5382 } | |
5383 } | |
5384 | |
5385 static void pass_arg2(MacroAssembler* masm, Register arg) { | |
5386 if (c_rarg2 != arg ) { | |
5387 masm->mov(c_rarg2, arg); | |
5388 } | |
5389 } | |
5390 | |
5391 static void pass_arg3(MacroAssembler* masm, Register arg) { | |
5392 if (c_rarg3 != arg ) { | |
5393 masm->mov(c_rarg3, arg); | |
5394 } | |
5395 } | |
5396 | |
5397 void MacroAssembler::stop(const char* msg) { | |
5398 address rip = pc(); | |
5399 pusha(); // get regs on stack | |
5400 lea(c_rarg0, ExternalAddress((address) msg)); | |
5401 lea(c_rarg1, InternalAddress(rip)); | |
5402 movq(c_rarg2, rsp); // pass pointer to regs array | |
5403 andq(rsp, -16); // align stack as required by ABI | |
5404 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64))); | |
5405 hlt(); | |
5406 } | |
5407 | |
5408 void MacroAssembler::warn(const char* msg) { | |
5409 push(r12); | |
5410 movq(r12, rsp); | |
5411 andq(rsp, -16); // align stack as required by push_CPU_state and call | |
5412 | |
5413 push_CPU_state(); // keeps alignment at 16 bytes | |
5414 lea(c_rarg0, ExternalAddress((address) msg)); | |
5415 call_VM_leaf(CAST_FROM_FN_PTR(address, warning), c_rarg0); | |
5416 pop_CPU_state(); | |
5417 | |
5418 movq(rsp, r12); | |
5419 pop(r12); | |
5420 } | |
5421 | |
5422 #ifndef PRODUCT | |
5423 extern "C" void findpc(intptr_t x); | |
5424 #endif | |
5425 | |
5426 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) { | |
5427 // In order to get locks to work, we need to fake a in_VM state | |
5428 if (ShowMessageBoxOnError ) { | |
5429 JavaThread* thread = JavaThread::current(); | |
5430 JavaThreadState saved_state = thread->thread_state(); | |
5431 thread->set_thread_state(_thread_in_vm); | |
5432 #ifndef PRODUCT | |
5433 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) { | |
5434 ttyLocker ttyl; | |
5435 BytecodeCounter::print(); | |
0 | 5436 } |
304 | 5437 #endif |
5438 // To see where a verify_oop failed, get $ebx+40/X for this frame. | |
5439 // XXX correct this offset for amd64 | |
5440 // This is the value of eip which points to where verify_oop will return. | |
5441 if (os::message_box(msg, "Execution stopped, print registers?")) { | |
5442 ttyLocker ttyl; | |
5443 tty->print_cr("rip = 0x%016lx", pc); | |
5444 #ifndef PRODUCT | |
5445 tty->cr(); | |
5446 findpc(pc); | |
5447 tty->cr(); | |
5448 #endif | |
5449 tty->print_cr("rax = 0x%016lx", regs[15]); | |
5450 tty->print_cr("rbx = 0x%016lx", regs[12]); | |
5451 tty->print_cr("rcx = 0x%016lx", regs[14]); | |
5452 tty->print_cr("rdx = 0x%016lx", regs[13]); | |
5453 tty->print_cr("rdi = 0x%016lx", regs[8]); | |
5454 tty->print_cr("rsi = 0x%016lx", regs[9]); | |
5455 tty->print_cr("rbp = 0x%016lx", regs[10]); | |
5456 tty->print_cr("rsp = 0x%016lx", regs[11]); | |
5457 tty->print_cr("r8 = 0x%016lx", regs[7]); | |
5458 tty->print_cr("r9 = 0x%016lx", regs[6]); | |
5459 tty->print_cr("r10 = 0x%016lx", regs[5]); | |
5460 tty->print_cr("r11 = 0x%016lx", regs[4]); | |
5461 tty->print_cr("r12 = 0x%016lx", regs[3]); | |
5462 tty->print_cr("r13 = 0x%016lx", regs[2]); | |
5463 tty->print_cr("r14 = 0x%016lx", regs[1]); | |
5464 tty->print_cr("r15 = 0x%016lx", regs[0]); | |
5465 BREAKPOINT; | |
0 | 5466 } |
304 | 5467 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state); |
5468 } else { | |
5469 ttyLocker ttyl; | |
5470 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", | |
5471 msg); | |
5472 } | |
5473 } | |
5474 | |
5475 #endif // _LP64 | |
5476 | |
5477 // Now versions that are common to 32/64 bit | |
5478 | |
5479 void MacroAssembler::addptr(Register dst, int32_t imm32) { | |
5480 LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32)); | |
5481 } | |
5482 | |
5483 void MacroAssembler::addptr(Register dst, Register src) { | |
5484 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); | |
5485 } | |
5486 | |
5487 void MacroAssembler::addptr(Address dst, Register src) { | |
5488 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); | |
5489 } | |
5490 | |
5491 void MacroAssembler::align(int modulus) { | |
5492 if (offset() % modulus != 0) { | |
5493 nop(modulus - (offset() % modulus)); | |
5494 } | |
5495 } | |
5496 | |
5497 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src) { | |
5498 andpd(dst, as_Address(src)); | |
5499 } | |
5500 | |
5501 void MacroAssembler::andptr(Register dst, int32_t imm32) { | |
5502 LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32)); | |
5503 } | |
5504 | |
5505 void MacroAssembler::atomic_incl(AddressLiteral counter_addr) { | |
5506 pushf(); | |
5507 if (os::is_MP()) | |
5508 lock(); | |
5509 incrementl(counter_addr); | |
5510 popf(); | |
5511 } | |
5512 | |
5513 // Writes to stack successive pages until offset reached to check for | |
5514 // stack overflow + shadow pages. This clobbers tmp. | |
5515 void MacroAssembler::bang_stack_size(Register size, Register tmp) { | |
5516 movptr(tmp, rsp); | |
5517 // Bang stack for total size given plus shadow page size. | |
5518 // Bang one page at a time because large size can bang beyond yellow and | |
5519 // red zones. | |
5520 Label loop; | |
5521 bind(loop); | |
5522 movl(Address(tmp, (-os::vm_page_size())), size ); | |
5523 subptr(tmp, os::vm_page_size()); | |
5524 subl(size, os::vm_page_size()); | |
5525 jcc(Assembler::greater, loop); | |
5526 | |
5527 // Bang down shadow pages too. | |
5528 // The -1 because we already subtracted 1 page. | |
5529 for (int i = 0; i< StackShadowPages-1; i++) { | |
5530 // this could be any sized move but this is can be a debugging crumb | |
5531 // so the bigger the better. | |
5532 movptr(Address(tmp, (-i*os::vm_page_size())), size ); | |
5533 } | |
5534 } | |
5535 | |
5536 void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) { | |
5537 assert(UseBiasedLocking, "why call this otherwise?"); | |
5538 | |
5539 // Check for biased locking unlock case, which is a no-op | |
5540 // Note: we do not have to check the thread ID for two reasons. | |
5541 // First, the interpreter checks for IllegalMonitorStateException at | |
5542 // a higher level. Second, if the bias was revoked while we held the | |
5543 // lock, the object could not be rebiased toward another thread, so | |
5544 // the bias bit would be clear. | |
5545 movptr(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes())); | |
5546 andptr(temp_reg, markOopDesc::biased_lock_mask_in_place); | |
5547 cmpptr(temp_reg, markOopDesc::biased_lock_pattern); | |
5548 jcc(Assembler::equal, done); | |
5549 } | |
5550 | |
5551 void MacroAssembler::c2bool(Register x) { | |
5552 // implements x == 0 ? 0 : 1 | |
5553 // note: must only look at least-significant byte of x | |
5554 // since C-style booleans are stored in one byte | |
5555 // only! (was bug) | |
5556 andl(x, 0xFF); | |
5557 setb(Assembler::notZero, x); | |
5558 } | |
5559 | |
5560 // Wouldn't need if AddressLiteral version had new name | |
5561 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) { | |
5562 Assembler::call(L, rtype); | |
5563 } | |
5564 | |
5565 void MacroAssembler::call(Register entry) { | |
5566 Assembler::call(entry); | |
5567 } | |
5568 | |
5569 void MacroAssembler::call(AddressLiteral entry) { | |
5570 if (reachable(entry)) { | |
5571 Assembler::call_literal(entry.target(), entry.rspec()); | |
5572 } else { | |
5573 lea(rscratch1, entry); | |
5574 Assembler::call(rscratch1); | |
5575 } | |
5576 } | |
5577 | |
5578 // Implementation of call_VM versions | |
5579 | |
5580 void MacroAssembler::call_VM(Register oop_result, | |
5581 address entry_point, | |
5582 bool check_exceptions) { | |
5583 Label C, E; | |
5584 call(C, relocInfo::none); | |
5585 jmp(E); | |
5586 | |
5587 bind(C); | |
5588 call_VM_helper(oop_result, entry_point, 0, check_exceptions); | |
5589 ret(0); | |
5590 | |
5591 bind(E); | |
5592 } | |
5593 | |
5594 void MacroAssembler::call_VM(Register oop_result, | |
5595 address entry_point, | |
5596 Register arg_1, | |
5597 bool check_exceptions) { | |
5598 Label C, E; | |
5599 call(C, relocInfo::none); | |
5600 jmp(E); | |
5601 | |
5602 bind(C); | |
5603 pass_arg1(this, arg_1); | |
5604 call_VM_helper(oop_result, entry_point, 1, check_exceptions); | |
5605 ret(0); | |
5606 | |
5607 bind(E); | |
5608 } | |
5609 | |
5610 void MacroAssembler::call_VM(Register oop_result, | |
5611 address entry_point, | |
5612 Register arg_1, | |
5613 Register arg_2, | |
5614 bool check_exceptions) { | |
5615 Label C, E; | |
5616 call(C, relocInfo::none); | |
5617 jmp(E); | |
5618 | |
5619 bind(C); | |
5620 | |
5621 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); | |
5622 | |
5623 pass_arg2(this, arg_2); | |
5624 pass_arg1(this, arg_1); | |
5625 call_VM_helper(oop_result, entry_point, 2, check_exceptions); | |
5626 ret(0); | |
5627 | |
5628 bind(E); | |
5629 } | |
5630 | |
5631 void MacroAssembler::call_VM(Register oop_result, | |
5632 address entry_point, | |
5633 Register arg_1, | |
5634 Register arg_2, | |
5635 Register arg_3, | |
5636 bool check_exceptions) { | |
5637 Label C, E; | |
5638 call(C, relocInfo::none); | |
5639 jmp(E); | |
5640 | |
5641 bind(C); | |
5642 | |
5643 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); | |
5644 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); | |
5645 pass_arg3(this, arg_3); | |
5646 | |
5647 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); | |
5648 pass_arg2(this, arg_2); | |
5649 | |
5650 pass_arg1(this, arg_1); | |
5651 call_VM_helper(oop_result, entry_point, 3, check_exceptions); | |
5652 ret(0); | |
5653 | |
5654 bind(E); | |
5655 } | |
5656 | |
5657 void MacroAssembler::call_VM(Register oop_result, | |
5658 Register last_java_sp, | |
5659 address entry_point, | |
5660 int number_of_arguments, | |
5661 bool check_exceptions) { | |
5662 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg); | |
5663 call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions); | |
5664 } | |
5665 | |
5666 void MacroAssembler::call_VM(Register oop_result, | |
5667 Register last_java_sp, | |
5668 address entry_point, | |
5669 Register arg_1, | |
5670 bool check_exceptions) { | |
5671 pass_arg1(this, arg_1); | |
5672 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions); | |
5673 } | |
5674 | |
5675 void MacroAssembler::call_VM(Register oop_result, | |
5676 Register last_java_sp, | |
5677 address entry_point, | |
5678 Register arg_1, | |
5679 Register arg_2, | |
5680 bool check_exceptions) { | |
5681 | |
5682 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); | |
5683 pass_arg2(this, arg_2); | |
5684 pass_arg1(this, arg_1); | |
5685 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions); | |
5686 } | |
5687 | |
5688 void MacroAssembler::call_VM(Register oop_result, | |
5689 Register last_java_sp, | |
5690 address entry_point, | |
5691 Register arg_1, | |
5692 Register arg_2, | |
5693 Register arg_3, | |
5694 bool check_exceptions) { | |
5695 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); | |
5696 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); | |
5697 pass_arg3(this, arg_3); | |
5698 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); | |
5699 pass_arg2(this, arg_2); | |
5700 pass_arg1(this, arg_1); | |
5701 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions); | |
5702 } | |
5703 | |
5704 void MacroAssembler::call_VM_base(Register oop_result, | |
5705 Register java_thread, | |
5706 Register last_java_sp, | |
5707 address entry_point, | |
5708 int number_of_arguments, | |
5709 bool check_exceptions) { | |
5710 // determine java_thread register | |
5711 if (!java_thread->is_valid()) { | |
5712 #ifdef _LP64 | |
5713 java_thread = r15_thread; | |
5714 #else | |
5715 java_thread = rdi; | |
5716 get_thread(java_thread); | |
5717 #endif // LP64 | |
5718 } | |
5719 // determine last_java_sp register | |
5720 if (!last_java_sp->is_valid()) { | |
5721 last_java_sp = rsp; | |
5722 } | |
5723 // debugging support | |
5724 assert(number_of_arguments >= 0 , "cannot have negative number of arguments"); | |
5725 LP64_ONLY(assert(java_thread == r15_thread, "unexpected register")); | |
5726 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result"); | |
5727 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp"); | |
5728 | |
5729 // push java thread (becomes first argument of C function) | |
5730 | |
5731 NOT_LP64(push(java_thread); number_of_arguments++); | |
5732 LP64_ONLY(mov(c_rarg0, r15_thread)); | |
5733 | |
5734 // set last Java frame before call | |
5735 assert(last_java_sp != rbp, "can't use ebp/rbp"); | |
5736 | |
5737 // Only interpreter should have to set fp | |
5738 set_last_Java_frame(java_thread, last_java_sp, rbp, NULL); | |
5739 | |
5740 // do the call, remove parameters | |
5741 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments); | |
5742 | |
5743 // restore the thread (cannot use the pushed argument since arguments | |
5744 // may be overwritten by C code generated by an optimizing compiler); | |
5745 // however can use the register value directly if it is callee saved. | |
5746 if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) { | |
5747 // rdi & rsi (also r15) are callee saved -> nothing to do | |
5748 #ifdef ASSERT | |
5749 guarantee(java_thread != rax, "change this code"); | |
5750 push(rax); | |
5751 { Label L; | |
5752 get_thread(rax); | |
5753 cmpptr(java_thread, rax); | |
5754 jcc(Assembler::equal, L); | |
5755 stop("MacroAssembler::call_VM_base: rdi not callee saved?"); | |
5756 bind(L); | |
0 | 5757 } |
304 | 5758 pop(rax); |
5759 #endif | |
5760 } else { | |
5761 get_thread(java_thread); | |
5762 } | |
5763 // reset last Java frame | |
5764 // Only interpreter should have to clear fp | |
5765 reset_last_Java_frame(java_thread, true, false); | |
5766 | |
5767 #ifndef CC_INTERP | |
5768 // C++ interp handles this in the interpreter | |
5769 check_and_handle_popframe(java_thread); | |
5770 check_and_handle_earlyret(java_thread); | |
5771 #endif /* CC_INTERP */ | |
5772 | |
5773 if (check_exceptions) { | |
5774 // check for pending exceptions (java_thread is set upon return) | |
5775 cmpptr(Address(java_thread, Thread::pending_exception_offset()), (int32_t) NULL_WORD); | |
5776 #ifndef _LP64 | |
5777 jump_cc(Assembler::notEqual, | |
5778 RuntimeAddress(StubRoutines::forward_exception_entry())); | |
5779 #else | |
5780 // This used to conditionally jump to forward_exception however it is | |
5781 // possible if we relocate that the branch will not reach. So we must jump | |
5782 // around so we can always reach | |
5783 | |
5784 Label ok; | |
5785 jcc(Assembler::equal, ok); | |
5786 jump(RuntimeAddress(StubRoutines::forward_exception_entry())); | |
5787 bind(ok); | |
5788 #endif // LP64 | |
5789 } | |
5790 | |
5791 // get oop result if there is one and reset the value in the thread | |
5792 if (oop_result->is_valid()) { | |
5793 movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset())); | |
512
db4caa99ef11
6787106: Hotspot 32 bit build fails on platforms having different definitions for intptr_t & int32_t
xlu
parents:
420
diff
changeset
|
5794 movptr(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD); |
304 | 5795 verify_oop(oop_result, "broken oop in call_VM_base"); |
5796 } | |
5797 } | |
5798 | |
5799 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) { | |
5800 | |
5801 // Calculate the value for last_Java_sp | |
5802 // somewhat subtle. call_VM does an intermediate call | |
5803 // which places a return address on the stack just under the | |
5804 // stack pointer as the user finsihed with it. This allows | |
5805 // use to retrieve last_Java_pc from last_Java_sp[-1]. | |
5806 // On 32bit we then have to push additional args on the stack to accomplish | |
5807 // the actual requested call. On 64bit call_VM only can use register args | |
5808 // so the only extra space is the return address that call_VM created. | |
5809 // This hopefully explains the calculations here. | |
5810 | |
5811 #ifdef _LP64 | |
5812 // We've pushed one address, correct last_Java_sp | |
5813 lea(rax, Address(rsp, wordSize)); | |
5814 #else | |
5815 lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize)); | |
5816 #endif // LP64 | |
5817 | |
5818 call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions); | |
5819 | |
5820 } | |
5821 | |
5822 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) { | |
5823 call_VM_leaf_base(entry_point, number_of_arguments); | |
5824 } | |
5825 | |
5826 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) { | |
5827 pass_arg0(this, arg_0); | |
5828 call_VM_leaf(entry_point, 1); | |
5829 } | |
5830 | |
5831 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) { | |
5832 | |
5833 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); | |
5834 pass_arg1(this, arg_1); | |
5835 pass_arg0(this, arg_0); | |
5836 call_VM_leaf(entry_point, 2); | |
5837 } | |
5838 | |
5839 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) { | |
5840 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg")); | |
5841 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); | |
5842 pass_arg2(this, arg_2); | |
5843 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); | |
5844 pass_arg1(this, arg_1); | |
5845 pass_arg0(this, arg_0); | |
5846 call_VM_leaf(entry_point, 3); | |
5847 } | |
5848 | |
5849 void MacroAssembler::check_and_handle_earlyret(Register java_thread) { | |
5850 } | |
5851 | |
5852 void MacroAssembler::check_and_handle_popframe(Register java_thread) { | |
5853 } | |
5854 | |
5855 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm) { | |
5856 if (reachable(src1)) { | |
5857 cmpl(as_Address(src1), imm); | |
5858 } else { | |
5859 lea(rscratch1, src1); | |
5860 cmpl(Address(rscratch1, 0), imm); | |
5861 } | |
5862 } | |
5863 | |
5864 void MacroAssembler::cmp32(Register src1, AddressLiteral src2) { | |
5865 assert(!src2.is_lval(), "use cmpptr"); | |
5866 if (reachable(src2)) { | |
5867 cmpl(src1, as_Address(src2)); | |
5868 } else { | |
5869 lea(rscratch1, src2); | |
5870 cmpl(src1, Address(rscratch1, 0)); | |
5871 } | |
5872 } | |
5873 | |
5874 void MacroAssembler::cmp32(Register src1, int32_t imm) { | |
5875 Assembler::cmpl(src1, imm); | |
5876 } | |
5877 | |
5878 void MacroAssembler::cmp32(Register src1, Address src2) { | |
5879 Assembler::cmpl(src1, src2); | |
5880 } | |
5881 | |
5882 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) { | |
5883 ucomisd(opr1, opr2); | |
5884 | |
5885 Label L; | |
5886 if (unordered_is_less) { | |
5887 movl(dst, -1); | |
5888 jcc(Assembler::parity, L); | |
5889 jcc(Assembler::below , L); | |
5890 movl(dst, 0); | |
5891 jcc(Assembler::equal , L); | |
5892 increment(dst); | |
5893 } else { // unordered is greater | |
5894 movl(dst, 1); | |
5895 jcc(Assembler::parity, L); | |
5896 jcc(Assembler::above , L); | |
5897 movl(dst, 0); | |
5898 jcc(Assembler::equal , L); | |
5899 decrementl(dst); | |
5900 } | |
5901 bind(L); | |
5902 } | |
5903 | |
5904 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) { | |
5905 ucomiss(opr1, opr2); | |
5906 | |
5907 Label L; | |
5908 if (unordered_is_less) { | |
5909 movl(dst, -1); | |
5910 jcc(Assembler::parity, L); | |
5911 jcc(Assembler::below , L); | |
5912 movl(dst, 0); | |
5913 jcc(Assembler::equal , L); | |
5914 increment(dst); | |
5915 } else { // unordered is greater | |
5916 movl(dst, 1); | |
5917 jcc(Assembler::parity, L); | |
5918 jcc(Assembler::above , L); | |
5919 movl(dst, 0); | |
5920 jcc(Assembler::equal , L); | |
5921 decrementl(dst); | |
5922 } | |
5923 bind(L); | |
5924 } | |
5925 | |
5926 | |
5927 void MacroAssembler::cmp8(AddressLiteral src1, int imm) { | |
5928 if (reachable(src1)) { | |
5929 cmpb(as_Address(src1), imm); | |
5930 } else { | |
5931 lea(rscratch1, src1); | |
5932 cmpb(Address(rscratch1, 0), imm); | |
5933 } | |
5934 } | |
5935 | |
5936 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2) { | |
5937 #ifdef _LP64 | |
5938 if (src2.is_lval()) { | |
5939 movptr(rscratch1, src2); | |
5940 Assembler::cmpq(src1, rscratch1); | |
5941 } else if (reachable(src2)) { | |
5942 cmpq(src1, as_Address(src2)); | |
5943 } else { | |
5944 lea(rscratch1, src2); | |
5945 Assembler::cmpq(src1, Address(rscratch1, 0)); | |
5946 } | |
5947 #else | |
5948 if (src2.is_lval()) { | |
5949 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec()); | |
5950 } else { | |
5951 cmpl(src1, as_Address(src2)); | |
5952 } | |
5953 #endif // _LP64 | |
5954 } | |
5955 | |
5956 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2) { | |
5957 assert(src2.is_lval(), "not a mem-mem compare"); | |
5958 #ifdef _LP64 | |
5959 // moves src2's literal address | |
5960 movptr(rscratch1, src2); | |
5961 Assembler::cmpq(src1, rscratch1); | |
5962 #else | |
5963 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec()); | |
5964 #endif // _LP64 | |
5965 } | |
5966 | |
5967 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr) { | |
5968 if (reachable(adr)) { | |
5969 if (os::is_MP()) | |
5970 lock(); | |
5971 cmpxchgptr(reg, as_Address(adr)); | |
5972 } else { | |
5973 lea(rscratch1, adr); | |
5974 if (os::is_MP()) | |
5975 lock(); | |
5976 cmpxchgptr(reg, Address(rscratch1, 0)); | |
5977 } | |
5978 } | |
5979 | |
5980 void MacroAssembler::cmpxchgptr(Register reg, Address adr) { | |
5981 LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr)); | |
5982 } | |
5983 | |
5984 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) { | |
5985 comisd(dst, as_Address(src)); | |
5986 } | |
5987 | |
5988 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) { | |
5989 comiss(dst, as_Address(src)); | |
5990 } | |
5991 | |
5992 | |
5993 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) { | |
5994 Condition negated_cond = negate_condition(cond); | |
5995 Label L; | |
5996 jcc(negated_cond, L); | |
5997 atomic_incl(counter_addr); | |
5998 bind(L); | |
5999 } | |
6000 | |
6001 int MacroAssembler::corrected_idivl(Register reg) { | |
6002 // Full implementation of Java idiv and irem; checks for | |
6003 // special case as described in JVM spec., p.243 & p.271. | |
6004 // The function returns the (pc) offset of the idivl | |
6005 // instruction - may be needed for implicit exceptions. | |
6006 // | |
6007 // normal case special case | |
6008 // | |
6009 // input : rax,: dividend min_int | |
6010 // reg: divisor (may not be rax,/rdx) -1 | |
6011 // | |
6012 // output: rax,: quotient (= rax, idiv reg) min_int | |
6013 // rdx: remainder (= rax, irem reg) 0 | |
6014 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register"); | |
6015 const int min_int = 0x80000000; | |
6016 Label normal_case, special_case; | |
6017 | |
6018 // check for special case | |
6019 cmpl(rax, min_int); | |
6020 jcc(Assembler::notEqual, normal_case); | |
6021 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0) | |
6022 cmpl(reg, -1); | |
6023 jcc(Assembler::equal, special_case); | |
6024 | |
6025 // handle normal case | |
6026 bind(normal_case); | |
6027 cdql(); | |
6028 int idivl_offset = offset(); | |
6029 idivl(reg); | |
6030 | |
6031 // normal and special case exit | |
6032 bind(special_case); | |
6033 | |
6034 return idivl_offset; | |
6035 } | |
6036 | |
6037 | |
6038 | |
6039 void MacroAssembler::decrementl(Register reg, int value) { | |
6040 if (value == min_jint) {subl(reg, value) ; return; } | |
6041 if (value < 0) { incrementl(reg, -value); return; } | |
6042 if (value == 0) { ; return; } | |
6043 if (value == 1 && UseIncDec) { decl(reg) ; return; } | |
6044 /* else */ { subl(reg, value) ; return; } | |
6045 } | |
6046 | |
6047 void MacroAssembler::decrementl(Address dst, int value) { | |
6048 if (value == min_jint) {subl(dst, value) ; return; } | |
6049 if (value < 0) { incrementl(dst, -value); return; } | |
6050 if (value == 0) { ; return; } | |
6051 if (value == 1 && UseIncDec) { decl(dst) ; return; } | |
6052 /* else */ { subl(dst, value) ; return; } | |
6053 } | |
6054 | |
6055 void MacroAssembler::division_with_shift (Register reg, int shift_value) { | |
6056 assert (shift_value > 0, "illegal shift value"); | |
6057 Label _is_positive; | |
6058 testl (reg, reg); | |
6059 jcc (Assembler::positive, _is_positive); | |
6060 int offset = (1 << shift_value) - 1 ; | |
6061 | |
6062 if (offset == 1) { | |
6063 incrementl(reg); | |
6064 } else { | |
6065 addl(reg, offset); | |
6066 } | |
6067 | |
6068 bind (_is_positive); | |
6069 sarl(reg, shift_value); | |
6070 } | |
6071 | |
6072 // !defined(COMPILER2) is because of stupid core builds | |
6073 #if !defined(_LP64) || defined(COMPILER1) || !defined(COMPILER2) | |
6074 void MacroAssembler::empty_FPU_stack() { | |
6075 if (VM_Version::supports_mmx()) { | |
6076 emms(); | |
6077 } else { | |
6078 for (int i = 8; i-- > 0; ) ffree(i); | |
6079 } | |
6080 } | |
6081 #endif // !LP64 || C1 || !C2 | |
6082 | |
6083 | |
6084 // Defines obj, preserves var_size_in_bytes | |
6085 void MacroAssembler::eden_allocate(Register obj, | |
6086 Register var_size_in_bytes, | |
6087 int con_size_in_bytes, | |
6088 Register t1, | |
6089 Label& slow_case) { | |
6090 assert(obj == rax, "obj must be in rax, for cmpxchg"); | |
6091 assert_different_registers(obj, var_size_in_bytes, t1); | |
362 | 6092 if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) { |
6093 jmp(slow_case); | |
304 | 6094 } else { |
362 | 6095 Register end = t1; |
6096 Label retry; | |
6097 bind(retry); | |
6098 ExternalAddress heap_top((address) Universe::heap()->top_addr()); | |
6099 movptr(obj, heap_top); | |
6100 if (var_size_in_bytes == noreg) { | |
6101 lea(end, Address(obj, con_size_in_bytes)); | |
6102 } else { | |
6103 lea(end, Address(obj, var_size_in_bytes, Address::times_1)); | |
6104 } | |
6105 // if end < obj then we wrapped around => object too long => slow case | |
6106 cmpptr(end, obj); | |
6107 jcc(Assembler::below, slow_case); | |
6108 cmpptr(end, ExternalAddress((address) Universe::heap()->end_addr())); | |
6109 jcc(Assembler::above, slow_case); | |
6110 // Compare obj with the top addr, and if still equal, store the new top addr in | |
6111 // end at the address of the top addr pointer. Sets ZF if was equal, and clears | |
6112 // it otherwise. Use lock prefix for atomicity on MPs. | |
6113 locked_cmpxchgptr(end, heap_top); | |
6114 jcc(Assembler::notEqual, retry); | |
6115 } | |
304 | 6116 } |
6117 | |
6118 void MacroAssembler::enter() { | |
6119 push(rbp); | |
6120 mov(rbp, rsp); | |
6121 } | |
0 | 6122 |
6123 void MacroAssembler::fcmp(Register tmp) { | |
6124 fcmp(tmp, 1, true, true); | |
6125 } | |
6126 | |
6127 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) { | |
6128 assert(!pop_right || pop_left, "usage error"); | |
6129 if (VM_Version::supports_cmov()) { | |
6130 assert(tmp == noreg, "unneeded temp"); | |
6131 if (pop_left) { | |
6132 fucomip(index); | |
6133 } else { | |
6134 fucomi(index); | |
6135 } | |
6136 if (pop_right) { | |
6137 fpop(); | |
6138 } | |
6139 } else { | |
6140 assert(tmp != noreg, "need temp"); | |
6141 if (pop_left) { | |
6142 if (pop_right) { | |
6143 fcompp(); | |
6144 } else { | |
6145 fcomp(index); | |
6146 } | |
6147 } else { | |
6148 fcom(index); | |
6149 } | |
6150 // convert FPU condition into eflags condition via rax, | |
6151 save_rax(tmp); | |
6152 fwait(); fnstsw_ax(); | |
6153 sahf(); | |
6154 restore_rax(tmp); | |
6155 } | |
6156 // condition codes set as follows: | |
6157 // | |
6158 // CF (corresponds to C0) if x < y | |
6159 // PF (corresponds to C2) if unordered | |
6160 // ZF (corresponds to C3) if x = y | |
6161 } | |
6162 | |
6163 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) { | |
6164 fcmp2int(dst, unordered_is_less, 1, true, true); | |
6165 } | |
6166 | |
6167 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) { | |
6168 fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right); | |
6169 Label L; | |
6170 if (unordered_is_less) { | |
6171 movl(dst, -1); | |
6172 jcc(Assembler::parity, L); | |
6173 jcc(Assembler::below , L); | |
6174 movl(dst, 0); | |
6175 jcc(Assembler::equal , L); | |
6176 increment(dst); | |
6177 } else { // unordered is greater | |
6178 movl(dst, 1); | |
6179 jcc(Assembler::parity, L); | |
6180 jcc(Assembler::above , L); | |
6181 movl(dst, 0); | |
6182 jcc(Assembler::equal , L); | |
304 | 6183 decrementl(dst); |
0 | 6184 } |
6185 bind(L); | |
6186 } | |
6187 | |
304 | 6188 void MacroAssembler::fld_d(AddressLiteral src) { |
6189 fld_d(as_Address(src)); | |
6190 } | |
6191 | |
6192 void MacroAssembler::fld_s(AddressLiteral src) { | |
6193 fld_s(as_Address(src)); | |
6194 } | |
6195 | |
6196 void MacroAssembler::fld_x(AddressLiteral src) { | |
6197 Assembler::fld_x(as_Address(src)); | |
6198 } | |
6199 | |
6200 void MacroAssembler::fldcw(AddressLiteral src) { | |
6201 Assembler::fldcw(as_Address(src)); | |
6202 } | |
0 | 6203 |
6204 void MacroAssembler::fpop() { | |
6205 ffree(); | |
6206 fincstp(); | |
6207 } | |
6208 | |
304 | 6209 void MacroAssembler::fremr(Register tmp) { |
6210 save_rax(tmp); | |
6211 { Label L; | |
6212 bind(L); | |
6213 fprem(); | |
6214 fwait(); fnstsw_ax(); | |
6215 #ifdef _LP64 | |
6216 testl(rax, 0x400); | |
6217 jcc(Assembler::notEqual, L); | |
6218 #else | |
6219 sahf(); | |
6220 jcc(Assembler::parity, L); | |
6221 #endif // _LP64 | |
6222 } | |
6223 restore_rax(tmp); | |
6224 // Result is in ST0. | |
6225 // Note: fxch & fpop to get rid of ST1 | |
6226 // (otherwise FPU stack could overflow eventually) | |
6227 fxch(1); | |
6228 fpop(); | |
6229 } | |
6230 | |
6231 | |
6232 void MacroAssembler::incrementl(AddressLiteral dst) { | |
6233 if (reachable(dst)) { | |
6234 incrementl(as_Address(dst)); | |
0 | 6235 } else { |
304 | 6236 lea(rscratch1, dst); |
6237 incrementl(Address(rscratch1, 0)); | |
6238 } | |
6239 } | |
6240 | |
6241 void MacroAssembler::incrementl(ArrayAddress dst) { | |
6242 incrementl(as_Address(dst)); | |
6243 } | |
6244 | |
6245 void MacroAssembler::incrementl(Register reg, int value) { | |
6246 if (value == min_jint) {addl(reg, value) ; return; } | |
6247 if (value < 0) { decrementl(reg, -value); return; } | |
6248 if (value == 0) { ; return; } | |
6249 if (value == 1 && UseIncDec) { incl(reg) ; return; } | |
6250 /* else */ { addl(reg, value) ; return; } | |
6251 } | |
6252 | |
6253 void MacroAssembler::incrementl(Address dst, int value) { | |
6254 if (value == min_jint) {addl(dst, value) ; return; } | |
6255 if (value < 0) { decrementl(dst, -value); return; } | |
6256 if (value == 0) { ; return; } | |
6257 if (value == 1 && UseIncDec) { incl(dst) ; return; } | |
6258 /* else */ { addl(dst, value) ; return; } | |
6259 } | |
6260 | |
6261 void MacroAssembler::jump(AddressLiteral dst) { | |
6262 if (reachable(dst)) { | |
6263 jmp_literal(dst.target(), dst.rspec()); | |
6264 } else { | |
6265 lea(rscratch1, dst); | |
6266 jmp(rscratch1); | |
6267 } | |
6268 } | |
6269 | |
6270 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst) { | |
6271 if (reachable(dst)) { | |
6272 InstructionMark im(this); | |
6273 relocate(dst.reloc()); | |
6274 const int short_size = 2; | |
6275 const int long_size = 6; | |
6276 int offs = (intptr_t)dst.target() - ((intptr_t)_code_pos); | |
6277 if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) { | |
6278 // 0111 tttn #8-bit disp | |
6279 emit_byte(0x70 | cc); | |
6280 emit_byte((offs - short_size) & 0xFF); | |
6281 } else { | |
6282 // 0000 1111 1000 tttn #32-bit disp | |
6283 emit_byte(0x0F); | |
6284 emit_byte(0x80 | cc); | |
6285 emit_long(offs - long_size); | |
6286 } | |
0 | 6287 } else { |
304 | 6288 #ifdef ASSERT |
6289 warning("reversing conditional branch"); | |
6290 #endif /* ASSERT */ | |
6291 Label skip; | |
6292 jccb(reverse[cc], skip); | |
6293 lea(rscratch1, dst); | |
6294 Assembler::jmp(rscratch1); | |
6295 bind(skip); | |
6296 } | |
6297 } | |
6298 | |
6299 void MacroAssembler::ldmxcsr(AddressLiteral src) { | |
6300 if (reachable(src)) { | |
6301 Assembler::ldmxcsr(as_Address(src)); | |
6302 } else { | |
6303 lea(rscratch1, src); | |
6304 Assembler::ldmxcsr(Address(rscratch1, 0)); | |
6305 } | |
6306 } | |
6307 | |
6308 int MacroAssembler::load_signed_byte(Register dst, Address src) { | |
6309 int off; | |
6310 if (LP64_ONLY(true ||) VM_Version::is_P6()) { | |
6311 off = offset(); | |
6312 movsbl(dst, src); // movsxb | |
6313 } else { | |
6314 off = load_unsigned_byte(dst, src); | |
6315 shll(dst, 24); | |
6316 sarl(dst, 24); | |
6317 } | |
6318 return off; | |
6319 } | |
6320 | |
622
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
606
diff
changeset
|
6321 // Note: load_signed_short used to be called load_signed_word. |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
606
diff
changeset
|
6322 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
606
diff
changeset
|
6323 // manual, which means 16 bits, that usage is found nowhere in HotSpot code. |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
606
diff
changeset
|
6324 // The term "word" in HotSpot means a 32- or 64-bit machine word. |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
606
diff
changeset
|
6325 int MacroAssembler::load_signed_short(Register dst, Address src) { |
304 | 6326 int off; |
6327 if (LP64_ONLY(true ||) VM_Version::is_P6()) { | |
6328 // This is dubious to me since it seems safe to do a signed 16 => 64 bit | |
6329 // version but this is what 64bit has always done. This seems to imply | |
6330 // that users are only using 32bits worth. | |
6331 off = offset(); | |
6332 movswl(dst, src); // movsxw | |
6333 } else { | |
622
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
606
diff
changeset
|
6334 off = load_unsigned_short(dst, src); |
304 | 6335 shll(dst, 16); |
6336 sarl(dst, 16); | |
6337 } | |
6338 return off; | |
6339 } | |
6340 | |
6341 int MacroAssembler::load_unsigned_byte(Register dst, Address src) { | |
6342 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16, | |
6343 // and "3.9 Partial Register Penalties", p. 22). | |
6344 int off; | |
6345 if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) { | |
6346 off = offset(); | |
6347 movzbl(dst, src); // movzxb | |
6348 } else { | |
6349 xorl(dst, dst); | |
6350 off = offset(); | |
6351 movb(dst, src); | |
6352 } | |
6353 return off; | |
6354 } | |
6355 | |
622
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
606
diff
changeset
|
6356 // Note: load_unsigned_short used to be called load_unsigned_word. |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
606
diff
changeset
|
6357 int MacroAssembler::load_unsigned_short(Register dst, Address src) { |
304 | 6358 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16, |
6359 // and "3.9 Partial Register Penalties", p. 22). | |
6360 int off; | |
6361 if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) { | |
6362 off = offset(); | |
6363 movzwl(dst, src); // movzxw | |
6364 } else { | |
6365 xorl(dst, dst); | |
6366 off = offset(); | |
6367 movw(dst, src); | |
6368 } | |
6369 return off; | |
6370 } | |
6371 | |
622
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
606
diff
changeset
|
6372 void MacroAssembler::load_sized_value(Register dst, Address src, |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
606
diff
changeset
|
6373 int size_in_bytes, bool is_signed) { |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
606
diff
changeset
|
6374 switch (size_in_bytes ^ (is_signed ? -1 : 0)) { |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
606
diff
changeset
|
6375 #ifndef _LP64 |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
606
diff
changeset
|
6376 // For case 8, caller is responsible for manually loading |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
606
diff
changeset
|
6377 // the second word into another register. |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
606
diff
changeset
|
6378 case ~8: // fall through: |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
606
diff
changeset
|
6379 case 8: movl( dst, src ); break; |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
606
diff
changeset
|
6380 #else |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
606
diff
changeset
|
6381 case ~8: // fall through: |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
606
diff
changeset
|
6382 case 8: movq( dst, src ); break; |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
606
diff
changeset
|
6383 #endif |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
606
diff
changeset
|
6384 case ~4: // fall through: |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
606
diff
changeset
|
6385 case 4: movl( dst, src ); break; |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
606
diff
changeset
|
6386 case ~2: load_signed_short( dst, src ); break; |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
606
diff
changeset
|
6387 case 2: load_unsigned_short( dst, src ); break; |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
606
diff
changeset
|
6388 case ~1: load_signed_byte( dst, src ); break; |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
606
diff
changeset
|
6389 case 1: load_unsigned_byte( dst, src ); break; |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
606
diff
changeset
|
6390 default: ShouldNotReachHere(); |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
606
diff
changeset
|
6391 } |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
606
diff
changeset
|
6392 } |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
606
diff
changeset
|
6393 |
304 | 6394 void MacroAssembler::mov32(AddressLiteral dst, Register src) { |
6395 if (reachable(dst)) { | |
6396 movl(as_Address(dst), src); | |
6397 } else { | |
6398 lea(rscratch1, dst); | |
6399 movl(Address(rscratch1, 0), src); | |
6400 } | |
6401 } | |
6402 | |
6403 void MacroAssembler::mov32(Register dst, AddressLiteral src) { | |
6404 if (reachable(src)) { | |
6405 movl(dst, as_Address(src)); | |
6406 } else { | |
6407 lea(rscratch1, src); | |
6408 movl(dst, Address(rscratch1, 0)); | |
6409 } | |
0 | 6410 } |
6411 | |
6412 // C++ bool manipulation | |
6413 | |
6414 void MacroAssembler::movbool(Register dst, Address src) { | |
6415 if(sizeof(bool) == 1) | |
6416 movb(dst, src); | |
6417 else if(sizeof(bool) == 2) | |
6418 movw(dst, src); | |
6419 else if(sizeof(bool) == 4) | |
6420 movl(dst, src); | |
6421 else | |
6422 // unsupported | |
6423 ShouldNotReachHere(); | |
6424 } | |
6425 | |
6426 void MacroAssembler::movbool(Address dst, bool boolconst) { | |
6427 if(sizeof(bool) == 1) | |
6428 movb(dst, (int) boolconst); | |
6429 else if(sizeof(bool) == 2) | |
6430 movw(dst, (int) boolconst); | |
6431 else if(sizeof(bool) == 4) | |
6432 movl(dst, (int) boolconst); | |
6433 else | |
6434 // unsupported | |
6435 ShouldNotReachHere(); | |
6436 } | |
6437 | |
6438 void MacroAssembler::movbool(Address dst, Register src) { | |
6439 if(sizeof(bool) == 1) | |
6440 movb(dst, src); | |
6441 else if(sizeof(bool) == 2) | |
6442 movw(dst, src); | |
6443 else if(sizeof(bool) == 4) | |
6444 movl(dst, src); | |
6445 else | |
6446 // unsupported | |
6447 ShouldNotReachHere(); | |
6448 } | |
6449 | |
304 | 6450 void MacroAssembler::movbyte(ArrayAddress dst, int src) { |
6451 movb(as_Address(dst), src); | |
6452 } | |
6453 | |
6454 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src) { | |
6455 if (reachable(src)) { | |
6456 if (UseXmmLoadAndClearUpper) { | |
6457 movsd (dst, as_Address(src)); | |
6458 } else { | |
6459 movlpd(dst, as_Address(src)); | |
6460 } | |
6461 } else { | |
6462 lea(rscratch1, src); | |
6463 if (UseXmmLoadAndClearUpper) { | |
6464 movsd (dst, Address(rscratch1, 0)); | |
6465 } else { | |
6466 movlpd(dst, Address(rscratch1, 0)); | |
6467 } | |
6468 } | |
6469 } | |
6470 | |
6471 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src) { | |
6472 if (reachable(src)) { | |
6473 movss(dst, as_Address(src)); | |
6474 } else { | |
6475 lea(rscratch1, src); | |
6476 movss(dst, Address(rscratch1, 0)); | |
6477 } | |
6478 } | |
6479 | |
6480 void MacroAssembler::movptr(Register dst, Register src) { | |
6481 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); | |
6482 } | |
6483 | |
6484 void MacroAssembler::movptr(Register dst, Address src) { | |
6485 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); | |
6486 } | |
6487 | |
6488 // src should NEVER be a real pointer. Use AddressLiteral for true pointers | |
6489 void MacroAssembler::movptr(Register dst, intptr_t src) { | |
6490 LP64_ONLY(mov64(dst, src)) NOT_LP64(movl(dst, src)); | |
6491 } | |
6492 | |
6493 void MacroAssembler::movptr(Address dst, Register src) { | |
6494 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); | |
6495 } | |
6496 | |
6497 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) { | |
6498 if (reachable(src)) { | |
6499 movss(dst, as_Address(src)); | |
6500 } else { | |
6501 lea(rscratch1, src); | |
6502 movss(dst, Address(rscratch1, 0)); | |
6503 } | |
6504 } | |
6505 | |
6506 void MacroAssembler::null_check(Register reg, int offset) { | |
6507 if (needs_explicit_null_check(offset)) { | |
6508 // provoke OS NULL exception if reg = NULL by | |
6509 // accessing M[reg] w/o changing any (non-CC) registers | |
6510 // NOTE: cmpl is plenty here to provoke a segv | |
6511 cmpptr(rax, Address(reg, 0)); | |
6512 // Note: should probably use testl(rax, Address(reg, 0)); | |
6513 // may be shorter code (however, this version of | |
6514 // testl needs to be implemented first) | |
6515 } else { | |
6516 // nothing to do, (later) access of M[reg + offset] | |
6517 // will provoke OS NULL exception if reg = NULL | |
6518 } | |
6519 } | |
6520 | |
6521 void MacroAssembler::os_breakpoint() { | |
6522 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability | |
6523 // (e.g., MSVC can't call ps() otherwise) | |
6524 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint))); | |
6525 } | |
6526 | |
6527 void MacroAssembler::pop_CPU_state() { | |
6528 pop_FPU_state(); | |
6529 pop_IU_state(); | |
6530 } | |
6531 | |
6532 void MacroAssembler::pop_FPU_state() { | |
6533 NOT_LP64(frstor(Address(rsp, 0));) | |
6534 LP64_ONLY(fxrstor(Address(rsp, 0));) | |
6535 addptr(rsp, FPUStateSizeInWords * wordSize); | |
6536 } | |
6537 | |
6538 void MacroAssembler::pop_IU_state() { | |
6539 popa(); | |
6540 LP64_ONLY(addq(rsp, 8)); | |
6541 popf(); | |
6542 } | |
6543 | |
6544 // Save Integer and Float state | |
6545 // Warning: Stack must be 16 byte aligned (64bit) | |
6546 void MacroAssembler::push_CPU_state() { | |
6547 push_IU_state(); | |
6548 push_FPU_state(); | |
6549 } | |
6550 | |
6551 void MacroAssembler::push_FPU_state() { | |
6552 subptr(rsp, FPUStateSizeInWords * wordSize); | |
6553 #ifndef _LP64 | |
6554 fnsave(Address(rsp, 0)); | |
6555 fwait(); | |
6556 #else | |
6557 fxsave(Address(rsp, 0)); | |
6558 #endif // LP64 | |
6559 } | |
6560 | |
6561 void MacroAssembler::push_IU_state() { | |
6562 // Push flags first because pusha kills them | |
6563 pushf(); | |
6564 // Make sure rsp stays 16-byte aligned | |
6565 LP64_ONLY(subq(rsp, 8)); | |
6566 pusha(); | |
6567 } | |
6568 | |
6569 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp, bool clear_pc) { | |
6570 // determine java_thread register | |
6571 if (!java_thread->is_valid()) { | |
6572 java_thread = rdi; | |
6573 get_thread(java_thread); | |
6574 } | |
6575 // we must set sp to zero to clear frame | |
512
db4caa99ef11
6787106: Hotspot 32 bit build fails on platforms having different definitions for intptr_t & int32_t
xlu
parents:
420
diff
changeset
|
6576 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), NULL_WORD); |
304 | 6577 if (clear_fp) { |
512
db4caa99ef11
6787106: Hotspot 32 bit build fails on platforms having different definitions for intptr_t & int32_t
xlu
parents:
420
diff
changeset
|
6578 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), NULL_WORD); |
304 | 6579 } |
6580 | |
6581 if (clear_pc) | |
512
db4caa99ef11
6787106: Hotspot 32 bit build fails on platforms having different definitions for intptr_t & int32_t
xlu
parents:
420
diff
changeset
|
6582 movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), NULL_WORD); |
304 | 6583 |
6584 } | |
6585 | |
6586 void MacroAssembler::restore_rax(Register tmp) { | |
6587 if (tmp == noreg) pop(rax); | |
6588 else if (tmp != rax) mov(rax, tmp); | |
6589 } | |
6590 | |
6591 void MacroAssembler::round_to(Register reg, int modulus) { | |
6592 addptr(reg, modulus - 1); | |
6593 andptr(reg, -modulus); | |
6594 } | |
6595 | |
6596 void MacroAssembler::save_rax(Register tmp) { | |
6597 if (tmp == noreg) push(rax); | |
6598 else if (tmp != rax) mov(tmp, rax); | |
6599 } | |
6600 | |
6601 // Write serialization page so VM thread can do a pseudo remote membar. | |
6602 // We use the current thread pointer to calculate a thread specific | |
6603 // offset to write to within the page. This minimizes bus traffic | |
6604 // due to cache line collision. | |
6605 void MacroAssembler::serialize_memory(Register thread, Register tmp) { | |
6606 movl(tmp, thread); | |
6607 shrl(tmp, os::get_serialize_page_shift_count()); | |
6608 andl(tmp, (os::vm_page_size() - sizeof(int))); | |
6609 | |
6610 Address index(noreg, tmp, Address::times_1); | |
6611 ExternalAddress page(os::get_memory_serialize_page()); | |
6612 | |
606
19962e74284f
6811384: MacroAssembler::serialize_memory may touch next page on amd64
never
parents:
520
diff
changeset
|
6613 // Size of store must match masking code above |
19962e74284f
6811384: MacroAssembler::serialize_memory may touch next page on amd64
never
parents:
520
diff
changeset
|
6614 movl(as_Address(ArrayAddress(page, index)), tmp); |
304 | 6615 } |
6616 | |
6617 // Calls to C land | |
6618 // | |
6619 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded | |
6620 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp | |
6621 // has to be reset to 0. This is required to allow proper stack traversal. | |
6622 void MacroAssembler::set_last_Java_frame(Register java_thread, | |
6623 Register last_java_sp, | |
6624 Register last_java_fp, | |
6625 address last_java_pc) { | |
6626 // determine java_thread register | |
6627 if (!java_thread->is_valid()) { | |
6628 java_thread = rdi; | |
6629 get_thread(java_thread); | |
6630 } | |
6631 // determine last_java_sp register | |
6632 if (!last_java_sp->is_valid()) { | |
6633 last_java_sp = rsp; | |
6634 } | |
6635 | |
6636 // last_java_fp is optional | |
6637 | |
6638 if (last_java_fp->is_valid()) { | |
6639 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp); | |
6640 } | |
6641 | |
6642 // last_java_pc is optional | |
6643 | |
6644 if (last_java_pc != NULL) { | |
6645 lea(Address(java_thread, | |
6646 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()), | |
6647 InternalAddress(last_java_pc)); | |
6648 | |
6649 } | |
6650 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp); | |
6651 } | |
6652 | |
6653 void MacroAssembler::shlptr(Register dst, int imm8) { | |
6654 LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8)); | |
6655 } | |
6656 | |
6657 void MacroAssembler::shrptr(Register dst, int imm8) { | |
6658 LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8)); | |
6659 } | |
6660 | |
6661 void MacroAssembler::sign_extend_byte(Register reg) { | |
6662 if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) { | |
6663 movsbl(reg, reg); // movsxb | |
6664 } else { | |
6665 shll(reg, 24); | |
6666 sarl(reg, 24); | |
6667 } | |
6668 } | |
6669 | |
6670 void MacroAssembler::sign_extend_short(Register reg) { | |
6671 if (LP64_ONLY(true ||) VM_Version::is_P6()) { | |
6672 movswl(reg, reg); // movsxw | |
6673 } else { | |
6674 shll(reg, 16); | |
6675 sarl(reg, 16); | |
6676 } | |
6677 } | |
6678 | |
362 | 6679 ////////////////////////////////////////////////////////////////////////////////// |
6680 #ifndef SERIALGC | |
6681 | |
6682 void MacroAssembler::g1_write_barrier_pre(Register obj, | |
6683 #ifndef _LP64 | |
6684 Register thread, | |
6685 #endif | |
6686 Register tmp, | |
6687 Register tmp2, | |
6688 bool tosca_live) { | |
6689 LP64_ONLY(Register thread = r15_thread;) | |
6690 Address in_progress(thread, in_bytes(JavaThread::satb_mark_queue_offset() + | |
6691 PtrQueue::byte_offset_of_active())); | |
6692 | |
6693 Address index(thread, in_bytes(JavaThread::satb_mark_queue_offset() + | |
6694 PtrQueue::byte_offset_of_index())); | |
6695 Address buffer(thread, in_bytes(JavaThread::satb_mark_queue_offset() + | |
6696 PtrQueue::byte_offset_of_buf())); | |
6697 | |
6698 | |
6699 Label done; | |
6700 Label runtime; | |
6701 | |
6702 // if (!marking_in_progress) goto done; | |
6703 if (in_bytes(PtrQueue::byte_width_of_active()) == 4) { | |
6704 cmpl(in_progress, 0); | |
6705 } else { | |
6706 assert(in_bytes(PtrQueue::byte_width_of_active()) == 1, "Assumption"); | |
6707 cmpb(in_progress, 0); | |
6708 } | |
6709 jcc(Assembler::equal, done); | |
6710 | |
6711 // if (x.f == NULL) goto done; | |
6712 cmpptr(Address(obj, 0), NULL_WORD); | |
6713 jcc(Assembler::equal, done); | |
6714 | |
6715 // Can we store original value in the thread's buffer? | |
6716 | |
6717 LP64_ONLY(movslq(tmp, index);) | |
6718 movptr(tmp2, Address(obj, 0)); | |
6719 #ifdef _LP64 | |
6720 cmpq(tmp, 0); | |
6721 #else | |
6722 cmpl(index, 0); | |
6723 #endif | |
6724 jcc(Assembler::equal, runtime); | |
6725 #ifdef _LP64 | |
6726 subq(tmp, wordSize); | |
6727 movl(index, tmp); | |
6728 addq(tmp, buffer); | |
6729 #else | |
6730 subl(index, wordSize); | |
6731 movl(tmp, buffer); | |
6732 addl(tmp, index); | |
6733 #endif | |
6734 movptr(Address(tmp, 0), tmp2); | |
6735 jmp(done); | |
6736 bind(runtime); | |
6737 // save the live input values | |
6738 if(tosca_live) push(rax); | |
6739 push(obj); | |
6740 #ifdef _LP64 | |
6741 movq(c_rarg0, Address(obj, 0)); | |
6742 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), c_rarg0, r15_thread); | |
6743 #else | |
6744 push(thread); | |
6745 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), tmp2, thread); | |
6746 pop(thread); | |
6747 #endif | |
6748 pop(obj); | |
6749 if(tosca_live) pop(rax); | |
6750 bind(done); | |
6751 | |
6752 } | |
6753 | |
6754 void MacroAssembler::g1_write_barrier_post(Register store_addr, | |
6755 Register new_val, | |
6756 #ifndef _LP64 | |
6757 Register thread, | |
6758 #endif | |
6759 Register tmp, | |
6760 Register tmp2) { | |
6761 | |
6762 LP64_ONLY(Register thread = r15_thread;) | |
6763 Address queue_index(thread, in_bytes(JavaThread::dirty_card_queue_offset() + | |
6764 PtrQueue::byte_offset_of_index())); | |
6765 Address buffer(thread, in_bytes(JavaThread::dirty_card_queue_offset() + | |
6766 PtrQueue::byte_offset_of_buf())); | |
6767 BarrierSet* bs = Universe::heap()->barrier_set(); | |
6768 CardTableModRefBS* ct = (CardTableModRefBS*)bs; | |
6769 Label done; | |
6770 Label runtime; | |
6771 | |
6772 // Does store cross heap regions? | |
6773 | |
6774 movptr(tmp, store_addr); | |
6775 xorptr(tmp, new_val); | |
6776 shrptr(tmp, HeapRegion::LogOfHRGrainBytes); | |
6777 jcc(Assembler::equal, done); | |
6778 | |
6779 // crosses regions, storing NULL? | |
6780 | |
6781 cmpptr(new_val, (int32_t) NULL_WORD); | |
6782 jcc(Assembler::equal, done); | |
6783 | |
6784 // storing region crossing non-NULL, is card already dirty? | |
6785 | |
6786 ExternalAddress cardtable((address) ct->byte_map_base); | |
6787 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code"); | |
6788 #ifdef _LP64 | |
6789 const Register card_addr = tmp; | |
6790 | |
6791 movq(card_addr, store_addr); | |
6792 shrq(card_addr, CardTableModRefBS::card_shift); | |
6793 | |
6794 lea(tmp2, cardtable); | |
6795 | |
6796 // get the address of the card | |
6797 addq(card_addr, tmp2); | |
6798 #else | |
6799 const Register card_index = tmp; | |
6800 | |
6801 movl(card_index, store_addr); | |
6802 shrl(card_index, CardTableModRefBS::card_shift); | |
6803 | |
6804 Address index(noreg, card_index, Address::times_1); | |
6805 const Register card_addr = tmp; | |
6806 lea(card_addr, as_Address(ArrayAddress(cardtable, index))); | |
6807 #endif | |
6808 cmpb(Address(card_addr, 0), 0); | |
6809 jcc(Assembler::equal, done); | |
6810 | |
6811 // storing a region crossing, non-NULL oop, card is clean. | |
6812 // dirty card and log. | |
6813 | |
6814 movb(Address(card_addr, 0), 0); | |
6815 | |
6816 cmpl(queue_index, 0); | |
6817 jcc(Assembler::equal, runtime); | |
6818 subl(queue_index, wordSize); | |
6819 movptr(tmp2, buffer); | |
6820 #ifdef _LP64 | |
6821 movslq(rscratch1, queue_index); | |
6822 addq(tmp2, rscratch1); | |
6823 movq(Address(tmp2, 0), card_addr); | |
6824 #else | |
6825 addl(tmp2, queue_index); | |
6826 movl(Address(tmp2, 0), card_index); | |
6827 #endif | |
6828 jmp(done); | |
6829 | |
6830 bind(runtime); | |
6831 // save the live input values | |
6832 push(store_addr); | |
6833 push(new_val); | |
6834 #ifdef _LP64 | |
6835 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, r15_thread); | |
6836 #else | |
6837 push(thread); | |
6838 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, thread); | |
6839 pop(thread); | |
6840 #endif | |
6841 pop(new_val); | |
6842 pop(store_addr); | |
6843 | |
6844 bind(done); | |
6845 | |
6846 } | |
6847 | |
6848 #endif // SERIALGC | |
6849 ////////////////////////////////////////////////////////////////////////////////// | |
6850 | |
6851 | |
304 | 6852 void MacroAssembler::store_check(Register obj) { |
6853 // Does a store check for the oop in register obj. The content of | |
6854 // register obj is destroyed afterwards. | |
6855 store_check_part_1(obj); | |
6856 store_check_part_2(obj); | |
6857 } | |
6858 | |
6859 void MacroAssembler::store_check(Register obj, Address dst) { | |
6860 store_check(obj); | |
6861 } | |
6862 | |
6863 | |
6864 // split the store check operation so that other instructions can be scheduled inbetween | |
6865 void MacroAssembler::store_check_part_1(Register obj) { | |
6866 BarrierSet* bs = Universe::heap()->barrier_set(); | |
6867 assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind"); | |
6868 shrptr(obj, CardTableModRefBS::card_shift); | |
6869 } | |
6870 | |
6871 void MacroAssembler::store_check_part_2(Register obj) { | |
6872 BarrierSet* bs = Universe::heap()->barrier_set(); | |
6873 assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind"); | |
6874 CardTableModRefBS* ct = (CardTableModRefBS*)bs; | |
6875 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code"); | |
6876 | |
6877 // The calculation for byte_map_base is as follows: | |
6878 // byte_map_base = _byte_map - (uintptr_t(low_bound) >> card_shift); | |
6879 // So this essentially converts an address to a displacement and | |
6880 // it will never need to be relocated. On 64bit however the value may be too | |
6881 // large for a 32bit displacement | |
6882 | |
6883 intptr_t disp = (intptr_t) ct->byte_map_base; | |
6884 if (is_simm32(disp)) { | |
6885 Address cardtable(noreg, obj, Address::times_1, disp); | |
6886 movb(cardtable, 0); | |
6887 } else { | |
6888 // By doing it as an ExternalAddress disp could be converted to a rip-relative | |
6889 // displacement and done in a single instruction given favorable mapping and | |
6890 // a smarter version of as_Address. Worst case it is two instructions which | |
6891 // is no worse off then loading disp into a register and doing as a simple | |
6892 // Address() as above. | |
6893 // We can't do as ExternalAddress as the only style since if disp == 0 we'll | |
6894 // assert since NULL isn't acceptable in a reloci (see 6644928). In any case | |
6895 // in some cases we'll get a single instruction version. | |
6896 | |
6897 ExternalAddress cardtable((address)disp); | |
6898 Address index(noreg, obj, Address::times_1); | |
6899 movb(as_Address(ArrayAddress(cardtable, index)), 0); | |
6900 } | |
6901 } | |
6902 | |
6903 void MacroAssembler::subptr(Register dst, int32_t imm32) { | |
6904 LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32)); | |
6905 } | |
6906 | |
6907 void MacroAssembler::subptr(Register dst, Register src) { | |
6908 LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); | |
6909 } | |
6910 | |
6911 void MacroAssembler::test32(Register src1, AddressLiteral src2) { | |
6912 // src2 must be rval | |
6913 | |
6914 if (reachable(src2)) { | |
6915 testl(src1, as_Address(src2)); | |
6916 } else { | |
6917 lea(rscratch1, src2); | |
6918 testl(src1, Address(rscratch1, 0)); | |
6919 } | |
6920 } | |
6921 | |
6922 // C++ bool manipulation | |
0 | 6923 void MacroAssembler::testbool(Register dst) { |
6924 if(sizeof(bool) == 1) | |
304 | 6925 testb(dst, 0xff); |
0 | 6926 else if(sizeof(bool) == 2) { |
6927 // testw implementation needed for two byte bools | |
6928 ShouldNotReachHere(); | |
6929 } else if(sizeof(bool) == 4) | |
6930 testl(dst, dst); | |
6931 else | |
6932 // unsupported | |
6933 ShouldNotReachHere(); | |
6934 } | |
6935 | |
304 | 6936 void MacroAssembler::testptr(Register dst, Register src) { |
6937 LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src)); | |
6938 } | |
6939 | |
6940 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes. | |
6941 void MacroAssembler::tlab_allocate(Register obj, | |
6942 Register var_size_in_bytes, | |
6943 int con_size_in_bytes, | |
6944 Register t1, | |
6945 Register t2, | |
6946 Label& slow_case) { | |
6947 assert_different_registers(obj, t1, t2); | |
6948 assert_different_registers(obj, var_size_in_bytes, t1); | |
6949 Register end = t2; | |
6950 Register thread = NOT_LP64(t1) LP64_ONLY(r15_thread); | |
6951 | |
6952 verify_tlab(); | |
6953 | |
6954 NOT_LP64(get_thread(thread)); | |
6955 | |
6956 movptr(obj, Address(thread, JavaThread::tlab_top_offset())); | |
6957 if (var_size_in_bytes == noreg) { | |
6958 lea(end, Address(obj, con_size_in_bytes)); | |
6959 } else { | |
6960 lea(end, Address(obj, var_size_in_bytes, Address::times_1)); | |
6961 } | |
6962 cmpptr(end, Address(thread, JavaThread::tlab_end_offset())); | |
6963 jcc(Assembler::above, slow_case); | |
6964 | |
6965 // update the tlab top pointer | |
6966 movptr(Address(thread, JavaThread::tlab_top_offset()), end); | |
6967 | |
6968 // recover var_size_in_bytes if necessary | |
6969 if (var_size_in_bytes == end) { | |
6970 subptr(var_size_in_bytes, obj); | |
6971 } | |
6972 verify_tlab(); | |
6973 } | |
6974 | |
6975 // Preserves rbx, and rdx. | |
6976 void MacroAssembler::tlab_refill(Label& retry, | |
6977 Label& try_eden, | |
6978 Label& slow_case) { | |
6979 Register top = rax; | |
6980 Register t1 = rcx; | |
6981 Register t2 = rsi; | |
6982 Register thread_reg = NOT_LP64(rdi) LP64_ONLY(r15_thread); | |
6983 assert_different_registers(top, thread_reg, t1, t2, /* preserve: */ rbx, rdx); | |
6984 Label do_refill, discard_tlab; | |
6985 | |
6986 if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) { | |
6987 // No allocation in the shared eden. | |
6988 jmp(slow_case); | |
6989 } | |
6990 | |
6991 NOT_LP64(get_thread(thread_reg)); | |
6992 | |
6993 movptr(top, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset()))); | |
6994 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset()))); | |
6995 | |
6996 // calculate amount of free space | |
6997 subptr(t1, top); | |
6998 shrptr(t1, LogHeapWordSize); | |
6999 | |
7000 // Retain tlab and allocate object in shared space if | |
7001 // the amount free in the tlab is too large to discard. | |
7002 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset()))); | |
7003 jcc(Assembler::lessEqual, discard_tlab); | |
7004 | |
7005 // Retain | |
7006 // %%% yuck as movptr... | |
7007 movptr(t2, (int32_t) ThreadLocalAllocBuffer::refill_waste_limit_increment()); | |
7008 addptr(Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())), t2); | |
7009 if (TLABStats) { | |
7010 // increment number of slow_allocations | |
7011 addl(Address(thread_reg, in_bytes(JavaThread::tlab_slow_allocations_offset())), 1); | |
7012 } | |
7013 jmp(try_eden); | |
7014 | |
7015 bind(discard_tlab); | |
7016 if (TLABStats) { | |
7017 // increment number of refills | |
7018 addl(Address(thread_reg, in_bytes(JavaThread::tlab_number_of_refills_offset())), 1); | |
7019 // accumulate wastage -- t1 is amount free in tlab | |
7020 addl(Address(thread_reg, in_bytes(JavaThread::tlab_fast_refill_waste_offset())), t1); | |
7021 } | |
7022 | |
7023 // if tlab is currently allocated (top or end != null) then | |
7024 // fill [top, end + alignment_reserve) with array object | |
7025 testptr (top, top); | |
7026 jcc(Assembler::zero, do_refill); | |
7027 | |
7028 // set up the mark word | |
7029 movptr(Address(top, oopDesc::mark_offset_in_bytes()), (intptr_t)markOopDesc::prototype()->copy_set_hash(0x2)); | |
7030 // set the length to the remaining space | |
7031 subptr(t1, typeArrayOopDesc::header_size(T_INT)); | |
7032 addptr(t1, (int32_t)ThreadLocalAllocBuffer::alignment_reserve()); | |
7033 shlptr(t1, log2_intptr(HeapWordSize/sizeof(jint))); | |
7034 movptr(Address(top, arrayOopDesc::length_offset_in_bytes()), t1); | |
7035 // set klass to intArrayKlass | |
7036 // dubious reloc why not an oop reloc? | |
7037 movptr(t1, ExternalAddress((address) Universe::intArrayKlassObj_addr())); | |
7038 // store klass last. concurrent gcs assumes klass length is valid if | |
7039 // klass field is not null. | |
7040 store_klass(top, t1); | |
7041 | |
7042 // refill the tlab with an eden allocation | |
7043 bind(do_refill); | |
7044 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset()))); | |
7045 shlptr(t1, LogHeapWordSize); | |
7046 // add object_size ?? | |
7047 eden_allocate(top, t1, 0, t2, slow_case); | |
7048 | |
7049 // Check that t1 was preserved in eden_allocate. | |
7050 #ifdef ASSERT | |
7051 if (UseTLAB) { | |
7052 Label ok; | |
7053 Register tsize = rsi; | |
7054 assert_different_registers(tsize, thread_reg, t1); | |
7055 push(tsize); | |
7056 movptr(tsize, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset()))); | |
7057 shlptr(tsize, LogHeapWordSize); | |
7058 cmpptr(t1, tsize); | |
7059 jcc(Assembler::equal, ok); | |
7060 stop("assert(t1 != tlab size)"); | |
7061 should_not_reach_here(); | |
7062 | |
7063 bind(ok); | |
7064 pop(tsize); | |
7065 } | |
7066 #endif | |
7067 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())), top); | |
7068 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())), top); | |
7069 addptr(top, t1); | |
7070 subptr(top, (int32_t)ThreadLocalAllocBuffer::alignment_reserve_in_bytes()); | |
7071 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())), top); | |
7072 verify_tlab(); | |
7073 jmp(retry); | |
7074 } | |
7075 | |
7076 static const double pi_4 = 0.7853981633974483; | |
7077 | |
7078 void MacroAssembler::trigfunc(char trig, int num_fpu_regs_in_use) { | |
7079 // A hand-coded argument reduction for values in fabs(pi/4, pi/2) | |
7080 // was attempted in this code; unfortunately it appears that the | |
7081 // switch to 80-bit precision and back causes this to be | |
7082 // unprofitable compared with simply performing a runtime call if | |
7083 // the argument is out of the (-pi/4, pi/4) range. | |
7084 | |
7085 Register tmp = noreg; | |
7086 if (!VM_Version::supports_cmov()) { | |
7087 // fcmp needs a temporary so preserve rbx, | |
7088 tmp = rbx; | |
7089 push(tmp); | |
7090 } | |
7091 | |
7092 Label slow_case, done; | |
7093 | |
520
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7094 ExternalAddress pi4_adr = (address)&pi_4; |
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7095 if (reachable(pi4_adr)) { |
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7096 // x ?<= pi/4 |
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7097 fld_d(pi4_adr); |
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7098 fld_s(1); // Stack: X PI/4 X |
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7099 fabs(); // Stack: |X| PI/4 X |
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7100 fcmp(tmp); |
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7101 jcc(Assembler::above, slow_case); |
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7102 |
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7103 // fastest case: -pi/4 <= x <= pi/4 |
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7104 switch(trig) { |
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7105 case 's': |
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7106 fsin(); |
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7107 break; |
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7108 case 'c': |
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7109 fcos(); |
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7110 break; |
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7111 case 't': |
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7112 ftan(); |
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7113 break; |
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7114 default: |
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7115 assert(false, "bad intrinsic"); |
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7116 break; |
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7117 } |
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7118 jmp(done); |
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7119 } |
304 | 7120 |
7121 // slow case: runtime call | |
7122 bind(slow_case); | |
7123 // Preserve registers across runtime call | |
7124 pusha(); | |
7125 int incoming_argument_and_return_value_offset = -1; | |
7126 if (num_fpu_regs_in_use > 1) { | |
7127 // Must preserve all other FPU regs (could alternatively convert | |
7128 // SharedRuntime::dsin and dcos into assembly routines known not to trash | |
7129 // FPU state, but can not trust C compiler) | |
7130 NEEDS_CLEANUP; | |
7131 // NOTE that in this case we also push the incoming argument to | |
7132 // the stack and restore it later; we also use this stack slot to | |
7133 // hold the return value from dsin or dcos. | |
7134 for (int i = 0; i < num_fpu_regs_in_use; i++) { | |
7135 subptr(rsp, sizeof(jdouble)); | |
7136 fstp_d(Address(rsp, 0)); | |
7137 } | |
7138 incoming_argument_and_return_value_offset = sizeof(jdouble)*(num_fpu_regs_in_use-1); | |
7139 fld_d(Address(rsp, incoming_argument_and_return_value_offset)); | |
7140 } | |
7141 subptr(rsp, sizeof(jdouble)); | |
7142 fstp_d(Address(rsp, 0)); | |
7143 #ifdef _LP64 | |
7144 movdbl(xmm0, Address(rsp, 0)); | |
7145 #endif // _LP64 | |
7146 | |
7147 // NOTE: we must not use call_VM_leaf here because that requires a | |
7148 // complete interpreter frame in debug mode -- same bug as 4387334 | |
7149 // MacroAssembler::call_VM_leaf_base is perfectly safe and will | |
7150 // do proper 64bit abi | |
7151 | |
7152 NEEDS_CLEANUP; | |
7153 // Need to add stack banging before this runtime call if it needs to | |
7154 // be taken; however, there is no generic stack banging routine at | |
7155 // the MacroAssembler level | |
7156 switch(trig) { | |
7157 case 's': | |
7158 { | |
7159 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::dsin), 0); | |
7160 } | |
7161 break; | |
7162 case 'c': | |
7163 { | |
7164 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::dcos), 0); | |
7165 } | |
7166 break; | |
7167 case 't': | |
7168 { | |
7169 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::dtan), 0); | |
7170 } | |
7171 break; | |
7172 default: | |
7173 assert(false, "bad intrinsic"); | |
7174 break; | |
7175 } | |
7176 #ifdef _LP64 | |
7177 movsd(Address(rsp, 0), xmm0); | |
7178 fld_d(Address(rsp, 0)); | |
7179 #endif // _LP64 | |
7180 addptr(rsp, sizeof(jdouble)); | |
7181 if (num_fpu_regs_in_use > 1) { | |
7182 // Must save return value to stack and then restore entire FPU stack | |
7183 fstp_d(Address(rsp, incoming_argument_and_return_value_offset)); | |
7184 for (int i = 0; i < num_fpu_regs_in_use; i++) { | |
7185 fld_d(Address(rsp, 0)); | |
7186 addptr(rsp, sizeof(jdouble)); | |
7187 } | |
7188 } | |
7189 popa(); | |
7190 | |
7191 // Come here with result in F-TOS | |
7192 bind(done); | |
7193 | |
7194 if (tmp != noreg) { | |
7195 pop(tmp); | |
7196 } | |
7197 } | |
7198 | |
7199 | |
623
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7200 // Look up the method for a megamorphic invokeinterface call. |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7201 // The target method is determined by <intf_klass, itable_index>. |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7202 // The receiver klass is in recv_klass. |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7203 // On success, the result will be in method_result, and execution falls through. |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7204 // On failure, execution transfers to the given label. |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7205 void MacroAssembler::lookup_interface_method(Register recv_klass, |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7206 Register intf_klass, |
665
c89f86385056
6814659: separable cleanups and subroutines for 6655638
jrose
parents:
647
diff
changeset
|
7207 RegisterOrConstant itable_index, |
623
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7208 Register method_result, |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7209 Register scan_temp, |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7210 Label& L_no_such_interface) { |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7211 assert_different_registers(recv_klass, intf_klass, method_result, scan_temp); |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7212 assert(itable_index.is_constant() || itable_index.as_register() == method_result, |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7213 "caller must use same register for non-constant itable index as for method"); |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7214 |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7215 // Compute start of first itableOffsetEntry (which is at the end of the vtable) |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7216 int vtable_base = instanceKlass::vtable_start_offset() * wordSize; |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7217 int itentry_off = itableMethodEntry::method_offset_in_bytes(); |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7218 int scan_step = itableOffsetEntry::size() * wordSize; |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7219 int vte_size = vtableEntry::size() * wordSize; |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7220 Address::ScaleFactor times_vte_scale = Address::times_ptr; |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7221 assert(vte_size == wordSize, "else adjust times_vte_scale"); |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7222 |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7223 movl(scan_temp, Address(recv_klass, instanceKlass::vtable_length_offset() * wordSize)); |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7224 |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7225 // %%% Could store the aligned, prescaled offset in the klassoop. |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7226 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base)); |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7227 if (HeapWordsPerLong > 1) { |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7228 // Round up to align_object_offset boundary |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7229 // see code for instanceKlass::start_of_itable! |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7230 round_to(scan_temp, BytesPerLong); |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7231 } |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7232 |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7233 // Adjust recv_klass by scaled itable_index, so we can free itable_index. |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7234 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below"); |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7235 lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off)); |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7236 |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7237 // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) { |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7238 // if (scan->interface() == intf) { |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7239 // result = (klass + scan->offset() + itable_index); |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7240 // } |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7241 // } |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7242 Label search, found_method; |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7243 |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7244 for (int peel = 1; peel >= 0; peel--) { |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7245 movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes())); |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7246 cmpptr(intf_klass, method_result); |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7247 |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7248 if (peel) { |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7249 jccb(Assembler::equal, found_method); |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7250 } else { |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7251 jccb(Assembler::notEqual, search); |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7252 // (invert the test to fall through to found_method...) |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7253 } |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7254 |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7255 if (!peel) break; |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7256 |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7257 bind(search); |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7258 |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7259 // Check that the previous entry is non-null. A null entry means that |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7260 // the receiver class doesn't implement the interface, and wasn't the |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7261 // same as when the caller was compiled. |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7262 testptr(method_result, method_result); |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7263 jcc(Assembler::zero, L_no_such_interface); |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7264 addptr(scan_temp, scan_step); |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7265 } |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7266 |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7267 bind(found_method); |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7268 |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7269 // Got a hit. |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7270 movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes())); |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7271 movptr(method_result, Address(recv_klass, scan_temp, Address::times_1)); |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7272 } |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7273 |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7274 |
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7275 void MacroAssembler::check_klass_subtype(Register sub_klass, |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7276 Register super_klass, |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7277 Register temp_reg, |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7278 Label& L_success) { |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7279 Label L_failure; |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7280 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, NULL); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7281 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7282 bind(L_failure); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7283 } |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7284 |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7285 |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7286 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass, |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7287 Register super_klass, |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7288 Register temp_reg, |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7289 Label* L_success, |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7290 Label* L_failure, |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7291 Label* L_slow_path, |
665
c89f86385056
6814659: separable cleanups and subroutines for 6655638
jrose
parents:
647
diff
changeset
|
7292 RegisterOrConstant super_check_offset) { |
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7293 assert_different_registers(sub_klass, super_klass, temp_reg); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7294 bool must_load_sco = (super_check_offset.constant_or_zero() == -1); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7295 if (super_check_offset.is_register()) { |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7296 assert_different_registers(sub_klass, super_klass, |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7297 super_check_offset.as_register()); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7298 } else if (must_load_sco) { |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7299 assert(temp_reg != noreg, "supply either a temp or a register offset"); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7300 } |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7301 |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7302 Label L_fallthrough; |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7303 int label_nulls = 0; |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7304 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; } |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7305 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; } |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7306 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; } |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7307 assert(label_nulls <= 1, "at most one NULL in the batch"); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7308 |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7309 int sc_offset = (klassOopDesc::header_size() * HeapWordSize + |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7310 Klass::secondary_super_cache_offset_in_bytes()); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7311 int sco_offset = (klassOopDesc::header_size() * HeapWordSize + |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7312 Klass::super_check_offset_offset_in_bytes()); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7313 Address super_check_offset_addr(super_klass, sco_offset); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7314 |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7315 // Hacked jcc, which "knows" that L_fallthrough, at least, is in |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7316 // range of a jccb. If this routine grows larger, reconsider at |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7317 // least some of these. |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7318 #define local_jcc(assembler_cond, label) \ |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7319 if (&(label) == &L_fallthrough) jccb(assembler_cond, label); \ |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7320 else jcc( assembler_cond, label) /*omit semi*/ |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7321 |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7322 // Hacked jmp, which may only be used just before L_fallthrough. |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7323 #define final_jmp(label) \ |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7324 if (&(label) == &L_fallthrough) { /*do nothing*/ } \ |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7325 else jmp(label) /*omit semi*/ |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7326 |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7327 // If the pointers are equal, we are done (e.g., String[] elements). |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7328 // This self-check enables sharing of secondary supertype arrays among |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7329 // non-primary types such as array-of-interface. Otherwise, each such |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7330 // type would need its own customized SSA. |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7331 // We move this check to the front of the fast path because many |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7332 // type checks are in fact trivially successful in this manner, |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7333 // so we get a nicely predicted branch right at the start of the check. |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7334 cmpptr(sub_klass, super_klass); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7335 local_jcc(Assembler::equal, *L_success); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7336 |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7337 // Check the supertype display: |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7338 if (must_load_sco) { |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7339 // Positive movl does right thing on LP64. |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7340 movl(temp_reg, super_check_offset_addr); |
665
c89f86385056
6814659: separable cleanups and subroutines for 6655638
jrose
parents:
647
diff
changeset
|
7341 super_check_offset = RegisterOrConstant(temp_reg); |
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7342 } |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7343 Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7344 cmpptr(super_klass, super_check_addr); // load displayed supertype |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7345 |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7346 // This check has worked decisively for primary supers. |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7347 // Secondary supers are sought in the super_cache ('super_cache_addr'). |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7348 // (Secondary supers are interfaces and very deeply nested subtypes.) |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7349 // This works in the same check above because of a tricky aliasing |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7350 // between the super_cache and the primary super display elements. |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7351 // (The 'super_check_addr' can address either, as the case requires.) |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7352 // Note that the cache is updated below if it does not help us find |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7353 // what we need immediately. |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7354 // So if it was a primary super, we can just fail immediately. |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7355 // Otherwise, it's the slow path for us (no success at this point). |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7356 |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7357 if (super_check_offset.is_register()) { |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7358 local_jcc(Assembler::equal, *L_success); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7359 cmpl(super_check_offset.as_register(), sc_offset); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7360 if (L_failure == &L_fallthrough) { |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7361 local_jcc(Assembler::equal, *L_slow_path); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7362 } else { |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7363 local_jcc(Assembler::notEqual, *L_failure); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7364 final_jmp(*L_slow_path); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7365 } |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7366 } else if (super_check_offset.as_constant() == sc_offset) { |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7367 // Need a slow path; fast failure is impossible. |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7368 if (L_slow_path == &L_fallthrough) { |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7369 local_jcc(Assembler::equal, *L_success); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7370 } else { |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7371 local_jcc(Assembler::notEqual, *L_slow_path); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7372 final_jmp(*L_success); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7373 } |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7374 } else { |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7375 // No slow path; it's a fast decision. |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7376 if (L_failure == &L_fallthrough) { |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7377 local_jcc(Assembler::equal, *L_success); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7378 } else { |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7379 local_jcc(Assembler::notEqual, *L_failure); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7380 final_jmp(*L_success); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7381 } |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7382 } |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7383 |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7384 bind(L_fallthrough); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7385 |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7386 #undef local_jcc |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7387 #undef final_jmp |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7388 } |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7389 |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7390 |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7391 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass, |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7392 Register super_klass, |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7393 Register temp_reg, |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7394 Register temp2_reg, |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7395 Label* L_success, |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7396 Label* L_failure, |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7397 bool set_cond_codes) { |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7398 assert_different_registers(sub_klass, super_klass, temp_reg); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7399 if (temp2_reg != noreg) |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7400 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7401 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg) |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7402 |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7403 Label L_fallthrough; |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7404 int label_nulls = 0; |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7405 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; } |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7406 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; } |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7407 assert(label_nulls <= 1, "at most one NULL in the batch"); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7408 |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7409 // a couple of useful fields in sub_klass: |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7410 int ss_offset = (klassOopDesc::header_size() * HeapWordSize + |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7411 Klass::secondary_supers_offset_in_bytes()); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7412 int sc_offset = (klassOopDesc::header_size() * HeapWordSize + |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7413 Klass::secondary_super_cache_offset_in_bytes()); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7414 Address secondary_supers_addr(sub_klass, ss_offset); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7415 Address super_cache_addr( sub_klass, sc_offset); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7416 |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7417 // Do a linear scan of the secondary super-klass chain. |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7418 // This code is rarely used, so simplicity is a virtue here. |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7419 // The repne_scan instruction uses fixed registers, which we must spill. |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7420 // Don't worry too much about pre-existing connections with the input regs. |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7421 |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7422 assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super) |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7423 assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter) |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7424 |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7425 // Get super_klass value into rax (even if it was in rdi or rcx). |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7426 bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false; |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7427 if (super_klass != rax || UseCompressedOops) { |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7428 if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; } |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7429 mov(rax, super_klass); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7430 } |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7431 if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; } |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7432 if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; } |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7433 |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7434 #ifndef PRODUCT |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7435 int* pst_counter = &SharedRuntime::_partial_subtype_ctr; |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7436 ExternalAddress pst_counter_addr((address) pst_counter); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7437 NOT_LP64( incrementl(pst_counter_addr) ); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7438 LP64_ONLY( lea(rcx, pst_counter_addr) ); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7439 LP64_ONLY( incrementl(Address(rcx, 0)) ); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7440 #endif //PRODUCT |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7441 |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7442 // We will consult the secondary-super array. |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7443 movptr(rdi, secondary_supers_addr); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7444 // Load the array length. (Positive movl does right thing on LP64.) |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7445 movl(rcx, Address(rdi, arrayOopDesc::length_offset_in_bytes())); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7446 // Skip to start of data. |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7447 addptr(rdi, arrayOopDesc::base_offset_in_bytes(T_OBJECT)); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7448 |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7449 // Scan RCX words at [RDI] for an occurrence of RAX. |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7450 // Set NZ/Z based on last compare. |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7451 #ifdef _LP64 |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7452 // This part is tricky, as values in supers array could be 32 or 64 bit wide |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7453 // and we store values in objArrays always encoded, thus we need to encode |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7454 // the value of rax before repne. Note that rax is dead after the repne. |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7455 if (UseCompressedOops) { |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7456 encode_heap_oop_not_null(rax); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7457 // The superclass is never null; it would be a basic system error if a null |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7458 // pointer were to sneak in here. Note that we have already loaded the |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7459 // Klass::super_check_offset from the super_klass in the fast path, |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7460 // so if there is a null in that register, we are already in the afterlife. |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7461 repne_scanl(); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7462 } else |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7463 #endif // _LP64 |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7464 repne_scan(); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7465 |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7466 // Unspill the temp. registers: |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7467 if (pushed_rdi) pop(rdi); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7468 if (pushed_rcx) pop(rcx); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7469 if (pushed_rax) pop(rax); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7470 |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7471 if (set_cond_codes) { |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7472 // Special hack for the AD files: rdi is guaranteed non-zero. |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7473 assert(!pushed_rdi, "rdi must be left non-NULL"); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7474 // Also, the condition codes are properly set Z/NZ on succeed/failure. |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7475 } |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7476 |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7477 if (L_failure == &L_fallthrough) |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7478 jccb(Assembler::notEqual, *L_failure); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7479 else jcc(Assembler::notEqual, *L_failure); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7480 |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7481 // Success. Cache the super we found and proceed in triumph. |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7482 movptr(super_cache_addr, super_klass); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7483 |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7484 if (L_success != &L_fallthrough) { |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7485 jmp(*L_success); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7486 } |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7487 |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7488 #undef IS_A_TEMP |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7489 |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7490 bind(L_fallthrough); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7491 } |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7492 |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7493 |
304 | 7494 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) { |
7495 ucomisd(dst, as_Address(src)); | |
7496 } | |
7497 | |
7498 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) { | |
7499 ucomiss(dst, as_Address(src)); | |
7500 } | |
7501 | |
7502 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src) { | |
7503 if (reachable(src)) { | |
7504 xorpd(dst, as_Address(src)); | |
7505 } else { | |
7506 lea(rscratch1, src); | |
7507 xorpd(dst, Address(rscratch1, 0)); | |
7508 } | |
7509 } | |
7510 | |
7511 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src) { | |
7512 if (reachable(src)) { | |
7513 xorps(dst, as_Address(src)); | |
7514 } else { | |
7515 lea(rscratch1, src); | |
7516 xorps(dst, Address(rscratch1, 0)); | |
7517 } | |
7518 } | |
7519 | |
0 | 7520 void MacroAssembler::verify_oop(Register reg, const char* s) { |
7521 if (!VerifyOops) return; | |
304 | 7522 |
0 | 7523 // Pass register number to verify_oop_subroutine |
7524 char* b = new char[strlen(s) + 50]; | |
7525 sprintf(b, "verify_oop: %s: %s", reg->name(), s); | |
304 | 7526 push(rax); // save rax, |
7527 push(reg); // pass register argument | |
0 | 7528 ExternalAddress buffer((address) b); |
304 | 7529 // avoid using pushptr, as it modifies scratch registers |
7530 // and our contract is not to modify anything | |
7531 movptr(rax, buffer.addr()); | |
7532 push(rax); | |
0 | 7533 // call indirectly to solve generation ordering problem |
7534 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address())); | |
7535 call(rax); | |
7536 } | |
7537 | |
7538 | |
665
c89f86385056
6814659: separable cleanups and subroutines for 6655638
jrose
parents:
647
diff
changeset
|
7539 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr, |
c89f86385056
6814659: separable cleanups and subroutines for 6655638
jrose
parents:
647
diff
changeset
|
7540 Register tmp, |
c89f86385056
6814659: separable cleanups and subroutines for 6655638
jrose
parents:
647
diff
changeset
|
7541 int offset) { |
622
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
606
diff
changeset
|
7542 intptr_t value = *delayed_value_addr; |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
606
diff
changeset
|
7543 if (value != 0) |
665
c89f86385056
6814659: separable cleanups and subroutines for 6655638
jrose
parents:
647
diff
changeset
|
7544 return RegisterOrConstant(value + offset); |
622
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
606
diff
changeset
|
7545 |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
606
diff
changeset
|
7546 // load indirectly to solve generation ordering problem |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
606
diff
changeset
|
7547 movptr(tmp, ExternalAddress((address) delayed_value_addr)); |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
606
diff
changeset
|
7548 |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
606
diff
changeset
|
7549 #ifdef ASSERT |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
606
diff
changeset
|
7550 Label L; |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
606
diff
changeset
|
7551 testl(tmp, tmp); |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
606
diff
changeset
|
7552 jccb(Assembler::notZero, L); |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
606
diff
changeset
|
7553 hlt(); |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
606
diff
changeset
|
7554 bind(L); |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
606
diff
changeset
|
7555 #endif |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
606
diff
changeset
|
7556 |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
606
diff
changeset
|
7557 if (offset != 0) |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
606
diff
changeset
|
7558 addptr(tmp, offset); |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
606
diff
changeset
|
7559 |
665
c89f86385056
6814659: separable cleanups and subroutines for 6655638
jrose
parents:
647
diff
changeset
|
7560 return RegisterOrConstant(tmp); |
622
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
606
diff
changeset
|
7561 } |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
606
diff
changeset
|
7562 |
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
606
diff
changeset
|
7563 |
0 | 7564 void MacroAssembler::verify_oop_addr(Address addr, const char* s) { |
7565 if (!VerifyOops) return; | |
304 | 7566 |
0 | 7567 // Address adjust(addr.base(), addr.index(), addr.scale(), addr.disp() + BytesPerWord); |
7568 // Pass register number to verify_oop_subroutine | |
7569 char* b = new char[strlen(s) + 50]; | |
7570 sprintf(b, "verify_oop_addr: %s", s); | |
304 | 7571 |
7572 push(rax); // save rax, | |
0 | 7573 // addr may contain rsp so we will have to adjust it based on the push |
7574 // we just did | |
304 | 7575 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which |
7576 // stores rax into addr which is backwards of what was intended. | |
0 | 7577 if (addr.uses(rsp)) { |
304 | 7578 lea(rax, addr); |
7579 pushptr(Address(rax, BytesPerWord)); | |
0 | 7580 } else { |
304 | 7581 pushptr(addr); |
7582 } | |
7583 | |
0 | 7584 ExternalAddress buffer((address) b); |
7585 // pass msg argument | |
304 | 7586 // avoid using pushptr, as it modifies scratch registers |
7587 // and our contract is not to modify anything | |
7588 movptr(rax, buffer.addr()); | |
7589 push(rax); | |
7590 | |
0 | 7591 // call indirectly to solve generation ordering problem |
7592 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address())); | |
7593 call(rax); | |
7594 // Caller pops the arguments and restores rax, from the stack | |
7595 } | |
7596 | |
304 | 7597 void MacroAssembler::verify_tlab() { |
7598 #ifdef ASSERT | |
7599 if (UseTLAB && VerifyOops) { | |
7600 Label next, ok; | |
7601 Register t1 = rsi; | |
7602 Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread); | |
7603 | |
7604 push(t1); | |
7605 NOT_LP64(push(thread_reg)); | |
7606 NOT_LP64(get_thread(thread_reg)); | |
7607 | |
7608 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset()))); | |
7609 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset()))); | |
7610 jcc(Assembler::aboveEqual, next); | |
7611 stop("assert(top >= start)"); | |
7612 should_not_reach_here(); | |
7613 | |
7614 bind(next); | |
7615 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset()))); | |
7616 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset()))); | |
7617 jcc(Assembler::aboveEqual, ok); | |
7618 stop("assert(top <= end)"); | |
7619 should_not_reach_here(); | |
7620 | |
7621 bind(ok); | |
7622 NOT_LP64(pop(thread_reg)); | |
7623 pop(t1); | |
7624 } | |
7625 #endif | |
7626 } | |
0 | 7627 |
7628 class ControlWord { | |
7629 public: | |
7630 int32_t _value; | |
7631 | |
7632 int rounding_control() const { return (_value >> 10) & 3 ; } | |
7633 int precision_control() const { return (_value >> 8) & 3 ; } | |
7634 bool precision() const { return ((_value >> 5) & 1) != 0; } | |
7635 bool underflow() const { return ((_value >> 4) & 1) != 0; } | |
7636 bool overflow() const { return ((_value >> 3) & 1) != 0; } | |
7637 bool zero_divide() const { return ((_value >> 2) & 1) != 0; } | |
7638 bool denormalized() const { return ((_value >> 1) & 1) != 0; } | |
7639 bool invalid() const { return ((_value >> 0) & 1) != 0; } | |
7640 | |
7641 void print() const { | |
7642 // rounding control | |
7643 const char* rc; | |
7644 switch (rounding_control()) { | |
7645 case 0: rc = "round near"; break; | |
7646 case 1: rc = "round down"; break; | |
7647 case 2: rc = "round up "; break; | |
7648 case 3: rc = "chop "; break; | |
7649 }; | |
7650 // precision control | |
7651 const char* pc; | |
7652 switch (precision_control()) { | |
7653 case 0: pc = "24 bits "; break; | |
7654 case 1: pc = "reserved"; break; | |
7655 case 2: pc = "53 bits "; break; | |
7656 case 3: pc = "64 bits "; break; | |
7657 }; | |
7658 // flags | |
7659 char f[9]; | |
7660 f[0] = ' '; | |
7661 f[1] = ' '; | |
7662 f[2] = (precision ()) ? 'P' : 'p'; | |
7663 f[3] = (underflow ()) ? 'U' : 'u'; | |
7664 f[4] = (overflow ()) ? 'O' : 'o'; | |
7665 f[5] = (zero_divide ()) ? 'Z' : 'z'; | |
7666 f[6] = (denormalized()) ? 'D' : 'd'; | |
7667 f[7] = (invalid ()) ? 'I' : 'i'; | |
7668 f[8] = '\x0'; | |
7669 // output | |
7670 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc); | |
7671 } | |
7672 | |
7673 }; | |
7674 | |
7675 class StatusWord { | |
7676 public: | |
7677 int32_t _value; | |
7678 | |
7679 bool busy() const { return ((_value >> 15) & 1) != 0; } | |
7680 bool C3() const { return ((_value >> 14) & 1) != 0; } | |
7681 bool C2() const { return ((_value >> 10) & 1) != 0; } | |
7682 bool C1() const { return ((_value >> 9) & 1) != 0; } | |
7683 bool C0() const { return ((_value >> 8) & 1) != 0; } | |
7684 int top() const { return (_value >> 11) & 7 ; } | |
7685 bool error_status() const { return ((_value >> 7) & 1) != 0; } | |
7686 bool stack_fault() const { return ((_value >> 6) & 1) != 0; } | |
7687 bool precision() const { return ((_value >> 5) & 1) != 0; } | |
7688 bool underflow() const { return ((_value >> 4) & 1) != 0; } | |
7689 bool overflow() const { return ((_value >> 3) & 1) != 0; } | |
7690 bool zero_divide() const { return ((_value >> 2) & 1) != 0; } | |
7691 bool denormalized() const { return ((_value >> 1) & 1) != 0; } | |
7692 bool invalid() const { return ((_value >> 0) & 1) != 0; } | |
7693 | |
7694 void print() const { | |
7695 // condition codes | |
7696 char c[5]; | |
7697 c[0] = (C3()) ? '3' : '-'; | |
7698 c[1] = (C2()) ? '2' : '-'; | |
7699 c[2] = (C1()) ? '1' : '-'; | |
7700 c[3] = (C0()) ? '0' : '-'; | |
7701 c[4] = '\x0'; | |
7702 // flags | |
7703 char f[9]; | |
7704 f[0] = (error_status()) ? 'E' : '-'; | |
7705 f[1] = (stack_fault ()) ? 'S' : '-'; | |
7706 f[2] = (precision ()) ? 'P' : '-'; | |
7707 f[3] = (underflow ()) ? 'U' : '-'; | |
7708 f[4] = (overflow ()) ? 'O' : '-'; | |
7709 f[5] = (zero_divide ()) ? 'Z' : '-'; | |
7710 f[6] = (denormalized()) ? 'D' : '-'; | |
7711 f[7] = (invalid ()) ? 'I' : '-'; | |
7712 f[8] = '\x0'; | |
7713 // output | |
7714 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top()); | |
7715 } | |
7716 | |
7717 }; | |
7718 | |
7719 class TagWord { | |
7720 public: | |
7721 int32_t _value; | |
7722 | |
7723 int tag_at(int i) const { return (_value >> (i*2)) & 3; } | |
7724 | |
7725 void print() const { | |
7726 printf("%04x", _value & 0xFFFF); | |
7727 } | |
7728 | |
7729 }; | |
7730 | |
7731 class FPU_Register { | |
7732 public: | |
7733 int32_t _m0; | |
7734 int32_t _m1; | |
7735 int16_t _ex; | |
7736 | |
7737 bool is_indefinite() const { | |
7738 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0; | |
7739 } | |
7740 | |
7741 void print() const { | |
7742 char sign = (_ex < 0) ? '-' : '+'; | |
7743 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " "; | |
7744 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind); | |
7745 }; | |
7746 | |
7747 }; | |
7748 | |
7749 class FPU_State { | |
7750 public: | |
7751 enum { | |
7752 register_size = 10, | |
7753 number_of_registers = 8, | |
7754 register_mask = 7 | |
7755 }; | |
7756 | |
7757 ControlWord _control_word; | |
7758 StatusWord _status_word; | |
7759 TagWord _tag_word; | |
7760 int32_t _error_offset; | |
7761 int32_t _error_selector; | |
7762 int32_t _data_offset; | |
7763 int32_t _data_selector; | |
7764 int8_t _register[register_size * number_of_registers]; | |
7765 | |
7766 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); } | |
7767 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; } | |
7768 | |
7769 const char* tag_as_string(int tag) const { | |
7770 switch (tag) { | |
7771 case 0: return "valid"; | |
7772 case 1: return "zero"; | |
7773 case 2: return "special"; | |
7774 case 3: return "empty"; | |
7775 } | |
7776 ShouldNotReachHere() | |
7777 return NULL; | |
7778 } | |
7779 | |
7780 void print() const { | |
7781 // print computation registers | |
7782 { int t = _status_word.top(); | |
7783 for (int i = 0; i < number_of_registers; i++) { | |
7784 int j = (i - t) & register_mask; | |
7785 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j); | |
7786 st(j)->print(); | |
7787 printf(" %s\n", tag_as_string(_tag_word.tag_at(i))); | |
7788 } | |
7789 } | |
7790 printf("\n"); | |
7791 // print control registers | |
7792 printf("ctrl = "); _control_word.print(); printf("\n"); | |
7793 printf("stat = "); _status_word .print(); printf("\n"); | |
7794 printf("tags = "); _tag_word .print(); printf("\n"); | |
7795 } | |
7796 | |
7797 }; | |
7798 | |
7799 class Flag_Register { | |
7800 public: | |
7801 int32_t _value; | |
7802 | |
7803 bool overflow() const { return ((_value >> 11) & 1) != 0; } | |
7804 bool direction() const { return ((_value >> 10) & 1) != 0; } | |
7805 bool sign() const { return ((_value >> 7) & 1) != 0; } | |
7806 bool zero() const { return ((_value >> 6) & 1) != 0; } | |
7807 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; } | |
7808 bool parity() const { return ((_value >> 2) & 1) != 0; } | |
7809 bool carry() const { return ((_value >> 0) & 1) != 0; } | |
7810 | |
7811 void print() const { | |
7812 // flags | |
7813 char f[8]; | |
7814 f[0] = (overflow ()) ? 'O' : '-'; | |
7815 f[1] = (direction ()) ? 'D' : '-'; | |
7816 f[2] = (sign ()) ? 'S' : '-'; | |
7817 f[3] = (zero ()) ? 'Z' : '-'; | |
7818 f[4] = (auxiliary_carry()) ? 'A' : '-'; | |
7819 f[5] = (parity ()) ? 'P' : '-'; | |
7820 f[6] = (carry ()) ? 'C' : '-'; | |
7821 f[7] = '\x0'; | |
7822 // output | |
7823 printf("%08x flags = %s", _value, f); | |
7824 } | |
7825 | |
7826 }; | |
7827 | |
7828 class IU_Register { | |
7829 public: | |
7830 int32_t _value; | |
7831 | |
7832 void print() const { | |
7833 printf("%08x %11d", _value, _value); | |
7834 } | |
7835 | |
7836 }; | |
7837 | |
7838 class IU_State { | |
7839 public: | |
7840 Flag_Register _eflags; | |
7841 IU_Register _rdi; | |
7842 IU_Register _rsi; | |
7843 IU_Register _rbp; | |
7844 IU_Register _rsp; | |
7845 IU_Register _rbx; | |
7846 IU_Register _rdx; | |
7847 IU_Register _rcx; | |
7848 IU_Register _rax; | |
7849 | |
7850 void print() const { | |
7851 // computation registers | |
7852 printf("rax, = "); _rax.print(); printf("\n"); | |
7853 printf("rbx, = "); _rbx.print(); printf("\n"); | |
7854 printf("rcx = "); _rcx.print(); printf("\n"); | |
7855 printf("rdx = "); _rdx.print(); printf("\n"); | |
7856 printf("rdi = "); _rdi.print(); printf("\n"); | |
7857 printf("rsi = "); _rsi.print(); printf("\n"); | |
7858 printf("rbp, = "); _rbp.print(); printf("\n"); | |
7859 printf("rsp = "); _rsp.print(); printf("\n"); | |
7860 printf("\n"); | |
7861 // control registers | |
7862 printf("flgs = "); _eflags.print(); printf("\n"); | |
7863 } | |
7864 }; | |
7865 | |
7866 | |
7867 class CPU_State { | |
7868 public: | |
7869 FPU_State _fpu_state; | |
7870 IU_State _iu_state; | |
7871 | |
7872 void print() const { | |
7873 printf("--------------------------------------------------\n"); | |
7874 _iu_state .print(); | |
7875 printf("\n"); | |
7876 _fpu_state.print(); | |
7877 printf("--------------------------------------------------\n"); | |
7878 } | |
7879 | |
7880 }; | |
7881 | |
7882 | |
7883 static void _print_CPU_state(CPU_State* state) { | |
7884 state->print(); | |
7885 }; | |
7886 | |
7887 | |
7888 void MacroAssembler::print_CPU_state() { | |
7889 push_CPU_state(); | |
304 | 7890 push(rsp); // pass CPU state |
0 | 7891 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state))); |
304 | 7892 addptr(rsp, wordSize); // discard argument |
0 | 7893 pop_CPU_state(); |
7894 } | |
7895 | |
7896 | |
7897 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) { | |
7898 static int counter = 0; | |
7899 FPU_State* fs = &state->_fpu_state; | |
7900 counter++; | |
7901 // For leaf calls, only verify that the top few elements remain empty. | |
7902 // We only need 1 empty at the top for C2 code. | |
7903 if( stack_depth < 0 ) { | |
7904 if( fs->tag_for_st(7) != 3 ) { | |
7905 printf("FPR7 not empty\n"); | |
7906 state->print(); | |
7907 assert(false, "error"); | |
7908 return false; | |
7909 } | |
7910 return true; // All other stack states do not matter | |
7911 } | |
7912 | |
7913 assert((fs->_control_word._value & 0xffff) == StubRoutines::_fpu_cntrl_wrd_std, | |
7914 "bad FPU control word"); | |
7915 | |
7916 // compute stack depth | |
7917 int i = 0; | |
7918 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) < 3) i++; | |
7919 int d = i; | |
7920 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++; | |
7921 // verify findings | |
7922 if (i != FPU_State::number_of_registers) { | |
7923 // stack not contiguous | |
7924 printf("%s: stack not contiguous at ST%d\n", s, i); | |
7925 state->print(); | |
7926 assert(false, "error"); | |
7927 return false; | |
7928 } | |
7929 // check if computed stack depth corresponds to expected stack depth | |
7930 if (stack_depth < 0) { | |
7931 // expected stack depth is -stack_depth or less | |
7932 if (d > -stack_depth) { | |
7933 // too many elements on the stack | |
7934 printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d); | |
7935 state->print(); | |
7936 assert(false, "error"); | |
7937 return false; | |
7938 } | |
7939 } else { | |
7940 // expected stack depth is stack_depth | |
7941 if (d != stack_depth) { | |
7942 // wrong stack depth | |
7943 printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d); | |
7944 state->print(); | |
7945 assert(false, "error"); | |
7946 return false; | |
7947 } | |
7948 } | |
7949 // everything is cool | |
7950 return true; | |
7951 } | |
7952 | |
7953 | |
7954 void MacroAssembler::verify_FPU(int stack_depth, const char* s) { | |
7955 if (!VerifyFPU) return; | |
7956 push_CPU_state(); | |
304 | 7957 push(rsp); // pass CPU state |
0 | 7958 ExternalAddress msg((address) s); |
7959 // pass message string s | |
7960 pushptr(msg.addr()); | |
304 | 7961 push(stack_depth); // pass stack depth |
0 | 7962 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU))); |
304 | 7963 addptr(rsp, 3 * wordSize); // discard arguments |
0 | 7964 // check for error |
7965 { Label L; | |
7966 testl(rax, rax); | |
7967 jcc(Assembler::notZero, L); | |
7968 int3(); // break if error condition | |
7969 bind(L); | |
7970 } | |
7971 pop_CPU_state(); | |
7972 } | |
7973 | |
304 | 7974 void MacroAssembler::load_klass(Register dst, Register src) { |
7975 #ifdef _LP64 | |
7976 if (UseCompressedOops) { | |
7977 movl(dst, Address(src, oopDesc::klass_offset_in_bytes())); | |
7978 decode_heap_oop_not_null(dst); | |
7979 } else | |
7980 #endif | |
7981 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes())); | |
7982 } | |
7983 | |
7984 void MacroAssembler::load_prototype_header(Register dst, Register src) { | |
7985 #ifdef _LP64 | |
7986 if (UseCompressedOops) { | |
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7987 assert (Universe::heap() != NULL, "java heap should be initialized"); |
304 | 7988 movl(dst, Address(src, oopDesc::klass_offset_in_bytes())); |
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7989 if (Universe::narrow_oop_shift() != 0) { |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7990 assert(Address::times_8 == LogMinObjAlignmentInBytes && |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7991 Address::times_8 == Universe::narrow_oop_shift(), "decode alg wrong"); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7992 movq(dst, Address(r12_heapbase, dst, Address::times_8, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes())); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7993 } else { |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7994 movq(dst, Address(dst, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes())); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7995 } |
304 | 7996 } else |
7997 #endif | |
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7998 { |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7999 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes())); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8000 movptr(dst, Address(dst, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes())); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8001 } |
304 | 8002 } |
8003 | |
8004 void MacroAssembler::store_klass(Register dst, Register src) { | |
8005 #ifdef _LP64 | |
8006 if (UseCompressedOops) { | |
8007 encode_heap_oop_not_null(src); | |
8008 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src); | |
8009 } else | |
8010 #endif | |
8011 movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src); | |
8012 } | |
8013 | |
8014 #ifdef _LP64 | |
8015 void MacroAssembler::store_klass_gap(Register dst, Register src) { | |
8016 if (UseCompressedOops) { | |
8017 // Store to klass gap in destination | |
8018 movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src); | |
8019 } | |
8020 } | |
8021 | |
8022 void MacroAssembler::load_heap_oop(Register dst, Address src) { | |
8023 if (UseCompressedOops) { | |
8024 movl(dst, src); | |
8025 decode_heap_oop(dst); | |
8026 } else { | |
8027 movq(dst, src); | |
8028 } | |
8029 } | |
8030 | |
8031 void MacroAssembler::store_heap_oop(Address dst, Register src) { | |
8032 if (UseCompressedOops) { | |
8033 assert(!dst.uses(src), "not enough registers"); | |
8034 encode_heap_oop(src); | |
8035 movl(dst, src); | |
8036 } else { | |
8037 movq(dst, src); | |
8038 } | |
8039 } | |
8040 | |
8041 // Algorithm must match oop.inline.hpp encode_heap_oop. | |
8042 void MacroAssembler::encode_heap_oop(Register r) { | |
8043 assert (UseCompressedOops, "should be compressed"); | |
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8044 assert (Universe::heap() != NULL, "java heap should be initialized"); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8045 if (Universe::narrow_oop_base() == NULL) { |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8046 verify_oop(r, "broken oop in encode_heap_oop"); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8047 if (Universe::narrow_oop_shift() != 0) { |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8048 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8049 shrq(r, LogMinObjAlignmentInBytes); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8050 } |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8051 return; |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8052 } |
0 | 8053 #ifdef ASSERT |
304 | 8054 if (CheckCompressedOops) { |
8055 Label ok; | |
8056 push(rscratch1); // cmpptr trashes rscratch1 | |
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8057 cmpptr(r12_heapbase, ExternalAddress((address)Universe::narrow_oop_base_addr())); |
304 | 8058 jcc(Assembler::equal, ok); |
8059 stop("MacroAssembler::encode_heap_oop: heap base corrupted?"); | |
0 | 8060 bind(ok); |
304 | 8061 pop(rscratch1); |
0 | 8062 } |
8063 #endif | |
304 | 8064 verify_oop(r, "broken oop in encode_heap_oop"); |
8065 testq(r, r); | |
8066 cmovq(Assembler::equal, r, r12_heapbase); | |
8067 subq(r, r12_heapbase); | |
8068 shrq(r, LogMinObjAlignmentInBytes); | |
8069 } | |
8070 | |
8071 void MacroAssembler::encode_heap_oop_not_null(Register r) { | |
8072 assert (UseCompressedOops, "should be compressed"); | |
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8073 assert (Universe::heap() != NULL, "java heap should be initialized"); |
0 | 8074 #ifdef ASSERT |
304 | 8075 if (CheckCompressedOops) { |
0 | 8076 Label ok; |
304 | 8077 testq(r, r); |
8078 jcc(Assembler::notEqual, ok); | |
8079 stop("null oop passed to encode_heap_oop_not_null"); | |
0 | 8080 bind(ok); |
304 | 8081 } |
8082 #endif | |
8083 verify_oop(r, "broken oop in encode_heap_oop_not_null"); | |
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8084 if (Universe::narrow_oop_base() != NULL) { |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8085 subq(r, r12_heapbase); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8086 } |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8087 if (Universe::narrow_oop_shift() != 0) { |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8088 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8089 shrq(r, LogMinObjAlignmentInBytes); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8090 } |
304 | 8091 } |
8092 | |
8093 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) { | |
8094 assert (UseCompressedOops, "should be compressed"); | |
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8095 assert (Universe::heap() != NULL, "java heap should be initialized"); |
304 | 8096 #ifdef ASSERT |
8097 if (CheckCompressedOops) { | |
8098 Label ok; | |
8099 testq(src, src); | |
8100 jcc(Assembler::notEqual, ok); | |
8101 stop("null oop passed to encode_heap_oop_not_null2"); | |
8102 bind(ok); | |
0 | 8103 } |
8104 #endif | |
304 | 8105 verify_oop(src, "broken oop in encode_heap_oop_not_null2"); |
8106 if (dst != src) { | |
8107 movq(dst, src); | |
8108 } | |
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8109 if (Universe::narrow_oop_base() != NULL) { |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8110 subq(dst, r12_heapbase); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8111 } |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8112 if (Universe::narrow_oop_shift() != 0) { |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8113 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8114 shrq(dst, LogMinObjAlignmentInBytes); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8115 } |
304 | 8116 } |
8117 | |
8118 void MacroAssembler::decode_heap_oop(Register r) { | |
8119 assert (UseCompressedOops, "should be compressed"); | |
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8120 assert (Universe::heap() != NULL, "java heap should be initialized"); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8121 if (Universe::narrow_oop_base() == NULL) { |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8122 if (Universe::narrow_oop_shift() != 0) { |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8123 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8124 shlq(r, LogMinObjAlignmentInBytes); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8125 } |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8126 verify_oop(r, "broken oop in decode_heap_oop"); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8127 return; |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8128 } |
304 | 8129 #ifdef ASSERT |
8130 if (CheckCompressedOops) { | |
8131 Label ok; | |
8132 push(rscratch1); | |
8133 cmpptr(r12_heapbase, | |
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8134 ExternalAddress((address)Universe::narrow_oop_base_addr())); |
304 | 8135 jcc(Assembler::equal, ok); |
8136 stop("MacroAssembler::decode_heap_oop: heap base corrupted?"); | |
8137 bind(ok); | |
8138 pop(rscratch1); | |
8139 } | |
8140 #endif | |
8141 | |
8142 Label done; | |
8143 shlq(r, LogMinObjAlignmentInBytes); | |
8144 jccb(Assembler::equal, done); | |
8145 addq(r, r12_heapbase); | |
8146 #if 0 | |
8147 // alternate decoding probably a wash. | |
8148 testq(r, r); | |
8149 jccb(Assembler::equal, done); | |
8150 leaq(r, Address(r12_heapbase, r, Address::times_8, 0)); | |
8151 #endif | |
8152 bind(done); | |
8153 verify_oop(r, "broken oop in decode_heap_oop"); | |
8154 } | |
8155 | |
8156 void MacroAssembler::decode_heap_oop_not_null(Register r) { | |
8157 assert (UseCompressedOops, "should only be used for compressed headers"); | |
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8158 assert (Universe::heap() != NULL, "java heap should be initialized"); |
304 | 8159 // Cannot assert, unverified entry point counts instructions (see .ad file) |
8160 // vtableStubs also counts instructions in pd_code_size_limit. | |
8161 // Also do not verify_oop as this is called by verify_oop. | |
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8162 if (Universe::narrow_oop_base() == NULL) { |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8163 if (Universe::narrow_oop_shift() != 0) { |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8164 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8165 shlq(r, LogMinObjAlignmentInBytes); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8166 } |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8167 } else { |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8168 assert (Address::times_8 == LogMinObjAlignmentInBytes && |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8169 Address::times_8 == Universe::narrow_oop_shift(), "decode alg wrong"); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8170 leaq(r, Address(r12_heapbase, r, Address::times_8, 0)); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8171 } |
304 | 8172 } |
8173 | |
8174 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) { | |
8175 assert (UseCompressedOops, "should only be used for compressed headers"); | |
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8176 assert (Universe::heap() != NULL, "java heap should be initialized"); |
304 | 8177 // Cannot assert, unverified entry point counts instructions (see .ad file) |
8178 // vtableStubs also counts instructions in pd_code_size_limit. | |
8179 // Also do not verify_oop as this is called by verify_oop. | |
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8180 if (Universe::narrow_oop_shift() != 0) { |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8181 assert (Address::times_8 == LogMinObjAlignmentInBytes && |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8182 Address::times_8 == Universe::narrow_oop_shift(), "decode alg wrong"); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8183 leaq(dst, Address(r12_heapbase, src, Address::times_8, 0)); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8184 } else if (dst != src) { |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8185 movq(dst, src); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8186 } |
304 | 8187 } |
8188 | |
8189 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) { | |
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8190 assert (UseCompressedOops, "should only be used for compressed headers"); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8191 assert (Universe::heap() != NULL, "java heap should be initialized"); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8192 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8193 int oop_index = oop_recorder()->find_index(obj); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8194 RelocationHolder rspec = oop_Relocation::spec(oop_index); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8195 mov_narrow_oop(dst, oop_index, rspec); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8196 } |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8197 |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8198 void MacroAssembler::set_narrow_oop(Address dst, jobject obj) { |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8199 assert (UseCompressedOops, "should only be used for compressed headers"); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8200 assert (Universe::heap() != NULL, "java heap should be initialized"); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8201 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); |
304 | 8202 int oop_index = oop_recorder()->find_index(obj); |
8203 RelocationHolder rspec = oop_Relocation::spec(oop_index); | |
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8204 mov_narrow_oop(dst, oop_index, rspec); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8205 } |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8206 |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8207 void MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) { |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8208 assert (UseCompressedOops, "should only be used for compressed headers"); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8209 assert (Universe::heap() != NULL, "java heap should be initialized"); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8210 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8211 int oop_index = oop_recorder()->find_index(obj); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8212 RelocationHolder rspec = oop_Relocation::spec(oop_index); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8213 Assembler::cmp_narrow_oop(dst, oop_index, rspec); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8214 } |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8215 |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8216 void MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) { |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8217 assert (UseCompressedOops, "should only be used for compressed headers"); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8218 assert (Universe::heap() != NULL, "java heap should be initialized"); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8219 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8220 int oop_index = oop_recorder()->find_index(obj); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8221 RelocationHolder rspec = oop_Relocation::spec(oop_index); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8222 Assembler::cmp_narrow_oop(dst, oop_index, rspec); |
304 | 8223 } |
8224 | |
8225 void MacroAssembler::reinit_heapbase() { | |
8226 if (UseCompressedOops) { | |
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8227 movptr(r12_heapbase, ExternalAddress((address)Universe::narrow_oop_base_addr())); |
304 | 8228 } |
8229 } | |
8230 #endif // _LP64 | |
0 | 8231 |
8232 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) { | |
8233 switch (cond) { | |
8234 // Note some conditions are synonyms for others | |
8235 case Assembler::zero: return Assembler::notZero; | |
8236 case Assembler::notZero: return Assembler::zero; | |
8237 case Assembler::less: return Assembler::greaterEqual; | |
8238 case Assembler::lessEqual: return Assembler::greater; | |
8239 case Assembler::greater: return Assembler::lessEqual; | |
8240 case Assembler::greaterEqual: return Assembler::less; | |
8241 case Assembler::below: return Assembler::aboveEqual; | |
8242 case Assembler::belowEqual: return Assembler::above; | |
8243 case Assembler::above: return Assembler::belowEqual; | |
8244 case Assembler::aboveEqual: return Assembler::below; | |
8245 case Assembler::overflow: return Assembler::noOverflow; | |
8246 case Assembler::noOverflow: return Assembler::overflow; | |
8247 case Assembler::negative: return Assembler::positive; | |
8248 case Assembler::positive: return Assembler::negative; | |
8249 case Assembler::parity: return Assembler::noParity; | |
8250 case Assembler::noParity: return Assembler::parity; | |
8251 } | |
8252 ShouldNotReachHere(); return Assembler::overflow; | |
8253 } | |
8254 | |
8255 SkipIfEqual::SkipIfEqual( | |
8256 MacroAssembler* masm, const bool* flag_addr, bool value) { | |
8257 _masm = masm; | |
8258 _masm->cmp8(ExternalAddress((address)flag_addr), value); | |
8259 _masm->jcc(Assembler::equal, _label); | |
8260 } | |
8261 | |
8262 SkipIfEqual::~SkipIfEqual() { | |
8263 _masm->bind(_label); | |
8264 } |