Mercurial > hg > graal-jvmci-8
comparison src/cpu/x86/vm/x86_64.ad @ 12972:59e8ad757e19
8026844: Various Math functions needs intrinsification
Reviewed-by: kvn, twisti
author | rbackman |
---|---|
date | Fri, 18 Oct 2013 10:41:56 +0200 |
parents | 268e7a2178d7 |
children | 7e8bd81ce93e 2b8e28fdf503 |
comparison
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inserted
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12971:3a04e444da6d | 12972:59e8ad757e19 |
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1651 | 1651 |
1652 const RegMask Matcher::mathExactI_result_proj_mask() { | 1652 const RegMask Matcher::mathExactI_result_proj_mask() { |
1653 return INT_RAX_REG_mask(); | 1653 return INT_RAX_REG_mask(); |
1654 } | 1654 } |
1655 | 1655 |
1656 const RegMask Matcher::mathExactL_result_proj_mask() { | |
1657 return LONG_RAX_REG_mask(); | |
1658 } | |
1659 | |
1656 const RegMask Matcher::mathExactI_flags_proj_mask() { | 1660 const RegMask Matcher::mathExactI_flags_proj_mask() { |
1657 return INT_FLAGS_mask(); | 1661 return INT_FLAGS_mask(); |
1658 } | 1662 } |
1659 | 1663 |
1660 %} | 1664 %} |
6960 __ addl($dst$$Register, $src$$constant); | 6964 __ addl($dst$$Register, $src$$constant); |
6961 %} | 6965 %} |
6962 ins_pipe(ialu_reg_reg); | 6966 ins_pipe(ialu_reg_reg); |
6963 %} | 6967 %} |
6964 | 6968 |
6969 instruct addExactI_rReg_mem(rax_RegI dst, memory src, rFlagsReg cr) | |
6970 %{ | |
6971 match(AddExactI dst (LoadI src)); | |
6972 effect(DEF cr); | |
6973 | |
6974 ins_cost(125); // XXX | |
6975 format %{ "addl $dst, $src\t# addExact int" %} | |
6976 ins_encode %{ | |
6977 __ addl($dst$$Register, $src$$Address); | |
6978 %} | |
6979 | |
6980 ins_pipe(ialu_reg_mem); | |
6981 %} | |
6982 | |
6983 instruct addExactL_rReg(rax_RegL dst, rRegL src, rFlagsReg cr) | |
6984 %{ | |
6985 match(AddExactL dst src); | |
6986 effect(DEF cr); | |
6987 | |
6988 format %{ "addq $dst, $src\t# addExact long" %} | |
6989 ins_encode %{ | |
6990 __ addq($dst$$Register, $src$$Register); | |
6991 %} | |
6992 ins_pipe(ialu_reg_reg); | |
6993 %} | |
6994 | |
6995 instruct addExactL_rReg_imm(rax_RegL dst, immL32 src, rFlagsReg cr) | |
6996 %{ | |
6997 match(AddExactL dst src); | |
6998 effect(DEF cr); | |
6999 | |
7000 format %{ "addq $dst, $src\t# addExact long" %} | |
7001 ins_encode %{ | |
7002 __ addq($dst$$Register, $src$$constant); | |
7003 %} | |
7004 ins_pipe(ialu_reg_reg); | |
7005 %} | |
7006 | |
7007 instruct addExactL_rReg_mem(rax_RegL dst, memory src, rFlagsReg cr) | |
7008 %{ | |
7009 match(AddExactL dst (LoadL src)); | |
7010 effect(DEF cr); | |
7011 | |
7012 ins_cost(125); // XXX | |
7013 format %{ "addq $dst, $src\t# addExact long" %} | |
7014 ins_encode %{ | |
7015 __ addq($dst$$Register, $src$$Address); | |
7016 %} | |
7017 | |
7018 ins_pipe(ialu_reg_mem); | |
7019 %} | |
7020 | |
6965 instruct addI_rReg(rRegI dst, rRegI src, rFlagsReg cr) | 7021 instruct addI_rReg(rRegI dst, rRegI src, rFlagsReg cr) |
6966 %{ | 7022 %{ |
6967 match(Set dst (AddI dst src)); | 7023 match(Set dst (AddI dst src)); |
6968 effect(KILL cr); | 7024 effect(KILL cr); |
6969 | 7025 |
7572 opcode(0x81); /* Opcode 81 /5 id */ | 7628 opcode(0x81); /* Opcode 81 /5 id */ |
7573 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src)); | 7629 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src)); |
7574 ins_pipe(ialu_mem_imm); | 7630 ins_pipe(ialu_mem_imm); |
7575 %} | 7631 %} |
7576 | 7632 |
7633 instruct subExactI_rReg(rax_RegI dst, rRegI src, rFlagsReg cr) | |
7634 %{ | |
7635 match(SubExactI dst src); | |
7636 effect(DEF cr); | |
7637 | |
7638 format %{ "subl $dst, $src\t# subExact int" %} | |
7639 ins_encode %{ | |
7640 __ subl($dst$$Register, $src$$Register); | |
7641 %} | |
7642 ins_pipe(ialu_reg_reg); | |
7643 %} | |
7644 | |
7645 instruct subExactI_rReg_imm(rax_RegI dst, immI src, rFlagsReg cr) | |
7646 %{ | |
7647 match(SubExactI dst src); | |
7648 effect(DEF cr); | |
7649 | |
7650 format %{ "subl $dst, $src\t# subExact int" %} | |
7651 ins_encode %{ | |
7652 __ subl($dst$$Register, $src$$constant); | |
7653 %} | |
7654 ins_pipe(ialu_reg_reg); | |
7655 %} | |
7656 | |
7657 instruct subExactI_rReg_mem(rax_RegI dst, memory src, rFlagsReg cr) | |
7658 %{ | |
7659 match(SubExactI dst (LoadI src)); | |
7660 effect(DEF cr); | |
7661 | |
7662 ins_cost(125); | |
7663 format %{ "subl $dst, $src\t# subExact int" %} | |
7664 ins_encode %{ | |
7665 __ subl($dst$$Register, $src$$Address); | |
7666 %} | |
7667 ins_pipe(ialu_reg_mem); | |
7668 %} | |
7669 | |
7670 instruct subExactL_rReg(rax_RegL dst, rRegL src, rFlagsReg cr) | |
7671 %{ | |
7672 match(SubExactL dst src); | |
7673 effect(DEF cr); | |
7674 | |
7675 format %{ "subq $dst, $src\t# subExact long" %} | |
7676 ins_encode %{ | |
7677 __ subq($dst$$Register, $src$$Register); | |
7678 %} | |
7679 ins_pipe(ialu_reg_reg); | |
7680 %} | |
7681 | |
7682 instruct subExactL_rReg_imm(rax_RegL dst, immL32 src, rFlagsReg cr) | |
7683 %{ | |
7684 match(SubExactL dst (LoadL src)); | |
7685 effect(DEF cr); | |
7686 | |
7687 format %{ "subq $dst, $src\t# subExact long" %} | |
7688 ins_encode %{ | |
7689 __ subq($dst$$Register, $src$$constant); | |
7690 %} | |
7691 ins_pipe(ialu_reg_reg); | |
7692 %} | |
7693 | |
7694 instruct subExactL_rReg_mem(rax_RegI dst, memory src, rFlagsReg cr) | |
7695 %{ | |
7696 match(SubExactI dst src); | |
7697 effect(DEF cr); | |
7698 | |
7699 ins_cost(125); | |
7700 format %{ "subq $dst, $src\t# subExact long" %} | |
7701 ins_encode %{ | |
7702 __ subq($dst$$Register, $src$$Address); | |
7703 %} | |
7704 ins_pipe(ialu_reg_mem); | |
7705 %} | |
7706 | |
7577 instruct subL_rReg(rRegL dst, rRegL src, rFlagsReg cr) | 7707 instruct subL_rReg(rRegL dst, rRegL src, rFlagsReg cr) |
7578 %{ | 7708 %{ |
7579 match(Set dst (SubL dst src)); | 7709 match(Set dst (SubL dst src)); |
7580 effect(KILL cr); | 7710 effect(KILL cr); |
7581 | 7711 |
7688 opcode(0xF7, 0x03); // Opcode F7 /3 | 7818 opcode(0xF7, 0x03); // Opcode F7 /3 |
7689 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); | 7819 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); |
7690 ins_pipe(ialu_reg); | 7820 ins_pipe(ialu_reg); |
7691 %} | 7821 %} |
7692 | 7822 |
7823 instruct negExactI_rReg(rax_RegI dst, rFlagsReg cr) | |
7824 %{ | |
7825 match(NegExactI dst); | |
7826 effect(KILL cr); | |
7827 | |
7828 format %{ "negl $dst\t# negExact int" %} | |
7829 ins_encode %{ | |
7830 __ negl($dst$$Register); | |
7831 %} | |
7832 ins_pipe(ialu_reg); | |
7833 %} | |
7834 | |
7835 instruct negExactL_rReg(rax_RegL dst, rFlagsReg cr) | |
7836 %{ | |
7837 match(NegExactL dst); | |
7838 effect(KILL cr); | |
7839 | |
7840 format %{ "negq $dst\t# negExact long" %} | |
7841 ins_encode %{ | |
7842 __ negq($dst$$Register); | |
7843 %} | |
7844 ins_pipe(ialu_reg); | |
7845 %} | |
7846 | |
7693 | 7847 |
7694 //----------Multiplication/Division Instructions------------------------------- | 7848 //----------Multiplication/Division Instructions------------------------------- |
7695 // Integer Multiplication Instructions | 7849 // Integer Multiplication Instructions |
7696 // Multiply Register | 7850 // Multiply Register |
7697 | 7851 |
7803 ins_cost(300); | 7957 ins_cost(300); |
7804 format %{ "imulq RDX:RAX, RAX, $src\t# mulhi" %} | 7958 format %{ "imulq RDX:RAX, RAX, $src\t# mulhi" %} |
7805 opcode(0xF7, 0x5); /* Opcode F7 /5 */ | 7959 opcode(0xF7, 0x5); /* Opcode F7 /5 */ |
7806 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src)); | 7960 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src)); |
7807 ins_pipe(ialu_reg_reg_alu0); | 7961 ins_pipe(ialu_reg_reg_alu0); |
7962 %} | |
7963 | |
7964 | |
7965 instruct mulExactI_rReg(rax_RegI dst, rRegI src, rFlagsReg cr) | |
7966 %{ | |
7967 match(MulExactI dst src); | |
7968 effect(DEF cr); | |
7969 | |
7970 ins_cost(300); | |
7971 format %{ "imull $dst, $src\t# mulExact int" %} | |
7972 ins_encode %{ | |
7973 __ imull($dst$$Register, $src$$Register); | |
7974 %} | |
7975 ins_pipe(ialu_reg_reg_alu0); | |
7976 %} | |
7977 | |
7978 | |
7979 instruct mulExactI_rReg_imm(rax_RegI dst, rRegI src, immI imm, rFlagsReg cr) | |
7980 %{ | |
7981 match(MulExactI src imm); | |
7982 effect(DEF cr); | |
7983 | |
7984 ins_cost(300); | |
7985 format %{ "imull $dst, $src, $imm\t# mulExact int" %} | |
7986 ins_encode %{ | |
7987 __ imull($dst$$Register, $src$$Register, $imm$$constant); | |
7988 %} | |
7989 ins_pipe(ialu_reg_reg_alu0); | |
7990 %} | |
7991 | |
7992 instruct mulExactI_rReg_mem(rax_RegI dst, memory src, rFlagsReg cr) | |
7993 %{ | |
7994 match(MulExactI dst (LoadI src)); | |
7995 effect(DEF cr); | |
7996 | |
7997 ins_cost(350); | |
7998 format %{ "imull $dst, $src\t# mulExact int" %} | |
7999 ins_encode %{ | |
8000 __ imull($dst$$Register, $src$$Address); | |
8001 %} | |
8002 ins_pipe(ialu_reg_mem_alu0); | |
8003 %} | |
8004 | |
8005 instruct mulExactL_rReg(rax_RegL dst, rRegL src, rFlagsReg cr) | |
8006 %{ | |
8007 match(MulExactL dst src); | |
8008 effect(DEF cr); | |
8009 | |
8010 ins_cost(300); | |
8011 format %{ "imulq $dst, $src\t# mulExact long" %} | |
8012 ins_encode %{ | |
8013 __ imulq($dst$$Register, $src$$Register); | |
8014 %} | |
8015 ins_pipe(ialu_reg_reg_alu0); | |
8016 %} | |
8017 | |
8018 instruct mulExactL_rReg_imm(rax_RegL dst, rRegL src, immL32 imm, rFlagsReg cr) | |
8019 %{ | |
8020 match(MulExactL src imm); | |
8021 effect(DEF cr); | |
8022 | |
8023 ins_cost(300); | |
8024 format %{ "imulq $dst, $src, $imm\t# mulExact long" %} | |
8025 ins_encode %{ | |
8026 __ imulq($dst$$Register, $src$$Register, $imm$$constant); | |
8027 %} | |
8028 ins_pipe(ialu_reg_reg_alu0); | |
8029 %} | |
8030 | |
8031 instruct mulExactL_rReg_mem(rax_RegL dst, memory src, rFlagsReg cr) | |
8032 %{ | |
8033 match(MulExactL dst (LoadL src)); | |
8034 effect(DEF cr); | |
8035 | |
8036 ins_cost(350); | |
8037 format %{ "imulq $dst, $src\t# mulExact long" %} | |
8038 ins_encode %{ | |
8039 __ imulq($dst$$Register, $src$$Address); | |
8040 %} | |
8041 ins_pipe(ialu_reg_mem_alu0); | |
7808 %} | 8042 %} |
7809 | 8043 |
7810 instruct divI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div, | 8044 instruct divI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div, |
7811 rFlagsReg cr) | 8045 rFlagsReg cr) |
7812 %{ | 8046 %{ |