Mercurial > hg > graal-jvmci-8
diff src/cpu/x86/vm/x86_64.ad @ 12972:59e8ad757e19
8026844: Various Math functions needs intrinsification
Reviewed-by: kvn, twisti
author | rbackman |
---|---|
date | Fri, 18 Oct 2013 10:41:56 +0200 |
parents | 268e7a2178d7 |
children | 7e8bd81ce93e 2b8e28fdf503 |
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--- a/src/cpu/x86/vm/x86_64.ad Wed Oct 23 16:25:48 2013 -0700 +++ b/src/cpu/x86/vm/x86_64.ad Fri Oct 18 10:41:56 2013 +0200 @@ -1653,6 +1653,10 @@ return INT_RAX_REG_mask(); } +const RegMask Matcher::mathExactL_result_proj_mask() { + return LONG_RAX_REG_mask(); +} + const RegMask Matcher::mathExactI_flags_proj_mask() { return INT_FLAGS_mask(); } @@ -6962,6 +6966,58 @@ ins_pipe(ialu_reg_reg); %} +instruct addExactI_rReg_mem(rax_RegI dst, memory src, rFlagsReg cr) +%{ + match(AddExactI dst (LoadI src)); + effect(DEF cr); + + ins_cost(125); // XXX + format %{ "addl $dst, $src\t# addExact int" %} + ins_encode %{ + __ addl($dst$$Register, $src$$Address); + %} + + ins_pipe(ialu_reg_mem); +%} + +instruct addExactL_rReg(rax_RegL dst, rRegL src, rFlagsReg cr) +%{ + match(AddExactL dst src); + effect(DEF cr); + + format %{ "addq $dst, $src\t# addExact long" %} + ins_encode %{ + __ addq($dst$$Register, $src$$Register); + %} + ins_pipe(ialu_reg_reg); +%} + +instruct addExactL_rReg_imm(rax_RegL dst, immL32 src, rFlagsReg cr) +%{ + match(AddExactL dst src); + effect(DEF cr); + + format %{ "addq $dst, $src\t# addExact long" %} + ins_encode %{ + __ addq($dst$$Register, $src$$constant); + %} + ins_pipe(ialu_reg_reg); +%} + +instruct addExactL_rReg_mem(rax_RegL dst, memory src, rFlagsReg cr) +%{ + match(AddExactL dst (LoadL src)); + effect(DEF cr); + + ins_cost(125); // XXX + format %{ "addq $dst, $src\t# addExact long" %} + ins_encode %{ + __ addq($dst$$Register, $src$$Address); + %} + + ins_pipe(ialu_reg_mem); +%} + instruct addI_rReg(rRegI dst, rRegI src, rFlagsReg cr) %{ match(Set dst (AddI dst src)); @@ -7574,6 +7630,80 @@ ins_pipe(ialu_mem_imm); %} +instruct subExactI_rReg(rax_RegI dst, rRegI src, rFlagsReg cr) +%{ + match(SubExactI dst src); + effect(DEF cr); + + format %{ "subl $dst, $src\t# subExact int" %} + ins_encode %{ + __ subl($dst$$Register, $src$$Register); + %} + ins_pipe(ialu_reg_reg); +%} + +instruct subExactI_rReg_imm(rax_RegI dst, immI src, rFlagsReg cr) +%{ + match(SubExactI dst src); + effect(DEF cr); + + format %{ "subl $dst, $src\t# subExact int" %} + ins_encode %{ + __ subl($dst$$Register, $src$$constant); + %} + ins_pipe(ialu_reg_reg); +%} + +instruct subExactI_rReg_mem(rax_RegI dst, memory src, rFlagsReg cr) +%{ + match(SubExactI dst (LoadI src)); + effect(DEF cr); + + ins_cost(125); + format %{ "subl $dst, $src\t# subExact int" %} + ins_encode %{ + __ subl($dst$$Register, $src$$Address); + %} + ins_pipe(ialu_reg_mem); +%} + +instruct subExactL_rReg(rax_RegL dst, rRegL src, rFlagsReg cr) +%{ + match(SubExactL dst src); + effect(DEF cr); + + format %{ "subq $dst, $src\t# subExact long" %} + ins_encode %{ + __ subq($dst$$Register, $src$$Register); + %} + ins_pipe(ialu_reg_reg); +%} + +instruct subExactL_rReg_imm(rax_RegL dst, immL32 src, rFlagsReg cr) +%{ + match(SubExactL dst (LoadL src)); + effect(DEF cr); + + format %{ "subq $dst, $src\t# subExact long" %} + ins_encode %{ + __ subq($dst$$Register, $src$$constant); + %} + ins_pipe(ialu_reg_reg); +%} + +instruct subExactL_rReg_mem(rax_RegI dst, memory src, rFlagsReg cr) +%{ + match(SubExactI dst src); + effect(DEF cr); + + ins_cost(125); + format %{ "subq $dst, $src\t# subExact long" %} + ins_encode %{ + __ subq($dst$$Register, $src$$Address); + %} + ins_pipe(ialu_reg_mem); +%} + instruct subL_rReg(rRegL dst, rRegL src, rFlagsReg cr) %{ match(Set dst (SubL dst src)); @@ -7690,6 +7820,30 @@ ins_pipe(ialu_reg); %} +instruct negExactI_rReg(rax_RegI dst, rFlagsReg cr) +%{ + match(NegExactI dst); + effect(KILL cr); + + format %{ "negl $dst\t# negExact int" %} + ins_encode %{ + __ negl($dst$$Register); + %} + ins_pipe(ialu_reg); +%} + +instruct negExactL_rReg(rax_RegL dst, rFlagsReg cr) +%{ + match(NegExactL dst); + effect(KILL cr); + + format %{ "negq $dst\t# negExact long" %} + ins_encode %{ + __ negq($dst$$Register); + %} + ins_pipe(ialu_reg); +%} + //----------Multiplication/Division Instructions------------------------------- // Integer Multiplication Instructions @@ -7807,6 +7961,86 @@ ins_pipe(ialu_reg_reg_alu0); %} + +instruct mulExactI_rReg(rax_RegI dst, rRegI src, rFlagsReg cr) +%{ + match(MulExactI dst src); + effect(DEF cr); + + ins_cost(300); + format %{ "imull $dst, $src\t# mulExact int" %} + ins_encode %{ + __ imull($dst$$Register, $src$$Register); + %} + ins_pipe(ialu_reg_reg_alu0); +%} + + +instruct mulExactI_rReg_imm(rax_RegI dst, rRegI src, immI imm, rFlagsReg cr) +%{ + match(MulExactI src imm); + effect(DEF cr); + + ins_cost(300); + format %{ "imull $dst, $src, $imm\t# mulExact int" %} + ins_encode %{ + __ imull($dst$$Register, $src$$Register, $imm$$constant); + %} + ins_pipe(ialu_reg_reg_alu0); +%} + +instruct mulExactI_rReg_mem(rax_RegI dst, memory src, rFlagsReg cr) +%{ + match(MulExactI dst (LoadI src)); + effect(DEF cr); + + ins_cost(350); + format %{ "imull $dst, $src\t# mulExact int" %} + ins_encode %{ + __ imull($dst$$Register, $src$$Address); + %} + ins_pipe(ialu_reg_mem_alu0); +%} + +instruct mulExactL_rReg(rax_RegL dst, rRegL src, rFlagsReg cr) +%{ + match(MulExactL dst src); + effect(DEF cr); + + ins_cost(300); + format %{ "imulq $dst, $src\t# mulExact long" %} + ins_encode %{ + __ imulq($dst$$Register, $src$$Register); + %} + ins_pipe(ialu_reg_reg_alu0); +%} + +instruct mulExactL_rReg_imm(rax_RegL dst, rRegL src, immL32 imm, rFlagsReg cr) +%{ + match(MulExactL src imm); + effect(DEF cr); + + ins_cost(300); + format %{ "imulq $dst, $src, $imm\t# mulExact long" %} + ins_encode %{ + __ imulq($dst$$Register, $src$$Register, $imm$$constant); + %} + ins_pipe(ialu_reg_reg_alu0); +%} + +instruct mulExactL_rReg_mem(rax_RegL dst, memory src, rFlagsReg cr) +%{ + match(MulExactL dst (LoadL src)); + effect(DEF cr); + + ins_cost(350); + format %{ "imulq $dst, $src\t# mulExact long" %} + ins_encode %{ + __ imulq($dst$$Register, $src$$Address); + %} + ins_pipe(ialu_reg_mem_alu0); +%} + instruct divI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div, rFlagsReg cr) %{