Mercurial > hg > graal-jvmci-8
comparison src/cpu/x86/vm/x86.ad @ 6183:6f8f439e247d
7177923: SIGBUS on sparc in compiled code for java.util.Calendar.clear()
Summary: disable vectorization of a memory access with more elements per vector than one which is used for alignment on sparc
Reviewed-by: twisti
author | kvn |
---|---|
date | Tue, 19 Jun 2012 15:12:56 -0700 |
parents | 8c92982cbbc4 |
children | 2c368ea3e844 |
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6182:765ee2d1674b | 6183:6f8f439e247d |
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2059 %} | 2059 %} |
2060 | 2060 |
2061 // Integer could be loaded into xmm register directly from memory. | 2061 // Integer could be loaded into xmm register directly from memory. |
2062 instruct Repl2I_mem(vecD dst, memory mem) %{ | 2062 instruct Repl2I_mem(vecD dst, memory mem) %{ |
2063 predicate(n->as_Vector()->length() == 2); | 2063 predicate(n->as_Vector()->length() == 2); |
2064 match(Set dst (ReplicateI mem)); | 2064 match(Set dst (ReplicateI (LoadVector mem))); |
2065 format %{ "movd $dst,$mem\n\t" | 2065 format %{ "movd $dst,$mem\n\t" |
2066 "pshufd $dst,$dst,0x00\t! replicate2I" %} | 2066 "pshufd $dst,$dst,0x00\t! replicate2I" %} |
2067 ins_encode %{ | 2067 ins_encode %{ |
2068 __ movdl($dst$$XMMRegister, $mem$$Address); | 2068 __ movdl($dst$$XMMRegister, $mem$$Address); |
2069 __ pshufd($dst$$XMMRegister, $dst$$XMMRegister, 0x00); | 2069 __ pshufd($dst$$XMMRegister, $dst$$XMMRegister, 0x00); |
2071 ins_pipe( fpu_reg_reg ); | 2071 ins_pipe( fpu_reg_reg ); |
2072 %} | 2072 %} |
2073 | 2073 |
2074 instruct Repl4I_mem(vecX dst, memory mem) %{ | 2074 instruct Repl4I_mem(vecX dst, memory mem) %{ |
2075 predicate(n->as_Vector()->length() == 4); | 2075 predicate(n->as_Vector()->length() == 4); |
2076 match(Set dst (ReplicateI mem)); | 2076 match(Set dst (ReplicateI (LoadVector mem))); |
2077 format %{ "movd $dst,$mem\n\t" | 2077 format %{ "movd $dst,$mem\n\t" |
2078 "pshufd $dst,$dst,0x00\t! replicate4I" %} | 2078 "pshufd $dst,$dst,0x00\t! replicate4I" %} |
2079 ins_encode %{ | 2079 ins_encode %{ |
2080 __ movdl($dst$$XMMRegister, $mem$$Address); | 2080 __ movdl($dst$$XMMRegister, $mem$$Address); |
2081 __ pshufd($dst$$XMMRegister, $dst$$XMMRegister, 0x00); | 2081 __ pshufd($dst$$XMMRegister, $dst$$XMMRegister, 0x00); |
2083 ins_pipe( pipe_slow ); | 2083 ins_pipe( pipe_slow ); |
2084 %} | 2084 %} |
2085 | 2085 |
2086 instruct Repl8I_mem(vecY dst, memory mem) %{ | 2086 instruct Repl8I_mem(vecY dst, memory mem) %{ |
2087 predicate(n->as_Vector()->length() == 8); | 2087 predicate(n->as_Vector()->length() == 8); |
2088 match(Set dst (ReplicateI mem)); | 2088 match(Set dst (ReplicateI (LoadVector mem))); |
2089 format %{ "movd $dst,$mem\n\t" | 2089 format %{ "movd $dst,$mem\n\t" |
2090 "pshufd $dst,$dst,0x00\n\t" | 2090 "pshufd $dst,$dst,0x00\n\t" |
2091 "vinsertf128h $dst,$dst,$dst\t! replicate8I" %} | 2091 "vinsertf128h $dst,$dst,$dst\t! replicate8I" %} |
2092 ins_encode %{ | 2092 ins_encode %{ |
2093 __ movdl($dst$$XMMRegister, $mem$$Address); | 2093 __ movdl($dst$$XMMRegister, $mem$$Address); |
2223 %} | 2223 %} |
2224 | 2224 |
2225 // Long could be loaded into xmm register directly from memory. | 2225 // Long could be loaded into xmm register directly from memory. |
2226 instruct Repl2L_mem(vecX dst, memory mem) %{ | 2226 instruct Repl2L_mem(vecX dst, memory mem) %{ |
2227 predicate(n->as_Vector()->length() == 2); | 2227 predicate(n->as_Vector()->length() == 2); |
2228 match(Set dst (ReplicateL mem)); | 2228 match(Set dst (ReplicateL (LoadVector mem))); |
2229 format %{ "movq $dst,$mem\n\t" | 2229 format %{ "movq $dst,$mem\n\t" |
2230 "movlhps $dst,$dst\t! replicate2L" %} | 2230 "movlhps $dst,$dst\t! replicate2L" %} |
2231 ins_encode %{ | 2231 ins_encode %{ |
2232 __ movq($dst$$XMMRegister, $mem$$Address); | 2232 __ movq($dst$$XMMRegister, $mem$$Address); |
2233 __ movlhps($dst$$XMMRegister, $dst$$XMMRegister); | 2233 __ movlhps($dst$$XMMRegister, $dst$$XMMRegister); |
2235 ins_pipe( pipe_slow ); | 2235 ins_pipe( pipe_slow ); |
2236 %} | 2236 %} |
2237 | 2237 |
2238 instruct Repl4L_mem(vecY dst, memory mem) %{ | 2238 instruct Repl4L_mem(vecY dst, memory mem) %{ |
2239 predicate(n->as_Vector()->length() == 4); | 2239 predicate(n->as_Vector()->length() == 4); |
2240 match(Set dst (ReplicateL mem)); | 2240 match(Set dst (ReplicateL (LoadVector mem))); |
2241 format %{ "movq $dst,$mem\n\t" | 2241 format %{ "movq $dst,$mem\n\t" |
2242 "movlhps $dst,$dst\n\t" | 2242 "movlhps $dst,$dst\n\t" |
2243 "vinsertf128h $dst,$dst,$dst\t! replicate4L" %} | 2243 "vinsertf128h $dst,$dst,$dst\t! replicate4L" %} |
2244 ins_encode %{ | 2244 ins_encode %{ |
2245 __ movq($dst$$XMMRegister, $mem$$Address); | 2245 __ movq($dst$$XMMRegister, $mem$$Address); |