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comparison src/share/vm/adlc/formssel.cpp @ 6179:8c92982cbbc4

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7119644: Increase superword's vector size up to 256 bits Summary: Increase vector size up to 256-bits for YMM AVX registers on x86. Reviewed-by: never, twisti, roland
author kvn
date Fri, 15 Jun 2012 01:25:19 -0700
parents 8b0a4867acf0
children da91efe96a93
comparison
equal deleted inserted replaced
6146:eba1d5bce9e8 6179:8c92982cbbc4
1 /* 1 /*
2 * Copyright (c) 1998, 2010, Oracle and/or its affiliates. All rights reserved. 2 * Copyright (c) 1998, 2012, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 * 4 *
5 * This code is free software; you can redistribute it and/or modify it 5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as 6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation. 7 * published by the Free Software Foundation.
430 if( _matrule == NULL ) return Form::none; 430 if( _matrule == NULL ) return Form::none;
431 431
432 return _matrule->is_ideal_store(); 432 return _matrule->is_ideal_store();
433 } 433 }
434 434
435 // Return 'true' if this instruction matches an ideal vector node
436 bool InstructForm::is_vector() const {
437 if( _matrule == NULL ) return false;
438
439 return _matrule->is_vector();
440 }
441
442
435 // Return the input register that must match the output register 443 // Return the input register that must match the output register
436 // If this is not required, return 0 444 // If this is not required, return 0
437 uint InstructForm::two_address(FormDict &globals) { 445 uint InstructForm::two_address(FormDict &globals) {
438 uint matching_input = 0; 446 uint matching_input = 0;
439 if(_components.count() == 0) return 0; 447 if(_components.count() == 0) return 0;
748 !strcmp(_matrule->_rChild->_opType,"CheckCastPP")) ) return true; 756 !strcmp(_matrule->_rChild->_opType,"CheckCastPP")) ) return true;
749 else if ( is_ideal_load() == Form::idealP ) return true; 757 else if ( is_ideal_load() == Form::idealP ) return true;
750 else if ( is_ideal_store() != Form::none ) return true; 758 else if ( is_ideal_store() != Form::none ) return true;
751 759
752 if (needs_base_oop_edge(globals)) return true; 760 if (needs_base_oop_edge(globals)) return true;
761
762 if (is_vector()) return true;
763 if (is_mach_constant()) return true;
753 764
754 return false; 765 return false;
755 } 766 }
756 767
757 768
3379 int MatchNode::needs_ideal_memory_edge(FormDict &globals) const { 3390 int MatchNode::needs_ideal_memory_edge(FormDict &globals) const {
3380 static const char *needs_ideal_memory_list[] = { 3391 static const char *needs_ideal_memory_list[] = {
3381 "StoreI","StoreL","StoreP","StoreN","StoreD","StoreF" , 3392 "StoreI","StoreL","StoreP","StoreN","StoreD","StoreF" ,
3382 "StoreB","StoreC","Store" ,"StoreFP", 3393 "StoreB","StoreC","Store" ,"StoreFP",
3383 "LoadI", "LoadUI2L", "LoadL", "LoadP" ,"LoadN", "LoadD" ,"LoadF" , 3394 "LoadI", "LoadUI2L", "LoadL", "LoadP" ,"LoadN", "LoadD" ,"LoadF" ,
3384 "LoadB" , "LoadUB", "LoadUS" ,"LoadS" ,"Load" , 3395 "LoadB" , "LoadUB", "LoadUS" ,"LoadS" ,"Load" ,
3385 "Store4I","Store2I","Store2L","Store2D","Store4F","Store2F","Store16B", 3396 "StoreVector", "LoadVector",
3386 "Store8B","Store4B","Store8C","Store4C","Store2C",
3387 "Load4I" ,"Load2I" ,"Load2L" ,"Load2D" ,"Load4F" ,"Load2F" ,"Load16B" ,
3388 "Load8B" ,"Load4B" ,"Load8C" ,"Load4C" ,"Load2C" ,"Load8S", "Load4S","Load2S",
3389 "LoadRange", "LoadKlass", "LoadNKlass", "LoadL_unaligned", "LoadD_unaligned", 3397 "LoadRange", "LoadKlass", "LoadNKlass", "LoadL_unaligned", "LoadD_unaligned",
3390 "LoadPLocked", 3398 "LoadPLocked",
3391 "StorePConditional", "StoreIConditional", "StoreLConditional", 3399 "StorePConditional", "StoreIConditional", "StoreLConditional",
3392 "CompareAndSwapI", "CompareAndSwapL", "CompareAndSwapP", "CompareAndSwapN", 3400 "CompareAndSwapI", "CompareAndSwapL", "CompareAndSwapP", "CompareAndSwapN",
3393 "StoreCM", 3401 "StoreCM",
3820 strcmp(opType,"RegP")==0 || 3828 strcmp(opType,"RegP")==0 ||
3821 strcmp(opType,"RegN")==0 || 3829 strcmp(opType,"RegN")==0 ||
3822 strcmp(opType,"RegL")==0 || 3830 strcmp(opType,"RegL")==0 ||
3823 strcmp(opType,"RegF")==0 || 3831 strcmp(opType,"RegF")==0 ||
3824 strcmp(opType,"RegD")==0 || 3832 strcmp(opType,"RegD")==0 ||
3833 strcmp(opType,"VecS")==0 ||
3834 strcmp(opType,"VecD")==0 ||
3835 strcmp(opType,"VecX")==0 ||
3836 strcmp(opType,"VecY")==0 ||
3825 strcmp(opType,"Reg" )==0) ) { 3837 strcmp(opType,"Reg" )==0) ) {
3826 return 1; 3838 return 1;
3827 } 3839 }
3828 } 3840 }
3829 return 0; 3841 return 0;
3936 strcmp(opType,"RoundFloat")==0 || 3948 strcmp(opType,"RoundFloat")==0 ||
3937 strcmp(opType,"ReverseBytesI")==0 || 3949 strcmp(opType,"ReverseBytesI")==0 ||
3938 strcmp(opType,"ReverseBytesL")==0 || 3950 strcmp(opType,"ReverseBytesL")==0 ||
3939 strcmp(opType,"ReverseBytesUS")==0 || 3951 strcmp(opType,"ReverseBytesUS")==0 ||
3940 strcmp(opType,"ReverseBytesS")==0 || 3952 strcmp(opType,"ReverseBytesS")==0 ||
3941 strcmp(opType,"Replicate16B")==0 || 3953 strcmp(opType,"ReplicateB")==0 ||
3942 strcmp(opType,"Replicate8B")==0 || 3954 strcmp(opType,"ReplicateS")==0 ||
3943 strcmp(opType,"Replicate4B")==0 || 3955 strcmp(opType,"ReplicateI")==0 ||
3944 strcmp(opType,"Replicate8C")==0 || 3956 strcmp(opType,"ReplicateL")==0 ||
3945 strcmp(opType,"Replicate4C")==0 || 3957 strcmp(opType,"ReplicateF")==0 ||
3946 strcmp(opType,"Replicate8S")==0 || 3958 strcmp(opType,"ReplicateD")==0 ||
3947 strcmp(opType,"Replicate4S")==0 ||
3948 strcmp(opType,"Replicate4I")==0 ||
3949 strcmp(opType,"Replicate2I")==0 ||
3950 strcmp(opType,"Replicate2L")==0 ||
3951 strcmp(opType,"Replicate4F")==0 ||
3952 strcmp(opType,"Replicate2F")==0 ||
3953 strcmp(opType,"Replicate2D")==0 ||
3954 0 /* 0 to line up columns nicely */ ) 3959 0 /* 0 to line up columns nicely */ )
3955 return 1; 3960 return 1;
3956 } 3961 }
3957 return 0; 3962 return 0;
3958 } 3963 }
4030 const char *opType = _rChild->_opType; 4035 const char *opType = _rChild->_opType;
4031 ideal_load = is_load_from_memory(opType); 4036 ideal_load = is_load_from_memory(opType);
4032 } 4037 }
4033 4038
4034 return ideal_load; 4039 return ideal_load;
4040 }
4041
4042 bool MatchRule::is_vector() const {
4043 if( _rChild ) {
4044 const char *opType = _rChild->_opType;
4045 if( strcmp(opType,"ReplicateB")==0 ||
4046 strcmp(opType,"ReplicateS")==0 ||
4047 strcmp(opType,"ReplicateI")==0 ||
4048 strcmp(opType,"ReplicateL")==0 ||
4049 strcmp(opType,"ReplicateF")==0 ||
4050 strcmp(opType,"ReplicateD")==0 ||
4051 strcmp(opType,"LoadVector")==0 ||
4052 strcmp(opType,"StoreVector")==0 ||
4053 0 /* 0 to line up columns nicely */ )
4054 return true;
4055 }
4056 return false;
4035 } 4057 }
4036 4058
4037 4059
4038 bool MatchRule::skip_antidep_check() const { 4060 bool MatchRule::skip_antidep_check() const {
4039 // Some loads operate on what is effectively immutable memory so we 4061 // Some loads operate on what is effectively immutable memory so we