Mercurial > hg > graal-jvmci-8
diff src/share/vm/adlc/formssel.cpp @ 6179:8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
Summary: Increase vector size up to 256-bits for YMM AVX registers on x86.
Reviewed-by: never, twisti, roland
author | kvn |
---|---|
date | Fri, 15 Jun 2012 01:25:19 -0700 |
parents | 8b0a4867acf0 |
children | da91efe96a93 |
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--- a/src/share/vm/adlc/formssel.cpp Thu Jun 14 14:59:52 2012 -0700 +++ b/src/share/vm/adlc/formssel.cpp Fri Jun 15 01:25:19 2012 -0700 @@ -1,5 +1,5 @@ /* - * Copyright (c) 1998, 2010, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 1998, 2012, Oracle and/or its affiliates. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it @@ -432,6 +432,14 @@ return _matrule->is_ideal_store(); } +// Return 'true' if this instruction matches an ideal vector node +bool InstructForm::is_vector() const { + if( _matrule == NULL ) return false; + + return _matrule->is_vector(); +} + + // Return the input register that must match the output register // If this is not required, return 0 uint InstructForm::two_address(FormDict &globals) { @@ -751,6 +759,9 @@ if (needs_base_oop_edge(globals)) return true; + if (is_vector()) return true; + if (is_mach_constant()) return true; + return false; } @@ -3381,11 +3392,8 @@ "StoreI","StoreL","StoreP","StoreN","StoreD","StoreF" , "StoreB","StoreC","Store" ,"StoreFP", "LoadI", "LoadUI2L", "LoadL", "LoadP" ,"LoadN", "LoadD" ,"LoadF" , - "LoadB" , "LoadUB", "LoadUS" ,"LoadS" ,"Load" , - "Store4I","Store2I","Store2L","Store2D","Store4F","Store2F","Store16B", - "Store8B","Store4B","Store8C","Store4C","Store2C", - "Load4I" ,"Load2I" ,"Load2L" ,"Load2D" ,"Load4F" ,"Load2F" ,"Load16B" , - "Load8B" ,"Load4B" ,"Load8C" ,"Load4C" ,"Load2C" ,"Load8S", "Load4S","Load2S", + "LoadB" , "LoadUB", "LoadUS" ,"LoadS" ,"Load" , + "StoreVector", "LoadVector", "LoadRange", "LoadKlass", "LoadNKlass", "LoadL_unaligned", "LoadD_unaligned", "LoadPLocked", "StorePConditional", "StoreIConditional", "StoreLConditional", @@ -3822,6 +3830,10 @@ strcmp(opType,"RegL")==0 || strcmp(opType,"RegF")==0 || strcmp(opType,"RegD")==0 || + strcmp(opType,"VecS")==0 || + strcmp(opType,"VecD")==0 || + strcmp(opType,"VecX")==0 || + strcmp(opType,"VecY")==0 || strcmp(opType,"Reg" )==0) ) { return 1; } @@ -3938,19 +3950,12 @@ strcmp(opType,"ReverseBytesL")==0 || strcmp(opType,"ReverseBytesUS")==0 || strcmp(opType,"ReverseBytesS")==0 || - strcmp(opType,"Replicate16B")==0 || - strcmp(opType,"Replicate8B")==0 || - strcmp(opType,"Replicate4B")==0 || - strcmp(opType,"Replicate8C")==0 || - strcmp(opType,"Replicate4C")==0 || - strcmp(opType,"Replicate8S")==0 || - strcmp(opType,"Replicate4S")==0 || - strcmp(opType,"Replicate4I")==0 || - strcmp(opType,"Replicate2I")==0 || - strcmp(opType,"Replicate2L")==0 || - strcmp(opType,"Replicate4F")==0 || - strcmp(opType,"Replicate2F")==0 || - strcmp(opType,"Replicate2D")==0 || + strcmp(opType,"ReplicateB")==0 || + strcmp(opType,"ReplicateS")==0 || + strcmp(opType,"ReplicateI")==0 || + strcmp(opType,"ReplicateL")==0 || + strcmp(opType,"ReplicateF")==0 || + strcmp(opType,"ReplicateD")==0 || 0 /* 0 to line up columns nicely */ ) return 1; } @@ -4034,6 +4039,23 @@ return ideal_load; } +bool MatchRule::is_vector() const { + if( _rChild ) { + const char *opType = _rChild->_opType; + if( strcmp(opType,"ReplicateB")==0 || + strcmp(opType,"ReplicateS")==0 || + strcmp(opType,"ReplicateI")==0 || + strcmp(opType,"ReplicateL")==0 || + strcmp(opType,"ReplicateF")==0 || + strcmp(opType,"ReplicateD")==0 || + strcmp(opType,"LoadVector")==0 || + strcmp(opType,"StoreVector")==0 || + 0 /* 0 to line up columns nicely */ ) + return true; + } + return false; +} + bool MatchRule::skip_antidep_check() const { // Some loads operate on what is effectively immutable memory so we