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comparison src/cpu/sparc/vm/sparc.ad @ 4047:d8cb48376797

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7097546: Optimize use of CMOVE instructions Summary: Avoid CMove in a loop if possible. May generate CMove if it could be moved outside a loop. Reviewed-by: never
author kvn
date Wed, 26 Oct 2011 06:08:56 -0700
parents 4bac06a82bc3
children 6729bbc1fcd6
comparison
equal deleted inserted replaced
4046:e69a66a1457b 4047:d8cb48376797
1857 // No scaling for the parameter the ClearArray node. 1857 // No scaling for the parameter the ClearArray node.
1858 const bool Matcher::init_array_count_is_in_bytes = true; 1858 const bool Matcher::init_array_count_is_in_bytes = true;
1859 1859
1860 // Threshold size for cleararray. 1860 // Threshold size for cleararray.
1861 const int Matcher::init_array_short_size = 8 * BytesPerLong; 1861 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1862
1863 // No additional cost for CMOVL.
1864 const int Matcher::long_cmove_cost() { return 0; }
1865
1866 // CMOVF/CMOVD are expensive on T4 and on SPARC64.
1867 const int Matcher::float_cmove_cost() {
1868 return (VM_Version::is_T4() || VM_Version::is_sparc64()) ? ConditionalMoveLimit : 0;
1869 }
1862 1870
1863 // Should the Matcher clone shifts on addressing modes, expecting them to 1871 // Should the Matcher clone shifts on addressing modes, expecting them to
1864 // be subsumed into complex addressing expressions or compute them into 1872 // be subsumed into complex addressing expressions or compute them into
1865 // registers? True for Intel but false for most RISCs 1873 // registers? True for Intel but false for most RISCs
1866 const bool Matcher::clone_shift_expressions = false; 1874 const bool Matcher::clone_shift_expressions = false;