Mercurial > hg > graal-jvmci-8
diff src/cpu/sparc/vm/sparc.ad @ 4047:d8cb48376797
7097546: Optimize use of CMOVE instructions
Summary: Avoid CMove in a loop if possible. May generate CMove if it could be moved outside a loop.
Reviewed-by: never
| author | kvn |
|---|---|
| date | Wed, 26 Oct 2011 06:08:56 -0700 |
| parents | 4bac06a82bc3 |
| children | 6729bbc1fcd6 |
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--- a/src/cpu/sparc/vm/sparc.ad Tue Oct 25 12:51:13 2011 -0700 +++ b/src/cpu/sparc/vm/sparc.ad Wed Oct 26 06:08:56 2011 -0700 @@ -1860,6 +1860,14 @@ // Threshold size for cleararray. const int Matcher::init_array_short_size = 8 * BytesPerLong; +// No additional cost for CMOVL. +const int Matcher::long_cmove_cost() { return 0; } + +// CMOVF/CMOVD are expensive on T4 and on SPARC64. +const int Matcher::float_cmove_cost() { + return (VM_Version::is_T4() || VM_Version::is_sparc64()) ? ConditionalMoveLimit : 0; +} + // Should the Matcher clone shifts on addressing modes, expecting them to // be subsumed into complex addressing expressions or compute them into // registers? True for Intel but false for most RISCs