Mercurial > hg > graal-jvmci-8
diff src/cpu/x86/vm/vm_version_x86.hpp @ 14726:92aa6797d639
Backed out merge changeset: b51e29501f30
Backed out merge revision to its first parent (8f483e200405)
| author | Doug Simon <doug.simon@oracle.com> |
|---|---|
| date | Mon, 24 Mar 2014 21:30:43 +0100 |
| parents | b51e29501f30 |
| children |
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--- a/src/cpu/x86/vm/vm_version_x86.hpp Fri Mar 21 16:36:59 2014 -0700 +++ b/src/cpu/x86/vm/vm_version_x86.hpp Mon Mar 24 21:30:43 2014 +0100 @@ -142,8 +142,7 @@ struct { uint32_t LahfSahf : 1, CmpLegacy : 1, - : 3, - lzcnt_intel : 1, + : 4, lzcnt : 1, sse4a : 1, misalignsse : 1, @@ -253,9 +252,7 @@ CPU_AVX2 = (1 << 18), CPU_AES = (1 << 19), CPU_ERMS = (1 << 20), // enhanced 'rep movsb/stosb' instructions - CPU_CLMUL = (1 << 21), // carryless multiply for CRC - CPU_BMI1 = (1 << 22), - CPU_BMI2 = (1 << 23) + CPU_CLMUL = (1 << 21) // carryless multiply for CRC } cpuFeatureFlags; enum { @@ -427,8 +424,6 @@ if (_cpuid_info.sef_cpuid7_ebx.bits.avx2 != 0) result |= CPU_AVX2; } - if(_cpuid_info.sef_cpuid7_ebx.bits.bmi1 != 0) - result |= CPU_BMI1; if (_cpuid_info.std_cpuid1_edx.bits.tsc != 0) result |= CPU_TSC; if (_cpuid_info.ext_cpuid7_edx.bits.tsc_invariance != 0) @@ -450,13 +445,6 @@ if (_cpuid_info.ext_cpuid1_ecx.bits.sse4a != 0) result |= CPU_SSE4A; } - // Intel features. - if(is_intel()) { - if(_cpuid_info.sef_cpuid7_ebx.bits.bmi2 != 0) - result |= CPU_BMI2; - if(_cpuid_info.ext_cpuid1_ecx.bits.lzcnt_intel != 0) - result |= CPU_LZCNT; - } return result; } @@ -573,8 +561,7 @@ static bool supports_aes() { return (_cpuFeatures & CPU_AES) != 0; } static bool supports_erms() { return (_cpuFeatures & CPU_ERMS) != 0; } static bool supports_clmul() { return (_cpuFeatures & CPU_CLMUL) != 0; } - static bool supports_bmi1() { return (_cpuFeatures & CPU_BMI1) != 0; } - static bool supports_bmi2() { return (_cpuFeatures & CPU_BMI2) != 0; } + // Intel features static bool is_intel_family_core() { return is_intel() && extended_cpu_family() == CPU_FAMILY_INTEL_CORE; }