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changeset 22639:5d6bb2cb3b9d

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Add new flags to jdk.internal.jvmci.amd64.AMD64.CPUFeature
author twisti
date Wed, 30 Sep 2015 11:29:19 +0200
parents c7ce66399b04
children 3abba3d4aef1
files jvmci/jdk.internal.jvmci.amd64/src/jdk/internal/jvmci/amd64/AMD64.java jvmci/jdk.internal.jvmci.hotspot.amd64/src/jdk/internal/jvmci/hotspot/amd64/AMD64HotSpotJVMCIBackendFactory.java src/cpu/x86/vm/vmStructs_x86.hpp
diffstat 3 files changed, 40 insertions(+), 20 deletions(-) [+]
line wrap: on
line diff
--- a/jvmci/jdk.internal.jvmci.amd64/src/jdk/internal/jvmci/amd64/AMD64.java	Wed Sep 30 11:41:40 2015 +0200
+++ b/jvmci/jdk.internal.jvmci.amd64/src/jdk/internal/jvmci/amd64/AMD64.java	Wed Sep 30 11:29:19 2015 +0200
@@ -119,24 +119,42 @@
     // @formatter:on
 
     /**
-     * Basic set of CPU features mirroring what is returned from the cpuid instruction.
+     * Basic set of CPU features mirroring what is returned from the cpuid instruction. See:
+     * {@code VM_Version::cpuFeatureFlags}.
      */
     public static enum CPUFeature {
+        CX8,
+        CMOV,
+        FXSR,
+        HT,
+        MMX,
+        AMD_3DNOW_PREFETCH,
         SSE,
         SSE2,
         SSE3,
-        SSE4a,
+        SSSE3,
+        SSE4A,
         SSE4_1,
         SSE4_2,
-        SSSE3,
         POPCNT,
         LZCNT,
+        TSC,
+        TSCINV,
         AVX,
         AVX2,
+        AES,
         ERMS,
-        AMD_3DNOW_PREFETCH,
-        AES,
-        BMI1
+        CLMUL,
+        BMI1,
+        BMI2,
+        RTM,
+        ADX,
+        AVX512F,
+        AVX512DQ,
+        AVX512PF,
+        AVX512ER,
+        AVX512CD,
+        AVX512BW
     }
 
     private final EnumSet<CPUFeature> features;
--- a/jvmci/jdk.internal.jvmci.hotspot.amd64/src/jdk/internal/jvmci/hotspot/amd64/AMD64HotSpotJVMCIBackendFactory.java	Wed Sep 30 11:41:40 2015 +0200
+++ b/jvmci/jdk.internal.jvmci.hotspot.amd64/src/jdk/internal/jvmci/hotspot/amd64/AMD64HotSpotJVMCIBackendFactory.java	Wed Sep 30 11:29:19 2015 +0200
@@ -49,6 +49,9 @@
     protected EnumSet<AMD64.CPUFeature> computeFeatures(HotSpotVMConfig config) {
         // Configure the feature set using the HotSpot flag settings.
         EnumSet<AMD64.CPUFeature> features = EnumSet.noneOf(AMD64.CPUFeature.class);
+        if ((config.x86CPUFeatures & config.cpu3DNOWPREFETCH) != 0) {
+            features.add(AMD64.CPUFeature.AMD_3DNOW_PREFETCH);
+        }
         assert config.useSSE >= 2 : "minimum config for x64";
         features.add(AMD64.CPUFeature.SSE);
         features.add(AMD64.CPUFeature.SSE2);
@@ -59,7 +62,7 @@
             features.add(AMD64.CPUFeature.SSSE3);
         }
         if ((config.x86CPUFeatures & config.cpuSSE4A) != 0) {
-            features.add(AMD64.CPUFeature.SSE4a);
+            features.add(AMD64.CPUFeature.SSE4A);
         }
         if ((config.x86CPUFeatures & config.cpuSSE41) != 0) {
             features.add(AMD64.CPUFeature.SSE4_1);
@@ -67,26 +70,23 @@
         if ((config.x86CPUFeatures & config.cpuSSE42) != 0) {
             features.add(AMD64.CPUFeature.SSE4_2);
         }
+        if ((config.x86CPUFeatures & config.cpuPOPCNT) != 0) {
+            features.add(AMD64.CPUFeature.POPCNT);
+        }
+        if ((config.x86CPUFeatures & config.cpuLZCNT) != 0) {
+            features.add(AMD64.CPUFeature.LZCNT);
+        }
         if ((config.x86CPUFeatures & config.cpuAVX) != 0) {
             features.add(AMD64.CPUFeature.AVX);
         }
         if ((config.x86CPUFeatures & config.cpuAVX2) != 0) {
             features.add(AMD64.CPUFeature.AVX2);
         }
-        if ((config.x86CPUFeatures & config.cpuERMS) != 0) {
-            features.add(AMD64.CPUFeature.ERMS);
-        }
-        if ((config.x86CPUFeatures & config.cpuLZCNT) != 0) {
-            features.add(AMD64.CPUFeature.LZCNT);
-        }
-        if ((config.x86CPUFeatures & config.cpuPOPCNT) != 0) {
-            features.add(AMD64.CPUFeature.POPCNT);
-        }
         if ((config.x86CPUFeatures & config.cpuAES) != 0) {
             features.add(AMD64.CPUFeature.AES);
         }
-        if ((config.x86CPUFeatures & config.cpu3DNOWPREFETCH) != 0) {
-            features.add(AMD64.CPUFeature.AMD_3DNOW_PREFETCH);
+        if ((config.x86CPUFeatures & config.cpuERMS) != 0) {
+            features.add(AMD64.CPUFeature.ERMS);
         }
         if ((config.x86CPUFeatures & config.cpuBMI1) != 0) {
             features.add(AMD64.CPUFeature.BMI1);
--- a/src/cpu/x86/vm/vmStructs_x86.hpp	Wed Sep 30 11:41:40 2015 +0200
+++ b/src/cpu/x86/vm/vmStructs_x86.hpp	Wed Sep 30 11:29:19 2015 +0200
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2001, 2013, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2001, 2015, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
@@ -72,7 +72,9 @@
   declare_constant(VM_Version::CPU_ERMS)                            \
   declare_constant(VM_Version::CPU_CLMUL)                           \
   declare_constant(VM_Version::CPU_BMI1)                            \
-  declare_constant(VM_Version::CPU_BMI2)
+  declare_constant(VM_Version::CPU_BMI2)                            \
+  declare_constant(VM_Version::CPU_RTM)                             \
+  declare_constant(VM_Version::CPU_ADX)
 
 #define VM_LONG_CONSTANTS_CPU(declare_constant, declare_preprocessor_constant, declare_c1_constant, declare_c2_constant, declare_c2_preprocessor_constant)