Mercurial > hg > truffle
annotate src/cpu/x86/vm/vm_version_x86.cpp @ 4759:127b3692c168
7116452: Add support for AVX instructions
Summary: Added support for AVX extension to the x86 instruction set.
Reviewed-by: never
author | kvn |
---|---|
date | Wed, 14 Dec 2011 14:54:38 -0800 |
parents | f08d439fab8c |
children | 22cee0ee8927 |
rev | line source |
---|---|
585 | 1 /* |
3860
3be7439273c5
7044486: open jdk repos have files with incorrect copyright headers, which can end up in src bundles
katleman
parents:
3787
diff
changeset
|
2 * Copyright (c) 1997, 2011, Oracle and/or its affiliates. All rights reserved. |
585 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
4 * | |
5 * This code is free software; you can redistribute it and/or modify it | |
6 * under the terms of the GNU General Public License version 2 only, as | |
7 * published by the Free Software Foundation. | |
8 * | |
9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 * version 2 for more details (a copy is included in the LICENSE file that | |
13 * accompanied this code). | |
14 * | |
15 * You should have received a copy of the GNU General Public License version | |
16 * 2 along with this work; if not, write to the Free Software Foundation, | |
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
18 * | |
1552
c18cbe5936b8
6941466: Oracle rebranding changes for Hotspot repositories
trims
parents:
1060
diff
changeset
|
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
c18cbe5936b8
6941466: Oracle rebranding changes for Hotspot repositories
trims
parents:
1060
diff
changeset
|
20 * or visit www.oracle.com if you need additional information or have any |
c18cbe5936b8
6941466: Oracle rebranding changes for Hotspot repositories
trims
parents:
1060
diff
changeset
|
21 * questions. |
585 | 22 * |
23 */ | |
24 | |
1972 | 25 #include "precompiled.hpp" |
26 #include "assembler_x86.inline.hpp" | |
27 #include "memory/resourceArea.hpp" | |
28 #include "runtime/java.hpp" | |
29 #include "runtime/stubCodeGenerator.hpp" | |
30 #include "vm_version_x86.hpp" | |
31 #ifdef TARGET_OS_FAMILY_linux | |
32 # include "os_linux.inline.hpp" | |
33 #endif | |
34 #ifdef TARGET_OS_FAMILY_solaris | |
35 # include "os_solaris.inline.hpp" | |
36 #endif | |
37 #ifdef TARGET_OS_FAMILY_windows | |
38 # include "os_windows.inline.hpp" | |
39 #endif | |
3960 | 40 #ifdef TARGET_OS_FAMILY_bsd |
41 # include "os_bsd.inline.hpp" | |
42 #endif | |
585 | 43 |
44 | |
45 int VM_Version::_cpu; | |
46 int VM_Version::_model; | |
47 int VM_Version::_stepping; | |
48 int VM_Version::_cpuFeatures; | |
49 const char* VM_Version::_features_str = ""; | |
50 VM_Version::CpuidInfo VM_Version::_cpuid_info = { 0, }; | |
51 | |
52 static BufferBlob* stub_blob; | |
4759 | 53 static const int stub_size = 500; |
585 | 54 |
55 extern "C" { | |
56 typedef void (*getPsrInfo_stub_t)(void*); | |
57 } | |
58 static getPsrInfo_stub_t getPsrInfo_stub = NULL; | |
59 | |
60 | |
61 class VM_Version_StubGenerator: public StubCodeGenerator { | |
62 public: | |
63 | |
64 VM_Version_StubGenerator(CodeBuffer *c) : StubCodeGenerator(c) {} | |
65 | |
66 address generate_getPsrInfo() { | |
67 // Flags to test CPU type. | |
68 const uint32_t EFL_AC = 0x40000; | |
69 const uint32_t EFL_ID = 0x200000; | |
70 // Values for when we don't have a CPUID instruction. | |
71 const int CPU_FAMILY_SHIFT = 8; | |
72 const uint32_t CPU_FAMILY_386 = (3 << CPU_FAMILY_SHIFT); | |
73 const uint32_t CPU_FAMILY_486 = (4 << CPU_FAMILY_SHIFT); | |
74 | |
1622 | 75 Label detect_486, cpu486, detect_586, std_cpuid1, std_cpuid4; |
4759 | 76 Label sef_cpuid, ext_cpuid, ext_cpuid1, ext_cpuid5, done; |
585 | 77 |
78 StubCodeMark mark(this, "VM_Version", "getPsrInfo_stub"); | |
79 # define __ _masm-> | |
80 | |
81 address start = __ pc(); | |
82 | |
83 // | |
84 // void getPsrInfo(VM_Version::CpuidInfo* cpuid_info); | |
85 // | |
86 // LP64: rcx and rdx are first and second argument registers on windows | |
87 | |
88 __ push(rbp); | |
89 #ifdef _LP64 | |
90 __ mov(rbp, c_rarg0); // cpuid_info address | |
91 #else | |
92 __ movptr(rbp, Address(rsp, 8)); // cpuid_info address | |
93 #endif | |
94 __ push(rbx); | |
95 __ push(rsi); | |
96 __ pushf(); // preserve rbx, and flags | |
97 __ pop(rax); | |
98 __ push(rax); | |
99 __ mov(rcx, rax); | |
100 // | |
101 // if we are unable to change the AC flag, we have a 386 | |
102 // | |
103 __ xorl(rax, EFL_AC); | |
104 __ push(rax); | |
105 __ popf(); | |
106 __ pushf(); | |
107 __ pop(rax); | |
108 __ cmpptr(rax, rcx); | |
109 __ jccb(Assembler::notEqual, detect_486); | |
110 | |
111 __ movl(rax, CPU_FAMILY_386); | |
112 __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax); | |
113 __ jmp(done); | |
114 | |
115 // | |
116 // If we are unable to change the ID flag, we have a 486 which does | |
117 // not support the "cpuid" instruction. | |
118 // | |
119 __ bind(detect_486); | |
120 __ mov(rax, rcx); | |
121 __ xorl(rax, EFL_ID); | |
122 __ push(rax); | |
123 __ popf(); | |
124 __ pushf(); | |
125 __ pop(rax); | |
126 __ cmpptr(rcx, rax); | |
127 __ jccb(Assembler::notEqual, detect_586); | |
128 | |
129 __ bind(cpu486); | |
130 __ movl(rax, CPU_FAMILY_486); | |
131 __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax); | |
132 __ jmp(done); | |
133 | |
134 // | |
135 // At this point, we have a chip which supports the "cpuid" instruction | |
136 // | |
137 __ bind(detect_586); | |
138 __ xorl(rax, rax); | |
139 __ cpuid(); | |
140 __ orl(rax, rax); | |
141 __ jcc(Assembler::equal, cpu486); // if cpuid doesn't support an input | |
142 // value of at least 1, we give up and | |
143 // assume a 486 | |
144 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); | |
145 __ movl(Address(rsi, 0), rax); | |
146 __ movl(Address(rsi, 4), rbx); | |
147 __ movl(Address(rsi, 8), rcx); | |
148 __ movl(Address(rsi,12), rdx); | |
149 | |
1622 | 150 __ cmpl(rax, 0xa); // Is cpuid(0xB) supported? |
151 __ jccb(Assembler::belowEqual, std_cpuid4); | |
152 | |
153 // | |
154 // cpuid(0xB) Processor Topology | |
155 // | |
156 __ movl(rax, 0xb); | |
157 __ xorl(rcx, rcx); // Threads level | |
158 __ cpuid(); | |
159 | |
160 __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB0_offset()))); | |
161 __ movl(Address(rsi, 0), rax); | |
162 __ movl(Address(rsi, 4), rbx); | |
163 __ movl(Address(rsi, 8), rcx); | |
164 __ movl(Address(rsi,12), rdx); | |
165 | |
166 __ movl(rax, 0xb); | |
167 __ movl(rcx, 1); // Cores level | |
168 __ cpuid(); | |
169 __ push(rax); | |
170 __ andl(rax, 0x1f); // Determine if valid topology level | |
171 __ orl(rax, rbx); // eax[4:0] | ebx[0:15] == 0 indicates invalid level | |
172 __ andl(rax, 0xffff); | |
173 __ pop(rax); | |
174 __ jccb(Assembler::equal, std_cpuid4); | |
175 | |
176 __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB1_offset()))); | |
177 __ movl(Address(rsi, 0), rax); | |
178 __ movl(Address(rsi, 4), rbx); | |
179 __ movl(Address(rsi, 8), rcx); | |
180 __ movl(Address(rsi,12), rdx); | |
181 | |
182 __ movl(rax, 0xb); | |
183 __ movl(rcx, 2); // Packages level | |
184 __ cpuid(); | |
185 __ push(rax); | |
186 __ andl(rax, 0x1f); // Determine if valid topology level | |
187 __ orl(rax, rbx); // eax[4:0] | ebx[0:15] == 0 indicates invalid level | |
188 __ andl(rax, 0xffff); | |
189 __ pop(rax); | |
190 __ jccb(Assembler::equal, std_cpuid4); | |
191 | |
192 __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB2_offset()))); | |
193 __ movl(Address(rsi, 0), rax); | |
194 __ movl(Address(rsi, 4), rbx); | |
195 __ movl(Address(rsi, 8), rcx); | |
196 __ movl(Address(rsi,12), rdx); | |
585 | 197 |
198 // | |
199 // cpuid(0x4) Deterministic cache params | |
200 // | |
1622 | 201 __ bind(std_cpuid4); |
585 | 202 __ movl(rax, 4); |
1622 | 203 __ cmpl(rax, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); // Is cpuid(0x4) supported? |
204 __ jccb(Assembler::greater, std_cpuid1); | |
205 | |
585 | 206 __ xorl(rcx, rcx); // L1 cache |
207 __ cpuid(); | |
208 __ push(rax); | |
209 __ andl(rax, 0x1f); // Determine if valid cache parameters used | |
210 __ orl(rax, rax); // eax[4:0] == 0 indicates invalid cache | |
211 __ pop(rax); | |
212 __ jccb(Assembler::equal, std_cpuid1); | |
213 | |
214 __ lea(rsi, Address(rbp, in_bytes(VM_Version::dcp_cpuid4_offset()))); | |
215 __ movl(Address(rsi, 0), rax); | |
216 __ movl(Address(rsi, 4), rbx); | |
217 __ movl(Address(rsi, 8), rcx); | |
218 __ movl(Address(rsi,12), rdx); | |
219 | |
220 // | |
221 // Standard cpuid(0x1) | |
222 // | |
223 __ bind(std_cpuid1); | |
224 __ movl(rax, 1); | |
225 __ cpuid(); | |
226 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset()))); | |
227 __ movl(Address(rsi, 0), rax); | |
228 __ movl(Address(rsi, 4), rbx); | |
229 __ movl(Address(rsi, 8), rcx); | |
230 __ movl(Address(rsi,12), rdx); | |
231 | |
4759 | 232 // |
233 // Check if OS has enabled XGETBV instruction to access XCR0 | |
234 // (OSXSAVE feature flag) and CPU supports AVX | |
235 // | |
236 __ andl(rcx, 0x18000000); | |
237 __ cmpl(rcx, 0x18000000); | |
238 __ jccb(Assembler::notEqual, sef_cpuid); | |
239 | |
240 // | |
241 // XCR0, XFEATURE_ENABLED_MASK register | |
242 // | |
243 __ xorl(rcx, rcx); // zero for XCR0 register | |
244 __ xgetbv(); | |
245 __ lea(rsi, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset()))); | |
246 __ movl(Address(rsi, 0), rax); | |
247 __ movl(Address(rsi, 4), rdx); | |
248 | |
249 // | |
250 // cpuid(0x7) Structured Extended Features | |
251 // | |
252 __ bind(sef_cpuid); | |
253 __ movl(rax, 7); | |
254 __ cmpl(rax, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); // Is cpuid(0x7) supported? | |
255 __ jccb(Assembler::greater, ext_cpuid); | |
256 | |
257 __ xorl(rcx, rcx); | |
258 __ cpuid(); | |
259 __ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset()))); | |
260 __ movl(Address(rsi, 0), rax); | |
261 __ movl(Address(rsi, 4), rbx); | |
262 | |
263 // | |
264 // Extended cpuid(0x80000000) | |
265 // | |
266 __ bind(ext_cpuid); | |
585 | 267 __ movl(rax, 0x80000000); |
268 __ cpuid(); | |
269 __ cmpl(rax, 0x80000000); // Is cpuid(0x80000001) supported? | |
270 __ jcc(Assembler::belowEqual, done); | |
271 __ cmpl(rax, 0x80000004); // Is cpuid(0x80000005) supported? | |
272 __ jccb(Assembler::belowEqual, ext_cpuid1); | |
273 __ cmpl(rax, 0x80000007); // Is cpuid(0x80000008) supported? | |
274 __ jccb(Assembler::belowEqual, ext_cpuid5); | |
275 // | |
276 // Extended cpuid(0x80000008) | |
277 // | |
278 __ movl(rax, 0x80000008); | |
279 __ cpuid(); | |
280 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid8_offset()))); | |
281 __ movl(Address(rsi, 0), rax); | |
282 __ movl(Address(rsi, 4), rbx); | |
283 __ movl(Address(rsi, 8), rcx); | |
284 __ movl(Address(rsi,12), rdx); | |
285 | |
286 // | |
287 // Extended cpuid(0x80000005) | |
288 // | |
289 __ bind(ext_cpuid5); | |
290 __ movl(rax, 0x80000005); | |
291 __ cpuid(); | |
292 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid5_offset()))); | |
293 __ movl(Address(rsi, 0), rax); | |
294 __ movl(Address(rsi, 4), rbx); | |
295 __ movl(Address(rsi, 8), rcx); | |
296 __ movl(Address(rsi,12), rdx); | |
297 | |
298 // | |
299 // Extended cpuid(0x80000001) | |
300 // | |
301 __ bind(ext_cpuid1); | |
302 __ movl(rax, 0x80000001); | |
303 __ cpuid(); | |
304 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid1_offset()))); | |
305 __ movl(Address(rsi, 0), rax); | |
306 __ movl(Address(rsi, 4), rbx); | |
307 __ movl(Address(rsi, 8), rcx); | |
308 __ movl(Address(rsi,12), rdx); | |
309 | |
310 // | |
311 // return | |
312 // | |
313 __ bind(done); | |
314 __ popf(); | |
315 __ pop(rsi); | |
316 __ pop(rbx); | |
317 __ pop(rbp); | |
318 __ ret(0); | |
319 | |
320 # undef __ | |
321 | |
322 return start; | |
323 }; | |
324 }; | |
325 | |
326 | |
327 void VM_Version::get_processor_features() { | |
328 | |
329 _cpu = 4; // 486 by default | |
330 _model = 0; | |
331 _stepping = 0; | |
332 _cpuFeatures = 0; | |
333 _logical_processors_per_package = 1; | |
334 | |
335 if (!Use486InstrsOnly) { | |
336 // Get raw processor info | |
337 getPsrInfo_stub(&_cpuid_info); | |
338 assert_is_initialized(); | |
339 _cpu = extended_cpu_family(); | |
340 _model = extended_cpu_model(); | |
341 _stepping = cpu_stepping(); | |
342 | |
343 if (cpu_family() > 4) { // it supports CPUID | |
344 _cpuFeatures = feature_flags(); | |
345 // Logical processors are only available on P4s and above, | |
346 // and only if hyperthreading is available. | |
347 _logical_processors_per_package = logical_processor_count(); | |
348 } | |
349 } | |
350 | |
351 _supports_cx8 = supports_cmpxchg8(); | |
352 | |
353 #ifdef _LP64 | |
354 // OS should support SSE for x64 and hardware should support at least SSE2. | |
355 if (!VM_Version::supports_sse2()) { | |
356 vm_exit_during_initialization("Unknown x64 processor: SSE2 not supported"); | |
357 } | |
1060 | 358 // in 64 bit the use of SSE2 is the minimum |
359 if (UseSSE < 2) UseSSE = 2; | |
585 | 360 #endif |
361 | |
3787
6ae7a1561b53
6990015: Incorrect Icache line size is used for 64 bit x86
kvn
parents:
3276
diff
changeset
|
362 #ifdef AMD64 |
6ae7a1561b53
6990015: Incorrect Icache line size is used for 64 bit x86
kvn
parents:
3276
diff
changeset
|
363 // flush_icache_stub have to be generated first. |
6ae7a1561b53
6990015: Incorrect Icache line size is used for 64 bit x86
kvn
parents:
3276
diff
changeset
|
364 // That is why Icache line size is hard coded in ICache class, |
6ae7a1561b53
6990015: Incorrect Icache line size is used for 64 bit x86
kvn
parents:
3276
diff
changeset
|
365 // see icache_x86.hpp. It is also the reason why we can't use |
6ae7a1561b53
6990015: Incorrect Icache line size is used for 64 bit x86
kvn
parents:
3276
diff
changeset
|
366 // clflush instruction in 32-bit VM since it could be running |
6ae7a1561b53
6990015: Incorrect Icache line size is used for 64 bit x86
kvn
parents:
3276
diff
changeset
|
367 // on CPU which does not support it. |
6ae7a1561b53
6990015: Incorrect Icache line size is used for 64 bit x86
kvn
parents:
3276
diff
changeset
|
368 // |
6ae7a1561b53
6990015: Incorrect Icache line size is used for 64 bit x86
kvn
parents:
3276
diff
changeset
|
369 // The only thing we can do is to verify that flushed |
6ae7a1561b53
6990015: Incorrect Icache line size is used for 64 bit x86
kvn
parents:
3276
diff
changeset
|
370 // ICache::line_size has correct value. |
6ae7a1561b53
6990015: Incorrect Icache line size is used for 64 bit x86
kvn
parents:
3276
diff
changeset
|
371 guarantee(_cpuid_info.std_cpuid1_edx.bits.clflush != 0, "clflush is not supported"); |
6ae7a1561b53
6990015: Incorrect Icache line size is used for 64 bit x86
kvn
parents:
3276
diff
changeset
|
372 // clflush_size is size in quadwords (8 bytes). |
6ae7a1561b53
6990015: Incorrect Icache line size is used for 64 bit x86
kvn
parents:
3276
diff
changeset
|
373 guarantee(_cpuid_info.std_cpuid1_ebx.bits.clflush_size == 8, "such clflush size is not supported"); |
6ae7a1561b53
6990015: Incorrect Icache line size is used for 64 bit x86
kvn
parents:
3276
diff
changeset
|
374 #endif |
6ae7a1561b53
6990015: Incorrect Icache line size is used for 64 bit x86
kvn
parents:
3276
diff
changeset
|
375 |
585 | 376 // If the OS doesn't support SSE, we can't use this feature even if the HW does |
377 if (!os::supports_sse()) | |
378 _cpuFeatures &= ~(CPU_SSE|CPU_SSE2|CPU_SSE3|CPU_SSSE3|CPU_SSE4A|CPU_SSE4_1|CPU_SSE4_2); | |
379 | |
380 if (UseSSE < 4) { | |
381 _cpuFeatures &= ~CPU_SSE4_1; | |
382 _cpuFeatures &= ~CPU_SSE4_2; | |
383 } | |
384 | |
385 if (UseSSE < 3) { | |
386 _cpuFeatures &= ~CPU_SSE3; | |
387 _cpuFeatures &= ~CPU_SSSE3; | |
388 _cpuFeatures &= ~CPU_SSE4A; | |
389 } | |
390 | |
391 if (UseSSE < 2) | |
392 _cpuFeatures &= ~CPU_SSE2; | |
393 | |
394 if (UseSSE < 1) | |
395 _cpuFeatures &= ~CPU_SSE; | |
396 | |
4759 | 397 if (UseAVX < 2) |
398 _cpuFeatures &= ~CPU_AVX2; | |
399 | |
400 if (UseAVX < 1) | |
401 _cpuFeatures &= ~CPU_AVX; | |
402 | |
585 | 403 if (logical_processors_per_package() == 1) { |
404 // HT processor could be installed on a system which doesn't support HT. | |
405 _cpuFeatures &= ~CPU_HT; | |
406 } | |
407 | |
408 char buf[256]; | |
4759 | 409 jio_snprintf(buf, sizeof(buf), "(%u cores per cpu, %u threads per core) family %d model %d stepping %d%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s", |
585 | 410 cores_per_cpu(), threads_per_core(), |
411 cpu_family(), _model, _stepping, | |
412 (supports_cmov() ? ", cmov" : ""), | |
413 (supports_cmpxchg8() ? ", cx8" : ""), | |
414 (supports_fxsr() ? ", fxsr" : ""), | |
415 (supports_mmx() ? ", mmx" : ""), | |
416 (supports_sse() ? ", sse" : ""), | |
417 (supports_sse2() ? ", sse2" : ""), | |
418 (supports_sse3() ? ", sse3" : ""), | |
419 (supports_ssse3()? ", ssse3": ""), | |
420 (supports_sse4_1() ? ", sse4.1" : ""), | |
421 (supports_sse4_2() ? ", sse4.2" : ""), | |
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
585
diff
changeset
|
422 (supports_popcnt() ? ", popcnt" : ""), |
4759 | 423 (supports_avx() ? ", avx" : ""), |
424 (supports_avx2() ? ", avx2" : ""), | |
585 | 425 (supports_mmx_ext() ? ", mmxext" : ""), |
2479 | 426 (supports_3dnow_prefetch() ? ", 3dnowpref" : ""), |
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
427 (supports_lzcnt() ? ", lzcnt": ""), |
585 | 428 (supports_sse4a() ? ", sse4a": ""), |
429 (supports_ht() ? ", ht": "")); | |
430 _features_str = strdup(buf); | |
431 | |
432 // UseSSE is set to the smaller of what hardware supports and what | |
433 // the command line requires. I.e., you cannot set UseSSE to 2 on | |
434 // older Pentiums which do not support it. | |
4759 | 435 if (UseSSE > 4) UseSSE=4; |
436 if (UseSSE < 0) UseSSE=0; | |
437 if (!supports_sse4_1()) // Drop to 3 if no SSE4 support | |
585 | 438 UseSSE = MIN2((intx)3,UseSSE); |
4759 | 439 if (!supports_sse3()) // Drop to 2 if no SSE3 support |
585 | 440 UseSSE = MIN2((intx)2,UseSSE); |
4759 | 441 if (!supports_sse2()) // Drop to 1 if no SSE2 support |
585 | 442 UseSSE = MIN2((intx)1,UseSSE); |
4759 | 443 if (!supports_sse ()) // Drop to 0 if no SSE support |
585 | 444 UseSSE = 0; |
445 | |
4759 | 446 if (UseAVX > 2) UseAVX=2; |
447 if (UseAVX < 0) UseAVX=0; | |
448 if (!supports_avx2()) // Drop to 1 if no AVX2 support | |
449 UseAVX = MIN2((intx)1,UseAVX); | |
450 if (!supports_avx ()) // Drop to 0 if no AVX support | |
451 UseAVX = 0; | |
452 | |
585 | 453 // On new cpus instructions which update whole XMM register should be used |
454 // to prevent partial register stall due to dependencies on high half. | |
455 // | |
456 // UseXmmLoadAndClearUpper == true --> movsd(xmm, mem) | |
457 // UseXmmLoadAndClearUpper == false --> movlpd(xmm, mem) | |
458 // UseXmmRegToRegMoveAll == true --> movaps(xmm, xmm), movapd(xmm, xmm). | |
459 // UseXmmRegToRegMoveAll == false --> movss(xmm, xmm), movsd(xmm, xmm). | |
460 | |
461 if( is_amd() ) { // AMD cpus specific settings | |
462 if( supports_sse2() && FLAG_IS_DEFAULT(UseAddressNop) ) { | |
463 // Use it on new AMD cpus starting from Opteron. | |
464 UseAddressNop = true; | |
465 } | |
466 if( supports_sse2() && FLAG_IS_DEFAULT(UseNewLongLShift) ) { | |
467 // Use it on new AMD cpus starting from Opteron. | |
468 UseNewLongLShift = true; | |
469 } | |
470 if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) { | |
471 if( supports_sse4a() ) { | |
472 UseXmmLoadAndClearUpper = true; // use movsd only on '10h' Opteron | |
473 } else { | |
474 UseXmmLoadAndClearUpper = false; | |
475 } | |
476 } | |
477 if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) { | |
478 if( supports_sse4a() ) { | |
479 UseXmmRegToRegMoveAll = true; // use movaps, movapd only on '10h' | |
480 } else { | |
481 UseXmmRegToRegMoveAll = false; | |
482 } | |
483 } | |
484 if( FLAG_IS_DEFAULT(UseXmmI2F) ) { | |
485 if( supports_sse4a() ) { | |
486 UseXmmI2F = true; | |
487 } else { | |
488 UseXmmI2F = false; | |
489 } | |
490 } | |
491 if( FLAG_IS_DEFAULT(UseXmmI2D) ) { | |
492 if( supports_sse4a() ) { | |
493 UseXmmI2D = true; | |
494 } else { | |
495 UseXmmI2D = false; | |
496 } | |
497 } | |
2406 | 498 if( FLAG_IS_DEFAULT(UseSSE42Intrinsics) ) { |
499 if( supports_sse4_2() && UseSSE >= 4 ) { | |
500 UseSSE42Intrinsics = true; | |
501 } | |
502 } | |
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
503 |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
504 // Use count leading zeros count instruction if available. |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
505 if (supports_lzcnt()) { |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
506 if (FLAG_IS_DEFAULT(UseCountLeadingZerosInstruction)) { |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
507 UseCountLeadingZerosInstruction = true; |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
508 } |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
509 } |
2358 | 510 |
3276
2a34a4fbc52c
7037812: few more defaults changes for new AMD processors
kvn
parents:
2479
diff
changeset
|
511 // some defaults for AMD family 15h |
2a34a4fbc52c
7037812: few more defaults changes for new AMD processors
kvn
parents:
2479
diff
changeset
|
512 if ( cpu_family() == 0x15 ) { |
2a34a4fbc52c
7037812: few more defaults changes for new AMD processors
kvn
parents:
2479
diff
changeset
|
513 // On family 15h processors default is no sw prefetch |
2358 | 514 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) { |
515 AllocatePrefetchStyle = 0; | |
516 } | |
3276
2a34a4fbc52c
7037812: few more defaults changes for new AMD processors
kvn
parents:
2479
diff
changeset
|
517 // Also, if some other prefetch style is specified, default instruction type is PREFETCHW |
2a34a4fbc52c
7037812: few more defaults changes for new AMD processors
kvn
parents:
2479
diff
changeset
|
518 if (FLAG_IS_DEFAULT(AllocatePrefetchInstr)) { |
2a34a4fbc52c
7037812: few more defaults changes for new AMD processors
kvn
parents:
2479
diff
changeset
|
519 AllocatePrefetchInstr = 3; |
2a34a4fbc52c
7037812: few more defaults changes for new AMD processors
kvn
parents:
2479
diff
changeset
|
520 } |
2a34a4fbc52c
7037812: few more defaults changes for new AMD processors
kvn
parents:
2479
diff
changeset
|
521 // On family 15h processors use XMM and UnalignedLoadStores for Array Copy |
2a34a4fbc52c
7037812: few more defaults changes for new AMD processors
kvn
parents:
2479
diff
changeset
|
522 if( FLAG_IS_DEFAULT(UseXMMForArrayCopy) ) { |
2a34a4fbc52c
7037812: few more defaults changes for new AMD processors
kvn
parents:
2479
diff
changeset
|
523 UseXMMForArrayCopy = true; |
2a34a4fbc52c
7037812: few more defaults changes for new AMD processors
kvn
parents:
2479
diff
changeset
|
524 } |
2a34a4fbc52c
7037812: few more defaults changes for new AMD processors
kvn
parents:
2479
diff
changeset
|
525 if( FLAG_IS_DEFAULT(UseUnalignedLoadStores) && UseXMMForArrayCopy ) { |
2a34a4fbc52c
7037812: few more defaults changes for new AMD processors
kvn
parents:
2479
diff
changeset
|
526 UseUnalignedLoadStores = true; |
2a34a4fbc52c
7037812: few more defaults changes for new AMD processors
kvn
parents:
2479
diff
changeset
|
527 } |
2358 | 528 } |
3276
2a34a4fbc52c
7037812: few more defaults changes for new AMD processors
kvn
parents:
2479
diff
changeset
|
529 |
585 | 530 } |
531 | |
532 if( is_intel() ) { // Intel cpus specific settings | |
533 if( FLAG_IS_DEFAULT(UseStoreImmI16) ) { | |
534 UseStoreImmI16 = false; // don't use it on Intel cpus | |
535 } | |
536 if( cpu_family() == 6 || cpu_family() == 15 ) { | |
537 if( FLAG_IS_DEFAULT(UseAddressNop) ) { | |
538 // Use it on all Intel cpus starting from PentiumPro | |
539 UseAddressNop = true; | |
540 } | |
541 } | |
542 if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) { | |
543 UseXmmLoadAndClearUpper = true; // use movsd on all Intel cpus | |
544 } | |
545 if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) { | |
546 if( supports_sse3() ) { | |
547 UseXmmRegToRegMoveAll = true; // use movaps, movapd on new Intel cpus | |
548 } else { | |
549 UseXmmRegToRegMoveAll = false; | |
550 } | |
551 } | |
552 if( cpu_family() == 6 && supports_sse3() ) { // New Intel cpus | |
553 #ifdef COMPILER2 | |
554 if( FLAG_IS_DEFAULT(MaxLoopPad) ) { | |
555 // For new Intel cpus do the next optimization: | |
556 // don't align the beginning of a loop if there are enough instructions | |
557 // left (NumberOfLoopInstrToAlign defined in c2_globals.hpp) | |
558 // in current fetch line (OptoLoopAlignment) or the padding | |
559 // is big (> MaxLoopPad). | |
560 // Set MaxLoopPad to 11 for new Intel cpus to reduce number of | |
561 // generated NOP instructions. 11 is the largest size of one | |
562 // address NOP instruction '0F 1F' (see Assembler::nop(i)). | |
563 MaxLoopPad = 11; | |
564 } | |
565 #endif // COMPILER2 | |
566 if( FLAG_IS_DEFAULT(UseXMMForArrayCopy) ) { | |
567 UseXMMForArrayCopy = true; // use SSE2 movq on new Intel cpus | |
568 } | |
569 if( supports_sse4_2() && supports_ht() ) { // Newest Intel cpus | |
570 if( FLAG_IS_DEFAULT(UseUnalignedLoadStores) && UseXMMForArrayCopy ) { | |
571 UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus | |
572 } | |
573 } | |
681 | 574 if( supports_sse4_2() && UseSSE >= 4 ) { |
575 if( FLAG_IS_DEFAULT(UseSSE42Intrinsics)) { | |
576 UseSSE42Intrinsics = true; | |
577 } | |
578 } | |
585 | 579 } |
580 } | |
581 | |
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
585
diff
changeset
|
582 // Use population count instruction if available. |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
585
diff
changeset
|
583 if (supports_popcnt()) { |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
585
diff
changeset
|
584 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) { |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
585
diff
changeset
|
585 UsePopCountInstruction = true; |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
585
diff
changeset
|
586 } |
4759 | 587 } else if (UsePopCountInstruction) { |
588 warning("POPCNT instruction is not available on this CPU"); | |
589 FLAG_SET_DEFAULT(UsePopCountInstruction, false); | |
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
585
diff
changeset
|
590 } |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
585
diff
changeset
|
591 |
1730
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1622
diff
changeset
|
592 #ifdef COMPILER2 |
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1622
diff
changeset
|
593 if (UseFPUForSpilling) { |
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1622
diff
changeset
|
594 if (UseSSE < 2) { |
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1622
diff
changeset
|
595 // Only supported with SSE2+ |
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1622
diff
changeset
|
596 FLAG_SET_DEFAULT(UseFPUForSpilling, false); |
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1622
diff
changeset
|
597 } |
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1622
diff
changeset
|
598 } |
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1622
diff
changeset
|
599 #endif |
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1622
diff
changeset
|
600 |
585 | 601 assert(0 <= ReadPrefetchInstr && ReadPrefetchInstr <= 3, "invalid value"); |
602 assert(0 <= AllocatePrefetchInstr && AllocatePrefetchInstr <= 3, "invalid value"); | |
603 | |
604 // set valid Prefetch instruction | |
605 if( ReadPrefetchInstr < 0 ) ReadPrefetchInstr = 0; | |
606 if( ReadPrefetchInstr > 3 ) ReadPrefetchInstr = 3; | |
2479 | 607 if( ReadPrefetchInstr == 3 && !supports_3dnow_prefetch() ) ReadPrefetchInstr = 0; |
608 if( !supports_sse() && supports_3dnow_prefetch() ) ReadPrefetchInstr = 3; | |
585 | 609 |
610 if( AllocatePrefetchInstr < 0 ) AllocatePrefetchInstr = 0; | |
611 if( AllocatePrefetchInstr > 3 ) AllocatePrefetchInstr = 3; | |
2479 | 612 if( AllocatePrefetchInstr == 3 && !supports_3dnow_prefetch() ) AllocatePrefetchInstr=0; |
613 if( !supports_sse() && supports_3dnow_prefetch() ) AllocatePrefetchInstr = 3; | |
585 | 614 |
615 // Allocation prefetch settings | |
3854 | 616 intx cache_line_size = prefetch_data_size(); |
585 | 617 if( cache_line_size > AllocatePrefetchStepSize ) |
618 AllocatePrefetchStepSize = cache_line_size; | |
3854 | 619 |
585 | 620 assert(AllocatePrefetchLines > 0, "invalid value"); |
3854 | 621 if( AllocatePrefetchLines < 1 ) // set valid value in product VM |
622 AllocatePrefetchLines = 3; | |
623 assert(AllocateInstancePrefetchLines > 0, "invalid value"); | |
624 if( AllocateInstancePrefetchLines < 1 ) // set valid value in product VM | |
625 AllocateInstancePrefetchLines = 1; | |
585 | 626 |
627 AllocatePrefetchDistance = allocate_prefetch_distance(); | |
628 AllocatePrefetchStyle = allocate_prefetch_style(); | |
629 | |
1622 | 630 if( is_intel() && cpu_family() == 6 && supports_sse3() ) { |
631 if( AllocatePrefetchStyle == 2 ) { // watermark prefetching on Core | |
585 | 632 #ifdef _LP64 |
1622 | 633 AllocatePrefetchDistance = 384; |
585 | 634 #else |
1622 | 635 AllocatePrefetchDistance = 320; |
585 | 636 #endif |
1622 | 637 } |
638 if( supports_sse4_2() && supports_ht() ) { // Nehalem based cpus | |
639 AllocatePrefetchDistance = 192; | |
640 AllocatePrefetchLines = 4; | |
1730
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1622
diff
changeset
|
641 #ifdef COMPILER2 |
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1622
diff
changeset
|
642 if (AggressiveOpts && FLAG_IS_DEFAULT(UseFPUForSpilling)) { |
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1622
diff
changeset
|
643 FLAG_SET_DEFAULT(UseFPUForSpilling, true); |
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1622
diff
changeset
|
644 } |
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1622
diff
changeset
|
645 #endif |
1622 | 646 } |
585 | 647 } |
648 assert(AllocatePrefetchDistance % AllocatePrefetchStepSize == 0, "invalid value"); | |
649 | |
650 #ifdef _LP64 | |
651 // Prefetch settings | |
652 PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes(); | |
653 PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes(); | |
654 PrefetchFieldsAhead = prefetch_fields_ahead(); | |
655 #endif | |
656 | |
657 #ifndef PRODUCT | |
658 if (PrintMiscellaneous && Verbose) { | |
659 tty->print_cr("Logical CPUs per core: %u", | |
660 logical_processors_per_package()); | |
4759 | 661 tty->print("UseSSE=%d",UseSSE); |
662 if (UseAVX > 0) { | |
663 tty->print(" UseAVX=%d",UseAVX); | |
664 } | |
665 tty->cr(); | |
3854 | 666 tty->print("Allocation"); |
2479 | 667 if (AllocatePrefetchStyle <= 0 || UseSSE == 0 && !supports_3dnow_prefetch()) { |
3854 | 668 tty->print_cr(": no prefetching"); |
585 | 669 } else { |
3854 | 670 tty->print(" prefetching: "); |
2479 | 671 if (UseSSE == 0 && supports_3dnow_prefetch()) { |
585 | 672 tty->print("PREFETCHW"); |
673 } else if (UseSSE >= 1) { | |
674 if (AllocatePrefetchInstr == 0) { | |
675 tty->print("PREFETCHNTA"); | |
676 } else if (AllocatePrefetchInstr == 1) { | |
677 tty->print("PREFETCHT0"); | |
678 } else if (AllocatePrefetchInstr == 2) { | |
679 tty->print("PREFETCHT2"); | |
680 } else if (AllocatePrefetchInstr == 3) { | |
681 tty->print("PREFETCHW"); | |
682 } | |
683 } | |
684 if (AllocatePrefetchLines > 1) { | |
3854 | 685 tty->print_cr(" at distance %d, %d lines of %d bytes", AllocatePrefetchDistance, AllocatePrefetchLines, AllocatePrefetchStepSize); |
585 | 686 } else { |
3854 | 687 tty->print_cr(" at distance %d, one line of %d bytes", AllocatePrefetchDistance, AllocatePrefetchStepSize); |
585 | 688 } |
689 } | |
690 | |
691 if (PrefetchCopyIntervalInBytes > 0) { | |
692 tty->print_cr("PrefetchCopyIntervalInBytes %d", PrefetchCopyIntervalInBytes); | |
693 } | |
694 if (PrefetchScanIntervalInBytes > 0) { | |
695 tty->print_cr("PrefetchScanIntervalInBytes %d", PrefetchScanIntervalInBytes); | |
696 } | |
697 if (PrefetchFieldsAhead > 0) { | |
698 tty->print_cr("PrefetchFieldsAhead %d", PrefetchFieldsAhead); | |
699 } | |
700 } | |
701 #endif // !PRODUCT | |
702 } | |
703 | |
704 void VM_Version::initialize() { | |
705 ResourceMark rm; | |
706 // Making this stub must be FIRST use of assembler | |
707 | |
708 stub_blob = BufferBlob::create("getPsrInfo_stub", stub_size); | |
709 if (stub_blob == NULL) { | |
710 vm_exit_during_initialization("Unable to allocate getPsrInfo_stub"); | |
711 } | |
1748 | 712 CodeBuffer c(stub_blob); |
585 | 713 VM_Version_StubGenerator g(&c); |
714 getPsrInfo_stub = CAST_TO_FN_PTR(getPsrInfo_stub_t, | |
715 g.generate_getPsrInfo()); | |
716 | |
717 get_processor_features(); | |
718 } |