Mercurial > hg > truffle
annotate src/cpu/x86/vm/vm_version_x86.hpp @ 4759:127b3692c168
7116452: Add support for AVX instructions
Summary: Added support for AVX extension to the x86 instruction set.
Reviewed-by: never
| author | kvn |
|---|---|
| date | Wed, 14 Dec 2011 14:54:38 -0800 |
| parents | 9f12ede5571a |
| children | 22cee0ee8927 |
| rev | line source |
|---|---|
| 585 | 1 /* |
|
3860
3be7439273c5
7044486: open jdk repos have files with incorrect copyright headers, which can end up in src bundles
katleman
parents:
3787
diff
changeset
|
2 * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved. |
| 585 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 4 * | |
| 5 * This code is free software; you can redistribute it and/or modify it | |
| 6 * under the terms of the GNU General Public License version 2 only, as | |
| 7 * published by the Free Software Foundation. | |
| 8 * | |
| 9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 * version 2 for more details (a copy is included in the LICENSE file that | |
| 13 * accompanied this code). | |
| 14 * | |
| 15 * You should have received a copy of the GNU General Public License version | |
| 16 * 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 * | |
|
1552
c18cbe5936b8
6941466: Oracle rebranding changes for Hotspot repositories
trims
parents:
775
diff
changeset
|
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
|
c18cbe5936b8
6941466: Oracle rebranding changes for Hotspot repositories
trims
parents:
775
diff
changeset
|
20 * or visit www.oracle.com if you need additional information or have any |
|
c18cbe5936b8
6941466: Oracle rebranding changes for Hotspot repositories
trims
parents:
775
diff
changeset
|
21 * questions. |
| 585 | 22 * |
| 23 */ | |
| 24 | |
| 1972 | 25 #ifndef CPU_X86_VM_VM_VERSION_X86_HPP |
| 26 #define CPU_X86_VM_VM_VERSION_X86_HPP | |
| 27 | |
| 28 #include "runtime/globals_extension.hpp" | |
| 29 #include "runtime/vm_version.hpp" | |
| 30 | |
| 585 | 31 class VM_Version : public Abstract_VM_Version { |
| 32 public: | |
| 33 // cpuid result register layouts. These are all unions of a uint32_t | |
| 34 // (in case anyone wants access to the register as a whole) and a bitfield. | |
| 35 | |
| 36 union StdCpuid1Eax { | |
| 37 uint32_t value; | |
| 38 struct { | |
| 39 uint32_t stepping : 4, | |
| 40 model : 4, | |
| 41 family : 4, | |
| 42 proc_type : 2, | |
| 43 : 2, | |
| 44 ext_model : 4, | |
| 45 ext_family : 8, | |
| 46 : 4; | |
| 47 } bits; | |
| 48 }; | |
| 49 | |
| 50 union StdCpuid1Ebx { // example, unused | |
| 51 uint32_t value; | |
| 52 struct { | |
| 53 uint32_t brand_id : 8, | |
| 54 clflush_size : 8, | |
| 55 threads_per_cpu : 8, | |
| 56 apic_id : 8; | |
| 57 } bits; | |
| 58 }; | |
| 59 | |
| 60 union StdCpuid1Ecx { | |
| 61 uint32_t value; | |
| 62 struct { | |
| 63 uint32_t sse3 : 1, | |
| 64 : 2, | |
| 65 monitor : 1, | |
| 66 : 1, | |
| 67 vmx : 1, | |
| 68 : 1, | |
| 69 est : 1, | |
| 70 : 1, | |
| 71 ssse3 : 1, | |
| 72 cid : 1, | |
| 73 : 2, | |
| 74 cmpxchg16: 1, | |
| 75 : 4, | |
| 76 dca : 1, | |
| 77 sse4_1 : 1, | |
| 78 sse4_2 : 1, | |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
585
diff
changeset
|
79 : 2, |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
585
diff
changeset
|
80 popcnt : 1, |
| 4759 | 81 : 3, |
| 82 osxsave : 1, | |
| 83 avx : 1, | |
| 84 : 3; | |
| 585 | 85 } bits; |
| 86 }; | |
| 87 | |
| 88 union StdCpuid1Edx { | |
| 89 uint32_t value; | |
| 90 struct { | |
| 91 uint32_t : 4, | |
| 92 tsc : 1, | |
| 93 : 3, | |
| 94 cmpxchg8 : 1, | |
| 95 : 6, | |
| 96 cmov : 1, | |
|
3787
6ae7a1561b53
6990015: Incorrect Icache line size is used for 64 bit x86
kvn
parents:
2479
diff
changeset
|
97 : 3, |
|
6ae7a1561b53
6990015: Incorrect Icache line size is used for 64 bit x86
kvn
parents:
2479
diff
changeset
|
98 clflush : 1, |
|
6ae7a1561b53
6990015: Incorrect Icache line size is used for 64 bit x86
kvn
parents:
2479
diff
changeset
|
99 : 3, |
| 585 | 100 mmx : 1, |
| 101 fxsr : 1, | |
| 102 sse : 1, | |
| 103 sse2 : 1, | |
| 104 : 1, | |
| 105 ht : 1, | |
| 106 : 3; | |
| 107 } bits; | |
| 108 }; | |
| 109 | |
| 110 union DcpCpuid4Eax { | |
| 111 uint32_t value; | |
| 112 struct { | |
| 113 uint32_t cache_type : 5, | |
| 114 : 21, | |
| 115 cores_per_cpu : 6; | |
| 116 } bits; | |
| 117 }; | |
| 118 | |
| 119 union DcpCpuid4Ebx { | |
| 120 uint32_t value; | |
| 121 struct { | |
| 122 uint32_t L1_line_size : 12, | |
| 123 partitions : 10, | |
| 124 associativity : 10; | |
| 125 } bits; | |
| 126 }; | |
| 127 | |
| 1622 | 128 union TplCpuidBEbx { |
| 129 uint32_t value; | |
| 130 struct { | |
| 131 uint32_t logical_cpus : 16, | |
| 132 : 16; | |
| 133 } bits; | |
| 134 }; | |
| 135 | |
| 585 | 136 union ExtCpuid1Ecx { |
| 137 uint32_t value; | |
| 138 struct { | |
| 139 uint32_t LahfSahf : 1, | |
| 140 CmpLegacy : 1, | |
| 141 : 4, | |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
643
diff
changeset
|
142 lzcnt : 1, |
| 585 | 143 sse4a : 1, |
| 144 misalignsse : 1, | |
| 145 prefetchw : 1, | |
| 146 : 22; | |
| 147 } bits; | |
| 148 }; | |
| 149 | |
| 150 union ExtCpuid1Edx { | |
| 151 uint32_t value; | |
| 152 struct { | |
| 153 uint32_t : 22, | |
| 154 mmx_amd : 1, | |
| 155 mmx : 1, | |
| 156 fxsr : 1, | |
| 157 : 4, | |
| 158 long_mode : 1, | |
| 159 tdnow2 : 1, | |
| 160 tdnow : 1; | |
| 161 } bits; | |
| 162 }; | |
| 163 | |
| 164 union ExtCpuid5Ex { | |
| 165 uint32_t value; | |
| 166 struct { | |
| 167 uint32_t L1_line_size : 8, | |
| 168 L1_tag_lines : 8, | |
| 169 L1_assoc : 8, | |
| 170 L1_size : 8; | |
| 171 } bits; | |
| 172 }; | |
| 173 | |
| 174 union ExtCpuid8Ecx { | |
| 175 uint32_t value; | |
| 176 struct { | |
| 177 uint32_t cores_per_cpu : 8, | |
| 178 : 24; | |
| 179 } bits; | |
| 180 }; | |
| 181 | |
| 4759 | 182 union SefCpuid7Eax { |
| 183 uint32_t value; | |
| 184 }; | |
| 185 | |
| 186 union SefCpuid7Ebx { | |
| 187 uint32_t value; | |
| 188 struct { | |
| 189 uint32_t fsgsbase : 1, | |
| 190 : 2, | |
| 191 bmi1 : 1, | |
| 192 : 1, | |
| 193 avx2 : 1, | |
| 194 : 2, | |
| 195 bmi2 : 1, | |
| 196 : 23; | |
| 197 } bits; | |
| 198 }; | |
| 199 | |
| 200 union XemXcr0Eax { | |
| 201 uint32_t value; | |
| 202 struct { | |
| 203 uint32_t x87 : 1, | |
| 204 sse : 1, | |
| 205 ymm : 1, | |
| 206 : 29; | |
| 207 } bits; | |
| 208 }; | |
| 209 | |
| 585 | 210 protected: |
| 211 static int _cpu; | |
| 212 static int _model; | |
| 213 static int _stepping; | |
| 214 static int _cpuFeatures; // features returned by the "cpuid" instruction | |
| 215 // 0 if this instruction is not available | |
| 216 static const char* _features_str; | |
| 217 | |
| 218 enum { | |
| 219 CPU_CX8 = (1 << 0), // next bits are from cpuid 1 (EDX) | |
| 220 CPU_CMOV = (1 << 1), | |
| 221 CPU_FXSR = (1 << 2), | |
| 222 CPU_HT = (1 << 3), | |
| 223 CPU_MMX = (1 << 4), | |
| 2479 | 224 CPU_3DNOW_PREFETCH = (1 << 5), // Processor supports 3dnow prefetch and prefetchw instructions |
| 225 // may not necessarily support other 3dnow instructions | |
| 585 | 226 CPU_SSE = (1 << 6), |
| 227 CPU_SSE2 = (1 << 7), | |
| 228 CPU_SSE3 = (1 << 8), // SSE3 comes from cpuid 1 (ECX) | |
| 229 CPU_SSSE3 = (1 << 9), | |
| 230 CPU_SSE4A = (1 << 10), | |
| 231 CPU_SSE4_1 = (1 << 11), | |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
585
diff
changeset
|
232 CPU_SSE4_2 = (1 << 12), |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
643
diff
changeset
|
233 CPU_POPCNT = (1 << 13), |
| 4759 | 234 CPU_LZCNT = (1 << 14), |
| 235 CPU_AVX = (1 << 15), | |
| 236 CPU_AVX2 = (1 << 16) | |
| 585 | 237 } cpuFeatureFlags; |
| 238 | |
| 239 // cpuid information block. All info derived from executing cpuid with | |
| 240 // various function numbers is stored here. Intel and AMD info is | |
| 241 // merged in this block: accessor methods disentangle it. | |
| 242 // | |
| 243 // The info block is laid out in subblocks of 4 dwords corresponding to | |
| 244 // eax, ebx, ecx and edx, whether or not they contain anything useful. | |
| 245 struct CpuidInfo { | |
| 246 // cpuid function 0 | |
| 247 uint32_t std_max_function; | |
| 248 uint32_t std_vendor_name_0; | |
| 249 uint32_t std_vendor_name_1; | |
| 250 uint32_t std_vendor_name_2; | |
| 251 | |
| 252 // cpuid function 1 | |
| 253 StdCpuid1Eax std_cpuid1_eax; | |
| 254 StdCpuid1Ebx std_cpuid1_ebx; | |
| 255 StdCpuid1Ecx std_cpuid1_ecx; | |
| 256 StdCpuid1Edx std_cpuid1_edx; | |
| 257 | |
| 258 // cpuid function 4 (deterministic cache parameters) | |
| 259 DcpCpuid4Eax dcp_cpuid4_eax; | |
| 260 DcpCpuid4Ebx dcp_cpuid4_ebx; | |
| 261 uint32_t dcp_cpuid4_ecx; // unused currently | |
| 262 uint32_t dcp_cpuid4_edx; // unused currently | |
| 263 | |
| 4759 | 264 // cpuid function 7 (structured extended features) |
| 265 SefCpuid7Eax sef_cpuid7_eax; | |
| 266 SefCpuid7Ebx sef_cpuid7_ebx; | |
| 267 uint32_t sef_cpuid7_ecx; // unused currently | |
| 268 uint32_t sef_cpuid7_edx; // unused currently | |
| 269 | |
| 1622 | 270 // cpuid function 0xB (processor topology) |
| 271 // ecx = 0 | |
| 272 uint32_t tpl_cpuidB0_eax; | |
| 273 TplCpuidBEbx tpl_cpuidB0_ebx; | |
| 274 uint32_t tpl_cpuidB0_ecx; // unused currently | |
| 275 uint32_t tpl_cpuidB0_edx; // unused currently | |
| 276 | |
| 277 // ecx = 1 | |
| 278 uint32_t tpl_cpuidB1_eax; | |
| 279 TplCpuidBEbx tpl_cpuidB1_ebx; | |
| 280 uint32_t tpl_cpuidB1_ecx; // unused currently | |
| 281 uint32_t tpl_cpuidB1_edx; // unused currently | |
| 282 | |
| 283 // ecx = 2 | |
| 284 uint32_t tpl_cpuidB2_eax; | |
| 285 TplCpuidBEbx tpl_cpuidB2_ebx; | |
| 286 uint32_t tpl_cpuidB2_ecx; // unused currently | |
| 287 uint32_t tpl_cpuidB2_edx; // unused currently | |
| 288 | |
| 585 | 289 // cpuid function 0x80000000 // example, unused |
| 290 uint32_t ext_max_function; | |
| 291 uint32_t ext_vendor_name_0; | |
| 292 uint32_t ext_vendor_name_1; | |
| 293 uint32_t ext_vendor_name_2; | |
| 294 | |
| 295 // cpuid function 0x80000001 | |
| 296 uint32_t ext_cpuid1_eax; // reserved | |
| 297 uint32_t ext_cpuid1_ebx; // reserved | |
| 298 ExtCpuid1Ecx ext_cpuid1_ecx; | |
| 299 ExtCpuid1Edx ext_cpuid1_edx; | |
| 300 | |
| 301 // cpuid functions 0x80000002 thru 0x80000004: example, unused | |
| 302 uint32_t proc_name_0, proc_name_1, proc_name_2, proc_name_3; | |
| 303 uint32_t proc_name_4, proc_name_5, proc_name_6, proc_name_7; | |
| 304 uint32_t proc_name_8, proc_name_9, proc_name_10,proc_name_11; | |
| 305 | |
| 306 // cpuid function 0x80000005 //AMD L1, Intel reserved | |
| 307 uint32_t ext_cpuid5_eax; // unused currently | |
| 308 uint32_t ext_cpuid5_ebx; // reserved | |
| 309 ExtCpuid5Ex ext_cpuid5_ecx; // L1 data cache info (AMD) | |
| 310 ExtCpuid5Ex ext_cpuid5_edx; // L1 instruction cache info (AMD) | |
| 311 | |
| 312 // cpuid function 0x80000008 | |
| 313 uint32_t ext_cpuid8_eax; // unused currently | |
| 314 uint32_t ext_cpuid8_ebx; // reserved | |
| 315 ExtCpuid8Ecx ext_cpuid8_ecx; | |
| 316 uint32_t ext_cpuid8_edx; // reserved | |
| 4759 | 317 |
| 318 // extended control register XCR0 (the XFEATURE_ENABLED_MASK register) | |
| 319 XemXcr0Eax xem_xcr0_eax; | |
| 320 uint32_t xem_xcr0_edx; // reserved | |
| 585 | 321 }; |
| 322 | |
| 323 // The actual cpuid info block | |
| 324 static CpuidInfo _cpuid_info; | |
| 325 | |
| 326 // Extractors and predicates | |
| 327 static uint32_t extended_cpu_family() { | |
| 328 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.family; | |
| 329 result += _cpuid_info.std_cpuid1_eax.bits.ext_family; | |
| 330 return result; | |
| 331 } | |
| 332 static uint32_t extended_cpu_model() { | |
| 333 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.model; | |
| 334 result |= _cpuid_info.std_cpuid1_eax.bits.ext_model << 4; | |
| 335 return result; | |
| 336 } | |
| 337 static uint32_t cpu_stepping() { | |
| 338 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.stepping; | |
| 339 return result; | |
| 340 } | |
| 341 static uint logical_processor_count() { | |
| 342 uint result = threads_per_core(); | |
| 343 return result; | |
| 344 } | |
| 345 static uint32_t feature_flags() { | |
| 346 uint32_t result = 0; | |
| 347 if (_cpuid_info.std_cpuid1_edx.bits.cmpxchg8 != 0) | |
| 348 result |= CPU_CX8; | |
| 349 if (_cpuid_info.std_cpuid1_edx.bits.cmov != 0) | |
| 350 result |= CPU_CMOV; | |
|
1789
a83b0246bb77
6934483: GCC 4.5 errors "suggest parentheses around something..." when compiling with -Werror and -Wall
twisti
parents:
1647
diff
changeset
|
351 if (_cpuid_info.std_cpuid1_edx.bits.fxsr != 0 || (is_amd() && |
|
a83b0246bb77
6934483: GCC 4.5 errors "suggest parentheses around something..." when compiling with -Werror and -Wall
twisti
parents:
1647
diff
changeset
|
352 _cpuid_info.ext_cpuid1_edx.bits.fxsr != 0)) |
| 585 | 353 result |= CPU_FXSR; |
| 354 // HT flag is set for multi-core processors also. | |
| 355 if (threads_per_core() > 1) | |
| 356 result |= CPU_HT; | |
|
1789
a83b0246bb77
6934483: GCC 4.5 errors "suggest parentheses around something..." when compiling with -Werror and -Wall
twisti
parents:
1647
diff
changeset
|
357 if (_cpuid_info.std_cpuid1_edx.bits.mmx != 0 || (is_amd() && |
|
a83b0246bb77
6934483: GCC 4.5 errors "suggest parentheses around something..." when compiling with -Werror and -Wall
twisti
parents:
1647
diff
changeset
|
358 _cpuid_info.ext_cpuid1_edx.bits.mmx != 0)) |
| 585 | 359 result |= CPU_MMX; |
| 360 if (_cpuid_info.std_cpuid1_edx.bits.sse != 0) | |
| 361 result |= CPU_SSE; | |
| 362 if (_cpuid_info.std_cpuid1_edx.bits.sse2 != 0) | |
| 363 result |= CPU_SSE2; | |
| 364 if (_cpuid_info.std_cpuid1_ecx.bits.sse3 != 0) | |
| 365 result |= CPU_SSE3; | |
| 366 if (_cpuid_info.std_cpuid1_ecx.bits.ssse3 != 0) | |
| 367 result |= CPU_SSSE3; | |
| 368 if (_cpuid_info.std_cpuid1_ecx.bits.sse4_1 != 0) | |
| 369 result |= CPU_SSE4_1; | |
| 370 if (_cpuid_info.std_cpuid1_ecx.bits.sse4_2 != 0) | |
| 371 result |= CPU_SSE4_2; | |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
585
diff
changeset
|
372 if (_cpuid_info.std_cpuid1_ecx.bits.popcnt != 0) |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
585
diff
changeset
|
373 result |= CPU_POPCNT; |
| 4759 | 374 if (_cpuid_info.std_cpuid1_ecx.bits.avx != 0 && |
| 375 _cpuid_info.std_cpuid1_ecx.bits.osxsave != 0 && | |
| 376 _cpuid_info.xem_xcr0_eax.bits.sse != 0 && | |
| 377 _cpuid_info.xem_xcr0_eax.bits.ymm != 0) { | |
| 378 result |= CPU_AVX; | |
| 379 if (_cpuid_info.sef_cpuid7_ebx.bits.avx2 != 0) | |
| 380 result |= CPU_AVX2; | |
| 381 } | |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
643
diff
changeset
|
382 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
643
diff
changeset
|
383 // AMD features. |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
643
diff
changeset
|
384 if (is_amd()) { |
| 2479 | 385 if ((_cpuid_info.ext_cpuid1_edx.bits.tdnow != 0) || |
| 386 (_cpuid_info.ext_cpuid1_ecx.bits.prefetchw != 0)) | |
| 387 result |= CPU_3DNOW_PREFETCH; | |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
643
diff
changeset
|
388 if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt != 0) |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
643
diff
changeset
|
389 result |= CPU_LZCNT; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
643
diff
changeset
|
390 if (_cpuid_info.ext_cpuid1_ecx.bits.sse4a != 0) |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
643
diff
changeset
|
391 result |= CPU_SSE4A; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
643
diff
changeset
|
392 } |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
643
diff
changeset
|
393 |
| 585 | 394 return result; |
| 395 } | |
| 396 | |
| 397 static void get_processor_features(); | |
| 398 | |
| 399 public: | |
| 400 // Offsets for cpuid asm stub | |
| 401 static ByteSize std_cpuid0_offset() { return byte_offset_of(CpuidInfo, std_max_function); } | |
| 402 static ByteSize std_cpuid1_offset() { return byte_offset_of(CpuidInfo, std_cpuid1_eax); } | |
| 403 static ByteSize dcp_cpuid4_offset() { return byte_offset_of(CpuidInfo, dcp_cpuid4_eax); } | |
| 4759 | 404 static ByteSize sef_cpuid7_offset() { return byte_offset_of(CpuidInfo, sef_cpuid7_eax); } |
| 585 | 405 static ByteSize ext_cpuid1_offset() { return byte_offset_of(CpuidInfo, ext_cpuid1_eax); } |
| 406 static ByteSize ext_cpuid5_offset() { return byte_offset_of(CpuidInfo, ext_cpuid5_eax); } | |
| 407 static ByteSize ext_cpuid8_offset() { return byte_offset_of(CpuidInfo, ext_cpuid8_eax); } | |
| 1622 | 408 static ByteSize tpl_cpuidB0_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB0_eax); } |
| 409 static ByteSize tpl_cpuidB1_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB1_eax); } | |
| 410 static ByteSize tpl_cpuidB2_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB2_eax); } | |
| 4759 | 411 static ByteSize xem_xcr0_offset() { return byte_offset_of(CpuidInfo, xem_xcr0_eax); } |
| 585 | 412 |
| 413 // Initialization | |
| 414 static void initialize(); | |
| 415 | |
| 416 // Asserts | |
| 417 static void assert_is_initialized() { | |
| 418 assert(_cpuid_info.std_cpuid1_eax.bits.family != 0, "VM_Version not initialized"); | |
| 419 } | |
| 420 | |
| 421 // | |
| 422 // Processor family: | |
| 423 // 3 - 386 | |
| 424 // 4 - 486 | |
| 425 // 5 - Pentium | |
| 426 // 6 - PentiumPro, Pentium II, Celeron, Xeon, Pentium III, Athlon, | |
| 427 // Pentium M, Core Solo, Core Duo, Core2 Duo | |
| 428 // family 6 model: 9, 13, 14, 15 | |
| 429 // 0x0f - Pentium 4, Opteron | |
| 430 // | |
| 431 // Note: The cpu family should be used to select between | |
| 432 // instruction sequences which are valid on all Intel | |
| 433 // processors. Use the feature test functions below to | |
| 434 // determine whether a particular instruction is supported. | |
| 435 // | |
| 436 static int cpu_family() { return _cpu;} | |
| 437 static bool is_P6() { return cpu_family() >= 6; } | |
| 438 | |
| 439 static bool is_amd() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x68747541; } // 'htuA' | |
| 440 static bool is_intel() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x756e6547; } // 'uneG' | |
| 441 | |
| 1647 | 442 static bool supports_processor_topology() { |
| 443 return (_cpuid_info.std_max_function >= 0xB) && | |
| 444 // eax[4:0] | ebx[0:15] == 0 indicates invalid topology level. | |
| 445 // Some cpus have max cpuid >= 0xB but do not support processor topology. | |
| 446 ((_cpuid_info.tpl_cpuidB0_eax & 0x1f | _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus) != 0); | |
| 447 } | |
| 448 | |
| 585 | 449 static uint cores_per_cpu() { |
| 450 uint result = 1; | |
| 451 if (is_intel()) { | |
| 1647 | 452 if (supports_processor_topology()) { |
| 1622 | 453 result = _cpuid_info.tpl_cpuidB1_ebx.bits.logical_cpus / |
| 454 _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus; | |
| 455 } else { | |
| 456 result = (_cpuid_info.dcp_cpuid4_eax.bits.cores_per_cpu + 1); | |
| 457 } | |
| 585 | 458 } else if (is_amd()) { |
| 459 result = (_cpuid_info.ext_cpuid8_ecx.bits.cores_per_cpu + 1); | |
| 460 } | |
| 461 return result; | |
| 462 } | |
| 463 | |
| 464 static uint threads_per_core() { | |
| 465 uint result = 1; | |
| 1647 | 466 if (is_intel() && supports_processor_topology()) { |
| 1622 | 467 result = _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus; |
| 468 } else if (_cpuid_info.std_cpuid1_edx.bits.ht != 0) { | |
| 585 | 469 result = _cpuid_info.std_cpuid1_ebx.bits.threads_per_cpu / |
| 470 cores_per_cpu(); | |
| 471 } | |
| 472 return result; | |
| 473 } | |
| 474 | |
| 3854 | 475 static intx prefetch_data_size() { |
| 585 | 476 intx result = 0; |
| 477 if (is_intel()) { | |
| 478 result = (_cpuid_info.dcp_cpuid4_ebx.bits.L1_line_size + 1); | |
| 479 } else if (is_amd()) { | |
| 480 result = _cpuid_info.ext_cpuid5_ecx.bits.L1_line_size; | |
| 481 } | |
| 482 if (result < 32) // not defined ? | |
| 483 result = 32; // 32 bytes by default on x86 and other x64 | |
| 484 return result; | |
| 485 } | |
| 486 | |
| 487 // | |
| 488 // Feature identification | |
| 489 // | |
| 490 static bool supports_cpuid() { return _cpuFeatures != 0; } | |
| 491 static bool supports_cmpxchg8() { return (_cpuFeatures & CPU_CX8) != 0; } | |
| 492 static bool supports_cmov() { return (_cpuFeatures & CPU_CMOV) != 0; } | |
| 493 static bool supports_fxsr() { return (_cpuFeatures & CPU_FXSR) != 0; } | |
| 494 static bool supports_ht() { return (_cpuFeatures & CPU_HT) != 0; } | |
| 495 static bool supports_mmx() { return (_cpuFeatures & CPU_MMX) != 0; } | |
| 496 static bool supports_sse() { return (_cpuFeatures & CPU_SSE) != 0; } | |
| 497 static bool supports_sse2() { return (_cpuFeatures & CPU_SSE2) != 0; } | |
| 498 static bool supports_sse3() { return (_cpuFeatures & CPU_SSE3) != 0; } | |
| 499 static bool supports_ssse3() { return (_cpuFeatures & CPU_SSSE3)!= 0; } | |
| 500 static bool supports_sse4_1() { return (_cpuFeatures & CPU_SSE4_1) != 0; } | |
| 501 static bool supports_sse4_2() { return (_cpuFeatures & CPU_SSE4_2) != 0; } | |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
585
diff
changeset
|
502 static bool supports_popcnt() { return (_cpuFeatures & CPU_POPCNT) != 0; } |
| 4759 | 503 static bool supports_avx() { return (_cpuFeatures & CPU_AVX) != 0; } |
| 504 static bool supports_avx2() { return (_cpuFeatures & CPU_AVX2) != 0; } | |
| 585 | 505 // |
| 506 // AMD features | |
| 507 // | |
| 2479 | 508 static bool supports_3dnow_prefetch() { return (_cpuFeatures & CPU_3DNOW_PREFETCH) != 0; } |
| 585 | 509 static bool supports_mmx_ext() { return is_amd() && _cpuid_info.ext_cpuid1_edx.bits.mmx_amd != 0; } |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
643
diff
changeset
|
510 static bool supports_lzcnt() { return (_cpuFeatures & CPU_LZCNT) != 0; } |
| 585 | 511 static bool supports_sse4a() { return (_cpuFeatures & CPU_SSE4A) != 0; } |
| 512 | |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1789
diff
changeset
|
513 // Intel Core and newer cpus have fast IDIV instruction (excluding Atom). |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1789
diff
changeset
|
514 static bool has_fast_idiv() { return is_intel() && cpu_family() == 6 && |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1789
diff
changeset
|
515 supports_sse3() && _model != 0x1C; } |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1789
diff
changeset
|
516 |
| 585 | 517 static bool supports_compare_and_exchange() { return true; } |
| 518 | |
| 519 static const char* cpu_features() { return _features_str; } | |
| 520 | |
| 521 static intx allocate_prefetch_distance() { | |
| 522 // This method should be called before allocate_prefetch_style(). | |
| 523 // | |
| 524 // Hardware prefetching (distance/size in bytes): | |
| 525 // Pentium 3 - 64 / 32 | |
| 526 // Pentium 4 - 256 / 128 | |
| 527 // Athlon - 64 / 32 ???? | |
| 528 // Opteron - 128 / 64 only when 2 sequential cache lines accessed | |
| 529 // Core - 128 / 64 | |
| 530 // | |
| 531 // Software prefetching (distance in bytes / instruction with best score): | |
| 532 // Pentium 3 - 128 / prefetchnta | |
| 533 // Pentium 4 - 512 / prefetchnta | |
| 534 // Athlon - 128 / prefetchnta | |
| 535 // Opteron - 256 / prefetchnta | |
| 536 // Core - 256 / prefetchnta | |
| 537 // It will be used only when AllocatePrefetchStyle > 0 | |
| 538 | |
| 539 intx count = AllocatePrefetchDistance; | |
| 540 if (count < 0) { // default ? | |
| 541 if (is_amd()) { // AMD | |
| 542 if (supports_sse2()) | |
| 543 count = 256; // Opteron | |
| 544 else | |
| 545 count = 128; // Athlon | |
| 546 } else { // Intel | |
| 547 if (supports_sse2()) | |
| 548 if (cpu_family() == 6) { | |
| 549 count = 256; // Pentium M, Core, Core2 | |
| 550 } else { | |
| 551 count = 512; // Pentium 4 | |
| 552 } | |
| 553 else | |
| 554 count = 128; // Pentium 3 (and all other old CPUs) | |
| 555 } | |
| 556 } | |
| 557 return count; | |
| 558 } | |
| 559 static intx allocate_prefetch_style() { | |
| 560 assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive"); | |
| 561 // Return 0 if AllocatePrefetchDistance was not defined. | |
| 562 return AllocatePrefetchDistance > 0 ? AllocatePrefetchStyle : 0; | |
| 563 } | |
| 564 | |
| 565 // Prefetch interval for gc copy/scan == 9 dcache lines. Derived from | |
| 566 // 50-warehouse specjbb runs on a 2-way 1.8ghz opteron using a 4gb heap. | |
| 567 // Tested intervals from 128 to 2048 in increments of 64 == one cache line. | |
| 568 // 256 bytes (4 dcache lines) was the nearest runner-up to 576. | |
| 569 | |
| 570 // gc copy/scan is disabled if prefetchw isn't supported, because | |
| 571 // Prefetch::write emits an inlined prefetchw on Linux. | |
| 572 // Do not use the 3dnow prefetchw instruction. It isn't supported on em64t. | |
| 573 // The used prefetcht0 instruction works for both amd64 and em64t. | |
| 574 static intx prefetch_copy_interval_in_bytes() { | |
| 575 intx interval = PrefetchCopyIntervalInBytes; | |
| 576 return interval >= 0 ? interval : 576; | |
| 577 } | |
| 578 static intx prefetch_scan_interval_in_bytes() { | |
| 579 intx interval = PrefetchScanIntervalInBytes; | |
| 580 return interval >= 0 ? interval : 576; | |
| 581 } | |
| 582 static intx prefetch_fields_ahead() { | |
| 583 intx count = PrefetchFieldsAhead; | |
| 584 return count >= 0 ? count : 1; | |
| 585 } | |
| 586 }; | |
| 1972 | 587 |
| 588 #endif // CPU_X86_VM_VM_VERSION_X86_HPP |