Mercurial > hg > truffle
annotate src/cpu/x86/vm/vm_version_x86.hpp @ 1622:76efbe666d6c
6964774: Adjust optimization flags setting
Summary: Adjust performance flags settings.
Reviewed-by: never, phh
| author | kvn |
|---|---|
| date | Tue, 29 Jun 2010 10:34:00 -0700 |
| parents | c18cbe5936b8 |
| children | 079980c86f33 |
| rev | line source |
|---|---|
| 585 | 1 /* |
| 1622 | 2 * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All Rights Reserved. |
| 585 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 4 * | |
| 5 * This code is free software; you can redistribute it and/or modify it | |
| 6 * under the terms of the GNU General Public License version 2 only, as | |
| 7 * published by the Free Software Foundation. | |
| 8 * | |
| 9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 * version 2 for more details (a copy is included in the LICENSE file that | |
| 13 * accompanied this code). | |
| 14 * | |
| 15 * You should have received a copy of the GNU General Public License version | |
| 16 * 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 * | |
|
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
| 585 | 22 * |
| 23 */ | |
| 24 | |
| 25 class VM_Version : public Abstract_VM_Version { | |
| 26 public: | |
| 27 // cpuid result register layouts. These are all unions of a uint32_t | |
| 28 // (in case anyone wants access to the register as a whole) and a bitfield. | |
| 29 | |
| 30 union StdCpuid1Eax { | |
| 31 uint32_t value; | |
| 32 struct { | |
| 33 uint32_t stepping : 4, | |
| 34 model : 4, | |
| 35 family : 4, | |
| 36 proc_type : 2, | |
| 37 : 2, | |
| 38 ext_model : 4, | |
| 39 ext_family : 8, | |
| 40 : 4; | |
| 41 } bits; | |
| 42 }; | |
| 43 | |
| 44 union StdCpuid1Ebx { // example, unused | |
| 45 uint32_t value; | |
| 46 struct { | |
| 47 uint32_t brand_id : 8, | |
| 48 clflush_size : 8, | |
| 49 threads_per_cpu : 8, | |
| 50 apic_id : 8; | |
| 51 } bits; | |
| 52 }; | |
| 53 | |
| 54 union StdCpuid1Ecx { | |
| 55 uint32_t value; | |
| 56 struct { | |
| 57 uint32_t sse3 : 1, | |
| 58 : 2, | |
| 59 monitor : 1, | |
| 60 : 1, | |
| 61 vmx : 1, | |
| 62 : 1, | |
| 63 est : 1, | |
| 64 : 1, | |
| 65 ssse3 : 1, | |
| 66 cid : 1, | |
| 67 : 2, | |
| 68 cmpxchg16: 1, | |
| 69 : 4, | |
| 70 dca : 1, | |
| 71 sse4_1 : 1, | |
| 72 sse4_2 : 1, | |
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73 : 2, |
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74 popcnt : 1, |
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75 : 8; |
| 585 | 76 } bits; |
| 77 }; | |
| 78 | |
| 79 union StdCpuid1Edx { | |
| 80 uint32_t value; | |
| 81 struct { | |
| 82 uint32_t : 4, | |
| 83 tsc : 1, | |
| 84 : 3, | |
| 85 cmpxchg8 : 1, | |
| 86 : 6, | |
| 87 cmov : 1, | |
| 88 : 7, | |
| 89 mmx : 1, | |
| 90 fxsr : 1, | |
| 91 sse : 1, | |
| 92 sse2 : 1, | |
| 93 : 1, | |
| 94 ht : 1, | |
| 95 : 3; | |
| 96 } bits; | |
| 97 }; | |
| 98 | |
| 99 union DcpCpuid4Eax { | |
| 100 uint32_t value; | |
| 101 struct { | |
| 102 uint32_t cache_type : 5, | |
| 103 : 21, | |
| 104 cores_per_cpu : 6; | |
| 105 } bits; | |
| 106 }; | |
| 107 | |
| 108 union DcpCpuid4Ebx { | |
| 109 uint32_t value; | |
| 110 struct { | |
| 111 uint32_t L1_line_size : 12, | |
| 112 partitions : 10, | |
| 113 associativity : 10; | |
| 114 } bits; | |
| 115 }; | |
| 116 | |
| 1622 | 117 union TplCpuidBEbx { |
| 118 uint32_t value; | |
| 119 struct { | |
| 120 uint32_t logical_cpus : 16, | |
| 121 : 16; | |
| 122 } bits; | |
| 123 }; | |
| 124 | |
| 585 | 125 union ExtCpuid1Ecx { |
| 126 uint32_t value; | |
| 127 struct { | |
| 128 uint32_t LahfSahf : 1, | |
| 129 CmpLegacy : 1, | |
| 130 : 4, | |
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131 lzcnt : 1, |
| 585 | 132 sse4a : 1, |
| 133 misalignsse : 1, | |
| 134 prefetchw : 1, | |
| 135 : 22; | |
| 136 } bits; | |
| 137 }; | |
| 138 | |
| 139 union ExtCpuid1Edx { | |
| 140 uint32_t value; | |
| 141 struct { | |
| 142 uint32_t : 22, | |
| 143 mmx_amd : 1, | |
| 144 mmx : 1, | |
| 145 fxsr : 1, | |
| 146 : 4, | |
| 147 long_mode : 1, | |
| 148 tdnow2 : 1, | |
| 149 tdnow : 1; | |
| 150 } bits; | |
| 151 }; | |
| 152 | |
| 153 union ExtCpuid5Ex { | |
| 154 uint32_t value; | |
| 155 struct { | |
| 156 uint32_t L1_line_size : 8, | |
| 157 L1_tag_lines : 8, | |
| 158 L1_assoc : 8, | |
| 159 L1_size : 8; | |
| 160 } bits; | |
| 161 }; | |
| 162 | |
| 163 union ExtCpuid8Ecx { | |
| 164 uint32_t value; | |
| 165 struct { | |
| 166 uint32_t cores_per_cpu : 8, | |
| 167 : 24; | |
| 168 } bits; | |
| 169 }; | |
| 170 | |
| 171 protected: | |
| 172 static int _cpu; | |
| 173 static int _model; | |
| 174 static int _stepping; | |
| 175 static int _cpuFeatures; // features returned by the "cpuid" instruction | |
| 176 // 0 if this instruction is not available | |
| 177 static const char* _features_str; | |
| 178 | |
| 179 enum { | |
| 180 CPU_CX8 = (1 << 0), // next bits are from cpuid 1 (EDX) | |
| 181 CPU_CMOV = (1 << 1), | |
| 182 CPU_FXSR = (1 << 2), | |
| 183 CPU_HT = (1 << 3), | |
| 184 CPU_MMX = (1 << 4), | |
| 185 CPU_3DNOW = (1 << 5), // 3DNow comes from cpuid 0x80000001 (EDX) | |
| 186 CPU_SSE = (1 << 6), | |
| 187 CPU_SSE2 = (1 << 7), | |
| 188 CPU_SSE3 = (1 << 8), // SSE3 comes from cpuid 1 (ECX) | |
| 189 CPU_SSSE3 = (1 << 9), | |
| 190 CPU_SSE4A = (1 << 10), | |
| 191 CPU_SSE4_1 = (1 << 11), | |
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192 CPU_SSE4_2 = (1 << 12), |
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193 CPU_POPCNT = (1 << 13), |
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194 CPU_LZCNT = (1 << 14) |
| 585 | 195 } cpuFeatureFlags; |
| 196 | |
| 197 // cpuid information block. All info derived from executing cpuid with | |
| 198 // various function numbers is stored here. Intel and AMD info is | |
| 199 // merged in this block: accessor methods disentangle it. | |
| 200 // | |
| 201 // The info block is laid out in subblocks of 4 dwords corresponding to | |
| 202 // eax, ebx, ecx and edx, whether or not they contain anything useful. | |
| 203 struct CpuidInfo { | |
| 204 // cpuid function 0 | |
| 205 uint32_t std_max_function; | |
| 206 uint32_t std_vendor_name_0; | |
| 207 uint32_t std_vendor_name_1; | |
| 208 uint32_t std_vendor_name_2; | |
| 209 | |
| 210 // cpuid function 1 | |
| 211 StdCpuid1Eax std_cpuid1_eax; | |
| 212 StdCpuid1Ebx std_cpuid1_ebx; | |
| 213 StdCpuid1Ecx std_cpuid1_ecx; | |
| 214 StdCpuid1Edx std_cpuid1_edx; | |
| 215 | |
| 216 // cpuid function 4 (deterministic cache parameters) | |
| 217 DcpCpuid4Eax dcp_cpuid4_eax; | |
| 218 DcpCpuid4Ebx dcp_cpuid4_ebx; | |
| 219 uint32_t dcp_cpuid4_ecx; // unused currently | |
| 220 uint32_t dcp_cpuid4_edx; // unused currently | |
| 221 | |
| 1622 | 222 // cpuid function 0xB (processor topology) |
| 223 // ecx = 0 | |
| 224 uint32_t tpl_cpuidB0_eax; | |
| 225 TplCpuidBEbx tpl_cpuidB0_ebx; | |
| 226 uint32_t tpl_cpuidB0_ecx; // unused currently | |
| 227 uint32_t tpl_cpuidB0_edx; // unused currently | |
| 228 | |
| 229 // ecx = 1 | |
| 230 uint32_t tpl_cpuidB1_eax; | |
| 231 TplCpuidBEbx tpl_cpuidB1_ebx; | |
| 232 uint32_t tpl_cpuidB1_ecx; // unused currently | |
| 233 uint32_t tpl_cpuidB1_edx; // unused currently | |
| 234 | |
| 235 // ecx = 2 | |
| 236 uint32_t tpl_cpuidB2_eax; | |
| 237 TplCpuidBEbx tpl_cpuidB2_ebx; | |
| 238 uint32_t tpl_cpuidB2_ecx; // unused currently | |
| 239 uint32_t tpl_cpuidB2_edx; // unused currently | |
| 240 | |
| 585 | 241 // cpuid function 0x80000000 // example, unused |
| 242 uint32_t ext_max_function; | |
| 243 uint32_t ext_vendor_name_0; | |
| 244 uint32_t ext_vendor_name_1; | |
| 245 uint32_t ext_vendor_name_2; | |
| 246 | |
| 247 // cpuid function 0x80000001 | |
| 248 uint32_t ext_cpuid1_eax; // reserved | |
| 249 uint32_t ext_cpuid1_ebx; // reserved | |
| 250 ExtCpuid1Ecx ext_cpuid1_ecx; | |
| 251 ExtCpuid1Edx ext_cpuid1_edx; | |
| 252 | |
| 253 // cpuid functions 0x80000002 thru 0x80000004: example, unused | |
| 254 uint32_t proc_name_0, proc_name_1, proc_name_2, proc_name_3; | |
| 255 uint32_t proc_name_4, proc_name_5, proc_name_6, proc_name_7; | |
| 256 uint32_t proc_name_8, proc_name_9, proc_name_10,proc_name_11; | |
| 257 | |
| 258 // cpuid function 0x80000005 //AMD L1, Intel reserved | |
| 259 uint32_t ext_cpuid5_eax; // unused currently | |
| 260 uint32_t ext_cpuid5_ebx; // reserved | |
| 261 ExtCpuid5Ex ext_cpuid5_ecx; // L1 data cache info (AMD) | |
| 262 ExtCpuid5Ex ext_cpuid5_edx; // L1 instruction cache info (AMD) | |
| 263 | |
| 264 // cpuid function 0x80000008 | |
| 265 uint32_t ext_cpuid8_eax; // unused currently | |
| 266 uint32_t ext_cpuid8_ebx; // reserved | |
| 267 ExtCpuid8Ecx ext_cpuid8_ecx; | |
| 268 uint32_t ext_cpuid8_edx; // reserved | |
| 269 }; | |
| 270 | |
| 271 // The actual cpuid info block | |
| 272 static CpuidInfo _cpuid_info; | |
| 273 | |
| 274 // Extractors and predicates | |
| 275 static uint32_t extended_cpu_family() { | |
| 276 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.family; | |
| 277 result += _cpuid_info.std_cpuid1_eax.bits.ext_family; | |
| 278 return result; | |
| 279 } | |
| 280 static uint32_t extended_cpu_model() { | |
| 281 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.model; | |
| 282 result |= _cpuid_info.std_cpuid1_eax.bits.ext_model << 4; | |
| 283 return result; | |
| 284 } | |
| 285 static uint32_t cpu_stepping() { | |
| 286 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.stepping; | |
| 287 return result; | |
| 288 } | |
| 289 static uint logical_processor_count() { | |
| 290 uint result = threads_per_core(); | |
| 291 return result; | |
| 292 } | |
| 293 static uint32_t feature_flags() { | |
| 294 uint32_t result = 0; | |
| 295 if (_cpuid_info.std_cpuid1_edx.bits.cmpxchg8 != 0) | |
| 296 result |= CPU_CX8; | |
| 297 if (_cpuid_info.std_cpuid1_edx.bits.cmov != 0) | |
| 298 result |= CPU_CMOV; | |
| 299 if (_cpuid_info.std_cpuid1_edx.bits.fxsr != 0 || is_amd() && | |
| 300 _cpuid_info.ext_cpuid1_edx.bits.fxsr != 0) | |
| 301 result |= CPU_FXSR; | |
| 302 // HT flag is set for multi-core processors also. | |
| 303 if (threads_per_core() > 1) | |
| 304 result |= CPU_HT; | |
| 305 if (_cpuid_info.std_cpuid1_edx.bits.mmx != 0 || is_amd() && | |
| 306 _cpuid_info.ext_cpuid1_edx.bits.mmx != 0) | |
| 307 result |= CPU_MMX; | |
| 308 if (_cpuid_info.std_cpuid1_edx.bits.sse != 0) | |
| 309 result |= CPU_SSE; | |
| 310 if (_cpuid_info.std_cpuid1_edx.bits.sse2 != 0) | |
| 311 result |= CPU_SSE2; | |
| 312 if (_cpuid_info.std_cpuid1_ecx.bits.sse3 != 0) | |
| 313 result |= CPU_SSE3; | |
| 314 if (_cpuid_info.std_cpuid1_ecx.bits.ssse3 != 0) | |
| 315 result |= CPU_SSSE3; | |
| 316 if (_cpuid_info.std_cpuid1_ecx.bits.sse4_1 != 0) | |
| 317 result |= CPU_SSE4_1; | |
| 318 if (_cpuid_info.std_cpuid1_ecx.bits.sse4_2 != 0) | |
| 319 result |= CPU_SSE4_2; | |
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320 if (_cpuid_info.std_cpuid1_ecx.bits.popcnt != 0) |
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321 result |= CPU_POPCNT; |
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322 |
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323 // AMD features. |
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324 if (is_amd()) { |
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325 if (_cpuid_info.ext_cpuid1_edx.bits.tdnow != 0) |
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326 result |= CPU_3DNOW; |
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327 if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt != 0) |
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328 result |= CPU_LZCNT; |
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329 if (_cpuid_info.ext_cpuid1_ecx.bits.sse4a != 0) |
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330 result |= CPU_SSE4A; |
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331 } |
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332 |
| 585 | 333 return result; |
| 334 } | |
| 335 | |
| 336 static void get_processor_features(); | |
| 337 | |
| 338 public: | |
| 339 // Offsets for cpuid asm stub | |
| 340 static ByteSize std_cpuid0_offset() { return byte_offset_of(CpuidInfo, std_max_function); } | |
| 341 static ByteSize std_cpuid1_offset() { return byte_offset_of(CpuidInfo, std_cpuid1_eax); } | |
| 342 static ByteSize dcp_cpuid4_offset() { return byte_offset_of(CpuidInfo, dcp_cpuid4_eax); } | |
| 343 static ByteSize ext_cpuid1_offset() { return byte_offset_of(CpuidInfo, ext_cpuid1_eax); } | |
| 344 static ByteSize ext_cpuid5_offset() { return byte_offset_of(CpuidInfo, ext_cpuid5_eax); } | |
| 345 static ByteSize ext_cpuid8_offset() { return byte_offset_of(CpuidInfo, ext_cpuid8_eax); } | |
| 1622 | 346 static ByteSize tpl_cpuidB0_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB0_eax); } |
| 347 static ByteSize tpl_cpuidB1_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB1_eax); } | |
| 348 static ByteSize tpl_cpuidB2_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB2_eax); } | |
| 585 | 349 |
| 350 // Initialization | |
| 351 static void initialize(); | |
| 352 | |
| 353 // Asserts | |
| 354 static void assert_is_initialized() { | |
| 355 assert(_cpuid_info.std_cpuid1_eax.bits.family != 0, "VM_Version not initialized"); | |
| 356 } | |
| 357 | |
| 358 // | |
| 359 // Processor family: | |
| 360 // 3 - 386 | |
| 361 // 4 - 486 | |
| 362 // 5 - Pentium | |
| 363 // 6 - PentiumPro, Pentium II, Celeron, Xeon, Pentium III, Athlon, | |
| 364 // Pentium M, Core Solo, Core Duo, Core2 Duo | |
| 365 // family 6 model: 9, 13, 14, 15 | |
| 366 // 0x0f - Pentium 4, Opteron | |
| 367 // | |
| 368 // Note: The cpu family should be used to select between | |
| 369 // instruction sequences which are valid on all Intel | |
| 370 // processors. Use the feature test functions below to | |
| 371 // determine whether a particular instruction is supported. | |
| 372 // | |
| 373 static int cpu_family() { return _cpu;} | |
| 374 static bool is_P6() { return cpu_family() >= 6; } | |
| 375 | |
| 376 static bool is_amd() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x68747541; } // 'htuA' | |
| 377 static bool is_intel() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x756e6547; } // 'uneG' | |
| 378 | |
| 379 static uint cores_per_cpu() { | |
| 380 uint result = 1; | |
| 381 if (is_intel()) { | |
| 1622 | 382 if (_cpuid_info.std_max_function >= 0xB) { |
| 383 result = _cpuid_info.tpl_cpuidB1_ebx.bits.logical_cpus / | |
| 384 _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus; | |
| 385 } else { | |
| 386 result = (_cpuid_info.dcp_cpuid4_eax.bits.cores_per_cpu + 1); | |
| 387 } | |
| 585 | 388 } else if (is_amd()) { |
| 389 result = (_cpuid_info.ext_cpuid8_ecx.bits.cores_per_cpu + 1); | |
| 390 } | |
| 391 return result; | |
| 392 } | |
| 393 | |
| 394 static uint threads_per_core() { | |
| 395 uint result = 1; | |
| 1622 | 396 if (is_intel() && _cpuid_info.std_max_function >= 0xB) { |
| 397 result = _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus; | |
| 398 } else if (_cpuid_info.std_cpuid1_edx.bits.ht != 0) { | |
| 585 | 399 result = _cpuid_info.std_cpuid1_ebx.bits.threads_per_cpu / |
| 400 cores_per_cpu(); | |
| 401 } | |
| 402 return result; | |
| 403 } | |
| 404 | |
| 405 static intx L1_data_cache_line_size() { | |
| 406 intx result = 0; | |
| 407 if (is_intel()) { | |
| 408 result = (_cpuid_info.dcp_cpuid4_ebx.bits.L1_line_size + 1); | |
| 409 } else if (is_amd()) { | |
| 410 result = _cpuid_info.ext_cpuid5_ecx.bits.L1_line_size; | |
| 411 } | |
| 412 if (result < 32) // not defined ? | |
| 413 result = 32; // 32 bytes by default on x86 and other x64 | |
| 414 return result; | |
| 415 } | |
| 416 | |
| 417 // | |
| 418 // Feature identification | |
| 419 // | |
| 420 static bool supports_cpuid() { return _cpuFeatures != 0; } | |
| 421 static bool supports_cmpxchg8() { return (_cpuFeatures & CPU_CX8) != 0; } | |
| 422 static bool supports_cmov() { return (_cpuFeatures & CPU_CMOV) != 0; } | |
| 423 static bool supports_fxsr() { return (_cpuFeatures & CPU_FXSR) != 0; } | |
| 424 static bool supports_ht() { return (_cpuFeatures & CPU_HT) != 0; } | |
| 425 static bool supports_mmx() { return (_cpuFeatures & CPU_MMX) != 0; } | |
| 426 static bool supports_sse() { return (_cpuFeatures & CPU_SSE) != 0; } | |
| 427 static bool supports_sse2() { return (_cpuFeatures & CPU_SSE2) != 0; } | |
| 428 static bool supports_sse3() { return (_cpuFeatures & CPU_SSE3) != 0; } | |
| 429 static bool supports_ssse3() { return (_cpuFeatures & CPU_SSSE3)!= 0; } | |
| 430 static bool supports_sse4_1() { return (_cpuFeatures & CPU_SSE4_1) != 0; } | |
| 431 static bool supports_sse4_2() { return (_cpuFeatures & CPU_SSE4_2) != 0; } | |
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6378821: bitCount() should use POPC on SPARC processors and AMD+10h
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432 static bool supports_popcnt() { return (_cpuFeatures & CPU_POPCNT) != 0; } |
| 585 | 433 // |
| 434 // AMD features | |
| 435 // | |
| 436 static bool supports_3dnow() { return (_cpuFeatures & CPU_3DNOW) != 0; } | |
| 437 static bool supports_mmx_ext() { return is_amd() && _cpuid_info.ext_cpuid1_edx.bits.mmx_amd != 0; } | |
| 438 static bool supports_3dnow2() { return is_amd() && _cpuid_info.ext_cpuid1_edx.bits.tdnow2 != 0; } | |
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6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
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439 static bool supports_lzcnt() { return (_cpuFeatures & CPU_LZCNT) != 0; } |
| 585 | 440 static bool supports_sse4a() { return (_cpuFeatures & CPU_SSE4A) != 0; } |
| 441 | |
| 442 static bool supports_compare_and_exchange() { return true; } | |
| 443 | |
| 444 static const char* cpu_features() { return _features_str; } | |
| 445 | |
| 446 static intx allocate_prefetch_distance() { | |
| 447 // This method should be called before allocate_prefetch_style(). | |
| 448 // | |
| 449 // Hardware prefetching (distance/size in bytes): | |
| 450 // Pentium 3 - 64 / 32 | |
| 451 // Pentium 4 - 256 / 128 | |
| 452 // Athlon - 64 / 32 ???? | |
| 453 // Opteron - 128 / 64 only when 2 sequential cache lines accessed | |
| 454 // Core - 128 / 64 | |
| 455 // | |
| 456 // Software prefetching (distance in bytes / instruction with best score): | |
| 457 // Pentium 3 - 128 / prefetchnta | |
| 458 // Pentium 4 - 512 / prefetchnta | |
| 459 // Athlon - 128 / prefetchnta | |
| 460 // Opteron - 256 / prefetchnta | |
| 461 // Core - 256 / prefetchnta | |
| 462 // It will be used only when AllocatePrefetchStyle > 0 | |
| 463 | |
| 464 intx count = AllocatePrefetchDistance; | |
| 465 if (count < 0) { // default ? | |
| 466 if (is_amd()) { // AMD | |
| 467 if (supports_sse2()) | |
| 468 count = 256; // Opteron | |
| 469 else | |
| 470 count = 128; // Athlon | |
| 471 } else { // Intel | |
| 472 if (supports_sse2()) | |
| 473 if (cpu_family() == 6) { | |
| 474 count = 256; // Pentium M, Core, Core2 | |
| 475 } else { | |
| 476 count = 512; // Pentium 4 | |
| 477 } | |
| 478 else | |
| 479 count = 128; // Pentium 3 (and all other old CPUs) | |
| 480 } | |
| 481 } | |
| 482 return count; | |
| 483 } | |
| 484 static intx allocate_prefetch_style() { | |
| 485 assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive"); | |
| 486 // Return 0 if AllocatePrefetchDistance was not defined. | |
| 487 return AllocatePrefetchDistance > 0 ? AllocatePrefetchStyle : 0; | |
| 488 } | |
| 489 | |
| 490 // Prefetch interval for gc copy/scan == 9 dcache lines. Derived from | |
| 491 // 50-warehouse specjbb runs on a 2-way 1.8ghz opteron using a 4gb heap. | |
| 492 // Tested intervals from 128 to 2048 in increments of 64 == one cache line. | |
| 493 // 256 bytes (4 dcache lines) was the nearest runner-up to 576. | |
| 494 | |
| 495 // gc copy/scan is disabled if prefetchw isn't supported, because | |
| 496 // Prefetch::write emits an inlined prefetchw on Linux. | |
| 497 // Do not use the 3dnow prefetchw instruction. It isn't supported on em64t. | |
| 498 // The used prefetcht0 instruction works for both amd64 and em64t. | |
| 499 static intx prefetch_copy_interval_in_bytes() { | |
| 500 intx interval = PrefetchCopyIntervalInBytes; | |
| 501 return interval >= 0 ? interval : 576; | |
| 502 } | |
| 503 static intx prefetch_scan_interval_in_bytes() { | |
| 504 intx interval = PrefetchScanIntervalInBytes; | |
| 505 return interval >= 0 ? interval : 576; | |
| 506 } | |
| 507 static intx prefetch_fields_ahead() { | |
| 508 intx count = PrefetchFieldsAhead; | |
| 509 return count >= 0 ? count : 1; | |
| 510 } | |
| 511 }; |