Mercurial > hg > truffle
annotate graal/com.oracle.graal.hsail/src/com/oracle/graal/hsail/HSAIL.java @ 13766:1a81855dae10
removed unused PTX code
author | Doug Simon <doug.simon@oracle.com> |
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date | Mon, 27 Jan 2014 15:49:33 +0100 |
parents | 343541fb3b49 |
children | 82e4fe6fa525 |
rev | line source |
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1 /* |
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2 * Copyright (c) 2009, 2011, Oracle and/or its affiliates. All rights reserved. |
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3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
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4 * |
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5 * This code is free software; you can redistribute it and/or modify it |
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6 * under the terms of the GNU General Public License version 2 only, as |
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7 * published by the Free Software Foundation. |
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8 * |
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9 * This code is distributed in the hope that it will be useful, but WITHOUT |
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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12 * version 2 for more details (a copy is included in the LICENSE file that |
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13 * accompanied this code). |
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14 * |
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15 * You should have received a copy of the GNU General Public License version |
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16 * 2 along with this work; if not, write to the Free Software Foundation, |
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17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
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18 * |
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
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22 */ |
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23 package com.oracle.graal.hsail; |
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24 |
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25 import static com.oracle.graal.api.code.ValueUtil.*; |
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26 |
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27 import java.nio.*; |
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28 |
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29 import com.oracle.graal.api.code.*; |
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30 import com.oracle.graal.api.code.Register.RegisterCategory; |
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31 import com.oracle.graal.api.meta.*; |
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32 |
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33 /** |
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34 * Represents the HSAIL architecture. |
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35 */ |
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36 public class HSAIL extends Architecture { |
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37 |
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38 public static final RegisterCategory CPU = new RegisterCategory("CPU"); |
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39 public static final RegisterCategory FPU = new RegisterCategory("FPU"); |
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40 |
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41 // Control registers. |
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42 public static final Register c0 = new Register(0, 0, "c0", CPU); |
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43 public static final Register c1 = new Register(1, 1, "c1", CPU); |
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44 public static final Register c2 = new Register(2, 2, "c2", CPU); |
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45 public static final Register c3 = new Register(3, 3, "c3", CPU); |
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46 public static final Register c4 = new Register(4, 4, "c4", CPU); |
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47 public static final Register c5 = new Register(5, 5, "c5", CPU); |
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48 public static final Register c6 = new Register(6, 6, "c6", CPU); |
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49 public static final Register c7 = new Register(7, 7, "c7", CPU); |
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50 |
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51 // 32 bit registers. |
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52 public static final Register s0 = new Register(8, 0, "s0", CPU); |
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53 public static final Register s1 = new Register(9, 1, "s1", CPU); |
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54 public static final Register s2 = new Register(10, 2, "s2", CPU); |
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55 public static final Register s3 = new Register(11, 3, "s3", CPU); |
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56 public static final Register s4 = new Register(12, 4, "s4", CPU); |
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57 public static final Register s5 = new Register(13, 5, "s5", CPU); |
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58 public static final Register s6 = new Register(14, 6, "s6", CPU); |
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59 public static final Register s7 = new Register(15, 7, "s7", CPU); |
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60 public static final Register s8 = new Register(16, 8, "s8", CPU); |
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61 public static final Register s9 = new Register(17, 9, "s9", CPU); |
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62 public static final Register s10 = new Register(18, 10, "s10", CPU); |
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63 public static final Register s11 = new Register(19, 11, "s11", CPU); |
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64 public static final Register s12 = new Register(20, 12, "s12", CPU); |
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65 public static final Register s13 = new Register(21, 13, "s13", CPU); |
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66 public static final Register s14 = new Register(22, 14, "s14", CPU); |
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67 public static final Register s15 = new Register(23, 15, "s15", CPU); |
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68 public static final Register s16 = new Register(24, 16, "s16", CPU); |
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69 public static final Register s17 = new Register(25, 17, "s17", CPU); |
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70 public static final Register s18 = new Register(26, 18, "s18", CPU); |
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71 public static final Register s19 = new Register(27, 19, "s19", CPU); |
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72 public static final Register s20 = new Register(28, 20, "s20", CPU); |
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73 public static final Register s21 = new Register(29, 21, "s21", CPU); |
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74 public static final Register s22 = new Register(30, 22, "s22", CPU); |
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75 public static final Register s23 = new Register(31, 23, "s23", CPU); |
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76 public static final Register s24 = new Register(32, 24, "s24", CPU); |
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77 public static final Register s25 = new Register(33, 25, "s25", CPU); |
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78 public static final Register s26 = new Register(34, 26, "s26", CPU); |
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79 public static final Register s27 = new Register(35, 27, "s27", CPU); |
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80 public static final Register s28 = new Register(36, 28, "s28", CPU); |
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81 public static final Register s29 = new Register(37, 29, "s29", CPU); |
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82 public static final Register s30 = new Register(38, 30, "s30", CPU); |
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83 public static final Register s31 = new Register(39, 31, "s31", CPU); |
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84 |
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85 // 64 bit registers. |
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86 public static final Register d0 = new Register(40, 0, "d0", CPU); |
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87 public static final Register d1 = new Register(41, 1, "d1", CPU); |
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88 public static final Register d2 = new Register(42, 2, "d2", CPU); |
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89 public static final Register d3 = new Register(43, 3, "d3", CPU); |
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90 public static final Register d4 = new Register(44, 4, "d4", CPU); |
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91 public static final Register d5 = new Register(45, 5, "d5", CPU); |
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92 public static final Register d6 = new Register(46, 6, "d6", CPU); |
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93 public static final Register d7 = new Register(47, 7, "d7", CPU); |
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94 public static final Register d8 = new Register(48, 8, "d8", CPU); |
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95 public static final Register d9 = new Register(49, 9, "d9", CPU); |
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96 public static final Register d10 = new Register(50, 10, "d10", CPU); |
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97 public static final Register d11 = new Register(51, 11, "d11", CPU); |
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98 public static final Register d12 = new Register(52, 12, "d12", CPU); |
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99 public static final Register d13 = new Register(53, 13, "d13", CPU); |
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100 public static final Register d14 = new Register(54, 14, "d14", CPU); |
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101 public static final Register d15 = new Register(55, 15, "d15", CPU); |
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102 |
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103 // 128 bit registers. |
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104 public static final Register q0 = new Register(56, 0, "q0", CPU); |
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105 public static final Register q1 = new Register(57, 1, "q1", CPU); |
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106 public static final Register q2 = new Register(58, 2, "q2", CPU); |
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107 public static final Register q3 = new Register(59, 3, "q3", CPU); |
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108 public static final Register q4 = new Register(60, 4, "q4", CPU); |
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109 public static final Register q5 = new Register(61, 5, "q5", CPU); |
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110 public static final Register q6 = new Register(62, 6, "q6", CPU); |
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111 public static final Register q7 = new Register(63, 7, "q7", CPU); |
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112 public static final Register q8 = new Register(64, 8, "q8", CPU); |
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113 public static final Register q9 = new Register(65, 9, "q9", CPU); |
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114 public static final Register q10 = new Register(66, 10, "q10", CPU); |
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115 public static final Register q11 = new Register(67, 11, "q11", CPU); |
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116 public static final Register q12 = new Register(68, 12, "q12", CPU); |
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117 public static final Register q13 = new Register(69, 13, "q13", CPU); |
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118 public static final Register q14 = new Register(70, 14, "q14", CPU); |
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119 public static final Register q15 = new Register(71, 15, "q15", CPU); |
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120 |
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121 // @formatter:off |
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122 public static final Register[] cRegisters = { |
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123 c0, c1, c2, c3, c4, c5, c6, c7 |
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124 }; |
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125 |
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126 public static final Register[] sRegisters = { |
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127 s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, |
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128 s11, s12, s13, s14, s15, s16, s17, s18, s19, |
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129 s20, s21, s22, s23, s24, s25, s26, s27, s28, |
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130 s29, s30, s31 |
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131 }; |
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132 |
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133 public static final Register[] dRegisters = { |
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134 d0, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10, d11, d12, d13, d14, d15 |
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135 }; |
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136 |
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137 public static final Register[] qRegisters = { |
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138 q0, q1, q2, q3, q4, q5, q6, q7, q8, q9, q10, q11, q12, q13, q14, q15 |
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139 }; |
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140 |
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141 public static final Register[] allRegisters = { |
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142 c0, c1, c2, c3, c4, c5, c6, c7, s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, |
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143 d0, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10, d11, d12, d13, |
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144 d14, d15, q0, q1, q2, q3, q4, q5, q6, q7, q8, q9, q10, q11, |
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145 q12, q13, q14, q15 |
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146 }; |
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147 |
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149 | |
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150 public HSAIL() { |
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151 super("HSAIL", 8, ByteOrder.LITTLE_ENDIAN, false, allRegisters, 0, 1, q15.encoding + 1, 8); |
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152 } |
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153 |
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154 public static int getStackOffset(Value reg) { |
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155 return -(((StackSlot) reg).getRawOffset()); |
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156 } |
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157 |
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158 public static String mapStackSlot(Value reg) { |
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159 StackSlot s = (StackSlot) reg; |
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160 long offset = -s.getRawOffset(); |
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161 return "[%spillseg]" + "[" + offset + "]"; |
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162 } |
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163 |
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164 public static String mapRegister(Value arg) { |
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165 Register reg; |
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166 int encoding = 0; |
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167 String regPrefix = null; |
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168 Kind kind = arg.getKind(); |
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169 if (kind == Kind.Double || kind == Kind.Long) { |
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170 regPrefix = "$d"; |
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171 } else if (kind == Kind.Int || kind == Kind.Float || kind == Kind.NarrowOop) { |
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172 regPrefix = "$s"; |
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173 } else { |
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174 regPrefix = "$d"; |
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175 } |
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176 reg = asRegister(arg); |
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177 encoding = reg.encoding(); |
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178 return new String(regPrefix + encoding); |
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179 } |
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180 |
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181 @Override |
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182 public boolean canStoreValue(RegisterCategory category, PlatformKind platformKind) { |
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183 if (!(platformKind instanceof Kind)) { |
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184 return false; |
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185 } |
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186 Kind kind = (Kind) platformKind; |
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187 if (category == CPU) { |
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188 switch (kind) { |
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189 case Boolean: |
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190 case Byte: |
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191 case Char: |
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192 case Short: |
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193 case Int: |
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194 case Long: |
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195 case Object: |
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196 case NarrowOop: |
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197 return true; |
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198 } |
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199 } else if (category == FPU) { |
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200 switch (kind) { |
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201 case Float: |
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202 case Double: |
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203 return true; |
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204 } |
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205 } |
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206 return false; |
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207 } |
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208 |
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209 @Override |
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210 public PlatformKind getLargestStorableKind(RegisterCategory category) { |
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211 if (category == CPU) { |
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212 return Kind.Long; |
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213 } else if (category == FPU) { |
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214 return Kind.Double; |
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215 } else { |
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216 return Kind.Illegal; |
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217 } |
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218 } |
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219 } |