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changeset 10898:ea308a63760b

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added unalignedMemoryAccess to Architecture
author twisti
date Fri, 26 Jul 2013 20:34:05 -0700
parents 9c4f90e48c60
children d9656f8eede0
files graal/com.oracle.graal.amd64/src/com/oracle/graal/amd64/AMD64.java graal/com.oracle.graal.api.code/src/com/oracle/graal/api/code/Architecture.java graal/com.oracle.graal.hsail/src/com/oracle/graal/hsail/HSAIL.java graal/com.oracle.graal.ptx/src/com/oracle/graal/ptx/PTX.java graal/com.oracle.graal.sparc/src/com/oracle/graal/sparc/SPARC.java
diffstat 5 files changed, 30 insertions(+), 35 deletions(-) [+]
line wrap: on
line diff
--- a/graal/com.oracle.graal.amd64/src/com/oracle/graal/amd64/AMD64.java	Fri Jul 26 14:03:07 2013 -0700
+++ b/graal/com.oracle.graal.amd64/src/com/oracle/graal/amd64/AMD64.java	Fri Jul 26 20:34:05 2013 -0700
@@ -109,23 +109,17 @@
         rip
     };
 
+    // @formatter:on
+
     private final int supportedSSEVersion;
     private final int supportedAVXVersion;
 
     public AMD64(int supportedSSEVersion, int supportedAVXVersion) {
-        super("AMD64",
-              8,
-              ByteOrder.LITTLE_ENDIAN,
-              allRegisters,
-              LOAD_STORE | STORE_STORE,
-              1,
-              r15.encoding + 1,
-              8);
+        super("AMD64", 8, ByteOrder.LITTLE_ENDIAN, true, allRegisters, LOAD_STORE | STORE_STORE, 1, r15.encoding + 1, 8);
         assert supportedSSEVersion >= 2;
         this.supportedSSEVersion = supportedSSEVersion;
         this.supportedAVXVersion = supportedAVXVersion;
     }
-    // @formatter:on
 
     public int getSupportedSSEVersion() {
         return supportedSSEVersion;
--- a/graal/com.oracle.graal.api.code/src/com/oracle/graal/api/code/Architecture.java	Fri Jul 26 14:03:07 2013 -0700
+++ b/graal/com.oracle.graal.api.code/src/com/oracle/graal/api/code/Architecture.java	Fri Jul 26 20:34:05 2013 -0700
@@ -63,6 +63,11 @@
     private final ByteOrder byteOrder;
 
     /**
+     * Whether the architecture supports unaligned memory accesses.
+     */
+    private final boolean unalignedMemoryAccess;
+
+    /**
      * Mask of the barrier constants denoting the barriers that are not required to be explicitly
      * inserted under this architecture.
      */
@@ -79,12 +84,13 @@
      */
     private final int returnAddressSize;
 
-    protected Architecture(String name, int wordSize, ByteOrder byteOrder, Register[] registers, int implicitMemoryBarriers, int nativeCallDisplacementOffset, int registerReferenceMapBitCount,
-                    int returnAddressSize) {
+    protected Architecture(String name, int wordSize, ByteOrder byteOrder, boolean unalignedMemoryAccess, Register[] registers, int implicitMemoryBarriers, int nativeCallDisplacementOffset,
+                    int registerReferenceMapBitCount, int returnAddressSize) {
         this.name = name;
         this.registers = registers;
         this.wordSize = wordSize;
         this.byteOrder = byteOrder;
+        this.unalignedMemoryAccess = unalignedMemoryAccess;
         this.implicitMemoryBarriers = implicitMemoryBarriers;
         this.machineCodeCallDisplacementOffset = nativeCallDisplacementOffset;
         this.registerReferenceMapBitCount = registerReferenceMapBitCount;
@@ -133,6 +139,13 @@
     }
 
     /**
+     * @return true if the architecture supports unaligned memory accesses.
+     */
+    public boolean supportsUnalignedMemoryAccess() {
+        return unalignedMemoryAccess;
+    }
+
+    /**
      * Gets the size of the return address pushed to the stack by a call instruction. A value of 0
      * denotes that call linkage uses registers instead.
      */
--- a/graal/com.oracle.graal.hsail/src/com/oracle/graal/hsail/HSAIL.java	Fri Jul 26 14:03:07 2013 -0700
+++ b/graal/com.oracle.graal.hsail/src/com/oracle/graal/hsail/HSAIL.java	Fri Jul 26 20:34:05 2013 -0700
@@ -337,18 +337,12 @@
         q22, q23, q24, q25, q26, q27, q28, q29, q30, q31
     };
 
+    // @formatter:on
+
     public HSAIL() {
-        super("HSAIL",
-                        8,
-                        ByteOrder.LITTLE_ENDIAN,
-                        allRegisters,
-                        LOAD_STORE | STORE_STORE,
-                        1,
-                        q31.encoding + 1,
-                        8);
+        super("HSAIL", 8, ByteOrder.LITTLE_ENDIAN, false, allRegisters, LOAD_STORE | STORE_STORE, 1, q31.encoding + 1, 8);
     }
 
-
     public static int getStackOffset(Value reg) {
         return -(((StackSlot) reg).getRawOffset());
     }
@@ -359,7 +353,6 @@
         return "[%spillseg]" + "[" + offset + "]";
     }
 
-    // @formatter:on
     public static String mapRegister(Value arg) {
         Register reg;
         int encoding = 0;
--- a/graal/com.oracle.graal.ptx/src/com/oracle/graal/ptx/PTX.java	Fri Jul 26 14:03:07 2013 -0700
+++ b/graal/com.oracle.graal.ptx/src/com/oracle/graal/ptx/PTX.java	Fri Jul 26 20:34:05 2013 -0700
@@ -108,17 +108,11 @@
         f8,  f9,  f10, f11, f12, f13, f14, f15
     };
 
+    // @formatter:on
+
     public PTX() {
-        super("PTX",
-              8,
-              ByteOrder.LITTLE_ENDIAN,
-              allRegisters,
-              LOAD_STORE | STORE_STORE,
-              0,
-              r15.encoding + 1,
-              8);
+        super("PTX", 8, ByteOrder.LITTLE_ENDIAN, false, allRegisters, LOAD_STORE | STORE_STORE, 0, r15.encoding + 1, 8);
     }
-    // @formatter:on
 
     @Override
     public boolean canStoreValue(RegisterCategory category, PlatformKind platformKind) {
--- a/graal/com.oracle.graal.sparc/src/com/oracle/graal/sparc/SPARC.java	Fri Jul 26 14:03:07 2013 -0700
+++ b/graal/com.oracle.graal.sparc/src/com/oracle/graal/sparc/SPARC.java	Fri Jul 26 20:34:05 2013 -0700
@@ -110,8 +110,8 @@
     public static final Register i6 = r30;
     public static final Register i7 = r31;
 
+    public static final Register sp = o6;
     public static final Register fp = i6;
-    public static final Register sp = o6;
 
     public static final Register[] cpuRegisters = {
         r0,  r1,  r2,  r3,  r4,  r5,  r6,  r7,
@@ -133,9 +133,9 @@
     public static final Register[] allRegisters = {
         // CPU
         r0,  r1,  r2,  r3,  r4,  r5,  r6,  r7,
-        r8,  r9, r10, r11, r12, r13, r14, r15,
-       r16, r17, r18, r19, r20, r21, r22, r23,
-       r24, r25, r26, r27, r28, r29, r30, r31,
+        r8,  r9,  r10, r11, r12, r13, r14, r15,
+        r16, r17, r18, r19, r20, r21, r22, r23,
+        r24, r25, r26, r27, r28, r29, r30, r31,
         // FPU
         f0,  f1,  f2,  f3,  f4,  f5,  f6,  f7,
     };
@@ -145,7 +145,8 @@
     public SPARC() {
         // The return address doesn't have an extra slot in the frame so we pass 0 for the return
         // address size.
-        super("SPARC", 8, ByteOrder.BIG_ENDIAN, allRegisters, LOAD_STORE | STORE_STORE, 1, r31.encoding + 1, 0);
+        // XXX think about the return address size again
+        super("SPARC", 8, ByteOrder.BIG_ENDIAN, false, allRegisters, LOAD_STORE | STORE_STORE, 1, r31.encoding + 1, 0);
     }
 
     @Override