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annotate graal/com.oracle.graal.ptx/src/com/oracle/graal/ptx/PTX.java @ 18752:1acaa69ff61b

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Truffle-DSL: refactor generator classes
author Christian Humer <christian.humer@gmail.com>
date Mon, 29 Dec 2014 23:38:16 +0100
parents edb88f5425e6
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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1 /*
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2 * Copyright (c) 2013, 2014, Oracle and/or its affiliates. All rights reserved.
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3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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4 *
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5 * This code is free software; you can redistribute it and/or modify it
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6 * under the terms of the GNU General Public License version 2 only, as
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7 * published by the Free Software Foundation.
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8 *
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9 * This code is distributed in the hope that it will be useful, but WITHOUT
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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12 * version 2 for more details (a copy is included in the LICENSE file that
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13 * accompanied this code).
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14 *
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15 * You should have received a copy of the GNU General Public License version
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16 * 2 along with this work; if not, write to the Free Software Foundation,
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17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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18 *
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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20 * or visit www.oracle.com if you need additional information or have any
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21 * questions.
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22 */
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23 package com.oracle.graal.ptx;
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24
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25 import static com.oracle.graal.api.code.MemoryBarriers.*;
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26
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27 import java.nio.*;
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28
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29 import com.oracle.graal.api.code.*;
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30 import com.oracle.graal.api.code.Register.RegisterCategory;
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31 import com.oracle.graal.api.meta.*;
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32
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33 /**
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34 * Represents the PTX architecture.
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35 */
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36 public class PTX extends Architecture {
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37
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38 public static final RegisterCategory REG = new RegisterCategory("REG");
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39 public static final RegisterCategory SREG = new RegisterCategory("SREG");
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40 public static final RegisterCategory PARAM = new RegisterCategory("PARAM");
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41
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42 // @formatter:off
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43
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44 /*
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45 * Register State Space
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46 *
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47 * Registers (.reg state space) are fast storage locations. The
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48 * number of GPU architectural registers is limited, and will vary
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49 * from platform to platform. When the limit is exceeded, register
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50 * variables will be spilled to memory, causing changes in
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51 * performance. For each architecture, there is a recommended
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52 * maximum number of registers to use (see the "CUDA Programming
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53 * Guide" for details).
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54 *
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55 * TODD: XXX
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56 *
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57 * However, PTX supports virtual registers. So, the generated PTX
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58 * code does not need to use a specified number of registers. Till
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59 * we figure out how to model a virtual register set in Graal, we
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60 * will pretend that we can use only 16 registers.
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61 */
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62
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63 public static final Register r0 = new Register(0, 0, "r0", REG);
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64 public static final Register r1 = new Register(1, 1, "r1", REG);
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65 public static final Register r2 = new Register(2, 2, "r2", REG);
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66 public static final Register r3 = new Register(3, 3, "r3", REG);
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67 public static final Register r4 = new Register(4, 4, "r4", REG);
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68 public static final Register r5 = new Register(5, 5, "r5", REG);
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69 public static final Register r6 = new Register(6, 6, "r6", REG);
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70 public static final Register r7 = new Register(7, 7, "r7", REG);
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71
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72 public static final Register r8 = new Register(8, 8, "r8", REG);
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73 public static final Register r9 = new Register(9, 9, "r9", REG);
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74 public static final Register r10 = new Register(10, 10, "r10", REG);
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75 public static final Register r11 = new Register(11, 11, "r11", REG);
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76 public static final Register r12 = new Register(12, 12, "r12", REG);
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77 public static final Register r13 = new Register(13, 13, "r13", REG);
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78 public static final Register r14 = new Register(14, 14, "r14", REG);
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79 public static final Register r15 = new Register(15, 15, "r15", REG);
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80
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81 public static final Register[] gprRegisters = {
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82 r0, r1, r2, r3, r4, r5, r6, r7,
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83 r8, r9, r10, r11, r12, r13, r14, r15
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84 };
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85
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86 /* Parameter State Space
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87 *
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88 * The parameter (.param) state space is used (1) to pass input
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89 * arguments from the host to the kernel, (2a) to declare formal
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90 * input and return parameters for device functions called from
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91 * within kernel execution, and (2b) to declare locally-scoped
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92 * byte array variables that serve as function call arguments,
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93 * typically for passing large structures by value to a function.
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94 *
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95 * TODO: XXX
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96 * The parameters are virtual symbols - just like registers. Bit,
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97 * Till we figure out how to model a virtual register set in Graal,
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98 * we will pretend that we can use only 8 parameters.
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99 */
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100
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101 public static final Register param0 = new Register(16, 16, "param0", PARAM);
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102 public static final Register param1 = new Register(17, 17, "param1", PARAM);
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103 public static final Register param2 = new Register(18, 18, "param2", PARAM);
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104 public static final Register param3 = new Register(19, 19, "param3", PARAM);
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105 public static final Register param4 = new Register(20, 20, "param4", PARAM);
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106 public static final Register param5 = new Register(21, 21, "param5", PARAM);
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107 public static final Register param6 = new Register(22, 22, "param6", PARAM);
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108 public static final Register param7 = new Register(23, 23, "param7", PARAM);
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109
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110 public static final Register[] paramRegisters = {
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111 param0, param1, param2, param3, param4, param5, param6, param7
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112 };
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113
11699
03fe11f5f186 PTX Codegen: predicate register materialization and declaration; conditional branch generation; fix register declaration.
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114 // Define a virtual register that holds return value
03fe11f5f186 PTX Codegen: predicate register materialization and declaration; conditional branch generation; fix register declaration.
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115 public static final Register retReg = new Register(24, 24, "retReg", REG);
03fe11f5f186 PTX Codegen: predicate register materialization and declaration; conditional branch generation; fix register declaration.
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parents: 11596
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116
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117 // PTX ISA Manual: Section 9:. Special Registers
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118
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119 // PTX includes a number of predefined, read-only variables, which
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bharadwaj
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120 // are visible as special registers and accessed through mov or
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bharadwaj
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121 // cvt instructions.
91e5f927af63 Initial implementation of PTXRuntime (RegisterConfig, PTX description etc); guarded with new flag UseGPU. Specify -XX:+UseGPU to exercise this new implementation.
bharadwaj
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122 // Thread identifier within a Co-operative Thread Array (CTA) - %tid
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123 public static final Register tid = new Register(100, 100, "tid", SREG);
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124 // Number of thread IDs per CTA - %ntid
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125 public static final Register ntid = new Register(101, 101, "ntid", SREG);
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bharadwaj
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126 // Lane identifier
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127 public static final Register laneid = new Register(102, 102, "laneid", SREG);
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128 // Warp identifier
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129 public static final Register warpid = new Register(103, 103, "warid", SREG);
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130 // Number of warp IDs
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131 public static final Register nwarpid = new Register(104, 104, "nwarpid", SREG);
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132 // CTA identifier
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133 public static final Register ctaid = new Register(105, 105, "ctaid", SREG);
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134 // Number of CTA IDs per grid
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135 public static final Register nctaid = new Register(106, 106, "nctaid", SREG);
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136 // Single Multiprocessor (SM) ID
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137 public static final Register smid = new Register(107, 107, "smid", SREG);
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bharadwaj
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138 // Number of SM IDs
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139 public static final Register nsmid = new Register(108, 108, "nsmid", SREG);
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bharadwaj
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140 // Grid ID
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141 public static final Register gridid = new Register(109, 109, "gridid", SREG);
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142 // 32-bit mask with bit set in position equal to thread's lane number in the warp
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143 public static final Register lanemask_eq = new Register(110, 110, "lanemask_eq", SREG);
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144 // 32-bit mask with bits set in positions less than or equal to thread's lane number in the warp
91e5f927af63 Initial implementation of PTXRuntime (RegisterConfig, PTX description etc); guarded with new flag UseGPU. Specify -XX:+UseGPU to exercise this new implementation.
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145 public static final Register lanemask_le = new Register(111, 111, "lanemask_le", SREG);
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146 // 32-bit mask with bits set in positions less than thread's lane number in the warp
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147 public static final Register lanemask_lt = new Register(112, 112, "lanemask_lt", SREG);
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148 // 32-bit mask with bits set in positions greater than or equal to thread's lane number in the warp
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149 public static final Register lanemask_ge = new Register(113, 113, "lanemask_ge", SREG);
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bharadwaj
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150 // 32-bit mask with bits set in positions greater than thread's lane number in the warp
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151 public static final Register lanemask_gt = new Register(114, 114, "lanemask_gt", SREG);
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152 // A predefined, read-only 32-bit unsigned 32-bit unsigned cycle counter
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153 public static final Register clock = new Register(114, 114, "clock", SREG);
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154 // A predefined, read-only 64-bit unsigned 32-bit unsigned cycle counter
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155 public static final Register clock64 = new Register(115, 115, "clock64", SREG);
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156 // Performance monitoring registers
91e5f927af63 Initial implementation of PTXRuntime (RegisterConfig, PTX description etc); guarded with new flag UseGPU. Specify -XX:+UseGPU to exercise this new implementation.
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157 public static final Register pm0 = new Register(116, 116, "pm0", SREG);
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158 public static final Register pm1 = new Register(117, 117, "pm1", SREG);
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159 public static final Register pm2 = new Register(118, 118, "pm2", SREG);
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160 public static final Register pm3 = new Register(119, 119, "pm3", SREG);
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161 public static final Register pm4 = new Register(120, 120, "pm4", SREG);
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162 public static final Register pm5 = new Register(121, 121, "pm5", SREG);
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163 public static final Register pm6 = new Register(122, 122, "pm6", SREG);
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164 public static final Register pm7 = new Register(123, 123, "pm7", SREG);
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165 // TODO: Add Driver-defined read-only %envreg<32>
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166 // and %globaltimer, %globaltimer_lo and %globaltimer_hi
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167
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168 public static final Register[] specialRegisters = {
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169 tid, ntid, laneid, warpid, nwarpid, ctaid,
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170 nctaid, smid, nsmid, gridid,
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171 lanemask_eq, lanemask_le, lanemask_lt, lanemask_ge, lanemask_gt,
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172 clock, clock64,
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173 pm0, pm1, pm2, pm3, pm4, pm5, pm6, pm7
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174 };
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175
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176 public static final Register[] allRegisters = {
11596
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177 // Parameter State Space
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178 param0, param1, param2, param3,
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179 param4, param5, param6, param7,
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180 // Register State Space
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181 r0, r1, r2, r3, r4, r5, r6, r7,
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182 r8, r9, r10, r11, r12, r13, r14, r15,
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183 // return register
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184 retReg,
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185 // Special Register State Space - SREG
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186 tid, ntid, laneid, warpid, nwarpid, ctaid,
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187 nctaid, smid, nsmid, gridid,
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188 lanemask_eq, lanemask_le, lanemask_lt, lanemask_ge, lanemask_gt,
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189 clock, clock64,
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190 pm0, pm1, pm2, pm3, pm4, pm5, pm6, pm7
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191 };
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192
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193 // @formatter:on
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194
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195 public PTX() {
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196 super("PTX", 8, ByteOrder.LITTLE_ENDIAN, false, allRegisters, LOAD_STORE | STORE_STORE, 0, r15.encoding + 1, 8);
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197 }
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198
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199 @Override
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200 public boolean canStoreValue(RegisterCategory category, PlatformKind lirKind) {
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201 if (!(lirKind instanceof Kind)) {
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202 return false;
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203 }
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204
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205 Kind kind = (Kind) lirKind;
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edb88f5425e6 switch to using use .equals() instead of == when comparing RegisterCaterory objects for equality
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206 if (category.equals(REG)) {
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207 switch (kind) {
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208 case Boolean:
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209 case Byte:
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210 case Char:
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211 case Short:
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212 case Int:
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213 case Long:
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214 case Object:
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215 case Float:
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216 case Double:
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217 return true;
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218 }
3ec29630cfb4 Use register categories instead of register flags.
Roland Schatz <roland.schatz@oracle.com>
parents: 7804
diff changeset
219 }
3ec29630cfb4 Use register categories instead of register flags.
Roland Schatz <roland.schatz@oracle.com>
parents: 7804
diff changeset
220
3ec29630cfb4 Use register categories instead of register flags.
Roland Schatz <roland.schatz@oracle.com>
parents: 7804
diff changeset
221 return false;
3ec29630cfb4 Use register categories instead of register flags.
Roland Schatz <roland.schatz@oracle.com>
parents: 7804
diff changeset
222 }
3ec29630cfb4 Use register categories instead of register flags.
Roland Schatz <roland.schatz@oracle.com>
parents: 7804
diff changeset
223
3ec29630cfb4 Use register categories instead of register flags.
Roland Schatz <roland.schatz@oracle.com>
parents: 7804
diff changeset
224 @Override
3ec29630cfb4 Use register categories instead of register flags.
Roland Schatz <roland.schatz@oracle.com>
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225 public PlatformKind getLargestStorableKind(RegisterCategory category) {
18253
edb88f5425e6 switch to using use .equals() instead of == when comparing RegisterCaterory objects for equality
Doug Simon <doug.simon@oracle.com>
parents: 16094
diff changeset
226 if (category.equals(REG)) {
9425
3ec29630cfb4 Use register categories instead of register flags.
Roland Schatz <roland.schatz@oracle.com>
parents: 7804
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227 return Kind.Double;
3ec29630cfb4 Use register categories instead of register flags.
Roland Schatz <roland.schatz@oracle.com>
parents: 7804
diff changeset
228 } else {
3ec29630cfb4 Use register categories instead of register flags.
Roland Schatz <roland.schatz@oracle.com>
parents: 7804
diff changeset
229 return Kind.Illegal;
3ec29630cfb4 Use register categories instead of register flags.
Roland Schatz <roland.schatz@oracle.com>
parents: 7804
diff changeset
230 }
3ec29630cfb4 Use register categories instead of register flags.
Roland Schatz <roland.schatz@oracle.com>
parents: 7804
diff changeset
231 }
11596
91e5f927af63 Initial implementation of PTXRuntime (RegisterConfig, PTX description etc); guarded with new flag UseGPU. Specify -XX:+UseGPU to exercise this new implementation.
bharadwaj
parents: 10898
diff changeset
232
7804
447f9ba1962b Experimental PTX backend. Contribution by Christian Thalinger.
Thomas Wuerthinger <thomas.wuerthinger@oracle.com>
parents:
diff changeset
233 }