Mercurial > hg > truffle
annotate src/cpu/x86/vm/c1_LIRAssembler_x86.cpp @ 4290:21400bafb3ff
Enforce that one fixed register cannot be a temporary operand multiple times with different kinds
author | Christian Wimmer <Christian.Wimmer@Oracle.com> |
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date | Tue, 17 Jan 2012 19:35:29 -0800 |
parents | f08d439fab8c |
children | 52b5d32fbfaf 069ab3f976d3 |
rev | line source |
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0 | 1 /* |
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2 * Copyright (c) 2000, 2011, Oracle and/or its affiliates. All rights reserved. |
0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
4 * | |
5 * This code is free software; you can redistribute it and/or modify it | |
6 * under the terms of the GNU General Public License version 2 only, as | |
7 * published by the Free Software Foundation. | |
8 * | |
9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 * version 2 for more details (a copy is included in the LICENSE file that | |
13 * accompanied this code). | |
14 * | |
15 * You should have received a copy of the GNU General Public License version | |
16 * 2 along with this work; if not, write to the Free Software Foundation, | |
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
18 * | |
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
0 | 22 * |
23 */ | |
24 | |
1972 | 25 #include "precompiled.hpp" |
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26 #include "asm/assembler.hpp" |
1972 | 27 #include "c1/c1_Compilation.hpp" |
28 #include "c1/c1_LIRAssembler.hpp" | |
29 #include "c1/c1_MacroAssembler.hpp" | |
30 #include "c1/c1_Runtime1.hpp" | |
31 #include "c1/c1_ValueStack.hpp" | |
32 #include "ci/ciArrayKlass.hpp" | |
33 #include "ci/ciInstance.hpp" | |
34 #include "gc_interface/collectedHeap.hpp" | |
35 #include "memory/barrierSet.hpp" | |
36 #include "memory/cardTableModRefBS.hpp" | |
37 #include "nativeInst_x86.hpp" | |
38 #include "oops/objArrayKlass.hpp" | |
39 #include "runtime/sharedRuntime.hpp" | |
0 | 40 |
41 | |
42 // These masks are used to provide 128-bit aligned bitmasks to the XMM | |
43 // instructions, to allow sign-masking or sign-bit flipping. They allow | |
44 // fast versions of NegF/NegD and AbsF/AbsD. | |
45 | |
46 // Note: 'double' and 'long long' have 32-bits alignment on x86. | |
47 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) { | |
48 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address | |
49 // of 128-bits operands for SSE instructions. | |
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50 jlong *operand = (jlong*)(((intptr_t)adr) & ((intptr_t)(~0xF))); |
0 | 51 // Store the value to a 128-bits operand. |
52 operand[0] = lo; | |
53 operand[1] = hi; | |
54 return operand; | |
55 } | |
56 | |
57 // Buffer for 128-bits masks used by SSE instructions. | |
58 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment) | |
59 | |
60 // Static initialization during VM startup. | |
61 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF)); | |
62 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF)); | |
63 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000)); | |
64 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000)); | |
65 | |
66 | |
67 | |
68 NEEDS_CLEANUP // remove this definitions ? | |
69 const Register IC_Klass = rax; // where the IC klass is cached | |
70 const Register SYNC_header = rax; // synchronization header | |
71 const Register SHIFT_count = rcx; // where count for shift operations must be | |
72 | |
73 #define __ _masm-> | |
74 | |
75 | |
76 static void select_different_registers(Register preserve, | |
77 Register extra, | |
78 Register &tmp1, | |
79 Register &tmp2) { | |
80 if (tmp1 == preserve) { | |
81 assert_different_registers(tmp1, tmp2, extra); | |
82 tmp1 = extra; | |
83 } else if (tmp2 == preserve) { | |
84 assert_different_registers(tmp1, tmp2, extra); | |
85 tmp2 = extra; | |
86 } | |
87 assert_different_registers(preserve, tmp1, tmp2); | |
88 } | |
89 | |
90 | |
91 | |
92 static void select_different_registers(Register preserve, | |
93 Register extra, | |
94 Register &tmp1, | |
95 Register &tmp2, | |
96 Register &tmp3) { | |
97 if (tmp1 == preserve) { | |
98 assert_different_registers(tmp1, tmp2, tmp3, extra); | |
99 tmp1 = extra; | |
100 } else if (tmp2 == preserve) { | |
101 assert_different_registers(tmp1, tmp2, tmp3, extra); | |
102 tmp2 = extra; | |
103 } else if (tmp3 == preserve) { | |
104 assert_different_registers(tmp1, tmp2, tmp3, extra); | |
105 tmp3 = extra; | |
106 } | |
107 assert_different_registers(preserve, tmp1, tmp2, tmp3); | |
108 } | |
109 | |
110 | |
111 | |
112 bool LIR_Assembler::is_small_constant(LIR_Opr opr) { | |
113 if (opr->is_constant()) { | |
114 LIR_Const* constant = opr->as_constant_ptr(); | |
115 switch (constant->type()) { | |
116 case T_INT: { | |
117 return true; | |
118 } | |
119 | |
120 default: | |
121 return false; | |
122 } | |
123 } | |
124 return false; | |
125 } | |
126 | |
127 | |
128 LIR_Opr LIR_Assembler::receiverOpr() { | |
304 | 129 return FrameMap::receiver_opr; |
0 | 130 } |
131 | |
132 LIR_Opr LIR_Assembler::osrBufferPointer() { | |
304 | 133 return FrameMap::as_pointer_opr(receiverOpr()->as_register()); |
0 | 134 } |
135 | |
136 //--------------fpu register translations----------------------- | |
137 | |
138 | |
139 address LIR_Assembler::float_constant(float f) { | |
140 address const_addr = __ float_constant(f); | |
141 if (const_addr == NULL) { | |
142 bailout("const section overflow"); | |
143 return __ code()->consts()->start(); | |
144 } else { | |
145 return const_addr; | |
146 } | |
147 } | |
148 | |
149 | |
150 address LIR_Assembler::double_constant(double d) { | |
151 address const_addr = __ double_constant(d); | |
152 if (const_addr == NULL) { | |
153 bailout("const section overflow"); | |
154 return __ code()->consts()->start(); | |
155 } else { | |
156 return const_addr; | |
157 } | |
158 } | |
159 | |
160 | |
161 void LIR_Assembler::set_24bit_FPU() { | |
162 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); | |
163 } | |
164 | |
165 void LIR_Assembler::reset_FPU() { | |
166 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); | |
167 } | |
168 | |
169 void LIR_Assembler::fpop() { | |
170 __ fpop(); | |
171 } | |
172 | |
173 void LIR_Assembler::fxch(int i) { | |
174 __ fxch(i); | |
175 } | |
176 | |
177 void LIR_Assembler::fld(int i) { | |
178 __ fld_s(i); | |
179 } | |
180 | |
181 void LIR_Assembler::ffree(int i) { | |
182 __ ffree(i); | |
183 } | |
184 | |
185 void LIR_Assembler::breakpoint() { | |
186 __ int3(); | |
187 } | |
188 | |
189 void LIR_Assembler::push(LIR_Opr opr) { | |
190 if (opr->is_single_cpu()) { | |
191 __ push_reg(opr->as_register()); | |
192 } else if (opr->is_double_cpu()) { | |
304 | 193 NOT_LP64(__ push_reg(opr->as_register_hi())); |
0 | 194 __ push_reg(opr->as_register_lo()); |
195 } else if (opr->is_stack()) { | |
196 __ push_addr(frame_map()->address_for_slot(opr->single_stack_ix())); | |
197 } else if (opr->is_constant()) { | |
198 LIR_Const* const_opr = opr->as_constant_ptr(); | |
199 if (const_opr->type() == T_OBJECT) { | |
200 __ push_oop(const_opr->as_jobject()); | |
201 } else if (const_opr->type() == T_INT) { | |
202 __ push_jint(const_opr->as_jint()); | |
203 } else { | |
204 ShouldNotReachHere(); | |
205 } | |
206 | |
207 } else { | |
208 ShouldNotReachHere(); | |
209 } | |
210 } | |
211 | |
212 void LIR_Assembler::pop(LIR_Opr opr) { | |
213 if (opr->is_single_cpu()) { | |
304 | 214 __ pop_reg(opr->as_register()); |
0 | 215 } else { |
216 ShouldNotReachHere(); | |
217 } | |
218 } | |
219 | |
304 | 220 bool LIR_Assembler::is_literal_address(LIR_Address* addr) { |
221 return addr->base()->is_illegal() && addr->index()->is_illegal(); | |
222 } | |
223 | |
0 | 224 //------------------------------------------- |
304 | 225 |
0 | 226 Address LIR_Assembler::as_Address(LIR_Address* addr) { |
304 | 227 return as_Address(addr, rscratch1); |
228 } | |
229 | |
230 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) { | |
0 | 231 if (addr->base()->is_illegal()) { |
232 assert(addr->index()->is_illegal(), "must be illegal too"); | |
304 | 233 AddressLiteral laddr((address)addr->disp(), relocInfo::none); |
234 if (! __ reachable(laddr)) { | |
235 __ movptr(tmp, laddr.addr()); | |
236 Address res(tmp, 0); | |
237 return res; | |
238 } else { | |
239 return __ as_Address(laddr); | |
240 } | |
0 | 241 } |
242 | |
304 | 243 Register base = addr->base()->as_pointer_register(); |
0 | 244 |
245 if (addr->index()->is_illegal()) { | |
246 return Address( base, addr->disp()); | |
304 | 247 } else if (addr->index()->is_cpu_register()) { |
248 Register index = addr->index()->as_pointer_register(); | |
0 | 249 return Address(base, index, (Address::ScaleFactor) addr->scale(), addr->disp()); |
250 } else if (addr->index()->is_constant()) { | |
304 | 251 intptr_t addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp(); |
252 assert(Assembler::is_simm32(addr_offset), "must be"); | |
0 | 253 |
254 return Address(base, addr_offset); | |
255 } else { | |
256 Unimplemented(); | |
257 return Address(); | |
258 } | |
259 } | |
260 | |
261 | |
262 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) { | |
263 Address base = as_Address(addr); | |
264 return Address(base._base, base._index, base._scale, base._disp + BytesPerWord); | |
265 } | |
266 | |
267 | |
268 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) { | |
269 return as_Address(addr); | |
270 } | |
271 | |
272 | |
273 void LIR_Assembler::osr_entry() { | |
274 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset()); | |
275 BlockBegin* osr_entry = compilation()->hir()->osr_entry(); | |
276 ValueStack* entry_state = osr_entry->state(); | |
277 int number_of_locks = entry_state->locks_size(); | |
278 | |
279 // we jump here if osr happens with the interpreter | |
280 // state set up to continue at the beginning of the | |
281 // loop that triggered osr - in particular, we have | |
282 // the following registers setup: | |
283 // | |
284 // rcx: osr buffer | |
285 // | |
286 | |
287 // build frame | |
288 ciMethod* m = compilation()->method(); | |
289 __ build_frame(initial_frame_size_in_bytes()); | |
290 | |
291 // OSR buffer is | |
292 // | |
293 // locals[nlocals-1..0] | |
294 // monitors[0..number_of_locks] | |
295 // | |
296 // locals is a direct copy of the interpreter frame so in the osr buffer | |
297 // so first slot in the local array is the last local from the interpreter | |
298 // and last slot is local[0] (receiver) from the interpreter | |
299 // | |
300 // Similarly with locks. The first lock slot in the osr buffer is the nth lock | |
301 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock | |
302 // in the interpreter frame (the method lock if a sync method) | |
303 | |
304 // Initialize monitors in the compiled activation. | |
305 // rcx: pointer to osr buffer | |
306 // | |
307 // All other registers are dead at this point and the locals will be | |
308 // copied into place by code emitted in the IR. | |
309 | |
304 | 310 Register OSR_buf = osrBufferPointer()->as_pointer_register(); |
0 | 311 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below"); |
312 int monitor_offset = BytesPerWord * method()->max_locals() + | |
1060 | 313 (2 * BytesPerWord) * (number_of_locks - 1); |
314 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in | |
315 // the OSR buffer using 2 word entries: first the lock and then | |
316 // the oop. | |
0 | 317 for (int i = 0; i < number_of_locks; i++) { |
1060 | 318 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord); |
0 | 319 #ifdef ASSERT |
320 // verify the interpreter's monitor has a non-null object | |
321 { | |
322 Label L; | |
1060 | 323 __ cmpptr(Address(OSR_buf, slot_offset + 1*BytesPerWord), (int32_t)NULL_WORD); |
0 | 324 __ jcc(Assembler::notZero, L); |
325 __ stop("locked object is NULL"); | |
326 __ bind(L); | |
327 } | |
328 #endif | |
1060 | 329 __ movptr(rbx, Address(OSR_buf, slot_offset + 0)); |
304 | 330 __ movptr(frame_map()->address_for_monitor_lock(i), rbx); |
1060 | 331 __ movptr(rbx, Address(OSR_buf, slot_offset + 1*BytesPerWord)); |
304 | 332 __ movptr(frame_map()->address_for_monitor_object(i), rbx); |
0 | 333 } |
334 } | |
335 } | |
336 | |
337 | |
338 // inline cache check; done before the frame is built. | |
339 int LIR_Assembler::check_icache() { | |
340 Register receiver = FrameMap::receiver_opr->as_register(); | |
341 Register ic_klass = IC_Klass; | |
304 | 342 const int ic_cmp_size = LP64_ONLY(10) NOT_LP64(9); |
2002 | 343 const bool do_post_padding = VerifyOops || UseCompressedOops; |
344 if (!do_post_padding) { | |
0 | 345 // insert some nops so that the verified entry point is aligned on CodeEntryAlignment |
304 | 346 while ((__ offset() + ic_cmp_size) % CodeEntryAlignment != 0) { |
0 | 347 __ nop(); |
348 } | |
349 } | |
350 int offset = __ offset(); | |
351 __ inline_cache_check(receiver, IC_Klass); | |
2002 | 352 assert(__ offset() % CodeEntryAlignment == 0 || do_post_padding, "alignment must be correct"); |
353 if (do_post_padding) { | |
0 | 354 // force alignment after the cache check. |
355 // It's been verified to be aligned if !VerifyOops | |
356 __ align(CodeEntryAlignment); | |
357 } | |
358 return offset; | |
359 } | |
360 | |
361 | |
362 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) { | |
363 jobject o = NULL; | |
364 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id); | |
365 __ movoop(reg, o); | |
366 patching_epilog(patch, lir_patch_normal, reg, info); | |
367 } | |
368 | |
369 | |
370 // This specifies the rsp decrement needed to build the frame | |
371 int LIR_Assembler::initial_frame_size_in_bytes() { | |
372 // if rounding, must let FrameMap know! | |
304 | 373 |
374 // The frame_map records size in slots (32bit word) | |
375 | |
376 // subtract two words to account for return address and link | |
377 return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word)) * VMRegImpl::stack_slot_size; | |
0 | 378 } |
379 | |
380 | |
1204 | 381 int LIR_Assembler::emit_exception_handler() { |
0 | 382 // if the last instruction is a call (typically to do a throw which |
383 // is coming at the end after block reordering) the return address | |
384 // must still point into the code area in order to avoid assertion | |
385 // failures when searching for the corresponding bci => add a nop | |
386 // (was bug 5/14/1999 - gri) | |
387 __ nop(); | |
388 | |
389 // generate code for exception handler | |
390 address handler_base = __ start_a_stub(exception_handler_size); | |
391 if (handler_base == NULL) { | |
392 // not enough space left for the handler | |
393 bailout("exception handler overflow"); | |
1204 | 394 return -1; |
0 | 395 } |
1204 | 396 |
0 | 397 int offset = code_offset(); |
398 | |
1295 | 399 // the exception oop and pc are in rax, and rdx |
0 | 400 // no other registers need to be preserved, so invalidate them |
1295 | 401 __ invalidate_registers(false, true, true, false, true, true); |
0 | 402 |
403 // check that there is really an exception | |
404 __ verify_not_null_oop(rax); | |
405 | |
1295 | 406 // search an exception handler (rax: exception oop, rdx: throwing pc) |
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407 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id))); |
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408 __ should_not_reach_here(); |
0 | 409 assert(code_offset() - offset <= exception_handler_size, "overflow"); |
410 __ end_a_stub(); | |
1204 | 411 |
412 return offset; | |
0 | 413 } |
414 | |
1204 | 415 |
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416 // Emit the code to remove the frame from the stack in the exception |
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417 // unwind path. |
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418 int LIR_Assembler::emit_unwind_handler() { |
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419 #ifndef PRODUCT |
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420 if (CommentedAssembly) { |
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421 _masm->block_comment("Unwind handler"); |
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422 } |
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423 #endif |
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424 |
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425 int offset = code_offset(); |
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426 |
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427 // Fetch the exception from TLS and clear out exception related thread state |
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428 __ get_thread(rsi); |
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429 __ movptr(rax, Address(rsi, JavaThread::exception_oop_offset())); |
3960 | 430 __ movptr(Address(rsi, JavaThread::exception_oop_offset()), (intptr_t)NULL_WORD); |
431 __ movptr(Address(rsi, JavaThread::exception_pc_offset()), (intptr_t)NULL_WORD); | |
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432 |
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433 __ bind(_unwind_handler_entry); |
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434 __ verify_not_null_oop(rax); |
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435 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) { |
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436 __ mov(rsi, rax); // Preserve the exception |
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437 } |
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438 |
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439 // Preform needed unlocking |
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440 MonitorExitStub* stub = NULL; |
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441 if (method()->is_synchronized()) { |
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442 monitor_address(0, FrameMap::rax_opr); |
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443 stub = new MonitorExitStub(FrameMap::rax_opr, true, 0); |
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444 __ unlock_object(rdi, rbx, rax, *stub->entry()); |
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445 __ bind(*stub->continuation()); |
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446 } |
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447 |
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448 if (compilation()->env()->dtrace_method_probes()) { |
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449 __ get_thread(rax); |
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450 __ movptr(Address(rsp, 0), rax); |
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451 __ movoop(Address(rsp, sizeof(void*)), method()->constant_encoding()); |
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452 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit))); |
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453 } |
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454 |
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455 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) { |
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456 __ mov(rax, rsi); // Restore the exception |
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457 } |
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458 |
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459 // remove the activation and dispatch to the unwind handler |
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460 __ remove_frame(initial_frame_size_in_bytes()); |
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461 __ jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id))); |
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462 |
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463 // Emit the slow path assembly |
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464 if (stub != NULL) { |
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465 stub->emit_code(this); |
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466 } |
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467 |
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468 return offset; |
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469 } |
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470 |
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471 |
1204 | 472 int LIR_Assembler::emit_deopt_handler() { |
0 | 473 // if the last instruction is a call (typically to do a throw which |
474 // is coming at the end after block reordering) the return address | |
475 // must still point into the code area in order to avoid assertion | |
476 // failures when searching for the corresponding bci => add a nop | |
477 // (was bug 5/14/1999 - gri) | |
478 __ nop(); | |
479 | |
480 // generate code for exception handler | |
481 address handler_base = __ start_a_stub(deopt_handler_size); | |
482 if (handler_base == NULL) { | |
483 // not enough space left for the handler | |
484 bailout("deopt handler overflow"); | |
1204 | 485 return -1; |
0 | 486 } |
1204 | 487 |
0 | 488 int offset = code_offset(); |
489 InternalAddress here(__ pc()); | |
1295 | 490 |
0 | 491 __ pushptr(here.addr()); |
492 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack())); | |
1295 | 493 |
0 | 494 assert(code_offset() - offset <= deopt_handler_size, "overflow"); |
495 __ end_a_stub(); | |
496 | |
1204 | 497 return offset; |
0 | 498 } |
499 | |
500 | |
501 // This is the fast version of java.lang.String.compare; it has not | |
502 // OSR-entry and therefore, we generate a slow version for OSR's | |
503 void LIR_Assembler::emit_string_compare(LIR_Opr arg0, LIR_Opr arg1, LIR_Opr dst, CodeEmitInfo* info) { | |
304 | 504 __ movptr (rbx, rcx); // receiver is in rcx |
505 __ movptr (rax, arg1->as_register()); | |
0 | 506 |
507 // Get addresses of first characters from both Strings | |
2002 | 508 __ load_heap_oop(rsi, Address(rax, java_lang_String::value_offset_in_bytes())); |
509 __ movptr (rcx, Address(rax, java_lang_String::offset_offset_in_bytes())); | |
510 __ lea (rsi, Address(rsi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR))); | |
0 | 511 |
512 | |
513 // rbx, may be NULL | |
514 add_debug_info_for_null_check_here(info); | |
2002 | 515 __ load_heap_oop(rdi, Address(rbx, java_lang_String::value_offset_in_bytes())); |
516 __ movptr (rcx, Address(rbx, java_lang_String::offset_offset_in_bytes())); | |
517 __ lea (rdi, Address(rdi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR))); | |
0 | 518 |
519 // compute minimum length (in rax) and difference of lengths (on top of stack) | |
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520 __ movl (rbx, Address(rbx, java_lang_String::count_offset_in_bytes())); |
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521 __ movl (rax, Address(rax, java_lang_String::count_offset_in_bytes())); |
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522 __ mov (rcx, rbx); |
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523 __ subptr(rbx, rax); // subtract lengths |
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524 __ push (rbx); // result |
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525 __ cmov (Assembler::lessEqual, rax, rcx); |
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526 |
0 | 527 // is minimum length 0? |
528 Label noLoop, haveResult; | |
304 | 529 __ testptr (rax, rax); |
0 | 530 __ jcc (Assembler::zero, noLoop); |
531 | |
532 // compare first characters | |
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533 __ load_unsigned_short(rcx, Address(rdi, 0)); |
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534 __ load_unsigned_short(rbx, Address(rsi, 0)); |
0 | 535 __ subl(rcx, rbx); |
536 __ jcc(Assembler::notZero, haveResult); | |
537 // starting loop | |
538 __ decrement(rax); // we already tested index: skip one | |
539 __ jcc(Assembler::zero, noLoop); | |
540 | |
541 // set rsi.edi to the end of the arrays (arrays have same length) | |
542 // negate the index | |
543 | |
304 | 544 __ lea(rsi, Address(rsi, rax, Address::times_2, type2aelembytes(T_CHAR))); |
545 __ lea(rdi, Address(rdi, rax, Address::times_2, type2aelembytes(T_CHAR))); | |
546 __ negptr(rax); | |
0 | 547 |
548 // compare the strings in a loop | |
549 | |
550 Label loop; | |
551 __ align(wordSize); | |
552 __ bind(loop); | |
622
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553 __ load_unsigned_short(rcx, Address(rdi, rax, Address::times_2, 0)); |
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554 __ load_unsigned_short(rbx, Address(rsi, rax, Address::times_2, 0)); |
0 | 555 __ subl(rcx, rbx); |
556 __ jcc(Assembler::notZero, haveResult); | |
557 __ increment(rax); | |
558 __ jcc(Assembler::notZero, loop); | |
559 | |
560 // strings are equal up to min length | |
561 | |
562 __ bind(noLoop); | |
304 | 563 __ pop(rax); |
0 | 564 return_op(LIR_OprFact::illegalOpr); |
565 | |
566 __ bind(haveResult); | |
567 // leave instruction is going to discard the TOS value | |
304 | 568 __ mov (rax, rcx); // result of call is in rax, |
0 | 569 } |
570 | |
571 | |
572 void LIR_Assembler::return_op(LIR_Opr result) { | |
573 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == rax, "word returns are in rax,"); | |
574 if (!result->is_illegal() && result->is_float_kind() && !result->is_xmm_register()) { | |
575 assert(result->fpu() == 0, "result must already be on TOS"); | |
576 } | |
577 | |
578 // Pop the stack before the safepoint code | |
1295 | 579 __ remove_frame(initial_frame_size_in_bytes()); |
0 | 580 |
581 bool result_is_oop = result->is_valid() ? result->is_oop() : false; | |
582 | |
583 // Note: we do not need to round double result; float result has the right precision | |
584 // the poll sets the condition code, but no data registers | |
585 AddressLiteral polling_page(os::get_polling_page() + (SafepointPollOffset % os::vm_page_size()), | |
586 relocInfo::poll_return_type); | |
304 | 587 |
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588 if (Assembler::is_polling_page_far()) { |
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589 __ lea(rscratch1, polling_page); |
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590 __ relocate(relocInfo::poll_return_type); |
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591 __ testl(rax, Address(rscratch1, 0)); |
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592 } else { |
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593 __ testl(rax, polling_page); |
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594 } |
0 | 595 __ ret(0); |
596 } | |
597 | |
598 | |
599 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) { | |
600 AddressLiteral polling_page(os::get_polling_page() + (SafepointPollOffset % os::vm_page_size()), | |
601 relocInfo::poll_type); | |
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602 guarantee(info != NULL, "Shouldn't be NULL"); |
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603 int offset = __ offset(); |
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604 if (Assembler::is_polling_page_far()) { |
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605 __ lea(rscratch1, polling_page); |
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606 offset = __ offset(); |
0 | 607 add_debug_info_for_branch(info); |
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608 __ testl(rax, Address(rscratch1, 0)); |
0 | 609 } else { |
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610 add_debug_info_for_branch(info); |
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611 __ testl(rax, polling_page); |
0 | 612 } |
613 return offset; | |
614 } | |
615 | |
616 | |
617 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) { | |
304 | 618 if (from_reg != to_reg) __ mov(to_reg, from_reg); |
0 | 619 } |
620 | |
621 void LIR_Assembler::swap_reg(Register a, Register b) { | |
304 | 622 __ xchgptr(a, b); |
0 | 623 } |
624 | |
625 | |
626 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) { | |
627 assert(src->is_constant(), "should not call otherwise"); | |
628 assert(dest->is_register(), "should not call otherwise"); | |
629 LIR_Const* c = src->as_constant_ptr(); | |
630 | |
631 switch (c->type()) { | |
2002 | 632 case T_INT: { |
633 assert(patch_code == lir_patch_none, "no patching handled here"); | |
634 __ movl(dest->as_register(), c->as_jint()); | |
635 break; | |
636 } | |
637 | |
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638 case T_ADDRESS: { |
0 | 639 assert(patch_code == lir_patch_none, "no patching handled here"); |
2002 | 640 __ movptr(dest->as_register(), c->as_jint()); |
0 | 641 break; |
642 } | |
643 | |
644 case T_LONG: { | |
645 assert(patch_code == lir_patch_none, "no patching handled here"); | |
304 | 646 #ifdef _LP64 |
647 __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong()); | |
648 #else | |
649 __ movptr(dest->as_register_lo(), c->as_jint_lo()); | |
650 __ movptr(dest->as_register_hi(), c->as_jint_hi()); | |
651 #endif // _LP64 | |
0 | 652 break; |
653 } | |
654 | |
655 case T_OBJECT: { | |
656 if (patch_code != lir_patch_none) { | |
657 jobject2reg_with_patching(dest->as_register(), info); | |
658 } else { | |
659 __ movoop(dest->as_register(), c->as_jobject()); | |
660 } | |
661 break; | |
662 } | |
663 | |
664 case T_FLOAT: { | |
665 if (dest->is_single_xmm()) { | |
666 if (c->is_zero_float()) { | |
667 __ xorps(dest->as_xmm_float_reg(), dest->as_xmm_float_reg()); | |
668 } else { | |
669 __ movflt(dest->as_xmm_float_reg(), | |
670 InternalAddress(float_constant(c->as_jfloat()))); | |
671 } | |
672 } else { | |
673 assert(dest->is_single_fpu(), "must be"); | |
674 assert(dest->fpu_regnr() == 0, "dest must be TOS"); | |
675 if (c->is_zero_float()) { | |
676 __ fldz(); | |
677 } else if (c->is_one_float()) { | |
678 __ fld1(); | |
679 } else { | |
680 __ fld_s (InternalAddress(float_constant(c->as_jfloat()))); | |
681 } | |
682 } | |
683 break; | |
684 } | |
685 | |
686 case T_DOUBLE: { | |
687 if (dest->is_double_xmm()) { | |
688 if (c->is_zero_double()) { | |
689 __ xorpd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg()); | |
690 } else { | |
691 __ movdbl(dest->as_xmm_double_reg(), | |
692 InternalAddress(double_constant(c->as_jdouble()))); | |
693 } | |
694 } else { | |
695 assert(dest->is_double_fpu(), "must be"); | |
696 assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); | |
697 if (c->is_zero_double()) { | |
698 __ fldz(); | |
699 } else if (c->is_one_double()) { | |
700 __ fld1(); | |
701 } else { | |
702 __ fld_d (InternalAddress(double_constant(c->as_jdouble()))); | |
703 } | |
704 } | |
705 break; | |
706 } | |
707 | |
708 default: | |
709 ShouldNotReachHere(); | |
710 } | |
711 } | |
712 | |
713 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) { | |
714 assert(src->is_constant(), "should not call otherwise"); | |
715 assert(dest->is_stack(), "should not call otherwise"); | |
716 LIR_Const* c = src->as_constant_ptr(); | |
717 | |
718 switch (c->type()) { | |
719 case T_INT: // fall through | |
720 case T_FLOAT: | |
2002 | 721 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits()); |
722 break; | |
723 | |
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724 case T_ADDRESS: |
2002 | 725 __ movptr(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits()); |
0 | 726 break; |
727 | |
728 case T_OBJECT: | |
729 __ movoop(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jobject()); | |
730 break; | |
731 | |
732 case T_LONG: // fall through | |
733 case T_DOUBLE: | |
304 | 734 #ifdef _LP64 |
735 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), | |
736 lo_word_offset_in_bytes), (intptr_t)c->as_jlong_bits()); | |
737 #else | |
738 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), | |
739 lo_word_offset_in_bytes), c->as_jint_lo_bits()); | |
740 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), | |
741 hi_word_offset_in_bytes), c->as_jint_hi_bits()); | |
742 #endif // _LP64 | |
0 | 743 break; |
744 | |
745 default: | |
746 ShouldNotReachHere(); | |
747 } | |
748 } | |
749 | |
2002 | 750 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) { |
0 | 751 assert(src->is_constant(), "should not call otherwise"); |
752 assert(dest->is_address(), "should not call otherwise"); | |
753 LIR_Const* c = src->as_constant_ptr(); | |
754 LIR_Address* addr = dest->as_address_ptr(); | |
755 | |
304 | 756 int null_check_here = code_offset(); |
0 | 757 switch (type) { |
758 case T_INT: // fall through | |
759 case T_FLOAT: | |
2002 | 760 __ movl(as_Address(addr), c->as_jint_bits()); |
761 break; | |
762 | |
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763 case T_ADDRESS: |
2002 | 764 __ movptr(as_Address(addr), c->as_jint_bits()); |
0 | 765 break; |
766 | |
767 case T_OBJECT: // fall through | |
768 case T_ARRAY: | |
769 if (c->as_jobject() == NULL) { | |
2002 | 770 if (UseCompressedOops && !wide) { |
771 __ movl(as_Address(addr), (int32_t)NULL_WORD); | |
772 } else { | |
773 __ movptr(as_Address(addr), NULL_WORD); | |
774 } | |
0 | 775 } else { |
304 | 776 if (is_literal_address(addr)) { |
777 ShouldNotReachHere(); | |
778 __ movoop(as_Address(addr, noreg), c->as_jobject()); | |
779 } else { | |
1060 | 780 #ifdef _LP64 |
781 __ movoop(rscratch1, c->as_jobject()); | |
2002 | 782 if (UseCompressedOops && !wide) { |
783 __ encode_heap_oop(rscratch1); | |
784 null_check_here = code_offset(); | |
785 __ movl(as_Address_lo(addr), rscratch1); | |
786 } else { | |
787 null_check_here = code_offset(); | |
788 __ movptr(as_Address_lo(addr), rscratch1); | |
789 } | |
1060 | 790 #else |
304 | 791 __ movoop(as_Address(addr), c->as_jobject()); |
1060 | 792 #endif |
304 | 793 } |
0 | 794 } |
795 break; | |
796 | |
797 case T_LONG: // fall through | |
798 case T_DOUBLE: | |
304 | 799 #ifdef _LP64 |
800 if (is_literal_address(addr)) { | |
801 ShouldNotReachHere(); | |
802 __ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits()); | |
803 } else { | |
804 __ movptr(r10, (intptr_t)c->as_jlong_bits()); | |
805 null_check_here = code_offset(); | |
806 __ movptr(as_Address_lo(addr), r10); | |
807 } | |
808 #else | |
809 // Always reachable in 32bit so this doesn't produce useless move literal | |
810 __ movptr(as_Address_hi(addr), c->as_jint_hi_bits()); | |
811 __ movptr(as_Address_lo(addr), c->as_jint_lo_bits()); | |
812 #endif // _LP64 | |
0 | 813 break; |
814 | |
815 case T_BOOLEAN: // fall through | |
816 case T_BYTE: | |
817 __ movb(as_Address(addr), c->as_jint() & 0xFF); | |
818 break; | |
819 | |
820 case T_CHAR: // fall through | |
821 case T_SHORT: | |
822 __ movw(as_Address(addr), c->as_jint() & 0xFFFF); | |
823 break; | |
824 | |
825 default: | |
826 ShouldNotReachHere(); | |
827 }; | |
304 | 828 |
829 if (info != NULL) { | |
830 add_debug_info_for_null_check(null_check_here, info); | |
831 } | |
0 | 832 } |
833 | |
834 | |
835 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) { | |
836 assert(src->is_register(), "should not call otherwise"); | |
837 assert(dest->is_register(), "should not call otherwise"); | |
838 | |
839 // move between cpu-registers | |
840 if (dest->is_single_cpu()) { | |
304 | 841 #ifdef _LP64 |
842 if (src->type() == T_LONG) { | |
843 // Can do LONG -> OBJECT | |
844 move_regs(src->as_register_lo(), dest->as_register()); | |
845 return; | |
846 } | |
847 #endif | |
0 | 848 assert(src->is_single_cpu(), "must match"); |
849 if (src->type() == T_OBJECT) { | |
850 __ verify_oop(src->as_register()); | |
851 } | |
852 move_regs(src->as_register(), dest->as_register()); | |
853 | |
854 } else if (dest->is_double_cpu()) { | |
304 | 855 #ifdef _LP64 |
856 if (src->type() == T_OBJECT || src->type() == T_ARRAY) { | |
857 // Surprising to me but we can see move of a long to t_object | |
858 __ verify_oop(src->as_register()); | |
859 move_regs(src->as_register(), dest->as_register_lo()); | |
860 return; | |
861 } | |
862 #endif | |
0 | 863 assert(src->is_double_cpu(), "must match"); |
864 Register f_lo = src->as_register_lo(); | |
865 Register f_hi = src->as_register_hi(); | |
866 Register t_lo = dest->as_register_lo(); | |
867 Register t_hi = dest->as_register_hi(); | |
304 | 868 #ifdef _LP64 |
869 assert(f_hi == f_lo, "must be same"); | |
870 assert(t_hi == t_lo, "must be same"); | |
871 move_regs(f_lo, t_lo); | |
872 #else | |
0 | 873 assert(f_lo != f_hi && t_lo != t_hi, "invalid register allocation"); |
874 | |
304 | 875 |
0 | 876 if (f_lo == t_hi && f_hi == t_lo) { |
877 swap_reg(f_lo, f_hi); | |
878 } else if (f_hi == t_lo) { | |
879 assert(f_lo != t_hi, "overwriting register"); | |
880 move_regs(f_hi, t_hi); | |
881 move_regs(f_lo, t_lo); | |
882 } else { | |
883 assert(f_hi != t_lo, "overwriting register"); | |
884 move_regs(f_lo, t_lo); | |
885 move_regs(f_hi, t_hi); | |
886 } | |
304 | 887 #endif // LP64 |
0 | 888 |
889 // special moves from fpu-register to xmm-register | |
890 // necessary for method results | |
891 } else if (src->is_single_xmm() && !dest->is_single_xmm()) { | |
892 __ movflt(Address(rsp, 0), src->as_xmm_float_reg()); | |
893 __ fld_s(Address(rsp, 0)); | |
894 } else if (src->is_double_xmm() && !dest->is_double_xmm()) { | |
895 __ movdbl(Address(rsp, 0), src->as_xmm_double_reg()); | |
896 __ fld_d(Address(rsp, 0)); | |
897 } else if (dest->is_single_xmm() && !src->is_single_xmm()) { | |
898 __ fstp_s(Address(rsp, 0)); | |
899 __ movflt(dest->as_xmm_float_reg(), Address(rsp, 0)); | |
900 } else if (dest->is_double_xmm() && !src->is_double_xmm()) { | |
901 __ fstp_d(Address(rsp, 0)); | |
902 __ movdbl(dest->as_xmm_double_reg(), Address(rsp, 0)); | |
903 | |
904 // move between xmm-registers | |
905 } else if (dest->is_single_xmm()) { | |
906 assert(src->is_single_xmm(), "must match"); | |
907 __ movflt(dest->as_xmm_float_reg(), src->as_xmm_float_reg()); | |
908 } else if (dest->is_double_xmm()) { | |
909 assert(src->is_double_xmm(), "must match"); | |
910 __ movdbl(dest->as_xmm_double_reg(), src->as_xmm_double_reg()); | |
911 | |
912 // move between fpu-registers (no instruction necessary because of fpu-stack) | |
913 } else if (dest->is_single_fpu() || dest->is_double_fpu()) { | |
914 assert(src->is_single_fpu() || src->is_double_fpu(), "must match"); | |
915 assert(src->fpu() == dest->fpu(), "currently should be nothing to do"); | |
916 } else { | |
917 ShouldNotReachHere(); | |
918 } | |
919 } | |
920 | |
921 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) { | |
922 assert(src->is_register(), "should not call otherwise"); | |
923 assert(dest->is_stack(), "should not call otherwise"); | |
924 | |
925 if (src->is_single_cpu()) { | |
926 Address dst = frame_map()->address_for_slot(dest->single_stack_ix()); | |
927 if (type == T_OBJECT || type == T_ARRAY) { | |
928 __ verify_oop(src->as_register()); | |
304 | 929 __ movptr (dst, src->as_register()); |
930 } else { | |
931 __ movl (dst, src->as_register()); | |
0 | 932 } |
933 | |
934 } else if (src->is_double_cpu()) { | |
935 Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes); | |
936 Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes); | |
304 | 937 __ movptr (dstLO, src->as_register_lo()); |
938 NOT_LP64(__ movptr (dstHI, src->as_register_hi())); | |
0 | 939 |
940 } else if (src->is_single_xmm()) { | |
941 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix()); | |
942 __ movflt(dst_addr, src->as_xmm_float_reg()); | |
943 | |
944 } else if (src->is_double_xmm()) { | |
945 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix()); | |
946 __ movdbl(dst_addr, src->as_xmm_double_reg()); | |
947 | |
948 } else if (src->is_single_fpu()) { | |
949 assert(src->fpu_regnr() == 0, "argument must be on TOS"); | |
950 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix()); | |
951 if (pop_fpu_stack) __ fstp_s (dst_addr); | |
952 else __ fst_s (dst_addr); | |
953 | |
954 } else if (src->is_double_fpu()) { | |
955 assert(src->fpu_regnrLo() == 0, "argument must be on TOS"); | |
956 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix()); | |
957 if (pop_fpu_stack) __ fstp_d (dst_addr); | |
958 else __ fst_d (dst_addr); | |
959 | |
960 } else { | |
961 ShouldNotReachHere(); | |
962 } | |
963 } | |
964 | |
965 | |
2002 | 966 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide, bool /* unaligned */) { |
0 | 967 LIR_Address* to_addr = dest->as_address_ptr(); |
968 PatchingStub* patch = NULL; | |
2002 | 969 Register compressed_src = rscratch1; |
0 | 970 |
971 if (type == T_ARRAY || type == T_OBJECT) { | |
972 __ verify_oop(src->as_register()); | |
2002 | 973 #ifdef _LP64 |
974 if (UseCompressedOops && !wide) { | |
975 __ movptr(compressed_src, src->as_register()); | |
976 __ encode_heap_oop(compressed_src); | |
977 } | |
978 #endif | |
0 | 979 } |
2002 | 980 |
0 | 981 if (patch_code != lir_patch_none) { |
982 patch = new PatchingStub(_masm, PatchingStub::access_field_id); | |
304 | 983 Address toa = as_Address(to_addr); |
984 assert(toa.disp() != 0, "must have"); | |
0 | 985 } |
2002 | 986 |
987 int null_check_here = code_offset(); | |
0 | 988 switch (type) { |
989 case T_FLOAT: { | |
990 if (src->is_single_xmm()) { | |
991 __ movflt(as_Address(to_addr), src->as_xmm_float_reg()); | |
992 } else { | |
993 assert(src->is_single_fpu(), "must be"); | |
994 assert(src->fpu_regnr() == 0, "argument must be on TOS"); | |
995 if (pop_fpu_stack) __ fstp_s(as_Address(to_addr)); | |
996 else __ fst_s (as_Address(to_addr)); | |
997 } | |
998 break; | |
999 } | |
1000 | |
1001 case T_DOUBLE: { | |
1002 if (src->is_double_xmm()) { | |
1003 __ movdbl(as_Address(to_addr), src->as_xmm_double_reg()); | |
1004 } else { | |
1005 assert(src->is_double_fpu(), "must be"); | |
1006 assert(src->fpu_regnrLo() == 0, "argument must be on TOS"); | |
1007 if (pop_fpu_stack) __ fstp_d(as_Address(to_addr)); | |
1008 else __ fst_d (as_Address(to_addr)); | |
1009 } | |
1010 break; | |
1011 } | |
1012 | |
1013 case T_ARRAY: // fall through | |
1014 case T_OBJECT: // fall through | |
2002 | 1015 if (UseCompressedOops && !wide) { |
1016 __ movl(as_Address(to_addr), compressed_src); | |
1017 } else { | |
1018 __ movptr(as_Address(to_addr), src->as_register()); | |
1019 } | |
1020 break; | |
1021 case T_ADDRESS: | |
304 | 1022 __ movptr(as_Address(to_addr), src->as_register()); |
1023 break; | |
0 | 1024 case T_INT: |
1025 __ movl(as_Address(to_addr), src->as_register()); | |
1026 break; | |
1027 | |
1028 case T_LONG: { | |
1029 Register from_lo = src->as_register_lo(); | |
1030 Register from_hi = src->as_register_hi(); | |
304 | 1031 #ifdef _LP64 |
1032 __ movptr(as_Address_lo(to_addr), from_lo); | |
1033 #else | |
0 | 1034 Register base = to_addr->base()->as_register(); |
1035 Register index = noreg; | |
1036 if (to_addr->index()->is_register()) { | |
1037 index = to_addr->index()->as_register(); | |
1038 } | |
1039 if (base == from_lo || index == from_lo) { | |
1040 assert(base != from_hi, "can't be"); | |
1041 assert(index == noreg || (index != base && index != from_hi), "can't handle this"); | |
1042 __ movl(as_Address_hi(to_addr), from_hi); | |
1043 if (patch != NULL) { | |
1044 patching_epilog(patch, lir_patch_high, base, info); | |
1045 patch = new PatchingStub(_masm, PatchingStub::access_field_id); | |
1046 patch_code = lir_patch_low; | |
1047 } | |
1048 __ movl(as_Address_lo(to_addr), from_lo); | |
1049 } else { | |
1050 assert(index == noreg || (index != base && index != from_lo), "can't handle this"); | |
1051 __ movl(as_Address_lo(to_addr), from_lo); | |
1052 if (patch != NULL) { | |
1053 patching_epilog(patch, lir_patch_low, base, info); | |
1054 patch = new PatchingStub(_masm, PatchingStub::access_field_id); | |
1055 patch_code = lir_patch_high; | |
1056 } | |
1057 __ movl(as_Address_hi(to_addr), from_hi); | |
1058 } | |
304 | 1059 #endif // _LP64 |
0 | 1060 break; |
1061 } | |
1062 | |
1063 case T_BYTE: // fall through | |
1064 case T_BOOLEAN: { | |
1065 Register src_reg = src->as_register(); | |
1066 Address dst_addr = as_Address(to_addr); | |
1067 assert(VM_Version::is_P6() || src_reg->has_byte_register(), "must use byte registers if not P6"); | |
1068 __ movb(dst_addr, src_reg); | |
1069 break; | |
1070 } | |
1071 | |
1072 case T_CHAR: // fall through | |
1073 case T_SHORT: | |
1074 __ movw(as_Address(to_addr), src->as_register()); | |
1075 break; | |
1076 | |
1077 default: | |
1078 ShouldNotReachHere(); | |
1079 } | |
2002 | 1080 if (info != NULL) { |
1081 add_debug_info_for_null_check(null_check_here, info); | |
1082 } | |
0 | 1083 |
1084 if (patch_code != lir_patch_none) { | |
1085 patching_epilog(patch, patch_code, to_addr->base()->as_register(), info); | |
1086 } | |
1087 } | |
1088 | |
1089 | |
1090 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) { | |
1091 assert(src->is_stack(), "should not call otherwise"); | |
1092 assert(dest->is_register(), "should not call otherwise"); | |
1093 | |
1094 if (dest->is_single_cpu()) { | |
1095 if (type == T_ARRAY || type == T_OBJECT) { | |
304 | 1096 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix())); |
0 | 1097 __ verify_oop(dest->as_register()); |
304 | 1098 } else { |
1099 __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix())); | |
0 | 1100 } |
1101 | |
1102 } else if (dest->is_double_cpu()) { | |
1103 Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes); | |
1104 Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes); | |
304 | 1105 __ movptr(dest->as_register_lo(), src_addr_LO); |
1106 NOT_LP64(__ movptr(dest->as_register_hi(), src_addr_HI)); | |
0 | 1107 |
1108 } else if (dest->is_single_xmm()) { | |
1109 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix()); | |
1110 __ movflt(dest->as_xmm_float_reg(), src_addr); | |
1111 | |
1112 } else if (dest->is_double_xmm()) { | |
1113 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix()); | |
1114 __ movdbl(dest->as_xmm_double_reg(), src_addr); | |
1115 | |
1116 } else if (dest->is_single_fpu()) { | |
1117 assert(dest->fpu_regnr() == 0, "dest must be TOS"); | |
1118 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix()); | |
1119 __ fld_s(src_addr); | |
1120 | |
1121 } else if (dest->is_double_fpu()) { | |
1122 assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); | |
1123 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix()); | |
1124 __ fld_d(src_addr); | |
1125 | |
1126 } else { | |
1127 ShouldNotReachHere(); | |
1128 } | |
1129 } | |
1130 | |
1131 | |
1132 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) { | |
1133 if (src->is_single_stack()) { | |
304 | 1134 if (type == T_OBJECT || type == T_ARRAY) { |
1135 __ pushptr(frame_map()->address_for_slot(src ->single_stack_ix())); | |
1136 __ popptr (frame_map()->address_for_slot(dest->single_stack_ix())); | |
1137 } else { | |
1060 | 1138 #ifndef _LP64 |
304 | 1139 __ pushl(frame_map()->address_for_slot(src ->single_stack_ix())); |
1140 __ popl (frame_map()->address_for_slot(dest->single_stack_ix())); | |
1060 | 1141 #else |
1142 //no pushl on 64bits | |
1143 __ movl(rscratch1, frame_map()->address_for_slot(src ->single_stack_ix())); | |
1144 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), rscratch1); | |
1145 #endif | |
304 | 1146 } |
0 | 1147 |
1148 } else if (src->is_double_stack()) { | |
304 | 1149 #ifdef _LP64 |
1150 __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix())); | |
1151 __ popptr (frame_map()->address_for_slot(dest->double_stack_ix())); | |
1152 #else | |
0 | 1153 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 0)); |
304 | 1154 // push and pop the part at src + wordSize, adding wordSize for the previous push |
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1155 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 2 * wordSize)); |
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1156 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 2 * wordSize)); |
0 | 1157 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 0)); |
304 | 1158 #endif // _LP64 |
0 | 1159 |
1160 } else { | |
1161 ShouldNotReachHere(); | |
1162 } | |
1163 } | |
1164 | |
1165 | |
2002 | 1166 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool /* unaligned */) { |
0 | 1167 assert(src->is_address(), "should not call otherwise"); |
1168 assert(dest->is_register(), "should not call otherwise"); | |
1169 | |
1170 LIR_Address* addr = src->as_address_ptr(); | |
1171 Address from_addr = as_Address(addr); | |
1172 | |
1173 switch (type) { | |
1174 case T_BOOLEAN: // fall through | |
1175 case T_BYTE: // fall through | |
1176 case T_CHAR: // fall through | |
1177 case T_SHORT: | |
1178 if (!VM_Version::is_P6() && !from_addr.uses(dest->as_register())) { | |
1179 // on pre P6 processors we may get partial register stalls | |
1180 // so blow away the value of to_rinfo before loading a | |
1181 // partial word into it. Do it here so that it precedes | |
1182 // the potential patch point below. | |
304 | 1183 __ xorptr(dest->as_register(), dest->as_register()); |
0 | 1184 } |
1185 break; | |
1186 } | |
1187 | |
1188 PatchingStub* patch = NULL; | |
1189 if (patch_code != lir_patch_none) { | |
1190 patch = new PatchingStub(_masm, PatchingStub::access_field_id); | |
304 | 1191 assert(from_addr.disp() != 0, "must have"); |
0 | 1192 } |
1193 if (info != NULL) { | |
1194 add_debug_info_for_null_check_here(info); | |
1195 } | |
1196 | |
1197 switch (type) { | |
1198 case T_FLOAT: { | |
1199 if (dest->is_single_xmm()) { | |
1200 __ movflt(dest->as_xmm_float_reg(), from_addr); | |
1201 } else { | |
1202 assert(dest->is_single_fpu(), "must be"); | |
1203 assert(dest->fpu_regnr() == 0, "dest must be TOS"); | |
1204 __ fld_s(from_addr); | |
1205 } | |
1206 break; | |
1207 } | |
1208 | |
1209 case T_DOUBLE: { | |
1210 if (dest->is_double_xmm()) { | |
1211 __ movdbl(dest->as_xmm_double_reg(), from_addr); | |
1212 } else { | |
1213 assert(dest->is_double_fpu(), "must be"); | |
1214 assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); | |
1215 __ fld_d(from_addr); | |
1216 } | |
1217 break; | |
1218 } | |
1219 | |
1220 case T_OBJECT: // fall through | |
1221 case T_ARRAY: // fall through | |
2002 | 1222 if (UseCompressedOops && !wide) { |
1223 __ movl(dest->as_register(), from_addr); | |
1224 } else { | |
1225 __ movptr(dest->as_register(), from_addr); | |
1226 } | |
1227 break; | |
1228 | |
1229 case T_ADDRESS: | |
304 | 1230 __ movptr(dest->as_register(), from_addr); |
1231 break; | |
0 | 1232 case T_INT: |
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1233 __ movl(dest->as_register(), from_addr); |
0 | 1234 break; |
1235 | |
1236 case T_LONG: { | |
1237 Register to_lo = dest->as_register_lo(); | |
1238 Register to_hi = dest->as_register_hi(); | |
304 | 1239 #ifdef _LP64 |
1240 __ movptr(to_lo, as_Address_lo(addr)); | |
1241 #else | |
0 | 1242 Register base = addr->base()->as_register(); |
1243 Register index = noreg; | |
1244 if (addr->index()->is_register()) { | |
1245 index = addr->index()->as_register(); | |
1246 } | |
1247 if ((base == to_lo && index == to_hi) || | |
1248 (base == to_hi && index == to_lo)) { | |
1249 // addresses with 2 registers are only formed as a result of | |
1250 // array access so this code will never have to deal with | |
1251 // patches or null checks. | |
1252 assert(info == NULL && patch == NULL, "must be"); | |
304 | 1253 __ lea(to_hi, as_Address(addr)); |
0 | 1254 __ movl(to_lo, Address(to_hi, 0)); |
1255 __ movl(to_hi, Address(to_hi, BytesPerWord)); | |
1256 } else if (base == to_lo || index == to_lo) { | |
1257 assert(base != to_hi, "can't be"); | |
1258 assert(index == noreg || (index != base && index != to_hi), "can't handle this"); | |
1259 __ movl(to_hi, as_Address_hi(addr)); | |
1260 if (patch != NULL) { | |
1261 patching_epilog(patch, lir_patch_high, base, info); | |
1262 patch = new PatchingStub(_masm, PatchingStub::access_field_id); | |
1263 patch_code = lir_patch_low; | |
1264 } | |
1265 __ movl(to_lo, as_Address_lo(addr)); | |
1266 } else { | |
1267 assert(index == noreg || (index != base && index != to_lo), "can't handle this"); | |
1268 __ movl(to_lo, as_Address_lo(addr)); | |
1269 if (patch != NULL) { | |
1270 patching_epilog(patch, lir_patch_low, base, info); | |
1271 patch = new PatchingStub(_masm, PatchingStub::access_field_id); | |
1272 patch_code = lir_patch_high; | |
1273 } | |
1274 __ movl(to_hi, as_Address_hi(addr)); | |
1275 } | |
304 | 1276 #endif // _LP64 |
0 | 1277 break; |
1278 } | |
1279 | |
1280 case T_BOOLEAN: // fall through | |
1281 case T_BYTE: { | |
1282 Register dest_reg = dest->as_register(); | |
1283 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6"); | |
1284 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { | |
304 | 1285 __ movsbl(dest_reg, from_addr); |
0 | 1286 } else { |
1287 __ movb(dest_reg, from_addr); | |
1288 __ shll(dest_reg, 24); | |
1289 __ sarl(dest_reg, 24); | |
1290 } | |
1291 break; | |
1292 } | |
1293 | |
1294 case T_CHAR: { | |
1295 Register dest_reg = dest->as_register(); | |
1296 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6"); | |
1297 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { | |
304 | 1298 __ movzwl(dest_reg, from_addr); |
0 | 1299 } else { |
1300 __ movw(dest_reg, from_addr); | |
1301 } | |
1302 break; | |
1303 } | |
1304 | |
1305 case T_SHORT: { | |
1306 Register dest_reg = dest->as_register(); | |
1307 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { | |
304 | 1308 __ movswl(dest_reg, from_addr); |
0 | 1309 } else { |
1310 __ movw(dest_reg, from_addr); | |
1311 __ shll(dest_reg, 16); | |
1312 __ sarl(dest_reg, 16); | |
1313 } | |
1314 break; | |
1315 } | |
1316 | |
1317 default: | |
1318 ShouldNotReachHere(); | |
1319 } | |
1320 | |
1321 if (patch != NULL) { | |
1322 patching_epilog(patch, patch_code, addr->base()->as_register(), info); | |
1323 } | |
1324 | |
1325 if (type == T_ARRAY || type == T_OBJECT) { | |
2002 | 1326 #ifdef _LP64 |
1327 if (UseCompressedOops && !wide) { | |
1328 __ decode_heap_oop(dest->as_register()); | |
1329 } | |
1330 #endif | |
0 | 1331 __ verify_oop(dest->as_register()); |
1332 } | |
1333 } | |
1334 | |
1335 | |
1336 void LIR_Assembler::prefetchr(LIR_Opr src) { | |
1337 LIR_Address* addr = src->as_address_ptr(); | |
1338 Address from_addr = as_Address(addr); | |
1339 | |
1340 if (VM_Version::supports_sse()) { | |
1341 switch (ReadPrefetchInstr) { | |
1342 case 0: | |
1343 __ prefetchnta(from_addr); break; | |
1344 case 1: | |
1345 __ prefetcht0(from_addr); break; | |
1346 case 2: | |
1347 __ prefetcht2(from_addr); break; | |
1348 default: | |
1349 ShouldNotReachHere(); break; | |
1350 } | |
2479 | 1351 } else if (VM_Version::supports_3dnow_prefetch()) { |
0 | 1352 __ prefetchr(from_addr); |
1353 } | |
1354 } | |
1355 | |
1356 | |
1357 void LIR_Assembler::prefetchw(LIR_Opr src) { | |
1358 LIR_Address* addr = src->as_address_ptr(); | |
1359 Address from_addr = as_Address(addr); | |
1360 | |
1361 if (VM_Version::supports_sse()) { | |
1362 switch (AllocatePrefetchInstr) { | |
1363 case 0: | |
1364 __ prefetchnta(from_addr); break; | |
1365 case 1: | |
1366 __ prefetcht0(from_addr); break; | |
1367 case 2: | |
1368 __ prefetcht2(from_addr); break; | |
1369 case 3: | |
1370 __ prefetchw(from_addr); break; | |
1371 default: | |
1372 ShouldNotReachHere(); break; | |
1373 } | |
2479 | 1374 } else if (VM_Version::supports_3dnow_prefetch()) { |
0 | 1375 __ prefetchw(from_addr); |
1376 } | |
1377 } | |
1378 | |
1379 | |
1380 NEEDS_CLEANUP; // This could be static? | |
1381 Address::ScaleFactor LIR_Assembler::array_element_size(BasicType type) const { | |
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1382 int elem_size = type2aelembytes(type); |
0 | 1383 switch (elem_size) { |
1384 case 1: return Address::times_1; | |
1385 case 2: return Address::times_2; | |
1386 case 4: return Address::times_4; | |
1387 case 8: return Address::times_8; | |
1388 } | |
1389 ShouldNotReachHere(); | |
1390 return Address::no_scale; | |
1391 } | |
1392 | |
1393 | |
1394 void LIR_Assembler::emit_op3(LIR_Op3* op) { | |
1395 switch (op->code()) { | |
1396 case lir_idiv: | |
1397 case lir_irem: | |
1398 arithmetic_idiv(op->code(), | |
1399 op->in_opr1(), | |
1400 op->in_opr2(), | |
1401 op->in_opr3(), | |
1402 op->result_opr(), | |
1403 op->info()); | |
1404 break; | |
1405 default: ShouldNotReachHere(); break; | |
1406 } | |
1407 } | |
1408 | |
1409 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) { | |
1410 #ifdef ASSERT | |
1411 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label"); | |
1412 if (op->block() != NULL) _branch_target_blocks.append(op->block()); | |
1413 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock()); | |
1414 #endif | |
1415 | |
1416 if (op->cond() == lir_cond_always) { | |
1417 if (op->info() != NULL) add_debug_info_for_branch(op->info()); | |
1418 __ jmp (*(op->label())); | |
1419 } else { | |
1420 Assembler::Condition acond = Assembler::zero; | |
1421 if (op->code() == lir_cond_float_branch) { | |
1422 assert(op->ublock() != NULL, "must have unordered successor"); | |
1423 __ jcc(Assembler::parity, *(op->ublock()->label())); | |
1424 switch(op->cond()) { | |
1425 case lir_cond_equal: acond = Assembler::equal; break; | |
1426 case lir_cond_notEqual: acond = Assembler::notEqual; break; | |
1427 case lir_cond_less: acond = Assembler::below; break; | |
1428 case lir_cond_lessEqual: acond = Assembler::belowEqual; break; | |
1429 case lir_cond_greaterEqual: acond = Assembler::aboveEqual; break; | |
1430 case lir_cond_greater: acond = Assembler::above; break; | |
1431 default: ShouldNotReachHere(); | |
1432 } | |
1433 } else { | |
1434 switch (op->cond()) { | |
1435 case lir_cond_equal: acond = Assembler::equal; break; | |
1436 case lir_cond_notEqual: acond = Assembler::notEqual; break; | |
1437 case lir_cond_less: acond = Assembler::less; break; | |
1438 case lir_cond_lessEqual: acond = Assembler::lessEqual; break; | |
1439 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break; | |
1440 case lir_cond_greater: acond = Assembler::greater; break; | |
1441 case lir_cond_belowEqual: acond = Assembler::belowEqual; break; | |
1442 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break; | |
1443 default: ShouldNotReachHere(); | |
1444 } | |
1445 } | |
1446 __ jcc(acond,*(op->label())); | |
1447 } | |
1448 } | |
1449 | |
1450 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) { | |
1451 LIR_Opr src = op->in_opr(); | |
1452 LIR_Opr dest = op->result_opr(); | |
1453 | |
1454 switch (op->bytecode()) { | |
1455 case Bytecodes::_i2l: | |
304 | 1456 #ifdef _LP64 |
1457 __ movl2ptr(dest->as_register_lo(), src->as_register()); | |
1458 #else | |
0 | 1459 move_regs(src->as_register(), dest->as_register_lo()); |
1460 move_regs(src->as_register(), dest->as_register_hi()); | |
1461 __ sarl(dest->as_register_hi(), 31); | |
304 | 1462 #endif // LP64 |
0 | 1463 break; |
1464 | |
1465 case Bytecodes::_l2i: | |
1466 move_regs(src->as_register_lo(), dest->as_register()); | |
1467 break; | |
1468 | |
1469 case Bytecodes::_i2b: | |
1470 move_regs(src->as_register(), dest->as_register()); | |
1471 __ sign_extend_byte(dest->as_register()); | |
1472 break; | |
1473 | |
1474 case Bytecodes::_i2c: | |
1475 move_regs(src->as_register(), dest->as_register()); | |
1476 __ andl(dest->as_register(), 0xFFFF); | |
1477 break; | |
1478 | |
1479 case Bytecodes::_i2s: | |
1480 move_regs(src->as_register(), dest->as_register()); | |
1481 __ sign_extend_short(dest->as_register()); | |
1482 break; | |
1483 | |
1484 | |
1485 case Bytecodes::_f2d: | |
1486 case Bytecodes::_d2f: | |
1487 if (dest->is_single_xmm()) { | |
1488 __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg()); | |
1489 } else if (dest->is_double_xmm()) { | |
1490 __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg()); | |
1491 } else { | |
1492 assert(src->fpu() == dest->fpu(), "register must be equal"); | |
1493 // do nothing (float result is rounded later through spilling) | |
1494 } | |
1495 break; | |
1496 | |
1497 case Bytecodes::_i2f: | |
1498 case Bytecodes::_i2d: | |
1499 if (dest->is_single_xmm()) { | |
304 | 1500 __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register()); |
0 | 1501 } else if (dest->is_double_xmm()) { |
304 | 1502 __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register()); |
0 | 1503 } else { |
1504 assert(dest->fpu() == 0, "result must be on TOS"); | |
1505 __ movl(Address(rsp, 0), src->as_register()); | |
1506 __ fild_s(Address(rsp, 0)); | |
1507 } | |
1508 break; | |
1509 | |
1510 case Bytecodes::_f2i: | |
1511 case Bytecodes::_d2i: | |
1512 if (src->is_single_xmm()) { | |
304 | 1513 __ cvttss2sil(dest->as_register(), src->as_xmm_float_reg()); |
0 | 1514 } else if (src->is_double_xmm()) { |
304 | 1515 __ cvttsd2sil(dest->as_register(), src->as_xmm_double_reg()); |
0 | 1516 } else { |
1517 assert(src->fpu() == 0, "input must be on TOS"); | |
1518 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc())); | |
1519 __ fist_s(Address(rsp, 0)); | |
1520 __ movl(dest->as_register(), Address(rsp, 0)); | |
1521 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); | |
1522 } | |
1523 | |
1524 // IA32 conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub | |
1525 assert(op->stub() != NULL, "stub required"); | |
1526 __ cmpl(dest->as_register(), 0x80000000); | |
1527 __ jcc(Assembler::equal, *op->stub()->entry()); | |
1528 __ bind(*op->stub()->continuation()); | |
1529 break; | |
1530 | |
1531 case Bytecodes::_l2f: | |
1532 case Bytecodes::_l2d: | |
1533 assert(!dest->is_xmm_register(), "result in xmm register not supported (no SSE instruction present)"); | |
1534 assert(dest->fpu() == 0, "result must be on TOS"); | |
1535 | |
304 | 1536 __ movptr(Address(rsp, 0), src->as_register_lo()); |
1537 NOT_LP64(__ movl(Address(rsp, BytesPerWord), src->as_register_hi())); | |
0 | 1538 __ fild_d(Address(rsp, 0)); |
1539 // float result is rounded later through spilling | |
1540 break; | |
1541 | |
1542 case Bytecodes::_f2l: | |
1543 case Bytecodes::_d2l: | |
1544 assert(!src->is_xmm_register(), "input in xmm register not supported (no SSE instruction present)"); | |
1545 assert(src->fpu() == 0, "input must be on TOS"); | |
304 | 1546 assert(dest == FrameMap::long0_opr, "runtime stub places result in these registers"); |
0 | 1547 |
1548 // instruction sequence too long to inline it here | |
1549 { | |
1550 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::fpu2long_stub_id))); | |
1551 } | |
1552 break; | |
1553 | |
1554 default: ShouldNotReachHere(); | |
1555 } | |
1556 } | |
1557 | |
1558 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) { | |
1559 if (op->init_check()) { | |
1560 __ cmpl(Address(op->klass()->as_register(), | |
1561 instanceKlass::init_state_offset_in_bytes() + sizeof(oopDesc)), | |
1562 instanceKlass::fully_initialized); | |
1563 add_debug_info_for_null_check_here(op->stub()->info()); | |
1564 __ jcc(Assembler::notEqual, *op->stub()->entry()); | |
1565 } | |
1566 __ allocate_object(op->obj()->as_register(), | |
1567 op->tmp1()->as_register(), | |
1568 op->tmp2()->as_register(), | |
1569 op->header_size(), | |
1570 op->object_size(), | |
1571 op->klass()->as_register(), | |
1572 *op->stub()->entry()); | |
1573 __ bind(*op->stub()->continuation()); | |
1574 } | |
1575 | |
1576 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) { | |
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1577 Register len = op->len()->as_register(); |
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1578 LP64_ONLY( __ movslq(len, len); ) |
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1579 |
0 | 1580 if (UseSlowPath || |
1581 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) || | |
1582 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) { | |
1583 __ jmp(*op->stub()->entry()); | |
1584 } else { | |
1585 Register tmp1 = op->tmp1()->as_register(); | |
1586 Register tmp2 = op->tmp2()->as_register(); | |
1587 Register tmp3 = op->tmp3()->as_register(); | |
1588 if (len == tmp1) { | |
1589 tmp1 = tmp3; | |
1590 } else if (len == tmp2) { | |
1591 tmp2 = tmp3; | |
1592 } else if (len == tmp3) { | |
1593 // everything is ok | |
1594 } else { | |
304 | 1595 __ mov(tmp3, len); |
0 | 1596 } |
1597 __ allocate_array(op->obj()->as_register(), | |
1598 len, | |
1599 tmp1, | |
1600 tmp2, | |
1601 arrayOopDesc::header_size(op->type()), | |
1602 array_element_size(op->type()), | |
1603 op->klass()->as_register(), | |
1604 *op->stub()->entry()); | |
1605 } | |
1606 __ bind(*op->stub()->continuation()); | |
1607 } | |
1608 | |
1783 | 1609 void LIR_Assembler::type_profile_helper(Register mdo, |
1610 ciMethodData *md, ciProfileData *data, | |
1611 Register recv, Label* update_done) { | |
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1612 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) { |
1783 | 1613 Label next_test; |
1614 // See if the receiver is receiver[n]. | |
1615 __ cmpptr(recv, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)))); | |
1616 __ jccb(Assembler::notEqual, next_test); | |
1617 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))); | |
1618 __ addptr(data_addr, DataLayout::counter_increment); | |
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1619 __ jmp(*update_done); |
1783 | 1620 __ bind(next_test); |
1621 } | |
1622 | |
1623 // Didn't find receiver; find next empty slot and fill it in | |
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1624 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) { |
1783 | 1625 Label next_test; |
1626 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))); | |
1627 __ cmpptr(recv_addr, (intptr_t)NULL_WORD); | |
1628 __ jccb(Assembler::notEqual, next_test); | |
1629 __ movptr(recv_addr, recv); | |
1630 __ movptr(Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))), DataLayout::counter_increment); | |
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1631 __ jmp(*update_done); |
1783 | 1632 __ bind(next_test); |
1633 } | |
1634 } | |
1635 | |
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1636 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) { |
1783 | 1637 // we always need a stub for the failure case. |
1638 CodeStub* stub = op->stub(); | |
1639 Register obj = op->object()->as_register(); | |
1640 Register k_RInfo = op->tmp1()->as_register(); | |
1641 Register klass_RInfo = op->tmp2()->as_register(); | |
1642 Register dst = op->result_opr()->as_register(); | |
1643 ciKlass* k = op->klass(); | |
1644 Register Rtmp1 = noreg; | |
1645 | |
1646 // check if it needs to be profiled | |
1647 ciMethodData* md; | |
1648 ciProfileData* data; | |
1649 | |
1650 if (op->should_profile()) { | |
1651 ciMethod* method = op->profiled_method(); | |
1652 assert(method != NULL, "Should have method"); | |
1653 int bci = op->profiled_bci(); | |
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1654 md = method->method_data_or_null(); |
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1655 assert(md != NULL, "Sanity"); |
1783 | 1656 data = md->bci_to_data(bci); |
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1657 assert(data != NULL, "need data for type check"); |
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1658 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check"); |
1783 | 1659 } |
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1660 Label profile_cast_success, profile_cast_failure; |
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1661 Label *success_target = op->should_profile() ? &profile_cast_success : success; |
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1662 Label *failure_target = op->should_profile() ? &profile_cast_failure : failure; |
1783 | 1663 |
1664 if (obj == k_RInfo) { | |
1665 k_RInfo = dst; | |
1666 } else if (obj == klass_RInfo) { | |
1667 klass_RInfo = dst; | |
1668 } | |
2002 | 1669 if (k->is_loaded() && !UseCompressedOops) { |
1783 | 1670 select_different_registers(obj, dst, k_RInfo, klass_RInfo); |
1671 } else { | |
1672 Rtmp1 = op->tmp3()->as_register(); | |
1673 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1); | |
1674 } | |
1675 | |
1676 assert_different_registers(obj, k_RInfo, klass_RInfo); | |
1677 if (!k->is_loaded()) { | |
1678 jobject2reg_with_patching(k_RInfo, op->info_for_patch()); | |
1679 } else { | |
1680 #ifdef _LP64 | |
1681 __ movoop(k_RInfo, k->constant_encoding()); | |
1682 #endif // _LP64 | |
1683 } | |
1684 assert(obj != k_RInfo, "must be different"); | |
1685 | |
1686 __ cmpptr(obj, (int32_t)NULL_WORD); | |
1687 if (op->should_profile()) { | |
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1688 Label not_null; |
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1689 __ jccb(Assembler::notEqual, not_null); |
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1690 // Object is null; update MDO and exit |
1783 | 1691 Register mdo = klass_RInfo; |
1692 __ movoop(mdo, md->constant_encoding()); | |
1693 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset())); | |
1694 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant()); | |
1695 __ orl(data_addr, header_bits); | |
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1696 __ jmp(*obj_is_null); |
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1697 __ bind(not_null); |
1783 | 1698 } else { |
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1699 __ jcc(Assembler::equal, *obj_is_null); |
1783 | 1700 } |
1701 __ verify_oop(obj); | |
1702 | |
1703 if (op->fast_check()) { | |
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1704 // get object class |
1783 | 1705 // not a safepoint as obj null check happens earlier |
1706 #ifdef _LP64 | |
2002 | 1707 if (UseCompressedOops) { |
1708 __ load_klass(Rtmp1, obj); | |
1709 __ cmpptr(k_RInfo, Rtmp1); | |
1783 | 1710 } else { |
1711 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); | |
1712 } | |
2002 | 1713 #else |
1714 if (k->is_loaded()) { | |
1715 __ cmpoop(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding()); | |
1716 } else { | |
1717 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); | |
1718 } | |
1719 #endif | |
1783 | 1720 __ jcc(Assembler::notEqual, *failure_target); |
1791
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1721 // successful cast, fall through to profile or jump |
1783 | 1722 } else { |
1723 // get object class | |
1724 // not a safepoint as obj null check happens earlier | |
2002 | 1725 __ load_klass(klass_RInfo, obj); |
1783 | 1726 if (k->is_loaded()) { |
1727 // See if we get an immediate positive hit | |
1728 #ifdef _LP64 | |
1729 __ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset())); | |
1730 #else | |
1731 __ cmpoop(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding()); | |
1732 #endif // _LP64 | |
1733 if (sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes() != k->super_check_offset()) { | |
1734 __ jcc(Assembler::notEqual, *failure_target); | |
1791
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1735 // successful cast, fall through to profile or jump |
1783 | 1736 } else { |
1737 // See if we get an immediate positive hit | |
1791
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1738 __ jcc(Assembler::equal, *success_target); |
1783 | 1739 // check for self |
1740 #ifdef _LP64 | |
1741 __ cmpptr(klass_RInfo, k_RInfo); | |
1742 #else | |
1743 __ cmpoop(klass_RInfo, k->constant_encoding()); | |
1744 #endif // _LP64 | |
1791
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1745 __ jcc(Assembler::equal, *success_target); |
1783 | 1746 |
1747 __ push(klass_RInfo); | |
1748 #ifdef _LP64 | |
1749 __ push(k_RInfo); | |
1750 #else | |
1751 __ pushoop(k->constant_encoding()); | |
1752 #endif // _LP64 | |
1753 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); | |
1754 __ pop(klass_RInfo); | |
1755 __ pop(klass_RInfo); | |
1756 // result is a boolean | |
1757 __ cmpl(klass_RInfo, 0); | |
1758 __ jcc(Assembler::equal, *failure_target); | |
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1759 // successful cast, fall through to profile or jump |
1783 | 1760 } |
1761 } else { | |
1762 // perform the fast part of the checking logic | |
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1763 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL); |
1783 | 1764 // call out-of-line instance of __ check_klass_subtype_slow_path(...): |
1765 __ push(klass_RInfo); | |
1766 __ push(k_RInfo); | |
1767 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); | |
1768 __ pop(klass_RInfo); | |
1769 __ pop(k_RInfo); | |
1770 // result is a boolean | |
1771 __ cmpl(k_RInfo, 0); | |
1772 __ jcc(Assembler::equal, *failure_target); | |
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1773 // successful cast, fall through to profile or jump |
1783 | 1774 } |
1775 } | |
1776 if (op->should_profile()) { | |
1777 Register mdo = klass_RInfo, recv = k_RInfo; | |
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1778 __ bind(profile_cast_success); |
1783 | 1779 __ movoop(mdo, md->constant_encoding()); |
2002 | 1780 __ load_klass(recv, obj); |
1783 | 1781 Label update_done; |
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1782 type_profile_helper(mdo, md, data, recv, success); |
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1783 __ jmp(*success); |
1783 | 1784 |
1785 __ bind(profile_cast_failure); | |
1786 __ movoop(mdo, md->constant_encoding()); | |
1787 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); | |
1788 __ subptr(counter_addr, DataLayout::counter_increment); | |
1791
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1789 __ jmp(*failure); |
1783 | 1790 } |
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1791 __ jmp(*success); |
1783 | 1792 } |
0 | 1793 |
1791
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1794 |
0 | 1795 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) { |
1796 LIR_Code code = op->code(); | |
1797 if (code == lir_store_check) { | |
1798 Register value = op->object()->as_register(); | |
1799 Register array = op->array()->as_register(); | |
1800 Register k_RInfo = op->tmp1()->as_register(); | |
1801 Register klass_RInfo = op->tmp2()->as_register(); | |
1802 Register Rtmp1 = op->tmp3()->as_register(); | |
1803 | |
1804 CodeStub* stub = op->stub(); | |
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1805 |
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1806 // check if it needs to be profiled |
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1807 ciMethodData* md; |
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1808 ciProfileData* data; |
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1809 |
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1810 if (op->should_profile()) { |
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1811 ciMethod* method = op->profiled_method(); |
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1812 assert(method != NULL, "Should have method"); |
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1813 int bci = op->profiled_bci(); |
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1814 md = method->method_data_or_null(); |
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1815 assert(md != NULL, "Sanity"); |
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1816 data = md->bci_to_data(bci); |
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1817 assert(data != NULL, "need data for type check"); |
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1818 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check"); |
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1819 } |
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1820 Label profile_cast_success, profile_cast_failure, done; |
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1821 Label *success_target = op->should_profile() ? &profile_cast_success : &done; |
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1822 Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry(); |
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1823 |
304 | 1824 __ cmpptr(value, (int32_t)NULL_WORD); |
1791
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1825 if (op->should_profile()) { |
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1826 Label not_null; |
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1827 __ jccb(Assembler::notEqual, not_null); |
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1828 // Object is null; update MDO and exit |
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1829 Register mdo = klass_RInfo; |
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1830 __ movoop(mdo, md->constant_encoding()); |
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1831 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset())); |
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1832 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant()); |
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1833 __ orl(data_addr, header_bits); |
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1834 __ jmp(done); |
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1835 __ bind(not_null); |
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1836 } else { |
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1837 __ jcc(Assembler::equal, done); |
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1838 } |
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1839 |
0 | 1840 add_debug_info_for_null_check_here(op->info_for_exception()); |
2002 | 1841 __ load_klass(k_RInfo, array); |
1842 __ load_klass(klass_RInfo, value); | |
1843 | |
1844 // get instance klass (it's already uncompressed) | |
304 | 1845 __ movptr(k_RInfo, Address(k_RInfo, objArrayKlass::element_klass_offset_in_bytes() + sizeof(oopDesc))); |
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1846 // perform the fast part of the checking logic |
1791
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1847 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL); |
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1848 // call out-of-line instance of __ check_klass_subtype_slow_path(...): |
304 | 1849 __ push(klass_RInfo); |
1850 __ push(k_RInfo); | |
0 | 1851 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); |
304 | 1852 __ pop(klass_RInfo); |
1853 __ pop(k_RInfo); | |
1854 // result is a boolean | |
0 | 1855 __ cmpl(k_RInfo, 0); |
1791
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1856 __ jcc(Assembler::equal, *failure_target); |
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1857 // fall through to the success case |
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1858 |
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1859 if (op->should_profile()) { |
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1860 Register mdo = klass_RInfo, recv = k_RInfo; |
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1861 __ bind(profile_cast_success); |
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1862 __ movoop(mdo, md->constant_encoding()); |
2002 | 1863 __ load_klass(recv, value); |
1791
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1864 Label update_done; |
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1865 type_profile_helper(mdo, md, data, recv, &done); |
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1866 __ jmpb(done); |
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1867 |
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1868 __ bind(profile_cast_failure); |
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1869 __ movoop(mdo, md->constant_encoding()); |
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1870 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); |
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1871 __ subptr(counter_addr, DataLayout::counter_increment); |
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1872 __ jmp(*stub->entry()); |
0 | 1873 } |
1791
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1874 |
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1875 __ bind(done); |
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1876 } else |
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1877 if (code == lir_checkcast) { |
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1878 Register obj = op->object()->as_register(); |
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1879 Register dst = op->result_opr()->as_register(); |
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1880 Label success; |
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1881 emit_typecheck_helper(op, &success, op->stub()->entry(), &success); |
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1882 __ bind(success); |
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1883 if (dst != obj) { |
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1884 __ mov(dst, obj); |
0 | 1885 } |
1791
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1886 } else |
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1887 if (code == lir_instanceof) { |
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1888 Register obj = op->object()->as_register(); |
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1889 Register dst = op->result_opr()->as_register(); |
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1890 Label success, failure, done; |
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1891 emit_typecheck_helper(op, &success, &failure, &failure); |
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1892 __ bind(failure); |
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1893 __ xorptr(dst, dst); |
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1894 __ jmpb(done); |
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1895 __ bind(success); |
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1896 __ movptr(dst, 1); |
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1897 __ bind(done); |
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1898 } else { |
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1899 ShouldNotReachHere(); |
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1900 } |
0 | 1901 |
1902 } | |
1903 | |
1904 | |
1905 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) { | |
304 | 1906 if (LP64_ONLY(false &&) op->code() == lir_cas_long && VM_Version::supports_cx8()) { |
0 | 1907 assert(op->cmp_value()->as_register_lo() == rax, "wrong register"); |
1908 assert(op->cmp_value()->as_register_hi() == rdx, "wrong register"); | |
1909 assert(op->new_value()->as_register_lo() == rbx, "wrong register"); | |
1910 assert(op->new_value()->as_register_hi() == rcx, "wrong register"); | |
1911 Register addr = op->addr()->as_register(); | |
1912 if (os::is_MP()) { | |
1913 __ lock(); | |
1914 } | |
304 | 1915 NOT_LP64(__ cmpxchg8(Address(addr, 0))); |
1916 | |
1917 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj ) { | |
1918 NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");) | |
1919 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo()); | |
0 | 1920 Register newval = op->new_value()->as_register(); |
1921 Register cmpval = op->cmp_value()->as_register(); | |
1922 assert(cmpval == rax, "wrong register"); | |
1923 assert(newval != NULL, "new val must be register"); | |
1924 assert(cmpval != newval, "cmp and new values must be in different registers"); | |
1925 assert(cmpval != addr, "cmp and addr must be in different registers"); | |
1926 assert(newval != addr, "new value and addr must be in different registers"); | |
2002 | 1927 |
304 | 1928 if ( op->code() == lir_cas_obj) { |
2002 | 1929 #ifdef _LP64 |
1930 if (UseCompressedOops) { | |
1931 __ encode_heap_oop(cmpval); | |
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1932 __ mov(rscratch1, newval); |
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1933 __ encode_heap_oop(rscratch1); |
2002 | 1934 if (os::is_MP()) { |
1935 __ lock(); | |
1936 } | |
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1937 // cmpval (rax) is implicitly used by this instruction |
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1938 __ cmpxchgl(rscratch1, Address(addr, 0)); |
2002 | 1939 } else |
1940 #endif | |
1941 { | |
1942 if (os::is_MP()) { | |
1943 __ lock(); | |
1944 } | |
1945 __ cmpxchgptr(newval, Address(addr, 0)); | |
1946 } | |
1947 } else { | |
1948 assert(op->code() == lir_cas_int, "lir_cas_int expected"); | |
1949 if (os::is_MP()) { | |
1950 __ lock(); | |
1951 } | |
304 | 1952 __ cmpxchgl(newval, Address(addr, 0)); |
1953 } | |
1954 #ifdef _LP64 | |
1955 } else if (op->code() == lir_cas_long) { | |
1956 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo()); | |
1957 Register newval = op->new_value()->as_register_lo(); | |
1958 Register cmpval = op->cmp_value()->as_register_lo(); | |
1959 assert(cmpval == rax, "wrong register"); | |
1960 assert(newval != NULL, "new val must be register"); | |
1961 assert(cmpval != newval, "cmp and new values must be in different registers"); | |
1962 assert(cmpval != addr, "cmp and addr must be in different registers"); | |
1963 assert(newval != addr, "new value and addr must be in different registers"); | |
1964 if (os::is_MP()) { | |
1965 __ lock(); | |
1966 } | |
1967 __ cmpxchgq(newval, Address(addr, 0)); | |
1968 #endif // _LP64 | |
0 | 1969 } else { |
1970 Unimplemented(); | |
1971 } | |
1972 } | |
1973 | |
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1974 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) { |
0 | 1975 Assembler::Condition acond, ncond; |
1976 switch (condition) { | |
1977 case lir_cond_equal: acond = Assembler::equal; ncond = Assembler::notEqual; break; | |
1978 case lir_cond_notEqual: acond = Assembler::notEqual; ncond = Assembler::equal; break; | |
1979 case lir_cond_less: acond = Assembler::less; ncond = Assembler::greaterEqual; break; | |
1980 case lir_cond_lessEqual: acond = Assembler::lessEqual; ncond = Assembler::greater; break; | |
1981 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; ncond = Assembler::less; break; | |
1982 case lir_cond_greater: acond = Assembler::greater; ncond = Assembler::lessEqual; break; | |
1983 case lir_cond_belowEqual: acond = Assembler::belowEqual; ncond = Assembler::above; break; | |
1984 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; ncond = Assembler::below; break; | |
1985 default: ShouldNotReachHere(); | |
1986 } | |
1987 | |
1988 if (opr1->is_cpu_register()) { | |
1989 reg2reg(opr1, result); | |
1990 } else if (opr1->is_stack()) { | |
1991 stack2reg(opr1, result, result->type()); | |
1992 } else if (opr1->is_constant()) { | |
1993 const2reg(opr1, result, lir_patch_none, NULL); | |
1994 } else { | |
1995 ShouldNotReachHere(); | |
1996 } | |
1997 | |
1998 if (VM_Version::supports_cmov() && !opr2->is_constant()) { | |
1999 // optimized version that does not require a branch | |
2000 if (opr2->is_single_cpu()) { | |
2001 assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move"); | |
304 | 2002 __ cmov(ncond, result->as_register(), opr2->as_register()); |
0 | 2003 } else if (opr2->is_double_cpu()) { |
2004 assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move"); | |
2005 assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move"); | |
304 | 2006 __ cmovptr(ncond, result->as_register_lo(), opr2->as_register_lo()); |
2007 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), opr2->as_register_hi());) | |
0 | 2008 } else if (opr2->is_single_stack()) { |
2009 __ cmovl(ncond, result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix())); | |
2010 } else if (opr2->is_double_stack()) { | |
304 | 2011 __ cmovptr(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes)); |
2012 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), frame_map()->address_for_slot(opr2->double_stack_ix(), hi_word_offset_in_bytes));) | |
0 | 2013 } else { |
2014 ShouldNotReachHere(); | |
2015 } | |
2016 | |
2017 } else { | |
2018 Label skip; | |
2019 __ jcc (acond, skip); | |
2020 if (opr2->is_cpu_register()) { | |
2021 reg2reg(opr2, result); | |
2022 } else if (opr2->is_stack()) { | |
2023 stack2reg(opr2, result, result->type()); | |
2024 } else if (opr2->is_constant()) { | |
2025 const2reg(opr2, result, lir_patch_none, NULL); | |
2026 } else { | |
2027 ShouldNotReachHere(); | |
2028 } | |
2029 __ bind(skip); | |
2030 } | |
2031 } | |
2032 | |
2033 | |
2034 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) { | |
2035 assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method"); | |
2036 | |
2037 if (left->is_single_cpu()) { | |
2038 assert(left == dest, "left and dest must be equal"); | |
2039 Register lreg = left->as_register(); | |
2040 | |
2041 if (right->is_single_cpu()) { | |
2042 // cpu register - cpu register | |
2043 Register rreg = right->as_register(); | |
2044 switch (code) { | |
2045 case lir_add: __ addl (lreg, rreg); break; | |
2046 case lir_sub: __ subl (lreg, rreg); break; | |
2047 case lir_mul: __ imull(lreg, rreg); break; | |
2048 default: ShouldNotReachHere(); | |
2049 } | |
2050 | |
2051 } else if (right->is_stack()) { | |
2052 // cpu register - stack | |
2053 Address raddr = frame_map()->address_for_slot(right->single_stack_ix()); | |
2054 switch (code) { | |
2055 case lir_add: __ addl(lreg, raddr); break; | |
2056 case lir_sub: __ subl(lreg, raddr); break; | |
2057 default: ShouldNotReachHere(); | |
2058 } | |
2059 | |
2060 } else if (right->is_constant()) { | |
2061 // cpu register - constant | |
2062 jint c = right->as_constant_ptr()->as_jint(); | |
2063 switch (code) { | |
2064 case lir_add: { | |
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2065 __ incrementl(lreg, c); |
0 | 2066 break; |
2067 } | |
2068 case lir_sub: { | |
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2069 __ decrementl(lreg, c); |
0 | 2070 break; |
2071 } | |
2072 default: ShouldNotReachHere(); | |
2073 } | |
2074 | |
2075 } else { | |
2076 ShouldNotReachHere(); | |
2077 } | |
2078 | |
2079 } else if (left->is_double_cpu()) { | |
2080 assert(left == dest, "left and dest must be equal"); | |
2081 Register lreg_lo = left->as_register_lo(); | |
2082 Register lreg_hi = left->as_register_hi(); | |
2083 | |
2084 if (right->is_double_cpu()) { | |
2085 // cpu register - cpu register | |
2086 Register rreg_lo = right->as_register_lo(); | |
2087 Register rreg_hi = right->as_register_hi(); | |
304 | 2088 NOT_LP64(assert_different_registers(lreg_lo, lreg_hi, rreg_lo, rreg_hi)); |
2089 LP64_ONLY(assert_different_registers(lreg_lo, rreg_lo)); | |
0 | 2090 switch (code) { |
2091 case lir_add: | |
304 | 2092 __ addptr(lreg_lo, rreg_lo); |
2093 NOT_LP64(__ adcl(lreg_hi, rreg_hi)); | |
0 | 2094 break; |
2095 case lir_sub: | |
304 | 2096 __ subptr(lreg_lo, rreg_lo); |
2097 NOT_LP64(__ sbbl(lreg_hi, rreg_hi)); | |
0 | 2098 break; |
2099 case lir_mul: | |
304 | 2100 #ifdef _LP64 |
2101 __ imulq(lreg_lo, rreg_lo); | |
2102 #else | |
0 | 2103 assert(lreg_lo == rax && lreg_hi == rdx, "must be"); |
2104 __ imull(lreg_hi, rreg_lo); | |
2105 __ imull(rreg_hi, lreg_lo); | |
2106 __ addl (rreg_hi, lreg_hi); | |
2107 __ mull (rreg_lo); | |
2108 __ addl (lreg_hi, rreg_hi); | |
304 | 2109 #endif // _LP64 |
0 | 2110 break; |
2111 default: | |
2112 ShouldNotReachHere(); | |
2113 } | |
2114 | |
2115 } else if (right->is_constant()) { | |
2116 // cpu register - constant | |
304 | 2117 #ifdef _LP64 |
2118 jlong c = right->as_constant_ptr()->as_jlong_bits(); | |
2119 __ movptr(r10, (intptr_t) c); | |
2120 switch (code) { | |
2121 case lir_add: | |
2122 __ addptr(lreg_lo, r10); | |
2123 break; | |
2124 case lir_sub: | |
2125 __ subptr(lreg_lo, r10); | |
2126 break; | |
2127 default: | |
2128 ShouldNotReachHere(); | |
2129 } | |
2130 #else | |
0 | 2131 jint c_lo = right->as_constant_ptr()->as_jint_lo(); |
2132 jint c_hi = right->as_constant_ptr()->as_jint_hi(); | |
2133 switch (code) { | |
2134 case lir_add: | |
304 | 2135 __ addptr(lreg_lo, c_lo); |
0 | 2136 __ adcl(lreg_hi, c_hi); |
2137 break; | |
2138 case lir_sub: | |
304 | 2139 __ subptr(lreg_lo, c_lo); |
0 | 2140 __ sbbl(lreg_hi, c_hi); |
2141 break; | |
2142 default: | |
2143 ShouldNotReachHere(); | |
2144 } | |
304 | 2145 #endif // _LP64 |
0 | 2146 |
2147 } else { | |
2148 ShouldNotReachHere(); | |
2149 } | |
2150 | |
2151 } else if (left->is_single_xmm()) { | |
2152 assert(left == dest, "left and dest must be equal"); | |
2153 XMMRegister lreg = left->as_xmm_float_reg(); | |
2154 | |
2155 if (right->is_single_xmm()) { | |
2156 XMMRegister rreg = right->as_xmm_float_reg(); | |
2157 switch (code) { | |
2158 case lir_add: __ addss(lreg, rreg); break; | |
2159 case lir_sub: __ subss(lreg, rreg); break; | |
2160 case lir_mul_strictfp: // fall through | |
2161 case lir_mul: __ mulss(lreg, rreg); break; | |
2162 case lir_div_strictfp: // fall through | |
2163 case lir_div: __ divss(lreg, rreg); break; | |
2164 default: ShouldNotReachHere(); | |
2165 } | |
2166 } else { | |
2167 Address raddr; | |
2168 if (right->is_single_stack()) { | |
2169 raddr = frame_map()->address_for_slot(right->single_stack_ix()); | |
2170 } else if (right->is_constant()) { | |
2171 // hack for now | |
2172 raddr = __ as_Address(InternalAddress(float_constant(right->as_jfloat()))); | |
2173 } else { | |
2174 ShouldNotReachHere(); | |
2175 } | |
2176 switch (code) { | |
2177 case lir_add: __ addss(lreg, raddr); break; | |
2178 case lir_sub: __ subss(lreg, raddr); break; | |
2179 case lir_mul_strictfp: // fall through | |
2180 case lir_mul: __ mulss(lreg, raddr); break; | |
2181 case lir_div_strictfp: // fall through | |
2182 case lir_div: __ divss(lreg, raddr); break; | |
2183 default: ShouldNotReachHere(); | |
2184 } | |
2185 } | |
2186 | |
2187 } else if (left->is_double_xmm()) { | |
2188 assert(left == dest, "left and dest must be equal"); | |
2189 | |
2190 XMMRegister lreg = left->as_xmm_double_reg(); | |
2191 if (right->is_double_xmm()) { | |
2192 XMMRegister rreg = right->as_xmm_double_reg(); | |
2193 switch (code) { | |
2194 case lir_add: __ addsd(lreg, rreg); break; | |
2195 case lir_sub: __ subsd(lreg, rreg); break; | |
2196 case lir_mul_strictfp: // fall through | |
2197 case lir_mul: __ mulsd(lreg, rreg); break; | |
2198 case lir_div_strictfp: // fall through | |
2199 case lir_div: __ divsd(lreg, rreg); break; | |
2200 default: ShouldNotReachHere(); | |
2201 } | |
2202 } else { | |
2203 Address raddr; | |
2204 if (right->is_double_stack()) { | |
2205 raddr = frame_map()->address_for_slot(right->double_stack_ix()); | |
2206 } else if (right->is_constant()) { | |
2207 // hack for now | |
2208 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble()))); | |
2209 } else { | |
2210 ShouldNotReachHere(); | |
2211 } | |
2212 switch (code) { | |
2213 case lir_add: __ addsd(lreg, raddr); break; | |
2214 case lir_sub: __ subsd(lreg, raddr); break; | |
2215 case lir_mul_strictfp: // fall through | |
2216 case lir_mul: __ mulsd(lreg, raddr); break; | |
2217 case lir_div_strictfp: // fall through | |
2218 case lir_div: __ divsd(lreg, raddr); break; | |
2219 default: ShouldNotReachHere(); | |
2220 } | |
2221 } | |
2222 | |
2223 } else if (left->is_single_fpu()) { | |
2224 assert(dest->is_single_fpu(), "fpu stack allocation required"); | |
2225 | |
2226 if (right->is_single_fpu()) { | |
2227 arith_fpu_implementation(code, left->fpu_regnr(), right->fpu_regnr(), dest->fpu_regnr(), pop_fpu_stack); | |
2228 | |
2229 } else { | |
2230 assert(left->fpu_regnr() == 0, "left must be on TOS"); | |
2231 assert(dest->fpu_regnr() == 0, "dest must be on TOS"); | |
2232 | |
2233 Address raddr; | |
2234 if (right->is_single_stack()) { | |
2235 raddr = frame_map()->address_for_slot(right->single_stack_ix()); | |
2236 } else if (right->is_constant()) { | |
2237 address const_addr = float_constant(right->as_jfloat()); | |
2238 assert(const_addr != NULL, "incorrect float/double constant maintainance"); | |
2239 // hack for now | |
2240 raddr = __ as_Address(InternalAddress(const_addr)); | |
2241 } else { | |
2242 ShouldNotReachHere(); | |
2243 } | |
2244 | |
2245 switch (code) { | |
2246 case lir_add: __ fadd_s(raddr); break; | |
2247 case lir_sub: __ fsub_s(raddr); break; | |
2248 case lir_mul_strictfp: // fall through | |
2249 case lir_mul: __ fmul_s(raddr); break; | |
2250 case lir_div_strictfp: // fall through | |
2251 case lir_div: __ fdiv_s(raddr); break; | |
2252 default: ShouldNotReachHere(); | |
2253 } | |
2254 } | |
2255 | |
2256 } else if (left->is_double_fpu()) { | |
2257 assert(dest->is_double_fpu(), "fpu stack allocation required"); | |
2258 | |
2259 if (code == lir_mul_strictfp || code == lir_div_strictfp) { | |
2260 // Double values require special handling for strictfp mul/div on x86 | |
2261 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias1())); | |
2262 __ fmulp(left->fpu_regnrLo() + 1); | |
2263 } | |
2264 | |
2265 if (right->is_double_fpu()) { | |
2266 arith_fpu_implementation(code, left->fpu_regnrLo(), right->fpu_regnrLo(), dest->fpu_regnrLo(), pop_fpu_stack); | |
2267 | |
2268 } else { | |
2269 assert(left->fpu_regnrLo() == 0, "left must be on TOS"); | |
2270 assert(dest->fpu_regnrLo() == 0, "dest must be on TOS"); | |
2271 | |
2272 Address raddr; | |
2273 if (right->is_double_stack()) { | |
2274 raddr = frame_map()->address_for_slot(right->double_stack_ix()); | |
2275 } else if (right->is_constant()) { | |
2276 // hack for now | |
2277 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble()))); | |
2278 } else { | |
2279 ShouldNotReachHere(); | |
2280 } | |
2281 | |
2282 switch (code) { | |
2283 case lir_add: __ fadd_d(raddr); break; | |
2284 case lir_sub: __ fsub_d(raddr); break; | |
2285 case lir_mul_strictfp: // fall through | |
2286 case lir_mul: __ fmul_d(raddr); break; | |
2287 case lir_div_strictfp: // fall through | |
2288 case lir_div: __ fdiv_d(raddr); break; | |
2289 default: ShouldNotReachHere(); | |
2290 } | |
2291 } | |
2292 | |
2293 if (code == lir_mul_strictfp || code == lir_div_strictfp) { | |
2294 // Double values require special handling for strictfp mul/div on x86 | |
2295 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias2())); | |
2296 __ fmulp(dest->fpu_regnrLo() + 1); | |
2297 } | |
2298 | |
2299 } else if (left->is_single_stack() || left->is_address()) { | |
2300 assert(left == dest, "left and dest must be equal"); | |
2301 | |
2302 Address laddr; | |
2303 if (left->is_single_stack()) { | |
2304 laddr = frame_map()->address_for_slot(left->single_stack_ix()); | |
2305 } else if (left->is_address()) { | |
2306 laddr = as_Address(left->as_address_ptr()); | |
2307 } else { | |
2308 ShouldNotReachHere(); | |
2309 } | |
2310 | |
2311 if (right->is_single_cpu()) { | |
2312 Register rreg = right->as_register(); | |
2313 switch (code) { | |
2314 case lir_add: __ addl(laddr, rreg); break; | |
2315 case lir_sub: __ subl(laddr, rreg); break; | |
2316 default: ShouldNotReachHere(); | |
2317 } | |
2318 } else if (right->is_constant()) { | |
2319 jint c = right->as_constant_ptr()->as_jint(); | |
2320 switch (code) { | |
2321 case lir_add: { | |
304 | 2322 __ incrementl(laddr, c); |
0 | 2323 break; |
2324 } | |
2325 case lir_sub: { | |
304 | 2326 __ decrementl(laddr, c); |
0 | 2327 break; |
2328 } | |
2329 default: ShouldNotReachHere(); | |
2330 } | |
2331 } else { | |
2332 ShouldNotReachHere(); | |
2333 } | |
2334 | |
2335 } else { | |
2336 ShouldNotReachHere(); | |
2337 } | |
2338 } | |
2339 | |
2340 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) { | |
2341 assert(pop_fpu_stack || (left_index == dest_index || right_index == dest_index), "invalid LIR"); | |
2342 assert(!pop_fpu_stack || (left_index - 1 == dest_index || right_index - 1 == dest_index), "invalid LIR"); | |
2343 assert(left_index == 0 || right_index == 0, "either must be on top of stack"); | |
2344 | |
2345 bool left_is_tos = (left_index == 0); | |
2346 bool dest_is_tos = (dest_index == 0); | |
2347 int non_tos_index = (left_is_tos ? right_index : left_index); | |
2348 | |
2349 switch (code) { | |
2350 case lir_add: | |
2351 if (pop_fpu_stack) __ faddp(non_tos_index); | |
2352 else if (dest_is_tos) __ fadd (non_tos_index); | |
2353 else __ fadda(non_tos_index); | |
2354 break; | |
2355 | |
2356 case lir_sub: | |
2357 if (left_is_tos) { | |
2358 if (pop_fpu_stack) __ fsubrp(non_tos_index); | |
2359 else if (dest_is_tos) __ fsub (non_tos_index); | |
2360 else __ fsubra(non_tos_index); | |
2361 } else { | |
2362 if (pop_fpu_stack) __ fsubp (non_tos_index); | |
2363 else if (dest_is_tos) __ fsubr (non_tos_index); | |
2364 else __ fsuba (non_tos_index); | |
2365 } | |
2366 break; | |
2367 | |
2368 case lir_mul_strictfp: // fall through | |
2369 case lir_mul: | |
2370 if (pop_fpu_stack) __ fmulp(non_tos_index); | |
2371 else if (dest_is_tos) __ fmul (non_tos_index); | |
2372 else __ fmula(non_tos_index); | |
2373 break; | |
2374 | |
2375 case lir_div_strictfp: // fall through | |
2376 case lir_div: | |
2377 if (left_is_tos) { | |
2378 if (pop_fpu_stack) __ fdivrp(non_tos_index); | |
2379 else if (dest_is_tos) __ fdiv (non_tos_index); | |
2380 else __ fdivra(non_tos_index); | |
2381 } else { | |
2382 if (pop_fpu_stack) __ fdivp (non_tos_index); | |
2383 else if (dest_is_tos) __ fdivr (non_tos_index); | |
2384 else __ fdiva (non_tos_index); | |
2385 } | |
2386 break; | |
2387 | |
2388 case lir_rem: | |
2389 assert(left_is_tos && dest_is_tos && right_index == 1, "must be guaranteed by FPU stack allocation"); | |
2390 __ fremr(noreg); | |
2391 break; | |
2392 | |
2393 default: | |
2394 ShouldNotReachHere(); | |
2395 } | |
2396 } | |
2397 | |
2398 | |
2399 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op) { | |
2400 if (value->is_double_xmm()) { | |
2401 switch(code) { | |
2402 case lir_abs : | |
2403 { | |
2404 if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) { | |
2405 __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); | |
2406 } | |
2407 __ andpd(dest->as_xmm_double_reg(), | |
2408 ExternalAddress((address)double_signmask_pool)); | |
2409 } | |
2410 break; | |
2411 | |
2412 case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break; | |
2413 // all other intrinsics are not available in the SSE instruction set, so FPU is used | |
2414 default : ShouldNotReachHere(); | |
2415 } | |
2416 | |
2417 } else if (value->is_double_fpu()) { | |
2418 assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS"); | |
2419 switch(code) { | |
2420 case lir_log : __ flog() ; break; | |
2421 case lir_log10 : __ flog10() ; break; | |
2422 case lir_abs : __ fabs() ; break; | |
2423 case lir_sqrt : __ fsqrt(); break; | |
2424 case lir_sin : | |
2425 // Should consider not saving rbx, if not necessary | |
2426 __ trigfunc('s', op->as_Op2()->fpu_stack_size()); | |
2427 break; | |
2428 case lir_cos : | |
2429 // Should consider not saving rbx, if not necessary | |
2430 assert(op->as_Op2()->fpu_stack_size() <= 6, "sin and cos need two free stack slots"); | |
2431 __ trigfunc('c', op->as_Op2()->fpu_stack_size()); | |
2432 break; | |
2433 case lir_tan : | |
2434 // Should consider not saving rbx, if not necessary | |
2435 __ trigfunc('t', op->as_Op2()->fpu_stack_size()); | |
2436 break; | |
2437 default : ShouldNotReachHere(); | |
2438 } | |
2439 } else { | |
2440 Unimplemented(); | |
2441 } | |
2442 } | |
2443 | |
2444 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) { | |
2445 // assert(left->destroys_register(), "check"); | |
2446 if (left->is_single_cpu()) { | |
2447 Register reg = left->as_register(); | |
2448 if (right->is_constant()) { | |
2449 int val = right->as_constant_ptr()->as_jint(); | |
2450 switch (code) { | |
2451 case lir_logic_and: __ andl (reg, val); break; | |
2452 case lir_logic_or: __ orl (reg, val); break; | |
2453 case lir_logic_xor: __ xorl (reg, val); break; | |
2454 default: ShouldNotReachHere(); | |
2455 } | |
2456 } else if (right->is_stack()) { | |
2457 // added support for stack operands | |
2458 Address raddr = frame_map()->address_for_slot(right->single_stack_ix()); | |
2459 switch (code) { | |
2460 case lir_logic_and: __ andl (reg, raddr); break; | |
2461 case lir_logic_or: __ orl (reg, raddr); break; | |
2462 case lir_logic_xor: __ xorl (reg, raddr); break; | |
2463 default: ShouldNotReachHere(); | |
2464 } | |
2465 } else { | |
2466 Register rright = right->as_register(); | |
2467 switch (code) { | |
304 | 2468 case lir_logic_and: __ andptr (reg, rright); break; |
2469 case lir_logic_or : __ orptr (reg, rright); break; | |
2470 case lir_logic_xor: __ xorptr (reg, rright); break; | |
0 | 2471 default: ShouldNotReachHere(); |
2472 } | |
2473 } | |
2474 move_regs(reg, dst->as_register()); | |
2475 } else { | |
2476 Register l_lo = left->as_register_lo(); | |
2477 Register l_hi = left->as_register_hi(); | |
2478 if (right->is_constant()) { | |
304 | 2479 #ifdef _LP64 |
2480 __ mov64(rscratch1, right->as_constant_ptr()->as_jlong()); | |
2481 switch (code) { | |
2482 case lir_logic_and: | |
2483 __ andq(l_lo, rscratch1); | |
2484 break; | |
2485 case lir_logic_or: | |
2486 __ orq(l_lo, rscratch1); | |
2487 break; | |
2488 case lir_logic_xor: | |
2489 __ xorq(l_lo, rscratch1); | |
2490 break; | |
2491 default: ShouldNotReachHere(); | |
2492 } | |
2493 #else | |
0 | 2494 int r_lo = right->as_constant_ptr()->as_jint_lo(); |
2495 int r_hi = right->as_constant_ptr()->as_jint_hi(); | |
2496 switch (code) { | |
2497 case lir_logic_and: | |
2498 __ andl(l_lo, r_lo); | |
2499 __ andl(l_hi, r_hi); | |
2500 break; | |
2501 case lir_logic_or: | |
2502 __ orl(l_lo, r_lo); | |
2503 __ orl(l_hi, r_hi); | |
2504 break; | |
2505 case lir_logic_xor: | |
2506 __ xorl(l_lo, r_lo); | |
2507 __ xorl(l_hi, r_hi); | |
2508 break; | |
2509 default: ShouldNotReachHere(); | |
2510 } | |
304 | 2511 #endif // _LP64 |
0 | 2512 } else { |
1572 | 2513 #ifdef _LP64 |
2514 Register r_lo; | |
2515 if (right->type() == T_OBJECT || right->type() == T_ARRAY) { | |
2516 r_lo = right->as_register(); | |
2517 } else { | |
2518 r_lo = right->as_register_lo(); | |
2519 } | |
2520 #else | |
0 | 2521 Register r_lo = right->as_register_lo(); |
2522 Register r_hi = right->as_register_hi(); | |
2523 assert(l_lo != r_hi, "overwriting registers"); | |
1572 | 2524 #endif |
0 | 2525 switch (code) { |
2526 case lir_logic_and: | |
304 | 2527 __ andptr(l_lo, r_lo); |
2528 NOT_LP64(__ andptr(l_hi, r_hi);) | |
0 | 2529 break; |
2530 case lir_logic_or: | |
304 | 2531 __ orptr(l_lo, r_lo); |
2532 NOT_LP64(__ orptr(l_hi, r_hi);) | |
0 | 2533 break; |
2534 case lir_logic_xor: | |
304 | 2535 __ xorptr(l_lo, r_lo); |
2536 NOT_LP64(__ xorptr(l_hi, r_hi);) | |
0 | 2537 break; |
2538 default: ShouldNotReachHere(); | |
2539 } | |
2540 } | |
2541 | |
2542 Register dst_lo = dst->as_register_lo(); | |
2543 Register dst_hi = dst->as_register_hi(); | |
2544 | |
304 | 2545 #ifdef _LP64 |
2546 move_regs(l_lo, dst_lo); | |
2547 #else | |
0 | 2548 if (dst_lo == l_hi) { |
2549 assert(dst_hi != l_lo, "overwriting registers"); | |
2550 move_regs(l_hi, dst_hi); | |
2551 move_regs(l_lo, dst_lo); | |
2552 } else { | |
2553 assert(dst_lo != l_hi, "overwriting registers"); | |
2554 move_regs(l_lo, dst_lo); | |
2555 move_regs(l_hi, dst_hi); | |
2556 } | |
304 | 2557 #endif // _LP64 |
0 | 2558 } |
2559 } | |
2560 | |
2561 | |
2562 // we assume that rax, and rdx can be overwritten | |
2563 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) { | |
2564 | |
2565 assert(left->is_single_cpu(), "left must be register"); | |
2566 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant"); | |
2567 assert(result->is_single_cpu(), "result must be register"); | |
2568 | |
2569 // assert(left->destroys_register(), "check"); | |
2570 // assert(right->destroys_register(), "check"); | |
2571 | |
2572 Register lreg = left->as_register(); | |
2573 Register dreg = result->as_register(); | |
2574 | |
2575 if (right->is_constant()) { | |
2576 int divisor = right->as_constant_ptr()->as_jint(); | |
2577 assert(divisor > 0 && is_power_of_2(divisor), "must be"); | |
2578 if (code == lir_idiv) { | |
2579 assert(lreg == rax, "must be rax,"); | |
2580 assert(temp->as_register() == rdx, "tmp register must be rdx"); | |
2581 __ cdql(); // sign extend into rdx:rax | |
2582 if (divisor == 2) { | |
2583 __ subl(lreg, rdx); | |
2584 } else { | |
2585 __ andl(rdx, divisor - 1); | |
2586 __ addl(lreg, rdx); | |
2587 } | |
2588 __ sarl(lreg, log2_intptr(divisor)); | |
2589 move_regs(lreg, dreg); | |
2590 } else if (code == lir_irem) { | |
2591 Label done; | |
304 | 2592 __ mov(dreg, lreg); |
0 | 2593 __ andl(dreg, 0x80000000 | (divisor - 1)); |
2594 __ jcc(Assembler::positive, done); | |
2595 __ decrement(dreg); | |
2596 __ orl(dreg, ~(divisor - 1)); | |
2597 __ increment(dreg); | |
2598 __ bind(done); | |
2599 } else { | |
2600 ShouldNotReachHere(); | |
2601 } | |
2602 } else { | |
2603 Register rreg = right->as_register(); | |
2604 assert(lreg == rax, "left register must be rax,"); | |
2605 assert(rreg != rdx, "right register must not be rdx"); | |
2606 assert(temp->as_register() == rdx, "tmp register must be rdx"); | |
2607 | |
2608 move_regs(lreg, rax); | |
2609 | |
2610 int idivl_offset = __ corrected_idivl(rreg); | |
2611 add_debug_info_for_div0(idivl_offset, info); | |
2612 if (code == lir_irem) { | |
2613 move_regs(rdx, dreg); // result is in rdx | |
2614 } else { | |
2615 move_regs(rax, dreg); | |
2616 } | |
2617 } | |
2618 } | |
2619 | |
2620 | |
2621 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) { | |
2622 if (opr1->is_single_cpu()) { | |
2623 Register reg1 = opr1->as_register(); | |
2624 if (opr2->is_single_cpu()) { | |
2625 // cpu register - cpu register | |
304 | 2626 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) { |
2627 __ cmpptr(reg1, opr2->as_register()); | |
2628 } else { | |
2629 assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY, "cmp int, oop?"); | |
2630 __ cmpl(reg1, opr2->as_register()); | |
2631 } | |
0 | 2632 } else if (opr2->is_stack()) { |
2633 // cpu register - stack | |
304 | 2634 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) { |
2635 __ cmpptr(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); | |
2636 } else { | |
2637 __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); | |
2638 } | |
0 | 2639 } else if (opr2->is_constant()) { |
2640 // cpu register - constant | |
2641 LIR_Const* c = opr2->as_constant_ptr(); | |
2642 if (c->type() == T_INT) { | |
2643 __ cmpl(reg1, c->as_jint()); | |
304 | 2644 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) { |
2645 // In 64bit oops are single register | |
0 | 2646 jobject o = c->as_jobject(); |
2647 if (o == NULL) { | |
304 | 2648 __ cmpptr(reg1, (int32_t)NULL_WORD); |
0 | 2649 } else { |
304 | 2650 #ifdef _LP64 |
2651 __ movoop(rscratch1, o); | |
2652 __ cmpptr(reg1, rscratch1); | |
2653 #else | |
0 | 2654 __ cmpoop(reg1, c->as_jobject()); |
304 | 2655 #endif // _LP64 |
0 | 2656 } |
2657 } else { | |
2658 ShouldNotReachHere(); | |
2659 } | |
2660 // cpu register - address | |
2661 } else if (opr2->is_address()) { | |
2662 if (op->info() != NULL) { | |
2663 add_debug_info_for_null_check_here(op->info()); | |
2664 } | |
2665 __ cmpl(reg1, as_Address(opr2->as_address_ptr())); | |
2666 } else { | |
2667 ShouldNotReachHere(); | |
2668 } | |
2669 | |
2670 } else if(opr1->is_double_cpu()) { | |
2671 Register xlo = opr1->as_register_lo(); | |
2672 Register xhi = opr1->as_register_hi(); | |
2673 if (opr2->is_double_cpu()) { | |
304 | 2674 #ifdef _LP64 |
2675 __ cmpptr(xlo, opr2->as_register_lo()); | |
2676 #else | |
0 | 2677 // cpu register - cpu register |
2678 Register ylo = opr2->as_register_lo(); | |
2679 Register yhi = opr2->as_register_hi(); | |
2680 __ subl(xlo, ylo); | |
2681 __ sbbl(xhi, yhi); | |
2682 if (condition == lir_cond_equal || condition == lir_cond_notEqual) { | |
2683 __ orl(xhi, xlo); | |
2684 } | |
304 | 2685 #endif // _LP64 |
0 | 2686 } else if (opr2->is_constant()) { |
2687 // cpu register - constant 0 | |
2688 assert(opr2->as_jlong() == (jlong)0, "only handles zero"); | |
304 | 2689 #ifdef _LP64 |
2690 __ cmpptr(xlo, (int32_t)opr2->as_jlong()); | |
2691 #else | |
0 | 2692 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles equals case"); |
2693 __ orl(xhi, xlo); | |
304 | 2694 #endif // _LP64 |
0 | 2695 } else { |
2696 ShouldNotReachHere(); | |
2697 } | |
2698 | |
2699 } else if (opr1->is_single_xmm()) { | |
2700 XMMRegister reg1 = opr1->as_xmm_float_reg(); | |
2701 if (opr2->is_single_xmm()) { | |
2702 // xmm register - xmm register | |
2703 __ ucomiss(reg1, opr2->as_xmm_float_reg()); | |
2704 } else if (opr2->is_stack()) { | |
2705 // xmm register - stack | |
2706 __ ucomiss(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); | |
2707 } else if (opr2->is_constant()) { | |
2708 // xmm register - constant | |
2709 __ ucomiss(reg1, InternalAddress(float_constant(opr2->as_jfloat()))); | |
2710 } else if (opr2->is_address()) { | |
2711 // xmm register - address | |
2712 if (op->info() != NULL) { | |
2713 add_debug_info_for_null_check_here(op->info()); | |
2714 } | |
2715 __ ucomiss(reg1, as_Address(opr2->as_address_ptr())); | |
2716 } else { | |
2717 ShouldNotReachHere(); | |
2718 } | |
2719 | |
2720 } else if (opr1->is_double_xmm()) { | |
2721 XMMRegister reg1 = opr1->as_xmm_double_reg(); | |
2722 if (opr2->is_double_xmm()) { | |
2723 // xmm register - xmm register | |
2724 __ ucomisd(reg1, opr2->as_xmm_double_reg()); | |
2725 } else if (opr2->is_stack()) { | |
2726 // xmm register - stack | |
2727 __ ucomisd(reg1, frame_map()->address_for_slot(opr2->double_stack_ix())); | |
2728 } else if (opr2->is_constant()) { | |
2729 // xmm register - constant | |
2730 __ ucomisd(reg1, InternalAddress(double_constant(opr2->as_jdouble()))); | |
2731 } else if (opr2->is_address()) { | |
2732 // xmm register - address | |
2733 if (op->info() != NULL) { | |
2734 add_debug_info_for_null_check_here(op->info()); | |
2735 } | |
2736 __ ucomisd(reg1, as_Address(opr2->pointer()->as_address())); | |
2737 } else { | |
2738 ShouldNotReachHere(); | |
2739 } | |
2740 | |
2741 } else if(opr1->is_single_fpu() || opr1->is_double_fpu()) { | |
2742 assert(opr1->is_fpu_register() && opr1->fpu() == 0, "currently left-hand side must be on TOS (relax this restriction)"); | |
2743 assert(opr2->is_fpu_register(), "both must be registers"); | |
2744 __ fcmp(noreg, opr2->fpu(), op->fpu_pop_count() > 0, op->fpu_pop_count() > 1); | |
2745 | |
2746 } else if (opr1->is_address() && opr2->is_constant()) { | |
304 | 2747 LIR_Const* c = opr2->as_constant_ptr(); |
2748 #ifdef _LP64 | |
2749 if (c->type() == T_OBJECT || c->type() == T_ARRAY) { | |
2750 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse"); | |
2751 __ movoop(rscratch1, c->as_jobject()); | |
2752 } | |
2753 #endif // LP64 | |
0 | 2754 if (op->info() != NULL) { |
2755 add_debug_info_for_null_check_here(op->info()); | |
2756 } | |
2757 // special case: address - constant | |
2758 LIR_Address* addr = opr1->as_address_ptr(); | |
2759 if (c->type() == T_INT) { | |
2760 __ cmpl(as_Address(addr), c->as_jint()); | |
304 | 2761 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) { |
2762 #ifdef _LP64 | |
2763 // %%% Make this explode if addr isn't reachable until we figure out a | |
2764 // better strategy by giving noreg as the temp for as_Address | |
2765 __ cmpptr(rscratch1, as_Address(addr, noreg)); | |
2766 #else | |
0 | 2767 __ cmpoop(as_Address(addr), c->as_jobject()); |
304 | 2768 #endif // _LP64 |
0 | 2769 } else { |
2770 ShouldNotReachHere(); | |
2771 } | |
2772 | |
2773 } else { | |
2774 ShouldNotReachHere(); | |
2775 } | |
2776 } | |
2777 | |
2778 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) { | |
2779 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) { | |
2780 if (left->is_single_xmm()) { | |
2781 assert(right->is_single_xmm(), "must match"); | |
2782 __ cmpss2int(left->as_xmm_float_reg(), right->as_xmm_float_reg(), dst->as_register(), code == lir_ucmp_fd2i); | |
2783 } else if (left->is_double_xmm()) { | |
2784 assert(right->is_double_xmm(), "must match"); | |
2785 __ cmpsd2int(left->as_xmm_double_reg(), right->as_xmm_double_reg(), dst->as_register(), code == lir_ucmp_fd2i); | |
2786 | |
2787 } else { | |
2788 assert(left->is_single_fpu() || left->is_double_fpu(), "must be"); | |
2789 assert(right->is_single_fpu() || right->is_double_fpu(), "must match"); | |
2790 | |
2791 assert(left->fpu() == 0, "left must be on TOS"); | |
2792 __ fcmp2int(dst->as_register(), code == lir_ucmp_fd2i, right->fpu(), | |
2793 op->fpu_pop_count() > 0, op->fpu_pop_count() > 1); | |
2794 } | |
2795 } else { | |
2796 assert(code == lir_cmp_l2i, "check"); | |
304 | 2797 #ifdef _LP64 |
1369 | 2798 Label done; |
2799 Register dest = dst->as_register(); | |
2800 __ cmpptr(left->as_register_lo(), right->as_register_lo()); | |
2801 __ movl(dest, -1); | |
2802 __ jccb(Assembler::less, done); | |
2803 __ set_byte_if_not_zero(dest); | |
2804 __ movzbl(dest, dest); | |
2805 __ bind(done); | |
304 | 2806 #else |
0 | 2807 __ lcmp2int(left->as_register_hi(), |
2808 left->as_register_lo(), | |
2809 right->as_register_hi(), | |
2810 right->as_register_lo()); | |
2811 move_regs(left->as_register_hi(), dst->as_register()); | |
304 | 2812 #endif // _LP64 |
0 | 2813 } |
2814 } | |
2815 | |
2816 | |
2817 void LIR_Assembler::align_call(LIR_Code code) { | |
2818 if (os::is_MP()) { | |
2819 // make sure that the displacement word of the call ends up word aligned | |
2820 int offset = __ offset(); | |
2821 switch (code) { | |
2822 case lir_static_call: | |
2823 case lir_optvirtual_call: | |
1295 | 2824 case lir_dynamic_call: |
0 | 2825 offset += NativeCall::displacement_offset; |
2826 break; | |
2827 case lir_icvirtual_call: | |
2828 offset += NativeCall::displacement_offset + NativeMovConstReg::instruction_size; | |
2829 break; | |
2830 case lir_virtual_call: // currently, sparc-specific for niagara | |
2831 default: ShouldNotReachHere(); | |
2832 } | |
2833 while (offset++ % BytesPerWord != 0) { | |
2834 __ nop(); | |
2835 } | |
2836 } | |
2837 } | |
2838 | |
2839 | |
1295 | 2840 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) { |
0 | 2841 assert(!os::is_MP() || (__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0, |
2842 "must be aligned"); | |
1295 | 2843 __ call(AddressLiteral(op->addr(), rtype)); |
1564 | 2844 add_call_info(code_offset(), op->info()); |
0 | 2845 } |
2846 | |
2847 | |
1295 | 2848 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) { |
0 | 2849 RelocationHolder rh = virtual_call_Relocation::spec(pc()); |
2850 __ movoop(IC_Klass, (jobject)Universe::non_oop_word()); | |
2851 assert(!os::is_MP() || | |
2852 (__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0, | |
2853 "must be aligned"); | |
1295 | 2854 __ call(AddressLiteral(op->addr(), rh)); |
1564 | 2855 add_call_info(code_offset(), op->info()); |
0 | 2856 } |
2857 | |
2858 | |
2859 /* Currently, vtable-dispatch is only enabled for sparc platforms */ | |
1295 | 2860 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) { |
0 | 2861 ShouldNotReachHere(); |
2862 } | |
2863 | |
1295 | 2864 |
0 | 2865 void LIR_Assembler::emit_static_call_stub() { |
2866 address call_pc = __ pc(); | |
2867 address stub = __ start_a_stub(call_stub_size); | |
2868 if (stub == NULL) { | |
2869 bailout("static call stub overflow"); | |
2870 return; | |
2871 } | |
2872 | |
2873 int start = __ offset(); | |
2874 if (os::is_MP()) { | |
2875 // make sure that the displacement word of the call ends up word aligned | |
2876 int offset = __ offset() + NativeMovConstReg::instruction_size + NativeCall::displacement_offset; | |
2877 while (offset++ % BytesPerWord != 0) { | |
2878 __ nop(); | |
2879 } | |
2880 } | |
2881 __ relocate(static_stub_Relocation::spec(call_pc)); | |
2882 __ movoop(rbx, (jobject)NULL); | |
2883 // must be set to -1 at code generation time | |
2884 assert(!os::is_MP() || ((__ offset() + 1) % BytesPerWord) == 0, "must be aligned on MP"); | |
304 | 2885 // On 64bit this will die since it will take a movq & jmp, must be only a jmp |
2886 __ jump(RuntimeAddress(__ pc())); | |
0 | 2887 |
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2888 assert(__ offset() - start <= call_stub_size, "stub too big"); |
0 | 2889 __ end_a_stub(); |
2890 } | |
2891 | |
2892 | |
1378
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2893 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) { |
0 | 2894 assert(exceptionOop->as_register() == rax, "must match"); |
1378
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2895 assert(exceptionPC->as_register() == rdx, "must match"); |
0 | 2896 |
2897 // exception object is not added to oop map by LinearScan | |
2898 // (LinearScan assumes that no oops are in fixed registers) | |
2899 info->add_register_oop(exceptionOop); | |
2900 Runtime1::StubID unwind_id; | |
2901 | |
1378
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2902 // get current pc information |
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2903 // pc is only needed if the method has an exception handler, the unwind code does not need it. |
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2904 int pc_for_athrow_offset = __ offset(); |
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2905 InternalAddress pc_for_athrow(__ pc()); |
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2906 __ lea(exceptionPC->as_register(), pc_for_athrow); |
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2907 add_call_info(pc_for_athrow_offset, info); // for exception handler |
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2908 |
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2909 __ verify_not_null_oop(rax); |
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2910 // search an exception handler (rax: exception oop, rdx: throwing pc) |
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2911 if (compilation()->has_fpu_code()) { |
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2912 unwind_id = Runtime1::handle_exception_id; |
0 | 2913 } else { |
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2914 unwind_id = Runtime1::handle_exception_nofpu_id; |
0 | 2915 } |
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2916 __ call(RuntimeAddress(Runtime1::entry_for(unwind_id))); |
0 | 2917 |
2918 // enough room for two byte trap | |
2919 __ nop(); | |
2920 } | |
2921 | |
2922 | |
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2923 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) { |
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2924 assert(exceptionOop->as_register() == rax, "must match"); |
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2925 |
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2926 __ jmp(_unwind_handler_entry); |
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2927 } |
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2928 |
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2929 |
0 | 2930 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) { |
2931 | |
2932 // optimized version for linear scan: | |
2933 // * count must be already in ECX (guaranteed by LinearScan) | |
2934 // * left and dest must be equal | |
2935 // * tmp must be unused | |
2936 assert(count->as_register() == SHIFT_count, "count must be in ECX"); | |
2937 assert(left == dest, "left and dest must be equal"); | |
2938 assert(tmp->is_illegal(), "wasting a register if tmp is allocated"); | |
2939 | |
2940 if (left->is_single_cpu()) { | |
2941 Register value = left->as_register(); | |
2942 assert(value != SHIFT_count, "left cannot be ECX"); | |
2943 | |
2944 switch (code) { | |
2945 case lir_shl: __ shll(value); break; | |
2946 case lir_shr: __ sarl(value); break; | |
2947 case lir_ushr: __ shrl(value); break; | |
2948 default: ShouldNotReachHere(); | |
2949 } | |
2950 } else if (left->is_double_cpu()) { | |
2951 Register lo = left->as_register_lo(); | |
2952 Register hi = left->as_register_hi(); | |
2953 assert(lo != SHIFT_count && hi != SHIFT_count, "left cannot be ECX"); | |
304 | 2954 #ifdef _LP64 |
2955 switch (code) { | |
2956 case lir_shl: __ shlptr(lo); break; | |
2957 case lir_shr: __ sarptr(lo); break; | |
2958 case lir_ushr: __ shrptr(lo); break; | |
2959 default: ShouldNotReachHere(); | |
2960 } | |
2961 #else | |
0 | 2962 |
2963 switch (code) { | |
2964 case lir_shl: __ lshl(hi, lo); break; | |
2965 case lir_shr: __ lshr(hi, lo, true); break; | |
2966 case lir_ushr: __ lshr(hi, lo, false); break; | |
2967 default: ShouldNotReachHere(); | |
2968 } | |
304 | 2969 #endif // LP64 |
0 | 2970 } else { |
2971 ShouldNotReachHere(); | |
2972 } | |
2973 } | |
2974 | |
2975 | |
2976 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) { | |
2977 if (dest->is_single_cpu()) { | |
2978 // first move left into dest so that left is not destroyed by the shift | |
2979 Register value = dest->as_register(); | |
2980 count = count & 0x1F; // Java spec | |
2981 | |
2982 move_regs(left->as_register(), value); | |
2983 switch (code) { | |
2984 case lir_shl: __ shll(value, count); break; | |
2985 case lir_shr: __ sarl(value, count); break; | |
2986 case lir_ushr: __ shrl(value, count); break; | |
2987 default: ShouldNotReachHere(); | |
2988 } | |
2989 } else if (dest->is_double_cpu()) { | |
304 | 2990 #ifndef _LP64 |
0 | 2991 Unimplemented(); |
304 | 2992 #else |
2993 // first move left into dest so that left is not destroyed by the shift | |
2994 Register value = dest->as_register_lo(); | |
2995 count = count & 0x1F; // Java spec | |
2996 | |
2997 move_regs(left->as_register_lo(), value); | |
2998 switch (code) { | |
2999 case lir_shl: __ shlptr(value, count); break; | |
3000 case lir_shr: __ sarptr(value, count); break; | |
3001 case lir_ushr: __ shrptr(value, count); break; | |
3002 default: ShouldNotReachHere(); | |
3003 } | |
3004 #endif // _LP64 | |
0 | 3005 } else { |
3006 ShouldNotReachHere(); | |
3007 } | |
3008 } | |
3009 | |
3010 | |
3011 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) { | |
3012 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); | |
3013 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; | |
3014 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); | |
304 | 3015 __ movptr (Address(rsp, offset_from_rsp_in_bytes), r); |
0 | 3016 } |
3017 | |
3018 | |
3019 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) { | |
3020 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); | |
3021 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; | |
3022 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); | |
304 | 3023 __ movptr (Address(rsp, offset_from_rsp_in_bytes), c); |
0 | 3024 } |
3025 | |
3026 | |
3027 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) { | |
3028 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); | |
3029 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; | |
3030 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); | |
3031 __ movoop (Address(rsp, offset_from_rsp_in_bytes), o); | |
3032 } | |
3033 | |
3034 | |
3035 // This code replaces a call to arraycopy; no exception may | |
3036 // be thrown in this code, they must be thrown in the System.arraycopy | |
3037 // activation frame; we could save some checks if this would not be the case | |
3038 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) { | |
3039 ciArrayKlass* default_type = op->expected_type(); | |
3040 Register src = op->src()->as_register(); | |
3041 Register dst = op->dst()->as_register(); | |
3042 Register src_pos = op->src_pos()->as_register(); | |
3043 Register dst_pos = op->dst_pos()->as_register(); | |
3044 Register length = op->length()->as_register(); | |
3045 Register tmp = op->tmp()->as_register(); | |
3046 | |
3047 CodeStub* stub = op->stub(); | |
3048 int flags = op->flags(); | |
3049 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL; | |
3050 if (basic_type == T_ARRAY) basic_type = T_OBJECT; | |
3051 | |
2446 | 3052 // if we don't know anything, just go through the generic arraycopy |
0 | 3053 if (default_type == NULL) { |
3054 Label done; | |
3055 // save outgoing arguments on stack in case call to System.arraycopy is needed | |
3056 // HACK ALERT. This code used to push the parameters in a hardwired fashion | |
3057 // for interpreter calling conventions. Now we have to do it in new style conventions. | |
3058 // For the moment until C1 gets the new register allocator I just force all the | |
3059 // args to the right place (except the register args) and then on the back side | |
3060 // reload the register args properly if we go slow path. Yuck | |
3061 | |
3062 // These are proper for the calling convention | |
3063 store_parameter(length, 2); | |
3064 store_parameter(dst_pos, 1); | |
3065 store_parameter(dst, 0); | |
3066 | |
3067 // these are just temporary placements until we need to reload | |
3068 store_parameter(src_pos, 3); | |
3069 store_parameter(src, 4); | |
304 | 3070 NOT_LP64(assert(src == rcx && src_pos == rdx, "mismatch in calling convention");) |
3071 | |
2446 | 3072 address C_entry = CAST_FROM_FN_PTR(address, Runtime1::arraycopy); |
3073 | |
3074 address copyfunc_addr = StubRoutines::generic_arraycopy(); | |
0 | 3075 |
3076 // pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint | |
304 | 3077 #ifdef _LP64 |
3078 // The arguments are in java calling convention so we can trivially shift them to C | |
3079 // convention | |
3080 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4); | |
3081 __ mov(c_rarg0, j_rarg0); | |
3082 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4); | |
3083 __ mov(c_rarg1, j_rarg1); | |
3084 assert_different_registers(c_rarg2, j_rarg3, j_rarg4); | |
3085 __ mov(c_rarg2, j_rarg2); | |
3086 assert_different_registers(c_rarg3, j_rarg4); | |
3087 __ mov(c_rarg3, j_rarg3); | |
3088 #ifdef _WIN64 | |
3089 // Allocate abi space for args but be sure to keep stack aligned | |
3090 __ subptr(rsp, 6*wordSize); | |
3091 store_parameter(j_rarg4, 4); | |
2446 | 3092 if (copyfunc_addr == NULL) { // Use C version if stub was not generated |
3093 __ call(RuntimeAddress(C_entry)); | |
3094 } else { | |
3095 #ifndef PRODUCT | |
3096 if (PrintC1Statistics) { | |
3097 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt)); | |
3098 } | |
3099 #endif | |
3100 __ call(RuntimeAddress(copyfunc_addr)); | |
3101 } | |
304 | 3102 __ addptr(rsp, 6*wordSize); |
3103 #else | |
3104 __ mov(c_rarg4, j_rarg4); | |
2446 | 3105 if (copyfunc_addr == NULL) { // Use C version if stub was not generated |
3106 __ call(RuntimeAddress(C_entry)); | |
3107 } else { | |
3108 #ifndef PRODUCT | |
3109 if (PrintC1Statistics) { | |
3110 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt)); | |
3111 } | |
3112 #endif | |
3113 __ call(RuntimeAddress(copyfunc_addr)); | |
3114 } | |
304 | 3115 #endif // _WIN64 |
3116 #else | |
3117 __ push(length); | |
3118 __ push(dst_pos); | |
3119 __ push(dst); | |
3120 __ push(src_pos); | |
3121 __ push(src); | |
2446 | 3122 |
3123 if (copyfunc_addr == NULL) { // Use C version if stub was not generated | |
3124 __ call_VM_leaf(C_entry, 5); // removes pushed parameter from the stack | |
3125 } else { | |
3126 #ifndef PRODUCT | |
3127 if (PrintC1Statistics) { | |
3128 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt)); | |
3129 } | |
3130 #endif | |
3131 __ call_VM_leaf(copyfunc_addr, 5); // removes pushed parameter from the stack | |
3132 } | |
0 | 3133 |
304 | 3134 #endif // _LP64 |
3135 | |
0 | 3136 __ cmpl(rax, 0); |
3137 __ jcc(Assembler::equal, *stub->continuation()); | |
3138 | |
2446 | 3139 if (copyfunc_addr != NULL) { |
3140 __ mov(tmp, rax); | |
3141 __ xorl(tmp, -1); | |
3142 } | |
3143 | |
0 | 3144 // Reload values from the stack so they are where the stub |
3145 // expects them. | |
304 | 3146 __ movptr (dst, Address(rsp, 0*BytesPerWord)); |
3147 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord)); | |
3148 __ movptr (length, Address(rsp, 2*BytesPerWord)); | |
3149 __ movptr (src_pos, Address(rsp, 3*BytesPerWord)); | |
3150 __ movptr (src, Address(rsp, 4*BytesPerWord)); | |
2446 | 3151 |
3152 if (copyfunc_addr != NULL) { | |
3153 __ subl(length, tmp); | |
3154 __ addl(src_pos, tmp); | |
3155 __ addl(dst_pos, tmp); | |
3156 } | |
0 | 3157 __ jmp(*stub->entry()); |
3158 | |
3159 __ bind(*stub->continuation()); | |
3160 return; | |
3161 } | |
3162 | |
3163 assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point"); | |
3164 | |
29
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3165 int elem_size = type2aelembytes(basic_type); |
0 | 3166 int shift_amount; |
3167 Address::ScaleFactor scale; | |
3168 | |
3169 switch (elem_size) { | |
3170 case 1 : | |
3171 shift_amount = 0; | |
3172 scale = Address::times_1; | |
3173 break; | |
3174 case 2 : | |
3175 shift_amount = 1; | |
3176 scale = Address::times_2; | |
3177 break; | |
3178 case 4 : | |
3179 shift_amount = 2; | |
3180 scale = Address::times_4; | |
3181 break; | |
3182 case 8 : | |
3183 shift_amount = 3; | |
3184 scale = Address::times_8; | |
3185 break; | |
3186 default: | |
3187 ShouldNotReachHere(); | |
3188 } | |
3189 | |
3190 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes()); | |
3191 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes()); | |
3192 Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes()); | |
3193 Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes()); | |
3194 | |
304 | 3195 // length and pos's are all sign extended at this point on 64bit |
3196 | |
0 | 3197 // test for NULL |
3198 if (flags & LIR_OpArrayCopy::src_null_check) { | |
304 | 3199 __ testptr(src, src); |
0 | 3200 __ jcc(Assembler::zero, *stub->entry()); |
3201 } | |
3202 if (flags & LIR_OpArrayCopy::dst_null_check) { | |
304 | 3203 __ testptr(dst, dst); |
0 | 3204 __ jcc(Assembler::zero, *stub->entry()); |
3205 } | |
3206 | |
3207 // check if negative | |
3208 if (flags & LIR_OpArrayCopy::src_pos_positive_check) { | |
3209 __ testl(src_pos, src_pos); | |
3210 __ jcc(Assembler::less, *stub->entry()); | |
3211 } | |
3212 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) { | |
3213 __ testl(dst_pos, dst_pos); | |
3214 __ jcc(Assembler::less, *stub->entry()); | |
3215 } | |
3216 | |
3217 if (flags & LIR_OpArrayCopy::src_range_check) { | |
304 | 3218 __ lea(tmp, Address(src_pos, length, Address::times_1, 0)); |
0 | 3219 __ cmpl(tmp, src_length_addr); |
3220 __ jcc(Assembler::above, *stub->entry()); | |
3221 } | |
3222 if (flags & LIR_OpArrayCopy::dst_range_check) { | |
304 | 3223 __ lea(tmp, Address(dst_pos, length, Address::times_1, 0)); |
0 | 3224 __ cmpl(tmp, dst_length_addr); |
3225 __ jcc(Assembler::above, *stub->entry()); | |
3226 } | |
3227 | |
2446 | 3228 if (flags & LIR_OpArrayCopy::length_positive_check) { |
3229 __ testl(length, length); | |
3230 __ jcc(Assembler::less, *stub->entry()); | |
3231 __ jcc(Assembler::zero, *stub->continuation()); | |
3232 } | |
3233 | |
3234 #ifdef _LP64 | |
3235 __ movl2ptr(src_pos, src_pos); //higher 32bits must be null | |
3236 __ movl2ptr(dst_pos, dst_pos); //higher 32bits must be null | |
3237 #endif | |
3238 | |
0 | 3239 if (flags & LIR_OpArrayCopy::type_check) { |
2446 | 3240 // We don't know the array types are compatible |
3241 if (basic_type != T_OBJECT) { | |
3242 // Simple test for basic type arrays | |
3243 if (UseCompressedOops) { | |
3244 __ movl(tmp, src_klass_addr); | |
3245 __ cmpl(tmp, dst_klass_addr); | |
3246 } else { | |
3247 __ movptr(tmp, src_klass_addr); | |
3248 __ cmpptr(tmp, dst_klass_addr); | |
3249 } | |
3250 __ jcc(Assembler::notEqual, *stub->entry()); | |
2002 | 3251 } else { |
2446 | 3252 // For object arrays, if src is a sub class of dst then we can |
3253 // safely do the copy. | |
3254 Label cont, slow; | |
3255 | |
3256 __ push(src); | |
3257 __ push(dst); | |
3258 | |
3259 __ load_klass(src, src); | |
3260 __ load_klass(dst, dst); | |
3261 | |
3262 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, NULL); | |
3263 | |
3264 __ push(src); | |
3265 __ push(dst); | |
3266 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); | |
3267 __ pop(dst); | |
3268 __ pop(src); | |
3269 | |
3270 __ cmpl(src, 0); | |
3271 __ jcc(Assembler::notEqual, cont); | |
3272 | |
3273 __ bind(slow); | |
3274 __ pop(dst); | |
3275 __ pop(src); | |
3276 | |
3277 address copyfunc_addr = StubRoutines::checkcast_arraycopy(); | |
3278 if (copyfunc_addr != NULL) { // use stub if available | |
3279 // src is not a sub class of dst so we have to do a | |
3280 // per-element check. | |
3281 | |
3282 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray; | |
3283 if ((flags & mask) != mask) { | |
3284 // Check that at least both of them object arrays. | |
3285 assert(flags & mask, "one of the two should be known to be an object array"); | |
3286 | |
3287 if (!(flags & LIR_OpArrayCopy::src_objarray)) { | |
3288 __ load_klass(tmp, src); | |
3289 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) { | |
3290 __ load_klass(tmp, dst); | |
3291 } | |
3292 int lh_offset = klassOopDesc::header_size() * HeapWordSize + | |
3293 Klass::layout_helper_offset_in_bytes(); | |
3294 Address klass_lh_addr(tmp, lh_offset); | |
3295 jint objArray_lh = Klass::array_layout_helper(T_OBJECT); | |
3296 __ cmpl(klass_lh_addr, objArray_lh); | |
3297 __ jcc(Assembler::notEqual, *stub->entry()); | |
3298 } | |
3299 | |
3739
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3300 // Spill because stubs can use any register they like and it's |
28263a73ebfb
7047491: C1: registers saved incorrectly when calling checkcast_arraycopy stub
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3301 // easier to restore just those that we care about. |
28263a73ebfb
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diff
changeset
|
3302 store_parameter(dst, 0); |
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7047491: C1: registers saved incorrectly when calling checkcast_arraycopy stub
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diff
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|
3303 store_parameter(dst_pos, 1); |
28263a73ebfb
7047491: C1: registers saved incorrectly when calling checkcast_arraycopy stub
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3401
diff
changeset
|
3304 store_parameter(length, 2); |
28263a73ebfb
7047491: C1: registers saved incorrectly when calling checkcast_arraycopy stub
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diff
changeset
|
3305 store_parameter(src_pos, 3); |
28263a73ebfb
7047491: C1: registers saved incorrectly when calling checkcast_arraycopy stub
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diff
changeset
|
3306 store_parameter(src, 4); |
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7047491: C1: registers saved incorrectly when calling checkcast_arraycopy stub
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|
3307 |
2446 | 3308 #ifndef _LP64 |
3309 __ movptr(tmp, dst_klass_addr); | |
3310 __ movptr(tmp, Address(tmp, objArrayKlass::element_klass_offset_in_bytes() + sizeof(oopDesc))); | |
3311 __ push(tmp); | |
3312 __ movl(tmp, Address(tmp, Klass::super_check_offset_offset_in_bytes() + sizeof(oopDesc))); | |
3313 __ push(tmp); | |
3314 __ push(length); | |
3315 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); | |
3316 __ push(tmp); | |
3317 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); | |
3318 __ push(tmp); | |
3319 | |
3320 __ call_VM_leaf(copyfunc_addr, 5); | |
3321 #else | |
3322 __ movl2ptr(length, length); //higher 32bits must be null | |
3323 | |
3324 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); | |
3325 assert_different_registers(c_rarg0, dst, dst_pos, length); | |
3326 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); | |
3327 assert_different_registers(c_rarg1, dst, length); | |
3328 | |
3329 __ mov(c_rarg2, length); | |
3330 assert_different_registers(c_rarg2, dst); | |
3331 | |
3332 #ifdef _WIN64 | |
3333 // Allocate abi space for args but be sure to keep stack aligned | |
3334 __ subptr(rsp, 6*wordSize); | |
3335 __ load_klass(c_rarg3, dst); | |
3336 __ movptr(c_rarg3, Address(c_rarg3, objArrayKlass::element_klass_offset_in_bytes() + sizeof(oopDesc))); | |
3337 store_parameter(c_rarg3, 4); | |
3338 __ movl(c_rarg3, Address(c_rarg3, Klass::super_check_offset_offset_in_bytes() + sizeof(oopDesc))); | |
3339 __ call(RuntimeAddress(copyfunc_addr)); | |
3340 __ addptr(rsp, 6*wordSize); | |
3341 #else | |
3342 __ load_klass(c_rarg4, dst); | |
3343 __ movptr(c_rarg4, Address(c_rarg4, objArrayKlass::element_klass_offset_in_bytes() + sizeof(oopDesc))); | |
3344 __ movl(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset_in_bytes() + sizeof(oopDesc))); | |
3345 __ call(RuntimeAddress(copyfunc_addr)); | |
3346 #endif | |
3347 | |
3348 #endif | |
3349 | |
3350 #ifndef PRODUCT | |
3351 if (PrintC1Statistics) { | |
3352 Label failed; | |
3353 __ testl(rax, rax); | |
3354 __ jcc(Assembler::notZero, failed); | |
3355 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt)); | |
3356 __ bind(failed); | |
3357 } | |
3358 #endif | |
3359 | |
3360 __ testl(rax, rax); | |
3361 __ jcc(Assembler::zero, *stub->continuation()); | |
3362 | |
3363 #ifndef PRODUCT | |
3364 if (PrintC1Statistics) { | |
3365 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt)); | |
3366 } | |
3367 #endif | |
3368 | |
3369 __ mov(tmp, rax); | |
3370 | |
3371 __ xorl(tmp, -1); | |
3372 | |
3739
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7047491: C1: registers saved incorrectly when calling checkcast_arraycopy stub
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3401
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|
3373 // Restore previously spilled arguments |
28263a73ebfb
7047491: C1: registers saved incorrectly when calling checkcast_arraycopy stub
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3401
diff
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|
3374 __ movptr (dst, Address(rsp, 0*BytesPerWord)); |
28263a73ebfb
7047491: C1: registers saved incorrectly when calling checkcast_arraycopy stub
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diff
changeset
|
3375 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord)); |
28263a73ebfb
7047491: C1: registers saved incorrectly when calling checkcast_arraycopy stub
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|
3376 __ movptr (length, Address(rsp, 2*BytesPerWord)); |
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7047491: C1: registers saved incorrectly when calling checkcast_arraycopy stub
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|
3377 __ movptr (src_pos, Address(rsp, 3*BytesPerWord)); |
28263a73ebfb
7047491: C1: registers saved incorrectly when calling checkcast_arraycopy stub
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diff
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|
3378 __ movptr (src, Address(rsp, 4*BytesPerWord)); |
28263a73ebfb
7047491: C1: registers saved incorrectly when calling checkcast_arraycopy stub
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3401
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|
3379 |
2446 | 3380 |
3381 __ subl(length, tmp); | |
3382 __ addl(src_pos, tmp); | |
3383 __ addl(dst_pos, tmp); | |
3384 } | |
3385 | |
3386 __ jmp(*stub->entry()); | |
3387 | |
3388 __ bind(cont); | |
3389 __ pop(dst); | |
3390 __ pop(src); | |
2002 | 3391 } |
0 | 3392 } |
3393 | |
3394 #ifdef ASSERT | |
3395 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) { | |
3396 // Sanity check the known type with the incoming class. For the | |
3397 // primitive case the types must match exactly with src.klass and | |
3398 // dst.klass each exactly matching the default type. For the | |
3399 // object array case, if no type check is needed then either the | |
3400 // dst type is exactly the expected type and the src type is a | |
3401 // subtype which we can't check or src is the same array as dst | |
3402 // but not necessarily exactly of type default_type. | |
3403 Label known_ok, halt; | |
989
148e5441d916
6863023: need non-perm oops in code cache for JSR 292
jrose
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780
diff
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|
3404 __ movoop(tmp, default_type->constant_encoding()); |
2002 | 3405 #ifdef _LP64 |
3406 if (UseCompressedOops) { | |
3407 __ encode_heap_oop(tmp); | |
3408 } | |
3409 #endif | |
3410 | |
0 | 3411 if (basic_type != T_OBJECT) { |
2002 | 3412 |
3413 if (UseCompressedOops) __ cmpl(tmp, dst_klass_addr); | |
3414 else __ cmpptr(tmp, dst_klass_addr); | |
0 | 3415 __ jcc(Assembler::notEqual, halt); |
2002 | 3416 if (UseCompressedOops) __ cmpl(tmp, src_klass_addr); |
3417 else __ cmpptr(tmp, src_klass_addr); | |
0 | 3418 __ jcc(Assembler::equal, known_ok); |
3419 } else { | |
2002 | 3420 if (UseCompressedOops) __ cmpl(tmp, dst_klass_addr); |
3421 else __ cmpptr(tmp, dst_klass_addr); | |
0 | 3422 __ jcc(Assembler::equal, known_ok); |
304 | 3423 __ cmpptr(src, dst); |
0 | 3424 __ jcc(Assembler::equal, known_ok); |
3425 } | |
3426 __ bind(halt); | |
3427 __ stop("incorrect type information in arraycopy"); | |
3428 __ bind(known_ok); | |
3429 } | |
3430 #endif | |
3431 | |
2446 | 3432 #ifndef PRODUCT |
3433 if (PrintC1Statistics) { | |
3434 __ incrementl(ExternalAddress(Runtime1::arraycopy_count_address(basic_type))); | |
304 | 3435 } |
2446 | 3436 #endif |
304 | 3437 |
3438 #ifdef _LP64 | |
3439 assert_different_registers(c_rarg0, dst, dst_pos, length); | |
3440 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); | |
3441 assert_different_registers(c_rarg1, length); | |
3442 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); | |
3443 __ mov(c_rarg2, length); | |
3444 | |
3445 #else | |
3446 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); | |
0 | 3447 store_parameter(tmp, 0); |
304 | 3448 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); |
0 | 3449 store_parameter(tmp, 1); |
3450 store_parameter(length, 2); | |
304 | 3451 #endif // _LP64 |
2446 | 3452 |
3453 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0; | |
3454 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0; | |
3455 const char *name; | |
3456 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false); | |
3457 __ call_VM_leaf(entry, 0); | |
0 | 3458 |
3459 __ bind(*stub->continuation()); | |
3460 } | |
3461 | |
3462 | |
3463 void LIR_Assembler::emit_lock(LIR_OpLock* op) { | |
3464 Register obj = op->obj_opr()->as_register(); // may not be an oop | |
3465 Register hdr = op->hdr_opr()->as_register(); | |
3466 Register lock = op->lock_opr()->as_register(); | |
3467 if (!UseFastLocking) { | |
3468 __ jmp(*op->stub()->entry()); | |
3469 } else if (op->code() == lir_lock) { | |
3470 Register scratch = noreg; | |
3471 if (UseBiasedLocking) { | |
3472 scratch = op->scratch_opr()->as_register(); | |
3473 } | |
3474 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); | |
3475 // add debug info for NullPointerException only if one is possible | |
3476 int null_check_offset = __ lock_object(hdr, obj, lock, scratch, *op->stub()->entry()); | |
3477 if (op->info() != NULL) { | |
3478 add_debug_info_for_null_check(null_check_offset, op->info()); | |
3479 } | |
3480 // done | |
3481 } else if (op->code() == lir_unlock) { | |
3482 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); | |
3483 __ unlock_object(hdr, obj, lock, *op->stub()->entry()); | |
3484 } else { | |
3485 Unimplemented(); | |
3486 } | |
3487 __ bind(*op->stub()->continuation()); | |
3488 } | |
3489 | |
3490 | |
3491 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) { | |
3492 ciMethod* method = op->profiled_method(); | |
3493 int bci = op->profiled_bci(); | |
3494 | |
3495 // Update counter for all call types | |
2007
5ddfcf4b079e
7003554: (tiered) assert(is_null_object() || handle() != NULL) failed: cannot embed null pointer
iveresov
parents:
2002
diff
changeset
|
3496 ciMethodData* md = method->method_data_or_null(); |
5ddfcf4b079e
7003554: (tiered) assert(is_null_object() || handle() != NULL) failed: cannot embed null pointer
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parents:
2002
diff
changeset
|
3497 assert(md != NULL, "Sanity"); |
0 | 3498 ciProfileData* data = md->bci_to_data(bci); |
3499 assert(data->is_CounterData(), "need CounterData for calls"); | |
3500 assert(op->mdo()->is_single_cpu(), "mdo must be allocated"); | |
3501 Register mdo = op->mdo()->as_register(); | |
989
148e5441d916
6863023: need non-perm oops in code cache for JSR 292
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parents:
780
diff
changeset
|
3502 __ movoop(mdo, md->constant_encoding()); |
0 | 3503 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); |
3504 Bytecodes::Code bc = method->java_code_at_bci(bci); | |
3505 // Perform additional virtual call profiling for invokevirtual and | |
3506 // invokeinterface bytecodes | |
3507 if ((bc == Bytecodes::_invokevirtual || bc == Bytecodes::_invokeinterface) && | |
1783 | 3508 C1ProfileVirtualCalls) { |
0 | 3509 assert(op->recv()->is_single_cpu(), "recv must be allocated"); |
3510 Register recv = op->recv()->as_register(); | |
3511 assert_different_registers(mdo, recv); | |
3512 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls"); | |
3513 ciKlass* known_klass = op->known_holder(); | |
1783 | 3514 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) { |
0 | 3515 // We know the type that will be seen at this call site; we can |
3516 // statically update the methodDataOop rather than needing to do | |
3517 // dynamic tests on the receiver type | |
3518 | |
3519 // NOTE: we should probably put a lock around this search to | |
3520 // avoid collisions by concurrent compilations | |
3521 ciVirtualCallData* vc_data = (ciVirtualCallData*) data; | |
3522 uint i; | |
3523 for (i = 0; i < VirtualCallData::row_limit(); i++) { | |
3524 ciKlass* receiver = vc_data->receiver(i); | |
3525 if (known_klass->equals(receiver)) { | |
3526 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))); | |
1783 | 3527 __ addptr(data_addr, DataLayout::counter_increment); |
0 | 3528 return; |
3529 } | |
3530 } | |
3531 | |
3532 // Receiver type not found in profile data; select an empty slot | |
3533 | |
3534 // Note that this is less efficient than it should be because it | |
3535 // always does a write to the receiver part of the | |
3536 // VirtualCallData rather than just the first time | |
3537 for (i = 0; i < VirtualCallData::row_limit(); i++) { | |
3538 ciKlass* receiver = vc_data->receiver(i); | |
3539 if (receiver == NULL) { | |
3540 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i))); | |
989
148e5441d916
6863023: need non-perm oops in code cache for JSR 292
jrose
parents:
780
diff
changeset
|
3541 __ movoop(recv_addr, known_klass->constant_encoding()); |
0 | 3542 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))); |
1783 | 3543 __ addptr(data_addr, DataLayout::counter_increment); |
0 | 3544 return; |
3545 } | |
3546 } | |
3547 } else { | |
2002 | 3548 __ load_klass(recv, recv); |
0 | 3549 Label update_done; |
1783 | 3550 type_profile_helper(mdo, md, data, recv, &update_done); |
1206
87684f1a88b5
6614597: Performance variability in jvm2008 xml.validation
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parents:
1204
diff
changeset
|
3551 // Receiver did not match any saved receiver and there is no empty row for it. |
1251
576e77447e3c
6923002: assert(false,"this call site should not be polymorphic")
kvn
parents:
1206
diff
changeset
|
3552 // Increment total counter to indicate polymorphic case. |
1783 | 3553 __ addptr(counter_addr, DataLayout::counter_increment); |
0 | 3554 |
3555 __ bind(update_done); | |
3556 } | |
1206
87684f1a88b5
6614597: Performance variability in jvm2008 xml.validation
kvn
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1204
diff
changeset
|
3557 } else { |
87684f1a88b5
6614597: Performance variability in jvm2008 xml.validation
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1204
diff
changeset
|
3558 // Static call |
1783 | 3559 __ addptr(counter_addr, DataLayout::counter_increment); |
0 | 3560 } |
3561 } | |
3562 | |
3563 void LIR_Assembler::emit_delay(LIR_OpDelay*) { | |
3564 Unimplemented(); | |
3565 } | |
3566 | |
3567 | |
3568 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) { | |
304 | 3569 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no)); |
0 | 3570 } |
3571 | |
3572 | |
3573 void LIR_Assembler::align_backward_branch_target() { | |
3574 __ align(BytesPerWord); | |
3575 } | |
3576 | |
3577 | |
3578 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) { | |
3579 if (left->is_single_cpu()) { | |
3580 __ negl(left->as_register()); | |
3581 move_regs(left->as_register(), dest->as_register()); | |
3582 | |
3583 } else if (left->is_double_cpu()) { | |
3584 Register lo = left->as_register_lo(); | |
304 | 3585 #ifdef _LP64 |
3586 Register dst = dest->as_register_lo(); | |
3587 __ movptr(dst, lo); | |
3588 __ negptr(dst); | |
3589 #else | |
0 | 3590 Register hi = left->as_register_hi(); |
3591 __ lneg(hi, lo); | |
3592 if (dest->as_register_lo() == hi) { | |
3593 assert(dest->as_register_hi() != lo, "destroying register"); | |
3594 move_regs(hi, dest->as_register_hi()); | |
3595 move_regs(lo, dest->as_register_lo()); | |
3596 } else { | |
3597 move_regs(lo, dest->as_register_lo()); | |
3598 move_regs(hi, dest->as_register_hi()); | |
3599 } | |
304 | 3600 #endif // _LP64 |
0 | 3601 |
3602 } else if (dest->is_single_xmm()) { | |
3603 if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) { | |
3604 __ movflt(dest->as_xmm_float_reg(), left->as_xmm_float_reg()); | |
3605 } | |
3606 __ xorps(dest->as_xmm_float_reg(), | |
3607 ExternalAddress((address)float_signflip_pool)); | |
3608 | |
3609 } else if (dest->is_double_xmm()) { | |
3610 if (left->as_xmm_double_reg() != dest->as_xmm_double_reg()) { | |
3611 __ movdbl(dest->as_xmm_double_reg(), left->as_xmm_double_reg()); | |
3612 } | |
3613 __ xorpd(dest->as_xmm_double_reg(), | |
3614 ExternalAddress((address)double_signflip_pool)); | |
3615 | |
3616 } else if (left->is_single_fpu() || left->is_double_fpu()) { | |
3617 assert(left->fpu() == 0, "arg must be on TOS"); | |
3618 assert(dest->fpu() == 0, "dest must be TOS"); | |
3619 __ fchs(); | |
3620 | |
3621 } else { | |
3622 ShouldNotReachHere(); | |
3623 } | |
3624 } | |
3625 | |
3626 | |
3627 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest) { | |
3628 assert(addr->is_address() && dest->is_register(), "check"); | |
304 | 3629 Register reg; |
3630 reg = dest->as_pointer_register(); | |
3631 __ lea(reg, as_Address(addr->as_address_ptr())); | |
0 | 3632 } |
3633 | |
3634 | |
3635 | |
3636 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) { | |
3637 assert(!tmp->is_valid(), "don't need temporary"); | |
3638 __ call(RuntimeAddress(dest)); | |
3639 if (info != NULL) { | |
3640 add_call_info_here(info); | |
3641 } | |
3642 } | |
3643 | |
3644 | |
3645 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) { | |
3646 assert(type == T_LONG, "only for volatile long fields"); | |
3647 | |
3648 if (info != NULL) { | |
3649 add_debug_info_for_null_check_here(info); | |
3650 } | |
3651 | |
3652 if (src->is_double_xmm()) { | |
3653 if (dest->is_double_cpu()) { | |
304 | 3654 #ifdef _LP64 |
3655 __ movdq(dest->as_register_lo(), src->as_xmm_double_reg()); | |
3656 #else | |
3657 __ movdl(dest->as_register_lo(), src->as_xmm_double_reg()); | |
0 | 3658 __ psrlq(src->as_xmm_double_reg(), 32); |
304 | 3659 __ movdl(dest->as_register_hi(), src->as_xmm_double_reg()); |
3660 #endif // _LP64 | |
0 | 3661 } else if (dest->is_double_stack()) { |
3662 __ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg()); | |
3663 } else if (dest->is_address()) { | |
3664 __ movdbl(as_Address(dest->as_address_ptr()), src->as_xmm_double_reg()); | |
3665 } else { | |
3666 ShouldNotReachHere(); | |
3667 } | |
3668 | |
3669 } else if (dest->is_double_xmm()) { | |
3670 if (src->is_double_stack()) { | |
3671 __ movdbl(dest->as_xmm_double_reg(), frame_map()->address_for_slot(src->double_stack_ix())); | |
3672 } else if (src->is_address()) { | |
3673 __ movdbl(dest->as_xmm_double_reg(), as_Address(src->as_address_ptr())); | |
3674 } else { | |
3675 ShouldNotReachHere(); | |
3676 } | |
3677 | |
3678 } else if (src->is_double_fpu()) { | |
3679 assert(src->fpu_regnrLo() == 0, "must be TOS"); | |
3680 if (dest->is_double_stack()) { | |
3681 __ fistp_d(frame_map()->address_for_slot(dest->double_stack_ix())); | |
3682 } else if (dest->is_address()) { | |
3683 __ fistp_d(as_Address(dest->as_address_ptr())); | |
3684 } else { | |
3685 ShouldNotReachHere(); | |
3686 } | |
3687 | |
3688 } else if (dest->is_double_fpu()) { | |
3689 assert(dest->fpu_regnrLo() == 0, "must be TOS"); | |
3690 if (src->is_double_stack()) { | |
3691 __ fild_d(frame_map()->address_for_slot(src->double_stack_ix())); | |
3692 } else if (src->is_address()) { | |
3693 __ fild_d(as_Address(src->as_address_ptr())); | |
3694 } else { | |
3695 ShouldNotReachHere(); | |
3696 } | |
3697 } else { | |
3698 ShouldNotReachHere(); | |
3699 } | |
3700 } | |
3701 | |
3702 | |
3703 void LIR_Assembler::membar() { | |
304 | 3704 // QQQ sparc TSO uses this, |
3705 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad)); | |
0 | 3706 } |
3707 | |
3708 void LIR_Assembler::membar_acquire() { | |
3709 // No x86 machines currently require load fences | |
3710 // __ load_fence(); | |
3711 } | |
3712 | |
3713 void LIR_Assembler::membar_release() { | |
3714 // No x86 machines currently require store fences | |
3715 // __ store_fence(); | |
3716 } | |
3717 | |
3718 void LIR_Assembler::get_thread(LIR_Opr result_reg) { | |
3719 assert(result_reg->is_register(), "check"); | |
304 | 3720 #ifdef _LP64 |
3721 // __ get_thread(result_reg->as_register_lo()); | |
3722 __ mov(result_reg->as_register(), r15_thread); | |
3723 #else | |
0 | 3724 __ get_thread(result_reg->as_register()); |
304 | 3725 #endif // _LP64 |
0 | 3726 } |
3727 | |
3728 | |
3729 void LIR_Assembler::peephole(LIR_List*) { | |
3730 // do nothing for now | |
3731 } | |
3732 | |
3733 | |
3734 #undef __ |