Mercurial > hg > truffle
annotate src/cpu/x86/vm/c1_LIRAssembler_x86.cpp @ 1972:f95d63e2154a
6989984: Use standard include model for Hospot
Summary: Replaced MakeDeps and the includeDB files with more standardized solutions.
Reviewed-by: coleenp, kvn, kamg
| author | stefank |
|---|---|
| date | Tue, 23 Nov 2010 13:22:55 -0800 |
| parents | c393f046f4c5 |
| children | ac637b7220d1 |
| rev | line source |
|---|---|
| 0 | 1 /* |
|
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2 * Copyright (c) 2000, 2010, Oracle and/or its affiliates. All rights reserved. |
| 0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 4 * | |
| 5 * This code is free software; you can redistribute it and/or modify it | |
| 6 * under the terms of the GNU General Public License version 2 only, as | |
| 7 * published by the Free Software Foundation. | |
| 8 * | |
| 9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 * version 2 for more details (a copy is included in the LICENSE file that | |
| 13 * accompanied this code). | |
| 14 * | |
| 15 * You should have received a copy of the GNU General Public License version | |
| 16 * 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 * | |
|
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
|
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20 * or visit www.oracle.com if you need additional information or have any |
|
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21 * questions. |
| 0 | 22 * |
| 23 */ | |
| 24 | |
| 1972 | 25 #include "precompiled.hpp" |
| 26 #include "c1/c1_Compilation.hpp" | |
| 27 #include "c1/c1_LIRAssembler.hpp" | |
| 28 #include "c1/c1_MacroAssembler.hpp" | |
| 29 #include "c1/c1_Runtime1.hpp" | |
| 30 #include "c1/c1_ValueStack.hpp" | |
| 31 #include "ci/ciArrayKlass.hpp" | |
| 32 #include "ci/ciInstance.hpp" | |
| 33 #include "gc_interface/collectedHeap.hpp" | |
| 34 #include "memory/barrierSet.hpp" | |
| 35 #include "memory/cardTableModRefBS.hpp" | |
| 36 #include "nativeInst_x86.hpp" | |
| 37 #include "oops/objArrayKlass.hpp" | |
| 38 #include "runtime/sharedRuntime.hpp" | |
| 0 | 39 |
| 40 | |
| 41 // These masks are used to provide 128-bit aligned bitmasks to the XMM | |
| 42 // instructions, to allow sign-masking or sign-bit flipping. They allow | |
| 43 // fast versions of NegF/NegD and AbsF/AbsD. | |
| 44 | |
| 45 // Note: 'double' and 'long long' have 32-bits alignment on x86. | |
| 46 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) { | |
| 47 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address | |
| 48 // of 128-bits operands for SSE instructions. | |
| 49 jlong *operand = (jlong*)(((long)adr)&((long)(~0xF))); | |
| 50 // Store the value to a 128-bits operand. | |
| 51 operand[0] = lo; | |
| 52 operand[1] = hi; | |
| 53 return operand; | |
| 54 } | |
| 55 | |
| 56 // Buffer for 128-bits masks used by SSE instructions. | |
| 57 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment) | |
| 58 | |
| 59 // Static initialization during VM startup. | |
| 60 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF)); | |
| 61 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF)); | |
| 62 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000)); | |
| 63 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000)); | |
| 64 | |
| 65 | |
| 66 | |
| 67 NEEDS_CLEANUP // remove this definitions ? | |
| 68 const Register IC_Klass = rax; // where the IC klass is cached | |
| 69 const Register SYNC_header = rax; // synchronization header | |
| 70 const Register SHIFT_count = rcx; // where count for shift operations must be | |
| 71 | |
| 72 #define __ _masm-> | |
| 73 | |
| 74 | |
| 75 static void select_different_registers(Register preserve, | |
| 76 Register extra, | |
| 77 Register &tmp1, | |
| 78 Register &tmp2) { | |
| 79 if (tmp1 == preserve) { | |
| 80 assert_different_registers(tmp1, tmp2, extra); | |
| 81 tmp1 = extra; | |
| 82 } else if (tmp2 == preserve) { | |
| 83 assert_different_registers(tmp1, tmp2, extra); | |
| 84 tmp2 = extra; | |
| 85 } | |
| 86 assert_different_registers(preserve, tmp1, tmp2); | |
| 87 } | |
| 88 | |
| 89 | |
| 90 | |
| 91 static void select_different_registers(Register preserve, | |
| 92 Register extra, | |
| 93 Register &tmp1, | |
| 94 Register &tmp2, | |
| 95 Register &tmp3) { | |
| 96 if (tmp1 == preserve) { | |
| 97 assert_different_registers(tmp1, tmp2, tmp3, extra); | |
| 98 tmp1 = extra; | |
| 99 } else if (tmp2 == preserve) { | |
| 100 assert_different_registers(tmp1, tmp2, tmp3, extra); | |
| 101 tmp2 = extra; | |
| 102 } else if (tmp3 == preserve) { | |
| 103 assert_different_registers(tmp1, tmp2, tmp3, extra); | |
| 104 tmp3 = extra; | |
| 105 } | |
| 106 assert_different_registers(preserve, tmp1, tmp2, tmp3); | |
| 107 } | |
| 108 | |
| 109 | |
| 110 | |
| 111 bool LIR_Assembler::is_small_constant(LIR_Opr opr) { | |
| 112 if (opr->is_constant()) { | |
| 113 LIR_Const* constant = opr->as_constant_ptr(); | |
| 114 switch (constant->type()) { | |
| 115 case T_INT: { | |
| 116 return true; | |
| 117 } | |
| 118 | |
| 119 default: | |
| 120 return false; | |
| 121 } | |
| 122 } | |
| 123 return false; | |
| 124 } | |
| 125 | |
| 126 | |
| 127 LIR_Opr LIR_Assembler::receiverOpr() { | |
| 304 | 128 return FrameMap::receiver_opr; |
| 0 | 129 } |
| 130 | |
| 131 LIR_Opr LIR_Assembler::incomingReceiverOpr() { | |
| 132 return receiverOpr(); | |
| 133 } | |
| 134 | |
| 135 LIR_Opr LIR_Assembler::osrBufferPointer() { | |
| 304 | 136 return FrameMap::as_pointer_opr(receiverOpr()->as_register()); |
| 0 | 137 } |
| 138 | |
| 139 //--------------fpu register translations----------------------- | |
| 140 | |
| 141 | |
| 142 address LIR_Assembler::float_constant(float f) { | |
| 143 address const_addr = __ float_constant(f); | |
| 144 if (const_addr == NULL) { | |
| 145 bailout("const section overflow"); | |
| 146 return __ code()->consts()->start(); | |
| 147 } else { | |
| 148 return const_addr; | |
| 149 } | |
| 150 } | |
| 151 | |
| 152 | |
| 153 address LIR_Assembler::double_constant(double d) { | |
| 154 address const_addr = __ double_constant(d); | |
| 155 if (const_addr == NULL) { | |
| 156 bailout("const section overflow"); | |
| 157 return __ code()->consts()->start(); | |
| 158 } else { | |
| 159 return const_addr; | |
| 160 } | |
| 161 } | |
| 162 | |
| 163 | |
| 164 void LIR_Assembler::set_24bit_FPU() { | |
| 165 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); | |
| 166 } | |
| 167 | |
| 168 void LIR_Assembler::reset_FPU() { | |
| 169 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); | |
| 170 } | |
| 171 | |
| 172 void LIR_Assembler::fpop() { | |
| 173 __ fpop(); | |
| 174 } | |
| 175 | |
| 176 void LIR_Assembler::fxch(int i) { | |
| 177 __ fxch(i); | |
| 178 } | |
| 179 | |
| 180 void LIR_Assembler::fld(int i) { | |
| 181 __ fld_s(i); | |
| 182 } | |
| 183 | |
| 184 void LIR_Assembler::ffree(int i) { | |
| 185 __ ffree(i); | |
| 186 } | |
| 187 | |
| 188 void LIR_Assembler::breakpoint() { | |
| 189 __ int3(); | |
| 190 } | |
| 191 | |
| 192 void LIR_Assembler::push(LIR_Opr opr) { | |
| 193 if (opr->is_single_cpu()) { | |
| 194 __ push_reg(opr->as_register()); | |
| 195 } else if (opr->is_double_cpu()) { | |
| 304 | 196 NOT_LP64(__ push_reg(opr->as_register_hi())); |
| 0 | 197 __ push_reg(opr->as_register_lo()); |
| 198 } else if (opr->is_stack()) { | |
| 199 __ push_addr(frame_map()->address_for_slot(opr->single_stack_ix())); | |
| 200 } else if (opr->is_constant()) { | |
| 201 LIR_Const* const_opr = opr->as_constant_ptr(); | |
| 202 if (const_opr->type() == T_OBJECT) { | |
| 203 __ push_oop(const_opr->as_jobject()); | |
| 204 } else if (const_opr->type() == T_INT) { | |
| 205 __ push_jint(const_opr->as_jint()); | |
| 206 } else { | |
| 207 ShouldNotReachHere(); | |
| 208 } | |
| 209 | |
| 210 } else { | |
| 211 ShouldNotReachHere(); | |
| 212 } | |
| 213 } | |
| 214 | |
| 215 void LIR_Assembler::pop(LIR_Opr opr) { | |
| 216 if (opr->is_single_cpu()) { | |
| 304 | 217 __ pop_reg(opr->as_register()); |
| 0 | 218 } else { |
| 219 ShouldNotReachHere(); | |
| 220 } | |
| 221 } | |
| 222 | |
| 304 | 223 bool LIR_Assembler::is_literal_address(LIR_Address* addr) { |
| 224 return addr->base()->is_illegal() && addr->index()->is_illegal(); | |
| 225 } | |
| 226 | |
| 0 | 227 //------------------------------------------- |
| 304 | 228 |
| 0 | 229 Address LIR_Assembler::as_Address(LIR_Address* addr) { |
| 304 | 230 return as_Address(addr, rscratch1); |
| 231 } | |
| 232 | |
| 233 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) { | |
| 0 | 234 if (addr->base()->is_illegal()) { |
| 235 assert(addr->index()->is_illegal(), "must be illegal too"); | |
| 304 | 236 AddressLiteral laddr((address)addr->disp(), relocInfo::none); |
| 237 if (! __ reachable(laddr)) { | |
| 238 __ movptr(tmp, laddr.addr()); | |
| 239 Address res(tmp, 0); | |
| 240 return res; | |
| 241 } else { | |
| 242 return __ as_Address(laddr); | |
| 243 } | |
| 0 | 244 } |
| 245 | |
| 304 | 246 Register base = addr->base()->as_pointer_register(); |
| 0 | 247 |
| 248 if (addr->index()->is_illegal()) { | |
| 249 return Address( base, addr->disp()); | |
| 304 | 250 } else if (addr->index()->is_cpu_register()) { |
| 251 Register index = addr->index()->as_pointer_register(); | |
| 0 | 252 return Address(base, index, (Address::ScaleFactor) addr->scale(), addr->disp()); |
| 253 } else if (addr->index()->is_constant()) { | |
| 304 | 254 intptr_t addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp(); |
| 255 assert(Assembler::is_simm32(addr_offset), "must be"); | |
| 0 | 256 |
| 257 return Address(base, addr_offset); | |
| 258 } else { | |
| 259 Unimplemented(); | |
| 260 return Address(); | |
| 261 } | |
| 262 } | |
| 263 | |
| 264 | |
| 265 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) { | |
| 266 Address base = as_Address(addr); | |
| 267 return Address(base._base, base._index, base._scale, base._disp + BytesPerWord); | |
| 268 } | |
| 269 | |
| 270 | |
| 271 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) { | |
| 272 return as_Address(addr); | |
| 273 } | |
| 274 | |
| 275 | |
| 276 void LIR_Assembler::osr_entry() { | |
| 277 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset()); | |
| 278 BlockBegin* osr_entry = compilation()->hir()->osr_entry(); | |
| 279 ValueStack* entry_state = osr_entry->state(); | |
| 280 int number_of_locks = entry_state->locks_size(); | |
| 281 | |
| 282 // we jump here if osr happens with the interpreter | |
| 283 // state set up to continue at the beginning of the | |
| 284 // loop that triggered osr - in particular, we have | |
| 285 // the following registers setup: | |
| 286 // | |
| 287 // rcx: osr buffer | |
| 288 // | |
| 289 | |
| 290 // build frame | |
| 291 ciMethod* m = compilation()->method(); | |
| 292 __ build_frame(initial_frame_size_in_bytes()); | |
| 293 | |
| 294 // OSR buffer is | |
| 295 // | |
| 296 // locals[nlocals-1..0] | |
| 297 // monitors[0..number_of_locks] | |
| 298 // | |
| 299 // locals is a direct copy of the interpreter frame so in the osr buffer | |
| 300 // so first slot in the local array is the last local from the interpreter | |
| 301 // and last slot is local[0] (receiver) from the interpreter | |
| 302 // | |
| 303 // Similarly with locks. The first lock slot in the osr buffer is the nth lock | |
| 304 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock | |
| 305 // in the interpreter frame (the method lock if a sync method) | |
| 306 | |
| 307 // Initialize monitors in the compiled activation. | |
| 308 // rcx: pointer to osr buffer | |
| 309 // | |
| 310 // All other registers are dead at this point and the locals will be | |
| 311 // copied into place by code emitted in the IR. | |
| 312 | |
| 304 | 313 Register OSR_buf = osrBufferPointer()->as_pointer_register(); |
| 0 | 314 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below"); |
| 315 int monitor_offset = BytesPerWord * method()->max_locals() + | |
| 1060 | 316 (2 * BytesPerWord) * (number_of_locks - 1); |
| 317 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in | |
| 318 // the OSR buffer using 2 word entries: first the lock and then | |
| 319 // the oop. | |
| 0 | 320 for (int i = 0; i < number_of_locks; i++) { |
| 1060 | 321 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord); |
| 0 | 322 #ifdef ASSERT |
| 323 // verify the interpreter's monitor has a non-null object | |
| 324 { | |
| 325 Label L; | |
| 1060 | 326 __ cmpptr(Address(OSR_buf, slot_offset + 1*BytesPerWord), (int32_t)NULL_WORD); |
| 0 | 327 __ jcc(Assembler::notZero, L); |
| 328 __ stop("locked object is NULL"); | |
| 329 __ bind(L); | |
| 330 } | |
| 331 #endif | |
| 1060 | 332 __ movptr(rbx, Address(OSR_buf, slot_offset + 0)); |
| 304 | 333 __ movptr(frame_map()->address_for_monitor_lock(i), rbx); |
| 1060 | 334 __ movptr(rbx, Address(OSR_buf, slot_offset + 1*BytesPerWord)); |
| 304 | 335 __ movptr(frame_map()->address_for_monitor_object(i), rbx); |
| 0 | 336 } |
| 337 } | |
| 338 } | |
| 339 | |
| 340 | |
| 341 // inline cache check; done before the frame is built. | |
| 342 int LIR_Assembler::check_icache() { | |
| 343 Register receiver = FrameMap::receiver_opr->as_register(); | |
| 344 Register ic_klass = IC_Klass; | |
| 304 | 345 const int ic_cmp_size = LP64_ONLY(10) NOT_LP64(9); |
| 0 | 346 |
| 347 if (!VerifyOops) { | |
| 348 // insert some nops so that the verified entry point is aligned on CodeEntryAlignment | |
| 304 | 349 while ((__ offset() + ic_cmp_size) % CodeEntryAlignment != 0) { |
| 0 | 350 __ nop(); |
| 351 } | |
| 352 } | |
| 353 int offset = __ offset(); | |
| 354 __ inline_cache_check(receiver, IC_Klass); | |
| 355 assert(__ offset() % CodeEntryAlignment == 0 || VerifyOops, "alignment must be correct"); | |
| 356 if (VerifyOops) { | |
| 357 // force alignment after the cache check. | |
| 358 // It's been verified to be aligned if !VerifyOops | |
| 359 __ align(CodeEntryAlignment); | |
| 360 } | |
| 361 return offset; | |
| 362 } | |
| 363 | |
| 364 | |
| 365 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) { | |
| 366 jobject o = NULL; | |
| 367 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id); | |
| 368 __ movoop(reg, o); | |
| 369 patching_epilog(patch, lir_patch_normal, reg, info); | |
| 370 } | |
| 371 | |
| 372 | |
| 373 void LIR_Assembler::monitorexit(LIR_Opr obj_opr, LIR_Opr lock_opr, Register new_hdr, int monitor_no, Register exception) { | |
| 374 if (exception->is_valid()) { | |
| 375 // preserve exception | |
| 376 // note: the monitor_exit runtime call is a leaf routine | |
| 377 // and cannot block => no GC can happen | |
| 378 // The slow case (MonitorAccessStub) uses the first two stack slots | |
| 379 // ([esp+0] and [esp+4]), therefore we store the exception at [esp+8] | |
| 304 | 380 __ movptr (Address(rsp, 2*wordSize), exception); |
| 0 | 381 } |
| 382 | |
| 383 Register obj_reg = obj_opr->as_register(); | |
| 384 Register lock_reg = lock_opr->as_register(); | |
| 385 | |
| 386 // setup registers (lock_reg must be rax, for lock_object) | |
| 387 assert(obj_reg != SYNC_header && lock_reg != SYNC_header, "rax, must be available here"); | |
| 388 Register hdr = lock_reg; | |
| 389 assert(new_hdr == SYNC_header, "wrong register"); | |
| 390 lock_reg = new_hdr; | |
| 391 // compute pointer to BasicLock | |
| 392 Address lock_addr = frame_map()->address_for_monitor_lock(monitor_no); | |
| 304 | 393 __ lea(lock_reg, lock_addr); |
| 0 | 394 // unlock object |
| 395 MonitorAccessStub* slow_case = new MonitorExitStub(lock_opr, true, monitor_no); | |
| 396 // _slow_case_stubs->append(slow_case); | |
| 397 // temporary fix: must be created after exceptionhandler, therefore as call stub | |
| 398 _slow_case_stubs->append(slow_case); | |
| 399 if (UseFastLocking) { | |
| 400 // try inlined fast unlocking first, revert to slow locking if it fails | |
| 401 // note: lock_reg points to the displaced header since the displaced header offset is 0! | |
| 402 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); | |
| 403 __ unlock_object(hdr, obj_reg, lock_reg, *slow_case->entry()); | |
| 404 } else { | |
| 405 // always do slow unlocking | |
| 406 // note: the slow unlocking code could be inlined here, however if we use | |
| 407 // slow unlocking, speed doesn't matter anyway and this solution is | |
| 408 // simpler and requires less duplicated code - additionally, the | |
| 409 // slow unlocking code is the same in either case which simplifies | |
| 410 // debugging | |
| 411 __ jmp(*slow_case->entry()); | |
| 412 } | |
| 413 // done | |
| 414 __ bind(*slow_case->continuation()); | |
| 415 | |
| 416 if (exception->is_valid()) { | |
| 417 // restore exception | |
| 304 | 418 __ movptr (exception, Address(rsp, 2 * wordSize)); |
| 0 | 419 } |
| 420 } | |
| 421 | |
| 422 // This specifies the rsp decrement needed to build the frame | |
| 423 int LIR_Assembler::initial_frame_size_in_bytes() { | |
| 424 // if rounding, must let FrameMap know! | |
| 304 | 425 |
| 426 // The frame_map records size in slots (32bit word) | |
| 427 | |
| 428 // subtract two words to account for return address and link | |
| 429 return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word)) * VMRegImpl::stack_slot_size; | |
| 0 | 430 } |
| 431 | |
| 432 | |
| 1204 | 433 int LIR_Assembler::emit_exception_handler() { |
| 0 | 434 // if the last instruction is a call (typically to do a throw which |
| 435 // is coming at the end after block reordering) the return address | |
| 436 // must still point into the code area in order to avoid assertion | |
| 437 // failures when searching for the corresponding bci => add a nop | |
| 438 // (was bug 5/14/1999 - gri) | |
| 439 __ nop(); | |
| 440 | |
| 441 // generate code for exception handler | |
| 442 address handler_base = __ start_a_stub(exception_handler_size); | |
| 443 if (handler_base == NULL) { | |
| 444 // not enough space left for the handler | |
| 445 bailout("exception handler overflow"); | |
| 1204 | 446 return -1; |
| 0 | 447 } |
| 1204 | 448 |
| 0 | 449 int offset = code_offset(); |
| 450 | |
| 1295 | 451 // the exception oop and pc are in rax, and rdx |
| 0 | 452 // no other registers need to be preserved, so invalidate them |
| 1295 | 453 __ invalidate_registers(false, true, true, false, true, true); |
| 0 | 454 |
| 455 // check that there is really an exception | |
| 456 __ verify_not_null_oop(rax); | |
| 457 | |
| 1295 | 458 // search an exception handler (rax: exception oop, rdx: throwing pc) |
| 459 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_nofpu_id))); | |
| 460 | |
| 461 __ stop("should not reach here"); | |
| 462 | |
| 0 | 463 assert(code_offset() - offset <= exception_handler_size, "overflow"); |
| 464 __ end_a_stub(); | |
| 1204 | 465 |
| 466 return offset; | |
| 0 | 467 } |
| 468 | |
| 1204 | 469 |
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470 // Emit the code to remove the frame from the stack in the exception |
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471 // unwind path. |
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472 int LIR_Assembler::emit_unwind_handler() { |
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473 #ifndef PRODUCT |
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474 if (CommentedAssembly) { |
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475 _masm->block_comment("Unwind handler"); |
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476 } |
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477 #endif |
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478 |
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479 int offset = code_offset(); |
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480 |
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481 // Fetch the exception from TLS and clear out exception related thread state |
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482 __ get_thread(rsi); |
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483 __ movptr(rax, Address(rsi, JavaThread::exception_oop_offset())); |
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484 __ movptr(Address(rsi, JavaThread::exception_oop_offset()), (int32_t)NULL_WORD); |
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485 __ movptr(Address(rsi, JavaThread::exception_pc_offset()), (int32_t)NULL_WORD); |
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486 |
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487 __ bind(_unwind_handler_entry); |
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488 __ verify_not_null_oop(rax); |
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489 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) { |
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490 __ mov(rsi, rax); // Preserve the exception |
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491 } |
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492 |
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493 // Preform needed unlocking |
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494 MonitorExitStub* stub = NULL; |
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495 if (method()->is_synchronized()) { |
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496 monitor_address(0, FrameMap::rax_opr); |
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497 stub = new MonitorExitStub(FrameMap::rax_opr, true, 0); |
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498 __ unlock_object(rdi, rbx, rax, *stub->entry()); |
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499 __ bind(*stub->continuation()); |
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500 } |
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501 |
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502 if (compilation()->env()->dtrace_method_probes()) { |
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503 __ get_thread(rax); |
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504 __ movptr(Address(rsp, 0), rax); |
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505 __ movoop(Address(rsp, sizeof(void*)), method()->constant_encoding()); |
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506 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit))); |
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507 } |
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508 |
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509 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) { |
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510 __ mov(rax, rsi); // Restore the exception |
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511 } |
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512 |
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513 // remove the activation and dispatch to the unwind handler |
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514 __ remove_frame(initial_frame_size_in_bytes()); |
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515 __ jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id))); |
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516 |
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517 // Emit the slow path assembly |
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518 if (stub != NULL) { |
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519 stub->emit_code(this); |
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520 } |
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521 |
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522 return offset; |
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523 } |
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524 |
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525 |
| 1204 | 526 int LIR_Assembler::emit_deopt_handler() { |
| 0 | 527 // if the last instruction is a call (typically to do a throw which |
| 528 // is coming at the end after block reordering) the return address | |
| 529 // must still point into the code area in order to avoid assertion | |
| 530 // failures when searching for the corresponding bci => add a nop | |
| 531 // (was bug 5/14/1999 - gri) | |
| 532 __ nop(); | |
| 533 | |
| 534 // generate code for exception handler | |
| 535 address handler_base = __ start_a_stub(deopt_handler_size); | |
| 536 if (handler_base == NULL) { | |
| 537 // not enough space left for the handler | |
| 538 bailout("deopt handler overflow"); | |
| 1204 | 539 return -1; |
| 0 | 540 } |
| 1204 | 541 |
| 0 | 542 int offset = code_offset(); |
| 543 InternalAddress here(__ pc()); | |
| 1295 | 544 |
| 0 | 545 __ pushptr(here.addr()); |
| 546 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack())); | |
| 1295 | 547 |
| 0 | 548 assert(code_offset() - offset <= deopt_handler_size, "overflow"); |
| 549 __ end_a_stub(); | |
| 550 | |
| 1204 | 551 return offset; |
| 0 | 552 } |
| 553 | |
| 554 | |
| 555 // This is the fast version of java.lang.String.compare; it has not | |
| 556 // OSR-entry and therefore, we generate a slow version for OSR's | |
| 557 void LIR_Assembler::emit_string_compare(LIR_Opr arg0, LIR_Opr arg1, LIR_Opr dst, CodeEmitInfo* info) { | |
| 304 | 558 __ movptr (rbx, rcx); // receiver is in rcx |
| 559 __ movptr (rax, arg1->as_register()); | |
| 0 | 560 |
| 561 // Get addresses of first characters from both Strings | |
| 304 | 562 __ movptr (rsi, Address(rax, java_lang_String::value_offset_in_bytes())); |
| 563 __ movptr (rcx, Address(rax, java_lang_String::offset_offset_in_bytes())); | |
| 564 __ lea (rsi, Address(rsi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR))); | |
| 0 | 565 |
| 566 | |
| 567 // rbx, may be NULL | |
| 568 add_debug_info_for_null_check_here(info); | |
| 304 | 569 __ movptr (rdi, Address(rbx, java_lang_String::value_offset_in_bytes())); |
| 570 __ movptr (rcx, Address(rbx, java_lang_String::offset_offset_in_bytes())); | |
| 571 __ lea (rdi, Address(rdi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR))); | |
| 0 | 572 |
| 573 // compute minimum length (in rax) and difference of lengths (on top of stack) | |
| 574 if (VM_Version::supports_cmov()) { | |
| 304 | 575 __ movl (rbx, Address(rbx, java_lang_String::count_offset_in_bytes())); |
| 576 __ movl (rax, Address(rax, java_lang_String::count_offset_in_bytes())); | |
| 577 __ mov (rcx, rbx); | |
| 578 __ subptr (rbx, rax); // subtract lengths | |
| 579 __ push (rbx); // result | |
| 580 __ cmov (Assembler::lessEqual, rax, rcx); | |
| 0 | 581 } else { |
| 582 Label L; | |
| 304 | 583 __ movl (rbx, Address(rbx, java_lang_String::count_offset_in_bytes())); |
| 584 __ movl (rcx, Address(rax, java_lang_String::count_offset_in_bytes())); | |
| 585 __ mov (rax, rbx); | |
| 586 __ subptr (rbx, rcx); | |
| 587 __ push (rbx); | |
| 588 __ jcc (Assembler::lessEqual, L); | |
| 589 __ mov (rax, rcx); | |
| 0 | 590 __ bind (L); |
| 591 } | |
| 592 // is minimum length 0? | |
| 593 Label noLoop, haveResult; | |
| 304 | 594 __ testptr (rax, rax); |
| 0 | 595 __ jcc (Assembler::zero, noLoop); |
| 596 | |
| 597 // compare first characters | |
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598 __ load_unsigned_short(rcx, Address(rdi, 0)); |
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599 __ load_unsigned_short(rbx, Address(rsi, 0)); |
| 0 | 600 __ subl(rcx, rbx); |
| 601 __ jcc(Assembler::notZero, haveResult); | |
| 602 // starting loop | |
| 603 __ decrement(rax); // we already tested index: skip one | |
| 604 __ jcc(Assembler::zero, noLoop); | |
| 605 | |
| 606 // set rsi.edi to the end of the arrays (arrays have same length) | |
| 607 // negate the index | |
| 608 | |
| 304 | 609 __ lea(rsi, Address(rsi, rax, Address::times_2, type2aelembytes(T_CHAR))); |
| 610 __ lea(rdi, Address(rdi, rax, Address::times_2, type2aelembytes(T_CHAR))); | |
| 611 __ negptr(rax); | |
| 0 | 612 |
| 613 // compare the strings in a loop | |
| 614 | |
| 615 Label loop; | |
| 616 __ align(wordSize); | |
| 617 __ bind(loop); | |
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618 __ load_unsigned_short(rcx, Address(rdi, rax, Address::times_2, 0)); |
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619 __ load_unsigned_short(rbx, Address(rsi, rax, Address::times_2, 0)); |
| 0 | 620 __ subl(rcx, rbx); |
| 621 __ jcc(Assembler::notZero, haveResult); | |
| 622 __ increment(rax); | |
| 623 __ jcc(Assembler::notZero, loop); | |
| 624 | |
| 625 // strings are equal up to min length | |
| 626 | |
| 627 __ bind(noLoop); | |
| 304 | 628 __ pop(rax); |
| 0 | 629 return_op(LIR_OprFact::illegalOpr); |
| 630 | |
| 631 __ bind(haveResult); | |
| 632 // leave instruction is going to discard the TOS value | |
| 304 | 633 __ mov (rax, rcx); // result of call is in rax, |
| 0 | 634 } |
| 635 | |
| 636 | |
| 637 void LIR_Assembler::return_op(LIR_Opr result) { | |
| 638 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == rax, "word returns are in rax,"); | |
| 639 if (!result->is_illegal() && result->is_float_kind() && !result->is_xmm_register()) { | |
| 640 assert(result->fpu() == 0, "result must already be on TOS"); | |
| 641 } | |
| 642 | |
| 643 // Pop the stack before the safepoint code | |
| 1295 | 644 __ remove_frame(initial_frame_size_in_bytes()); |
| 0 | 645 |
| 646 bool result_is_oop = result->is_valid() ? result->is_oop() : false; | |
| 647 | |
| 648 // Note: we do not need to round double result; float result has the right precision | |
| 649 // the poll sets the condition code, but no data registers | |
| 650 AddressLiteral polling_page(os::get_polling_page() + (SafepointPollOffset % os::vm_page_size()), | |
| 651 relocInfo::poll_return_type); | |
| 304 | 652 |
| 653 // NOTE: the requires that the polling page be reachable else the reloc | |
| 654 // goes to the movq that loads the address and not the faulting instruction | |
| 655 // which breaks the signal handler code | |
| 656 | |
| 0 | 657 __ test32(rax, polling_page); |
| 658 | |
| 659 __ ret(0); | |
| 660 } | |
| 661 | |
| 662 | |
| 663 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) { | |
| 664 AddressLiteral polling_page(os::get_polling_page() + (SafepointPollOffset % os::vm_page_size()), | |
| 665 relocInfo::poll_type); | |
| 666 | |
| 667 if (info != NULL) { | |
| 668 add_debug_info_for_branch(info); | |
| 669 } else { | |
| 670 ShouldNotReachHere(); | |
| 671 } | |
| 672 | |
| 673 int offset = __ offset(); | |
| 304 | 674 |
| 675 // NOTE: the requires that the polling page be reachable else the reloc | |
| 676 // goes to the movq that loads the address and not the faulting instruction | |
| 677 // which breaks the signal handler code | |
| 678 | |
| 0 | 679 __ test32(rax, polling_page); |
| 680 return offset; | |
| 681 } | |
| 682 | |
| 683 | |
| 684 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) { | |
| 304 | 685 if (from_reg != to_reg) __ mov(to_reg, from_reg); |
| 0 | 686 } |
| 687 | |
| 688 void LIR_Assembler::swap_reg(Register a, Register b) { | |
| 304 | 689 __ xchgptr(a, b); |
| 0 | 690 } |
| 691 | |
| 692 | |
| 693 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) { | |
| 694 assert(src->is_constant(), "should not call otherwise"); | |
| 695 assert(dest->is_register(), "should not call otherwise"); | |
| 696 LIR_Const* c = src->as_constant_ptr(); | |
| 697 | |
| 698 switch (c->type()) { | |
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699 case T_INT: |
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700 case T_ADDRESS: { |
| 0 | 701 assert(patch_code == lir_patch_none, "no patching handled here"); |
| 702 __ movl(dest->as_register(), c->as_jint()); | |
| 703 break; | |
| 704 } | |
| 705 | |
| 706 case T_LONG: { | |
| 707 assert(patch_code == lir_patch_none, "no patching handled here"); | |
| 304 | 708 #ifdef _LP64 |
| 709 __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong()); | |
| 710 #else | |
| 711 __ movptr(dest->as_register_lo(), c->as_jint_lo()); | |
| 712 __ movptr(dest->as_register_hi(), c->as_jint_hi()); | |
| 713 #endif // _LP64 | |
| 0 | 714 break; |
| 715 } | |
| 716 | |
| 717 case T_OBJECT: { | |
| 718 if (patch_code != lir_patch_none) { | |
| 719 jobject2reg_with_patching(dest->as_register(), info); | |
| 720 } else { | |
| 721 __ movoop(dest->as_register(), c->as_jobject()); | |
| 722 } | |
| 723 break; | |
| 724 } | |
| 725 | |
| 726 case T_FLOAT: { | |
| 727 if (dest->is_single_xmm()) { | |
| 728 if (c->is_zero_float()) { | |
| 729 __ xorps(dest->as_xmm_float_reg(), dest->as_xmm_float_reg()); | |
| 730 } else { | |
| 731 __ movflt(dest->as_xmm_float_reg(), | |
| 732 InternalAddress(float_constant(c->as_jfloat()))); | |
| 733 } | |
| 734 } else { | |
| 735 assert(dest->is_single_fpu(), "must be"); | |
| 736 assert(dest->fpu_regnr() == 0, "dest must be TOS"); | |
| 737 if (c->is_zero_float()) { | |
| 738 __ fldz(); | |
| 739 } else if (c->is_one_float()) { | |
| 740 __ fld1(); | |
| 741 } else { | |
| 742 __ fld_s (InternalAddress(float_constant(c->as_jfloat()))); | |
| 743 } | |
| 744 } | |
| 745 break; | |
| 746 } | |
| 747 | |
| 748 case T_DOUBLE: { | |
| 749 if (dest->is_double_xmm()) { | |
| 750 if (c->is_zero_double()) { | |
| 751 __ xorpd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg()); | |
| 752 } else { | |
| 753 __ movdbl(dest->as_xmm_double_reg(), | |
| 754 InternalAddress(double_constant(c->as_jdouble()))); | |
| 755 } | |
| 756 } else { | |
| 757 assert(dest->is_double_fpu(), "must be"); | |
| 758 assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); | |
| 759 if (c->is_zero_double()) { | |
| 760 __ fldz(); | |
| 761 } else if (c->is_one_double()) { | |
| 762 __ fld1(); | |
| 763 } else { | |
| 764 __ fld_d (InternalAddress(double_constant(c->as_jdouble()))); | |
| 765 } | |
| 766 } | |
| 767 break; | |
| 768 } | |
| 769 | |
| 770 default: | |
| 771 ShouldNotReachHere(); | |
| 772 } | |
| 773 } | |
| 774 | |
| 775 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) { | |
| 776 assert(src->is_constant(), "should not call otherwise"); | |
| 777 assert(dest->is_stack(), "should not call otherwise"); | |
| 778 LIR_Const* c = src->as_constant_ptr(); | |
| 779 | |
| 780 switch (c->type()) { | |
| 781 case T_INT: // fall through | |
| 782 case T_FLOAT: | |
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783 case T_ADDRESS: |
| 0 | 784 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits()); |
| 785 break; | |
| 786 | |
| 787 case T_OBJECT: | |
| 788 __ movoop(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jobject()); | |
| 789 break; | |
| 790 | |
| 791 case T_LONG: // fall through | |
| 792 case T_DOUBLE: | |
| 304 | 793 #ifdef _LP64 |
| 794 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), | |
| 795 lo_word_offset_in_bytes), (intptr_t)c->as_jlong_bits()); | |
| 796 #else | |
| 797 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), | |
| 798 lo_word_offset_in_bytes), c->as_jint_lo_bits()); | |
| 799 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), | |
| 800 hi_word_offset_in_bytes), c->as_jint_hi_bits()); | |
| 801 #endif // _LP64 | |
| 0 | 802 break; |
| 803 | |
| 804 default: | |
| 805 ShouldNotReachHere(); | |
| 806 } | |
| 807 } | |
| 808 | |
| 809 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info ) { | |
| 810 assert(src->is_constant(), "should not call otherwise"); | |
| 811 assert(dest->is_address(), "should not call otherwise"); | |
| 812 LIR_Const* c = src->as_constant_ptr(); | |
| 813 LIR_Address* addr = dest->as_address_ptr(); | |
| 814 | |
| 304 | 815 int null_check_here = code_offset(); |
| 0 | 816 switch (type) { |
| 817 case T_INT: // fall through | |
| 818 case T_FLOAT: | |
|
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819 case T_ADDRESS: |
| 0 | 820 __ movl(as_Address(addr), c->as_jint_bits()); |
| 821 break; | |
| 822 | |
| 823 case T_OBJECT: // fall through | |
| 824 case T_ARRAY: | |
| 825 if (c->as_jobject() == NULL) { | |
|
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826 __ movptr(as_Address(addr), NULL_WORD); |
| 0 | 827 } else { |
| 304 | 828 if (is_literal_address(addr)) { |
| 829 ShouldNotReachHere(); | |
| 830 __ movoop(as_Address(addr, noreg), c->as_jobject()); | |
| 831 } else { | |
| 1060 | 832 #ifdef _LP64 |
| 833 __ movoop(rscratch1, c->as_jobject()); | |
| 834 null_check_here = code_offset(); | |
| 835 __ movptr(as_Address_lo(addr), rscratch1); | |
| 836 #else | |
| 304 | 837 __ movoop(as_Address(addr), c->as_jobject()); |
| 1060 | 838 #endif |
| 304 | 839 } |
| 0 | 840 } |
| 841 break; | |
| 842 | |
| 843 case T_LONG: // fall through | |
| 844 case T_DOUBLE: | |
| 304 | 845 #ifdef _LP64 |
| 846 if (is_literal_address(addr)) { | |
| 847 ShouldNotReachHere(); | |
| 848 __ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits()); | |
| 849 } else { | |
| 850 __ movptr(r10, (intptr_t)c->as_jlong_bits()); | |
| 851 null_check_here = code_offset(); | |
| 852 __ movptr(as_Address_lo(addr), r10); | |
| 853 } | |
| 854 #else | |
| 855 // Always reachable in 32bit so this doesn't produce useless move literal | |
| 856 __ movptr(as_Address_hi(addr), c->as_jint_hi_bits()); | |
| 857 __ movptr(as_Address_lo(addr), c->as_jint_lo_bits()); | |
| 858 #endif // _LP64 | |
| 0 | 859 break; |
| 860 | |
| 861 case T_BOOLEAN: // fall through | |
| 862 case T_BYTE: | |
| 863 __ movb(as_Address(addr), c->as_jint() & 0xFF); | |
| 864 break; | |
| 865 | |
| 866 case T_CHAR: // fall through | |
| 867 case T_SHORT: | |
| 868 __ movw(as_Address(addr), c->as_jint() & 0xFFFF); | |
| 869 break; | |
| 870 | |
| 871 default: | |
| 872 ShouldNotReachHere(); | |
| 873 }; | |
| 304 | 874 |
| 875 if (info != NULL) { | |
| 876 add_debug_info_for_null_check(null_check_here, info); | |
| 877 } | |
| 0 | 878 } |
| 879 | |
| 880 | |
| 881 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) { | |
| 882 assert(src->is_register(), "should not call otherwise"); | |
| 883 assert(dest->is_register(), "should not call otherwise"); | |
| 884 | |
| 885 // move between cpu-registers | |
| 886 if (dest->is_single_cpu()) { | |
| 304 | 887 #ifdef _LP64 |
| 888 if (src->type() == T_LONG) { | |
| 889 // Can do LONG -> OBJECT | |
| 890 move_regs(src->as_register_lo(), dest->as_register()); | |
| 891 return; | |
| 892 } | |
| 893 #endif | |
| 0 | 894 assert(src->is_single_cpu(), "must match"); |
| 895 if (src->type() == T_OBJECT) { | |
| 896 __ verify_oop(src->as_register()); | |
| 897 } | |
| 898 move_regs(src->as_register(), dest->as_register()); | |
| 899 | |
| 900 } else if (dest->is_double_cpu()) { | |
| 304 | 901 #ifdef _LP64 |
| 902 if (src->type() == T_OBJECT || src->type() == T_ARRAY) { | |
| 903 // Surprising to me but we can see move of a long to t_object | |
| 904 __ verify_oop(src->as_register()); | |
| 905 move_regs(src->as_register(), dest->as_register_lo()); | |
| 906 return; | |
| 907 } | |
| 908 #endif | |
| 0 | 909 assert(src->is_double_cpu(), "must match"); |
| 910 Register f_lo = src->as_register_lo(); | |
| 911 Register f_hi = src->as_register_hi(); | |
| 912 Register t_lo = dest->as_register_lo(); | |
| 913 Register t_hi = dest->as_register_hi(); | |
| 304 | 914 #ifdef _LP64 |
| 915 assert(f_hi == f_lo, "must be same"); | |
| 916 assert(t_hi == t_lo, "must be same"); | |
| 917 move_regs(f_lo, t_lo); | |
| 918 #else | |
| 0 | 919 assert(f_lo != f_hi && t_lo != t_hi, "invalid register allocation"); |
| 920 | |
| 304 | 921 |
| 0 | 922 if (f_lo == t_hi && f_hi == t_lo) { |
| 923 swap_reg(f_lo, f_hi); | |
| 924 } else if (f_hi == t_lo) { | |
| 925 assert(f_lo != t_hi, "overwriting register"); | |
| 926 move_regs(f_hi, t_hi); | |
| 927 move_regs(f_lo, t_lo); | |
| 928 } else { | |
| 929 assert(f_hi != t_lo, "overwriting register"); | |
| 930 move_regs(f_lo, t_lo); | |
| 931 move_regs(f_hi, t_hi); | |
| 932 } | |
| 304 | 933 #endif // LP64 |
| 0 | 934 |
| 935 // special moves from fpu-register to xmm-register | |
| 936 // necessary for method results | |
| 937 } else if (src->is_single_xmm() && !dest->is_single_xmm()) { | |
| 938 __ movflt(Address(rsp, 0), src->as_xmm_float_reg()); | |
| 939 __ fld_s(Address(rsp, 0)); | |
| 940 } else if (src->is_double_xmm() && !dest->is_double_xmm()) { | |
| 941 __ movdbl(Address(rsp, 0), src->as_xmm_double_reg()); | |
| 942 __ fld_d(Address(rsp, 0)); | |
| 943 } else if (dest->is_single_xmm() && !src->is_single_xmm()) { | |
| 944 __ fstp_s(Address(rsp, 0)); | |
| 945 __ movflt(dest->as_xmm_float_reg(), Address(rsp, 0)); | |
| 946 } else if (dest->is_double_xmm() && !src->is_double_xmm()) { | |
| 947 __ fstp_d(Address(rsp, 0)); | |
| 948 __ movdbl(dest->as_xmm_double_reg(), Address(rsp, 0)); | |
| 949 | |
| 950 // move between xmm-registers | |
| 951 } else if (dest->is_single_xmm()) { | |
| 952 assert(src->is_single_xmm(), "must match"); | |
| 953 __ movflt(dest->as_xmm_float_reg(), src->as_xmm_float_reg()); | |
| 954 } else if (dest->is_double_xmm()) { | |
| 955 assert(src->is_double_xmm(), "must match"); | |
| 956 __ movdbl(dest->as_xmm_double_reg(), src->as_xmm_double_reg()); | |
| 957 | |
| 958 // move between fpu-registers (no instruction necessary because of fpu-stack) | |
| 959 } else if (dest->is_single_fpu() || dest->is_double_fpu()) { | |
| 960 assert(src->is_single_fpu() || src->is_double_fpu(), "must match"); | |
| 961 assert(src->fpu() == dest->fpu(), "currently should be nothing to do"); | |
| 962 } else { | |
| 963 ShouldNotReachHere(); | |
| 964 } | |
| 965 } | |
| 966 | |
| 967 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) { | |
| 968 assert(src->is_register(), "should not call otherwise"); | |
| 969 assert(dest->is_stack(), "should not call otherwise"); | |
| 970 | |
| 971 if (src->is_single_cpu()) { | |
| 972 Address dst = frame_map()->address_for_slot(dest->single_stack_ix()); | |
| 973 if (type == T_OBJECT || type == T_ARRAY) { | |
| 974 __ verify_oop(src->as_register()); | |
| 304 | 975 __ movptr (dst, src->as_register()); |
| 976 } else { | |
| 977 __ movl (dst, src->as_register()); | |
| 0 | 978 } |
| 979 | |
| 980 } else if (src->is_double_cpu()) { | |
| 981 Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes); | |
| 982 Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes); | |
| 304 | 983 __ movptr (dstLO, src->as_register_lo()); |
| 984 NOT_LP64(__ movptr (dstHI, src->as_register_hi())); | |
| 0 | 985 |
| 986 } else if (src->is_single_xmm()) { | |
| 987 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix()); | |
| 988 __ movflt(dst_addr, src->as_xmm_float_reg()); | |
| 989 | |
| 990 } else if (src->is_double_xmm()) { | |
| 991 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix()); | |
| 992 __ movdbl(dst_addr, src->as_xmm_double_reg()); | |
| 993 | |
| 994 } else if (src->is_single_fpu()) { | |
| 995 assert(src->fpu_regnr() == 0, "argument must be on TOS"); | |
| 996 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix()); | |
| 997 if (pop_fpu_stack) __ fstp_s (dst_addr); | |
| 998 else __ fst_s (dst_addr); | |
| 999 | |
| 1000 } else if (src->is_double_fpu()) { | |
| 1001 assert(src->fpu_regnrLo() == 0, "argument must be on TOS"); | |
| 1002 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix()); | |
| 1003 if (pop_fpu_stack) __ fstp_d (dst_addr); | |
| 1004 else __ fst_d (dst_addr); | |
| 1005 | |
| 1006 } else { | |
| 1007 ShouldNotReachHere(); | |
| 1008 } | |
| 1009 } | |
| 1010 | |
| 1011 | |
| 1012 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool /* unaligned */) { | |
| 1013 LIR_Address* to_addr = dest->as_address_ptr(); | |
| 1014 PatchingStub* patch = NULL; | |
| 1015 | |
| 1016 if (type == T_ARRAY || type == T_OBJECT) { | |
| 1017 __ verify_oop(src->as_register()); | |
| 1018 } | |
| 1019 if (patch_code != lir_patch_none) { | |
| 1020 patch = new PatchingStub(_masm, PatchingStub::access_field_id); | |
| 304 | 1021 Address toa = as_Address(to_addr); |
| 1022 assert(toa.disp() != 0, "must have"); | |
| 0 | 1023 } |
| 1024 if (info != NULL) { | |
| 1025 add_debug_info_for_null_check_here(info); | |
| 1026 } | |
| 1027 | |
| 1028 switch (type) { | |
| 1029 case T_FLOAT: { | |
| 1030 if (src->is_single_xmm()) { | |
| 1031 __ movflt(as_Address(to_addr), src->as_xmm_float_reg()); | |
| 1032 } else { | |
| 1033 assert(src->is_single_fpu(), "must be"); | |
| 1034 assert(src->fpu_regnr() == 0, "argument must be on TOS"); | |
| 1035 if (pop_fpu_stack) __ fstp_s(as_Address(to_addr)); | |
| 1036 else __ fst_s (as_Address(to_addr)); | |
| 1037 } | |
| 1038 break; | |
| 1039 } | |
| 1040 | |
| 1041 case T_DOUBLE: { | |
| 1042 if (src->is_double_xmm()) { | |
| 1043 __ movdbl(as_Address(to_addr), src->as_xmm_double_reg()); | |
| 1044 } else { | |
| 1045 assert(src->is_double_fpu(), "must be"); | |
| 1046 assert(src->fpu_regnrLo() == 0, "argument must be on TOS"); | |
| 1047 if (pop_fpu_stack) __ fstp_d(as_Address(to_addr)); | |
| 1048 else __ fst_d (as_Address(to_addr)); | |
| 1049 } | |
| 1050 break; | |
| 1051 } | |
| 1052 | |
| 1053 case T_ADDRESS: // fall through | |
| 1054 case T_ARRAY: // fall through | |
| 1055 case T_OBJECT: // fall through | |
| 304 | 1056 #ifdef _LP64 |
| 1057 __ movptr(as_Address(to_addr), src->as_register()); | |
| 1058 break; | |
| 1059 #endif // _LP64 | |
| 0 | 1060 case T_INT: |
| 1061 __ movl(as_Address(to_addr), src->as_register()); | |
| 1062 break; | |
| 1063 | |
| 1064 case T_LONG: { | |
| 1065 Register from_lo = src->as_register_lo(); | |
| 1066 Register from_hi = src->as_register_hi(); | |
| 304 | 1067 #ifdef _LP64 |
| 1068 __ movptr(as_Address_lo(to_addr), from_lo); | |
| 1069 #else | |
| 0 | 1070 Register base = to_addr->base()->as_register(); |
| 1071 Register index = noreg; | |
| 1072 if (to_addr->index()->is_register()) { | |
| 1073 index = to_addr->index()->as_register(); | |
| 1074 } | |
| 1075 if (base == from_lo || index == from_lo) { | |
| 1076 assert(base != from_hi, "can't be"); | |
| 1077 assert(index == noreg || (index != base && index != from_hi), "can't handle this"); | |
| 1078 __ movl(as_Address_hi(to_addr), from_hi); | |
| 1079 if (patch != NULL) { | |
| 1080 patching_epilog(patch, lir_patch_high, base, info); | |
| 1081 patch = new PatchingStub(_masm, PatchingStub::access_field_id); | |
| 1082 patch_code = lir_patch_low; | |
| 1083 } | |
| 1084 __ movl(as_Address_lo(to_addr), from_lo); | |
| 1085 } else { | |
| 1086 assert(index == noreg || (index != base && index != from_lo), "can't handle this"); | |
| 1087 __ movl(as_Address_lo(to_addr), from_lo); | |
| 1088 if (patch != NULL) { | |
| 1089 patching_epilog(patch, lir_patch_low, base, info); | |
| 1090 patch = new PatchingStub(_masm, PatchingStub::access_field_id); | |
| 1091 patch_code = lir_patch_high; | |
| 1092 } | |
| 1093 __ movl(as_Address_hi(to_addr), from_hi); | |
| 1094 } | |
| 304 | 1095 #endif // _LP64 |
| 0 | 1096 break; |
| 1097 } | |
| 1098 | |
| 1099 case T_BYTE: // fall through | |
| 1100 case T_BOOLEAN: { | |
| 1101 Register src_reg = src->as_register(); | |
| 1102 Address dst_addr = as_Address(to_addr); | |
| 1103 assert(VM_Version::is_P6() || src_reg->has_byte_register(), "must use byte registers if not P6"); | |
| 1104 __ movb(dst_addr, src_reg); | |
| 1105 break; | |
| 1106 } | |
| 1107 | |
| 1108 case T_CHAR: // fall through | |
| 1109 case T_SHORT: | |
| 1110 __ movw(as_Address(to_addr), src->as_register()); | |
| 1111 break; | |
| 1112 | |
| 1113 default: | |
| 1114 ShouldNotReachHere(); | |
| 1115 } | |
| 1116 | |
| 1117 if (patch_code != lir_patch_none) { | |
| 1118 patching_epilog(patch, patch_code, to_addr->base()->as_register(), info); | |
| 1119 } | |
| 1120 } | |
| 1121 | |
| 1122 | |
| 1123 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) { | |
| 1124 assert(src->is_stack(), "should not call otherwise"); | |
| 1125 assert(dest->is_register(), "should not call otherwise"); | |
| 1126 | |
| 1127 if (dest->is_single_cpu()) { | |
| 1128 if (type == T_ARRAY || type == T_OBJECT) { | |
| 304 | 1129 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix())); |
| 0 | 1130 __ verify_oop(dest->as_register()); |
| 304 | 1131 } else { |
| 1132 __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix())); | |
| 0 | 1133 } |
| 1134 | |
| 1135 } else if (dest->is_double_cpu()) { | |
| 1136 Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes); | |
| 1137 Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes); | |
| 304 | 1138 __ movptr(dest->as_register_lo(), src_addr_LO); |
| 1139 NOT_LP64(__ movptr(dest->as_register_hi(), src_addr_HI)); | |
| 0 | 1140 |
| 1141 } else if (dest->is_single_xmm()) { | |
| 1142 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix()); | |
| 1143 __ movflt(dest->as_xmm_float_reg(), src_addr); | |
| 1144 | |
| 1145 } else if (dest->is_double_xmm()) { | |
| 1146 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix()); | |
| 1147 __ movdbl(dest->as_xmm_double_reg(), src_addr); | |
| 1148 | |
| 1149 } else if (dest->is_single_fpu()) { | |
| 1150 assert(dest->fpu_regnr() == 0, "dest must be TOS"); | |
| 1151 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix()); | |
| 1152 __ fld_s(src_addr); | |
| 1153 | |
| 1154 } else if (dest->is_double_fpu()) { | |
| 1155 assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); | |
| 1156 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix()); | |
| 1157 __ fld_d(src_addr); | |
| 1158 | |
| 1159 } else { | |
| 1160 ShouldNotReachHere(); | |
| 1161 } | |
| 1162 } | |
| 1163 | |
| 1164 | |
| 1165 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) { | |
| 1166 if (src->is_single_stack()) { | |
| 304 | 1167 if (type == T_OBJECT || type == T_ARRAY) { |
| 1168 __ pushptr(frame_map()->address_for_slot(src ->single_stack_ix())); | |
| 1169 __ popptr (frame_map()->address_for_slot(dest->single_stack_ix())); | |
| 1170 } else { | |
| 1060 | 1171 #ifndef _LP64 |
| 304 | 1172 __ pushl(frame_map()->address_for_slot(src ->single_stack_ix())); |
| 1173 __ popl (frame_map()->address_for_slot(dest->single_stack_ix())); | |
| 1060 | 1174 #else |
| 1175 //no pushl on 64bits | |
| 1176 __ movl(rscratch1, frame_map()->address_for_slot(src ->single_stack_ix())); | |
| 1177 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), rscratch1); | |
| 1178 #endif | |
| 304 | 1179 } |
| 0 | 1180 |
| 1181 } else if (src->is_double_stack()) { | |
| 304 | 1182 #ifdef _LP64 |
| 1183 __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix())); | |
| 1184 __ popptr (frame_map()->address_for_slot(dest->double_stack_ix())); | |
| 1185 #else | |
| 0 | 1186 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 0)); |
| 304 | 1187 // push and pop the part at src + wordSize, adding wordSize for the previous push |
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1188 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 2 * wordSize)); |
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1189 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 2 * wordSize)); |
| 0 | 1190 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 0)); |
| 304 | 1191 #endif // _LP64 |
| 0 | 1192 |
| 1193 } else { | |
| 1194 ShouldNotReachHere(); | |
| 1195 } | |
| 1196 } | |
| 1197 | |
| 1198 | |
| 1199 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool /* unaligned */) { | |
| 1200 assert(src->is_address(), "should not call otherwise"); | |
| 1201 assert(dest->is_register(), "should not call otherwise"); | |
| 1202 | |
| 1203 LIR_Address* addr = src->as_address_ptr(); | |
| 1204 Address from_addr = as_Address(addr); | |
| 1205 | |
| 1206 switch (type) { | |
| 1207 case T_BOOLEAN: // fall through | |
| 1208 case T_BYTE: // fall through | |
| 1209 case T_CHAR: // fall through | |
| 1210 case T_SHORT: | |
| 1211 if (!VM_Version::is_P6() && !from_addr.uses(dest->as_register())) { | |
| 1212 // on pre P6 processors we may get partial register stalls | |
| 1213 // so blow away the value of to_rinfo before loading a | |
| 1214 // partial word into it. Do it here so that it precedes | |
| 1215 // the potential patch point below. | |
| 304 | 1216 __ xorptr(dest->as_register(), dest->as_register()); |
| 0 | 1217 } |
| 1218 break; | |
| 1219 } | |
| 1220 | |
| 1221 PatchingStub* patch = NULL; | |
| 1222 if (patch_code != lir_patch_none) { | |
| 1223 patch = new PatchingStub(_masm, PatchingStub::access_field_id); | |
| 304 | 1224 assert(from_addr.disp() != 0, "must have"); |
| 0 | 1225 } |
| 1226 if (info != NULL) { | |
| 1227 add_debug_info_for_null_check_here(info); | |
| 1228 } | |
| 1229 | |
| 1230 switch (type) { | |
| 1231 case T_FLOAT: { | |
| 1232 if (dest->is_single_xmm()) { | |
| 1233 __ movflt(dest->as_xmm_float_reg(), from_addr); | |
| 1234 } else { | |
| 1235 assert(dest->is_single_fpu(), "must be"); | |
| 1236 assert(dest->fpu_regnr() == 0, "dest must be TOS"); | |
| 1237 __ fld_s(from_addr); | |
| 1238 } | |
| 1239 break; | |
| 1240 } | |
| 1241 | |
| 1242 case T_DOUBLE: { | |
| 1243 if (dest->is_double_xmm()) { | |
| 1244 __ movdbl(dest->as_xmm_double_reg(), from_addr); | |
| 1245 } else { | |
| 1246 assert(dest->is_double_fpu(), "must be"); | |
| 1247 assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); | |
| 1248 __ fld_d(from_addr); | |
| 1249 } | |
| 1250 break; | |
| 1251 } | |
| 1252 | |
| 1253 case T_ADDRESS: // fall through | |
| 1254 case T_OBJECT: // fall through | |
| 1255 case T_ARRAY: // fall through | |
| 304 | 1256 #ifdef _LP64 |
| 1257 __ movptr(dest->as_register(), from_addr); | |
| 1258 break; | |
| 1259 #endif // _L64 | |
| 0 | 1260 case T_INT: |
|
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314e17ca2c23
6946892: c1 shouldn't sign-extend to upper 32bits on x64
iveresov
parents:
1378
diff
changeset
|
1261 __ movl(dest->as_register(), from_addr); |
| 0 | 1262 break; |
| 1263 | |
| 1264 case T_LONG: { | |
| 1265 Register to_lo = dest->as_register_lo(); | |
| 1266 Register to_hi = dest->as_register_hi(); | |
| 304 | 1267 #ifdef _LP64 |
| 1268 __ movptr(to_lo, as_Address_lo(addr)); | |
| 1269 #else | |
| 0 | 1270 Register base = addr->base()->as_register(); |
| 1271 Register index = noreg; | |
| 1272 if (addr->index()->is_register()) { | |
| 1273 index = addr->index()->as_register(); | |
| 1274 } | |
| 1275 if ((base == to_lo && index == to_hi) || | |
| 1276 (base == to_hi && index == to_lo)) { | |
| 1277 // addresses with 2 registers are only formed as a result of | |
| 1278 // array access so this code will never have to deal with | |
| 1279 // patches or null checks. | |
| 1280 assert(info == NULL && patch == NULL, "must be"); | |
| 304 | 1281 __ lea(to_hi, as_Address(addr)); |
| 0 | 1282 __ movl(to_lo, Address(to_hi, 0)); |
| 1283 __ movl(to_hi, Address(to_hi, BytesPerWord)); | |
| 1284 } else if (base == to_lo || index == to_lo) { | |
| 1285 assert(base != to_hi, "can't be"); | |
| 1286 assert(index == noreg || (index != base && index != to_hi), "can't handle this"); | |
| 1287 __ movl(to_hi, as_Address_hi(addr)); | |
| 1288 if (patch != NULL) { | |
| 1289 patching_epilog(patch, lir_patch_high, base, info); | |
| 1290 patch = new PatchingStub(_masm, PatchingStub::access_field_id); | |
| 1291 patch_code = lir_patch_low; | |
| 1292 } | |
| 1293 __ movl(to_lo, as_Address_lo(addr)); | |
| 1294 } else { | |
| 1295 assert(index == noreg || (index != base && index != to_lo), "can't handle this"); | |
| 1296 __ movl(to_lo, as_Address_lo(addr)); | |
| 1297 if (patch != NULL) { | |
| 1298 patching_epilog(patch, lir_patch_low, base, info); | |
| 1299 patch = new PatchingStub(_masm, PatchingStub::access_field_id); | |
| 1300 patch_code = lir_patch_high; | |
| 1301 } | |
| 1302 __ movl(to_hi, as_Address_hi(addr)); | |
| 1303 } | |
| 304 | 1304 #endif // _LP64 |
| 0 | 1305 break; |
| 1306 } | |
| 1307 | |
| 1308 case T_BOOLEAN: // fall through | |
| 1309 case T_BYTE: { | |
| 1310 Register dest_reg = dest->as_register(); | |
| 1311 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6"); | |
| 1312 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { | |
| 304 | 1313 __ movsbl(dest_reg, from_addr); |
| 0 | 1314 } else { |
| 1315 __ movb(dest_reg, from_addr); | |
| 1316 __ shll(dest_reg, 24); | |
| 1317 __ sarl(dest_reg, 24); | |
| 1318 } | |
| 1319 break; | |
| 1320 } | |
| 1321 | |
| 1322 case T_CHAR: { | |
| 1323 Register dest_reg = dest->as_register(); | |
| 1324 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6"); | |
| 1325 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { | |
| 304 | 1326 __ movzwl(dest_reg, from_addr); |
| 0 | 1327 } else { |
| 1328 __ movw(dest_reg, from_addr); | |
| 1329 } | |
| 1330 break; | |
| 1331 } | |
| 1332 | |
| 1333 case T_SHORT: { | |
| 1334 Register dest_reg = dest->as_register(); | |
| 1335 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { | |
| 304 | 1336 __ movswl(dest_reg, from_addr); |
| 0 | 1337 } else { |
| 1338 __ movw(dest_reg, from_addr); | |
| 1339 __ shll(dest_reg, 16); | |
| 1340 __ sarl(dest_reg, 16); | |
| 1341 } | |
| 1342 break; | |
| 1343 } | |
| 1344 | |
| 1345 default: | |
| 1346 ShouldNotReachHere(); | |
| 1347 } | |
| 1348 | |
| 1349 if (patch != NULL) { | |
| 1350 patching_epilog(patch, patch_code, addr->base()->as_register(), info); | |
| 1351 } | |
| 1352 | |
| 1353 if (type == T_ARRAY || type == T_OBJECT) { | |
| 1354 __ verify_oop(dest->as_register()); | |
| 1355 } | |
| 1356 } | |
| 1357 | |
| 1358 | |
| 1359 void LIR_Assembler::prefetchr(LIR_Opr src) { | |
| 1360 LIR_Address* addr = src->as_address_ptr(); | |
| 1361 Address from_addr = as_Address(addr); | |
| 1362 | |
| 1363 if (VM_Version::supports_sse()) { | |
| 1364 switch (ReadPrefetchInstr) { | |
| 1365 case 0: | |
| 1366 __ prefetchnta(from_addr); break; | |
| 1367 case 1: | |
| 1368 __ prefetcht0(from_addr); break; | |
| 1369 case 2: | |
| 1370 __ prefetcht2(from_addr); break; | |
| 1371 default: | |
| 1372 ShouldNotReachHere(); break; | |
| 1373 } | |
| 1374 } else if (VM_Version::supports_3dnow()) { | |
| 1375 __ prefetchr(from_addr); | |
| 1376 } | |
| 1377 } | |
| 1378 | |
| 1379 | |
| 1380 void LIR_Assembler::prefetchw(LIR_Opr src) { | |
| 1381 LIR_Address* addr = src->as_address_ptr(); | |
| 1382 Address from_addr = as_Address(addr); | |
| 1383 | |
| 1384 if (VM_Version::supports_sse()) { | |
| 1385 switch (AllocatePrefetchInstr) { | |
| 1386 case 0: | |
| 1387 __ prefetchnta(from_addr); break; | |
| 1388 case 1: | |
| 1389 __ prefetcht0(from_addr); break; | |
| 1390 case 2: | |
| 1391 __ prefetcht2(from_addr); break; | |
| 1392 case 3: | |
| 1393 __ prefetchw(from_addr); break; | |
| 1394 default: | |
| 1395 ShouldNotReachHere(); break; | |
| 1396 } | |
| 1397 } else if (VM_Version::supports_3dnow()) { | |
| 1398 __ prefetchw(from_addr); | |
| 1399 } | |
| 1400 } | |
| 1401 | |
| 1402 | |
| 1403 NEEDS_CLEANUP; // This could be static? | |
| 1404 Address::ScaleFactor LIR_Assembler::array_element_size(BasicType type) const { | |
|
29
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6633953: type2aelembytes{T_ADDRESS} should be 8 bytes in 64 bit VM
kvn
parents:
0
diff
changeset
|
1405 int elem_size = type2aelembytes(type); |
| 0 | 1406 switch (elem_size) { |
| 1407 case 1: return Address::times_1; | |
| 1408 case 2: return Address::times_2; | |
| 1409 case 4: return Address::times_4; | |
| 1410 case 8: return Address::times_8; | |
| 1411 } | |
| 1412 ShouldNotReachHere(); | |
| 1413 return Address::no_scale; | |
| 1414 } | |
| 1415 | |
| 1416 | |
| 1417 void LIR_Assembler::emit_op3(LIR_Op3* op) { | |
| 1418 switch (op->code()) { | |
| 1419 case lir_idiv: | |
| 1420 case lir_irem: | |
| 1421 arithmetic_idiv(op->code(), | |
| 1422 op->in_opr1(), | |
| 1423 op->in_opr2(), | |
| 1424 op->in_opr3(), | |
| 1425 op->result_opr(), | |
| 1426 op->info()); | |
| 1427 break; | |
| 1428 default: ShouldNotReachHere(); break; | |
| 1429 } | |
| 1430 } | |
| 1431 | |
| 1432 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) { | |
| 1433 #ifdef ASSERT | |
| 1434 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label"); | |
| 1435 if (op->block() != NULL) _branch_target_blocks.append(op->block()); | |
| 1436 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock()); | |
| 1437 #endif | |
| 1438 | |
| 1439 if (op->cond() == lir_cond_always) { | |
| 1440 if (op->info() != NULL) add_debug_info_for_branch(op->info()); | |
| 1441 __ jmp (*(op->label())); | |
| 1442 } else { | |
| 1443 Assembler::Condition acond = Assembler::zero; | |
| 1444 if (op->code() == lir_cond_float_branch) { | |
| 1445 assert(op->ublock() != NULL, "must have unordered successor"); | |
| 1446 __ jcc(Assembler::parity, *(op->ublock()->label())); | |
| 1447 switch(op->cond()) { | |
| 1448 case lir_cond_equal: acond = Assembler::equal; break; | |
| 1449 case lir_cond_notEqual: acond = Assembler::notEqual; break; | |
| 1450 case lir_cond_less: acond = Assembler::below; break; | |
| 1451 case lir_cond_lessEqual: acond = Assembler::belowEqual; break; | |
| 1452 case lir_cond_greaterEqual: acond = Assembler::aboveEqual; break; | |
| 1453 case lir_cond_greater: acond = Assembler::above; break; | |
| 1454 default: ShouldNotReachHere(); | |
| 1455 } | |
| 1456 } else { | |
| 1457 switch (op->cond()) { | |
| 1458 case lir_cond_equal: acond = Assembler::equal; break; | |
| 1459 case lir_cond_notEqual: acond = Assembler::notEqual; break; | |
| 1460 case lir_cond_less: acond = Assembler::less; break; | |
| 1461 case lir_cond_lessEqual: acond = Assembler::lessEqual; break; | |
| 1462 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break; | |
| 1463 case lir_cond_greater: acond = Assembler::greater; break; | |
| 1464 case lir_cond_belowEqual: acond = Assembler::belowEqual; break; | |
| 1465 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break; | |
| 1466 default: ShouldNotReachHere(); | |
| 1467 } | |
| 1468 } | |
| 1469 __ jcc(acond,*(op->label())); | |
| 1470 } | |
| 1471 } | |
| 1472 | |
| 1473 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) { | |
| 1474 LIR_Opr src = op->in_opr(); | |
| 1475 LIR_Opr dest = op->result_opr(); | |
| 1476 | |
| 1477 switch (op->bytecode()) { | |
| 1478 case Bytecodes::_i2l: | |
| 304 | 1479 #ifdef _LP64 |
| 1480 __ movl2ptr(dest->as_register_lo(), src->as_register()); | |
| 1481 #else | |
| 0 | 1482 move_regs(src->as_register(), dest->as_register_lo()); |
| 1483 move_regs(src->as_register(), dest->as_register_hi()); | |
| 1484 __ sarl(dest->as_register_hi(), 31); | |
| 304 | 1485 #endif // LP64 |
| 0 | 1486 break; |
| 1487 | |
| 1488 case Bytecodes::_l2i: | |
| 1489 move_regs(src->as_register_lo(), dest->as_register()); | |
| 1490 break; | |
| 1491 | |
| 1492 case Bytecodes::_i2b: | |
| 1493 move_regs(src->as_register(), dest->as_register()); | |
| 1494 __ sign_extend_byte(dest->as_register()); | |
| 1495 break; | |
| 1496 | |
| 1497 case Bytecodes::_i2c: | |
| 1498 move_regs(src->as_register(), dest->as_register()); | |
| 1499 __ andl(dest->as_register(), 0xFFFF); | |
| 1500 break; | |
| 1501 | |
| 1502 case Bytecodes::_i2s: | |
| 1503 move_regs(src->as_register(), dest->as_register()); | |
| 1504 __ sign_extend_short(dest->as_register()); | |
| 1505 break; | |
| 1506 | |
| 1507 | |
| 1508 case Bytecodes::_f2d: | |
| 1509 case Bytecodes::_d2f: | |
| 1510 if (dest->is_single_xmm()) { | |
| 1511 __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg()); | |
| 1512 } else if (dest->is_double_xmm()) { | |
| 1513 __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg()); | |
| 1514 } else { | |
| 1515 assert(src->fpu() == dest->fpu(), "register must be equal"); | |
| 1516 // do nothing (float result is rounded later through spilling) | |
| 1517 } | |
| 1518 break; | |
| 1519 | |
| 1520 case Bytecodes::_i2f: | |
| 1521 case Bytecodes::_i2d: | |
| 1522 if (dest->is_single_xmm()) { | |
| 304 | 1523 __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register()); |
| 0 | 1524 } else if (dest->is_double_xmm()) { |
| 304 | 1525 __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register()); |
| 0 | 1526 } else { |
| 1527 assert(dest->fpu() == 0, "result must be on TOS"); | |
| 1528 __ movl(Address(rsp, 0), src->as_register()); | |
| 1529 __ fild_s(Address(rsp, 0)); | |
| 1530 } | |
| 1531 break; | |
| 1532 | |
| 1533 case Bytecodes::_f2i: | |
| 1534 case Bytecodes::_d2i: | |
| 1535 if (src->is_single_xmm()) { | |
| 304 | 1536 __ cvttss2sil(dest->as_register(), src->as_xmm_float_reg()); |
| 0 | 1537 } else if (src->is_double_xmm()) { |
| 304 | 1538 __ cvttsd2sil(dest->as_register(), src->as_xmm_double_reg()); |
| 0 | 1539 } else { |
| 1540 assert(src->fpu() == 0, "input must be on TOS"); | |
| 1541 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc())); | |
| 1542 __ fist_s(Address(rsp, 0)); | |
| 1543 __ movl(dest->as_register(), Address(rsp, 0)); | |
| 1544 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); | |
| 1545 } | |
| 1546 | |
| 1547 // IA32 conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub | |
| 1548 assert(op->stub() != NULL, "stub required"); | |
| 1549 __ cmpl(dest->as_register(), 0x80000000); | |
| 1550 __ jcc(Assembler::equal, *op->stub()->entry()); | |
| 1551 __ bind(*op->stub()->continuation()); | |
| 1552 break; | |
| 1553 | |
| 1554 case Bytecodes::_l2f: | |
| 1555 case Bytecodes::_l2d: | |
| 1556 assert(!dest->is_xmm_register(), "result in xmm register not supported (no SSE instruction present)"); | |
| 1557 assert(dest->fpu() == 0, "result must be on TOS"); | |
| 1558 | |
| 304 | 1559 __ movptr(Address(rsp, 0), src->as_register_lo()); |
| 1560 NOT_LP64(__ movl(Address(rsp, BytesPerWord), src->as_register_hi())); | |
| 0 | 1561 __ fild_d(Address(rsp, 0)); |
| 1562 // float result is rounded later through spilling | |
| 1563 break; | |
| 1564 | |
| 1565 case Bytecodes::_f2l: | |
| 1566 case Bytecodes::_d2l: | |
| 1567 assert(!src->is_xmm_register(), "input in xmm register not supported (no SSE instruction present)"); | |
| 1568 assert(src->fpu() == 0, "input must be on TOS"); | |
| 304 | 1569 assert(dest == FrameMap::long0_opr, "runtime stub places result in these registers"); |
| 0 | 1570 |
| 1571 // instruction sequence too long to inline it here | |
| 1572 { | |
| 1573 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::fpu2long_stub_id))); | |
| 1574 } | |
| 1575 break; | |
| 1576 | |
| 1577 default: ShouldNotReachHere(); | |
| 1578 } | |
| 1579 } | |
| 1580 | |
| 1581 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) { | |
| 1582 if (op->init_check()) { | |
| 1583 __ cmpl(Address(op->klass()->as_register(), | |
| 1584 instanceKlass::init_state_offset_in_bytes() + sizeof(oopDesc)), | |
| 1585 instanceKlass::fully_initialized); | |
| 1586 add_debug_info_for_null_check_here(op->stub()->info()); | |
| 1587 __ jcc(Assembler::notEqual, *op->stub()->entry()); | |
| 1588 } | |
| 1589 __ allocate_object(op->obj()->as_register(), | |
| 1590 op->tmp1()->as_register(), | |
| 1591 op->tmp2()->as_register(), | |
| 1592 op->header_size(), | |
| 1593 op->object_size(), | |
| 1594 op->klass()->as_register(), | |
| 1595 *op->stub()->entry()); | |
| 1596 __ bind(*op->stub()->continuation()); | |
| 1597 } | |
| 1598 | |
| 1599 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) { | |
| 1600 if (UseSlowPath || | |
| 1601 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) || | |
| 1602 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) { | |
| 1603 __ jmp(*op->stub()->entry()); | |
| 1604 } else { | |
| 1605 Register len = op->len()->as_register(); | |
| 1606 Register tmp1 = op->tmp1()->as_register(); | |
| 1607 Register tmp2 = op->tmp2()->as_register(); | |
| 1608 Register tmp3 = op->tmp3()->as_register(); | |
| 1609 if (len == tmp1) { | |
| 1610 tmp1 = tmp3; | |
| 1611 } else if (len == tmp2) { | |
| 1612 tmp2 = tmp3; | |
| 1613 } else if (len == tmp3) { | |
| 1614 // everything is ok | |
| 1615 } else { | |
| 304 | 1616 __ mov(tmp3, len); |
| 0 | 1617 } |
| 1618 __ allocate_array(op->obj()->as_register(), | |
| 1619 len, | |
| 1620 tmp1, | |
| 1621 tmp2, | |
| 1622 arrayOopDesc::header_size(op->type()), | |
| 1623 array_element_size(op->type()), | |
| 1624 op->klass()->as_register(), | |
| 1625 *op->stub()->entry()); | |
| 1626 } | |
| 1627 __ bind(*op->stub()->continuation()); | |
| 1628 } | |
| 1629 | |
| 1783 | 1630 void LIR_Assembler::type_profile_helper(Register mdo, |
| 1631 ciMethodData *md, ciProfileData *data, | |
| 1632 Register recv, Label* update_done) { | |
|
1808
5511edd5d719
6988779: c1_LIRAssembler_x86.cpp crashes VS2010 compiler
iveresov
parents:
1791
diff
changeset
|
1633 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) { |
| 1783 | 1634 Label next_test; |
| 1635 // See if the receiver is receiver[n]. | |
| 1636 __ cmpptr(recv, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)))); | |
| 1637 __ jccb(Assembler::notEqual, next_test); | |
| 1638 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))); | |
| 1639 __ addptr(data_addr, DataLayout::counter_increment); | |
|
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3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1640 __ jmp(*update_done); |
| 1783 | 1641 __ bind(next_test); |
| 1642 } | |
| 1643 | |
| 1644 // Didn't find receiver; find next empty slot and fill it in | |
|
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6988779: c1_LIRAssembler_x86.cpp crashes VS2010 compiler
iveresov
parents:
1791
diff
changeset
|
1645 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) { |
| 1783 | 1646 Label next_test; |
| 1647 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))); | |
| 1648 __ cmpptr(recv_addr, (intptr_t)NULL_WORD); | |
| 1649 __ jccb(Assembler::notEqual, next_test); | |
| 1650 __ movptr(recv_addr, recv); | |
| 1651 __ movptr(Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))), DataLayout::counter_increment); | |
|
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6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1652 __ jmp(*update_done); |
| 1783 | 1653 __ bind(next_test); |
| 1654 } | |
| 1655 } | |
| 1656 | |
|
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1657 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) { |
| 1783 | 1658 // we always need a stub for the failure case. |
| 1659 CodeStub* stub = op->stub(); | |
| 1660 Register obj = op->object()->as_register(); | |
| 1661 Register k_RInfo = op->tmp1()->as_register(); | |
| 1662 Register klass_RInfo = op->tmp2()->as_register(); | |
| 1663 Register dst = op->result_opr()->as_register(); | |
| 1664 ciKlass* k = op->klass(); | |
| 1665 Register Rtmp1 = noreg; | |
| 1666 | |
| 1667 // check if it needs to be profiled | |
| 1668 ciMethodData* md; | |
| 1669 ciProfileData* data; | |
| 1670 | |
| 1671 if (op->should_profile()) { | |
| 1672 ciMethod* method = op->profiled_method(); | |
| 1673 assert(method != NULL, "Should have method"); | |
| 1674 int bci = op->profiled_bci(); | |
| 1675 md = method->method_data(); | |
| 1676 if (md == NULL) { | |
| 1677 bailout("out of memory building methodDataOop"); | |
| 1678 return; | |
| 1679 } | |
| 1680 data = md->bci_to_data(bci); | |
|
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6919069: client compiler needs to capture more profile information for tiered work
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parents:
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diff
changeset
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1681 assert(data != NULL, "need data for type check"); |
|
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
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diff
changeset
|
1682 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check"); |
| 1783 | 1683 } |
|
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1684 Label profile_cast_success, profile_cast_failure; |
|
3a294e483abc
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diff
changeset
|
1685 Label *success_target = op->should_profile() ? &profile_cast_success : success; |
|
3a294e483abc
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1686 Label *failure_target = op->should_profile() ? &profile_cast_failure : failure; |
| 1783 | 1687 |
| 1688 if (obj == k_RInfo) { | |
| 1689 k_RInfo = dst; | |
| 1690 } else if (obj == klass_RInfo) { | |
| 1691 klass_RInfo = dst; | |
| 1692 } | |
| 1693 if (k->is_loaded()) { | |
| 1694 select_different_registers(obj, dst, k_RInfo, klass_RInfo); | |
| 1695 } else { | |
| 1696 Rtmp1 = op->tmp3()->as_register(); | |
| 1697 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1); | |
| 1698 } | |
| 1699 | |
| 1700 assert_different_registers(obj, k_RInfo, klass_RInfo); | |
| 1701 if (!k->is_loaded()) { | |
| 1702 jobject2reg_with_patching(k_RInfo, op->info_for_patch()); | |
| 1703 } else { | |
| 1704 #ifdef _LP64 | |
| 1705 __ movoop(k_RInfo, k->constant_encoding()); | |
| 1706 #endif // _LP64 | |
| 1707 } | |
| 1708 assert(obj != k_RInfo, "must be different"); | |
| 1709 | |
| 1710 __ cmpptr(obj, (int32_t)NULL_WORD); | |
| 1711 if (op->should_profile()) { | |
|
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1712 Label not_null; |
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1713 __ jccb(Assembler::notEqual, not_null); |
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1714 // Object is null; update MDO and exit |
| 1783 | 1715 Register mdo = klass_RInfo; |
| 1716 __ movoop(mdo, md->constant_encoding()); | |
| 1717 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset())); | |
| 1718 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant()); | |
| 1719 __ orl(data_addr, header_bits); | |
|
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1720 __ jmp(*obj_is_null); |
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1721 __ bind(not_null); |
| 1783 | 1722 } else { |
|
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1723 __ jcc(Assembler::equal, *obj_is_null); |
| 1783 | 1724 } |
| 1725 __ verify_oop(obj); | |
| 1726 | |
| 1727 if (op->fast_check()) { | |
|
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1728 // get object class |
| 1783 | 1729 // not a safepoint as obj null check happens earlier |
| 1730 if (k->is_loaded()) { | |
| 1731 #ifdef _LP64 | |
| 1732 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); | |
| 1733 #else | |
| 1734 __ cmpoop(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding()); | |
| 1735 #endif // _LP64 | |
| 1736 } else { | |
| 1737 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); | |
| 1738 } | |
| 1739 __ jcc(Assembler::notEqual, *failure_target); | |
|
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1740 // successful cast, fall through to profile or jump |
| 1783 | 1741 } else { |
| 1742 // get object class | |
| 1743 // not a safepoint as obj null check happens earlier | |
| 1744 __ movptr(klass_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); | |
| 1745 if (k->is_loaded()) { | |
| 1746 // See if we get an immediate positive hit | |
| 1747 #ifdef _LP64 | |
| 1748 __ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset())); | |
| 1749 #else | |
| 1750 __ cmpoop(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding()); | |
| 1751 #endif // _LP64 | |
| 1752 if (sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes() != k->super_check_offset()) { | |
| 1753 __ jcc(Assembler::notEqual, *failure_target); | |
|
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1754 // successful cast, fall through to profile or jump |
| 1783 | 1755 } else { |
| 1756 // See if we get an immediate positive hit | |
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1757 __ jcc(Assembler::equal, *success_target); |
| 1783 | 1758 // check for self |
| 1759 #ifdef _LP64 | |
| 1760 __ cmpptr(klass_RInfo, k_RInfo); | |
| 1761 #else | |
| 1762 __ cmpoop(klass_RInfo, k->constant_encoding()); | |
| 1763 #endif // _LP64 | |
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1764 __ jcc(Assembler::equal, *success_target); |
| 1783 | 1765 |
| 1766 __ push(klass_RInfo); | |
| 1767 #ifdef _LP64 | |
| 1768 __ push(k_RInfo); | |
| 1769 #else | |
| 1770 __ pushoop(k->constant_encoding()); | |
| 1771 #endif // _LP64 | |
| 1772 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); | |
| 1773 __ pop(klass_RInfo); | |
| 1774 __ pop(klass_RInfo); | |
| 1775 // result is a boolean | |
| 1776 __ cmpl(klass_RInfo, 0); | |
| 1777 __ jcc(Assembler::equal, *failure_target); | |
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1778 // successful cast, fall through to profile or jump |
| 1783 | 1779 } |
| 1780 } else { | |
| 1781 // perform the fast part of the checking logic | |
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1782 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL); |
| 1783 | 1783 // call out-of-line instance of __ check_klass_subtype_slow_path(...): |
| 1784 __ push(klass_RInfo); | |
| 1785 __ push(k_RInfo); | |
| 1786 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); | |
| 1787 __ pop(klass_RInfo); | |
| 1788 __ pop(k_RInfo); | |
| 1789 // result is a boolean | |
| 1790 __ cmpl(k_RInfo, 0); | |
| 1791 __ jcc(Assembler::equal, *failure_target); | |
|
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1792 // successful cast, fall through to profile or jump |
| 1783 | 1793 } |
| 1794 } | |
| 1795 if (op->should_profile()) { | |
| 1796 Register mdo = klass_RInfo, recv = k_RInfo; | |
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1797 __ bind(profile_cast_success); |
| 1783 | 1798 __ movoop(mdo, md->constant_encoding()); |
| 1799 __ movptr(recv, Address(obj, oopDesc::klass_offset_in_bytes())); | |
| 1800 Label update_done; | |
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1801 type_profile_helper(mdo, md, data, recv, success); |
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1802 __ jmp(*success); |
| 1783 | 1803 |
| 1804 __ bind(profile_cast_failure); | |
| 1805 __ movoop(mdo, md->constant_encoding()); | |
| 1806 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); | |
| 1807 __ subptr(counter_addr, DataLayout::counter_increment); | |
|
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1808 __ jmp(*failure); |
| 1783 | 1809 } |
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1810 __ jmp(*success); |
| 1783 | 1811 } |
| 0 | 1812 |
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1813 |
| 0 | 1814 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) { |
| 1815 LIR_Code code = op->code(); | |
| 1816 if (code == lir_store_check) { | |
| 1817 Register value = op->object()->as_register(); | |
| 1818 Register array = op->array()->as_register(); | |
| 1819 Register k_RInfo = op->tmp1()->as_register(); | |
| 1820 Register klass_RInfo = op->tmp2()->as_register(); | |
| 1821 Register Rtmp1 = op->tmp3()->as_register(); | |
| 1822 | |
| 1823 CodeStub* stub = op->stub(); | |
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1824 |
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1825 // check if it needs to be profiled |
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1826 ciMethodData* md; |
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1827 ciProfileData* data; |
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1828 |
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1829 if (op->should_profile()) { |
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1830 ciMethod* method = op->profiled_method(); |
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1831 assert(method != NULL, "Should have method"); |
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1832 int bci = op->profiled_bci(); |
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1833 md = method->method_data(); |
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1834 if (md == NULL) { |
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1835 bailout("out of memory building methodDataOop"); |
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1836 return; |
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1837 } |
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1838 data = md->bci_to_data(bci); |
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1839 assert(data != NULL, "need data for type check"); |
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1840 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check"); |
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1841 } |
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1842 Label profile_cast_success, profile_cast_failure, done; |
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1843 Label *success_target = op->should_profile() ? &profile_cast_success : &done; |
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1844 Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry(); |
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1845 |
| 304 | 1846 __ cmpptr(value, (int32_t)NULL_WORD); |
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1847 if (op->should_profile()) { |
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1848 Label not_null; |
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1849 __ jccb(Assembler::notEqual, not_null); |
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1850 // Object is null; update MDO and exit |
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1851 Register mdo = klass_RInfo; |
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1852 __ movoop(mdo, md->constant_encoding()); |
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1853 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset())); |
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1854 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant()); |
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1855 __ orl(data_addr, header_bits); |
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1856 __ jmp(done); |
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1857 __ bind(not_null); |
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1858 } else { |
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1859 __ jcc(Assembler::equal, done); |
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1860 } |
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1861 |
| 0 | 1862 add_debug_info_for_null_check_here(op->info_for_exception()); |
| 304 | 1863 __ movptr(k_RInfo, Address(array, oopDesc::klass_offset_in_bytes())); |
| 1864 __ movptr(klass_RInfo, Address(value, oopDesc::klass_offset_in_bytes())); | |
| 0 | 1865 |
| 1866 // get instance klass | |
| 304 | 1867 __ movptr(k_RInfo, Address(k_RInfo, objArrayKlass::element_klass_offset_in_bytes() + sizeof(oopDesc))); |
|
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1868 // perform the fast part of the checking logic |
|
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1869 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL); |
|
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1870 // call out-of-line instance of __ check_klass_subtype_slow_path(...): |
| 304 | 1871 __ push(klass_RInfo); |
| 1872 __ push(k_RInfo); | |
| 0 | 1873 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); |
| 304 | 1874 __ pop(klass_RInfo); |
| 1875 __ pop(k_RInfo); | |
| 1876 // result is a boolean | |
| 0 | 1877 __ cmpl(k_RInfo, 0); |
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1878 __ jcc(Assembler::equal, *failure_target); |
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1879 // fall through to the success case |
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1880 |
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1881 if (op->should_profile()) { |
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1882 Register mdo = klass_RInfo, recv = k_RInfo; |
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1883 __ bind(profile_cast_success); |
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1884 __ movoop(mdo, md->constant_encoding()); |
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1885 __ movptr(recv, Address(value, oopDesc::klass_offset_in_bytes())); |
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1886 Label update_done; |
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1887 type_profile_helper(mdo, md, data, recv, &done); |
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1888 __ jmpb(done); |
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1889 |
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1890 __ bind(profile_cast_failure); |
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1891 __ movoop(mdo, md->constant_encoding()); |
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1892 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); |
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1893 __ subptr(counter_addr, DataLayout::counter_increment); |
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1894 __ jmp(*stub->entry()); |
| 0 | 1895 } |
|
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1896 |
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1897 __ bind(done); |
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1898 } else |
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1899 if (code == lir_checkcast) { |
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1900 Register obj = op->object()->as_register(); |
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1901 Register dst = op->result_opr()->as_register(); |
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1902 Label success; |
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1903 emit_typecheck_helper(op, &success, op->stub()->entry(), &success); |
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1904 __ bind(success); |
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1905 if (dst != obj) { |
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1906 __ mov(dst, obj); |
| 0 | 1907 } |
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1908 } else |
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1909 if (code == lir_instanceof) { |
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1910 Register obj = op->object()->as_register(); |
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1911 Register dst = op->result_opr()->as_register(); |
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1912 Label success, failure, done; |
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1913 emit_typecheck_helper(op, &success, &failure, &failure); |
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1914 __ bind(failure); |
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1915 __ xorptr(dst, dst); |
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1916 __ jmpb(done); |
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1917 __ bind(success); |
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1918 __ movptr(dst, 1); |
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1919 __ bind(done); |
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1920 } else { |
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1921 ShouldNotReachHere(); |
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1922 } |
| 0 | 1923 |
| 1924 } | |
| 1925 | |
| 1926 | |
| 1927 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) { | |
| 304 | 1928 if (LP64_ONLY(false &&) op->code() == lir_cas_long && VM_Version::supports_cx8()) { |
| 0 | 1929 assert(op->cmp_value()->as_register_lo() == rax, "wrong register"); |
| 1930 assert(op->cmp_value()->as_register_hi() == rdx, "wrong register"); | |
| 1931 assert(op->new_value()->as_register_lo() == rbx, "wrong register"); | |
| 1932 assert(op->new_value()->as_register_hi() == rcx, "wrong register"); | |
| 1933 Register addr = op->addr()->as_register(); | |
| 1934 if (os::is_MP()) { | |
| 1935 __ lock(); | |
| 1936 } | |
| 304 | 1937 NOT_LP64(__ cmpxchg8(Address(addr, 0))); |
| 1938 | |
| 1939 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj ) { | |
| 1940 NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");) | |
| 1941 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo()); | |
| 0 | 1942 Register newval = op->new_value()->as_register(); |
| 1943 Register cmpval = op->cmp_value()->as_register(); | |
| 1944 assert(cmpval == rax, "wrong register"); | |
| 1945 assert(newval != NULL, "new val must be register"); | |
| 1946 assert(cmpval != newval, "cmp and new values must be in different registers"); | |
| 1947 assert(cmpval != addr, "cmp and addr must be in different registers"); | |
| 1948 assert(newval != addr, "new value and addr must be in different registers"); | |
| 1949 if (os::is_MP()) { | |
| 1950 __ lock(); | |
| 1951 } | |
| 304 | 1952 if ( op->code() == lir_cas_obj) { |
| 1953 __ cmpxchgptr(newval, Address(addr, 0)); | |
| 1954 } else if (op->code() == lir_cas_int) { | |
| 1955 __ cmpxchgl(newval, Address(addr, 0)); | |
| 1956 } | |
| 1957 #ifdef _LP64 | |
| 1958 } else if (op->code() == lir_cas_long) { | |
| 1959 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo()); | |
| 1960 Register newval = op->new_value()->as_register_lo(); | |
| 1961 Register cmpval = op->cmp_value()->as_register_lo(); | |
| 1962 assert(cmpval == rax, "wrong register"); | |
| 1963 assert(newval != NULL, "new val must be register"); | |
| 1964 assert(cmpval != newval, "cmp and new values must be in different registers"); | |
| 1965 assert(cmpval != addr, "cmp and addr must be in different registers"); | |
| 1966 assert(newval != addr, "new value and addr must be in different registers"); | |
| 1967 if (os::is_MP()) { | |
| 1968 __ lock(); | |
| 1969 } | |
| 1970 __ cmpxchgq(newval, Address(addr, 0)); | |
| 1971 #endif // _LP64 | |
| 0 | 1972 } else { |
| 1973 Unimplemented(); | |
| 1974 } | |
| 1975 } | |
| 1976 | |
| 1977 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result) { | |
| 1978 Assembler::Condition acond, ncond; | |
| 1979 switch (condition) { | |
| 1980 case lir_cond_equal: acond = Assembler::equal; ncond = Assembler::notEqual; break; | |
| 1981 case lir_cond_notEqual: acond = Assembler::notEqual; ncond = Assembler::equal; break; | |
| 1982 case lir_cond_less: acond = Assembler::less; ncond = Assembler::greaterEqual; break; | |
| 1983 case lir_cond_lessEqual: acond = Assembler::lessEqual; ncond = Assembler::greater; break; | |
| 1984 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; ncond = Assembler::less; break; | |
| 1985 case lir_cond_greater: acond = Assembler::greater; ncond = Assembler::lessEqual; break; | |
| 1986 case lir_cond_belowEqual: acond = Assembler::belowEqual; ncond = Assembler::above; break; | |
| 1987 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; ncond = Assembler::below; break; | |
| 1988 default: ShouldNotReachHere(); | |
| 1989 } | |
| 1990 | |
| 1991 if (opr1->is_cpu_register()) { | |
| 1992 reg2reg(opr1, result); | |
| 1993 } else if (opr1->is_stack()) { | |
| 1994 stack2reg(opr1, result, result->type()); | |
| 1995 } else if (opr1->is_constant()) { | |
| 1996 const2reg(opr1, result, lir_patch_none, NULL); | |
| 1997 } else { | |
| 1998 ShouldNotReachHere(); | |
| 1999 } | |
| 2000 | |
| 2001 if (VM_Version::supports_cmov() && !opr2->is_constant()) { | |
| 2002 // optimized version that does not require a branch | |
| 2003 if (opr2->is_single_cpu()) { | |
| 2004 assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move"); | |
| 304 | 2005 __ cmov(ncond, result->as_register(), opr2->as_register()); |
| 0 | 2006 } else if (opr2->is_double_cpu()) { |
| 2007 assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move"); | |
| 2008 assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move"); | |
| 304 | 2009 __ cmovptr(ncond, result->as_register_lo(), opr2->as_register_lo()); |
| 2010 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), opr2->as_register_hi());) | |
| 0 | 2011 } else if (opr2->is_single_stack()) { |
| 2012 __ cmovl(ncond, result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix())); | |
| 2013 } else if (opr2->is_double_stack()) { | |
| 304 | 2014 __ cmovptr(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes)); |
| 2015 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), frame_map()->address_for_slot(opr2->double_stack_ix(), hi_word_offset_in_bytes));) | |
| 0 | 2016 } else { |
| 2017 ShouldNotReachHere(); | |
| 2018 } | |
| 2019 | |
| 2020 } else { | |
| 2021 Label skip; | |
| 2022 __ jcc (acond, skip); | |
| 2023 if (opr2->is_cpu_register()) { | |
| 2024 reg2reg(opr2, result); | |
| 2025 } else if (opr2->is_stack()) { | |
| 2026 stack2reg(opr2, result, result->type()); | |
| 2027 } else if (opr2->is_constant()) { | |
| 2028 const2reg(opr2, result, lir_patch_none, NULL); | |
| 2029 } else { | |
| 2030 ShouldNotReachHere(); | |
| 2031 } | |
| 2032 __ bind(skip); | |
| 2033 } | |
| 2034 } | |
| 2035 | |
| 2036 | |
| 2037 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) { | |
| 2038 assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method"); | |
| 2039 | |
| 2040 if (left->is_single_cpu()) { | |
| 2041 assert(left == dest, "left and dest must be equal"); | |
| 2042 Register lreg = left->as_register(); | |
| 2043 | |
| 2044 if (right->is_single_cpu()) { | |
| 2045 // cpu register - cpu register | |
| 2046 Register rreg = right->as_register(); | |
| 2047 switch (code) { | |
| 2048 case lir_add: __ addl (lreg, rreg); break; | |
| 2049 case lir_sub: __ subl (lreg, rreg); break; | |
| 2050 case lir_mul: __ imull(lreg, rreg); break; | |
| 2051 default: ShouldNotReachHere(); | |
| 2052 } | |
| 2053 | |
| 2054 } else if (right->is_stack()) { | |
| 2055 // cpu register - stack | |
| 2056 Address raddr = frame_map()->address_for_slot(right->single_stack_ix()); | |
| 2057 switch (code) { | |
| 2058 case lir_add: __ addl(lreg, raddr); break; | |
| 2059 case lir_sub: __ subl(lreg, raddr); break; | |
| 2060 default: ShouldNotReachHere(); | |
| 2061 } | |
| 2062 | |
| 2063 } else if (right->is_constant()) { | |
| 2064 // cpu register - constant | |
| 2065 jint c = right->as_constant_ptr()->as_jint(); | |
| 2066 switch (code) { | |
| 2067 case lir_add: { | |
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2068 __ incrementl(lreg, c); |
| 0 | 2069 break; |
| 2070 } | |
| 2071 case lir_sub: { | |
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2072 __ decrementl(lreg, c); |
| 0 | 2073 break; |
| 2074 } | |
| 2075 default: ShouldNotReachHere(); | |
| 2076 } | |
| 2077 | |
| 2078 } else { | |
| 2079 ShouldNotReachHere(); | |
| 2080 } | |
| 2081 | |
| 2082 } else if (left->is_double_cpu()) { | |
| 2083 assert(left == dest, "left and dest must be equal"); | |
| 2084 Register lreg_lo = left->as_register_lo(); | |
| 2085 Register lreg_hi = left->as_register_hi(); | |
| 2086 | |
| 2087 if (right->is_double_cpu()) { | |
| 2088 // cpu register - cpu register | |
| 2089 Register rreg_lo = right->as_register_lo(); | |
| 2090 Register rreg_hi = right->as_register_hi(); | |
| 304 | 2091 NOT_LP64(assert_different_registers(lreg_lo, lreg_hi, rreg_lo, rreg_hi)); |
| 2092 LP64_ONLY(assert_different_registers(lreg_lo, rreg_lo)); | |
| 0 | 2093 switch (code) { |
| 2094 case lir_add: | |
| 304 | 2095 __ addptr(lreg_lo, rreg_lo); |
| 2096 NOT_LP64(__ adcl(lreg_hi, rreg_hi)); | |
| 0 | 2097 break; |
| 2098 case lir_sub: | |
| 304 | 2099 __ subptr(lreg_lo, rreg_lo); |
| 2100 NOT_LP64(__ sbbl(lreg_hi, rreg_hi)); | |
| 0 | 2101 break; |
| 2102 case lir_mul: | |
| 304 | 2103 #ifdef _LP64 |
| 2104 __ imulq(lreg_lo, rreg_lo); | |
| 2105 #else | |
| 0 | 2106 assert(lreg_lo == rax && lreg_hi == rdx, "must be"); |
| 2107 __ imull(lreg_hi, rreg_lo); | |
| 2108 __ imull(rreg_hi, lreg_lo); | |
| 2109 __ addl (rreg_hi, lreg_hi); | |
| 2110 __ mull (rreg_lo); | |
| 2111 __ addl (lreg_hi, rreg_hi); | |
| 304 | 2112 #endif // _LP64 |
| 0 | 2113 break; |
| 2114 default: | |
| 2115 ShouldNotReachHere(); | |
| 2116 } | |
| 2117 | |
| 2118 } else if (right->is_constant()) { | |
| 2119 // cpu register - constant | |
| 304 | 2120 #ifdef _LP64 |
| 2121 jlong c = right->as_constant_ptr()->as_jlong_bits(); | |
| 2122 __ movptr(r10, (intptr_t) c); | |
| 2123 switch (code) { | |
| 2124 case lir_add: | |
| 2125 __ addptr(lreg_lo, r10); | |
| 2126 break; | |
| 2127 case lir_sub: | |
| 2128 __ subptr(lreg_lo, r10); | |
| 2129 break; | |
| 2130 default: | |
| 2131 ShouldNotReachHere(); | |
| 2132 } | |
| 2133 #else | |
| 0 | 2134 jint c_lo = right->as_constant_ptr()->as_jint_lo(); |
| 2135 jint c_hi = right->as_constant_ptr()->as_jint_hi(); | |
| 2136 switch (code) { | |
| 2137 case lir_add: | |
| 304 | 2138 __ addptr(lreg_lo, c_lo); |
| 0 | 2139 __ adcl(lreg_hi, c_hi); |
| 2140 break; | |
| 2141 case lir_sub: | |
| 304 | 2142 __ subptr(lreg_lo, c_lo); |
| 0 | 2143 __ sbbl(lreg_hi, c_hi); |
| 2144 break; | |
| 2145 default: | |
| 2146 ShouldNotReachHere(); | |
| 2147 } | |
| 304 | 2148 #endif // _LP64 |
| 0 | 2149 |
| 2150 } else { | |
| 2151 ShouldNotReachHere(); | |
| 2152 } | |
| 2153 | |
| 2154 } else if (left->is_single_xmm()) { | |
| 2155 assert(left == dest, "left and dest must be equal"); | |
| 2156 XMMRegister lreg = left->as_xmm_float_reg(); | |
| 2157 | |
| 2158 if (right->is_single_xmm()) { | |
| 2159 XMMRegister rreg = right->as_xmm_float_reg(); | |
| 2160 switch (code) { | |
| 2161 case lir_add: __ addss(lreg, rreg); break; | |
| 2162 case lir_sub: __ subss(lreg, rreg); break; | |
| 2163 case lir_mul_strictfp: // fall through | |
| 2164 case lir_mul: __ mulss(lreg, rreg); break; | |
| 2165 case lir_div_strictfp: // fall through | |
| 2166 case lir_div: __ divss(lreg, rreg); break; | |
| 2167 default: ShouldNotReachHere(); | |
| 2168 } | |
| 2169 } else { | |
| 2170 Address raddr; | |
| 2171 if (right->is_single_stack()) { | |
| 2172 raddr = frame_map()->address_for_slot(right->single_stack_ix()); | |
| 2173 } else if (right->is_constant()) { | |
| 2174 // hack for now | |
| 2175 raddr = __ as_Address(InternalAddress(float_constant(right->as_jfloat()))); | |
| 2176 } else { | |
| 2177 ShouldNotReachHere(); | |
| 2178 } | |
| 2179 switch (code) { | |
| 2180 case lir_add: __ addss(lreg, raddr); break; | |
| 2181 case lir_sub: __ subss(lreg, raddr); break; | |
| 2182 case lir_mul_strictfp: // fall through | |
| 2183 case lir_mul: __ mulss(lreg, raddr); break; | |
| 2184 case lir_div_strictfp: // fall through | |
| 2185 case lir_div: __ divss(lreg, raddr); break; | |
| 2186 default: ShouldNotReachHere(); | |
| 2187 } | |
| 2188 } | |
| 2189 | |
| 2190 } else if (left->is_double_xmm()) { | |
| 2191 assert(left == dest, "left and dest must be equal"); | |
| 2192 | |
| 2193 XMMRegister lreg = left->as_xmm_double_reg(); | |
| 2194 if (right->is_double_xmm()) { | |
| 2195 XMMRegister rreg = right->as_xmm_double_reg(); | |
| 2196 switch (code) { | |
| 2197 case lir_add: __ addsd(lreg, rreg); break; | |
| 2198 case lir_sub: __ subsd(lreg, rreg); break; | |
| 2199 case lir_mul_strictfp: // fall through | |
| 2200 case lir_mul: __ mulsd(lreg, rreg); break; | |
| 2201 case lir_div_strictfp: // fall through | |
| 2202 case lir_div: __ divsd(lreg, rreg); break; | |
| 2203 default: ShouldNotReachHere(); | |
| 2204 } | |
| 2205 } else { | |
| 2206 Address raddr; | |
| 2207 if (right->is_double_stack()) { | |
| 2208 raddr = frame_map()->address_for_slot(right->double_stack_ix()); | |
| 2209 } else if (right->is_constant()) { | |
| 2210 // hack for now | |
| 2211 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble()))); | |
| 2212 } else { | |
| 2213 ShouldNotReachHere(); | |
| 2214 } | |
| 2215 switch (code) { | |
| 2216 case lir_add: __ addsd(lreg, raddr); break; | |
| 2217 case lir_sub: __ subsd(lreg, raddr); break; | |
| 2218 case lir_mul_strictfp: // fall through | |
| 2219 case lir_mul: __ mulsd(lreg, raddr); break; | |
| 2220 case lir_div_strictfp: // fall through | |
| 2221 case lir_div: __ divsd(lreg, raddr); break; | |
| 2222 default: ShouldNotReachHere(); | |
| 2223 } | |
| 2224 } | |
| 2225 | |
| 2226 } else if (left->is_single_fpu()) { | |
| 2227 assert(dest->is_single_fpu(), "fpu stack allocation required"); | |
| 2228 | |
| 2229 if (right->is_single_fpu()) { | |
| 2230 arith_fpu_implementation(code, left->fpu_regnr(), right->fpu_regnr(), dest->fpu_regnr(), pop_fpu_stack); | |
| 2231 | |
| 2232 } else { | |
| 2233 assert(left->fpu_regnr() == 0, "left must be on TOS"); | |
| 2234 assert(dest->fpu_regnr() == 0, "dest must be on TOS"); | |
| 2235 | |
| 2236 Address raddr; | |
| 2237 if (right->is_single_stack()) { | |
| 2238 raddr = frame_map()->address_for_slot(right->single_stack_ix()); | |
| 2239 } else if (right->is_constant()) { | |
| 2240 address const_addr = float_constant(right->as_jfloat()); | |
| 2241 assert(const_addr != NULL, "incorrect float/double constant maintainance"); | |
| 2242 // hack for now | |
| 2243 raddr = __ as_Address(InternalAddress(const_addr)); | |
| 2244 } else { | |
| 2245 ShouldNotReachHere(); | |
| 2246 } | |
| 2247 | |
| 2248 switch (code) { | |
| 2249 case lir_add: __ fadd_s(raddr); break; | |
| 2250 case lir_sub: __ fsub_s(raddr); break; | |
| 2251 case lir_mul_strictfp: // fall through | |
| 2252 case lir_mul: __ fmul_s(raddr); break; | |
| 2253 case lir_div_strictfp: // fall through | |
| 2254 case lir_div: __ fdiv_s(raddr); break; | |
| 2255 default: ShouldNotReachHere(); | |
| 2256 } | |
| 2257 } | |
| 2258 | |
| 2259 } else if (left->is_double_fpu()) { | |
| 2260 assert(dest->is_double_fpu(), "fpu stack allocation required"); | |
| 2261 | |
| 2262 if (code == lir_mul_strictfp || code == lir_div_strictfp) { | |
| 2263 // Double values require special handling for strictfp mul/div on x86 | |
| 2264 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias1())); | |
| 2265 __ fmulp(left->fpu_regnrLo() + 1); | |
| 2266 } | |
| 2267 | |
| 2268 if (right->is_double_fpu()) { | |
| 2269 arith_fpu_implementation(code, left->fpu_regnrLo(), right->fpu_regnrLo(), dest->fpu_regnrLo(), pop_fpu_stack); | |
| 2270 | |
| 2271 } else { | |
| 2272 assert(left->fpu_regnrLo() == 0, "left must be on TOS"); | |
| 2273 assert(dest->fpu_regnrLo() == 0, "dest must be on TOS"); | |
| 2274 | |
| 2275 Address raddr; | |
| 2276 if (right->is_double_stack()) { | |
| 2277 raddr = frame_map()->address_for_slot(right->double_stack_ix()); | |
| 2278 } else if (right->is_constant()) { | |
| 2279 // hack for now | |
| 2280 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble()))); | |
| 2281 } else { | |
| 2282 ShouldNotReachHere(); | |
| 2283 } | |
| 2284 | |
| 2285 switch (code) { | |
| 2286 case lir_add: __ fadd_d(raddr); break; | |
| 2287 case lir_sub: __ fsub_d(raddr); break; | |
| 2288 case lir_mul_strictfp: // fall through | |
| 2289 case lir_mul: __ fmul_d(raddr); break; | |
| 2290 case lir_div_strictfp: // fall through | |
| 2291 case lir_div: __ fdiv_d(raddr); break; | |
| 2292 default: ShouldNotReachHere(); | |
| 2293 } | |
| 2294 } | |
| 2295 | |
| 2296 if (code == lir_mul_strictfp || code == lir_div_strictfp) { | |
| 2297 // Double values require special handling for strictfp mul/div on x86 | |
| 2298 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias2())); | |
| 2299 __ fmulp(dest->fpu_regnrLo() + 1); | |
| 2300 } | |
| 2301 | |
| 2302 } else if (left->is_single_stack() || left->is_address()) { | |
| 2303 assert(left == dest, "left and dest must be equal"); | |
| 2304 | |
| 2305 Address laddr; | |
| 2306 if (left->is_single_stack()) { | |
| 2307 laddr = frame_map()->address_for_slot(left->single_stack_ix()); | |
| 2308 } else if (left->is_address()) { | |
| 2309 laddr = as_Address(left->as_address_ptr()); | |
| 2310 } else { | |
| 2311 ShouldNotReachHere(); | |
| 2312 } | |
| 2313 | |
| 2314 if (right->is_single_cpu()) { | |
| 2315 Register rreg = right->as_register(); | |
| 2316 switch (code) { | |
| 2317 case lir_add: __ addl(laddr, rreg); break; | |
| 2318 case lir_sub: __ subl(laddr, rreg); break; | |
| 2319 default: ShouldNotReachHere(); | |
| 2320 } | |
| 2321 } else if (right->is_constant()) { | |
| 2322 jint c = right->as_constant_ptr()->as_jint(); | |
| 2323 switch (code) { | |
| 2324 case lir_add: { | |
| 304 | 2325 __ incrementl(laddr, c); |
| 0 | 2326 break; |
| 2327 } | |
| 2328 case lir_sub: { | |
| 304 | 2329 __ decrementl(laddr, c); |
| 0 | 2330 break; |
| 2331 } | |
| 2332 default: ShouldNotReachHere(); | |
| 2333 } | |
| 2334 } else { | |
| 2335 ShouldNotReachHere(); | |
| 2336 } | |
| 2337 | |
| 2338 } else { | |
| 2339 ShouldNotReachHere(); | |
| 2340 } | |
| 2341 } | |
| 2342 | |
| 2343 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) { | |
| 2344 assert(pop_fpu_stack || (left_index == dest_index || right_index == dest_index), "invalid LIR"); | |
| 2345 assert(!pop_fpu_stack || (left_index - 1 == dest_index || right_index - 1 == dest_index), "invalid LIR"); | |
| 2346 assert(left_index == 0 || right_index == 0, "either must be on top of stack"); | |
| 2347 | |
| 2348 bool left_is_tos = (left_index == 0); | |
| 2349 bool dest_is_tos = (dest_index == 0); | |
| 2350 int non_tos_index = (left_is_tos ? right_index : left_index); | |
| 2351 | |
| 2352 switch (code) { | |
| 2353 case lir_add: | |
| 2354 if (pop_fpu_stack) __ faddp(non_tos_index); | |
| 2355 else if (dest_is_tos) __ fadd (non_tos_index); | |
| 2356 else __ fadda(non_tos_index); | |
| 2357 break; | |
| 2358 | |
| 2359 case lir_sub: | |
| 2360 if (left_is_tos) { | |
| 2361 if (pop_fpu_stack) __ fsubrp(non_tos_index); | |
| 2362 else if (dest_is_tos) __ fsub (non_tos_index); | |
| 2363 else __ fsubra(non_tos_index); | |
| 2364 } else { | |
| 2365 if (pop_fpu_stack) __ fsubp (non_tos_index); | |
| 2366 else if (dest_is_tos) __ fsubr (non_tos_index); | |
| 2367 else __ fsuba (non_tos_index); | |
| 2368 } | |
| 2369 break; | |
| 2370 | |
| 2371 case lir_mul_strictfp: // fall through | |
| 2372 case lir_mul: | |
| 2373 if (pop_fpu_stack) __ fmulp(non_tos_index); | |
| 2374 else if (dest_is_tos) __ fmul (non_tos_index); | |
| 2375 else __ fmula(non_tos_index); | |
| 2376 break; | |
| 2377 | |
| 2378 case lir_div_strictfp: // fall through | |
| 2379 case lir_div: | |
| 2380 if (left_is_tos) { | |
| 2381 if (pop_fpu_stack) __ fdivrp(non_tos_index); | |
| 2382 else if (dest_is_tos) __ fdiv (non_tos_index); | |
| 2383 else __ fdivra(non_tos_index); | |
| 2384 } else { | |
| 2385 if (pop_fpu_stack) __ fdivp (non_tos_index); | |
| 2386 else if (dest_is_tos) __ fdivr (non_tos_index); | |
| 2387 else __ fdiva (non_tos_index); | |
| 2388 } | |
| 2389 break; | |
| 2390 | |
| 2391 case lir_rem: | |
| 2392 assert(left_is_tos && dest_is_tos && right_index == 1, "must be guaranteed by FPU stack allocation"); | |
| 2393 __ fremr(noreg); | |
| 2394 break; | |
| 2395 | |
| 2396 default: | |
| 2397 ShouldNotReachHere(); | |
| 2398 } | |
| 2399 } | |
| 2400 | |
| 2401 | |
| 2402 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op) { | |
| 2403 if (value->is_double_xmm()) { | |
| 2404 switch(code) { | |
| 2405 case lir_abs : | |
| 2406 { | |
| 2407 if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) { | |
| 2408 __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); | |
| 2409 } | |
| 2410 __ andpd(dest->as_xmm_double_reg(), | |
| 2411 ExternalAddress((address)double_signmask_pool)); | |
| 2412 } | |
| 2413 break; | |
| 2414 | |
| 2415 case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break; | |
| 2416 // all other intrinsics are not available in the SSE instruction set, so FPU is used | |
| 2417 default : ShouldNotReachHere(); | |
| 2418 } | |
| 2419 | |
| 2420 } else if (value->is_double_fpu()) { | |
| 2421 assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS"); | |
| 2422 switch(code) { | |
| 2423 case lir_log : __ flog() ; break; | |
| 2424 case lir_log10 : __ flog10() ; break; | |
| 2425 case lir_abs : __ fabs() ; break; | |
| 2426 case lir_sqrt : __ fsqrt(); break; | |
| 2427 case lir_sin : | |
| 2428 // Should consider not saving rbx, if not necessary | |
| 2429 __ trigfunc('s', op->as_Op2()->fpu_stack_size()); | |
| 2430 break; | |
| 2431 case lir_cos : | |
| 2432 // Should consider not saving rbx, if not necessary | |
| 2433 assert(op->as_Op2()->fpu_stack_size() <= 6, "sin and cos need two free stack slots"); | |
| 2434 __ trigfunc('c', op->as_Op2()->fpu_stack_size()); | |
| 2435 break; | |
| 2436 case lir_tan : | |
| 2437 // Should consider not saving rbx, if not necessary | |
| 2438 __ trigfunc('t', op->as_Op2()->fpu_stack_size()); | |
| 2439 break; | |
| 2440 default : ShouldNotReachHere(); | |
| 2441 } | |
| 2442 } else { | |
| 2443 Unimplemented(); | |
| 2444 } | |
| 2445 } | |
| 2446 | |
| 2447 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) { | |
| 2448 // assert(left->destroys_register(), "check"); | |
| 2449 if (left->is_single_cpu()) { | |
| 2450 Register reg = left->as_register(); | |
| 2451 if (right->is_constant()) { | |
| 2452 int val = right->as_constant_ptr()->as_jint(); | |
| 2453 switch (code) { | |
| 2454 case lir_logic_and: __ andl (reg, val); break; | |
| 2455 case lir_logic_or: __ orl (reg, val); break; | |
| 2456 case lir_logic_xor: __ xorl (reg, val); break; | |
| 2457 default: ShouldNotReachHere(); | |
| 2458 } | |
| 2459 } else if (right->is_stack()) { | |
| 2460 // added support for stack operands | |
| 2461 Address raddr = frame_map()->address_for_slot(right->single_stack_ix()); | |
| 2462 switch (code) { | |
| 2463 case lir_logic_and: __ andl (reg, raddr); break; | |
| 2464 case lir_logic_or: __ orl (reg, raddr); break; | |
| 2465 case lir_logic_xor: __ xorl (reg, raddr); break; | |
| 2466 default: ShouldNotReachHere(); | |
| 2467 } | |
| 2468 } else { | |
| 2469 Register rright = right->as_register(); | |
| 2470 switch (code) { | |
| 304 | 2471 case lir_logic_and: __ andptr (reg, rright); break; |
| 2472 case lir_logic_or : __ orptr (reg, rright); break; | |
| 2473 case lir_logic_xor: __ xorptr (reg, rright); break; | |
| 0 | 2474 default: ShouldNotReachHere(); |
| 2475 } | |
| 2476 } | |
| 2477 move_regs(reg, dst->as_register()); | |
| 2478 } else { | |
| 2479 Register l_lo = left->as_register_lo(); | |
| 2480 Register l_hi = left->as_register_hi(); | |
| 2481 if (right->is_constant()) { | |
| 304 | 2482 #ifdef _LP64 |
| 2483 __ mov64(rscratch1, right->as_constant_ptr()->as_jlong()); | |
| 2484 switch (code) { | |
| 2485 case lir_logic_and: | |
| 2486 __ andq(l_lo, rscratch1); | |
| 2487 break; | |
| 2488 case lir_logic_or: | |
| 2489 __ orq(l_lo, rscratch1); | |
| 2490 break; | |
| 2491 case lir_logic_xor: | |
| 2492 __ xorq(l_lo, rscratch1); | |
| 2493 break; | |
| 2494 default: ShouldNotReachHere(); | |
| 2495 } | |
| 2496 #else | |
| 0 | 2497 int r_lo = right->as_constant_ptr()->as_jint_lo(); |
| 2498 int r_hi = right->as_constant_ptr()->as_jint_hi(); | |
| 2499 switch (code) { | |
| 2500 case lir_logic_and: | |
| 2501 __ andl(l_lo, r_lo); | |
| 2502 __ andl(l_hi, r_hi); | |
| 2503 break; | |
| 2504 case lir_logic_or: | |
| 2505 __ orl(l_lo, r_lo); | |
| 2506 __ orl(l_hi, r_hi); | |
| 2507 break; | |
| 2508 case lir_logic_xor: | |
| 2509 __ xorl(l_lo, r_lo); | |
| 2510 __ xorl(l_hi, r_hi); | |
| 2511 break; | |
| 2512 default: ShouldNotReachHere(); | |
| 2513 } | |
| 304 | 2514 #endif // _LP64 |
| 0 | 2515 } else { |
| 1572 | 2516 #ifdef _LP64 |
| 2517 Register r_lo; | |
| 2518 if (right->type() == T_OBJECT || right->type() == T_ARRAY) { | |
| 2519 r_lo = right->as_register(); | |
| 2520 } else { | |
| 2521 r_lo = right->as_register_lo(); | |
| 2522 } | |
| 2523 #else | |
| 0 | 2524 Register r_lo = right->as_register_lo(); |
| 2525 Register r_hi = right->as_register_hi(); | |
| 2526 assert(l_lo != r_hi, "overwriting registers"); | |
| 1572 | 2527 #endif |
| 0 | 2528 switch (code) { |
| 2529 case lir_logic_and: | |
| 304 | 2530 __ andptr(l_lo, r_lo); |
| 2531 NOT_LP64(__ andptr(l_hi, r_hi);) | |
| 0 | 2532 break; |
| 2533 case lir_logic_or: | |
| 304 | 2534 __ orptr(l_lo, r_lo); |
| 2535 NOT_LP64(__ orptr(l_hi, r_hi);) | |
| 0 | 2536 break; |
| 2537 case lir_logic_xor: | |
| 304 | 2538 __ xorptr(l_lo, r_lo); |
| 2539 NOT_LP64(__ xorptr(l_hi, r_hi);) | |
| 0 | 2540 break; |
| 2541 default: ShouldNotReachHere(); | |
| 2542 } | |
| 2543 } | |
| 2544 | |
| 2545 Register dst_lo = dst->as_register_lo(); | |
| 2546 Register dst_hi = dst->as_register_hi(); | |
| 2547 | |
| 304 | 2548 #ifdef _LP64 |
| 2549 move_regs(l_lo, dst_lo); | |
| 2550 #else | |
| 0 | 2551 if (dst_lo == l_hi) { |
| 2552 assert(dst_hi != l_lo, "overwriting registers"); | |
| 2553 move_regs(l_hi, dst_hi); | |
| 2554 move_regs(l_lo, dst_lo); | |
| 2555 } else { | |
| 2556 assert(dst_lo != l_hi, "overwriting registers"); | |
| 2557 move_regs(l_lo, dst_lo); | |
| 2558 move_regs(l_hi, dst_hi); | |
| 2559 } | |
| 304 | 2560 #endif // _LP64 |
| 0 | 2561 } |
| 2562 } | |
| 2563 | |
| 2564 | |
| 2565 // we assume that rax, and rdx can be overwritten | |
| 2566 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) { | |
| 2567 | |
| 2568 assert(left->is_single_cpu(), "left must be register"); | |
| 2569 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant"); | |
| 2570 assert(result->is_single_cpu(), "result must be register"); | |
| 2571 | |
| 2572 // assert(left->destroys_register(), "check"); | |
| 2573 // assert(right->destroys_register(), "check"); | |
| 2574 | |
| 2575 Register lreg = left->as_register(); | |
| 2576 Register dreg = result->as_register(); | |
| 2577 | |
| 2578 if (right->is_constant()) { | |
| 2579 int divisor = right->as_constant_ptr()->as_jint(); | |
| 2580 assert(divisor > 0 && is_power_of_2(divisor), "must be"); | |
| 2581 if (code == lir_idiv) { | |
| 2582 assert(lreg == rax, "must be rax,"); | |
| 2583 assert(temp->as_register() == rdx, "tmp register must be rdx"); | |
| 2584 __ cdql(); // sign extend into rdx:rax | |
| 2585 if (divisor == 2) { | |
| 2586 __ subl(lreg, rdx); | |
| 2587 } else { | |
| 2588 __ andl(rdx, divisor - 1); | |
| 2589 __ addl(lreg, rdx); | |
| 2590 } | |
| 2591 __ sarl(lreg, log2_intptr(divisor)); | |
| 2592 move_regs(lreg, dreg); | |
| 2593 } else if (code == lir_irem) { | |
| 2594 Label done; | |
| 304 | 2595 __ mov(dreg, lreg); |
| 0 | 2596 __ andl(dreg, 0x80000000 | (divisor - 1)); |
| 2597 __ jcc(Assembler::positive, done); | |
| 2598 __ decrement(dreg); | |
| 2599 __ orl(dreg, ~(divisor - 1)); | |
| 2600 __ increment(dreg); | |
| 2601 __ bind(done); | |
| 2602 } else { | |
| 2603 ShouldNotReachHere(); | |
| 2604 } | |
| 2605 } else { | |
| 2606 Register rreg = right->as_register(); | |
| 2607 assert(lreg == rax, "left register must be rax,"); | |
| 2608 assert(rreg != rdx, "right register must not be rdx"); | |
| 2609 assert(temp->as_register() == rdx, "tmp register must be rdx"); | |
| 2610 | |
| 2611 move_regs(lreg, rax); | |
| 2612 | |
| 2613 int idivl_offset = __ corrected_idivl(rreg); | |
| 2614 add_debug_info_for_div0(idivl_offset, info); | |
| 2615 if (code == lir_irem) { | |
| 2616 move_regs(rdx, dreg); // result is in rdx | |
| 2617 } else { | |
| 2618 move_regs(rax, dreg); | |
| 2619 } | |
| 2620 } | |
| 2621 } | |
| 2622 | |
| 2623 | |
| 2624 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) { | |
| 2625 if (opr1->is_single_cpu()) { | |
| 2626 Register reg1 = opr1->as_register(); | |
| 2627 if (opr2->is_single_cpu()) { | |
| 2628 // cpu register - cpu register | |
| 304 | 2629 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) { |
| 2630 __ cmpptr(reg1, opr2->as_register()); | |
| 2631 } else { | |
| 2632 assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY, "cmp int, oop?"); | |
| 2633 __ cmpl(reg1, opr2->as_register()); | |
| 2634 } | |
| 0 | 2635 } else if (opr2->is_stack()) { |
| 2636 // cpu register - stack | |
| 304 | 2637 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) { |
| 2638 __ cmpptr(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); | |
| 2639 } else { | |
| 2640 __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); | |
| 2641 } | |
| 0 | 2642 } else if (opr2->is_constant()) { |
| 2643 // cpu register - constant | |
| 2644 LIR_Const* c = opr2->as_constant_ptr(); | |
| 2645 if (c->type() == T_INT) { | |
| 2646 __ cmpl(reg1, c->as_jint()); | |
| 304 | 2647 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) { |
| 2648 // In 64bit oops are single register | |
| 0 | 2649 jobject o = c->as_jobject(); |
| 2650 if (o == NULL) { | |
| 304 | 2651 __ cmpptr(reg1, (int32_t)NULL_WORD); |
| 0 | 2652 } else { |
| 304 | 2653 #ifdef _LP64 |
| 2654 __ movoop(rscratch1, o); | |
| 2655 __ cmpptr(reg1, rscratch1); | |
| 2656 #else | |
| 0 | 2657 __ cmpoop(reg1, c->as_jobject()); |
| 304 | 2658 #endif // _LP64 |
| 0 | 2659 } |
| 2660 } else { | |
| 2661 ShouldNotReachHere(); | |
| 2662 } | |
| 2663 // cpu register - address | |
| 2664 } else if (opr2->is_address()) { | |
| 2665 if (op->info() != NULL) { | |
| 2666 add_debug_info_for_null_check_here(op->info()); | |
| 2667 } | |
| 2668 __ cmpl(reg1, as_Address(opr2->as_address_ptr())); | |
| 2669 } else { | |
| 2670 ShouldNotReachHere(); | |
| 2671 } | |
| 2672 | |
| 2673 } else if(opr1->is_double_cpu()) { | |
| 2674 Register xlo = opr1->as_register_lo(); | |
| 2675 Register xhi = opr1->as_register_hi(); | |
| 2676 if (opr2->is_double_cpu()) { | |
| 304 | 2677 #ifdef _LP64 |
| 2678 __ cmpptr(xlo, opr2->as_register_lo()); | |
| 2679 #else | |
| 0 | 2680 // cpu register - cpu register |
| 2681 Register ylo = opr2->as_register_lo(); | |
| 2682 Register yhi = opr2->as_register_hi(); | |
| 2683 __ subl(xlo, ylo); | |
| 2684 __ sbbl(xhi, yhi); | |
| 2685 if (condition == lir_cond_equal || condition == lir_cond_notEqual) { | |
| 2686 __ orl(xhi, xlo); | |
| 2687 } | |
| 304 | 2688 #endif // _LP64 |
| 0 | 2689 } else if (opr2->is_constant()) { |
| 2690 // cpu register - constant 0 | |
| 2691 assert(opr2->as_jlong() == (jlong)0, "only handles zero"); | |
| 304 | 2692 #ifdef _LP64 |
| 2693 __ cmpptr(xlo, (int32_t)opr2->as_jlong()); | |
| 2694 #else | |
| 0 | 2695 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles equals case"); |
| 2696 __ orl(xhi, xlo); | |
| 304 | 2697 #endif // _LP64 |
| 0 | 2698 } else { |
| 2699 ShouldNotReachHere(); | |
| 2700 } | |
| 2701 | |
| 2702 } else if (opr1->is_single_xmm()) { | |
| 2703 XMMRegister reg1 = opr1->as_xmm_float_reg(); | |
| 2704 if (opr2->is_single_xmm()) { | |
| 2705 // xmm register - xmm register | |
| 2706 __ ucomiss(reg1, opr2->as_xmm_float_reg()); | |
| 2707 } else if (opr2->is_stack()) { | |
| 2708 // xmm register - stack | |
| 2709 __ ucomiss(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); | |
| 2710 } else if (opr2->is_constant()) { | |
| 2711 // xmm register - constant | |
| 2712 __ ucomiss(reg1, InternalAddress(float_constant(opr2->as_jfloat()))); | |
| 2713 } else if (opr2->is_address()) { | |
| 2714 // xmm register - address | |
| 2715 if (op->info() != NULL) { | |
| 2716 add_debug_info_for_null_check_here(op->info()); | |
| 2717 } | |
| 2718 __ ucomiss(reg1, as_Address(opr2->as_address_ptr())); | |
| 2719 } else { | |
| 2720 ShouldNotReachHere(); | |
| 2721 } | |
| 2722 | |
| 2723 } else if (opr1->is_double_xmm()) { | |
| 2724 XMMRegister reg1 = opr1->as_xmm_double_reg(); | |
| 2725 if (opr2->is_double_xmm()) { | |
| 2726 // xmm register - xmm register | |
| 2727 __ ucomisd(reg1, opr2->as_xmm_double_reg()); | |
| 2728 } else if (opr2->is_stack()) { | |
| 2729 // xmm register - stack | |
| 2730 __ ucomisd(reg1, frame_map()->address_for_slot(opr2->double_stack_ix())); | |
| 2731 } else if (opr2->is_constant()) { | |
| 2732 // xmm register - constant | |
| 2733 __ ucomisd(reg1, InternalAddress(double_constant(opr2->as_jdouble()))); | |
| 2734 } else if (opr2->is_address()) { | |
| 2735 // xmm register - address | |
| 2736 if (op->info() != NULL) { | |
| 2737 add_debug_info_for_null_check_here(op->info()); | |
| 2738 } | |
| 2739 __ ucomisd(reg1, as_Address(opr2->pointer()->as_address())); | |
| 2740 } else { | |
| 2741 ShouldNotReachHere(); | |
| 2742 } | |
| 2743 | |
| 2744 } else if(opr1->is_single_fpu() || opr1->is_double_fpu()) { | |
| 2745 assert(opr1->is_fpu_register() && opr1->fpu() == 0, "currently left-hand side must be on TOS (relax this restriction)"); | |
| 2746 assert(opr2->is_fpu_register(), "both must be registers"); | |
| 2747 __ fcmp(noreg, opr2->fpu(), op->fpu_pop_count() > 0, op->fpu_pop_count() > 1); | |
| 2748 | |
| 2749 } else if (opr1->is_address() && opr2->is_constant()) { | |
| 304 | 2750 LIR_Const* c = opr2->as_constant_ptr(); |
| 2751 #ifdef _LP64 | |
| 2752 if (c->type() == T_OBJECT || c->type() == T_ARRAY) { | |
| 2753 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse"); | |
| 2754 __ movoop(rscratch1, c->as_jobject()); | |
| 2755 } | |
| 2756 #endif // LP64 | |
| 0 | 2757 if (op->info() != NULL) { |
| 2758 add_debug_info_for_null_check_here(op->info()); | |
| 2759 } | |
| 2760 // special case: address - constant | |
| 2761 LIR_Address* addr = opr1->as_address_ptr(); | |
| 2762 if (c->type() == T_INT) { | |
| 2763 __ cmpl(as_Address(addr), c->as_jint()); | |
| 304 | 2764 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) { |
| 2765 #ifdef _LP64 | |
| 2766 // %%% Make this explode if addr isn't reachable until we figure out a | |
| 2767 // better strategy by giving noreg as the temp for as_Address | |
| 2768 __ cmpptr(rscratch1, as_Address(addr, noreg)); | |
| 2769 #else | |
| 0 | 2770 __ cmpoop(as_Address(addr), c->as_jobject()); |
| 304 | 2771 #endif // _LP64 |
| 0 | 2772 } else { |
| 2773 ShouldNotReachHere(); | |
| 2774 } | |
| 2775 | |
| 2776 } else { | |
| 2777 ShouldNotReachHere(); | |
| 2778 } | |
| 2779 } | |
| 2780 | |
| 2781 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) { | |
| 2782 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) { | |
| 2783 if (left->is_single_xmm()) { | |
| 2784 assert(right->is_single_xmm(), "must match"); | |
| 2785 __ cmpss2int(left->as_xmm_float_reg(), right->as_xmm_float_reg(), dst->as_register(), code == lir_ucmp_fd2i); | |
| 2786 } else if (left->is_double_xmm()) { | |
| 2787 assert(right->is_double_xmm(), "must match"); | |
| 2788 __ cmpsd2int(left->as_xmm_double_reg(), right->as_xmm_double_reg(), dst->as_register(), code == lir_ucmp_fd2i); | |
| 2789 | |
| 2790 } else { | |
| 2791 assert(left->is_single_fpu() || left->is_double_fpu(), "must be"); | |
| 2792 assert(right->is_single_fpu() || right->is_double_fpu(), "must match"); | |
| 2793 | |
| 2794 assert(left->fpu() == 0, "left must be on TOS"); | |
| 2795 __ fcmp2int(dst->as_register(), code == lir_ucmp_fd2i, right->fpu(), | |
| 2796 op->fpu_pop_count() > 0, op->fpu_pop_count() > 1); | |
| 2797 } | |
| 2798 } else { | |
| 2799 assert(code == lir_cmp_l2i, "check"); | |
| 304 | 2800 #ifdef _LP64 |
| 1369 | 2801 Label done; |
| 2802 Register dest = dst->as_register(); | |
| 2803 __ cmpptr(left->as_register_lo(), right->as_register_lo()); | |
| 2804 __ movl(dest, -1); | |
| 2805 __ jccb(Assembler::less, done); | |
| 2806 __ set_byte_if_not_zero(dest); | |
| 2807 __ movzbl(dest, dest); | |
| 2808 __ bind(done); | |
| 304 | 2809 #else |
| 0 | 2810 __ lcmp2int(left->as_register_hi(), |
| 2811 left->as_register_lo(), | |
| 2812 right->as_register_hi(), | |
| 2813 right->as_register_lo()); | |
| 2814 move_regs(left->as_register_hi(), dst->as_register()); | |
| 304 | 2815 #endif // _LP64 |
| 0 | 2816 } |
| 2817 } | |
| 2818 | |
| 2819 | |
| 2820 void LIR_Assembler::align_call(LIR_Code code) { | |
| 2821 if (os::is_MP()) { | |
| 2822 // make sure that the displacement word of the call ends up word aligned | |
| 2823 int offset = __ offset(); | |
| 2824 switch (code) { | |
| 2825 case lir_static_call: | |
| 2826 case lir_optvirtual_call: | |
| 1295 | 2827 case lir_dynamic_call: |
| 0 | 2828 offset += NativeCall::displacement_offset; |
| 2829 break; | |
| 2830 case lir_icvirtual_call: | |
| 2831 offset += NativeCall::displacement_offset + NativeMovConstReg::instruction_size; | |
| 2832 break; | |
| 2833 case lir_virtual_call: // currently, sparc-specific for niagara | |
| 2834 default: ShouldNotReachHere(); | |
| 2835 } | |
| 2836 while (offset++ % BytesPerWord != 0) { | |
| 2837 __ nop(); | |
| 2838 } | |
| 2839 } | |
| 2840 } | |
| 2841 | |
| 2842 | |
| 1295 | 2843 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) { |
| 0 | 2844 assert(!os::is_MP() || (__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0, |
| 2845 "must be aligned"); | |
| 1295 | 2846 __ call(AddressLiteral(op->addr(), rtype)); |
| 1564 | 2847 add_call_info(code_offset(), op->info()); |
| 0 | 2848 } |
| 2849 | |
| 2850 | |
| 1295 | 2851 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) { |
| 0 | 2852 RelocationHolder rh = virtual_call_Relocation::spec(pc()); |
| 2853 __ movoop(IC_Klass, (jobject)Universe::non_oop_word()); | |
| 2854 assert(!os::is_MP() || | |
| 2855 (__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0, | |
| 2856 "must be aligned"); | |
| 1295 | 2857 __ call(AddressLiteral(op->addr(), rh)); |
| 1564 | 2858 add_call_info(code_offset(), op->info()); |
| 0 | 2859 } |
| 2860 | |
| 2861 | |
| 2862 /* Currently, vtable-dispatch is only enabled for sparc platforms */ | |
| 1295 | 2863 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) { |
| 0 | 2864 ShouldNotReachHere(); |
| 2865 } | |
| 2866 | |
| 1295 | 2867 |
| 0 | 2868 void LIR_Assembler::emit_static_call_stub() { |
| 2869 address call_pc = __ pc(); | |
| 2870 address stub = __ start_a_stub(call_stub_size); | |
| 2871 if (stub == NULL) { | |
| 2872 bailout("static call stub overflow"); | |
| 2873 return; | |
| 2874 } | |
| 2875 | |
| 2876 int start = __ offset(); | |
| 2877 if (os::is_MP()) { | |
| 2878 // make sure that the displacement word of the call ends up word aligned | |
| 2879 int offset = __ offset() + NativeMovConstReg::instruction_size + NativeCall::displacement_offset; | |
| 2880 while (offset++ % BytesPerWord != 0) { | |
| 2881 __ nop(); | |
| 2882 } | |
| 2883 } | |
| 2884 __ relocate(static_stub_Relocation::spec(call_pc)); | |
| 2885 __ movoop(rbx, (jobject)NULL); | |
| 2886 // must be set to -1 at code generation time | |
| 2887 assert(!os::is_MP() || ((__ offset() + 1) % BytesPerWord) == 0, "must be aligned on MP"); | |
| 304 | 2888 // On 64bit this will die since it will take a movq & jmp, must be only a jmp |
| 2889 __ jump(RuntimeAddress(__ pc())); | |
| 0 | 2890 |
|
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2891 assert(__ offset() - start <= call_stub_size, "stub too big"); |
| 0 | 2892 __ end_a_stub(); |
| 2893 } | |
| 2894 | |
| 2895 | |
|
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2896 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) { |
| 0 | 2897 assert(exceptionOop->as_register() == rax, "must match"); |
|
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2898 assert(exceptionPC->as_register() == rdx, "must match"); |
| 0 | 2899 |
| 2900 // exception object is not added to oop map by LinearScan | |
| 2901 // (LinearScan assumes that no oops are in fixed registers) | |
| 2902 info->add_register_oop(exceptionOop); | |
| 2903 Runtime1::StubID unwind_id; | |
| 2904 | |
|
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2905 // get current pc information |
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2906 // pc is only needed if the method has an exception handler, the unwind code does not need it. |
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2907 int pc_for_athrow_offset = __ offset(); |
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2908 InternalAddress pc_for_athrow(__ pc()); |
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2909 __ lea(exceptionPC->as_register(), pc_for_athrow); |
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2910 add_call_info(pc_for_athrow_offset, info); // for exception handler |
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2911 |
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2912 __ verify_not_null_oop(rax); |
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2913 // search an exception handler (rax: exception oop, rdx: throwing pc) |
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2914 if (compilation()->has_fpu_code()) { |
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2915 unwind_id = Runtime1::handle_exception_id; |
| 0 | 2916 } else { |
|
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2917 unwind_id = Runtime1::handle_exception_nofpu_id; |
| 0 | 2918 } |
|
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2919 __ call(RuntimeAddress(Runtime1::entry_for(unwind_id))); |
| 0 | 2920 |
| 2921 // enough room for two byte trap | |
| 2922 __ nop(); | |
| 2923 } | |
| 2924 | |
| 2925 | |
|
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2926 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) { |
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2927 assert(exceptionOop->as_register() == rax, "must match"); |
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2928 |
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2929 __ jmp(_unwind_handler_entry); |
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2930 } |
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2931 |
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2932 |
| 0 | 2933 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) { |
| 2934 | |
| 2935 // optimized version for linear scan: | |
| 2936 // * count must be already in ECX (guaranteed by LinearScan) | |
| 2937 // * left and dest must be equal | |
| 2938 // * tmp must be unused | |
| 2939 assert(count->as_register() == SHIFT_count, "count must be in ECX"); | |
| 2940 assert(left == dest, "left and dest must be equal"); | |
| 2941 assert(tmp->is_illegal(), "wasting a register if tmp is allocated"); | |
| 2942 | |
| 2943 if (left->is_single_cpu()) { | |
| 2944 Register value = left->as_register(); | |
| 2945 assert(value != SHIFT_count, "left cannot be ECX"); | |
| 2946 | |
| 2947 switch (code) { | |
| 2948 case lir_shl: __ shll(value); break; | |
| 2949 case lir_shr: __ sarl(value); break; | |
| 2950 case lir_ushr: __ shrl(value); break; | |
| 2951 default: ShouldNotReachHere(); | |
| 2952 } | |
| 2953 } else if (left->is_double_cpu()) { | |
| 2954 Register lo = left->as_register_lo(); | |
| 2955 Register hi = left->as_register_hi(); | |
| 2956 assert(lo != SHIFT_count && hi != SHIFT_count, "left cannot be ECX"); | |
| 304 | 2957 #ifdef _LP64 |
| 2958 switch (code) { | |
| 2959 case lir_shl: __ shlptr(lo); break; | |
| 2960 case lir_shr: __ sarptr(lo); break; | |
| 2961 case lir_ushr: __ shrptr(lo); break; | |
| 2962 default: ShouldNotReachHere(); | |
| 2963 } | |
| 2964 #else | |
| 0 | 2965 |
| 2966 switch (code) { | |
| 2967 case lir_shl: __ lshl(hi, lo); break; | |
| 2968 case lir_shr: __ lshr(hi, lo, true); break; | |
| 2969 case lir_ushr: __ lshr(hi, lo, false); break; | |
| 2970 default: ShouldNotReachHere(); | |
| 2971 } | |
| 304 | 2972 #endif // LP64 |
| 0 | 2973 } else { |
| 2974 ShouldNotReachHere(); | |
| 2975 } | |
| 2976 } | |
| 2977 | |
| 2978 | |
| 2979 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) { | |
| 2980 if (dest->is_single_cpu()) { | |
| 2981 // first move left into dest so that left is not destroyed by the shift | |
| 2982 Register value = dest->as_register(); | |
| 2983 count = count & 0x1F; // Java spec | |
| 2984 | |
| 2985 move_regs(left->as_register(), value); | |
| 2986 switch (code) { | |
| 2987 case lir_shl: __ shll(value, count); break; | |
| 2988 case lir_shr: __ sarl(value, count); break; | |
| 2989 case lir_ushr: __ shrl(value, count); break; | |
| 2990 default: ShouldNotReachHere(); | |
| 2991 } | |
| 2992 } else if (dest->is_double_cpu()) { | |
| 304 | 2993 #ifndef _LP64 |
| 0 | 2994 Unimplemented(); |
| 304 | 2995 #else |
| 2996 // first move left into dest so that left is not destroyed by the shift | |
| 2997 Register value = dest->as_register_lo(); | |
| 2998 count = count & 0x1F; // Java spec | |
| 2999 | |
| 3000 move_regs(left->as_register_lo(), value); | |
| 3001 switch (code) { | |
| 3002 case lir_shl: __ shlptr(value, count); break; | |
| 3003 case lir_shr: __ sarptr(value, count); break; | |
| 3004 case lir_ushr: __ shrptr(value, count); break; | |
| 3005 default: ShouldNotReachHere(); | |
| 3006 } | |
| 3007 #endif // _LP64 | |
| 0 | 3008 } else { |
| 3009 ShouldNotReachHere(); | |
| 3010 } | |
| 3011 } | |
| 3012 | |
| 3013 | |
| 3014 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) { | |
| 3015 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); | |
| 3016 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; | |
| 3017 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); | |
| 304 | 3018 __ movptr (Address(rsp, offset_from_rsp_in_bytes), r); |
| 0 | 3019 } |
| 3020 | |
| 3021 | |
| 3022 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) { | |
| 3023 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); | |
| 3024 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; | |
| 3025 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); | |
| 304 | 3026 __ movptr (Address(rsp, offset_from_rsp_in_bytes), c); |
| 0 | 3027 } |
| 3028 | |
| 3029 | |
| 3030 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) { | |
| 3031 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); | |
| 3032 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; | |
| 3033 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); | |
| 3034 __ movoop (Address(rsp, offset_from_rsp_in_bytes), o); | |
| 3035 } | |
| 3036 | |
| 3037 | |
| 3038 // This code replaces a call to arraycopy; no exception may | |
| 3039 // be thrown in this code, they must be thrown in the System.arraycopy | |
| 3040 // activation frame; we could save some checks if this would not be the case | |
| 3041 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) { | |
| 3042 ciArrayKlass* default_type = op->expected_type(); | |
| 3043 Register src = op->src()->as_register(); | |
| 3044 Register dst = op->dst()->as_register(); | |
| 3045 Register src_pos = op->src_pos()->as_register(); | |
| 3046 Register dst_pos = op->dst_pos()->as_register(); | |
| 3047 Register length = op->length()->as_register(); | |
| 3048 Register tmp = op->tmp()->as_register(); | |
| 3049 | |
| 3050 CodeStub* stub = op->stub(); | |
| 3051 int flags = op->flags(); | |
| 3052 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL; | |
| 3053 if (basic_type == T_ARRAY) basic_type = T_OBJECT; | |
| 3054 | |
| 3055 // if we don't know anything or it's an object array, just go through the generic arraycopy | |
| 3056 if (default_type == NULL) { | |
| 3057 Label done; | |
| 3058 // save outgoing arguments on stack in case call to System.arraycopy is needed | |
| 3059 // HACK ALERT. This code used to push the parameters in a hardwired fashion | |
| 3060 // for interpreter calling conventions. Now we have to do it in new style conventions. | |
| 3061 // For the moment until C1 gets the new register allocator I just force all the | |
| 3062 // args to the right place (except the register args) and then on the back side | |
| 3063 // reload the register args properly if we go slow path. Yuck | |
| 3064 | |
| 3065 // These are proper for the calling convention | |
| 3066 | |
| 3067 store_parameter(length, 2); | |
| 3068 store_parameter(dst_pos, 1); | |
| 3069 store_parameter(dst, 0); | |
| 3070 | |
| 3071 // these are just temporary placements until we need to reload | |
| 3072 store_parameter(src_pos, 3); | |
| 3073 store_parameter(src, 4); | |
| 304 | 3074 NOT_LP64(assert(src == rcx && src_pos == rdx, "mismatch in calling convention");) |
| 3075 | |
| 3076 address entry = CAST_FROM_FN_PTR(address, Runtime1::arraycopy); | |
| 0 | 3077 |
| 3078 // pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint | |
| 304 | 3079 #ifdef _LP64 |
| 3080 // The arguments are in java calling convention so we can trivially shift them to C | |
| 3081 // convention | |
| 3082 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4); | |
| 3083 __ mov(c_rarg0, j_rarg0); | |
| 3084 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4); | |
| 3085 __ mov(c_rarg1, j_rarg1); | |
| 3086 assert_different_registers(c_rarg2, j_rarg3, j_rarg4); | |
| 3087 __ mov(c_rarg2, j_rarg2); | |
| 3088 assert_different_registers(c_rarg3, j_rarg4); | |
| 3089 __ mov(c_rarg3, j_rarg3); | |
| 3090 #ifdef _WIN64 | |
| 3091 // Allocate abi space for args but be sure to keep stack aligned | |
| 3092 __ subptr(rsp, 6*wordSize); | |
| 3093 store_parameter(j_rarg4, 4); | |
| 3094 __ call(RuntimeAddress(entry)); | |
| 3095 __ addptr(rsp, 6*wordSize); | |
| 3096 #else | |
| 3097 __ mov(c_rarg4, j_rarg4); | |
| 3098 __ call(RuntimeAddress(entry)); | |
| 3099 #endif // _WIN64 | |
| 3100 #else | |
| 3101 __ push(length); | |
| 3102 __ push(dst_pos); | |
| 3103 __ push(dst); | |
| 3104 __ push(src_pos); | |
| 3105 __ push(src); | |
| 0 | 3106 __ call_VM_leaf(entry, 5); // removes pushed parameter from the stack |
| 3107 | |
| 304 | 3108 #endif // _LP64 |
| 3109 | |
| 0 | 3110 __ cmpl(rax, 0); |
| 3111 __ jcc(Assembler::equal, *stub->continuation()); | |
| 3112 | |
| 3113 // Reload values from the stack so they are where the stub | |
| 3114 // expects them. | |
| 304 | 3115 __ movptr (dst, Address(rsp, 0*BytesPerWord)); |
| 3116 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord)); | |
| 3117 __ movptr (length, Address(rsp, 2*BytesPerWord)); | |
| 3118 __ movptr (src_pos, Address(rsp, 3*BytesPerWord)); | |
| 3119 __ movptr (src, Address(rsp, 4*BytesPerWord)); | |
| 0 | 3120 __ jmp(*stub->entry()); |
| 3121 | |
| 3122 __ bind(*stub->continuation()); | |
| 3123 return; | |
| 3124 } | |
| 3125 | |
| 3126 assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point"); | |
| 3127 | |
|
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3128 int elem_size = type2aelembytes(basic_type); |
| 0 | 3129 int shift_amount; |
| 3130 Address::ScaleFactor scale; | |
| 3131 | |
| 3132 switch (elem_size) { | |
| 3133 case 1 : | |
| 3134 shift_amount = 0; | |
| 3135 scale = Address::times_1; | |
| 3136 break; | |
| 3137 case 2 : | |
| 3138 shift_amount = 1; | |
| 3139 scale = Address::times_2; | |
| 3140 break; | |
| 3141 case 4 : | |
| 3142 shift_amount = 2; | |
| 3143 scale = Address::times_4; | |
| 3144 break; | |
| 3145 case 8 : | |
| 3146 shift_amount = 3; | |
| 3147 scale = Address::times_8; | |
| 3148 break; | |
| 3149 default: | |
| 3150 ShouldNotReachHere(); | |
| 3151 } | |
| 3152 | |
| 3153 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes()); | |
| 3154 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes()); | |
| 3155 Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes()); | |
| 3156 Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes()); | |
| 3157 | |
| 304 | 3158 // length and pos's are all sign extended at this point on 64bit |
| 3159 | |
| 0 | 3160 // test for NULL |
| 3161 if (flags & LIR_OpArrayCopy::src_null_check) { | |
| 304 | 3162 __ testptr(src, src); |
| 0 | 3163 __ jcc(Assembler::zero, *stub->entry()); |
| 3164 } | |
| 3165 if (flags & LIR_OpArrayCopy::dst_null_check) { | |
| 304 | 3166 __ testptr(dst, dst); |
| 0 | 3167 __ jcc(Assembler::zero, *stub->entry()); |
| 3168 } | |
| 3169 | |
| 3170 // check if negative | |
| 3171 if (flags & LIR_OpArrayCopy::src_pos_positive_check) { | |
| 3172 __ testl(src_pos, src_pos); | |
| 3173 __ jcc(Assembler::less, *stub->entry()); | |
| 3174 } | |
| 3175 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) { | |
| 3176 __ testl(dst_pos, dst_pos); | |
| 3177 __ jcc(Assembler::less, *stub->entry()); | |
| 3178 } | |
| 3179 if (flags & LIR_OpArrayCopy::length_positive_check) { | |
| 3180 __ testl(length, length); | |
| 3181 __ jcc(Assembler::less, *stub->entry()); | |
| 3182 } | |
| 3183 | |
| 3184 if (flags & LIR_OpArrayCopy::src_range_check) { | |
| 304 | 3185 __ lea(tmp, Address(src_pos, length, Address::times_1, 0)); |
| 0 | 3186 __ cmpl(tmp, src_length_addr); |
| 3187 __ jcc(Assembler::above, *stub->entry()); | |
| 3188 } | |
| 3189 if (flags & LIR_OpArrayCopy::dst_range_check) { | |
| 304 | 3190 __ lea(tmp, Address(dst_pos, length, Address::times_1, 0)); |
| 0 | 3191 __ cmpl(tmp, dst_length_addr); |
| 3192 __ jcc(Assembler::above, *stub->entry()); | |
| 3193 } | |
| 3194 | |
| 3195 if (flags & LIR_OpArrayCopy::type_check) { | |
| 304 | 3196 __ movptr(tmp, src_klass_addr); |
| 3197 __ cmpptr(tmp, dst_klass_addr); | |
| 0 | 3198 __ jcc(Assembler::notEqual, *stub->entry()); |
| 3199 } | |
| 3200 | |
| 3201 #ifdef ASSERT | |
| 3202 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) { | |
| 3203 // Sanity check the known type with the incoming class. For the | |
| 3204 // primitive case the types must match exactly with src.klass and | |
| 3205 // dst.klass each exactly matching the default type. For the | |
| 3206 // object array case, if no type check is needed then either the | |
| 3207 // dst type is exactly the expected type and the src type is a | |
| 3208 // subtype which we can't check or src is the same array as dst | |
| 3209 // but not necessarily exactly of type default_type. | |
| 3210 Label known_ok, halt; | |
|
989
148e5441d916
6863023: need non-perm oops in code cache for JSR 292
jrose
parents:
780
diff
changeset
|
3211 __ movoop(tmp, default_type->constant_encoding()); |
| 0 | 3212 if (basic_type != T_OBJECT) { |
| 304 | 3213 __ cmpptr(tmp, dst_klass_addr); |
| 0 | 3214 __ jcc(Assembler::notEqual, halt); |
| 304 | 3215 __ cmpptr(tmp, src_klass_addr); |
| 0 | 3216 __ jcc(Assembler::equal, known_ok); |
| 3217 } else { | |
| 304 | 3218 __ cmpptr(tmp, dst_klass_addr); |
| 0 | 3219 __ jcc(Assembler::equal, known_ok); |
| 304 | 3220 __ cmpptr(src, dst); |
| 0 | 3221 __ jcc(Assembler::equal, known_ok); |
| 3222 } | |
| 3223 __ bind(halt); | |
| 3224 __ stop("incorrect type information in arraycopy"); | |
| 3225 __ bind(known_ok); | |
| 3226 } | |
| 3227 #endif | |
| 3228 | |
| 304 | 3229 if (shift_amount > 0 && basic_type != T_OBJECT) { |
| 3230 __ shlptr(length, shift_amount); | |
| 3231 } | |
| 3232 | |
| 3233 #ifdef _LP64 | |
| 3234 assert_different_registers(c_rarg0, dst, dst_pos, length); | |
| 1060 | 3235 __ movl2ptr(src_pos, src_pos); //higher 32bits must be null |
| 304 | 3236 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); |
| 3237 assert_different_registers(c_rarg1, length); | |
| 1060 | 3238 __ movl2ptr(dst_pos, dst_pos); //higher 32bits must be null |
| 304 | 3239 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); |
| 3240 __ mov(c_rarg2, length); | |
| 3241 | |
| 3242 #else | |
| 3243 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); | |
| 0 | 3244 store_parameter(tmp, 0); |
| 304 | 3245 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); |
| 0 | 3246 store_parameter(tmp, 1); |
| 3247 store_parameter(length, 2); | |
| 304 | 3248 #endif // _LP64 |
| 0 | 3249 if (basic_type == T_OBJECT) { |
| 3250 __ call_VM_leaf(CAST_FROM_FN_PTR(address, Runtime1::oop_arraycopy), 0); | |
| 3251 } else { | |
| 3252 __ call_VM_leaf(CAST_FROM_FN_PTR(address, Runtime1::primitive_arraycopy), 0); | |
| 3253 } | |
| 3254 | |
| 3255 __ bind(*stub->continuation()); | |
| 3256 } | |
| 3257 | |
| 3258 | |
| 3259 void LIR_Assembler::emit_lock(LIR_OpLock* op) { | |
| 3260 Register obj = op->obj_opr()->as_register(); // may not be an oop | |
| 3261 Register hdr = op->hdr_opr()->as_register(); | |
| 3262 Register lock = op->lock_opr()->as_register(); | |
| 3263 if (!UseFastLocking) { | |
| 3264 __ jmp(*op->stub()->entry()); | |
| 3265 } else if (op->code() == lir_lock) { | |
| 3266 Register scratch = noreg; | |
| 3267 if (UseBiasedLocking) { | |
| 3268 scratch = op->scratch_opr()->as_register(); | |
| 3269 } | |
| 3270 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); | |
| 3271 // add debug info for NullPointerException only if one is possible | |
| 3272 int null_check_offset = __ lock_object(hdr, obj, lock, scratch, *op->stub()->entry()); | |
| 3273 if (op->info() != NULL) { | |
| 3274 add_debug_info_for_null_check(null_check_offset, op->info()); | |
| 3275 } | |
| 3276 // done | |
| 3277 } else if (op->code() == lir_unlock) { | |
| 3278 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); | |
| 3279 __ unlock_object(hdr, obj, lock, *op->stub()->entry()); | |
| 3280 } else { | |
| 3281 Unimplemented(); | |
| 3282 } | |
| 3283 __ bind(*op->stub()->continuation()); | |
| 3284 } | |
| 3285 | |
| 3286 | |
| 3287 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) { | |
| 3288 ciMethod* method = op->profiled_method(); | |
| 3289 int bci = op->profiled_bci(); | |
| 3290 | |
| 3291 // Update counter for all call types | |
| 3292 ciMethodData* md = method->method_data(); | |
| 3293 if (md == NULL) { | |
| 3294 bailout("out of memory building methodDataOop"); | |
| 3295 return; | |
| 3296 } | |
| 3297 ciProfileData* data = md->bci_to_data(bci); | |
| 3298 assert(data->is_CounterData(), "need CounterData for calls"); | |
| 3299 assert(op->mdo()->is_single_cpu(), "mdo must be allocated"); | |
| 3300 Register mdo = op->mdo()->as_register(); | |
|
989
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6863023: need non-perm oops in code cache for JSR 292
jrose
parents:
780
diff
changeset
|
3301 __ movoop(mdo, md->constant_encoding()); |
| 0 | 3302 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); |
| 3303 Bytecodes::Code bc = method->java_code_at_bci(bci); | |
| 3304 // Perform additional virtual call profiling for invokevirtual and | |
| 3305 // invokeinterface bytecodes | |
| 3306 if ((bc == Bytecodes::_invokevirtual || bc == Bytecodes::_invokeinterface) && | |
| 1783 | 3307 C1ProfileVirtualCalls) { |
| 0 | 3308 assert(op->recv()->is_single_cpu(), "recv must be allocated"); |
| 3309 Register recv = op->recv()->as_register(); | |
| 3310 assert_different_registers(mdo, recv); | |
| 3311 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls"); | |
| 3312 ciKlass* known_klass = op->known_holder(); | |
| 1783 | 3313 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) { |
| 0 | 3314 // We know the type that will be seen at this call site; we can |
| 3315 // statically update the methodDataOop rather than needing to do | |
| 3316 // dynamic tests on the receiver type | |
| 3317 | |
| 3318 // NOTE: we should probably put a lock around this search to | |
| 3319 // avoid collisions by concurrent compilations | |
| 3320 ciVirtualCallData* vc_data = (ciVirtualCallData*) data; | |
| 3321 uint i; | |
| 3322 for (i = 0; i < VirtualCallData::row_limit(); i++) { | |
| 3323 ciKlass* receiver = vc_data->receiver(i); | |
| 3324 if (known_klass->equals(receiver)) { | |
| 3325 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))); | |
| 1783 | 3326 __ addptr(data_addr, DataLayout::counter_increment); |
| 0 | 3327 return; |
| 3328 } | |
| 3329 } | |
| 3330 | |
| 3331 // Receiver type not found in profile data; select an empty slot | |
| 3332 | |
| 3333 // Note that this is less efficient than it should be because it | |
| 3334 // always does a write to the receiver part of the | |
| 3335 // VirtualCallData rather than just the first time | |
| 3336 for (i = 0; i < VirtualCallData::row_limit(); i++) { | |
| 3337 ciKlass* receiver = vc_data->receiver(i); | |
| 3338 if (receiver == NULL) { | |
| 3339 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i))); | |
|
989
148e5441d916
6863023: need non-perm oops in code cache for JSR 292
jrose
parents:
780
diff
changeset
|
3340 __ movoop(recv_addr, known_klass->constant_encoding()); |
| 0 | 3341 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))); |
| 1783 | 3342 __ addptr(data_addr, DataLayout::counter_increment); |
| 0 | 3343 return; |
| 3344 } | |
| 3345 } | |
| 3346 } else { | |
| 304 | 3347 __ movptr(recv, Address(recv, oopDesc::klass_offset_in_bytes())); |
| 0 | 3348 Label update_done; |
| 1783 | 3349 type_profile_helper(mdo, md, data, recv, &update_done); |
|
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diff
changeset
|
3350 // Receiver did not match any saved receiver and there is no empty row for it. |
|
1251
576e77447e3c
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diff
changeset
|
3351 // Increment total counter to indicate polymorphic case. |
| 1783 | 3352 __ addptr(counter_addr, DataLayout::counter_increment); |
| 0 | 3353 |
| 3354 __ bind(update_done); | |
| 3355 } | |
|
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diff
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|
3356 } else { |
|
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kvn
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diff
changeset
|
3357 // Static call |
| 1783 | 3358 __ addptr(counter_addr, DataLayout::counter_increment); |
| 0 | 3359 } |
| 3360 } | |
| 3361 | |
| 3362 void LIR_Assembler::emit_delay(LIR_OpDelay*) { | |
| 3363 Unimplemented(); | |
| 3364 } | |
| 3365 | |
| 3366 | |
| 3367 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) { | |
| 304 | 3368 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no)); |
| 0 | 3369 } |
| 3370 | |
| 3371 | |
| 3372 void LIR_Assembler::align_backward_branch_target() { | |
| 3373 __ align(BytesPerWord); | |
| 3374 } | |
| 3375 | |
| 3376 | |
| 3377 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) { | |
| 3378 if (left->is_single_cpu()) { | |
| 3379 __ negl(left->as_register()); | |
| 3380 move_regs(left->as_register(), dest->as_register()); | |
| 3381 | |
| 3382 } else if (left->is_double_cpu()) { | |
| 3383 Register lo = left->as_register_lo(); | |
| 304 | 3384 #ifdef _LP64 |
| 3385 Register dst = dest->as_register_lo(); | |
| 3386 __ movptr(dst, lo); | |
| 3387 __ negptr(dst); | |
| 3388 #else | |
| 0 | 3389 Register hi = left->as_register_hi(); |
| 3390 __ lneg(hi, lo); | |
| 3391 if (dest->as_register_lo() == hi) { | |
| 3392 assert(dest->as_register_hi() != lo, "destroying register"); | |
| 3393 move_regs(hi, dest->as_register_hi()); | |
| 3394 move_regs(lo, dest->as_register_lo()); | |
| 3395 } else { | |
| 3396 move_regs(lo, dest->as_register_lo()); | |
| 3397 move_regs(hi, dest->as_register_hi()); | |
| 3398 } | |
| 304 | 3399 #endif // _LP64 |
| 0 | 3400 |
| 3401 } else if (dest->is_single_xmm()) { | |
| 3402 if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) { | |
| 3403 __ movflt(dest->as_xmm_float_reg(), left->as_xmm_float_reg()); | |
| 3404 } | |
| 3405 __ xorps(dest->as_xmm_float_reg(), | |
| 3406 ExternalAddress((address)float_signflip_pool)); | |
| 3407 | |
| 3408 } else if (dest->is_double_xmm()) { | |
| 3409 if (left->as_xmm_double_reg() != dest->as_xmm_double_reg()) { | |
| 3410 __ movdbl(dest->as_xmm_double_reg(), left->as_xmm_double_reg()); | |
| 3411 } | |
| 3412 __ xorpd(dest->as_xmm_double_reg(), | |
| 3413 ExternalAddress((address)double_signflip_pool)); | |
| 3414 | |
| 3415 } else if (left->is_single_fpu() || left->is_double_fpu()) { | |
| 3416 assert(left->fpu() == 0, "arg must be on TOS"); | |
| 3417 assert(dest->fpu() == 0, "dest must be TOS"); | |
| 3418 __ fchs(); | |
| 3419 | |
| 3420 } else { | |
| 3421 ShouldNotReachHere(); | |
| 3422 } | |
| 3423 } | |
| 3424 | |
| 3425 | |
| 3426 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest) { | |
| 3427 assert(addr->is_address() && dest->is_register(), "check"); | |
| 304 | 3428 Register reg; |
| 3429 reg = dest->as_pointer_register(); | |
| 3430 __ lea(reg, as_Address(addr->as_address_ptr())); | |
| 0 | 3431 } |
| 3432 | |
| 3433 | |
| 3434 | |
| 3435 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) { | |
| 3436 assert(!tmp->is_valid(), "don't need temporary"); | |
| 3437 __ call(RuntimeAddress(dest)); | |
| 3438 if (info != NULL) { | |
| 3439 add_call_info_here(info); | |
| 3440 } | |
| 3441 } | |
| 3442 | |
| 3443 | |
| 3444 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) { | |
| 3445 assert(type == T_LONG, "only for volatile long fields"); | |
| 3446 | |
| 3447 if (info != NULL) { | |
| 3448 add_debug_info_for_null_check_here(info); | |
| 3449 } | |
| 3450 | |
| 3451 if (src->is_double_xmm()) { | |
| 3452 if (dest->is_double_cpu()) { | |
| 304 | 3453 #ifdef _LP64 |
| 3454 __ movdq(dest->as_register_lo(), src->as_xmm_double_reg()); | |
| 3455 #else | |
| 3456 __ movdl(dest->as_register_lo(), src->as_xmm_double_reg()); | |
| 0 | 3457 __ psrlq(src->as_xmm_double_reg(), 32); |
| 304 | 3458 __ movdl(dest->as_register_hi(), src->as_xmm_double_reg()); |
| 3459 #endif // _LP64 | |
| 0 | 3460 } else if (dest->is_double_stack()) { |
| 3461 __ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg()); | |
| 3462 } else if (dest->is_address()) { | |
| 3463 __ movdbl(as_Address(dest->as_address_ptr()), src->as_xmm_double_reg()); | |
| 3464 } else { | |
| 3465 ShouldNotReachHere(); | |
| 3466 } | |
| 3467 | |
| 3468 } else if (dest->is_double_xmm()) { | |
| 3469 if (src->is_double_stack()) { | |
| 3470 __ movdbl(dest->as_xmm_double_reg(), frame_map()->address_for_slot(src->double_stack_ix())); | |
| 3471 } else if (src->is_address()) { | |
| 3472 __ movdbl(dest->as_xmm_double_reg(), as_Address(src->as_address_ptr())); | |
| 3473 } else { | |
| 3474 ShouldNotReachHere(); | |
| 3475 } | |
| 3476 | |
| 3477 } else if (src->is_double_fpu()) { | |
| 3478 assert(src->fpu_regnrLo() == 0, "must be TOS"); | |
| 3479 if (dest->is_double_stack()) { | |
| 3480 __ fistp_d(frame_map()->address_for_slot(dest->double_stack_ix())); | |
| 3481 } else if (dest->is_address()) { | |
| 3482 __ fistp_d(as_Address(dest->as_address_ptr())); | |
| 3483 } else { | |
| 3484 ShouldNotReachHere(); | |
| 3485 } | |
| 3486 | |
| 3487 } else if (dest->is_double_fpu()) { | |
| 3488 assert(dest->fpu_regnrLo() == 0, "must be TOS"); | |
| 3489 if (src->is_double_stack()) { | |
| 3490 __ fild_d(frame_map()->address_for_slot(src->double_stack_ix())); | |
| 3491 } else if (src->is_address()) { | |
| 3492 __ fild_d(as_Address(src->as_address_ptr())); | |
| 3493 } else { | |
| 3494 ShouldNotReachHere(); | |
| 3495 } | |
| 3496 } else { | |
| 3497 ShouldNotReachHere(); | |
| 3498 } | |
| 3499 } | |
| 3500 | |
| 3501 | |
| 3502 void LIR_Assembler::membar() { | |
| 304 | 3503 // QQQ sparc TSO uses this, |
| 3504 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad)); | |
| 0 | 3505 } |
| 3506 | |
| 3507 void LIR_Assembler::membar_acquire() { | |
| 3508 // No x86 machines currently require load fences | |
| 3509 // __ load_fence(); | |
| 3510 } | |
| 3511 | |
| 3512 void LIR_Assembler::membar_release() { | |
| 3513 // No x86 machines currently require store fences | |
| 3514 // __ store_fence(); | |
| 3515 } | |
| 3516 | |
| 3517 void LIR_Assembler::get_thread(LIR_Opr result_reg) { | |
| 3518 assert(result_reg->is_register(), "check"); | |
| 304 | 3519 #ifdef _LP64 |
| 3520 // __ get_thread(result_reg->as_register_lo()); | |
| 3521 __ mov(result_reg->as_register(), r15_thread); | |
| 3522 #else | |
| 0 | 3523 __ get_thread(result_reg->as_register()); |
| 304 | 3524 #endif // _LP64 |
| 0 | 3525 } |
| 3526 | |
| 3527 | |
| 3528 void LIR_Assembler::peephole(LIR_List*) { | |
| 3529 // do nothing for now | |
| 3530 } | |
| 3531 | |
| 3532 | |
| 3533 #undef __ |