Mercurial > hg > truffle
annotate src/os_cpu/solaris_x86/vm/solaris_x86_32.ad @ 795:215f81b4d9b3
6841831: G1: assert(contains_reference(from),"We just added it!") fires
Summary: During parallel rset updating we have to make sure that the worker ids of the refinement threads do not intersect with the worker ids that can be claimed by the mutator threads.
Reviewed-by: tonyp
| author | iveresov |
|---|---|
| date | Mon, 18 May 2009 11:52:46 -0700 |
| parents | a1980da045cc |
| children | c18cbe5936b8 |
| rev | line source |
|---|---|
| 0 | 1 // |
| 337 | 2 // Copyright 1999-2008 Sun Microsystems, Inc. All Rights Reserved. |
| 0 | 3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 4 // | |
| 5 // This code is free software; you can redistribute it and/or modify it | |
| 6 // under the terms of the GNU General Public License version 2 only, as | |
| 7 // published by the Free Software Foundation. | |
| 8 // | |
| 9 // This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 // version 2 for more details (a copy is included in the LICENSE file that | |
| 13 // accompanied this code). | |
| 14 // | |
| 15 // You should have received a copy of the GNU General Public License version | |
| 16 // 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 // | |
| 19 // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
| 20 // CA 95054 USA or visit www.sun.com if you need additional information or | |
| 21 // have any questions. | |
| 22 // | |
| 23 // | |
| 24 | |
| 25 // X86 Solaris Architecture Description File | |
| 26 | |
| 27 //----------OS-DEPENDENT ENCODING BLOCK----------------------------------------------------- | |
| 28 // This block specifies the encoding classes used by the compiler to output | |
| 29 // byte streams. Encoding classes generate functions which are called by | |
| 30 // Machine Instruction Nodes in order to generate the bit encoding of the | |
| 31 // instruction. Operands specify their base encoding interface with the | |
| 32 // interface keyword. There are currently supported four interfaces, | |
| 33 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an | |
| 34 // operand to generate a function which returns its register number when | |
| 35 // queried. CONST_INTER causes an operand to generate a function which | |
| 36 // returns the value of the constant when queried. MEMORY_INTER causes an | |
| 37 // operand to generate four functions which return the Base Register, the | |
| 38 // Index Register, the Scale Value, and the Offset Value of the operand when | |
| 39 // queried. COND_INTER causes an operand to generate six functions which | |
| 40 // return the encoding code (ie - encoding bits for the instruction) | |
| 41 // associated with each basic boolean condition for a conditional instruction. | |
| 42 // Instructions specify two basic values for encoding. They use the | |
| 43 // ins_encode keyword to specify their encoding class (which must be one of | |
| 44 // the class names specified in the encoding block), and they use the | |
| 45 // opcode keyword to specify, in order, their primary, secondary, and | |
| 46 // tertiary opcode. Only the opcode sections which a particular instruction | |
| 47 // needs for encoding need to be specified. | |
| 48 encode %{ | |
| 49 // Build emit functions for each basic byte or larger field in the intel | |
| 50 // encoding scheme (opcode, rm, sib, immediate), and call them from C++ | |
| 51 // code in the enc_class source block. Emit functions will live in the | |
| 52 // main source block for now. In future, we can generalize this by | |
| 53 // adding a syntax that specifies the sizes of fields in an order, | |
| 54 // so that the adlc can build the emit functions automagically | |
| 55 | |
| 56 enc_class solaris_tlsencode (eRegP dst) %{ | |
| 57 Register dstReg = as_Register($dst$$reg); | |
| 58 MacroAssembler* masm = new MacroAssembler(&cbuf); | |
| 59 masm->get_thread(dstReg); | |
| 60 %} | |
| 61 | |
| 62 enc_class solaris_breakpoint %{ | |
| 63 MacroAssembler* masm = new MacroAssembler(&cbuf); | |
| 64 // Really need to fix this | |
| 304 | 65 masm->push(rax); |
| 66 masm->push(rcx); | |
| 67 masm->push(rdx); | |
| 0 | 68 masm->call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint))); |
| 304 | 69 masm->pop(rdx); |
| 70 masm->pop(rcx); | |
| 71 masm->pop(rax); | |
| 0 | 72 %} |
| 73 | |
| 74 enc_class call_epilog %{ | |
| 75 if( VerifyStackAtCalls ) { | |
| 76 // Check that stack depth is unchanged: find majik cookie on stack | |
| 77 int framesize = ra_->reg2offset_unchecked(OptoReg::add(ra_->_matcher._old_SP,-3*VMRegImpl::slots_per_word)); | |
| 78 if(framesize >= 128) { | |
| 79 emit_opcode(cbuf, 0x81); // cmp [esp+0],0xbadb1ood | |
| 80 emit_d8(cbuf,0xBC); | |
| 81 emit_d8(cbuf,0x24); | |
| 82 emit_d32(cbuf,framesize); // Find majik cookie from ESP | |
| 83 emit_d32(cbuf, 0xbadb100d); | |
| 84 } | |
| 85 else { | |
| 86 emit_opcode(cbuf, 0x81); // cmp [esp+0],0xbadb1ood | |
| 87 emit_d8(cbuf,0x7C); | |
| 88 emit_d8(cbuf,0x24); | |
| 89 emit_d8(cbuf,framesize); // Find majik cookie from ESP | |
| 90 emit_d32(cbuf, 0xbadb100d); | |
| 91 } | |
| 92 // jmp EQ around INT3 | |
| 93 // QQQ TODO | |
| 94 const int jump_around = 11; // size of call to breakpoint (and register preserve), 1 for CC | |
| 95 emit_opcode(cbuf,0x74); | |
| 96 emit_d8(cbuf, jump_around); | |
| 97 // QQQ temporary | |
| 98 emit_break(cbuf); | |
| 99 // Die if stack mismatch | |
| 100 // emit_opcode(cbuf,0xCC); | |
| 101 } | |
| 102 %} | |
| 103 | |
| 104 %} | |
| 105 | |
| 106 // INSTRUCTIONS -- Platform dependent | |
| 107 | |
| 108 //----------OS and Locking Instructions---------------------------------------- | |
| 109 | |
| 110 // This name is KNOWN by the ADLC and cannot be changed. | |
| 111 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type | |
| 112 // for this guy. | |
|
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a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
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changeset
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113 instruct tlsLoadP(eRegP dst, eFlagsReg cr) %{ |
| 0 | 114 match(Set dst (ThreadLocal)); |
| 115 effect(DEF dst, KILL cr); | |
| 116 | |
|
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6462850: generate biased locking code in C2 ideal graph
kvn
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changeset
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117 format %{ "MOV $dst, Thread::current()" %} |
| 0 | 118 ins_encode( solaris_tlsencode(dst) ); |
| 119 ins_pipe( ialu_reg_fat ); | |
| 120 %} | |
| 121 | |
|
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a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
337
diff
changeset
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122 instruct TLS(eRegP dst) %{ |
| 0 | 123 match(Set dst (ThreadLocal)); |
| 124 | |
| 125 expand %{ | |
| 126 tlsLoadP(dst); | |
| 127 %} | |
| 128 %} | |
| 129 | |
| 130 // Die now | |
| 131 instruct ShouldNotReachHere( ) | |
| 132 %{ | |
| 133 match(Halt); | |
| 134 | |
| 135 // Use the following format syntax | |
| 136 format %{ "INT3 ; ShouldNotReachHere" %} | |
| 137 // QQQ TODO for now call breakpoint | |
| 138 // opcode(0xCC); | |
| 139 // ins_encode(Opc); | |
| 140 ins_encode(solaris_breakpoint); | |
| 141 ins_pipe( pipe_slow ); | |
| 142 %} | |
| 143 | |
| 144 | |
| 145 | |
| 146 // Platform dependent source | |
| 147 | |
| 148 source %{ | |
| 149 | |
| 150 // emit an interrupt that is caught by the debugger | |
| 151 void emit_break(CodeBuffer &cbuf) { | |
| 152 | |
| 153 // Debugger doesn't really catch this but best we can do so far QQQ | |
| 154 MacroAssembler* masm = new MacroAssembler(&cbuf); | |
| 155 masm->call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint))); | |
| 156 } | |
| 157 | |
| 158 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 159 emit_break(cbuf); | |
| 160 } | |
| 161 | |
| 162 | |
| 163 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const { | |
| 164 return 5; | |
| 165 } | |
| 166 | |
| 167 %} |