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7199
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1 /*
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2 * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved.
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3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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4 *
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5 * This code is free software; you can redistribute it and/or modify it
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6 * under the terms of the GNU General Public License version 2 only, as
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7 * published by the Free Software Foundation.
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8 *
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9 * This code is distributed in the hope that it will be useful, but WITHOUT
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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12 * version 2 for more details (a copy is included in the LICENSE file that
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13 * accompanied this code).
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14 *
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15 * You should have received a copy of the GNU General Public License version
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16 * 2 along with this work; if not, write to the Free Software Foundation,
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17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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18 *
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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20 * or visit www.oracle.com if you need additional information or have any
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21 * questions.
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22 *
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23 */
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24
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25 #ifndef CPU_X86_VM_MACROASSEMBLER_X86_HPP
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26 #define CPU_X86_VM_MACROASSEMBLER_X86_HPP
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27
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28 #include "asm/assembler.hpp"
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29
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30
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31 // MacroAssembler extends Assembler by frequently used macros.
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32 //
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33 // Instructions for which a 'better' code sequence exists depending
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34 // on arguments should also go in here.
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35
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36 class MacroAssembler: public Assembler {
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37 friend class LIR_Assembler;
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38 friend class Runtime1; // as_Address()
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39
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40 protected:
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41
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42 Address as_Address(AddressLiteral adr);
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43 Address as_Address(ArrayAddress adr);
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44
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45 // Support for VM calls
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46 //
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47 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
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48 // may customize this version by overriding it for its purposes (e.g., to save/restore
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49 // additional registers when doing a VM call).
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50 #ifdef CC_INTERP
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51 // c++ interpreter never wants to use interp_masm version of call_VM
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52 #define VIRTUAL
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53 #else
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54 #define VIRTUAL virtual
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55 #endif
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56
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57 VIRTUAL void call_VM_leaf_base(
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58 address entry_point, // the entry point
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59 int number_of_arguments // the number of arguments to pop after the call
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60 );
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61
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62 // This is the base routine called by the different versions of call_VM. The interpreter
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63 // may customize this version by overriding it for its purposes (e.g., to save/restore
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64 // additional registers when doing a VM call).
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65 //
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66 // If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base
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67 // returns the register which contains the thread upon return. If a thread register has been
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68 // specified, the return value will correspond to that register. If no last_java_sp is specified
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69 // (noreg) than rsp will be used instead.
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70 VIRTUAL void call_VM_base( // returns the register containing the thread upon return
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71 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
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72 Register java_thread, // the thread if computed before ; use noreg otherwise
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73 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
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74 address entry_point, // the entry point
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75 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
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76 bool check_exceptions // whether to check for pending exceptions after return
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77 );
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78
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79 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
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80 // The implementation is only non-empty for the InterpreterMacroAssembler,
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81 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
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82 virtual void check_and_handle_popframe(Register java_thread);
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83 virtual void check_and_handle_earlyret(Register java_thread);
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84
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85 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
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86
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87 // helpers for FPU flag access
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88 // tmp is a temporary register, if none is available use noreg
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89 void save_rax (Register tmp);
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90 void restore_rax(Register tmp);
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91
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92 public:
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93 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
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94
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95 // Support for NULL-checks
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96 //
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97 // Generates code that causes a NULL OS exception if the content of reg is NULL.
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98 // If the accessed location is M[reg + offset] and the offset is known, provide the
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99 // offset. No explicit code generation is needed if the offset is within a certain
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100 // range (0 <= offset <= page_size).
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101
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102 void null_check(Register reg, int offset = -1);
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103 static bool needs_explicit_null_check(intptr_t offset);
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104
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105 // Required platform-specific helpers for Label::patch_instructions.
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106 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
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107 void pd_patch_instruction(address branch, address target) {
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108 unsigned char op = branch[0];
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109 assert(op == 0xE8 /* call */ ||
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110 op == 0xE9 /* jmp */ ||
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111 op == 0xEB /* short jmp */ ||
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112 (op & 0xF0) == 0x70 /* short jcc */ ||
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113 op == 0x0F && (branch[1] & 0xF0) == 0x80 /* jcc */,
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114 "Invalid opcode at patch point");
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115
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116 if (op == 0xEB || (op & 0xF0) == 0x70) {
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117 // short offset operators (jmp and jcc)
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118 char* disp = (char*) &branch[1];
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119 int imm8 = target - (address) &disp[1];
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120 guarantee(this->is8bit(imm8), "Short forward jump exceeds 8-bit offset");
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121 *disp = imm8;
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122 } else {
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123 int* disp = (int*) &branch[(op == 0x0F)? 2: 1];
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124 int imm32 = target - (address) &disp[1];
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125 *disp = imm32;
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126 }
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127 }
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128
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129 #ifndef PRODUCT
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130 static void pd_print_patched_instruction(address branch) {
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131 const char* s;
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132 unsigned char op = branch[0];
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133 if (op == 0xE8) {
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134 s = "call";
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135 } else if (op == 0xE9 || op == 0xEB) {
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136 s = "jmp";
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137 } else if ((op & 0xF0) == 0x70) {
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138 s = "jcc";
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139 } else if (op == 0x0F) {
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140 s = "jcc";
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141 } else {
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142 s = "????";
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143 }
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144 tty->print("%s (unresolved)", s);
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145 }
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146 #endif
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147
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148 // The following 4 methods return the offset of the appropriate move instruction
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149
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150 // Support for fast byte/short loading with zero extension (depending on particular CPU)
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151 int load_unsigned_byte(Register dst, Address src);
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152 int load_unsigned_short(Register dst, Address src);
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153
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154 // Support for fast byte/short loading with sign extension (depending on particular CPU)
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155 int load_signed_byte(Register dst, Address src);
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156 int load_signed_short(Register dst, Address src);
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157
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158 // Support for sign-extension (hi:lo = extend_sign(lo))
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159 void extend_sign(Register hi, Register lo);
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160
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161 // Load and store values by size and signed-ness
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162 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
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163 void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
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164
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165 // Support for inc/dec with optimal instruction selection depending on value
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166
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167 void increment(Register reg, int value = 1) { LP64_ONLY(incrementq(reg, value)) NOT_LP64(incrementl(reg, value)) ; }
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168 void decrement(Register reg, int value = 1) { LP64_ONLY(decrementq(reg, value)) NOT_LP64(decrementl(reg, value)) ; }
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169
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170 void decrementl(Address dst, int value = 1);
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171 void decrementl(Register reg, int value = 1);
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172
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173 void decrementq(Register reg, int value = 1);
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174 void decrementq(Address dst, int value = 1);
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175
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176 void incrementl(Address dst, int value = 1);
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177 void incrementl(Register reg, int value = 1);
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178
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179 void incrementq(Register reg, int value = 1);
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180 void incrementq(Address dst, int value = 1);
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181
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182
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183 // Support optimal SSE move instructions.
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184 void movflt(XMMRegister dst, XMMRegister src) {
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185 if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; }
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186 else { movss (dst, src); return; }
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187 }
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188 void movflt(XMMRegister dst, Address src) { movss(dst, src); }
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189 void movflt(XMMRegister dst, AddressLiteral src);
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190 void movflt(Address dst, XMMRegister src) { movss(dst, src); }
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191
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192 void movdbl(XMMRegister dst, XMMRegister src) {
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193 if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; }
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194 else { movsd (dst, src); return; }
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195 }
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196
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197 void movdbl(XMMRegister dst, AddressLiteral src);
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198
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199 void movdbl(XMMRegister dst, Address src) {
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200 if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; }
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201 else { movlpd(dst, src); return; }
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202 }
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203 void movdbl(Address dst, XMMRegister src) { movsd(dst, src); }
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204
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205 void incrementl(AddressLiteral dst);
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206 void incrementl(ArrayAddress dst);
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207
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208 // Alignment
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209 void align(int modulus);
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210
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211 // A 5 byte nop that is safe for patching (see patch_verified_entry)
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212 void fat_nop();
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213
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214 // Stack frame creation/removal
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215 void enter();
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216 void leave();
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217
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218 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
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219 // The pointer will be loaded into the thread register.
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220 void get_thread(Register thread);
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221
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222
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223 // Support for VM calls
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224 //
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225 // It is imperative that all calls into the VM are handled via the call_VM macros.
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226 // They make sure that the stack linkage is setup correctly. call_VM's correspond
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227 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
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228
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229
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230 void call_VM(Register oop_result,
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231 address entry_point,
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232 bool check_exceptions = true);
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233 void call_VM(Register oop_result,
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234 address entry_point,
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235 Register arg_1,
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236 bool check_exceptions = true);
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237 void call_VM(Register oop_result,
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238 address entry_point,
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239 Register arg_1, Register arg_2,
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240 bool check_exceptions = true);
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241 void call_VM(Register oop_result,
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242 address entry_point,
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243 Register arg_1, Register arg_2, Register arg_3,
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244 bool check_exceptions = true);
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245
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246 // Overloadings with last_Java_sp
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247 void call_VM(Register oop_result,
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248 Register last_java_sp,
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249 address entry_point,
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250 int number_of_arguments = 0,
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251 bool check_exceptions = true);
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252 void call_VM(Register oop_result,
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253 Register last_java_sp,
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254 address entry_point,
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255 Register arg_1, bool
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256 check_exceptions = true);
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257 void call_VM(Register oop_result,
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258 Register last_java_sp,
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259 address entry_point,
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260 Register arg_1, Register arg_2,
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261 bool check_exceptions = true);
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262 void call_VM(Register oop_result,
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263 Register last_java_sp,
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264 address entry_point,
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265 Register arg_1, Register arg_2, Register arg_3,
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266 bool check_exceptions = true);
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267
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268 void get_vm_result (Register oop_result, Register thread);
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269 void get_vm_result_2(Register metadata_result, Register thread);
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270
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271 // These always tightly bind to MacroAssembler::call_VM_base
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272 // bypassing the virtual implementation
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273 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
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274 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
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275 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
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276 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
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277 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
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278
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279 void call_VM_leaf(address entry_point,
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280 int number_of_arguments = 0);
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281 void call_VM_leaf(address entry_point,
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282 Register arg_1);
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283 void call_VM_leaf(address entry_point,
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284 Register arg_1, Register arg_2);
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285 void call_VM_leaf(address entry_point,
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286 Register arg_1, Register arg_2, Register arg_3);
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287
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288 // These always tightly bind to MacroAssembler::call_VM_leaf_base
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289 // bypassing the virtual implementation
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290 void super_call_VM_leaf(address entry_point);
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291 void super_call_VM_leaf(address entry_point, Register arg_1);
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292 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
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293 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
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294 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
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295
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296 // last Java Frame (fills frame anchor)
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297 void set_last_Java_frame(Register thread,
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298 Register last_java_sp,
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299 Register last_java_fp,
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300 address last_java_pc);
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301
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302 // thread in the default location (r15_thread on 64bit)
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303 void set_last_Java_frame(Register last_java_sp,
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304 Register last_java_fp,
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305 address last_java_pc);
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306
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307 void reset_last_Java_frame(Register thread, bool clear_fp, bool clear_pc);
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308
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309 // thread in the default location (r15_thread on 64bit)
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310 void reset_last_Java_frame(bool clear_fp, bool clear_pc);
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311
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312 // Stores
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313 void store_check(Register obj); // store check for obj - register is destroyed afterwards
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314 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed)
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315
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316 #ifndef SERIALGC
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317
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318 void g1_write_barrier_pre(Register obj,
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319 Register pre_val,
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320 Register thread,
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321 Register tmp,
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322 bool tosca_live,
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323 bool expand_call);
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324
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325 void g1_write_barrier_post(Register store_addr,
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326 Register new_val,
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327 Register thread,
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328 Register tmp,
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329 Register tmp2);
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330
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331 #endif // SERIALGC
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332
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333 // split store_check(Register obj) to enhance instruction interleaving
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334 void store_check_part_1(Register obj);
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335 void store_check_part_2(Register obj);
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336
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337 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
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338 void c2bool(Register x);
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339
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340 // C++ bool manipulation
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341
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342 void movbool(Register dst, Address src);
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343 void movbool(Address dst, bool boolconst);
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344 void movbool(Address dst, Register src);
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345 void testbool(Register dst);
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346
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347 // oop manipulations
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348 void load_klass(Register dst, Register src);
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349 void store_klass(Register dst, Register src);
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350
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351 void load_heap_oop(Register dst, Address src);
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352 void load_heap_oop_not_null(Register dst, Address src);
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353 void store_heap_oop(Address dst, Register src);
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354 void cmp_heap_oop(Register src1, Address src2, Register tmp = noreg);
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355
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356 // Used for storing NULL. All other oop constants should be
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357 // stored using routines that take a jobject.
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358 void store_heap_oop_null(Address dst);
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359
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360 void load_prototype_header(Register dst, Register src);
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361
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362 #ifdef _LP64
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363 void store_klass_gap(Register dst, Register src);
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364
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365 // This dummy is to prevent a call to store_heap_oop from
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366 // converting a zero (like NULL) into a Register by giving
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367 // the compiler two choices it can't resolve
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368
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369 void store_heap_oop(Address dst, void* dummy);
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370
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371 void encode_heap_oop(Register r);
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372 void decode_heap_oop(Register r);
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373 void encode_heap_oop_not_null(Register r);
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374 void decode_heap_oop_not_null(Register r);
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375 void encode_heap_oop_not_null(Register dst, Register src);
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376 void decode_heap_oop_not_null(Register dst, Register src);
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377
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378 void set_narrow_oop(Register dst, jobject obj);
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379 void set_narrow_oop(Address dst, jobject obj);
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380 void cmp_narrow_oop(Register dst, jobject obj);
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381 void cmp_narrow_oop(Address dst, jobject obj);
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382
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383 void encode_klass_not_null(Register r);
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384 void decode_klass_not_null(Register r);
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385 void encode_klass_not_null(Register dst, Register src);
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386 void decode_klass_not_null(Register dst, Register src);
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387 void set_narrow_klass(Register dst, Klass* k);
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388 void set_narrow_klass(Address dst, Klass* k);
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389 void cmp_narrow_klass(Register dst, Klass* k);
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390 void cmp_narrow_klass(Address dst, Klass* k);
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391
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392 // if heap base register is used - reinit it with the correct value
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393 void reinit_heapbase();
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394
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395 DEBUG_ONLY(void verify_heapbase(const char* msg);)
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396
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397 #endif // _LP64
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398
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399 // Int division/remainder for Java
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400 // (as idivl, but checks for special case as described in JVM spec.)
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401 // returns idivl instruction offset for implicit exception handling
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402 int corrected_idivl(Register reg);
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403
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404 // Long division/remainder for Java
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405 // (as idivq, but checks for special case as described in JVM spec.)
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406 // returns idivq instruction offset for implicit exception handling
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407 int corrected_idivq(Register reg);
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408
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409 void int3();
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410
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411 // Long operation macros for a 32bit cpu
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412 // Long negation for Java
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413 void lneg(Register hi, Register lo);
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414
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415 // Long multiplication for Java
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416 // (destroys contents of eax, ebx, ecx and edx)
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417 void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y
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418
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419 // Long shifts for Java
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420 // (semantics as described in JVM spec.)
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421 void lshl(Register hi, Register lo); // hi:lo << (rcx & 0x3f)
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422 void lshr(Register hi, Register lo, bool sign_extension = false); // hi:lo >> (rcx & 0x3f)
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423
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424 // Long compare for Java
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425 // (semantics as described in JVM spec.)
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426 void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y)
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427
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428
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429 // misc
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430
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431 // Sign extension
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432 void sign_extend_short(Register reg);
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433 void sign_extend_byte(Register reg);
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434
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|
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435 // Division by power of 2, rounding towards 0
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436 void division_with_shift(Register reg, int shift_value);
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437
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438 // Compares the top-most stack entries on the FPU stack and sets the eflags as follows:
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439 //
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440 // CF (corresponds to C0) if x < y
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441 // PF (corresponds to C2) if unordered
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442 // ZF (corresponds to C3) if x = y
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443 //
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444 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
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445 // tmp is a temporary register, if none is available use noreg (only matters for non-P6 code)
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446 void fcmp(Register tmp);
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|
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447 // Variant of the above which allows y to be further down the stack
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|
448 // and which only pops x and y if specified. If pop_right is
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|
449 // specified then pop_left must also be specified.
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|
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450 void fcmp(Register tmp, int index, bool pop_left, bool pop_right);
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451
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|
|
452 // Floating-point comparison for Java
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|
|
453 // Compares the top-most stack entries on the FPU stack and stores the result in dst.
|
|
|
454 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
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|
|
455 // (semantics as described in JVM spec.)
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|
|
456 void fcmp2int(Register dst, bool unordered_is_less);
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|
|
457 // Variant of the above which allows y to be further down the stack
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|
|
458 // and which only pops x and y if specified. If pop_right is
|
|
|
459 // specified then pop_left must also be specified.
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|
|
460 void fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right);
|
|
|
461
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|
|
462 // Floating-point remainder for Java (ST0 = ST0 fremr ST1, ST1 is empty afterwards)
|
|
|
463 // tmp is a temporary register, if none is available use noreg
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|
|
464 void fremr(Register tmp);
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|
|
465
|
|
|
466
|
|
|
467 // same as fcmp2int, but using SSE2
|
|
|
468 void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
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|
|
469 void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
|
|
|
470
|
|
|
471 // Inlined sin/cos generator for Java; must not use CPU instruction
|
|
|
472 // directly on Intel as it does not have high enough precision
|
|
|
473 // outside of the range [-pi/4, pi/4]. Extra argument indicate the
|
|
|
474 // number of FPU stack slots in use; all but the topmost will
|
|
|
475 // require saving if a slow case is necessary. Assumes argument is
|
|
|
476 // on FP TOS; result is on FP TOS. No cpu registers are changed by
|
|
|
477 // this code.
|
|
|
478 void trigfunc(char trig, int num_fpu_regs_in_use = 1);
|
|
|
479
|
|
|
480 // branch to L if FPU flag C2 is set/not set
|
|
|
481 // tmp is a temporary register, if none is available use noreg
|
|
|
482 void jC2 (Register tmp, Label& L);
|
|
|
483 void jnC2(Register tmp, Label& L);
|
|
|
484
|
|
|
485 // Pop ST (ffree & fincstp combined)
|
|
|
486 void fpop();
|
|
|
487
|
|
|
488 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack
|
|
|
489 void push_fTOS();
|
|
|
490
|
|
|
491 // pops double TOS element from CPU stack and pushes on FPU stack
|
|
|
492 void pop_fTOS();
|
|
|
493
|
|
|
494 void empty_FPU_stack();
|
|
|
495
|
|
|
496 void push_IU_state();
|
|
|
497 void pop_IU_state();
|
|
|
498
|
|
|
499 void push_FPU_state();
|
|
|
500 void pop_FPU_state();
|
|
|
501
|
|
|
502 void push_CPU_state();
|
|
|
503 void pop_CPU_state();
|
|
|
504
|
|
|
505 // Round up to a power of two
|
|
|
506 void round_to(Register reg, int modulus);
|
|
|
507
|
|
|
508 // Callee saved registers handling
|
|
|
509 void push_callee_saved_registers();
|
|
|
510 void pop_callee_saved_registers();
|
|
|
511
|
|
|
512 // allocation
|
|
|
513 void eden_allocate(
|
|
|
514 Register obj, // result: pointer to object after successful allocation
|
|
|
515 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
|
|
|
516 int con_size_in_bytes, // object size in bytes if known at compile time
|
|
|
517 Register t1, // temp register
|
|
|
518 Label& slow_case // continuation point if fast allocation fails
|
|
|
519 );
|
|
|
520 void tlab_allocate(
|
|
|
521 Register obj, // result: pointer to object after successful allocation
|
|
|
522 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
|
|
|
523 int con_size_in_bytes, // object size in bytes if known at compile time
|
|
|
524 Register t1, // temp register
|
|
|
525 Register t2, // temp register
|
|
|
526 Label& slow_case // continuation point if fast allocation fails
|
|
|
527 );
|
|
|
528 Register tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case); // returns TLS address
|
|
|
529 void incr_allocated_bytes(Register thread,
|
|
|
530 Register var_size_in_bytes, int con_size_in_bytes,
|
|
|
531 Register t1 = noreg);
|
|
|
532
|
|
|
533 // interface method calling
|
|
|
534 void lookup_interface_method(Register recv_klass,
|
|
|
535 Register intf_klass,
|
|
|
536 RegisterOrConstant itable_index,
|
|
|
537 Register method_result,
|
|
|
538 Register scan_temp,
|
|
|
539 Label& no_such_interface);
|
|
|
540
|
|
|
541 // virtual method calling
|
|
|
542 void lookup_virtual_method(Register recv_klass,
|
|
|
543 RegisterOrConstant vtable_index,
|
|
|
544 Register method_result);
|
|
|
545
|
|
|
546 // Test sub_klass against super_klass, with fast and slow paths.
|
|
|
547
|
|
|
548 // The fast path produces a tri-state answer: yes / no / maybe-slow.
|
|
|
549 // One of the three labels can be NULL, meaning take the fall-through.
|
|
|
550 // If super_check_offset is -1, the value is loaded up from super_klass.
|
|
|
551 // No registers are killed, except temp_reg.
|
|
|
552 void check_klass_subtype_fast_path(Register sub_klass,
|
|
|
553 Register super_klass,
|
|
|
554 Register temp_reg,
|
|
|
555 Label* L_success,
|
|
|
556 Label* L_failure,
|
|
|
557 Label* L_slow_path,
|
|
|
558 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
|
|
|
559
|
|
|
560 // The rest of the type check; must be wired to a corresponding fast path.
|
|
|
561 // It does not repeat the fast path logic, so don't use it standalone.
|
|
|
562 // The temp_reg and temp2_reg can be noreg, if no temps are available.
|
|
|
563 // Updates the sub's secondary super cache as necessary.
|
|
|
564 // If set_cond_codes, condition codes will be Z on success, NZ on failure.
|
|
|
565 void check_klass_subtype_slow_path(Register sub_klass,
|
|
|
566 Register super_klass,
|
|
|
567 Register temp_reg,
|
|
|
568 Register temp2_reg,
|
|
|
569 Label* L_success,
|
|
|
570 Label* L_failure,
|
|
|
571 bool set_cond_codes = false);
|
|
|
572
|
|
|
573 // Simplified, combined version, good for typical uses.
|
|
|
574 // Falls through on failure.
|
|
|
575 void check_klass_subtype(Register sub_klass,
|
|
|
576 Register super_klass,
|
|
|
577 Register temp_reg,
|
|
|
578 Label& L_success);
|
|
|
579
|
|
|
580 // method handles (JSR 292)
|
|
|
581 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
|
|
|
582
|
|
|
583 //----
|
|
|
584 void set_word_if_not_zero(Register reg); // sets reg to 1 if not zero, otherwise 0
|
|
|
585
|
|
|
586 // Debugging
|
|
|
587
|
|
|
588 // only if +VerifyOops
|
|
|
589 // TODO: Make these macros with file and line like sparc version!
|
|
|
590 void verify_oop(Register reg, const char* s = "broken oop");
|
|
|
591 void verify_oop_addr(Address addr, const char * s = "broken oop addr");
|
|
|
592
|
|
|
593 // TODO: verify method and klass metadata (compare against vptr?)
|
|
|
594 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
|
|
|
595 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
|
|
|
596
|
|
|
597 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
|
|
|
598 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
|
|
|
599
|
|
|
600 // only if +VerifyFPU
|
|
|
601 void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
|
|
|
602
|
|
|
603 // prints msg, dumps registers and stops execution
|
|
|
604 void stop(const char* msg);
|
|
|
605
|
|
|
606 // prints msg and continues
|
|
|
607 void warn(const char* msg);
|
|
|
608
|
|
|
609 // dumps registers and other state
|
|
|
610 void print_state();
|
|
|
611
|
|
|
612 static void debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg);
|
|
|
613 static void debug64(char* msg, int64_t pc, int64_t regs[]);
|
|
|
614 static void print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip);
|
|
|
615 static void print_state64(int64_t pc, int64_t regs[]);
|
|
|
616
|
|
|
617 void os_breakpoint();
|
|
|
618
|
|
|
619 void untested() { stop("untested"); }
|
|
|
620
|
|
|
621 void unimplemented(const char* what = "") { char* b = new char[1024]; jio_snprintf(b, 1024, "unimplemented: %s", what); stop(b); }
|
|
|
622
|
|
|
623 void should_not_reach_here() { stop("should not reach here"); }
|
|
|
624
|
|
|
625 void print_CPU_state();
|
|
|
626
|
|
|
627 // Stack overflow checking
|
|
|
628 void bang_stack_with_offset(int offset) {
|
|
|
629 // stack grows down, caller passes positive offset
|
|
|
630 assert(offset > 0, "must bang with negative offset");
|
|
|
631 movl(Address(rsp, (-offset)), rax);
|
|
|
632 }
|
|
|
633
|
|
|
634 // Writes to stack successive pages until offset reached to check for
|
|
|
635 // stack overflow + shadow pages. Also, clobbers tmp
|
|
|
636 void bang_stack_size(Register size, Register tmp);
|
|
|
637
|
|
|
638 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
|
|
|
639 Register tmp,
|
|
|
640 int offset);
|
|
|
641
|
|
|
642 // Support for serializing memory accesses between threads
|
|
|
643 void serialize_memory(Register thread, Register tmp);
|
|
|
644
|
|
|
645 void verify_tlab();
|
|
|
646
|
|
|
647 // Biased locking support
|
|
|
648 // lock_reg and obj_reg must be loaded up with the appropriate values.
|
|
|
649 // swap_reg must be rax, and is killed.
|
|
|
650 // tmp_reg is optional. If it is supplied (i.e., != noreg) it will
|
|
|
651 // be killed; if not supplied, push/pop will be used internally to
|
|
|
652 // allocate a temporary (inefficient, avoid if possible).
|
|
|
653 // Optional slow case is for implementations (interpreter and C1) which branch to
|
|
|
654 // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
|
|
|
655 // Returns offset of first potentially-faulting instruction for null
|
|
|
656 // check info (currently consumed only by C1). If
|
|
|
657 // swap_reg_contains_mark is true then returns -1 as it is assumed
|
|
|
658 // the calling code has already passed any potential faults.
|
|
|
659 int biased_locking_enter(Register lock_reg, Register obj_reg,
|
|
|
660 Register swap_reg, Register tmp_reg,
|
|
|
661 bool swap_reg_contains_mark,
|
|
|
662 Label& done, Label* slow_case = NULL,
|
|
|
663 BiasedLockingCounters* counters = NULL);
|
|
|
664 void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
|
|
|
665
|
|
|
666
|
|
|
667 Condition negate_condition(Condition cond);
|
|
|
668
|
|
|
669 // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit
|
|
|
670 // operands. In general the names are modified to avoid hiding the instruction in Assembler
|
|
|
671 // so that we don't need to implement all the varieties in the Assembler with trivial wrappers
|
|
|
672 // here in MacroAssembler. The major exception to this rule is call
|
|
|
673
|
|
|
674 // Arithmetics
|
|
|
675
|
|
|
676
|
|
|
677 void addptr(Address dst, int32_t src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)) ; }
|
|
|
678 void addptr(Address dst, Register src);
|
|
|
679
|
|
|
680 void addptr(Register dst, Address src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); }
|
|
|
681 void addptr(Register dst, int32_t src);
|
|
|
682 void addptr(Register dst, Register src);
|
|
|
683 void addptr(Register dst, RegisterOrConstant src) {
|
|
|
684 if (src.is_constant()) addptr(dst, (int) src.as_constant());
|
|
|
685 else addptr(dst, src.as_register());
|
|
|
686 }
|
|
|
687
|
|
|
688 void andptr(Register dst, int32_t src);
|
|
|
689 void andptr(Register src1, Register src2) { LP64_ONLY(andq(src1, src2)) NOT_LP64(andl(src1, src2)) ; }
|
|
|
690
|
|
|
691 void cmp8(AddressLiteral src1, int imm);
|
|
|
692
|
|
|
693 // renamed to drag out the casting of address to int32_t/intptr_t
|
|
|
694 void cmp32(Register src1, int32_t imm);
|
|
|
695
|
|
|
696 void cmp32(AddressLiteral src1, int32_t imm);
|
|
|
697 // compare reg - mem, or reg - &mem
|
|
|
698 void cmp32(Register src1, AddressLiteral src2);
|
|
|
699
|
|
|
700 void cmp32(Register src1, Address src2);
|
|
|
701
|
|
|
702 #ifndef _LP64
|
|
|
703 void cmpklass(Address dst, Metadata* obj);
|
|
|
704 void cmpklass(Register dst, Metadata* obj);
|
|
|
705 void cmpoop(Address dst, jobject obj);
|
|
|
706 void cmpoop(Register dst, jobject obj);
|
|
|
707 #endif // _LP64
|
|
|
708
|
|
|
709 // NOTE src2 must be the lval. This is NOT an mem-mem compare
|
|
|
710 void cmpptr(Address src1, AddressLiteral src2);
|
|
|
711
|
|
|
712 void cmpptr(Register src1, AddressLiteral src2);
|
|
|
713
|
|
|
714 void cmpptr(Register src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
|
|
|
715 void cmpptr(Register src1, Address src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
|
|
|
716 // void cmpptr(Address src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
|
|
|
717
|
|
|
718 void cmpptr(Register src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
|
|
|
719 void cmpptr(Address src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
|
|
|
720
|
|
|
721 // cmp64 to avoild hiding cmpq
|
|
|
722 void cmp64(Register src1, AddressLiteral src);
|
|
|
723
|
|
|
724 void cmpxchgptr(Register reg, Address adr);
|
|
|
725
|
|
|
726 void locked_cmpxchgptr(Register reg, AddressLiteral adr);
|
|
|
727
|
|
|
728
|
|
|
729 void imulptr(Register dst, Register src) { LP64_ONLY(imulq(dst, src)) NOT_LP64(imull(dst, src)); }
|
|
|
730
|
|
|
731
|
|
|
732 void negptr(Register dst) { LP64_ONLY(negq(dst)) NOT_LP64(negl(dst)); }
|
|
|
733
|
|
|
734 void notptr(Register dst) { LP64_ONLY(notq(dst)) NOT_LP64(notl(dst)); }
|
|
|
735
|
|
|
736 void shlptr(Register dst, int32_t shift);
|
|
|
737 void shlptr(Register dst) { LP64_ONLY(shlq(dst)) NOT_LP64(shll(dst)); }
|
|
|
738
|
|
|
739 void shrptr(Register dst, int32_t shift);
|
|
|
740 void shrptr(Register dst) { LP64_ONLY(shrq(dst)) NOT_LP64(shrl(dst)); }
|
|
|
741
|
|
|
742 void sarptr(Register dst) { LP64_ONLY(sarq(dst)) NOT_LP64(sarl(dst)); }
|
|
|
743 void sarptr(Register dst, int32_t src) { LP64_ONLY(sarq(dst, src)) NOT_LP64(sarl(dst, src)); }
|
|
|
744
|
|
|
745 void subptr(Address dst, int32_t src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
|
|
|
746
|
|
|
747 void subptr(Register dst, Address src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
|
|
|
748 void subptr(Register dst, int32_t src);
|
|
|
749 // Force generation of a 4 byte immediate value even if it fits into 8bit
|
|
|
750 void subptr_imm32(Register dst, int32_t src);
|
|
|
751 void subptr(Register dst, Register src);
|
|
|
752 void subptr(Register dst, RegisterOrConstant src) {
|
|
|
753 if (src.is_constant()) subptr(dst, (int) src.as_constant());
|
|
|
754 else subptr(dst, src.as_register());
|
|
|
755 }
|
|
|
756
|
|
|
757 void sbbptr(Address dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
|
|
|
758 void sbbptr(Register dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
|
|
|
759
|
|
|
760 void xchgptr(Register src1, Register src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
|
|
|
761 void xchgptr(Register src1, Address src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
|
|
|
762
|
|
|
763 void xaddptr(Address src1, Register src2) { LP64_ONLY(xaddq(src1, src2)) NOT_LP64(xaddl(src1, src2)) ; }
|
|
|
764
|
|
|
765
|
|
|
766
|
|
|
767 // Helper functions for statistics gathering.
|
|
|
768 // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes.
|
|
|
769 void cond_inc32(Condition cond, AddressLiteral counter_addr);
|
|
|
770 // Unconditional atomic increment.
|
|
|
771 void atomic_incl(AddressLiteral counter_addr);
|
|
|
772
|
|
|
773 void lea(Register dst, AddressLiteral adr);
|
|
|
774 void lea(Address dst, AddressLiteral adr);
|
|
|
775 void lea(Register dst, Address adr) { Assembler::lea(dst, adr); }
|
|
|
776
|
|
|
777 void leal32(Register dst, Address src) { leal(dst, src); }
|
|
|
778
|
|
|
779 // Import other testl() methods from the parent class or else
|
|
|
780 // they will be hidden by the following overriding declaration.
|
|
|
781 using Assembler::testl;
|
|
|
782 void testl(Register dst, AddressLiteral src);
|
|
|
783
|
|
|
784 void orptr(Register dst, Address src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
|
|
|
785 void orptr(Register dst, Register src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
|
|
|
786 void orptr(Register dst, int32_t src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
|
|
|
787
|
|
|
788 void testptr(Register src, int32_t imm32) { LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); }
|
|
|
789 void testptr(Register src1, Register src2);
|
|
|
790
|
|
|
791 void xorptr(Register dst, Register src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
|
|
|
792 void xorptr(Register dst, Address src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
|
|
|
793
|
|
|
794 // Calls
|
|
|
795
|
|
|
796 void call(Label& L, relocInfo::relocType rtype);
|
|
|
797 void call(Register entry);
|
|
|
798
|
|
|
799 // NOTE: this call tranfers to the effective address of entry NOT
|
|
|
800 // the address contained by entry. This is because this is more natural
|
|
|
801 // for jumps/calls.
|
|
|
802 void call(AddressLiteral entry);
|
|
|
803
|
|
|
804 // Emit the CompiledIC call idiom
|
|
|
805 void ic_call(address entry);
|
|
|
806
|
|
|
807 // Jumps
|
|
|
808
|
|
|
809 // NOTE: these jumps tranfer to the effective address of dst NOT
|
|
|
810 // the address contained by dst. This is because this is more natural
|
|
|
811 // for jumps/calls.
|
|
|
812 void jump(AddressLiteral dst);
|
|
|
813 void jump_cc(Condition cc, AddressLiteral dst);
|
|
|
814
|
|
|
815 // 32bit can do a case table jump in one instruction but we no longer allow the base
|
|
|
816 // to be installed in the Address class. This jump will tranfers to the address
|
|
|
817 // contained in the location described by entry (not the address of entry)
|
|
|
818 void jump(ArrayAddress entry);
|
|
|
819
|
|
|
820 // Floating
|
|
|
821
|
|
|
822 void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); }
|
|
|
823 void andpd(XMMRegister dst, AddressLiteral src);
|
|
|
824
|
|
|
825 void andps(XMMRegister dst, XMMRegister src) { Assembler::andps(dst, src); }
|
|
|
826 void andps(XMMRegister dst, Address src) { Assembler::andps(dst, src); }
|
|
|
827 void andps(XMMRegister dst, AddressLiteral src);
|
|
|
828
|
|
|
829 void comiss(XMMRegister dst, XMMRegister src) { Assembler::comiss(dst, src); }
|
|
|
830 void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); }
|
|
|
831 void comiss(XMMRegister dst, AddressLiteral src);
|
|
|
832
|
|
|
833 void comisd(XMMRegister dst, XMMRegister src) { Assembler::comisd(dst, src); }
|
|
|
834 void comisd(XMMRegister dst, Address src) { Assembler::comisd(dst, src); }
|
|
|
835 void comisd(XMMRegister dst, AddressLiteral src);
|
|
|
836
|
|
|
837 void fadd_s(Address src) { Assembler::fadd_s(src); }
|
|
|
838 void fadd_s(AddressLiteral src) { Assembler::fadd_s(as_Address(src)); }
|
|
|
839
|
|
|
840 void fldcw(Address src) { Assembler::fldcw(src); }
|
|
|
841 void fldcw(AddressLiteral src);
|
|
|
842
|
|
|
843 void fld_s(int index) { Assembler::fld_s(index); }
|
|
|
844 void fld_s(Address src) { Assembler::fld_s(src); }
|
|
|
845 void fld_s(AddressLiteral src);
|
|
|
846
|
|
|
847 void fld_d(Address src) { Assembler::fld_d(src); }
|
|
|
848 void fld_d(AddressLiteral src);
|
|
|
849
|
|
|
850 void fld_x(Address src) { Assembler::fld_x(src); }
|
|
|
851 void fld_x(AddressLiteral src);
|
|
|
852
|
|
|
853 void fmul_s(Address src) { Assembler::fmul_s(src); }
|
|
|
854 void fmul_s(AddressLiteral src) { Assembler::fmul_s(as_Address(src)); }
|
|
|
855
|
|
|
856 void ldmxcsr(Address src) { Assembler::ldmxcsr(src); }
|
|
|
857 void ldmxcsr(AddressLiteral src);
|
|
|
858
|
|
|
859 // compute pow(x,y) and exp(x) with x86 instructions. Don't cover
|
|
|
860 // all corner cases and may result in NaN and require fallback to a
|
|
|
861 // runtime call.
|
|
|
862 void fast_pow();
|
|
|
863 void fast_exp();
|
|
|
864 void increase_precision();
|
|
|
865 void restore_precision();
|
|
|
866
|
|
|
867 // computes exp(x). Fallback to runtime call included.
|
|
|
868 void exp_with_fallback(int num_fpu_regs_in_use) { pow_or_exp(true, num_fpu_regs_in_use); }
|
|
|
869 // computes pow(x,y). Fallback to runtime call included.
|
|
|
870 void pow_with_fallback(int num_fpu_regs_in_use) { pow_or_exp(false, num_fpu_regs_in_use); }
|
|
|
871
|
|
|
872 private:
|
|
|
873
|
|
|
874 // call runtime as a fallback for trig functions and pow/exp.
|
|
|
875 void fp_runtime_fallback(address runtime_entry, int nb_args, int num_fpu_regs_in_use);
|
|
|
876
|
|
|
877 // computes 2^(Ylog2X); Ylog2X in ST(0)
|
|
|
878 void pow_exp_core_encoding();
|
|
|
879
|
|
|
880 // computes pow(x,y) or exp(x). Fallback to runtime call included.
|
|
|
881 void pow_or_exp(bool is_exp, int num_fpu_regs_in_use);
|
|
|
882
|
|
|
883 // these are private because users should be doing movflt/movdbl
|
|
|
884
|
|
|
885 void movss(Address dst, XMMRegister src) { Assembler::movss(dst, src); }
|
|
|
886 void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); }
|
|
|
887 void movss(XMMRegister dst, Address src) { Assembler::movss(dst, src); }
|
|
|
888 void movss(XMMRegister dst, AddressLiteral src);
|
|
|
889
|
|
|
890 void movlpd(XMMRegister dst, Address src) {Assembler::movlpd(dst, src); }
|
|
|
891 void movlpd(XMMRegister dst, AddressLiteral src);
|
|
|
892
|
|
|
893 public:
|
|
|
894
|
|
|
895 void addsd(XMMRegister dst, XMMRegister src) { Assembler::addsd(dst, src); }
|
|
|
896 void addsd(XMMRegister dst, Address src) { Assembler::addsd(dst, src); }
|
|
|
897 void addsd(XMMRegister dst, AddressLiteral src);
|
|
|
898
|
|
|
899 void addss(XMMRegister dst, XMMRegister src) { Assembler::addss(dst, src); }
|
|
|
900 void addss(XMMRegister dst, Address src) { Assembler::addss(dst, src); }
|
|
|
901 void addss(XMMRegister dst, AddressLiteral src);
|
|
|
902
|
|
|
903 void divsd(XMMRegister dst, XMMRegister src) { Assembler::divsd(dst, src); }
|
|
|
904 void divsd(XMMRegister dst, Address src) { Assembler::divsd(dst, src); }
|
|
|
905 void divsd(XMMRegister dst, AddressLiteral src);
|
|
|
906
|
|
|
907 void divss(XMMRegister dst, XMMRegister src) { Assembler::divss(dst, src); }
|
|
|
908 void divss(XMMRegister dst, Address src) { Assembler::divss(dst, src); }
|
|
|
909 void divss(XMMRegister dst, AddressLiteral src);
|
|
|
910
|
|
|
911 // Move Unaligned Double Quadword
|
|
|
912 void movdqu(Address dst, XMMRegister src) { Assembler::movdqu(dst, src); }
|
|
|
913 void movdqu(XMMRegister dst, Address src) { Assembler::movdqu(dst, src); }
|
|
|
914 void movdqu(XMMRegister dst, XMMRegister src) { Assembler::movdqu(dst, src); }
|
|
|
915 void movdqu(XMMRegister dst, AddressLiteral src);
|
|
|
916
|
|
|
917 void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); }
|
|
|
918 void movsd(Address dst, XMMRegister src) { Assembler::movsd(dst, src); }
|
|
|
919 void movsd(XMMRegister dst, Address src) { Assembler::movsd(dst, src); }
|
|
|
920 void movsd(XMMRegister dst, AddressLiteral src);
|
|
|
921
|
|
|
922 void mulsd(XMMRegister dst, XMMRegister src) { Assembler::mulsd(dst, src); }
|
|
|
923 void mulsd(XMMRegister dst, Address src) { Assembler::mulsd(dst, src); }
|
|
|
924 void mulsd(XMMRegister dst, AddressLiteral src);
|
|
|
925
|
|
|
926 void mulss(XMMRegister dst, XMMRegister src) { Assembler::mulss(dst, src); }
|
|
|
927 void mulss(XMMRegister dst, Address src) { Assembler::mulss(dst, src); }
|
|
|
928 void mulss(XMMRegister dst, AddressLiteral src);
|
|
|
929
|
|
|
930 void sqrtsd(XMMRegister dst, XMMRegister src) { Assembler::sqrtsd(dst, src); }
|
|
|
931 void sqrtsd(XMMRegister dst, Address src) { Assembler::sqrtsd(dst, src); }
|
|
|
932 void sqrtsd(XMMRegister dst, AddressLiteral src);
|
|
|
933
|
|
|
934 void sqrtss(XMMRegister dst, XMMRegister src) { Assembler::sqrtss(dst, src); }
|
|
|
935 void sqrtss(XMMRegister dst, Address src) { Assembler::sqrtss(dst, src); }
|
|
|
936 void sqrtss(XMMRegister dst, AddressLiteral src);
|
|
|
937
|
|
|
938 void subsd(XMMRegister dst, XMMRegister src) { Assembler::subsd(dst, src); }
|
|
|
939 void subsd(XMMRegister dst, Address src) { Assembler::subsd(dst, src); }
|
|
|
940 void subsd(XMMRegister dst, AddressLiteral src);
|
|
|
941
|
|
|
942 void subss(XMMRegister dst, XMMRegister src) { Assembler::subss(dst, src); }
|
|
|
943 void subss(XMMRegister dst, Address src) { Assembler::subss(dst, src); }
|
|
|
944 void subss(XMMRegister dst, AddressLiteral src);
|
|
|
945
|
|
|
946 void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); }
|
|
|
947 void ucomiss(XMMRegister dst, Address src) { Assembler::ucomiss(dst, src); }
|
|
|
948 void ucomiss(XMMRegister dst, AddressLiteral src);
|
|
|
949
|
|
|
950 void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); }
|
|
|
951 void ucomisd(XMMRegister dst, Address src) { Assembler::ucomisd(dst, src); }
|
|
|
952 void ucomisd(XMMRegister dst, AddressLiteral src);
|
|
|
953
|
|
|
954 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
|
|
|
955 void xorpd(XMMRegister dst, XMMRegister src) { Assembler::xorpd(dst, src); }
|
|
|
956 void xorpd(XMMRegister dst, Address src) { Assembler::xorpd(dst, src); }
|
|
|
957 void xorpd(XMMRegister dst, AddressLiteral src);
|
|
|
958
|
|
|
959 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
|
|
|
960 void xorps(XMMRegister dst, XMMRegister src) { Assembler::xorps(dst, src); }
|
|
|
961 void xorps(XMMRegister dst, Address src) { Assembler::xorps(dst, src); }
|
|
|
962 void xorps(XMMRegister dst, AddressLiteral src);
|
|
|
963
|
|
|
964 // Shuffle Bytes
|
|
|
965 void pshufb(XMMRegister dst, XMMRegister src) { Assembler::pshufb(dst, src); }
|
|
|
966 void pshufb(XMMRegister dst, Address src) { Assembler::pshufb(dst, src); }
|
|
|
967 void pshufb(XMMRegister dst, AddressLiteral src);
|
|
|
968 // AVX 3-operands instructions
|
|
|
969
|
|
|
970 void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddsd(dst, nds, src); }
|
|
|
971 void vaddsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddsd(dst, nds, src); }
|
|
|
972 void vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
|
|
|
973
|
|
|
974 void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddss(dst, nds, src); }
|
|
|
975 void vaddss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddss(dst, nds, src); }
|
|
|
976 void vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
|
|
|
977
|
|
|
978 void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { Assembler::vandpd(dst, nds, src, vector256); }
|
|
|
979 void vandpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { Assembler::vandpd(dst, nds, src, vector256); }
|
|
|
980 void vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256);
|
|
|
981
|
|
|
982 void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { Assembler::vandps(dst, nds, src, vector256); }
|
|
|
983 void vandps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { Assembler::vandps(dst, nds, src, vector256); }
|
|
|
984 void vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256);
|
|
|
985
|
|
|
986 void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivsd(dst, nds, src); }
|
|
|
987 void vdivsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivsd(dst, nds, src); }
|
|
|
988 void vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
|
|
|
989
|
|
|
990 void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivss(dst, nds, src); }
|
|
|
991 void vdivss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivss(dst, nds, src); }
|
|
|
992 void vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
|
|
|
993
|
|
|
994 void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulsd(dst, nds, src); }
|
|
|
995 void vmulsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulsd(dst, nds, src); }
|
|
|
996 void vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
|
|
|
997
|
|
|
998 void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulss(dst, nds, src); }
|
|
|
999 void vmulss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulss(dst, nds, src); }
|
|
|
1000 void vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
|
|
|
1001
|
|
|
1002 void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubsd(dst, nds, src); }
|
|
|
1003 void vsubsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubsd(dst, nds, src); }
|
|
|
1004 void vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
|
|
|
1005
|
|
|
1006 void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubss(dst, nds, src); }
|
|
|
1007 void vsubss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubss(dst, nds, src); }
|
|
|
1008 void vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
|
|
|
1009
|
|
|
1010 // AVX Vector instructions
|
|
|
1011
|
|
|
1012 void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { Assembler::vxorpd(dst, nds, src, vector256); }
|
|
|
1013 void vxorpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { Assembler::vxorpd(dst, nds, src, vector256); }
|
|
|
1014 void vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256);
|
|
|
1015
|
|
|
1016 void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { Assembler::vxorps(dst, nds, src, vector256); }
|
|
|
1017 void vxorps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { Assembler::vxorps(dst, nds, src, vector256); }
|
|
|
1018 void vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256);
|
|
|
1019
|
|
|
1020 void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
|
|
|
1021 if (UseAVX > 1 || !vector256) // vpxor 256 bit is available only in AVX2
|
|
|
1022 Assembler::vpxor(dst, nds, src, vector256);
|
|
|
1023 else
|
|
|
1024 Assembler::vxorpd(dst, nds, src, vector256);
|
|
|
1025 }
|
|
|
1026 void vpxor(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
|
|
|
1027 if (UseAVX > 1 || !vector256) // vpxor 256 bit is available only in AVX2
|
|
|
1028 Assembler::vpxor(dst, nds, src, vector256);
|
|
|
1029 else
|
|
|
1030 Assembler::vxorpd(dst, nds, src, vector256);
|
|
|
1031 }
|
|
|
1032
|
|
|
1033 // Move packed integer values from low 128 bit to hign 128 bit in 256 bit vector.
|
|
|
1034 void vinserti128h(XMMRegister dst, XMMRegister nds, XMMRegister src) {
|
|
|
1035 if (UseAVX > 1) // vinserti128h is available only in AVX2
|
|
|
1036 Assembler::vinserti128h(dst, nds, src);
|
|
|
1037 else
|
|
|
1038 Assembler::vinsertf128h(dst, nds, src);
|
|
|
1039 }
|
|
|
1040
|
|
|
1041 // Data
|
|
|
1042
|
|
|
1043 void cmov32( Condition cc, Register dst, Address src);
|
|
|
1044 void cmov32( Condition cc, Register dst, Register src);
|
|
|
1045
|
|
|
1046 void cmov( Condition cc, Register dst, Register src) { cmovptr(cc, dst, src); }
|
|
|
1047
|
|
|
1048 void cmovptr(Condition cc, Register dst, Address src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
|
|
|
1049 void cmovptr(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
|
|
|
1050
|
|
|
1051 void movoop(Register dst, jobject obj);
|
|
|
1052 void movoop(Address dst, jobject obj);
|
|
|
1053
|
|
|
1054 void mov_metadata(Register dst, Metadata* obj);
|
|
|
1055 void mov_metadata(Address dst, Metadata* obj);
|
|
|
1056
|
|
|
1057 void movptr(ArrayAddress dst, Register src);
|
|
|
1058 // can this do an lea?
|
|
|
1059 void movptr(Register dst, ArrayAddress src);
|
|
|
1060
|
|
|
1061 void movptr(Register dst, Address src);
|
|
|
1062
|
|
|
1063 void movptr(Register dst, AddressLiteral src);
|
|
|
1064
|
|
|
1065 void movptr(Register dst, intptr_t src);
|
|
|
1066 void movptr(Register dst, Register src);
|
|
|
1067 void movptr(Address dst, intptr_t src);
|
|
|
1068
|
|
|
1069 void movptr(Address dst, Register src);
|
|
|
1070
|
|
|
1071 void movptr(Register dst, RegisterOrConstant src) {
|
|
|
1072 if (src.is_constant()) movptr(dst, src.as_constant());
|
|
|
1073 else movptr(dst, src.as_register());
|
|
|
1074 }
|
|
|
1075
|
|
|
1076 #ifdef _LP64
|
|
|
1077 // Generally the next two are only used for moving NULL
|
|
|
1078 // Although there are situations in initializing the mark word where
|
|
|
1079 // they could be used. They are dangerous.
|
|
|
1080
|
|
|
1081 // They only exist on LP64 so that int32_t and intptr_t are not the same
|
|
|
1082 // and we have ambiguous declarations.
|
|
|
1083
|
|
|
1084 void movptr(Address dst, int32_t imm32);
|
|
|
1085 void movptr(Register dst, int32_t imm32);
|
|
|
1086 #endif // _LP64
|
|
|
1087
|
|
|
1088 // to avoid hiding movl
|
|
|
1089 void mov32(AddressLiteral dst, Register src);
|
|
|
1090 void mov32(Register dst, AddressLiteral src);
|
|
|
1091
|
|
|
1092 // to avoid hiding movb
|
|
|
1093 void movbyte(ArrayAddress dst, int src);
|
|
|
1094
|
|
|
1095 // Import other mov() methods from the parent class or else
|
|
|
1096 // they will be hidden by the following overriding declaration.
|
|
|
1097 using Assembler::movdl;
|
|
|
1098 using Assembler::movq;
|
|
|
1099 void movdl(XMMRegister dst, AddressLiteral src);
|
|
|
1100 void movq(XMMRegister dst, AddressLiteral src);
|
|
|
1101
|
|
|
1102 // Can push value or effective address
|
|
|
1103 void pushptr(AddressLiteral src);
|
|
|
1104
|
|
|
1105 void pushptr(Address src) { LP64_ONLY(pushq(src)) NOT_LP64(pushl(src)); }
|
|
|
1106 void popptr(Address src) { LP64_ONLY(popq(src)) NOT_LP64(popl(src)); }
|
|
|
1107
|
|
|
1108 void pushoop(jobject obj);
|
|
|
1109 void pushklass(Metadata* obj);
|
|
|
1110
|
|
|
1111 // sign extend as need a l to ptr sized element
|
|
|
1112 void movl2ptr(Register dst, Address src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src)); }
|
|
|
1113 void movl2ptr(Register dst, Register src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(if (dst != src) movl(dst, src)); }
|
|
|
1114
|
|
|
1115 // C2 compiled method's prolog code.
|
|
|
1116 void verified_entry(int framesize, bool stack_bang, bool fp_mode_24b);
|
|
|
1117
|
|
|
1118 // IndexOf strings.
|
|
|
1119 // Small strings are loaded through stack if they cross page boundary.
|
|
|
1120 void string_indexof(Register str1, Register str2,
|
|
|
1121 Register cnt1, Register cnt2,
|
|
|
1122 int int_cnt2, Register result,
|
|
|
1123 XMMRegister vec, Register tmp);
|
|
|
1124
|
|
|
1125 // IndexOf for constant substrings with size >= 8 elements
|
|
|
1126 // which don't need to be loaded through stack.
|
|
|
1127 void string_indexofC8(Register str1, Register str2,
|
|
|
1128 Register cnt1, Register cnt2,
|
|
|
1129 int int_cnt2, Register result,
|
|
|
1130 XMMRegister vec, Register tmp);
|
|
|
1131
|
|
|
1132 // Smallest code: we don't need to load through stack,
|
|
|
1133 // check string tail.
|
|
|
1134
|
|
|
1135 // Compare strings.
|
|
|
1136 void string_compare(Register str1, Register str2,
|
|
|
1137 Register cnt1, Register cnt2, Register result,
|
|
|
1138 XMMRegister vec1);
|
|
|
1139
|
|
|
1140 // Compare char[] arrays.
|
|
|
1141 void char_arrays_equals(bool is_array_equ, Register ary1, Register ary2,
|
|
|
1142 Register limit, Register result, Register chr,
|
|
|
1143 XMMRegister vec1, XMMRegister vec2);
|
|
|
1144
|
|
|
1145 // Fill primitive arrays
|
|
|
1146 void generate_fill(BasicType t, bool aligned,
|
|
|
1147 Register to, Register value, Register count,
|
|
|
1148 Register rtmp, XMMRegister xtmp);
|
|
|
1149
|
|
|
1150 #undef VIRTUAL
|
|
|
1151
|
|
|
1152 };
|
|
|
1153
|
|
|
1154 /**
|
|
|
1155 * class SkipIfEqual:
|
|
|
1156 *
|
|
|
1157 * Instantiating this class will result in assembly code being output that will
|
|
|
1158 * jump around any code emitted between the creation of the instance and it's
|
|
|
1159 * automatic destruction at the end of a scope block, depending on the value of
|
|
|
1160 * the flag passed to the constructor, which will be checked at run-time.
|
|
|
1161 */
|
|
|
1162 class SkipIfEqual {
|
|
|
1163 private:
|
|
|
1164 MacroAssembler* _masm;
|
|
|
1165 Label _label;
|
|
|
1166
|
|
|
1167 public:
|
|
|
1168 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
|
|
|
1169 ~SkipIfEqual();
|
|
|
1170 };
|
|
|
1171
|
|
|
1172 #endif // CPU_X86_VM_MACROASSEMBLER_X86_HPP
|
