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1 /*
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2 * Copyright 2003-2007 Sun Microsystems, Inc. All Rights Reserved.
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3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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4 *
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5 * This code is free software; you can redistribute it and/or modify it
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6 * under the terms of the GNU General Public License version 2 only, as
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7 * published by the Free Software Foundation.
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8 *
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9 * This code is distributed in the hope that it will be useful, but WITHOUT
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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12 * version 2 for more details (a copy is included in the LICENSE file that
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13 * accompanied this code).
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14 *
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15 * You should have received a copy of the GNU General Public License version
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16 * 2 along with this work; if not, write to the Free Software Foundation,
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17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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18 *
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19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
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20 * CA 95054 USA or visit www.sun.com if you need additional information or
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21 * have any questions.
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22 *
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23 */
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24
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25 class BiasedLockingCounters;
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26
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27 // Contains all the definitions needed for amd64 assembly code generation.
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28
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29 #ifdef _LP64
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30 // Calling convention
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31 class Argument VALUE_OBJ_CLASS_SPEC {
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32 public:
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33 enum {
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34 #ifdef _WIN64
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35 n_int_register_parameters_c = 4, // rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...)
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36 n_float_register_parameters_c = 4, // xmm0 - xmm3 (c_farg0, c_farg1, ... )
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37 #else
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38 n_int_register_parameters_c = 6, // rdi, rsi, rdx, rcx, r8, r9 (c_rarg0, c_rarg1, ...)
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39 n_float_register_parameters_c = 8, // xmm0 - xmm7 (c_farg0, c_farg1, ... )
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40 #endif
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41 n_int_register_parameters_j = 6, // j_rarg0, j_rarg1, ...
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42 n_float_register_parameters_j = 8 // j_farg0, j_farg1, ...
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43 };
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44 };
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45
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46
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47 // Symbolically name the register arguments used by the c calling convention.
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48 // Windows is different from linux/solaris. So much for standards...
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49
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50 #ifdef _WIN64
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51
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52 REGISTER_DECLARATION(Register, c_rarg0, rcx);
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53 REGISTER_DECLARATION(Register, c_rarg1, rdx);
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54 REGISTER_DECLARATION(Register, c_rarg2, r8);
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55 REGISTER_DECLARATION(Register, c_rarg3, r9);
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56
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57 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0);
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58 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1);
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59 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2);
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60 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3);
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61
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62 #else
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63
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64 REGISTER_DECLARATION(Register, c_rarg0, rdi);
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65 REGISTER_DECLARATION(Register, c_rarg1, rsi);
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66 REGISTER_DECLARATION(Register, c_rarg2, rdx);
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67 REGISTER_DECLARATION(Register, c_rarg3, rcx);
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68 REGISTER_DECLARATION(Register, c_rarg4, r8);
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69 REGISTER_DECLARATION(Register, c_rarg5, r9);
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70
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71 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0);
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72 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1);
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73 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2);
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74 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3);
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75 REGISTER_DECLARATION(XMMRegister, c_farg4, xmm4);
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76 REGISTER_DECLARATION(XMMRegister, c_farg5, xmm5);
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77 REGISTER_DECLARATION(XMMRegister, c_farg6, xmm6);
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78 REGISTER_DECLARATION(XMMRegister, c_farg7, xmm7);
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79
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80 #endif
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81
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82 // Symbolically name the register arguments used by the Java calling convention.
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83 // We have control over the convention for java so we can do what we please.
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84 // What pleases us is to offset the java calling convention so that when
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85 // we call a suitable jni method the arguments are lined up and we don't
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86 // have to do little shuffling. A suitable jni method is non-static and a
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87 // small number of arguments (two fewer args on windows)
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88 //
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89 // |-------------------------------------------------------|
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90 // | c_rarg0 c_rarg1 c_rarg2 c_rarg3 c_rarg4 c_rarg5 |
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91 // |-------------------------------------------------------|
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92 // | rcx rdx r8 r9 rdi* rsi* | windows (* not a c_rarg)
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93 // | rdi rsi rdx rcx r8 r9 | solaris/linux
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94 // |-------------------------------------------------------|
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95 // | j_rarg5 j_rarg0 j_rarg1 j_rarg2 j_rarg3 j_rarg4 |
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96 // |-------------------------------------------------------|
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97
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98 REGISTER_DECLARATION(Register, j_rarg0, c_rarg1);
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99 REGISTER_DECLARATION(Register, j_rarg1, c_rarg2);
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100 REGISTER_DECLARATION(Register, j_rarg2, c_rarg3);
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101 // Windows runs out of register args here
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102 #ifdef _WIN64
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103 REGISTER_DECLARATION(Register, j_rarg3, rdi);
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104 REGISTER_DECLARATION(Register, j_rarg4, rsi);
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105 #else
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106 REGISTER_DECLARATION(Register, j_rarg3, c_rarg4);
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107 REGISTER_DECLARATION(Register, j_rarg4, c_rarg5);
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108 #endif /* _WIN64 */
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109 REGISTER_DECLARATION(Register, j_rarg5, c_rarg0);
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110
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111 REGISTER_DECLARATION(XMMRegister, j_farg0, xmm0);
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112 REGISTER_DECLARATION(XMMRegister, j_farg1, xmm1);
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113 REGISTER_DECLARATION(XMMRegister, j_farg2, xmm2);
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114 REGISTER_DECLARATION(XMMRegister, j_farg3, xmm3);
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115 REGISTER_DECLARATION(XMMRegister, j_farg4, xmm4);
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116 REGISTER_DECLARATION(XMMRegister, j_farg5, xmm5);
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117 REGISTER_DECLARATION(XMMRegister, j_farg6, xmm6);
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118 REGISTER_DECLARATION(XMMRegister, j_farg7, xmm7);
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119
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120 REGISTER_DECLARATION(Register, rscratch1, r10); // volatile
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121 REGISTER_DECLARATION(Register, rscratch2, r11); // volatile
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122
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123 REGISTER_DECLARATION(Register, r15_thread, r15); // callee-saved
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124
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125 #endif // _LP64
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126
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127 // Address is an abstraction used to represent a memory location
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128 // using any of the amd64 addressing modes with one object.
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129 //
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130 // Note: A register location is represented via a Register, not
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131 // via an address for efficiency & simplicity reasons.
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132
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133 class ArrayAddress;
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134
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135 class Address VALUE_OBJ_CLASS_SPEC {
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136 public:
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137 enum ScaleFactor {
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138 no_scale = -1,
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139 times_1 = 0,
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140 times_2 = 1,
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141 times_4 = 2,
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142 times_8 = 3
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143 };
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144
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145 private:
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146 Register _base;
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147 Register _index;
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148 ScaleFactor _scale;
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149 int _disp;
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150 RelocationHolder _rspec;
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151
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152 // Easily misused constructors make them private
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153 Address(int disp, address loc, relocInfo::relocType rtype);
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154 Address(int disp, address loc, RelocationHolder spec);
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155
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156 public:
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157 // creation
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158 Address()
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159 : _base(noreg),
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160 _index(noreg),
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161 _scale(no_scale),
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162 _disp(0) {
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163 }
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164
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165 // No default displacement otherwise Register can be implicitly
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166 // converted to 0(Register) which is quite a different animal.
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167
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168 Address(Register base, int disp)
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169 : _base(base),
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170 _index(noreg),
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171 _scale(no_scale),
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172 _disp(disp) {
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173 }
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174
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175 Address(Register base, Register index, ScaleFactor scale, int disp = 0)
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176 : _base (base),
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177 _index(index),
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178 _scale(scale),
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179 _disp (disp) {
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180 assert(!index->is_valid() == (scale == Address::no_scale),
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181 "inconsistent address");
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182 }
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183
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184 // The following two overloads are used in connection with the
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185 // ByteSize type (see sizes.hpp). They simplify the use of
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186 // ByteSize'd arguments in assembly code. Note that their equivalent
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187 // for the optimized build are the member functions with int disp
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188 // argument since ByteSize is mapped to an int type in that case.
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189 //
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190 // Note: DO NOT introduce similar overloaded functions for WordSize
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191 // arguments as in the optimized mode, both ByteSize and WordSize
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192 // are mapped to the same type and thus the compiler cannot make a
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193 // distinction anymore (=> compiler errors).
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194
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195 #ifdef ASSERT
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196 Address(Register base, ByteSize disp)
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197 : _base(base),
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198 _index(noreg),
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199 _scale(no_scale),
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200 _disp(in_bytes(disp)) {
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201 }
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202
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203 Address(Register base, Register index, ScaleFactor scale, ByteSize disp)
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204 : _base(base),
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205 _index(index),
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206 _scale(scale),
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207 _disp(in_bytes(disp)) {
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208 assert(!index->is_valid() == (scale == Address::no_scale),
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209 "inconsistent address");
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210 }
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211 #endif // ASSERT
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212
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213 // accessors
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214 bool uses(Register reg) const {
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215 return _base == reg || _index == reg;
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216 }
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217
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218 // Convert the raw encoding form into the form expected by the constructor for
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219 // Address. An index of 4 (rsp) corresponds to having no index, so convert
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220 // that to noreg for the Address constructor.
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221 static Address make_raw(int base, int index, int scale, int disp);
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222
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223 static Address make_array(ArrayAddress);
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224
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225 private:
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226 bool base_needs_rex() const {
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227 return _base != noreg && _base->encoding() >= 8;
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228 }
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229
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230 bool index_needs_rex() const {
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231 return _index != noreg &&_index->encoding() >= 8;
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232 }
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233
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234 relocInfo::relocType reloc() const { return _rspec.type(); }
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235
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236 friend class Assembler;
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237 friend class MacroAssembler;
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238 friend class LIR_Assembler; // base/index/scale/disp
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239 };
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240
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241 //
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242 // AddressLiteral has been split out from Address because operands of this type
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243 // need to be treated specially on 32bit vs. 64bit platforms. By splitting it out
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244 // the few instructions that need to deal with address literals are unique and the
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245 // MacroAssembler does not have to implement every instruction in the Assembler
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246 // in order to search for address literals that may need special handling depending
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247 // on the instruction and the platform. As small step on the way to merging i486/amd64
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248 // directories.
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249 //
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250 class AddressLiteral VALUE_OBJ_CLASS_SPEC {
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251 friend class ArrayAddress;
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252 RelocationHolder _rspec;
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253 // Typically we use AddressLiterals we want to use their rval
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254 // However in some situations we want the lval (effect address) of the item.
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255 // We provide a special factory for making those lvals.
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256 bool _is_lval;
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257
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258 // If the target is far we'll need to load the ea of this to
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259 // a register to reach it. Otherwise if near we can do rip
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260 // relative addressing.
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261
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262 address _target;
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263
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264 protected:
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265 // creation
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266 AddressLiteral()
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267 : _is_lval(false),
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268 _target(NULL)
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269 {}
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270
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271 public:
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272
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273
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274 AddressLiteral(address target, relocInfo::relocType rtype);
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275
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276 AddressLiteral(address target, RelocationHolder const& rspec)
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277 : _rspec(rspec),
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278 _is_lval(false),
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279 _target(target)
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280 {}
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281
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282 AddressLiteral addr() {
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283 AddressLiteral ret = *this;
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284 ret._is_lval = true;
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285 return ret;
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286 }
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287
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288
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289 private:
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290
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291 address target() { return _target; }
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292 bool is_lval() { return _is_lval; }
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293
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294 relocInfo::relocType reloc() const { return _rspec.type(); }
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295 const RelocationHolder& rspec() const { return _rspec; }
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296
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297 friend class Assembler;
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298 friend class MacroAssembler;
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299 friend class Address;
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300 friend class LIR_Assembler;
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301 };
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302
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303 // Convience classes
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304 class RuntimeAddress: public AddressLiteral {
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305
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306 public:
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307
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308 RuntimeAddress(address target) : AddressLiteral(target, relocInfo::runtime_call_type) {}
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309
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310 };
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311
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312 class OopAddress: public AddressLiteral {
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313
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314 public:
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315
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316 OopAddress(address target) : AddressLiteral(target, relocInfo::oop_type){}
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317
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318 };
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319
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320 class ExternalAddress: public AddressLiteral {
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321
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322 public:
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323
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324 ExternalAddress(address target) : AddressLiteral(target, relocInfo::external_word_type){}
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325
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326 };
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327
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328 class InternalAddress: public AddressLiteral {
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329
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330 public:
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331
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332 InternalAddress(address target) : AddressLiteral(target, relocInfo::internal_word_type) {}
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333
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334 };
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335
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336 // x86 can do array addressing as a single operation since disp can be an absolute
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337 // address but amd64 can't [e.g. array_base(rx, ry:width) ]. We create a class
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338 // that expresses the concept but does extra magic on amd64 to get the final result
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339
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340 class ArrayAddress VALUE_OBJ_CLASS_SPEC {
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341 private:
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342
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343 AddressLiteral _base;
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344 Address _index;
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345
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346 public:
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347
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348 ArrayAddress() {};
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349 ArrayAddress(AddressLiteral base, Address index): _base(base), _index(index) {};
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350 AddressLiteral base() { return _base; }
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351 Address index() { return _index; }
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352
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353 };
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354
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355 // The amd64 Assembler: Pure assembler doing NO optimizations on
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356 // the instruction level (e.g. mov rax, 0 is not translated into xor
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357 // rax, rax!); i.e., what you write is what you get. The Assembler is
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358 // generating code into a CodeBuffer.
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359
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360 const int FPUStateSizeInWords = 512 / wordSize;
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361
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362 class Assembler : public AbstractAssembler {
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363 friend class AbstractAssembler; // for the non-virtual hack
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364 friend class StubGenerator;
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365
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366
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367 protected:
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368 #ifdef ASSERT
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369 void check_relocation(RelocationHolder const& rspec, int format);
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370 #endif
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371
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372 inline void emit_long64(jlong x);
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373
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374 void emit_data(jint data, relocInfo::relocType rtype, int format /* = 1 */);
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375 void emit_data(jint data, RelocationHolder const& rspec, int format /* = 1 */);
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376 void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0);
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377 void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0);
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378
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379 // Helper functions for groups of instructions
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380 void emit_arith_b(int op1, int op2, Register dst, int imm8);
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381
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382 void emit_arith(int op1, int op2, Register dst, int imm32);
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383 // only x86??
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384 void emit_arith(int op1, int op2, Register dst, jobject obj);
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385 void emit_arith(int op1, int op2, Register dst, Register src);
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386
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387 void emit_operand(Register reg,
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388 Register base, Register index, Address::ScaleFactor scale,
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389 int disp,
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390 RelocationHolder const& rspec,
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391 int rip_relative_correction = 0);
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392 void emit_operand(Register reg, Address adr,
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393 int rip_relative_correction = 0);
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394 void emit_operand(XMMRegister reg,
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395 Register base, Register index, Address::ScaleFactor scale,
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396 int disp,
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397 RelocationHolder const& rspec,
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398 int rip_relative_correction = 0);
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399 void emit_operand(XMMRegister reg, Address adr,
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400 int rip_relative_correction = 0);
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401
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402 // Immediate-to-memory forms
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403 void emit_arith_operand(int op1, Register rm, Address adr, int imm32);
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404
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405 void emit_farith(int b1, int b2, int i);
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406
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407 bool reachable(AddressLiteral adr);
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408
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409 // These are all easily abused and hence protected
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410
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411 // Make these disappear in 64bit mode since they would never be correct
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412 #ifndef _LP64
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413 void cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec);
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414 void cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec);
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415
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416 void mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec);
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417 void mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec);
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418
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419 void push_literal32(int32_t imm32, RelocationHolder const& rspec);
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420 #endif // _LP64
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421
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422
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423 void mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec);
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424
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425 // These are unique in that we are ensured by the caller that the 32bit
|
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426 // relative in these instructions will always be able to reach the potentially
|
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427 // 64bit address described by entry. Since they can take a 64bit address they
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|
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428 // don't have the 32 suffix like the other instructions in this class.
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429 void jmp_literal(address entry, RelocationHolder const& rspec);
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|
430 void call_literal(address entry, RelocationHolder const& rspec);
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431
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432 public:
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|
433 enum Condition { // The amd64 condition codes used for conditional jumps/moves.
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434 zero = 0x4,
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|
435 notZero = 0x5,
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436 equal = 0x4,
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|
|
437 notEqual = 0x5,
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|
438 less = 0xc,
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|
|
439 lessEqual = 0xe,
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|
440 greater = 0xf,
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|
441 greaterEqual = 0xd,
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|
442 below = 0x2,
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443 belowEqual = 0x6,
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444 above = 0x7,
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445 aboveEqual = 0x3,
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446 overflow = 0x0,
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|
447 noOverflow = 0x1,
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|
448 carrySet = 0x2,
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|
449 carryClear = 0x3,
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|
450 negative = 0x8,
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|
451 positive = 0x9,
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|
452 parity = 0xa,
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|
453 noParity = 0xb
|
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|
454 };
|
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|
455
|
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|
456 enum Prefix {
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|
457 // segment overrides
|
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|
458 // XXX remove segment prefixes
|
|
|
459 CS_segment = 0x2e,
|
|
|
460 SS_segment = 0x36,
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|
|
461 DS_segment = 0x3e,
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|
462 ES_segment = 0x26,
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|
463 FS_segment = 0x64,
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|
464 GS_segment = 0x65,
|
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465
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|
|
466 REX = 0x40,
|
|
|
467
|
|
|
468 REX_B = 0x41,
|
|
|
469 REX_X = 0x42,
|
|
|
470 REX_XB = 0x43,
|
|
|
471 REX_R = 0x44,
|
|
|
472 REX_RB = 0x45,
|
|
|
473 REX_RX = 0x46,
|
|
|
474 REX_RXB = 0x47,
|
|
|
475
|
|
|
476 REX_W = 0x48,
|
|
|
477
|
|
|
478 REX_WB = 0x49,
|
|
|
479 REX_WX = 0x4A,
|
|
|
480 REX_WXB = 0x4B,
|
|
|
481 REX_WR = 0x4C,
|
|
|
482 REX_WRB = 0x4D,
|
|
|
483 REX_WRX = 0x4E,
|
|
|
484 REX_WRXB = 0x4F
|
|
|
485 };
|
|
|
486
|
|
|
487 enum WhichOperand {
|
|
|
488 // input to locate_operand, and format code for relocations
|
|
|
489 imm64_operand = 0, // embedded 64-bit immediate operand
|
|
|
490 disp32_operand = 1, // embedded 32-bit displacement
|
|
|
491 call32_operand = 2, // embedded 32-bit self-relative displacement
|
|
|
492 _WhichOperand_limit = 3
|
|
|
493 };
|
|
|
494
|
|
|
495 public:
|
|
|
496
|
|
|
497 // Creation
|
|
|
498 Assembler(CodeBuffer* code)
|
|
|
499 : AbstractAssembler(code) {
|
|
|
500 }
|
|
|
501
|
|
|
502 // Decoding
|
|
|
503 static address locate_operand(address inst, WhichOperand which);
|
|
|
504 static address locate_next_instruction(address inst);
|
|
|
505
|
|
|
506 // Utilities
|
|
|
507
|
|
|
508 static bool is_simm(int64_t x, int nbits) { return -( CONST64(1) << (nbits-1) ) <= x && x < ( CONST64(1) << (nbits-1) ); }
|
|
|
509 static bool is_simm32 (int64_t x) { return x == (int64_t)(int32_t)x; }
|
|
|
510
|
|
|
511
|
|
|
512 // Stack
|
|
|
513 void pushaq();
|
|
|
514 void popaq();
|
|
|
515
|
|
|
516 void pushfq();
|
|
|
517 void popfq();
|
|
|
518
|
|
|
519 void pushq(int imm32);
|
|
|
520
|
|
|
521 void pushq(Register src);
|
|
|
522 void pushq(Address src);
|
|
|
523
|
|
|
524 void popq(Register dst);
|
|
|
525 void popq(Address dst);
|
|
|
526
|
|
|
527 // Instruction prefixes
|
|
|
528 void prefix(Prefix p);
|
|
|
529
|
|
|
530 int prefix_and_encode(int reg_enc, bool byteinst = false);
|
|
|
531 int prefixq_and_encode(int reg_enc);
|
|
|
532
|
|
|
533 int prefix_and_encode(int dst_enc, int src_enc, bool byteinst = false);
|
|
|
534 int prefixq_and_encode(int dst_enc, int src_enc);
|
|
|
535
|
|
|
536 void prefix(Register reg);
|
|
|
537 void prefix(Address adr);
|
|
|
538 void prefixq(Address adr);
|
|
|
539
|
|
|
540 void prefix(Address adr, Register reg, bool byteinst = false);
|
|
|
541 void prefixq(Address adr, Register reg);
|
|
|
542
|
|
|
543 void prefix(Address adr, XMMRegister reg);
|
|
|
544
|
|
|
545 // Moves
|
|
|
546 void movb(Register dst, Address src);
|
|
|
547 void movb(Address dst, int imm8);
|
|
|
548 void movb(Address dst, Register src);
|
|
|
549
|
|
|
550 void movw(Address dst, int imm16);
|
|
|
551 void movw(Register dst, Address src);
|
|
|
552 void movw(Address dst, Register src);
|
|
|
553
|
|
|
554 void movl(Register dst, int imm32);
|
|
|
555 void movl(Register dst, Register src);
|
|
|
556 void movl(Register dst, Address src);
|
|
|
557 void movl(Address dst, int imm32);
|
|
|
558 void movl(Address dst, Register src);
|
|
|
559
|
|
|
560 void movq(Register dst, Register src);
|
|
|
561 void movq(Register dst, Address src);
|
|
|
562 void movq(Address dst, Register src);
|
|
|
563 // These prevent using movq from converting a zero (like NULL) into Register
|
|
|
564 // by giving the compiler two choices it can't resolve
|
|
|
565 void movq(Address dst, void* dummy);
|
|
|
566 void movq(Register dst, void* dummy);
|
|
|
567
|
|
|
568 void mov64(Register dst, intptr_t imm64);
|
|
|
569 void mov64(Address dst, intptr_t imm64);
|
|
|
570
|
|
|
571 void movsbl(Register dst, Address src);
|
|
|
572 void movsbl(Register dst, Register src);
|
|
|
573 void movswl(Register dst, Address src);
|
|
|
574 void movswl(Register dst, Register src);
|
|
|
575 void movslq(Register dst, Address src);
|
|
|
576 void movslq(Register dst, Register src);
|
|
|
577
|
|
|
578 void movzbl(Register dst, Address src);
|
|
|
579 void movzbl(Register dst, Register src);
|
|
|
580 void movzwl(Register dst, Address src);
|
|
|
581 void movzwl(Register dst, Register src);
|
|
|
582
|
|
|
583 protected: // Avoid using the next instructions directly.
|
|
|
584 // New cpus require use of movsd and movss to avoid partial register stall
|
|
|
585 // when loading from memory. But for old Opteron use movlpd instead of movsd.
|
|
|
586 // The selection is done in MacroAssembler::movdbl() and movflt().
|
|
|
587 void movss(XMMRegister dst, XMMRegister src);
|
|
|
588 void movss(XMMRegister dst, Address src);
|
|
|
589 void movss(Address dst, XMMRegister src);
|
|
|
590 void movsd(XMMRegister dst, XMMRegister src);
|
|
|
591 void movsd(Address dst, XMMRegister src);
|
|
|
592 void movsd(XMMRegister dst, Address src);
|
|
|
593 void movlpd(XMMRegister dst, Address src);
|
|
|
594 // New cpus require use of movaps and movapd to avoid partial register stall
|
|
|
595 // when moving between registers.
|
|
|
596 void movapd(XMMRegister dst, XMMRegister src);
|
|
|
597 void movaps(XMMRegister dst, XMMRegister src);
|
|
|
598 public:
|
|
|
599
|
|
|
600 void movdl(XMMRegister dst, Register src);
|
|
|
601 void movdl(Register dst, XMMRegister src);
|
|
|
602 void movdq(XMMRegister dst, Register src);
|
|
|
603 void movdq(Register dst, XMMRegister src);
|
|
|
604
|
|
|
605 void cmovl(Condition cc, Register dst, Register src);
|
|
|
606 void cmovl(Condition cc, Register dst, Address src);
|
|
|
607 void cmovq(Condition cc, Register dst, Register src);
|
|
|
608 void cmovq(Condition cc, Register dst, Address src);
|
|
|
609
|
|
|
610 // Prefetches
|
|
|
611 private:
|
|
|
612 void prefetch_prefix(Address src);
|
|
|
613 public:
|
|
|
614 void prefetcht0(Address src);
|
|
|
615 void prefetcht1(Address src);
|
|
|
616 void prefetcht2(Address src);
|
|
|
617 void prefetchnta(Address src);
|
|
|
618 void prefetchw(Address src);
|
|
|
619
|
|
|
620 // Arithmetics
|
|
|
621 void adcl(Register dst, int imm32);
|
|
|
622 void adcl(Register dst, Address src);
|
|
|
623 void adcl(Register dst, Register src);
|
|
|
624 void adcq(Register dst, int imm32);
|
|
|
625 void adcq(Register dst, Address src);
|
|
|
626 void adcq(Register dst, Register src);
|
|
|
627
|
|
|
628 void addl(Address dst, int imm32);
|
|
|
629 void addl(Address dst, Register src);
|
|
|
630 void addl(Register dst, int imm32);
|
|
|
631 void addl(Register dst, Address src);
|
|
|
632 void addl(Register dst, Register src);
|
|
|
633 void addq(Address dst, int imm32);
|
|
|
634 void addq(Address dst, Register src);
|
|
|
635 void addq(Register dst, int imm32);
|
|
|
636 void addq(Register dst, Address src);
|
|
|
637 void addq(Register dst, Register src);
|
|
|
638
|
|
|
639 void andl(Register dst, int imm32);
|
|
|
640 void andl(Register dst, Address src);
|
|
|
641 void andl(Register dst, Register src);
|
|
|
642 void andq(Register dst, int imm32);
|
|
|
643 void andq(Register dst, Address src);
|
|
|
644 void andq(Register dst, Register src);
|
|
|
645
|
|
|
646 void cmpb(Address dst, int imm8);
|
|
|
647 void cmpl(Address dst, int imm32);
|
|
|
648 void cmpl(Register dst, int imm32);
|
|
|
649 void cmpl(Register dst, Register src);
|
|
|
650 void cmpl(Register dst, Address src);
|
|
|
651 void cmpq(Address dst, int imm32);
|
|
|
652 void cmpq(Address dst, Register src);
|
|
|
653 void cmpq(Register dst, int imm32);
|
|
|
654 void cmpq(Register dst, Register src);
|
|
|
655 void cmpq(Register dst, Address src);
|
|
|
656
|
|
|
657 void ucomiss(XMMRegister dst, XMMRegister src);
|
|
|
658 void ucomisd(XMMRegister dst, XMMRegister src);
|
|
|
659
|
|
|
660 protected:
|
|
|
661 // Don't use next inc() and dec() methods directly. INC & DEC instructions
|
|
|
662 // could cause a partial flag stall since they don't set CF flag.
|
|
|
663 // Use MacroAssembler::decrement() & MacroAssembler::increment() methods
|
|
|
664 // which call inc() & dec() or add() & sub() in accordance with
|
|
|
665 // the product flag UseIncDec value.
|
|
|
666
|
|
|
667 void decl(Register dst);
|
|
|
668 void decl(Address dst);
|
|
|
669 void decq(Register dst);
|
|
|
670 void decq(Address dst);
|
|
|
671
|
|
|
672 void incl(Register dst);
|
|
|
673 void incl(Address dst);
|
|
|
674 void incq(Register dst);
|
|
|
675 void incq(Address dst);
|
|
|
676
|
|
|
677 public:
|
|
|
678 void idivl(Register src);
|
|
|
679 void idivq(Register src);
|
|
|
680 void cdql();
|
|
|
681 void cdqq();
|
|
|
682
|
|
|
683 void imull(Register dst, Register src);
|
|
|
684 void imull(Register dst, Register src, int value);
|
|
|
685 void imulq(Register dst, Register src);
|
|
|
686 void imulq(Register dst, Register src, int value);
|
|
|
687
|
|
|
688 void leal(Register dst, Address src);
|
|
|
689 void leaq(Register dst, Address src);
|
|
|
690
|
|
|
691 void mull(Address src);
|
|
|
692 void mull(Register src);
|
|
|
693
|
|
|
694 void negl(Register dst);
|
|
|
695 void negq(Register dst);
|
|
|
696
|
|
|
697 void notl(Register dst);
|
|
|
698 void notq(Register dst);
|
|
|
699
|
|
|
700 void orl(Address dst, int imm32);
|
|
|
701 void orl(Register dst, int imm32);
|
|
|
702 void orl(Register dst, Address src);
|
|
|
703 void orl(Register dst, Register src);
|
|
|
704 void orq(Address dst, int imm32);
|
|
|
705 void orq(Register dst, int imm32);
|
|
|
706 void orq(Register dst, Address src);
|
|
|
707 void orq(Register dst, Register src);
|
|
|
708
|
|
|
709 void rcll(Register dst, int imm8);
|
|
|
710 void rclq(Register dst, int imm8);
|
|
|
711
|
|
|
712 void sarl(Register dst, int imm8);
|
|
|
713 void sarl(Register dst);
|
|
|
714 void sarq(Register dst, int imm8);
|
|
|
715 void sarq(Register dst);
|
|
|
716
|
|
|
717 void sbbl(Address dst, int imm32);
|
|
|
718 void sbbl(Register dst, int imm32);
|
|
|
719 void sbbl(Register dst, Address src);
|
|
|
720 void sbbl(Register dst, Register src);
|
|
|
721 void sbbq(Address dst, int imm32);
|
|
|
722 void sbbq(Register dst, int imm32);
|
|
|
723 void sbbq(Register dst, Address src);
|
|
|
724 void sbbq(Register dst, Register src);
|
|
|
725
|
|
|
726 void shll(Register dst, int imm8);
|
|
|
727 void shll(Register dst);
|
|
|
728 void shlq(Register dst, int imm8);
|
|
|
729 void shlq(Register dst);
|
|
|
730
|
|
|
731 void shrl(Register dst, int imm8);
|
|
|
732 void shrl(Register dst);
|
|
|
733 void shrq(Register dst, int imm8);
|
|
|
734 void shrq(Register dst);
|
|
|
735
|
|
|
736 void subl(Address dst, int imm32);
|
|
|
737 void subl(Address dst, Register src);
|
|
|
738 void subl(Register dst, int imm32);
|
|
|
739 void subl(Register dst, Address src);
|
|
|
740 void subl(Register dst, Register src);
|
|
|
741 void subq(Address dst, int imm32);
|
|
|
742 void subq(Address dst, Register src);
|
|
|
743 void subq(Register dst, int imm32);
|
|
|
744 void subq(Register dst, Address src);
|
|
|
745 void subq(Register dst, Register src);
|
|
|
746
|
|
|
747 void testb(Register dst, int imm8);
|
|
|
748 void testl(Register dst, int imm32);
|
|
|
749 void testl(Register dst, Register src);
|
|
|
750 void testq(Register dst, int imm32);
|
|
|
751 void testq(Register dst, Register src);
|
|
|
752
|
|
|
753 void xaddl(Address dst, Register src);
|
|
|
754 void xaddq(Address dst, Register src);
|
|
|
755
|
|
|
756 void xorl(Register dst, int imm32);
|
|
|
757 void xorl(Register dst, Address src);
|
|
|
758 void xorl(Register dst, Register src);
|
|
|
759 void xorq(Register dst, int imm32);
|
|
|
760 void xorq(Register dst, Address src);
|
|
|
761 void xorq(Register dst, Register src);
|
|
|
762
|
|
|
763 // Miscellaneous
|
|
|
764 void bswapl(Register reg);
|
|
|
765 void bswapq(Register reg);
|
|
|
766 void lock();
|
|
|
767
|
|
|
768 void xchgl(Register reg, Address adr);
|
|
|
769 void xchgl(Register dst, Register src);
|
|
|
770 void xchgq(Register reg, Address adr);
|
|
|
771 void xchgq(Register dst, Register src);
|
|
|
772
|
|
|
773 void cmpxchgl(Register reg, Address adr);
|
|
|
774 void cmpxchgq(Register reg, Address adr);
|
|
|
775
|
|
|
776 void nop(int i = 1);
|
|
|
777 void addr_nop_4();
|
|
|
778 void addr_nop_5();
|
|
|
779 void addr_nop_7();
|
|
|
780 void addr_nop_8();
|
|
|
781
|
|
|
782 void hlt();
|
|
|
783 void ret(int imm16);
|
|
|
784 void smovl();
|
|
|
785 void rep_movl();
|
|
|
786 void rep_movq();
|
|
|
787 void rep_set();
|
|
|
788 void repne_scan();
|
|
|
789 void setb(Condition cc, Register dst);
|
|
|
790
|
|
|
791 void clflush(Address adr);
|
|
|
792
|
|
|
793 enum Membar_mask_bits {
|
|
|
794 StoreStore = 1 << 3,
|
|
|
795 LoadStore = 1 << 2,
|
|
|
796 StoreLoad = 1 << 1,
|
|
|
797 LoadLoad = 1 << 0
|
|
|
798 };
|
|
|
799
|
|
|
800 // Serializes memory.
|
|
|
801 void membar(Membar_mask_bits order_constraint) {
|
|
|
802 // We only have to handle StoreLoad and LoadLoad
|
|
|
803 if (order_constraint & StoreLoad) {
|
|
|
804 // MFENCE subsumes LFENCE
|
|
|
805 mfence();
|
|
|
806 } /* [jk] not needed currently: else if (order_constraint & LoadLoad) {
|
|
|
807 lfence();
|
|
|
808 } */
|
|
|
809 }
|
|
|
810
|
|
|
811 void lfence() {
|
|
|
812 emit_byte(0x0F);
|
|
|
813 emit_byte(0xAE);
|
|
|
814 emit_byte(0xE8);
|
|
|
815 }
|
|
|
816
|
|
|
817 void mfence() {
|
|
|
818 emit_byte(0x0F);
|
|
|
819 emit_byte(0xAE);
|
|
|
820 emit_byte(0xF0);
|
|
|
821 }
|
|
|
822
|
|
|
823 // Identify processor type and features
|
|
|
824 void cpuid() {
|
|
|
825 emit_byte(0x0F);
|
|
|
826 emit_byte(0xA2);
|
|
|
827 }
|
|
|
828
|
|
|
829 void cld() { emit_byte(0xfc);
|
|
|
830 }
|
|
|
831
|
|
|
832 void std() { emit_byte(0xfd);
|
|
|
833 }
|
|
|
834
|
|
|
835
|
|
|
836 // Calls
|
|
|
837
|
|
|
838 void call(Label& L, relocInfo::relocType rtype);
|
|
|
839 void call(Register reg);
|
|
|
840 void call(Address adr);
|
|
|
841
|
|
|
842 // Jumps
|
|
|
843
|
|
|
844 void jmp(Register reg);
|
|
|
845 void jmp(Address adr);
|
|
|
846
|
|
|
847 // Label operations & relative jumps (PPUM Appendix D)
|
|
|
848 // unconditional jump to L
|
|
|
849 void jmp(Label& L, relocInfo::relocType rtype = relocInfo::none);
|
|
|
850
|
|
|
851
|
|
|
852 // Unconditional 8-bit offset jump to L.
|
|
|
853 // WARNING: be very careful using this for forward jumps. If the label is
|
|
|
854 // not bound within an 8-bit offset of this instruction, a run-time error
|
|
|
855 // will occur.
|
|
|
856 void jmpb(Label& L);
|
|
|
857
|
|
|
858 // jcc is the generic conditional branch generator to run- time
|
|
|
859 // routines, jcc is used for branches to labels. jcc takes a branch
|
|
|
860 // opcode (cc) and a label (L) and generates either a backward
|
|
|
861 // branch or a forward branch and links it to the label fixup
|
|
|
862 // chain. Usage:
|
|
|
863 //
|
|
|
864 // Label L; // unbound label
|
|
|
865 // jcc(cc, L); // forward branch to unbound label
|
|
|
866 // bind(L); // bind label to the current pc
|
|
|
867 // jcc(cc, L); // backward branch to bound label
|
|
|
868 // bind(L); // illegal: a label may be bound only once
|
|
|
869 //
|
|
|
870 // Note: The same Label can be used for forward and backward branches
|
|
|
871 // but it may be bound only once.
|
|
|
872
|
|
|
873 void jcc(Condition cc, Label& L,
|
|
|
874 relocInfo::relocType rtype = relocInfo::none);
|
|
|
875
|
|
|
876 // Conditional jump to a 8-bit offset to L.
|
|
|
877 // WARNING: be very careful using this for forward jumps. If the label is
|
|
|
878 // not bound within an 8-bit offset of this instruction, a run-time error
|
|
|
879 // will occur.
|
|
|
880 void jccb(Condition cc, Label& L);
|
|
|
881
|
|
|
882 // Floating-point operations
|
|
|
883
|
|
|
884 void fxsave(Address dst);
|
|
|
885 void fxrstor(Address src);
|
|
|
886 void ldmxcsr(Address src);
|
|
|
887 void stmxcsr(Address dst);
|
|
|
888
|
|
|
889 void addss(XMMRegister dst, XMMRegister src);
|
|
|
890 void addss(XMMRegister dst, Address src);
|
|
|
891 void subss(XMMRegister dst, XMMRegister src);
|
|
|
892 void subss(XMMRegister dst, Address src);
|
|
|
893 void mulss(XMMRegister dst, XMMRegister src);
|
|
|
894 void mulss(XMMRegister dst, Address src);
|
|
|
895 void divss(XMMRegister dst, XMMRegister src);
|
|
|
896 void divss(XMMRegister dst, Address src);
|
|
|
897 void addsd(XMMRegister dst, XMMRegister src);
|
|
|
898 void addsd(XMMRegister dst, Address src);
|
|
|
899 void subsd(XMMRegister dst, XMMRegister src);
|
|
|
900 void subsd(XMMRegister dst, Address src);
|
|
|
901 void mulsd(XMMRegister dst, XMMRegister src);
|
|
|
902 void mulsd(XMMRegister dst, Address src);
|
|
|
903 void divsd(XMMRegister dst, XMMRegister src);
|
|
|
904 void divsd(XMMRegister dst, Address src);
|
|
|
905
|
|
|
906 // We only need the double form
|
|
|
907 void sqrtsd(XMMRegister dst, XMMRegister src);
|
|
|
908 void sqrtsd(XMMRegister dst, Address src);
|
|
|
909
|
|
|
910 void xorps(XMMRegister dst, XMMRegister src);
|
|
|
911 void xorps(XMMRegister dst, Address src);
|
|
|
912 void xorpd(XMMRegister dst, XMMRegister src);
|
|
|
913 void xorpd(XMMRegister dst, Address src);
|
|
|
914
|
|
|
915 void cvtsi2ssl(XMMRegister dst, Register src);
|
|
|
916 void cvtsi2ssq(XMMRegister dst, Register src);
|
|
|
917 void cvtsi2sdl(XMMRegister dst, Register src);
|
|
|
918 void cvtsi2sdq(XMMRegister dst, Register src);
|
|
|
919 void cvttss2sil(Register dst, XMMRegister src); // truncates
|
|
|
920 void cvttss2siq(Register dst, XMMRegister src); // truncates
|
|
|
921 void cvttsd2sil(Register dst, XMMRegister src); // truncates
|
|
|
922 void cvttsd2siq(Register dst, XMMRegister src); // truncates
|
|
|
923 void cvtss2sd(XMMRegister dst, XMMRegister src);
|
|
|
924 void cvtsd2ss(XMMRegister dst, XMMRegister src);
|
|
71
|
925 void cvtdq2pd(XMMRegister dst, XMMRegister src);
|
|
|
926 void cvtdq2ps(XMMRegister dst, XMMRegister src);
|
|
0
|
927
|
|
|
928 void pxor(XMMRegister dst, Address src); // Xor Packed Byte Integer Values
|
|
|
929 void pxor(XMMRegister dst, XMMRegister src); // Xor Packed Byte Integer Values
|
|
|
930
|
|
|
931 void movdqa(XMMRegister dst, Address src); // Move Aligned Double Quadword
|
|
|
932 void movdqa(XMMRegister dst, XMMRegister src);
|
|
|
933 void movdqa(Address dst, XMMRegister src);
|
|
|
934
|
|
|
935 void movq(XMMRegister dst, Address src);
|
|
|
936 void movq(Address dst, XMMRegister src);
|
|
|
937
|
|
|
938 void pshufd(XMMRegister dst, XMMRegister src, int mode); // Shuffle Packed Doublewords
|
|
|
939 void pshufd(XMMRegister dst, Address src, int mode);
|
|
|
940 void pshuflw(XMMRegister dst, XMMRegister src, int mode); // Shuffle Packed Low Words
|
|
|
941 void pshuflw(XMMRegister dst, Address src, int mode);
|
|
|
942
|
|
|
943 void psrlq(XMMRegister dst, int shift); // Shift Right Logical Quadword Immediate
|
|
|
944
|
|
|
945 void punpcklbw(XMMRegister dst, XMMRegister src); // Interleave Low Bytes
|
|
|
946 void punpcklbw(XMMRegister dst, Address src);
|
|
|
947 };
|
|
|
948
|
|
|
949
|
|
|
950 // MacroAssembler extends Assembler by frequently used macros.
|
|
|
951 //
|
|
|
952 // Instructions for which a 'better' code sequence exists depending
|
|
|
953 // on arguments should also go in here.
|
|
|
954
|
|
|
955 class MacroAssembler : public Assembler {
|
|
|
956 friend class LIR_Assembler;
|
|
|
957 protected:
|
|
|
958
|
|
|
959 Address as_Address(AddressLiteral adr);
|
|
|
960 Address as_Address(ArrayAddress adr);
|
|
|
961
|
|
|
962 // Support for VM calls
|
|
|
963 //
|
|
|
964 // This is the base routine called by the different versions of
|
|
|
965 // call_VM_leaf. The interpreter may customize this version by
|
|
|
966 // overriding it for its purposes (e.g., to save/restore additional
|
|
|
967 // registers when doing a VM call).
|
|
|
968
|
|
|
969 virtual void call_VM_leaf_base(
|
|
|
970 address entry_point, // the entry point
|
|
|
971 int number_of_arguments // the number of arguments to
|
|
|
972 // pop after the call
|
|
|
973 );
|
|
|
974
|
|
|
975 // This is the base routine called by the different versions of
|
|
|
976 // call_VM. The interpreter may customize this version by overriding
|
|
|
977 // it for its purposes (e.g., to save/restore additional registers
|
|
|
978 // when doing a VM call).
|
|
|
979 //
|
|
|
980 // If no java_thread register is specified (noreg) than rdi will be
|
|
|
981 // used instead. call_VM_base returns the register which contains
|
|
|
982 // the thread upon return. If a thread register has been specified,
|
|
|
983 // the return value will correspond to that register. If no
|
|
|
984 // last_java_sp is specified (noreg) than rsp will be used instead.
|
|
|
985 virtual void call_VM_base( // returns the register
|
|
|
986 // containing the thread upon
|
|
|
987 // return
|
|
|
988 Register oop_result, // where an oop-result ends up
|
|
|
989 // if any; use noreg otherwise
|
|
|
990 Register java_thread, // the thread if computed
|
|
|
991 // before ; use noreg otherwise
|
|
|
992 Register last_java_sp, // to set up last_Java_frame in
|
|
|
993 // stubs; use noreg otherwise
|
|
|
994 address entry_point, // the entry point
|
|
|
995 int number_of_arguments, // the number of arguments (w/o
|
|
|
996 // thread) to pop after the
|
|
|
997 // call
|
|
|
998 bool check_exceptions // whether to check for pending
|
|
|
999 // exceptions after return
|
|
|
1000 );
|
|
|
1001
|
|
|
1002 // This routines should emit JVMTI PopFrame handling and ForceEarlyReturn code.
|
|
|
1003 // The implementation is only non-empty for the InterpreterMacroAssembler,
|
|
|
1004 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
|
|
|
1005 virtual void check_and_handle_popframe(Register java_thread);
|
|
|
1006 virtual void check_and_handle_earlyret(Register java_thread);
|
|
|
1007
|
|
|
1008 void call_VM_helper(Register oop_result,
|
|
|
1009 address entry_point,
|
|
|
1010 int number_of_arguments,
|
|
|
1011 bool check_exceptions = true);
|
|
|
1012
|
|
|
1013 public:
|
|
|
1014 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
|
|
|
1015
|
|
|
1016 // Support for NULL-checks
|
|
|
1017 //
|
|
|
1018 // Generates code that causes a NULL OS exception if the content of
|
|
|
1019 // reg is NULL. If the accessed location is M[reg + offset] and the
|
|
|
1020 // offset is known, provide the offset. No explicit code generation
|
|
|
1021 // is needed if the offset is within a certain range (0 <= offset <=
|
|
|
1022 // page_size).
|
|
|
1023 void null_check(Register reg, int offset = -1);
|
|
|
1024 static bool needs_explicit_null_check(int offset);
|
|
|
1025
|
|
|
1026 // Required platform-specific helpers for Label::patch_instructions.
|
|
|
1027 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
|
|
|
1028 void pd_patch_instruction(address branch, address target);
|
|
|
1029 #ifndef PRODUCT
|
|
|
1030 static void pd_print_patched_instruction(address branch);
|
|
|
1031 #endif
|
|
|
1032
|
|
|
1033
|
|
|
1034 // The following 4 methods return the offset of the appropriate move
|
|
|
1035 // instruction. Note: these are 32 bit instructions
|
|
|
1036
|
|
|
1037 // Support for fast byte/word loading with zero extension (depending
|
|
|
1038 // on particular CPU)
|
|
|
1039 int load_unsigned_byte(Register dst, Address src);
|
|
|
1040 int load_unsigned_word(Register dst, Address src);
|
|
|
1041
|
|
|
1042 // Support for fast byte/word loading with sign extension (depending
|
|
|
1043 // on particular CPU)
|
|
|
1044 int load_signed_byte(Register dst, Address src);
|
|
|
1045 int load_signed_word(Register dst, Address src);
|
|
|
1046
|
|
|
1047 // Support for inc/dec with optimal instruction selection depending
|
|
|
1048 // on value
|
|
|
1049 void incrementl(Register reg, int value = 1);
|
|
|
1050 void decrementl(Register reg, int value = 1);
|
|
|
1051 void incrementq(Register reg, int value = 1);
|
|
|
1052 void decrementq(Register reg, int value = 1);
|
|
|
1053
|
|
|
1054 void incrementl(Address dst, int value = 1);
|
|
|
1055 void decrementl(Address dst, int value = 1);
|
|
|
1056 void incrementq(Address dst, int value = 1);
|
|
|
1057 void decrementq(Address dst, int value = 1);
|
|
|
1058
|
|
|
1059 // Support optimal SSE move instructions.
|
|
|
1060 void movflt(XMMRegister dst, XMMRegister src) {
|
|
|
1061 if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; }
|
|
|
1062 else { movss (dst, src); return; }
|
|
|
1063 }
|
|
|
1064
|
|
|
1065 void movflt(XMMRegister dst, Address src) { movss(dst, src); }
|
|
|
1066
|
|
|
1067 void movflt(XMMRegister dst, AddressLiteral src);
|
|
|
1068
|
|
|
1069 void movflt(Address dst, XMMRegister src) { movss(dst, src); }
|
|
|
1070
|
|
|
1071 void movdbl(XMMRegister dst, XMMRegister src) {
|
|
|
1072 if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; }
|
|
|
1073 else { movsd (dst, src); return; }
|
|
|
1074 }
|
|
|
1075
|
|
|
1076 void movdbl(XMMRegister dst, AddressLiteral src);
|
|
|
1077
|
|
|
1078 void movdbl(XMMRegister dst, Address src) {
|
|
|
1079 if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; }
|
|
|
1080 else { movlpd(dst, src); return; }
|
|
|
1081 }
|
|
|
1082
|
|
|
1083 void movdbl(Address dst, XMMRegister src) { movsd(dst, src); }
|
|
|
1084
|
|
|
1085 void incrementl(AddressLiteral dst);
|
|
|
1086 void incrementl(ArrayAddress dst);
|
|
|
1087
|
|
|
1088 // Alignment
|
|
|
1089 void align(int modulus);
|
|
|
1090
|
|
|
1091 // Misc
|
|
|
1092 void fat_nop(); // 5 byte nop
|
|
|
1093
|
|
|
1094
|
|
|
1095 // C++ bool manipulation
|
|
|
1096
|
|
|
1097 void movbool(Register dst, Address src);
|
|
|
1098 void movbool(Address dst, bool boolconst);
|
|
|
1099 void movbool(Address dst, Register src);
|
|
|
1100 void testbool(Register dst);
|
|
|
1101
|
|
|
1102 // Stack frame creation/removal
|
|
|
1103 void enter();
|
|
|
1104 void leave();
|
|
|
1105
|
|
|
1106 // Support for getting the JavaThread pointer (i.e.; a reference to
|
|
|
1107 // thread-local information) The pointer will be loaded into the
|
|
|
1108 // thread register.
|
|
|
1109 void get_thread(Register thread);
|
|
|
1110
|
|
|
1111 void int3();
|
|
|
1112
|
|
|
1113 // Support for VM calls
|
|
|
1114 //
|
|
|
1115 // It is imperative that all calls into the VM are handled via the
|
|
|
1116 // call_VM macros. They make sure that the stack linkage is setup
|
|
|
1117 // correctly. call_VM's correspond to ENTRY/ENTRY_X entry points
|
|
|
1118 // while call_VM_leaf's correspond to LEAF entry points.
|
|
|
1119 void call_VM(Register oop_result,
|
|
|
1120 address entry_point,
|
|
|
1121 bool check_exceptions = true);
|
|
|
1122 void call_VM(Register oop_result,
|
|
|
1123 address entry_point,
|
|
|
1124 Register arg_1,
|
|
|
1125 bool check_exceptions = true);
|
|
|
1126 void call_VM(Register oop_result,
|
|
|
1127 address entry_point,
|
|
|
1128 Register arg_1, Register arg_2,
|
|
|
1129 bool check_exceptions = true);
|
|
|
1130 void call_VM(Register oop_result,
|
|
|
1131 address entry_point,
|
|
|
1132 Register arg_1, Register arg_2, Register arg_3,
|
|
|
1133 bool check_exceptions = true);
|
|
|
1134
|
|
|
1135 // Overloadings with last_Java_sp
|
|
|
1136 void call_VM(Register oop_result,
|
|
|
1137 Register last_java_sp,
|
|
|
1138 address entry_point,
|
|
|
1139 int number_of_arguments = 0,
|
|
|
1140 bool check_exceptions = true);
|
|
|
1141 void call_VM(Register oop_result,
|
|
|
1142 Register last_java_sp,
|
|
|
1143 address entry_point,
|
|
|
1144 Register arg_1, bool
|
|
|
1145 check_exceptions = true);
|
|
|
1146 void call_VM(Register oop_result,
|
|
|
1147 Register last_java_sp,
|
|
|
1148 address entry_point,
|
|
|
1149 Register arg_1, Register arg_2,
|
|
|
1150 bool check_exceptions = true);
|
|
|
1151 void call_VM(Register oop_result,
|
|
|
1152 Register last_java_sp,
|
|
|
1153 address entry_point,
|
|
|
1154 Register arg_1, Register arg_2, Register arg_3,
|
|
|
1155 bool check_exceptions = true);
|
|
|
1156
|
|
|
1157 void call_VM_leaf(address entry_point,
|
|
|
1158 int number_of_arguments = 0);
|
|
|
1159 void call_VM_leaf(address entry_point,
|
|
|
1160 Register arg_1);
|
|
|
1161 void call_VM_leaf(address entry_point,
|
|
|
1162 Register arg_1, Register arg_2);
|
|
|
1163 void call_VM_leaf(address entry_point,
|
|
|
1164 Register arg_1, Register arg_2, Register arg_3);
|
|
|
1165
|
|
|
1166 // last Java Frame (fills frame anchor)
|
|
|
1167 void set_last_Java_frame(Register last_java_sp,
|
|
|
1168 Register last_java_fp,
|
|
|
1169 address last_java_pc);
|
|
|
1170 void reset_last_Java_frame(bool clear_fp, bool clear_pc);
|
|
|
1171
|
|
|
1172 // Stores
|
|
|
1173 void store_check(Register obj); // store check for
|
|
|
1174 // obj - register is
|
|
|
1175 // destroyed
|
|
|
1176 // afterwards
|
|
|
1177 void store_check(Register obj, Address dst); // same as above, dst
|
|
|
1178 // is exact store
|
|
|
1179 // location (reg. is
|
|
|
1180 // destroyed)
|
|
|
1181
|
|
|
1182 // split store_check(Register obj) to enhance instruction interleaving
|
|
|
1183 void store_check_part_1(Register obj);
|
|
|
1184 void store_check_part_2(Register obj);
|
|
|
1185
|
|
|
1186 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
|
|
|
1187 void c2bool(Register x);
|
|
|
1188
|
|
|
1189 // Int division/reminder for Java
|
|
|
1190 // (as idivl, but checks for special case as described in JVM spec.)
|
|
|
1191 // returns idivl instruction offset for implicit exception handling
|
|
|
1192 int corrected_idivl(Register reg);
|
|
|
1193 // Long division/reminder for Java
|
|
|
1194 // (as idivq, but checks for special case as described in JVM spec.)
|
|
|
1195 // returns idivq instruction offset for implicit exception handling
|
|
|
1196 int corrected_idivq(Register reg);
|
|
|
1197
|
|
|
1198 // Push and pop integer/fpu/cpu state
|
|
|
1199 void push_IU_state();
|
|
|
1200 void pop_IU_state();
|
|
|
1201
|
|
|
1202 void push_FPU_state();
|
|
|
1203 void pop_FPU_state();
|
|
|
1204
|
|
|
1205 void push_CPU_state();
|
|
|
1206 void pop_CPU_state();
|
|
|
1207
|
|
|
1208 // Sign extension
|
|
|
1209 void sign_extend_short(Register reg);
|
|
|
1210 void sign_extend_byte(Register reg);
|
|
|
1211
|
|
|
1212 // Division by power of 2, rounding towards 0
|
|
|
1213 void division_with_shift(Register reg, int shift_value);
|
|
|
1214
|
|
|
1215 // Round up to a power of two
|
|
|
1216 void round_to_l(Register reg, int modulus);
|
|
|
1217 void round_to_q(Register reg, int modulus);
|
|
|
1218
|
|
|
1219 // allocation
|
|
|
1220 void eden_allocate(
|
|
|
1221 Register obj, // result: pointer to object after
|
|
|
1222 // successful allocation
|
|
|
1223 Register var_size_in_bytes, // object size in bytes if unknown at
|
|
|
1224 // compile time; invalid otherwise
|
|
|
1225 int con_size_in_bytes, // object size in bytes if known at
|
|
|
1226 // compile time
|
|
|
1227 Register t1, // temp register
|
|
|
1228 Label& slow_case // continuation point if fast
|
|
|
1229 // allocation fails
|
|
|
1230 );
|
|
|
1231 void tlab_allocate(
|
|
|
1232 Register obj, // result: pointer to object after
|
|
|
1233 // successful allocation
|
|
|
1234 Register var_size_in_bytes, // object size in bytes if unknown at
|
|
|
1235 // compile time; invalid otherwise
|
|
|
1236 int con_size_in_bytes, // object size in bytes if known at
|
|
|
1237 // compile time
|
|
|
1238 Register t1, // temp register
|
|
|
1239 Register t2, // temp register
|
|
|
1240 Label& slow_case // continuation point if fast
|
|
|
1241 // allocation fails
|
|
|
1242 );
|
|
|
1243 void tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case);
|
|
|
1244
|
|
|
1245 //----
|
|
|
1246
|
|
|
1247 // Debugging
|
|
|
1248
|
|
|
1249 // only if +VerifyOops
|
|
|
1250 void verify_oop(Register reg, const char* s = "broken oop");
|
|
|
1251 void verify_oop_addr(Address addr, const char * s = "broken oop addr");
|
|
|
1252
|
|
|
1253 // only if +VerifyFPU
|
|
|
1254 void verify_FPU(int stack_depth, const char* s = "illegal FPU state") {}
|
|
|
1255
|
|
|
1256 // prints msg, dumps registers and stops execution
|
|
|
1257 void stop(const char* msg);
|
|
|
1258
|
|
|
1259 // prints message and continues
|
|
|
1260 void warn(const char* msg);
|
|
|
1261
|
|
|
1262 static void debug(char* msg, int64_t pc, int64_t regs[]);
|
|
|
1263
|
|
|
1264 void os_breakpoint();
|
|
|
1265
|
|
|
1266 void untested()
|
|
|
1267 {
|
|
|
1268 stop("untested");
|
|
|
1269 }
|
|
|
1270
|
|
|
1271 void unimplemented(const char* what = "")
|
|
|
1272 {
|
|
|
1273 char* b = new char[1024];
|
|
|
1274 sprintf(b, "unimplemented: %s", what);
|
|
|
1275 stop(b);
|
|
|
1276 }
|
|
|
1277
|
|
|
1278 void should_not_reach_here()
|
|
|
1279 {
|
|
|
1280 stop("should not reach here");
|
|
|
1281 }
|
|
|
1282
|
|
|
1283 // Stack overflow checking
|
|
|
1284 void bang_stack_with_offset(int offset)
|
|
|
1285 {
|
|
|
1286 // stack grows down, caller passes positive offset
|
|
|
1287 assert(offset > 0, "must bang with negative offset");
|
|
|
1288 movl(Address(rsp, (-offset)), rax);
|
|
|
1289 }
|
|
|
1290
|
|
|
1291 // Writes to stack successive pages until offset reached to check for
|
|
|
1292 // stack overflow + shadow pages. Also, clobbers tmp
|
|
|
1293 void bang_stack_size(Register offset, Register tmp);
|
|
|
1294
|
|
|
1295 // Support for serializing memory accesses between threads.
|
|
|
1296 void serialize_memory(Register thread, Register tmp);
|
|
|
1297
|
|
|
1298 void verify_tlab();
|
|
|
1299
|
|
|
1300 // Biased locking support
|
|
|
1301 // lock_reg and obj_reg must be loaded up with the appropriate values.
|
|
|
1302 // swap_reg must be rax and is killed.
|
|
|
1303 // tmp_reg must be supplied and is killed.
|
|
|
1304 // If swap_reg_contains_mark is true then the code assumes that the
|
|
|
1305 // mark word of the object has already been loaded into swap_reg.
|
|
|
1306 // Optional slow case is for implementations (interpreter and C1) which branch to
|
|
|
1307 // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
|
|
|
1308 // Returns offset of first potentially-faulting instruction for null
|
|
|
1309 // check info (currently consumed only by C1). If
|
|
|
1310 // swap_reg_contains_mark is true then returns -1 as it is assumed
|
|
|
1311 // the calling code has already passed any potential faults.
|
|
|
1312 int biased_locking_enter(Register lock_reg, Register obj_reg, Register swap_reg, Register tmp_reg,
|
|
|
1313 bool swap_reg_contains_mark,
|
|
|
1314 Label& done, Label* slow_case = NULL,
|
|
|
1315 BiasedLockingCounters* counters = NULL);
|
|
|
1316 void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
|
|
|
1317
|
|
|
1318 Condition negate_condition(Condition cond);
|
|
|
1319
|
|
|
1320 // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit
|
|
|
1321 // operands. In general the names are modified to avoid hiding the instruction in Assembler
|
|
|
1322 // so that we don't need to implement all the varieties in the Assembler with trivial wrappers
|
|
|
1323 // here in MacroAssembler. The major exception to this rule is call
|
|
|
1324
|
|
|
1325 // Arithmetics
|
|
|
1326
|
|
|
1327 void cmp8(AddressLiteral src1, int8_t imm32);
|
|
|
1328
|
|
|
1329 void cmp32(AddressLiteral src1, int32_t src2);
|
|
|
1330 // compare reg - mem, or reg - &mem
|
|
|
1331 void cmp32(Register src1, AddressLiteral src2);
|
|
|
1332
|
|
|
1333 void cmp32(Register src1, Address src2);
|
|
|
1334
|
|
|
1335 #ifndef _LP64
|
|
|
1336 void cmpoop(Address dst, jobject obj);
|
|
|
1337 void cmpoop(Register dst, jobject obj);
|
|
|
1338 #endif // _LP64
|
|
|
1339
|
|
|
1340 // NOTE src2 must be the lval. This is NOT an mem-mem compare
|
|
|
1341 void cmpptr(Address src1, AddressLiteral src2);
|
|
|
1342
|
|
|
1343 void cmpptr(Register src1, AddressLiteral src);
|
|
|
1344
|
|
|
1345 // will be cmpreg(?)
|
|
|
1346 void cmp64(Register src1, AddressLiteral src);
|
|
|
1347
|
|
|
1348 void cmpxchgptr(Register reg, Address adr);
|
|
|
1349 void cmpxchgptr(Register reg, AddressLiteral adr);
|
|
|
1350
|
|
|
1351 // Helper functions for statistics gathering.
|
|
|
1352 // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes.
|
|
|
1353 void cond_inc32(Condition cond, AddressLiteral counter_addr);
|
|
|
1354 // Unconditional atomic increment.
|
|
|
1355 void atomic_incl(AddressLiteral counter_addr);
|
|
|
1356
|
|
|
1357
|
|
|
1358 void lea(Register dst, AddressLiteral src);
|
|
|
1359 void lea(Register dst, Address src);
|
|
|
1360
|
|
|
1361
|
|
|
1362 // Calls
|
|
|
1363 void call(Label& L, relocInfo::relocType rtype);
|
|
|
1364 void call(Register entry);
|
|
|
1365 void call(AddressLiteral entry);
|
|
|
1366
|
|
|
1367 // Jumps
|
|
|
1368
|
|
|
1369 // 32bit can do a case table jump in one instruction but we no longer allow the base
|
|
|
1370 // to be installed in the Address class
|
|
|
1371 void jump(ArrayAddress entry);
|
|
|
1372
|
|
|
1373 void jump(AddressLiteral entry);
|
|
|
1374 void jump_cc(Condition cc, AddressLiteral dst);
|
|
|
1375
|
|
|
1376 // Floating
|
|
|
1377
|
|
|
1378 void ldmxcsr(Address src) { Assembler::ldmxcsr(src); }
|
|
|
1379 void ldmxcsr(AddressLiteral src);
|
|
|
1380
|
|
|
1381 private:
|
|
|
1382 // these are private because users should be doing movflt/movdbl
|
|
|
1383
|
|
|
1384 void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); }
|
|
|
1385 void movss(Address dst, XMMRegister src) { Assembler::movss(dst, src); }
|
|
|
1386 void movss(XMMRegister dst, Address src) { Assembler::movss(dst, src); }
|
|
|
1387 void movss(XMMRegister dst, AddressLiteral src);
|
|
|
1388
|
|
|
1389 void movlpd(XMMRegister dst, Address src) {Assembler::movlpd(dst, src); }
|
|
|
1390 void movlpd(XMMRegister dst, AddressLiteral src);
|
|
|
1391
|
|
|
1392 public:
|
|
|
1393
|
|
|
1394
|
|
|
1395 void xorpd(XMMRegister dst, XMMRegister src) {Assembler::xorpd(dst, src); }
|
|
|
1396 void xorpd(XMMRegister dst, Address src) {Assembler::xorpd(dst, src); }
|
|
|
1397 void xorpd(XMMRegister dst, AddressLiteral src);
|
|
|
1398
|
|
|
1399 void xorps(XMMRegister dst, XMMRegister src) {Assembler::xorps(dst, src); }
|
|
|
1400 void xorps(XMMRegister dst, Address src) {Assembler::xorps(dst, src); }
|
|
|
1401 void xorps(XMMRegister dst, AddressLiteral src);
|
|
|
1402
|
|
|
1403
|
|
|
1404 // Data
|
|
|
1405
|
|
|
1406 void movoop(Register dst, jobject obj);
|
|
|
1407 void movoop(Address dst, jobject obj);
|
|
|
1408
|
|
|
1409 void movptr(ArrayAddress dst, Register src);
|
|
|
1410 void movptr(Register dst, AddressLiteral src);
|
|
|
1411
|
|
|
1412 void movptr(Register dst, intptr_t src);
|
|
|
1413 void movptr(Address dst, intptr_t src);
|
|
|
1414
|
|
|
1415 void movptr(Register dst, ArrayAddress src);
|
|
|
1416
|
|
|
1417 // to avoid hiding movl
|
|
|
1418 void mov32(AddressLiteral dst, Register src);
|
|
|
1419 void mov32(Register dst, AddressLiteral src);
|
|
|
1420
|
|
|
1421 void pushoop(jobject obj);
|
|
|
1422
|
|
|
1423 // Can push value or effective address
|
|
|
1424 void pushptr(AddressLiteral src);
|
|
|
1425
|
|
|
1426 };
|
|
|
1427
|
|
|
1428 /**
|
|
|
1429 * class SkipIfEqual:
|
|
|
1430 *
|
|
|
1431 * Instantiating this class will result in assembly code being output that will
|
|
|
1432 * jump around any code emitted between the creation of the instance and it's
|
|
|
1433 * automatic destruction at the end of a scope block, depending on the value of
|
|
|
1434 * the flag passed to the constructor, which will be checked at run-time.
|
|
|
1435 */
|
|
|
1436 class SkipIfEqual {
|
|
|
1437 private:
|
|
|
1438 MacroAssembler* _masm;
|
|
|
1439 Label _label;
|
|
|
1440
|
|
|
1441 public:
|
|
|
1442 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
|
|
|
1443 ~SkipIfEqual();
|
|
|
1444 };
|
|
|
1445
|
|
|
1446
|
|
|
1447 #ifdef ASSERT
|
|
|
1448 inline bool AbstractAssembler::pd_check_instruction_mark() { return true; }
|
|
|
1449 #endif
|
