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annotate graal/com.oracle.max.graal.lir/src/com/oracle/graal/lir/LIRVerifier.java @ 5060:4ed4295ce15f

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Update import statements.
author Thomas Wuerthinger <thomas.wuerthinger@oracle.com>
date Thu, 08 Mar 2012 19:11:12 +0100
parents ed559a528128
children
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1 /*
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2 * Copyright (c) 2009, 2012, Oracle and/or its affiliates. All rights reserved.
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3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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4 *
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5 * This code is free software; you can redistribute it and/or modify it
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6 * under the terms of the GNU General Public License version 2 only, as
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7 * published by the Free Software Foundation.
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8 *
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9 * This code is distributed in the hope that it will be useful, but WITHOUT
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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12 * version 2 for more details (a copy is included in the LICENSE file that
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13 * accompanied this code).
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14 *
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15 * You should have received a copy of the GNU General Public License version
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16 * 2 along with this work; if not, write to the Free Software Foundation,
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17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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18 *
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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20 * or visit www.oracle.com if you need additional information or have any
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21 * questions.
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22 */
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23 package com.oracle.graal.lir;
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24
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25 import static com.oracle.max.cri.ci.CiValueUtil.*;
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26 import static com.oracle.graal.lir.ValueUtil.*;
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27
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28 import java.util.*;
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29
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30 import com.oracle.max.cri.ci.*;
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31 import com.oracle.max.criutils.*;
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32 import com.oracle.graal.graph.*;
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33 import com.oracle.graal.lir.LIRInstruction.*;
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34 import com.oracle.graal.lir.cfg.*;
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35
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36 public final class LIRVerifier {
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37 private final LIR lir;
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38 private final FrameMap frameMap;
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39
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40 private final boolean beforeRegisterAllocation;
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41
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42 private final BitSet[] blockLiveOut;
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43 private final Object[] variableDefinitions;
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44
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45 private BitSet liveOutFor(Block block) {
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46 return blockLiveOut[block.getId()];
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47 }
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48 private void setLiveOutFor(Block block, BitSet liveOut) {
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49 blockLiveOut[block.getId()] = liveOut;
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50 }
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51
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52 private int maxRegisterNum() {
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53 return frameMap.target.arch.registers.length;
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54 }
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55
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56 private boolean isAllocatableRegister(CiValue value) {
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57 return isRegister(value) && frameMap.registerConfig.getAttributesMap()[asRegister(value).number].isAllocatable;
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58 }
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59
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60 public static boolean verify(final LIRInstruction op) {
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61 ValueProcedure allowedProc = new ValueProcedure() { @Override public CiValue doValue(CiValue value, OperandMode mode, EnumSet<OperandFlag> flags) { return allowed(op, value, mode, flags); } };
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62
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63 op.forEachInput(allowedProc);
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64 op.forEachAlive(allowedProc);
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65 op.forEachState(allowedProc);
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66 op.forEachTemp(allowedProc);
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67 op.forEachOutput(allowedProc);
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68
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69 op.verify();
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70 return true;
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71 }
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72
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73 public static boolean verify(boolean beforeRegisterAllocation, LIR lir, FrameMap frameMap) {
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74 LIRVerifier verifier = new LIRVerifier(beforeRegisterAllocation, lir, frameMap);
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75 verifier.verify();
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76 return true;
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77 }
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78
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79
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80 private LIRVerifier(boolean beforeRegisterAllocation, LIR lir, FrameMap frameMap) {
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81 this.beforeRegisterAllocation = beforeRegisterAllocation;
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82 this.lir = lir;
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83 this.frameMap = frameMap;
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84 this.blockLiveOut = new BitSet[lir.linearScanOrder().size()];
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85 this.variableDefinitions = new Object[lir.numVariables()];
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86 }
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87
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88 private BitSet curVariablesLive;
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89 private CiValue[] curRegistersLive;
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90
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91 private Block curBlock;
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92 private Object curInstruction;
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93 private BitSet curRegistersDefined;
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94
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95 private void verify() {
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96 ValueProcedure useProc = new ValueProcedure() { @Override public CiValue doValue(CiValue value, OperandMode mode, EnumSet<OperandFlag> flags) { return use(value, mode, flags); } };
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97 ValueProcedure defProc = new ValueProcedure() { @Override public CiValue doValue(CiValue value, OperandMode mode, EnumSet<OperandFlag> flags) { return def(value, mode, flags); } };
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98
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99 curRegistersDefined = new BitSet();
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100 for (Block block : lir.linearScanOrder()) {
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101 curBlock = block;
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102 curVariablesLive = new BitSet();
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103 curRegistersLive = new CiValue[maxRegisterNum()];
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104
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105 if (block.getDominator() != null) {
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106 curVariablesLive.or(liveOutFor(block.getDominator()));
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107 }
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108
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109 assert block.lir.get(0) instanceof StandardOp.LabelOp : "block must start with label";
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110 if (block.numberOfPreds() > 1) {
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111 assert block.lir.get(0) instanceof StandardOp.PhiLabelOp : "phi mapping required for multiple predecessors";
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112 CiValue[] phiDefinitions = ((StandardOp.PhiLabelOp) block.lir.get(0)).getPhiDefinitions();
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113 if (!beforeRegisterAllocation) {
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114 assert phiDefinitions.length == 0;
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115 }
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116 for (Block pred : block.getPredecessors()) {
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117 assert pred.numberOfSux() == 1;
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118 LIRInstruction last = pred.lir.get(pred.lir.size() - 1);
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119 assert last instanceof StandardOp.PhiJumpOp : "phi mapping required for multiple successors";
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120 CiValue[] phiUses = ((StandardOp.PhiJumpOp) last).getPhiInputs();
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121 if (!beforeRegisterAllocation) {
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122 assert phiUses.length == 0;
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123 }
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124 }
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125 }
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126
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127 if (block.numberOfSux() > 0) {
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128 LIRInstruction last = block.lir.get(block.lir.size() - 1);
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129 assert last instanceof StandardOp.JumpOp || last instanceof LIRXirInstruction : "block with successor must end with unconditional jump";
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Christian Wimmer <Christian.Wimmer@Oracle.com>
parents: 4317
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130 }
df5547057954 Remove LIROpcode and use non-anonymous subclasses of LIRInstruction
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parents: 4317
diff changeset
131
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57cb8ec5f6bb Restructure block and control flow graph data structures
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parents: 4323
diff changeset
132 for (LIRInstruction op : block.lir) {
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133 curInstruction = op;
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parents:
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134
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parents:
diff changeset
135 op.forEachInput(useProc);
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parents:
diff changeset
136 if (op.hasCall()) {
4265
4643ccd37dac * removed CiStatistics
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parents: 4245
diff changeset
137 for (CiRegister register : frameMap.registerConfig.getCallerSaveRegisters()) {
4169
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138 curRegistersLive[register.number] = null;
f5328dda9714 Initial commit of SSA-based spill-all register assignment
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parents:
diff changeset
139 }
f5328dda9714 Initial commit of SSA-based spill-all register assignment
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parents:
diff changeset
140 }
4290
21400bafb3ff Enforce that one fixed register cannot be a temporary operand multiple times with different kinds
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diff changeset
141 curRegistersDefined.clear();
4169
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142 op.forEachAlive(useProc);
f5328dda9714 Initial commit of SSA-based spill-all register assignment
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parents:
diff changeset
143 op.forEachState(useProc);
4245
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diff changeset
144 op.forEachTemp(defProc);
75c620f90ab9 Support stack-operands and register hints in new register allocator API
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diff changeset
145 op.forEachOutput(defProc);
4169
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parents:
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146
f5328dda9714 Initial commit of SSA-based spill-all register assignment
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parents:
diff changeset
147 curInstruction = null;
f5328dda9714 Initial commit of SSA-based spill-all register assignment
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parents:
diff changeset
148 }
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parents:
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149
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parents:
diff changeset
150 setLiveOutFor(block, curVariablesLive);
f5328dda9714 Initial commit of SSA-based spill-all register assignment
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parents:
diff changeset
151 }
f5328dda9714 Initial commit of SSA-based spill-all register assignment
Christian Wimmer <Christian.Wimmer@Oracle.com>
parents:
diff changeset
152 }
f5328dda9714 Initial commit of SSA-based spill-all register assignment
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parents:
diff changeset
153
4245
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diff changeset
154 private CiValue use(CiValue value, OperandMode mode, EnumSet<OperandFlag> flags) {
75c620f90ab9 Support stack-operands and register hints in new register allocator API
Christian Wimmer <Christian.Wimmer@Oracle.com>
parents: 4212
diff changeset
155 allowed(curInstruction, value, mode, flags);
75c620f90ab9 Support stack-operands and register hints in new register allocator API
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parents: 4212
diff changeset
156
4317
ef004bae30ae Improvement to LIR Verification
Christian Wimmer <Christian.Wimmer@Oracle.com>
parents: 4290
diff changeset
157 if (isVariable(value)) {
ef004bae30ae Improvement to LIR Verification
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parents: 4290
diff changeset
158 assert beforeRegisterAllocation;
ef004bae30ae Improvement to LIR Verification
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parents: 4290
diff changeset
159
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parents:
diff changeset
160 int variableIdx = asVariable(value).index;
f5328dda9714 Initial commit of SSA-based spill-all register assignment
Christian Wimmer <Christian.Wimmer@Oracle.com>
parents:
diff changeset
161 if (!curVariablesLive.get(variableIdx)) {
f5328dda9714 Initial commit of SSA-based spill-all register assignment
Christian Wimmer <Christian.Wimmer@Oracle.com>
parents:
diff changeset
162 TTY.println("block %s instruction %s", curBlock, curInstruction);
f5328dda9714 Initial commit of SSA-based spill-all register assignment
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parents:
diff changeset
163 TTY.println("live variables: %s", curVariablesLive);
f5328dda9714 Initial commit of SSA-based spill-all register assignment
Christian Wimmer <Christian.Wimmer@Oracle.com>
parents:
diff changeset
164 if (variableDefinitions[variableIdx] != null) {
f5328dda9714 Initial commit of SSA-based spill-all register assignment
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parents:
diff changeset
165 TTY.println("definition of %s: %s", value, variableDefinitions[variableIdx]);
f5328dda9714 Initial commit of SSA-based spill-all register assignment
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parents:
diff changeset
166 }
f5328dda9714 Initial commit of SSA-based spill-all register assignment
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parents:
diff changeset
167 TTY.println("ERROR: Use of variable %s that is not defined in dominator", value);
4524
dcc8f5c6f394 Refactorings to prepare for LIR project splitting
Christian Wimmer <Christian.Wimmer@Oracle.com>
parents: 4522
diff changeset
168 throw GraalInternalError.shouldNotReachHere();
4169
f5328dda9714 Initial commit of SSA-based spill-all register assignment
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parents:
diff changeset
169 }
f5328dda9714 Initial commit of SSA-based spill-all register assignment
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parents:
diff changeset
170
4317
ef004bae30ae Improvement to LIR Verification
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parents: 4290
diff changeset
171 } else if (isAllocatableRegister(value)) {
4169
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parents:
diff changeset
172 int regNum = asRegister(value).number;
4317
ef004bae30ae Improvement to LIR Verification
Christian Wimmer <Christian.Wimmer@Oracle.com>
parents: 4290
diff changeset
173 if (mode == OperandMode.Alive) {
ef004bae30ae Improvement to LIR Verification
Christian Wimmer <Christian.Wimmer@Oracle.com>
parents: 4290
diff changeset
174 curRegistersDefined.set(regNum);
ef004bae30ae Improvement to LIR Verification
Christian Wimmer <Christian.Wimmer@Oracle.com>
parents: 4290
diff changeset
175 }
ef004bae30ae Improvement to LIR Verification
Christian Wimmer <Christian.Wimmer@Oracle.com>
parents: 4290
diff changeset
176
ef004bae30ae Improvement to LIR Verification
Christian Wimmer <Christian.Wimmer@Oracle.com>
parents: 4290
diff changeset
177 if (beforeRegisterAllocation && curRegistersLive[regNum] != value) {
4169
f5328dda9714 Initial commit of SSA-based spill-all register assignment
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parents:
diff changeset
178 TTY.println("block %s instruction %s", curBlock, curInstruction);
f5328dda9714 Initial commit of SSA-based spill-all register assignment
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parents:
diff changeset
179 TTY.println("live registers: %s", Arrays.toString(curRegistersLive));
f5328dda9714 Initial commit of SSA-based spill-all register assignment
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parents:
diff changeset
180 TTY.println("ERROR: Use of fixed register %s that is not defined in this block", value);
4524
dcc8f5c6f394 Refactorings to prepare for LIR project splitting
Christian Wimmer <Christian.Wimmer@Oracle.com>
parents: 4522
diff changeset
181 throw GraalInternalError.shouldNotReachHere();
4169
f5328dda9714 Initial commit of SSA-based spill-all register assignment
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parents:
diff changeset
182 }
f5328dda9714 Initial commit of SSA-based spill-all register assignment
Christian Wimmer <Christian.Wimmer@Oracle.com>
parents:
diff changeset
183 }
f5328dda9714 Initial commit of SSA-based spill-all register assignment
Christian Wimmer <Christian.Wimmer@Oracle.com>
parents:
diff changeset
184 return value;
f5328dda9714 Initial commit of SSA-based spill-all register assignment
Christian Wimmer <Christian.Wimmer@Oracle.com>
parents:
diff changeset
185 }
f5328dda9714 Initial commit of SSA-based spill-all register assignment
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parents:
diff changeset
186
4245
75c620f90ab9 Support stack-operands and register hints in new register allocator API
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parents: 4212
diff changeset
187 private CiValue def(CiValue value, OperandMode mode, EnumSet<OperandFlag> flags) {
75c620f90ab9 Support stack-operands and register hints in new register allocator API
Christian Wimmer <Christian.Wimmer@Oracle.com>
parents: 4212
diff changeset
188 allowed(curInstruction, value, mode, flags);
75c620f90ab9 Support stack-operands and register hints in new register allocator API
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parents: 4212
diff changeset
189
4317
ef004bae30ae Improvement to LIR Verification
Christian Wimmer <Christian.Wimmer@Oracle.com>
parents: 4290
diff changeset
190 if (isVariable(value)) {
ef004bae30ae Improvement to LIR Verification
Christian Wimmer <Christian.Wimmer@Oracle.com>
parents: 4290
diff changeset
191 assert beforeRegisterAllocation;
ef004bae30ae Improvement to LIR Verification
Christian Wimmer <Christian.Wimmer@Oracle.com>
parents: 4290
diff changeset
192
4169
f5328dda9714 Initial commit of SSA-based spill-all register assignment
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parents:
diff changeset
193 int variableIdx = asVariable(value).index;
f5328dda9714 Initial commit of SSA-based spill-all register assignment
Christian Wimmer <Christian.Wimmer@Oracle.com>
parents:
diff changeset
194 if (variableDefinitions[variableIdx] != null) {
f5328dda9714 Initial commit of SSA-based spill-all register assignment
Christian Wimmer <Christian.Wimmer@Oracle.com>
parents:
diff changeset
195 TTY.println("block %s instruction %s", curBlock, curInstruction);
f5328dda9714 Initial commit of SSA-based spill-all register assignment
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parents:
diff changeset
196 TTY.println("live variables: %s", curVariablesLive);
f5328dda9714 Initial commit of SSA-based spill-all register assignment
Christian Wimmer <Christian.Wimmer@Oracle.com>
parents:
diff changeset
197 TTY.println("definition of %s: %s", value, variableDefinitions[variableIdx]);
f5328dda9714 Initial commit of SSA-based spill-all register assignment
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parents:
diff changeset
198 TTY.println("ERROR: Variable %s defined multiple times", value);
4524
dcc8f5c6f394 Refactorings to prepare for LIR project splitting
Christian Wimmer <Christian.Wimmer@Oracle.com>
parents: 4522
diff changeset
199 throw GraalInternalError.shouldNotReachHere();
4169
f5328dda9714 Initial commit of SSA-based spill-all register assignment
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parents:
diff changeset
200 }
f5328dda9714 Initial commit of SSA-based spill-all register assignment
Christian Wimmer <Christian.Wimmer@Oracle.com>
parents:
diff changeset
201 assert curInstruction != null;
f5328dda9714 Initial commit of SSA-based spill-all register assignment
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parents:
diff changeset
202 variableDefinitions[variableIdx] = curInstruction;
f5328dda9714 Initial commit of SSA-based spill-all register assignment
Christian Wimmer <Christian.Wimmer@Oracle.com>
parents:
diff changeset
203 assert !curVariablesLive.get(variableIdx);
4245
75c620f90ab9 Support stack-operands and register hints in new register allocator API
Christian Wimmer <Christian.Wimmer@Oracle.com>
parents: 4212
diff changeset
204 if (mode == OperandMode.Output) {
4169
f5328dda9714 Initial commit of SSA-based spill-all register assignment
Christian Wimmer <Christian.Wimmer@Oracle.com>
parents:
diff changeset
205 curVariablesLive.set(variableIdx);
f5328dda9714 Initial commit of SSA-based spill-all register assignment
Christian Wimmer <Christian.Wimmer@Oracle.com>
parents:
diff changeset
206 }
f5328dda9714 Initial commit of SSA-based spill-all register assignment
Christian Wimmer <Christian.Wimmer@Oracle.com>
parents:
diff changeset
207
4317
ef004bae30ae Improvement to LIR Verification
Christian Wimmer <Christian.Wimmer@Oracle.com>
parents: 4290
diff changeset
208 } else if (isAllocatableRegister(value)) {
4169
f5328dda9714 Initial commit of SSA-based spill-all register assignment
Christian Wimmer <Christian.Wimmer@Oracle.com>
parents:
diff changeset
209 int regNum = asRegister(value).number;
4290
21400bafb3ff Enforce that one fixed register cannot be a temporary operand multiple times with different kinds
Christian Wimmer <Christian.Wimmer@Oracle.com>
parents: 4265
diff changeset
210 if (curRegistersDefined.get(regNum)) {
21400bafb3ff Enforce that one fixed register cannot be a temporary operand multiple times with different kinds
Christian Wimmer <Christian.Wimmer@Oracle.com>
parents: 4265
diff changeset
211 TTY.println("block %s instruction %s", curBlock, curInstruction);
21400bafb3ff Enforce that one fixed register cannot be a temporary operand multiple times with different kinds
Christian Wimmer <Christian.Wimmer@Oracle.com>
parents: 4265
diff changeset
212 TTY.println("ERROR: Same register defined twice in the same instruction: %s", value);
4524
dcc8f5c6f394 Refactorings to prepare for LIR project splitting
Christian Wimmer <Christian.Wimmer@Oracle.com>
parents: 4522
diff changeset
213 throw GraalInternalError.shouldNotReachHere();
4290
21400bafb3ff Enforce that one fixed register cannot be a temporary operand multiple times with different kinds
Christian Wimmer <Christian.Wimmer@Oracle.com>
parents: 4265
diff changeset
214 }
21400bafb3ff Enforce that one fixed register cannot be a temporary operand multiple times with different kinds
Christian Wimmer <Christian.Wimmer@Oracle.com>
parents: 4265
diff changeset
215 curRegistersDefined.set(regNum);
21400bafb3ff Enforce that one fixed register cannot be a temporary operand multiple times with different kinds
Christian Wimmer <Christian.Wimmer@Oracle.com>
parents: 4265
diff changeset
216
21400bafb3ff Enforce that one fixed register cannot be a temporary operand multiple times with different kinds
Christian Wimmer <Christian.Wimmer@Oracle.com>
parents: 4265
diff changeset
217 if (beforeRegisterAllocation) {
21400bafb3ff Enforce that one fixed register cannot be a temporary operand multiple times with different kinds
Christian Wimmer <Christian.Wimmer@Oracle.com>
parents: 4265
diff changeset
218 if (mode == OperandMode.Output) {
21400bafb3ff Enforce that one fixed register cannot be a temporary operand multiple times with different kinds
Christian Wimmer <Christian.Wimmer@Oracle.com>
parents: 4265
diff changeset
219 curRegistersLive[regNum] = value;
21400bafb3ff Enforce that one fixed register cannot be a temporary operand multiple times with different kinds
Christian Wimmer <Christian.Wimmer@Oracle.com>
parents: 4265
diff changeset
220 } else {
21400bafb3ff Enforce that one fixed register cannot be a temporary operand multiple times with different kinds
Christian Wimmer <Christian.Wimmer@Oracle.com>
parents: 4265
diff changeset
221 curRegistersLive[regNum] = null;
21400bafb3ff Enforce that one fixed register cannot be a temporary operand multiple times with different kinds
Christian Wimmer <Christian.Wimmer@Oracle.com>
parents: 4265
diff changeset
222 }
4169
f5328dda9714 Initial commit of SSA-based spill-all register assignment
Christian Wimmer <Christian.Wimmer@Oracle.com>
parents:
diff changeset
223 }
f5328dda9714 Initial commit of SSA-based spill-all register assignment
Christian Wimmer <Christian.Wimmer@Oracle.com>
parents:
diff changeset
224 }
f5328dda9714 Initial commit of SSA-based spill-all register assignment
Christian Wimmer <Christian.Wimmer@Oracle.com>
parents:
diff changeset
225 return value;
f5328dda9714 Initial commit of SSA-based spill-all register assignment
Christian Wimmer <Christian.Wimmer@Oracle.com>
parents:
diff changeset
226 }
4245
75c620f90ab9 Support stack-operands and register hints in new register allocator API
Christian Wimmer <Christian.Wimmer@Oracle.com>
parents: 4212
diff changeset
227
75c620f90ab9 Support stack-operands and register hints in new register allocator API
Christian Wimmer <Christian.Wimmer@Oracle.com>
parents: 4212
diff changeset
228 private static CiValue allowed(Object op, CiValue value, OperandMode mode, EnumSet<OperandFlag> flags) {
75c620f90ab9 Support stack-operands and register hints in new register allocator API
Christian Wimmer <Christian.Wimmer@Oracle.com>
parents: 4212
diff changeset
229 if ((isVariable(value) && flags.contains(OperandFlag.Register)) ||
75c620f90ab9 Support stack-operands and register hints in new register allocator API
Christian Wimmer <Christian.Wimmer@Oracle.com>
parents: 4212
diff changeset
230 (isRegister(value) && flags.contains(OperandFlag.Register)) ||
75c620f90ab9 Support stack-operands and register hints in new register allocator API
Christian Wimmer <Christian.Wimmer@Oracle.com>
parents: 4212
diff changeset
231 (isStackSlot(value) && flags.contains(OperandFlag.Stack)) ||
75c620f90ab9 Support stack-operands and register hints in new register allocator API
Christian Wimmer <Christian.Wimmer@Oracle.com>
parents: 4212
diff changeset
232 (isConstant(value) && flags.contains(OperandFlag.Constant) && mode != OperandMode.Output) ||
75c620f90ab9 Support stack-operands and register hints in new register allocator API
Christian Wimmer <Christian.Wimmer@Oracle.com>
parents: 4212
diff changeset
233 (isIllegal(value) && flags.contains(OperandFlag.Illegal))) {
75c620f90ab9 Support stack-operands and register hints in new register allocator API
Christian Wimmer <Christian.Wimmer@Oracle.com>
parents: 4212
diff changeset
234 return value;
75c620f90ab9 Support stack-operands and register hints in new register allocator API
Christian Wimmer <Christian.Wimmer@Oracle.com>
parents: 4212
diff changeset
235 }
75c620f90ab9 Support stack-operands and register hints in new register allocator API
Christian Wimmer <Christian.Wimmer@Oracle.com>
parents: 4212
diff changeset
236 TTY.println("instruction %s", op);
75c620f90ab9 Support stack-operands and register hints in new register allocator API
Christian Wimmer <Christian.Wimmer@Oracle.com>
parents: 4212
diff changeset
237 TTY.println("mode: %s flags: %s", mode, flags);
75c620f90ab9 Support stack-operands and register hints in new register allocator API
Christian Wimmer <Christian.Wimmer@Oracle.com>
parents: 4212
diff changeset
238 TTY.println("Unexpected value: %s %s", value.getClass().getSimpleName(), value);
4524
dcc8f5c6f394 Refactorings to prepare for LIR project splitting
Christian Wimmer <Christian.Wimmer@Oracle.com>
parents: 4522
diff changeset
239 throw GraalInternalError.shouldNotReachHere();
4245
75c620f90ab9 Support stack-operands and register hints in new register allocator API
Christian Wimmer <Christian.Wimmer@Oracle.com>
parents: 4212
diff changeset
240 }
4169
f5328dda9714 Initial commit of SSA-based spill-all register assignment
Christian Wimmer <Christian.Wimmer@Oracle.com>
parents:
diff changeset
241 }