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annotate graal/com.oracle.graal.lir.amd64/src/com/oracle/graal/lir/amd64/AMD64ShiftOp.java @ 21673:5024c80224c7

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moved com.oracle.graal.[amd64|sparc] to com.oracle.jvmci.[amd64|sparc] (JBS:GRAAL-53)
author Doug Simon <doug.simon@oracle.com>
date Tue, 02 Jun 2015 22:11:52 +0200
parents 48c1ebd24120
children 6df25b1418be
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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19867
89c729e9e0a4 Refactoring of AMD64 code generation.
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1 /*
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2 * Copyright (c) 2015, 2015, Oracle and/or its affiliates. All rights reserved.
89c729e9e0a4 Refactoring of AMD64 code generation.
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3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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4 *
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5 * This code is free software; you can redistribute it and/or modify it
89c729e9e0a4 Refactoring of AMD64 code generation.
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6 * under the terms of the GNU General Public License version 2 only, as
89c729e9e0a4 Refactoring of AMD64 code generation.
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7 * published by the Free Software Foundation.
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8 *
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9 * This code is distributed in the hope that it will be useful, but WITHOUT
89c729e9e0a4 Refactoring of AMD64 code generation.
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
89c729e9e0a4 Refactoring of AMD64 code generation.
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
89c729e9e0a4 Refactoring of AMD64 code generation.
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12 * version 2 for more details (a copy is included in the LICENSE file that
89c729e9e0a4 Refactoring of AMD64 code generation.
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13 * accompanied this code).
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14 *
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15 * You should have received a copy of the GNU General Public License version
89c729e9e0a4 Refactoring of AMD64 code generation.
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16 * 2 along with this work; if not, write to the Free Software Foundation,
89c729e9e0a4 Refactoring of AMD64 code generation.
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17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
89c729e9e0a4 Refactoring of AMD64 code generation.
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18 *
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
89c729e9e0a4 Refactoring of AMD64 code generation.
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20 * or visit www.oracle.com if you need additional information or have any
89c729e9e0a4 Refactoring of AMD64 code generation.
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21 * questions.
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22 */
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23 package com.oracle.graal.lir.amd64;
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24
21673
5024c80224c7 moved com.oracle.graal.[amd64|sparc] to com.oracle.jvmci.[amd64|sparc] (JBS:GRAAL-53)
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25 import com.oracle.jvmci.amd64.*;
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48c1ebd24120 renamed com.oracle.graal.api[meta|code] modules to com.oracle.jvmci.[meta|code] (JBS:GRAAL-53)
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26 import com.oracle.jvmci.meta.AllocatableValue;
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5024c80224c7 moved com.oracle.graal.[amd64|sparc] to com.oracle.jvmci.[amd64|sparc] (JBS:GRAAL-53)
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27
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48c1ebd24120 renamed com.oracle.graal.api[meta|code] modules to com.oracle.jvmci.[meta|code] (JBS:GRAAL-53)
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28 import static com.oracle.jvmci.code.ValueUtil.*;
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29 import static com.oracle.graal.lir.LIRInstruction.OperandFlag.*;
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30
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31 import com.oracle.graal.asm.amd64.AMD64Assembler.AMD64MOp;
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32 import com.oracle.graal.asm.amd64.AMD64Assembler.OperandSize;
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93c50cefb9e8 moved GraalInternalError to com.oracle.jvmci.common and renamed it to JVMCIError (JBS:GRAAL-53)
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33 import com.oracle.graal.asm.amd64.*;
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34 import com.oracle.graal.lir.*;
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35 import com.oracle.graal.lir.asm.*;
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36
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46dde3e92715 Restructure AMD64 LIR classes.
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37 /**
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38 * AMD64 shift/rotate operation. This operation has a single operand for the first input and output.
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39 * The second input must be in the RCX register.
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40 */
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41 public class AMD64ShiftOp extends AMD64LIRInstruction {
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42 public static final LIRInstructionClass<AMD64ShiftOp> TYPE = LIRInstructionClass.create(AMD64ShiftOp.class);
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43
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44 @Opcode private final AMD64MOp opcode;
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45 private final OperandSize size;
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46
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47 @Def({REG, HINT}) protected AllocatableValue result;
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48 @Use({REG, STACK}) protected AllocatableValue x;
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49 @Alive({REG}) protected AllocatableValue y;
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50
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51 public AMD64ShiftOp(AMD64MOp opcode, OperandSize size, AllocatableValue result, AllocatableValue x, AllocatableValue y) {
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52 super(TYPE);
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53 this.opcode = opcode;
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54 this.size = size;
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55
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56 this.result = result;
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57 this.x = x;
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58 this.y = y;
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59 }
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60
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61 @Override
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62 public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
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63 AMD64Move.move(crb, masm, result, x);
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64 opcode.emit(masm, size, asRegister(result));
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65 }
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66
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67 @Override
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68 public void verify() {
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69 assert asRegister(y).equals(AMD64.rcx);
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70 }
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71 }