Mercurial > hg > truffle
annotate src/cpu/sparc/vm/assembler_sparc.inline.hpp @ 622:56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
Summary: minor assembler enhancements preparing for method handles
Reviewed-by: kvn
| author | jrose |
|---|---|
| date | Wed, 04 Mar 2009 09:58:39 -0800 |
| parents | a61af66fc99e |
| children | 9adddb8c0fc8 |
| rev | line source |
|---|---|
| 0 | 1 /* |
| 2 * Copyright 1997-2006 Sun Microsystems, Inc. All Rights Reserved. | |
| 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
| 4 * | |
| 5 * This code is free software; you can redistribute it and/or modify it | |
| 6 * under the terms of the GNU General Public License version 2 only, as | |
| 7 * published by the Free Software Foundation. | |
| 8 * | |
| 9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 * version 2 for more details (a copy is included in the LICENSE file that | |
| 13 * accompanied this code). | |
| 14 * | |
| 15 * You should have received a copy of the GNU General Public License version | |
| 16 * 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 * | |
| 19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
| 20 * CA 95054 USA or visit www.sun.com if you need additional information or | |
| 21 * have any questions. | |
| 22 * | |
| 23 */ | |
| 24 | |
| 25 inline void MacroAssembler::pd_patch_instruction(address branch, address target) { | |
| 26 jint& stub_inst = *(jint*) branch; | |
| 27 stub_inst = patched_branch(target - branch, stub_inst, 0); | |
| 28 } | |
| 29 | |
| 30 #ifndef PRODUCT | |
| 31 inline void MacroAssembler::pd_print_patched_instruction(address branch) { | |
| 32 jint stub_inst = *(jint*) branch; | |
| 33 print_instruction(stub_inst); | |
| 34 ::tty->print("%s", " (unresolved)"); | |
| 35 } | |
| 36 #endif // PRODUCT | |
| 37 | |
| 38 inline bool Address::is_simm13(int offset) { return Assembler::is_simm13(disp() + offset); } | |
| 39 | |
| 40 | |
| 41 // inlines for SPARC assembler -- dmu 5/97 | |
| 42 | |
| 43 inline void Assembler::check_delay() { | |
| 44 # ifdef CHECK_DELAY | |
| 45 guarantee( delay_state != at_delay_slot, "must say delayed() when filling delay slot"); | |
| 46 delay_state = no_delay; | |
| 47 # endif | |
| 48 } | |
| 49 | |
| 50 inline void Assembler::emit_long(int x) { | |
| 51 check_delay(); | |
| 52 AbstractAssembler::emit_long(x); | |
| 53 } | |
| 54 | |
| 55 inline void Assembler::emit_data(int x, relocInfo::relocType rtype) { | |
| 56 relocate(rtype); | |
| 57 emit_long(x); | |
| 58 } | |
| 59 | |
| 60 inline void Assembler::emit_data(int x, RelocationHolder const& rspec) { | |
| 61 relocate(rspec); | |
| 62 emit_long(x); | |
| 63 } | |
| 64 | |
| 65 | |
| 66 inline void Assembler::add( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(add_op3) | rs1(s1) | rs2(s2) ); } | |
| 67 inline void Assembler::add( Register s1, int simm13a, Register d, relocInfo::relocType rtype ) { emit_data( op(arith_op) | rd(d) | op3(add_op3) | rs1(s1) | immed(true) | simm(simm13a, 13), rtype ); } | |
| 68 inline void Assembler::add( Register s1, int simm13a, Register d, RelocationHolder const& rspec ) { emit_data( op(arith_op) | rd(d) | op3(add_op3) | rs1(s1) | immed(true) | simm(simm13a, 13), rspec ); } | |
| 69 inline void Assembler::add( const Address& a, Register d, int offset) { add( a.base(), a.disp() + offset, d, a.rspec(offset)); } | |
| 70 | |
| 71 inline void Assembler::bpr( RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt ) { v9_only(); emit_data( op(branch_op) | annul(a) | cond(c) | op2(bpr_op2) | wdisp16(intptr_t(d), intptr_t(pc())) | predict(p) | rs1(s1), rt); has_delay_slot(); } | |
| 72 inline void Assembler::bpr( RCondition c, bool a, Predict p, Register s1, Label& L) { bpr( c, a, p, s1, target(L)); } | |
| 73 | |
| 74 inline void Assembler::fb( Condition c, bool a, address d, relocInfo::relocType rt ) { v9_dep(); emit_data( op(branch_op) | annul(a) | cond(c) | op2(fb_op2) | wdisp(intptr_t(d), intptr_t(pc()), 22), rt); has_delay_slot(); } | |
| 75 inline void Assembler::fb( Condition c, bool a, Label& L ) { fb(c, a, target(L)); } | |
| 76 | |
| 77 inline void Assembler::fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt ) { v9_only(); emit_data( op(branch_op) | annul(a) | cond(c) | op2(fbp_op2) | branchcc(cc) | predict(p) | wdisp(intptr_t(d), intptr_t(pc()), 19), rt); has_delay_slot(); } | |
| 78 inline void Assembler::fbp( Condition c, bool a, CC cc, Predict p, Label& L ) { fbp(c, a, cc, p, target(L)); } | |
| 79 | |
| 80 inline void Assembler::cb( Condition c, bool a, address d, relocInfo::relocType rt ) { v8_only(); emit_data( op(branch_op) | annul(a) | cond(c) | op2(cb_op2) | wdisp(intptr_t(d), intptr_t(pc()), 22), rt); has_delay_slot(); } | |
| 81 inline void Assembler::cb( Condition c, bool a, Label& L ) { cb(c, a, target(L)); } | |
| 82 | |
| 83 inline void Assembler::br( Condition c, bool a, address d, relocInfo::relocType rt ) { v9_dep(); emit_data( op(branch_op) | annul(a) | cond(c) | op2(br_op2) | wdisp(intptr_t(d), intptr_t(pc()), 22), rt); has_delay_slot(); } | |
| 84 inline void Assembler::br( Condition c, bool a, Label& L ) { br(c, a, target(L)); } | |
| 85 | |
| 86 inline void Assembler::bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt ) { v9_only(); emit_data( op(branch_op) | annul(a) | cond(c) | op2(bp_op2) | branchcc(cc) | predict(p) | wdisp(intptr_t(d), intptr_t(pc()), 19), rt); has_delay_slot(); } | |
| 87 inline void Assembler::bp( Condition c, bool a, CC cc, Predict p, Label& L ) { bp(c, a, cc, p, target(L)); } | |
| 88 | |
| 89 inline void Assembler::call( address d, relocInfo::relocType rt ) { emit_data( op(call_op) | wdisp(intptr_t(d), intptr_t(pc()), 30), rt); has_delay_slot(); assert(rt != relocInfo::virtual_call_type, "must use virtual_call_Relocation::spec"); } | |
| 90 inline void Assembler::call( Label& L, relocInfo::relocType rt ) { call( target(L), rt); } | |
| 91 | |
| 92 inline void Assembler::flush( Register s1, Register s2) { emit_long( op(arith_op) | op3(flush_op3) | rs1(s1) | rs2(s2)); } | |
| 93 inline void Assembler::flush( Register s1, int simm13a) { emit_data( op(arith_op) | op3(flush_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); } | |
| 94 | |
| 95 inline void Assembler::jmpl( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(jmpl_op3) | rs1(s1) | rs2(s2)); has_delay_slot(); } | |
| 96 inline void Assembler::jmpl( Register s1, int simm13a, Register d, RelocationHolder const& rspec ) { emit_data( op(arith_op) | rd(d) | op3(jmpl_op3) | rs1(s1) | immed(true) | simm(simm13a, 13), rspec); has_delay_slot(); } | |
| 97 | |
| 98 inline void Assembler::jmpl( Address& a, Register d, int offset) { jmpl( a.base(), a.disp() + offset, d, a.rspec(offset)); } | |
| 99 | |
| 100 | |
| 101 inline void Assembler::ldf( FloatRegisterImpl::Width w, Register s1, Register s2, FloatRegister d) { emit_long( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3, w) | rs1(s1) | rs2(s2) ); } | |
| 102 inline void Assembler::ldf( FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d) { emit_data( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13)); } | |
| 103 | |
| 104 inline void Assembler::ldf( FloatRegisterImpl::Width w, const Address& a, FloatRegister d, int offset) { relocate(a.rspec(offset)); ldf( w, a.base(), a.disp() + offset, d); } | |
| 105 | |
| 106 inline void Assembler::ldfsr( Register s1, Register s2) { v9_dep(); emit_long( op(ldst_op) | op3(ldfsr_op3) | rs1(s1) | rs2(s2) ); } | |
| 107 inline void Assembler::ldfsr( Register s1, int simm13a) { v9_dep(); emit_data( op(ldst_op) | op3(ldfsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); } | |
| 108 inline void Assembler::ldxfsr( Register s1, Register s2) { v9_only(); emit_long( op(ldst_op) | rd(G1) | op3(ldfsr_op3) | rs1(s1) | rs2(s2) ); } | |
| 109 inline void Assembler::ldxfsr( Register s1, int simm13a) { v9_only(); emit_data( op(ldst_op) | rd(G1) | op3(ldfsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); } | |
| 110 | |
| 111 inline void Assembler::ldc( Register s1, Register s2, int crd) { v8_only(); emit_long( op(ldst_op) | fcn(crd) | op3(ldc_op3 ) | rs1(s1) | rs2(s2) ); } | |
| 112 inline void Assembler::ldc( Register s1, int simm13a, int crd) { v8_only(); emit_data( op(ldst_op) | fcn(crd) | op3(ldc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13)); } | |
| 113 inline void Assembler::lddc( Register s1, Register s2, int crd) { v8_only(); emit_long( op(ldst_op) | fcn(crd) | op3(lddc_op3 ) | rs1(s1) | rs2(s2) ); } | |
| 114 inline void Assembler::lddc( Register s1, int simm13a, int crd) { v8_only(); emit_data( op(ldst_op) | fcn(crd) | op3(lddc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13)); } | |
| 115 inline void Assembler::ldcsr( Register s1, Register s2, int crd) { v8_only(); emit_long( op(ldst_op) | fcn(crd) | op3(ldcsr_op3) | rs1(s1) | rs2(s2) ); } | |
| 116 inline void Assembler::ldcsr( Register s1, int simm13a, int crd) { v8_only(); emit_data( op(ldst_op) | fcn(crd) | op3(ldcsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); } | |
| 117 | |
| 118 inline void Assembler::ldsb( Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(ldsb_op3) | rs1(s1) | rs2(s2) ); } | |
| 119 inline void Assembler::ldsb( Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(ldsb_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); } | |
| 120 | |
| 121 inline void Assembler::ldsh( Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(ldsh_op3) | rs1(s1) | rs2(s2) ); } | |
| 122 inline void Assembler::ldsh( Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(ldsh_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); } | |
| 123 inline void Assembler::ldsw( Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(ldsw_op3) | rs1(s1) | rs2(s2) ); } | |
| 124 inline void Assembler::ldsw( Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(ldsw_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); } | |
| 125 inline void Assembler::ldub( Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(ldub_op3) | rs1(s1) | rs2(s2) ); } | |
| 126 inline void Assembler::ldub( Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(ldub_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); } | |
| 127 inline void Assembler::lduh( Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(lduh_op3) | rs1(s1) | rs2(s2) ); } | |
| 128 inline void Assembler::lduh( Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(lduh_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); } | |
| 129 inline void Assembler::lduw( Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(lduw_op3) | rs1(s1) | rs2(s2) ); } | |
| 130 inline void Assembler::lduw( Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(lduw_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); } | |
| 131 | |
| 132 inline void Assembler::ldx( Register s1, Register s2, Register d) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(ldx_op3) | rs1(s1) | rs2(s2) ); } | |
| 133 inline void Assembler::ldx( Register s1, int simm13a, Register d) { v9_only(); emit_data( op(ldst_op) | rd(d) | op3(ldx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); } | |
| 134 inline void Assembler::ldd( Register s1, Register s2, Register d) { v9_dep(); assert(d->is_even(), "not even"); emit_long( op(ldst_op) | rd(d) | op3(ldd_op3) | rs1(s1) | rs2(s2) ); } | |
| 135 inline void Assembler::ldd( Register s1, int simm13a, Register d) { v9_dep(); assert(d->is_even(), "not even"); emit_data( op(ldst_op) | rd(d) | op3(ldd_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); } | |
| 136 | |
| 137 #ifdef _LP64 | |
| 138 // Make all 32 bit loads signed so 64 bit registers maintain proper sign | |
| 139 inline void Assembler::ld( Register s1, Register s2, Register d) { ldsw( s1, s2, d); } | |
| 140 inline void Assembler::ld( Register s1, int simm13a, Register d) { ldsw( s1, simm13a, d); } | |
| 141 #else | |
| 142 inline void Assembler::ld( Register s1, Register s2, Register d) { lduw( s1, s2, d); } | |
| 143 inline void Assembler::ld( Register s1, int simm13a, Register d) { lduw( s1, simm13a, d); } | |
| 144 #endif | |
| 145 | |
|
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146 inline void Assembler::ldub( Register s1, RegisterConstant s2, Register d) { |
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147 if (s2.is_register()) ldsb(s1, s2.as_register(), d); |
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148 else ldsb(s1, s2.as_constant(), d); |
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149 } |
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150 inline void Assembler::ldsb( Register s1, RegisterConstant s2, Register d) { |
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151 if (s2.is_register()) ldsb(s1, s2.as_register(), d); |
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152 else ldsb(s1, s2.as_constant(), d); |
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153 } |
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154 inline void Assembler::lduh( Register s1, RegisterConstant s2, Register d) { |
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155 if (s2.is_register()) ldsh(s1, s2.as_register(), d); |
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156 else ldsh(s1, s2.as_constant(), d); |
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157 } |
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158 inline void Assembler::ldsh( Register s1, RegisterConstant s2, Register d) { |
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159 if (s2.is_register()) ldsh(s1, s2.as_register(), d); |
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160 else ldsh(s1, s2.as_constant(), d); |
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161 } |
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162 inline void Assembler::lduw( Register s1, RegisterConstant s2, Register d) { |
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163 if (s2.is_register()) ldsw(s1, s2.as_register(), d); |
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164 else ldsw(s1, s2.as_constant(), d); |
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165 } |
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166 inline void Assembler::ldsw( Register s1, RegisterConstant s2, Register d) { |
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167 if (s2.is_register()) ldsw(s1, s2.as_register(), d); |
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168 else ldsw(s1, s2.as_constant(), d); |
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169 } |
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170 inline void Assembler::ldx( Register s1, RegisterConstant s2, Register d) { |
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171 if (s2.is_register()) ldx(s1, s2.as_register(), d); |
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172 else ldx(s1, s2.as_constant(), d); |
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173 } |
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174 inline void Assembler::ld( Register s1, RegisterConstant s2, Register d) { |
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175 if (s2.is_register()) ld(s1, s2.as_register(), d); |
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176 else ld(s1, s2.as_constant(), d); |
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177 } |
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178 inline void Assembler::ldd( Register s1, RegisterConstant s2, Register d) { |
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179 if (s2.is_register()) ldd(s1, s2.as_register(), d); |
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180 else ldd(s1, s2.as_constant(), d); |
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181 } |
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182 |
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183 // form effective addresses this way: |
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184 inline void Assembler::add( Register s1, RegisterConstant s2, Register d, int offset) { |
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185 if (s2.is_register()) add(s1, s2.as_register(), d); |
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186 else { add(s1, s2.as_constant() + offset, d); offset = 0; } |
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187 if (offset != 0) add(d, offset, d); |
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188 } |
| 0 | 189 |
| 190 inline void Assembler::ld( const Address& a, Register d, int offset ) { relocate(a.rspec(offset)); ld( a.base(), a.disp() + offset, d ); } | |
| 191 inline void Assembler::ldsb( const Address& a, Register d, int offset ) { relocate(a.rspec(offset)); ldsb( a.base(), a.disp() + offset, d ); } | |
| 192 inline void Assembler::ldsh( const Address& a, Register d, int offset ) { relocate(a.rspec(offset)); ldsh( a.base(), a.disp() + offset, d ); } | |
| 193 inline void Assembler::ldsw( const Address& a, Register d, int offset ) { relocate(a.rspec(offset)); ldsw( a.base(), a.disp() + offset, d ); } | |
| 194 inline void Assembler::ldub( const Address& a, Register d, int offset ) { relocate(a.rspec(offset)); ldub( a.base(), a.disp() + offset, d ); } | |
| 195 inline void Assembler::lduh( const Address& a, Register d, int offset ) { relocate(a.rspec(offset)); lduh( a.base(), a.disp() + offset, d ); } | |
| 196 inline void Assembler::lduw( const Address& a, Register d, int offset ) { relocate(a.rspec(offset)); lduw( a.base(), a.disp() + offset, d ); } | |
| 197 inline void Assembler::ldd( const Address& a, Register d, int offset ) { relocate(a.rspec(offset)); ldd( a.base(), a.disp() + offset, d ); } | |
| 198 inline void Assembler::ldx( const Address& a, Register d, int offset ) { relocate(a.rspec(offset)); ldx( a.base(), a.disp() + offset, d ); } | |
| 199 | |
| 200 | |
| 201 inline void Assembler::ldstub( Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(ldstub_op3) | rs1(s1) | rs2(s2) ); } | |
| 202 inline void Assembler::ldstub( Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(ldstub_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); } | |
| 203 | |
| 204 | |
| 205 inline void Assembler::prefetch(Register s1, Register s2, PrefetchFcn f) { v9_only(); emit_long( op(ldst_op) | fcn(f) | op3(prefetch_op3) | rs1(s1) | rs2(s2) ); } | |
| 206 inline void Assembler::prefetch(Register s1, int simm13a, PrefetchFcn f) { v9_only(); emit_data( op(ldst_op) | fcn(f) | op3(prefetch_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); } | |
| 207 | |
| 208 inline void Assembler::prefetch(const Address& a, PrefetchFcn f, int offset) { v9_only(); relocate(a.rspec(offset)); prefetch(a.base(), a.disp() + offset, f); } | |
| 209 | |
| 210 | |
| 211 inline void Assembler::rett( Register s1, Register s2 ) { emit_long( op(arith_op) | op3(rett_op3) | rs1(s1) | rs2(s2)); has_delay_slot(); } | |
| 212 inline void Assembler::rett( Register s1, int simm13a, relocInfo::relocType rt) { emit_data( op(arith_op) | op3(rett_op3) | rs1(s1) | immed(true) | simm(simm13a, 13), rt); has_delay_slot(); } | |
| 213 | |
| 214 inline void Assembler::sethi( int imm22a, Register d, RelocationHolder const& rspec ) { emit_data( op(branch_op) | rd(d) | op2(sethi_op2) | hi22(imm22a), rspec); } | |
| 215 | |
| 216 // pp 222 | |
| 217 | |
| 218 inline void Assembler::stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2) { emit_long( op(ldst_op) | fd(d, w) | alt_op3(stf_op3, w) | rs1(s1) | rs2(s2) ); } | |
| 219 inline void Assembler::stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a) { emit_data( op(ldst_op) | fd(d, w) | alt_op3(stf_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13)); } | |
| 220 | |
| 221 inline void Assembler::stf( FloatRegisterImpl::Width w, FloatRegister d, const Address& a, int offset) { relocate(a.rspec(offset)); stf(w, d, a.base(), a.disp() + offset); } | |
| 222 | |
| 223 inline void Assembler::stfsr( Register s1, Register s2) { v9_dep(); emit_long( op(ldst_op) | op3(stfsr_op3) | rs1(s1) | rs2(s2) ); } | |
| 224 inline void Assembler::stfsr( Register s1, int simm13a) { v9_dep(); emit_data( op(ldst_op) | op3(stfsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); } | |
| 225 inline void Assembler::stxfsr( Register s1, Register s2) { v9_only(); emit_long( op(ldst_op) | rd(G1) | op3(stfsr_op3) | rs1(s1) | rs2(s2) ); } | |
| 226 inline void Assembler::stxfsr( Register s1, int simm13a) { v9_only(); emit_data( op(ldst_op) | rd(G1) | op3(stfsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); } | |
| 227 | |
| 228 // p 226 | |
| 229 | |
| 230 inline void Assembler::stb( Register d, Register s1, Register s2) { emit_long( op(ldst_op) | rd(d) | op3(stb_op3) | rs1(s1) | rs2(s2) ); } | |
| 231 inline void Assembler::stb( Register d, Register s1, int simm13a) { emit_data( op(ldst_op) | rd(d) | op3(stb_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); } | |
| 232 inline void Assembler::sth( Register d, Register s1, Register s2) { emit_long( op(ldst_op) | rd(d) | op3(sth_op3) | rs1(s1) | rs2(s2) ); } | |
| 233 inline void Assembler::sth( Register d, Register s1, int simm13a) { emit_data( op(ldst_op) | rd(d) | op3(sth_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); } | |
| 234 inline void Assembler::stw( Register d, Register s1, Register s2) { emit_long( op(ldst_op) | rd(d) | op3(stw_op3) | rs1(s1) | rs2(s2) ); } | |
| 235 inline void Assembler::stw( Register d, Register s1, int simm13a) { emit_data( op(ldst_op) | rd(d) | op3(stw_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); } | |
| 236 | |
| 237 | |
| 238 inline void Assembler::stx( Register d, Register s1, Register s2) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(stx_op3) | rs1(s1) | rs2(s2) ); } | |
| 239 inline void Assembler::stx( Register d, Register s1, int simm13a) { v9_only(); emit_data( op(ldst_op) | rd(d) | op3(stx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); } | |
| 240 inline void Assembler::std( Register d, Register s1, Register s2) { v9_dep(); assert(d->is_even(), "not even"); emit_long( op(ldst_op) | rd(d) | op3(std_op3) | rs1(s1) | rs2(s2) ); } | |
| 241 inline void Assembler::std( Register d, Register s1, int simm13a) { v9_dep(); assert(d->is_even(), "not even"); emit_data( op(ldst_op) | rd(d) | op3(std_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); } | |
| 242 | |
| 243 inline void Assembler::st( Register d, Register s1, Register s2) { stw(d, s1, s2); } | |
| 244 inline void Assembler::st( Register d, Register s1, int simm13a) { stw(d, s1, simm13a); } | |
| 245 | |
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246 inline void Assembler::stb( Register d, Register s1, RegisterConstant s2) { |
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247 if (s2.is_register()) stb(d, s1, s2.as_register()); |
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248 else stb(d, s1, s2.as_constant()); |
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249 } |
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250 inline void Assembler::sth( Register d, Register s1, RegisterConstant s2) { |
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251 if (s2.is_register()) sth(d, s1, s2.as_register()); |
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252 else sth(d, s1, s2.as_constant()); |
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253 } |
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254 inline void Assembler::stx( Register d, Register s1, RegisterConstant s2) { |
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255 if (s2.is_register()) stx(d, s1, s2.as_register()); |
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256 else stx(d, s1, s2.as_constant()); |
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257 } |
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258 inline void Assembler::std( Register d, Register s1, RegisterConstant s2) { |
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259 if (s2.is_register()) std(d, s1, s2.as_register()); |
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260 else std(d, s1, s2.as_constant()); |
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261 } |
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262 inline void Assembler::st( Register d, Register s1, RegisterConstant s2) { |
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263 if (s2.is_register()) st(d, s1, s2.as_register()); |
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264 else st(d, s1, s2.as_constant()); |
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265 } |
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266 |
| 0 | 267 inline void Assembler::stb( Register d, const Address& a, int offset) { relocate(a.rspec(offset)); stb( d, a.base(), a.disp() + offset); } |
| 268 inline void Assembler::sth( Register d, const Address& a, int offset) { relocate(a.rspec(offset)); sth( d, a.base(), a.disp() + offset); } | |
| 269 inline void Assembler::stw( Register d, const Address& a, int offset) { relocate(a.rspec(offset)); stw( d, a.base(), a.disp() + offset); } | |
| 270 inline void Assembler::st( Register d, const Address& a, int offset) { relocate(a.rspec(offset)); st( d, a.base(), a.disp() + offset); } | |
| 271 inline void Assembler::std( Register d, const Address& a, int offset) { relocate(a.rspec(offset)); std( d, a.base(), a.disp() + offset); } | |
| 272 inline void Assembler::stx( Register d, const Address& a, int offset) { relocate(a.rspec(offset)); stx( d, a.base(), a.disp() + offset); } | |
| 273 | |
| 274 // v8 p 99 | |
| 275 | |
| 276 inline void Assembler::stc( int crd, Register s1, Register s2) { v8_only(); emit_long( op(ldst_op) | fcn(crd) | op3(stc_op3 ) | rs1(s1) | rs2(s2) ); } | |
| 277 inline void Assembler::stc( int crd, Register s1, int simm13a) { v8_only(); emit_data( op(ldst_op) | fcn(crd) | op3(stc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13)); } | |
| 278 inline void Assembler::stdc( int crd, Register s1, Register s2) { v8_only(); emit_long( op(ldst_op) | fcn(crd) | op3(stdc_op3) | rs1(s1) | rs2(s2) ); } | |
| 279 inline void Assembler::stdc( int crd, Register s1, int simm13a) { v8_only(); emit_data( op(ldst_op) | fcn(crd) | op3(stdc_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); } | |
| 280 inline void Assembler::stcsr( int crd, Register s1, Register s2) { v8_only(); emit_long( op(ldst_op) | fcn(crd) | op3(stcsr_op3) | rs1(s1) | rs2(s2) ); } | |
| 281 inline void Assembler::stcsr( int crd, Register s1, int simm13a) { v8_only(); emit_data( op(ldst_op) | fcn(crd) | op3(stcsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); } | |
| 282 inline void Assembler::stdcq( int crd, Register s1, Register s2) { v8_only(); emit_long( op(ldst_op) | fcn(crd) | op3(stdcq_op3) | rs1(s1) | rs2(s2) ); } | |
| 283 inline void Assembler::stdcq( int crd, Register s1, int simm13a) { v8_only(); emit_data( op(ldst_op) | fcn(crd) | op3(stdcq_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); } | |
| 284 | |
| 285 | |
| 286 // pp 231 | |
| 287 | |
| 288 inline void Assembler::swap( Register s1, Register s2, Register d) { v9_dep(); emit_long( op(ldst_op) | rd(d) | op3(swap_op3) | rs1(s1) | rs2(s2) ); } | |
| 289 inline void Assembler::swap( Register s1, int simm13a, Register d) { v9_dep(); emit_data( op(ldst_op) | rd(d) | op3(swap_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); } | |
| 290 | |
| 291 inline void Assembler::swap( Address& a, Register d, int offset ) { relocate(a.rspec(offset)); swap( a.base(), a.disp() + offset, d ); } | |
| 292 | |
| 293 | |
| 294 // Use the right loads/stores for the platform | |
| 295 inline void MacroAssembler::ld_ptr( Register s1, Register s2, Register d ) { | |
| 296 #ifdef _LP64 | |
| 297 Assembler::ldx( s1, s2, d); | |
| 298 #else | |
| 299 Assembler::ld( s1, s2, d); | |
| 300 #endif | |
| 301 } | |
| 302 | |
| 303 inline void MacroAssembler::ld_ptr( Register s1, int simm13a, Register d ) { | |
| 304 #ifdef _LP64 | |
| 305 Assembler::ldx( s1, simm13a, d); | |
| 306 #else | |
| 307 Assembler::ld( s1, simm13a, d); | |
| 308 #endif | |
| 309 } | |
| 310 | |
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311 inline void MacroAssembler::ld_ptr( Register s1, RegisterConstant s2, Register d ) { |
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312 #ifdef _LP64 |
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313 Assembler::ldx( s1, s2, d); |
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314 #else |
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315 Assembler::ld( s1, s2, d); |
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316 #endif |
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317 } |
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318 |
| 0 | 319 inline void MacroAssembler::ld_ptr( const Address& a, Register d, int offset ) { |
| 320 #ifdef _LP64 | |
| 321 Assembler::ldx( a, d, offset ); | |
| 322 #else | |
| 323 Assembler::ld( a, d, offset ); | |
| 324 #endif | |
| 325 } | |
| 326 | |
| 327 inline void MacroAssembler::st_ptr( Register d, Register s1, Register s2 ) { | |
| 328 #ifdef _LP64 | |
| 329 Assembler::stx( d, s1, s2); | |
| 330 #else | |
| 331 Assembler::st( d, s1, s2); | |
| 332 #endif | |
| 333 } | |
| 334 | |
| 335 inline void MacroAssembler::st_ptr( Register d, Register s1, int simm13a ) { | |
| 336 #ifdef _LP64 | |
| 337 Assembler::stx( d, s1, simm13a); | |
| 338 #else | |
| 339 Assembler::st( d, s1, simm13a); | |
| 340 #endif | |
| 341 } | |
| 342 | |
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343 inline void MacroAssembler::st_ptr( Register d, Register s1, RegisterConstant s2 ) { |
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344 #ifdef _LP64 |
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345 Assembler::stx( d, s1, s2); |
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346 #else |
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347 Assembler::st( d, s1, s2); |
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348 #endif |
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349 } |
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350 |
| 0 | 351 inline void MacroAssembler::st_ptr( Register d, const Address& a, int offset) { |
| 352 #ifdef _LP64 | |
| 353 Assembler::stx( d, a, offset); | |
| 354 #else | |
| 355 Assembler::st( d, a, offset); | |
| 356 #endif | |
| 357 } | |
| 358 | |
| 359 // Use the right loads/stores for the platform | |
| 360 inline void MacroAssembler::ld_long( Register s1, Register s2, Register d ) { | |
| 361 #ifdef _LP64 | |
| 362 Assembler::ldx(s1, s2, d); | |
| 363 #else | |
| 364 Assembler::ldd(s1, s2, d); | |
| 365 #endif | |
| 366 } | |
| 367 | |
| 368 inline void MacroAssembler::ld_long( Register s1, int simm13a, Register d ) { | |
| 369 #ifdef _LP64 | |
| 370 Assembler::ldx(s1, simm13a, d); | |
| 371 #else | |
| 372 Assembler::ldd(s1, simm13a, d); | |
| 373 #endif | |
| 374 } | |
| 375 | |
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376 inline void MacroAssembler::ld_long( Register s1, RegisterConstant s2, Register d ) { |
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377 #ifdef _LP64 |
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378 Assembler::ldx(s1, s2, d); |
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379 #else |
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380 Assembler::ldd(s1, s2, d); |
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381 #endif |
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382 } |
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383 |
| 0 | 384 inline void MacroAssembler::ld_long( const Address& a, Register d, int offset ) { |
| 385 #ifdef _LP64 | |
| 386 Assembler::ldx(a, d, offset ); | |
| 387 #else | |
| 388 Assembler::ldd(a, d, offset ); | |
| 389 #endif | |
| 390 } | |
| 391 | |
| 392 inline void MacroAssembler::st_long( Register d, Register s1, Register s2 ) { | |
| 393 #ifdef _LP64 | |
| 394 Assembler::stx(d, s1, s2); | |
| 395 #else | |
| 396 Assembler::std(d, s1, s2); | |
| 397 #endif | |
| 398 } | |
| 399 | |
| 400 inline void MacroAssembler::st_long( Register d, Register s1, int simm13a ) { | |
| 401 #ifdef _LP64 | |
| 402 Assembler::stx(d, s1, simm13a); | |
| 403 #else | |
| 404 Assembler::std(d, s1, simm13a); | |
| 405 #endif | |
| 406 } | |
| 407 | |
|
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408 inline void MacroAssembler::st_long( Register d, Register s1, RegisterConstant s2 ) { |
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409 #ifdef _LP64 |
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410 Assembler::stx(d, s1, s2); |
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411 #else |
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412 Assembler::std(d, s1, s2); |
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413 #endif |
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414 } |
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415 |
| 0 | 416 inline void MacroAssembler::st_long( Register d, const Address& a, int offset ) { |
| 417 #ifdef _LP64 | |
| 418 Assembler::stx(d, a, offset); | |
| 419 #else | |
| 420 Assembler::std(d, a, offset); | |
| 421 #endif | |
| 422 } | |
| 423 | |
| 424 // Functions for isolating 64 bit shifts for LP64 | |
| 425 | |
| 426 inline void MacroAssembler::sll_ptr( Register s1, Register s2, Register d ) { | |
| 427 #ifdef _LP64 | |
| 428 Assembler::sllx(s1, s2, d); | |
| 429 #else | |
| 430 Assembler::sll(s1, s2, d); | |
| 431 #endif | |
| 432 } | |
| 433 | |
| 434 inline void MacroAssembler::sll_ptr( Register s1, int imm6a, Register d ) { | |
| 435 #ifdef _LP64 | |
| 436 Assembler::sllx(s1, imm6a, d); | |
| 437 #else | |
| 438 Assembler::sll(s1, imm6a, d); | |
| 439 #endif | |
| 440 } | |
| 441 | |
| 442 inline void MacroAssembler::srl_ptr( Register s1, Register s2, Register d ) { | |
| 443 #ifdef _LP64 | |
| 444 Assembler::srlx(s1, s2, d); | |
| 445 #else | |
| 446 Assembler::srl(s1, s2, d); | |
| 447 #endif | |
| 448 } | |
| 449 | |
| 450 inline void MacroAssembler::srl_ptr( Register s1, int imm6a, Register d ) { | |
| 451 #ifdef _LP64 | |
| 452 Assembler::srlx(s1, imm6a, d); | |
| 453 #else | |
| 454 Assembler::srl(s1, imm6a, d); | |
| 455 #endif | |
| 456 } | |
| 457 | |
| 458 // Use the right branch for the platform | |
| 459 | |
| 460 inline void MacroAssembler::br( Condition c, bool a, Predict p, address d, relocInfo::relocType rt ) { | |
| 461 if (VM_Version::v9_instructions_work()) | |
| 462 Assembler::bp(c, a, icc, p, d, rt); | |
| 463 else | |
| 464 Assembler::br(c, a, d, rt); | |
| 465 } | |
| 466 | |
| 467 inline void MacroAssembler::br( Condition c, bool a, Predict p, Label& L ) { | |
| 468 br(c, a, p, target(L)); | |
| 469 } | |
| 470 | |
| 471 | |
| 472 // Branch that tests either xcc or icc depending on the | |
| 473 // architecture compiled (LP64 or not) | |
| 474 inline void MacroAssembler::brx( Condition c, bool a, Predict p, address d, relocInfo::relocType rt ) { | |
| 475 #ifdef _LP64 | |
| 476 Assembler::bp(c, a, xcc, p, d, rt); | |
| 477 #else | |
| 478 MacroAssembler::br(c, a, p, d, rt); | |
| 479 #endif | |
| 480 } | |
| 481 | |
| 482 inline void MacroAssembler::brx( Condition c, bool a, Predict p, Label& L ) { | |
| 483 brx(c, a, p, target(L)); | |
| 484 } | |
| 485 | |
| 486 inline void MacroAssembler::ba( bool a, Label& L ) { | |
| 487 br(always, a, pt, L); | |
| 488 } | |
| 489 | |
| 490 // Warning: V9 only functions | |
| 491 inline void MacroAssembler::bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt ) { | |
| 492 Assembler::bp(c, a, cc, p, d, rt); | |
| 493 } | |
| 494 | |
| 495 inline void MacroAssembler::bp( Condition c, bool a, CC cc, Predict p, Label& L ) { | |
| 496 Assembler::bp(c, a, cc, p, L); | |
| 497 } | |
| 498 | |
| 499 inline void MacroAssembler::fb( Condition c, bool a, Predict p, address d, relocInfo::relocType rt ) { | |
| 500 if (VM_Version::v9_instructions_work()) | |
| 501 fbp(c, a, fcc0, p, d, rt); | |
| 502 else | |
| 503 Assembler::fb(c, a, d, rt); | |
| 504 } | |
| 505 | |
| 506 inline void MacroAssembler::fb( Condition c, bool a, Predict p, Label& L ) { | |
| 507 fb(c, a, p, target(L)); | |
| 508 } | |
| 509 | |
| 510 inline void MacroAssembler::fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt ) { | |
| 511 Assembler::fbp(c, a, cc, p, d, rt); | |
| 512 } | |
| 513 | |
| 514 inline void MacroAssembler::fbp( Condition c, bool a, CC cc, Predict p, Label& L ) { | |
| 515 Assembler::fbp(c, a, cc, p, L); | |
| 516 } | |
| 517 | |
| 518 inline void MacroAssembler::jmp( Register s1, Register s2 ) { jmpl( s1, s2, G0 ); } | |
| 519 inline void MacroAssembler::jmp( Register s1, int simm13a, RelocationHolder const& rspec ) { jmpl( s1, simm13a, G0, rspec); } | |
| 520 | |
| 521 // Call with a check to see if we need to deal with the added | |
| 522 // expense of relocation and if we overflow the displacement | |
| 523 // of the quick call instruction./ | |
| 524 // Check to see if we have to deal with relocations | |
| 525 inline void MacroAssembler::call( address d, relocInfo::relocType rt ) { | |
| 526 #ifdef _LP64 | |
| 527 intptr_t disp; | |
| 528 // NULL is ok because it will be relocated later. | |
| 529 // Must change NULL to a reachable address in order to | |
| 530 // pass asserts here and in wdisp. | |
| 531 if ( d == NULL ) | |
| 532 d = pc(); | |
| 533 | |
| 534 // Is this address within range of the call instruction? | |
| 535 // If not, use the expensive instruction sequence | |
| 536 disp = (intptr_t)d - (intptr_t)pc(); | |
| 537 if ( disp != (intptr_t)(int32_t)disp ) { | |
| 538 relocate(rt); | |
| 539 Address dest(O7, (address)d); | |
| 540 sethi(dest, /*ForceRelocatable=*/ true); | |
| 541 jmpl(dest, O7); | |
| 542 } | |
| 543 else { | |
| 544 Assembler::call( d, rt ); | |
| 545 } | |
| 546 #else | |
| 547 Assembler::call( d, rt ); | |
| 548 #endif | |
| 549 } | |
| 550 | |
| 551 inline void MacroAssembler::call( Label& L, relocInfo::relocType rt ) { | |
| 552 MacroAssembler::call( target(L), rt); | |
| 553 } | |
| 554 | |
| 555 | |
| 556 | |
| 557 inline void MacroAssembler::callr( Register s1, Register s2 ) { jmpl( s1, s2, O7 ); } | |
| 558 inline void MacroAssembler::callr( Register s1, int simm13a, RelocationHolder const& rspec ) { jmpl( s1, simm13a, O7, rspec); } | |
| 559 | |
| 560 // prefetch instruction | |
| 561 inline void MacroAssembler::iprefetch( address d, relocInfo::relocType rt ) { | |
| 562 if (VM_Version::v9_instructions_work()) | |
| 563 Assembler::bp( never, true, xcc, pt, d, rt ); | |
| 564 } | |
| 565 inline void MacroAssembler::iprefetch( Label& L) { iprefetch( target(L) ); } | |
| 566 | |
| 567 | |
| 568 // clobbers o7 on V8!! | |
| 569 // returns delta from gotten pc to addr after | |
| 570 inline int MacroAssembler::get_pc( Register d ) { | |
| 571 int x = offset(); | |
| 572 if (VM_Version::v9_instructions_work()) | |
| 573 rdpc(d); | |
| 574 else { | |
| 575 Label lbl; | |
| 576 Assembler::call(lbl, relocInfo::none); // No relocation as this is call to pc+0x8 | |
| 577 if (d == O7) delayed()->nop(); | |
| 578 else delayed()->mov(O7, d); | |
| 579 bind(lbl); | |
| 580 } | |
| 581 return offset() - x; | |
| 582 } | |
| 583 | |
| 584 | |
| 585 // Note: All MacroAssembler::set_foo functions are defined out-of-line. | |
| 586 | |
| 587 | |
| 588 // Loads the current PC of the following instruction as an immediate value in | |
| 589 // 2 instructions. All PCs in the CodeCache are within 2 Gig of each other. | |
| 590 inline intptr_t MacroAssembler::load_pc_address( Register reg, int bytes_to_skip ) { | |
| 591 intptr_t thepc = (intptr_t)pc() + 2*BytesPerInstWord + bytes_to_skip; | |
| 592 #ifdef _LP64 | |
| 593 Unimplemented(); | |
| 594 #else | |
| 595 Assembler::sethi( thepc & ~0x3ff, reg, internal_word_Relocation::spec((address)thepc)); | |
| 596 Assembler::add(reg,thepc & 0x3ff, reg, internal_word_Relocation::spec((address)thepc)); | |
| 597 #endif | |
| 598 return thepc; | |
| 599 } | |
| 600 | |
| 601 inline void MacroAssembler::load_address( Address& a, int offset ) { | |
| 602 assert_not_delayed(); | |
| 603 #ifdef _LP64 | |
| 604 sethi(a); | |
| 605 add(a, a.base(), offset); | |
| 606 #else | |
| 607 if (a.hi() == 0 && a.rtype() == relocInfo::none) { | |
| 608 set(a.disp() + offset, a.base()); | |
| 609 } | |
| 610 else { | |
| 611 sethi(a); | |
| 612 add(a, a.base(), offset); | |
| 613 } | |
| 614 #endif | |
| 615 } | |
| 616 | |
| 617 | |
| 618 inline void MacroAssembler::split_disp( Address& a, Register temp ) { | |
| 619 assert_not_delayed(); | |
| 620 a = a.split_disp(); | |
| 621 Assembler::sethi(a.hi(), temp, a.rspec()); | |
| 622 add(a.base(), temp, a.base()); | |
| 623 } | |
| 624 | |
| 625 | |
| 626 inline void MacroAssembler::load_contents( Address& a, Register d, int offset ) { | |
| 627 assert_not_delayed(); | |
| 628 sethi(a); | |
| 629 ld(a, d, offset); | |
| 630 } | |
| 631 | |
| 632 | |
| 633 inline void MacroAssembler::load_ptr_contents( Address& a, Register d, int offset ) { | |
| 634 assert_not_delayed(); | |
| 635 sethi(a); | |
| 636 ld_ptr(a, d, offset); | |
| 637 } | |
| 638 | |
| 639 | |
| 640 inline void MacroAssembler::store_contents( Register s, Address& a, int offset ) { | |
| 641 assert_not_delayed(); | |
| 642 sethi(a); | |
| 643 st(s, a, offset); | |
| 644 } | |
| 645 | |
| 646 | |
| 647 inline void MacroAssembler::store_ptr_contents( Register s, Address& a, int offset ) { | |
| 648 assert_not_delayed(); | |
| 649 sethi(a); | |
| 650 st_ptr(s, a, offset); | |
| 651 } | |
| 652 | |
| 653 | |
| 654 // This code sequence is relocatable to any address, even on LP64. | |
| 655 inline void MacroAssembler::jumpl_to( Address& a, Register d, int offset ) { | |
| 656 assert_not_delayed(); | |
| 657 // Force fixed length sethi because NativeJump and NativeFarCall don't handle | |
| 658 // variable length instruction streams. | |
| 659 sethi(a, /*ForceRelocatable=*/ true); | |
| 660 jmpl(a, d, offset); | |
| 661 } | |
| 662 | |
| 663 | |
| 664 inline void MacroAssembler::jump_to( Address& a, int offset ) { | |
| 665 jumpl_to( a, G0, offset ); | |
| 666 } | |
| 667 | |
| 668 | |
| 669 inline void MacroAssembler::set_oop( jobject obj, Register d ) { | |
| 670 set_oop(allocate_oop_address(obj, d)); | |
| 671 } | |
| 672 | |
| 673 | |
| 674 inline void MacroAssembler::set_oop_constant( jobject obj, Register d ) { | |
| 675 set_oop(constant_oop_address(obj, d)); | |
| 676 } | |
| 677 | |
| 678 | |
| 679 inline void MacroAssembler::set_oop( Address obj_addr ) { | |
| 680 assert(obj_addr.rspec().type()==relocInfo::oop_type, "must be an oop reloc"); | |
| 681 load_address(obj_addr); | |
| 682 } | |
| 683 | |
| 684 | |
| 685 inline void MacroAssembler::load_argument( Argument& a, Register d ) { | |
| 686 if (a.is_register()) | |
| 687 mov(a.as_register(), d); | |
| 688 else | |
| 689 ld (a.as_address(), d); | |
| 690 } | |
| 691 | |
| 692 inline void MacroAssembler::store_argument( Register s, Argument& a ) { | |
| 693 if (a.is_register()) | |
| 694 mov(s, a.as_register()); | |
| 695 else | |
| 696 st_ptr (s, a.as_address()); // ABI says everything is right justified. | |
| 697 } | |
| 698 | |
| 699 inline void MacroAssembler::store_ptr_argument( Register s, Argument& a ) { | |
| 700 if (a.is_register()) | |
| 701 mov(s, a.as_register()); | |
| 702 else | |
| 703 st_ptr (s, a.as_address()); | |
| 704 } | |
| 705 | |
| 706 | |
| 707 #ifdef _LP64 | |
| 708 inline void MacroAssembler::store_float_argument( FloatRegister s, Argument& a ) { | |
| 709 if (a.is_float_register()) | |
| 710 // V9 ABI has F1, F3, F5 are used to pass instead of O0, O1, O2 | |
| 711 fmov(FloatRegisterImpl::S, s, a.as_float_register() ); | |
| 712 else | |
| 713 // Floats are stored in the high half of the stack entry | |
| 714 // The low half is undefined per the ABI. | |
| 715 stf(FloatRegisterImpl::S, s, a.as_address(), sizeof(jfloat)); | |
| 716 } | |
| 717 | |
| 718 inline void MacroAssembler::store_double_argument( FloatRegister s, Argument& a ) { | |
| 719 if (a.is_float_register()) | |
| 720 // V9 ABI has D0, D2, D4 are used to pass instead of O0, O1, O2 | |
| 721 fmov(FloatRegisterImpl::D, s, a.as_double_register() ); | |
| 722 else | |
| 723 stf(FloatRegisterImpl::D, s, a.as_address()); | |
| 724 } | |
| 725 | |
| 726 inline void MacroAssembler::store_long_argument( Register s, Argument& a ) { | |
| 727 if (a.is_register()) | |
| 728 mov(s, a.as_register()); | |
| 729 else | |
| 730 stx(s, a.as_address()); | |
| 731 } | |
| 732 #endif | |
| 733 | |
| 734 inline void MacroAssembler::clrb( Register s1, Register s2) { stb( G0, s1, s2 ); } | |
| 735 inline void MacroAssembler::clrh( Register s1, Register s2) { sth( G0, s1, s2 ); } | |
| 736 inline void MacroAssembler::clr( Register s1, Register s2) { stw( G0, s1, s2 ); } | |
| 737 inline void MacroAssembler::clrx( Register s1, Register s2) { stx( G0, s1, s2 ); } | |
| 738 | |
| 739 inline void MacroAssembler::clrb( Register s1, int simm13a) { stb( G0, s1, simm13a); } | |
| 740 inline void MacroAssembler::clrh( Register s1, int simm13a) { sth( G0, s1, simm13a); } | |
| 741 inline void MacroAssembler::clr( Register s1, int simm13a) { stw( G0, s1, simm13a); } | |
| 742 inline void MacroAssembler::clrx( Register s1, int simm13a) { stx( G0, s1, simm13a); } | |
| 743 | |
| 744 // returns if membar generates anything, obviously this code should mirror | |
| 745 // membar below. | |
| 746 inline bool MacroAssembler::membar_has_effect( Membar_mask_bits const7a ) { | |
| 747 if( !os::is_MP() ) return false; // Not needed on single CPU | |
| 748 if( VM_Version::v9_instructions_work() ) { | |
| 749 const Membar_mask_bits effective_mask = | |
| 750 Membar_mask_bits(const7a & ~(LoadLoad | LoadStore | StoreStore)); | |
| 751 return (effective_mask != 0); | |
| 752 } else { | |
| 753 return true; | |
| 754 } | |
| 755 } | |
| 756 | |
| 757 inline void MacroAssembler::membar( Membar_mask_bits const7a ) { | |
| 758 // Uniprocessors do not need memory barriers | |
| 759 if (!os::is_MP()) return; | |
| 760 // Weakened for current Sparcs and TSO. See the v9 manual, sections 8.4.3, | |
| 761 // 8.4.4.3, a.31 and a.50. | |
| 762 if( VM_Version::v9_instructions_work() ) { | |
| 763 // Under TSO, setting bit 3, 2, or 0 is redundant, so the only value | |
| 764 // of the mmask subfield of const7a that does anything that isn't done | |
| 765 // implicitly is StoreLoad. | |
| 766 const Membar_mask_bits effective_mask = | |
| 767 Membar_mask_bits(const7a & ~(LoadLoad | LoadStore | StoreStore)); | |
| 768 if ( effective_mask != 0 ) { | |
| 769 Assembler::membar( effective_mask ); | |
| 770 } | |
| 771 } else { | |
| 772 // stbar is the closest there is on v8. Equivalent to membar(StoreStore). We | |
| 773 // do not issue the stbar because to my knowledge all v8 machines implement TSO, | |
| 774 // which guarantees that all stores behave as if an stbar were issued just after | |
| 775 // each one of them. On these machines, stbar ought to be a nop. There doesn't | |
| 776 // appear to be an equivalent of membar(StoreLoad) on v8: TSO doesn't require it, | |
| 777 // it can't be specified by stbar, nor have I come up with a way to simulate it. | |
| 778 // | |
| 779 // Addendum. Dave says that ldstub guarantees a write buffer flush to coherent | |
| 780 // space. Put one here to be on the safe side. | |
| 781 Assembler::ldstub(SP, 0, G0); | |
| 782 } | |
| 783 } |