Mercurial > hg > truffle
annotate src/cpu/x86/vm/assembler_x86.hpp @ 1493:5dabb4e73380
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date | Thu, 06 May 2010 13:03:03 -0700 |
parents | 2f1ec89b9995 |
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0 | 1 /* |
624 | 2 * Copyright 1997-2009 Sun Microsystems, Inc. All Rights Reserved. |
0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
4 * | |
5 * This code is free software; you can redistribute it and/or modify it | |
6 * under the terms of the GNU General Public License version 2 only, as | |
7 * published by the Free Software Foundation. | |
8 * | |
9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 * version 2 for more details (a copy is included in the LICENSE file that | |
13 * accompanied this code). | |
14 * | |
15 * You should have received a copy of the GNU General Public License version | |
16 * 2 along with this work; if not, write to the Free Software Foundation, | |
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
18 * | |
19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
20 * CA 95054 USA or visit www.sun.com if you need additional information or | |
21 * have any questions. | |
22 * | |
23 */ | |
24 | |
25 class BiasedLockingCounters; | |
26 | |
27 // Contains all the definitions needed for x86 assembly code generation. | |
28 | |
29 // Calling convention | |
30 class Argument VALUE_OBJ_CLASS_SPEC { | |
31 public: | |
32 enum { | |
33 #ifdef _LP64 | |
34 #ifdef _WIN64 | |
35 n_int_register_parameters_c = 4, // rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...) | |
36 n_float_register_parameters_c = 4, // xmm0 - xmm3 (c_farg0, c_farg1, ... ) | |
37 #else | |
38 n_int_register_parameters_c = 6, // rdi, rsi, rdx, rcx, r8, r9 (c_rarg0, c_rarg1, ...) | |
39 n_float_register_parameters_c = 8, // xmm0 - xmm7 (c_farg0, c_farg1, ... ) | |
40 #endif // _WIN64 | |
41 n_int_register_parameters_j = 6, // j_rarg0, j_rarg1, ... | |
42 n_float_register_parameters_j = 8 // j_farg0, j_farg1, ... | |
43 #else | |
44 n_register_parameters = 0 // 0 registers used to pass arguments | |
45 #endif // _LP64 | |
46 }; | |
47 }; | |
48 | |
49 | |
50 #ifdef _LP64 | |
51 // Symbolically name the register arguments used by the c calling convention. | |
52 // Windows is different from linux/solaris. So much for standards... | |
53 | |
54 #ifdef _WIN64 | |
55 | |
56 REGISTER_DECLARATION(Register, c_rarg0, rcx); | |
57 REGISTER_DECLARATION(Register, c_rarg1, rdx); | |
58 REGISTER_DECLARATION(Register, c_rarg2, r8); | |
59 REGISTER_DECLARATION(Register, c_rarg3, r9); | |
60 | |
304 | 61 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0); |
62 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1); | |
63 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2); | |
64 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3); | |
0 | 65 |
66 #else | |
67 | |
68 REGISTER_DECLARATION(Register, c_rarg0, rdi); | |
69 REGISTER_DECLARATION(Register, c_rarg1, rsi); | |
70 REGISTER_DECLARATION(Register, c_rarg2, rdx); | |
71 REGISTER_DECLARATION(Register, c_rarg3, rcx); | |
72 REGISTER_DECLARATION(Register, c_rarg4, r8); | |
73 REGISTER_DECLARATION(Register, c_rarg5, r9); | |
74 | |
304 | 75 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0); |
76 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1); | |
77 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2); | |
78 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3); | |
79 REGISTER_DECLARATION(XMMRegister, c_farg4, xmm4); | |
80 REGISTER_DECLARATION(XMMRegister, c_farg5, xmm5); | |
81 REGISTER_DECLARATION(XMMRegister, c_farg6, xmm6); | |
82 REGISTER_DECLARATION(XMMRegister, c_farg7, xmm7); | |
0 | 83 |
84 #endif // _WIN64 | |
85 | |
86 // Symbolically name the register arguments used by the Java calling convention. | |
87 // We have control over the convention for java so we can do what we please. | |
88 // What pleases us is to offset the java calling convention so that when | |
89 // we call a suitable jni method the arguments are lined up and we don't | |
90 // have to do little shuffling. A suitable jni method is non-static and a | |
91 // small number of arguments (two fewer args on windows) | |
92 // | |
93 // |-------------------------------------------------------| | |
94 // | c_rarg0 c_rarg1 c_rarg2 c_rarg3 c_rarg4 c_rarg5 | | |
95 // |-------------------------------------------------------| | |
96 // | rcx rdx r8 r9 rdi* rsi* | windows (* not a c_rarg) | |
97 // | rdi rsi rdx rcx r8 r9 | solaris/linux | |
98 // |-------------------------------------------------------| | |
99 // | j_rarg5 j_rarg0 j_rarg1 j_rarg2 j_rarg3 j_rarg4 | | |
100 // |-------------------------------------------------------| | |
101 | |
102 REGISTER_DECLARATION(Register, j_rarg0, c_rarg1); | |
103 REGISTER_DECLARATION(Register, j_rarg1, c_rarg2); | |
104 REGISTER_DECLARATION(Register, j_rarg2, c_rarg3); | |
105 // Windows runs out of register args here | |
106 #ifdef _WIN64 | |
107 REGISTER_DECLARATION(Register, j_rarg3, rdi); | |
108 REGISTER_DECLARATION(Register, j_rarg4, rsi); | |
109 #else | |
110 REGISTER_DECLARATION(Register, j_rarg3, c_rarg4); | |
111 REGISTER_DECLARATION(Register, j_rarg4, c_rarg5); | |
112 #endif /* _WIN64 */ | |
113 REGISTER_DECLARATION(Register, j_rarg5, c_rarg0); | |
114 | |
304 | 115 REGISTER_DECLARATION(XMMRegister, j_farg0, xmm0); |
116 REGISTER_DECLARATION(XMMRegister, j_farg1, xmm1); | |
117 REGISTER_DECLARATION(XMMRegister, j_farg2, xmm2); | |
118 REGISTER_DECLARATION(XMMRegister, j_farg3, xmm3); | |
119 REGISTER_DECLARATION(XMMRegister, j_farg4, xmm4); | |
120 REGISTER_DECLARATION(XMMRegister, j_farg5, xmm5); | |
121 REGISTER_DECLARATION(XMMRegister, j_farg6, xmm6); | |
122 REGISTER_DECLARATION(XMMRegister, j_farg7, xmm7); | |
0 | 123 |
124 REGISTER_DECLARATION(Register, rscratch1, r10); // volatile | |
125 REGISTER_DECLARATION(Register, rscratch2, r11); // volatile | |
126 | |
304 | 127 REGISTER_DECLARATION(Register, r12_heapbase, r12); // callee-saved |
0 | 128 REGISTER_DECLARATION(Register, r15_thread, r15); // callee-saved |
129 | |
304 | 130 #else |
131 // rscratch1 will apear in 32bit code that is dead but of course must compile | |
132 // Using noreg ensures if the dead code is incorrectly live and executed it | |
133 // will cause an assertion failure | |
134 #define rscratch1 noreg | |
135 | |
0 | 136 #endif // _LP64 |
137 | |
138 // Address is an abstraction used to represent a memory location | |
139 // using any of the amd64 addressing modes with one object. | |
140 // | |
141 // Note: A register location is represented via a Register, not | |
142 // via an address for efficiency & simplicity reasons. | |
143 | |
144 class ArrayAddress; | |
145 | |
146 class Address VALUE_OBJ_CLASS_SPEC { | |
147 public: | |
148 enum ScaleFactor { | |
149 no_scale = -1, | |
150 times_1 = 0, | |
151 times_2 = 1, | |
152 times_4 = 2, | |
304 | 153 times_8 = 3, |
154 times_ptr = LP64_ONLY(times_8) NOT_LP64(times_4) | |
0 | 155 }; |
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156 static ScaleFactor times(int size) { |
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157 assert(size >= 1 && size <= 8 && is_power_of_2(size), "bad scale size"); |
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158 if (size == 8) return times_8; |
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159 if (size == 4) return times_4; |
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160 if (size == 2) return times_2; |
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161 return times_1; |
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162 } |
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163 static int scale_size(ScaleFactor scale) { |
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164 assert(scale != no_scale, ""); |
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165 assert(((1 << (int)times_1) == 1 && |
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166 (1 << (int)times_2) == 2 && |
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167 (1 << (int)times_4) == 4 && |
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168 (1 << (int)times_8) == 8), ""); |
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169 return (1 << (int)scale); |
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170 } |
0 | 171 |
172 private: | |
173 Register _base; | |
174 Register _index; | |
175 ScaleFactor _scale; | |
176 int _disp; | |
177 RelocationHolder _rspec; | |
178 | |
304 | 179 // Easily misused constructors make them private |
180 // %%% can we make these go away? | |
181 NOT_LP64(Address(address loc, RelocationHolder spec);) | |
182 Address(int disp, address loc, relocInfo::relocType rtype); | |
183 Address(int disp, address loc, RelocationHolder spec); | |
0 | 184 |
185 public: | |
304 | 186 |
187 int disp() { return _disp; } | |
0 | 188 // creation |
189 Address() | |
190 : _base(noreg), | |
191 _index(noreg), | |
192 _scale(no_scale), | |
193 _disp(0) { | |
194 } | |
195 | |
196 // No default displacement otherwise Register can be implicitly | |
197 // converted to 0(Register) which is quite a different animal. | |
198 | |
199 Address(Register base, int disp) | |
200 : _base(base), | |
201 _index(noreg), | |
202 _scale(no_scale), | |
203 _disp(disp) { | |
204 } | |
205 | |
206 Address(Register base, Register index, ScaleFactor scale, int disp = 0) | |
207 : _base (base), | |
208 _index(index), | |
209 _scale(scale), | |
210 _disp (disp) { | |
211 assert(!index->is_valid() == (scale == Address::no_scale), | |
212 "inconsistent address"); | |
213 } | |
214 | |
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215 Address(Register base, RegisterOrConstant index, ScaleFactor scale = times_1, int disp = 0) |
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216 : _base (base), |
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217 _index(index.register_or_noreg()), |
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218 _scale(scale), |
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219 _disp (disp + (index.constant_or_zero() * scale_size(scale))) { |
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220 if (!index.is_register()) scale = Address::no_scale; |
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221 assert(!_index->is_valid() == (scale == Address::no_scale), |
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222 "inconsistent address"); |
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223 } |
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224 |
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225 Address plus_disp(int disp) const { |
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226 Address a = (*this); |
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227 a._disp += disp; |
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228 return a; |
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229 } |
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230 |
0 | 231 // The following two overloads are used in connection with the |
232 // ByteSize type (see sizes.hpp). They simplify the use of | |
233 // ByteSize'd arguments in assembly code. Note that their equivalent | |
234 // for the optimized build are the member functions with int disp | |
235 // argument since ByteSize is mapped to an int type in that case. | |
236 // | |
237 // Note: DO NOT introduce similar overloaded functions for WordSize | |
238 // arguments as in the optimized mode, both ByteSize and WordSize | |
239 // are mapped to the same type and thus the compiler cannot make a | |
240 // distinction anymore (=> compiler errors). | |
241 | |
242 #ifdef ASSERT | |
243 Address(Register base, ByteSize disp) | |
244 : _base(base), | |
245 _index(noreg), | |
246 _scale(no_scale), | |
247 _disp(in_bytes(disp)) { | |
248 } | |
249 | |
250 Address(Register base, Register index, ScaleFactor scale, ByteSize disp) | |
251 : _base(base), | |
252 _index(index), | |
253 _scale(scale), | |
254 _disp(in_bytes(disp)) { | |
255 assert(!index->is_valid() == (scale == Address::no_scale), | |
256 "inconsistent address"); | |
257 } | |
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258 |
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259 Address(Register base, RegisterOrConstant index, ScaleFactor scale, ByteSize disp) |
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260 : _base (base), |
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261 _index(index.register_or_noreg()), |
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262 _scale(scale), |
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263 _disp (in_bytes(disp) + (index.constant_or_zero() * scale_size(scale))) { |
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264 if (!index.is_register()) scale = Address::no_scale; |
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265 assert(!_index->is_valid() == (scale == Address::no_scale), |
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266 "inconsistent address"); |
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267 } |
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268 |
0 | 269 #endif // ASSERT |
270 | |
271 // accessors | |
342
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272 bool uses(Register reg) const { return _base == reg || _index == reg; } |
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273 Register base() const { return _base; } |
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274 Register index() const { return _index; } |
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275 ScaleFactor scale() const { return _scale; } |
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276 int disp() const { return _disp; } |
0 | 277 |
278 // Convert the raw encoding form into the form expected by the constructor for | |
279 // Address. An index of 4 (rsp) corresponds to having no index, so convert | |
280 // that to noreg for the Address constructor. | |
624 | 281 static Address make_raw(int base, int index, int scale, int disp, bool disp_is_oop); |
0 | 282 |
283 static Address make_array(ArrayAddress); | |
284 | |
285 private: | |
286 bool base_needs_rex() const { | |
287 return _base != noreg && _base->encoding() >= 8; | |
288 } | |
289 | |
290 bool index_needs_rex() const { | |
291 return _index != noreg &&_index->encoding() >= 8; | |
292 } | |
293 | |
294 relocInfo::relocType reloc() const { return _rspec.type(); } | |
295 | |
296 friend class Assembler; | |
297 friend class MacroAssembler; | |
298 friend class LIR_Assembler; // base/index/scale/disp | |
299 }; | |
300 | |
301 // | |
302 // AddressLiteral has been split out from Address because operands of this type | |
303 // need to be treated specially on 32bit vs. 64bit platforms. By splitting it out | |
304 // the few instructions that need to deal with address literals are unique and the | |
305 // MacroAssembler does not have to implement every instruction in the Assembler | |
306 // in order to search for address literals that may need special handling depending | |
307 // on the instruction and the platform. As small step on the way to merging i486/amd64 | |
308 // directories. | |
309 // | |
310 class AddressLiteral VALUE_OBJ_CLASS_SPEC { | |
311 friend class ArrayAddress; | |
312 RelocationHolder _rspec; | |
313 // Typically we use AddressLiterals we want to use their rval | |
314 // However in some situations we want the lval (effect address) of the item. | |
315 // We provide a special factory for making those lvals. | |
316 bool _is_lval; | |
317 | |
318 // If the target is far we'll need to load the ea of this to | |
319 // a register to reach it. Otherwise if near we can do rip | |
320 // relative addressing. | |
321 | |
322 address _target; | |
323 | |
324 protected: | |
325 // creation | |
326 AddressLiteral() | |
327 : _is_lval(false), | |
328 _target(NULL) | |
329 {} | |
330 | |
331 public: | |
332 | |
333 | |
334 AddressLiteral(address target, relocInfo::relocType rtype); | |
335 | |
336 AddressLiteral(address target, RelocationHolder const& rspec) | |
337 : _rspec(rspec), | |
338 _is_lval(false), | |
339 _target(target) | |
340 {} | |
341 | |
342 AddressLiteral addr() { | |
343 AddressLiteral ret = *this; | |
344 ret._is_lval = true; | |
345 return ret; | |
346 } | |
347 | |
348 | |
349 private: | |
350 | |
351 address target() { return _target; } | |
352 bool is_lval() { return _is_lval; } | |
353 | |
354 relocInfo::relocType reloc() const { return _rspec.type(); } | |
355 const RelocationHolder& rspec() const { return _rspec; } | |
356 | |
357 friend class Assembler; | |
358 friend class MacroAssembler; | |
359 friend class Address; | |
360 friend class LIR_Assembler; | |
361 }; | |
362 | |
363 // Convience classes | |
364 class RuntimeAddress: public AddressLiteral { | |
365 | |
366 public: | |
367 | |
368 RuntimeAddress(address target) : AddressLiteral(target, relocInfo::runtime_call_type) {} | |
369 | |
370 }; | |
371 | |
372 class OopAddress: public AddressLiteral { | |
373 | |
374 public: | |
375 | |
376 OopAddress(address target) : AddressLiteral(target, relocInfo::oop_type){} | |
377 | |
378 }; | |
379 | |
380 class ExternalAddress: public AddressLiteral { | |
381 | |
382 public: | |
383 | |
384 ExternalAddress(address target) : AddressLiteral(target, relocInfo::external_word_type){} | |
385 | |
386 }; | |
387 | |
388 class InternalAddress: public AddressLiteral { | |
389 | |
390 public: | |
391 | |
392 InternalAddress(address target) : AddressLiteral(target, relocInfo::internal_word_type) {} | |
393 | |
394 }; | |
395 | |
396 // x86 can do array addressing as a single operation since disp can be an absolute | |
397 // address amd64 can't. We create a class that expresses the concept but does extra | |
398 // magic on amd64 to get the final result | |
399 | |
400 class ArrayAddress VALUE_OBJ_CLASS_SPEC { | |
401 private: | |
402 | |
403 AddressLiteral _base; | |
404 Address _index; | |
405 | |
406 public: | |
407 | |
408 ArrayAddress() {}; | |
409 ArrayAddress(AddressLiteral base, Address index): _base(base), _index(index) {}; | |
410 AddressLiteral base() { return _base; } | |
411 Address index() { return _index; } | |
412 | |
413 }; | |
414 | |
304 | 415 const int FPUStateSizeInWords = NOT_LP64(27) LP64_ONLY( 512 / wordSize); |
0 | 416 |
417 // The Intel x86/Amd64 Assembler: Pure assembler doing NO optimizations on the instruction | |
418 // level (e.g. mov rax, 0 is not translated into xor rax, rax!); i.e., what you write | |
419 // is what you get. The Assembler is generating code into a CodeBuffer. | |
420 | |
421 class Assembler : public AbstractAssembler { | |
422 friend class AbstractAssembler; // for the non-virtual hack | |
423 friend class LIR_Assembler; // as_Address() | |
304 | 424 friend class StubGenerator; |
0 | 425 |
426 public: | |
427 enum Condition { // The x86 condition codes used for conditional jumps/moves. | |
428 zero = 0x4, | |
429 notZero = 0x5, | |
430 equal = 0x4, | |
431 notEqual = 0x5, | |
432 less = 0xc, | |
433 lessEqual = 0xe, | |
434 greater = 0xf, | |
435 greaterEqual = 0xd, | |
436 below = 0x2, | |
437 belowEqual = 0x6, | |
438 above = 0x7, | |
439 aboveEqual = 0x3, | |
440 overflow = 0x0, | |
441 noOverflow = 0x1, | |
442 carrySet = 0x2, | |
443 carryClear = 0x3, | |
444 negative = 0x8, | |
445 positive = 0x9, | |
446 parity = 0xa, | |
447 noParity = 0xb | |
448 }; | |
449 | |
450 enum Prefix { | |
451 // segment overrides | |
452 CS_segment = 0x2e, | |
453 SS_segment = 0x36, | |
454 DS_segment = 0x3e, | |
455 ES_segment = 0x26, | |
456 FS_segment = 0x64, | |
457 GS_segment = 0x65, | |
458 | |
459 REX = 0x40, | |
460 | |
461 REX_B = 0x41, | |
462 REX_X = 0x42, | |
463 REX_XB = 0x43, | |
464 REX_R = 0x44, | |
465 REX_RB = 0x45, | |
466 REX_RX = 0x46, | |
467 REX_RXB = 0x47, | |
468 | |
469 REX_W = 0x48, | |
470 | |
471 REX_WB = 0x49, | |
472 REX_WX = 0x4A, | |
473 REX_WXB = 0x4B, | |
474 REX_WR = 0x4C, | |
475 REX_WRB = 0x4D, | |
476 REX_WRX = 0x4E, | |
477 REX_WRXB = 0x4F | |
478 }; | |
479 | |
480 enum WhichOperand { | |
481 // input to locate_operand, and format code for relocations | |
304 | 482 imm_operand = 0, // embedded 32-bit|64-bit immediate operand |
0 | 483 disp32_operand = 1, // embedded 32-bit displacement or address |
484 call32_operand = 2, // embedded 32-bit self-relative displacement | |
304 | 485 #ifndef _LP64 |
0 | 486 _WhichOperand_limit = 3 |
304 | 487 #else |
488 narrow_oop_operand = 3, // embedded 32-bit immediate narrow oop | |
489 _WhichOperand_limit = 4 | |
490 #endif | |
0 | 491 }; |
492 | |
304 | 493 |
494 | |
495 // NOTE: The general philopsophy of the declarations here is that 64bit versions | |
496 // of instructions are freely declared without the need for wrapping them an ifdef. | |
497 // (Some dangerous instructions are ifdef's out of inappropriate jvm's.) | |
498 // In the .cpp file the implementations are wrapped so that they are dropped out | |
499 // of the resulting jvm. This is done mostly to keep the footprint of KERNEL | |
500 // to the size it was prior to merging up the 32bit and 64bit assemblers. | |
501 // | |
502 // This does mean you'll get a linker/runtime error if you use a 64bit only instruction | |
503 // in a 32bit vm. This is somewhat unfortunate but keeps the ifdef noise down. | |
504 | |
505 private: | |
506 | |
507 | |
508 // 64bit prefixes | |
509 int prefix_and_encode(int reg_enc, bool byteinst = false); | |
510 int prefixq_and_encode(int reg_enc); | |
511 | |
512 int prefix_and_encode(int dst_enc, int src_enc, bool byteinst = false); | |
513 int prefixq_and_encode(int dst_enc, int src_enc); | |
514 | |
515 void prefix(Register reg); | |
516 void prefix(Address adr); | |
517 void prefixq(Address adr); | |
518 | |
519 void prefix(Address adr, Register reg, bool byteinst = false); | |
520 void prefixq(Address adr, Register reg); | |
521 | |
522 void prefix(Address adr, XMMRegister reg); | |
523 | |
524 void prefetch_prefix(Address src); | |
525 | |
526 // Helper functions for groups of instructions | |
527 void emit_arith_b(int op1, int op2, Register dst, int imm8); | |
528 | |
529 void emit_arith(int op1, int op2, Register dst, int32_t imm32); | |
530 // only 32bit?? | |
531 void emit_arith(int op1, int op2, Register dst, jobject obj); | |
532 void emit_arith(int op1, int op2, Register dst, Register src); | |
533 | |
534 void emit_operand(Register reg, | |
535 Register base, Register index, Address::ScaleFactor scale, | |
536 int disp, | |
537 RelocationHolder const& rspec, | |
538 int rip_relative_correction = 0); | |
539 | |
540 void emit_operand(Register reg, Address adr, int rip_relative_correction = 0); | |
541 | |
542 // operands that only take the original 32bit registers | |
543 void emit_operand32(Register reg, Address adr); | |
544 | |
545 void emit_operand(XMMRegister reg, | |
546 Register base, Register index, Address::ScaleFactor scale, | |
547 int disp, | |
548 RelocationHolder const& rspec); | |
549 | |
550 void emit_operand(XMMRegister reg, Address adr); | |
551 | |
552 void emit_operand(MMXRegister reg, Address adr); | |
553 | |
554 // workaround gcc (3.2.1-7) bug | |
555 void emit_operand(Address adr, MMXRegister reg); | |
556 | |
557 | |
558 // Immediate-to-memory forms | |
559 void emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32); | |
560 | |
561 void emit_farith(int b1, int b2, int i); | |
562 | |
563 | |
564 protected: | |
565 #ifdef ASSERT | |
566 void check_relocation(RelocationHolder const& rspec, int format); | |
567 #endif | |
568 | |
569 inline void emit_long64(jlong x); | |
570 | |
571 void emit_data(jint data, relocInfo::relocType rtype, int format); | |
572 void emit_data(jint data, RelocationHolder const& rspec, int format); | |
573 void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0); | |
574 void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0); | |
575 | |
576 | |
577 bool reachable(AddressLiteral adr) NOT_LP64({ return true;}); | |
578 | |
579 // These are all easily abused and hence protected | |
580 | |
581 // 32BIT ONLY SECTION | |
582 #ifndef _LP64 | |
583 // Make these disappear in 64bit mode since they would never be correct | |
584 void cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY | |
585 void cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY | |
586 | |
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587 void mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY |
304 | 588 void mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY |
589 | |
590 void push_literal32(int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY | |
591 #else | |
592 // 64BIT ONLY SECTION | |
593 void mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec); // 64BIT ONLY | |
642
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594 |
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595 void cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec); |
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596 void cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec); |
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597 |
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598 void mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec); |
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599 void mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec); |
304 | 600 #endif // _LP64 |
601 | |
602 // These are unique in that we are ensured by the caller that the 32bit | |
603 // relative in these instructions will always be able to reach the potentially | |
604 // 64bit address described by entry. Since they can take a 64bit address they | |
605 // don't have the 32 suffix like the other instructions in this class. | |
606 | |
607 void call_literal(address entry, RelocationHolder const& rspec); | |
608 void jmp_literal(address entry, RelocationHolder const& rspec); | |
609 | |
610 // Avoid using directly section | |
611 // Instructions in this section are actually usable by anyone without danger | |
612 // of failure but have performance issues that are addressed my enhanced | |
613 // instructions which will do the proper thing base on the particular cpu. | |
614 // We protect them because we don't trust you... | |
615 | |
616 // Don't use next inc() and dec() methods directly. INC & DEC instructions | |
617 // could cause a partial flag stall since they don't set CF flag. | |
618 // Use MacroAssembler::decrement() & MacroAssembler::increment() methods | |
619 // which call inc() & dec() or add() & sub() in accordance with | |
620 // the product flag UseIncDec value. | |
621 | |
622 void decl(Register dst); | |
623 void decl(Address dst); | |
624 void decq(Register dst); | |
625 void decq(Address dst); | |
626 | |
627 void incl(Register dst); | |
628 void incl(Address dst); | |
629 void incq(Register dst); | |
630 void incq(Address dst); | |
631 | |
632 // New cpus require use of movsd and movss to avoid partial register stall | |
633 // when loading from memory. But for old Opteron use movlpd instead of movsd. | |
634 // The selection is done in MacroAssembler::movdbl() and movflt(). | |
635 | |
636 // Move Scalar Single-Precision Floating-Point Values | |
637 void movss(XMMRegister dst, Address src); | |
638 void movss(XMMRegister dst, XMMRegister src); | |
639 void movss(Address dst, XMMRegister src); | |
640 | |
641 // Move Scalar Double-Precision Floating-Point Values | |
642 void movsd(XMMRegister dst, Address src); | |
643 void movsd(XMMRegister dst, XMMRegister src); | |
644 void movsd(Address dst, XMMRegister src); | |
645 void movlpd(XMMRegister dst, Address src); | |
646 | |
647 // New cpus require use of movaps and movapd to avoid partial register stall | |
648 // when moving between registers. | |
649 void movaps(XMMRegister dst, XMMRegister src); | |
650 void movapd(XMMRegister dst, XMMRegister src); | |
651 | |
652 // End avoid using directly | |
653 | |
654 | |
655 // Instruction prefixes | |
656 void prefix(Prefix p); | |
657 | |
0 | 658 public: |
659 | |
660 // Creation | |
661 Assembler(CodeBuffer* code) : AbstractAssembler(code) {} | |
662 | |
663 // Decoding | |
664 static address locate_operand(address inst, WhichOperand which); | |
665 static address locate_next_instruction(address inst); | |
666 | |
304 | 667 // Utilities |
668 | |
669 #ifdef _LP64 | |
670 static bool is_simm(int64_t x, int nbits) { return -( CONST64(1) << (nbits-1) ) <= x && x < ( CONST64(1) << (nbits-1) ); } | |
671 static bool is_simm32(int64_t x) { return x == (int64_t)(int32_t)x; } | |
672 #else | |
673 static bool is_simm(int32_t x, int nbits) { return -( 1 << (nbits-1) ) <= x && x < ( 1 << (nbits-1) ); } | |
674 static bool is_simm32(int32_t x) { return true; } | |
675 #endif // LP64 | |
676 | |
677 // Generic instructions | |
678 // Does 32bit or 64bit as needed for the platform. In some sense these | |
679 // belong in macro assembler but there is no need for both varieties to exist | |
680 | |
681 void lea(Register dst, Address src); | |
682 | |
683 void mov(Register dst, Register src); | |
684 | |
685 void pusha(); | |
686 void popa(); | |
687 | |
688 void pushf(); | |
689 void popf(); | |
690 | |
691 void push(int32_t imm32); | |
692 | |
693 void push(Register src); | |
694 | |
695 void pop(Register dst); | |
696 | |
697 // These are dummies to prevent surprise implicit conversions to Register | |
698 void push(void* v); | |
699 void pop(void* v); | |
700 | |
701 | |
702 // These do register sized moves/scans | |
703 void rep_mov(); | |
704 void rep_set(); | |
705 void repne_scan(); | |
706 #ifdef _LP64 | |
707 void repne_scanl(); | |
708 #endif | |
709 | |
710 // Vanilla instructions in lexical order | |
711 | |
712 void adcl(Register dst, int32_t imm32); | |
0 | 713 void adcl(Register dst, Address src); |
714 void adcl(Register dst, Register src); | |
715 | |
304 | 716 void adcq(Register dst, int32_t imm32); |
717 void adcq(Register dst, Address src); | |
718 void adcq(Register dst, Register src); | |
719 | |
720 | |
721 void addl(Address dst, int32_t imm32); | |
0 | 722 void addl(Address dst, Register src); |
304 | 723 void addl(Register dst, int32_t imm32); |
0 | 724 void addl(Register dst, Address src); |
725 void addl(Register dst, Register src); | |
726 | |
304 | 727 void addq(Address dst, int32_t imm32); |
728 void addq(Address dst, Register src); | |
729 void addq(Register dst, int32_t imm32); | |
730 void addq(Register dst, Address src); | |
731 void addq(Register dst, Register src); | |
732 | |
733 | |
0 | 734 void addr_nop_4(); |
735 void addr_nop_5(); | |
736 void addr_nop_7(); | |
737 void addr_nop_8(); | |
738 | |
304 | 739 // Add Scalar Double-Precision Floating-Point Values |
740 void addsd(XMMRegister dst, Address src); | |
741 void addsd(XMMRegister dst, XMMRegister src); | |
742 | |
743 // Add Scalar Single-Precision Floating-Point Values | |
744 void addss(XMMRegister dst, Address src); | |
745 void addss(XMMRegister dst, XMMRegister src); | |
746 | |
747 void andl(Register dst, int32_t imm32); | |
748 void andl(Register dst, Address src); | |
749 void andl(Register dst, Register src); | |
750 | |
751 void andq(Register dst, int32_t imm32); | |
752 void andq(Register dst, Address src); | |
753 void andq(Register dst, Register src); | |
754 | |
755 | |
756 // Bitwise Logical AND of Packed Double-Precision Floating-Point Values | |
757 void andpd(XMMRegister dst, Address src); | |
758 void andpd(XMMRegister dst, XMMRegister src); | |
759 | |
775
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760 void bsfl(Register dst, Register src); |
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761 void bsrl(Register dst, Register src); |
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762 |
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763 #ifdef _LP64 |
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764 void bsfq(Register dst, Register src); |
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765 void bsrq(Register dst, Register src); |
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766 #endif |
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767 |
304 | 768 void bswapl(Register reg); |
769 | |
770 void bswapq(Register reg); | |
771 | |
0 | 772 void call(Label& L, relocInfo::relocType rtype); |
773 void call(Register reg); // push pc; pc <- reg | |
774 void call(Address adr); // push pc; pc <- adr | |
775 | |
304 | 776 void cdql(); |
777 | |
778 void cdqq(); | |
779 | |
780 void cld() { emit_byte(0xfc); } | |
781 | |
782 void clflush(Address adr); | |
783 | |
784 void cmovl(Condition cc, Register dst, Register src); | |
785 void cmovl(Condition cc, Register dst, Address src); | |
786 | |
787 void cmovq(Condition cc, Register dst, Register src); | |
788 void cmovq(Condition cc, Register dst, Address src); | |
789 | |
790 | |
791 void cmpb(Address dst, int imm8); | |
792 | |
793 void cmpl(Address dst, int32_t imm32); | |
794 | |
795 void cmpl(Register dst, int32_t imm32); | |
796 void cmpl(Register dst, Register src); | |
797 void cmpl(Register dst, Address src); | |
798 | |
799 void cmpq(Address dst, int32_t imm32); | |
800 void cmpq(Address dst, Register src); | |
801 | |
802 void cmpq(Register dst, int32_t imm32); | |
803 void cmpq(Register dst, Register src); | |
804 void cmpq(Register dst, Address src); | |
805 | |
806 // these are dummies used to catch attempting to convert NULL to Register | |
807 void cmpl(Register dst, void* junk); // dummy | |
808 void cmpq(Register dst, void* junk); // dummy | |
809 | |
810 void cmpw(Address dst, int imm16); | |
811 | |
812 void cmpxchg8 (Address adr); | |
813 | |
814 void cmpxchgl(Register reg, Address adr); | |
815 | |
816 void cmpxchgq(Register reg, Address adr); | |
817 | |
818 // Ordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS | |
819 void comisd(XMMRegister dst, Address src); | |
820 | |
821 // Ordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS | |
822 void comiss(XMMRegister dst, Address src); | |
823 | |
824 // Identify processor type and features | |
825 void cpuid() { | |
826 emit_byte(0x0F); | |
827 emit_byte(0xA2); | |
828 } | |
829 | |
830 // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value | |
831 void cvtsd2ss(XMMRegister dst, XMMRegister src); | |
832 | |
833 // Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value | |
834 void cvtsi2sdl(XMMRegister dst, Register src); | |
835 void cvtsi2sdq(XMMRegister dst, Register src); | |
836 | |
837 // Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value | |
838 void cvtsi2ssl(XMMRegister dst, Register src); | |
839 void cvtsi2ssq(XMMRegister dst, Register src); | |
840 | |
841 // Convert Packed Signed Doubleword Integers to Packed Double-Precision Floating-Point Value | |
842 void cvtdq2pd(XMMRegister dst, XMMRegister src); | |
843 | |
844 // Convert Packed Signed Doubleword Integers to Packed Single-Precision Floating-Point Value | |
845 void cvtdq2ps(XMMRegister dst, XMMRegister src); | |
846 | |
847 // Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value | |
848 void cvtss2sd(XMMRegister dst, XMMRegister src); | |
849 | |
850 // Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer | |
851 void cvttsd2sil(Register dst, Address src); | |
852 void cvttsd2sil(Register dst, XMMRegister src); | |
853 void cvttsd2siq(Register dst, XMMRegister src); | |
854 | |
855 // Convert with Truncation Scalar Single-Precision Floating-Point Value to Doubleword Integer | |
856 void cvttss2sil(Register dst, XMMRegister src); | |
857 void cvttss2siq(Register dst, XMMRegister src); | |
858 | |
859 // Divide Scalar Double-Precision Floating-Point Values | |
860 void divsd(XMMRegister dst, Address src); | |
861 void divsd(XMMRegister dst, XMMRegister src); | |
862 | |
863 // Divide Scalar Single-Precision Floating-Point Values | |
864 void divss(XMMRegister dst, Address src); | |
865 void divss(XMMRegister dst, XMMRegister src); | |
866 | |
867 void emms(); | |
868 | |
869 void fabs(); | |
870 | |
871 void fadd(int i); | |
872 | |
873 void fadd_d(Address src); | |
874 void fadd_s(Address src); | |
875 | |
876 // "Alternate" versions of x87 instructions place result down in FPU | |
877 // stack instead of on TOS | |
878 | |
879 void fadda(int i); // "alternate" fadd | |
880 void faddp(int i = 1); | |
881 | |
882 void fchs(); | |
883 | |
884 void fcom(int i); | |
885 | |
886 void fcomp(int i = 1); | |
887 void fcomp_d(Address src); | |
888 void fcomp_s(Address src); | |
889 | |
890 void fcompp(); | |
891 | |
892 void fcos(); | |
893 | |
894 void fdecstp(); | |
895 | |
896 void fdiv(int i); | |
897 void fdiv_d(Address src); | |
898 void fdivr_s(Address src); | |
899 void fdiva(int i); // "alternate" fdiv | |
900 void fdivp(int i = 1); | |
901 | |
902 void fdivr(int i); | |
903 void fdivr_d(Address src); | |
904 void fdiv_s(Address src); | |
905 | |
906 void fdivra(int i); // "alternate" reversed fdiv | |
907 | |
908 void fdivrp(int i = 1); | |
909 | |
910 void ffree(int i = 0); | |
911 | |
912 void fild_d(Address adr); | |
913 void fild_s(Address adr); | |
914 | |
915 void fincstp(); | |
916 | |
917 void finit(); | |
918 | |
919 void fist_s (Address adr); | |
920 void fistp_d(Address adr); | |
921 void fistp_s(Address adr); | |
922 | |
923 void fld1(); | |
924 | |
925 void fld_d(Address adr); | |
926 void fld_s(Address adr); | |
927 void fld_s(int index); | |
928 void fld_x(Address adr); // extended-precision (80-bit) format | |
929 | |
930 void fldcw(Address src); | |
931 | |
932 void fldenv(Address src); | |
933 | |
934 void fldlg2(); | |
935 | |
936 void fldln2(); | |
937 | |
938 void fldz(); | |
939 | |
940 void flog(); | |
941 void flog10(); | |
942 | |
943 void fmul(int i); | |
944 | |
945 void fmul_d(Address src); | |
946 void fmul_s(Address src); | |
947 | |
948 void fmula(int i); // "alternate" fmul | |
949 | |
950 void fmulp(int i = 1); | |
951 | |
952 void fnsave(Address dst); | |
953 | |
954 void fnstcw(Address src); | |
955 | |
956 void fnstsw_ax(); | |
957 | |
958 void fprem(); | |
959 void fprem1(); | |
960 | |
961 void frstor(Address src); | |
962 | |
963 void fsin(); | |
964 | |
965 void fsqrt(); | |
966 | |
967 void fst_d(Address adr); | |
968 void fst_s(Address adr); | |
969 | |
970 void fstp_d(Address adr); | |
971 void fstp_d(int index); | |
972 void fstp_s(Address adr); | |
973 void fstp_x(Address adr); // extended-precision (80-bit) format | |
974 | |
975 void fsub(int i); | |
976 void fsub_d(Address src); | |
977 void fsub_s(Address src); | |
978 | |
979 void fsuba(int i); // "alternate" fsub | |
980 | |
981 void fsubp(int i = 1); | |
982 | |
983 void fsubr(int i); | |
984 void fsubr_d(Address src); | |
985 void fsubr_s(Address src); | |
986 | |
987 void fsubra(int i); // "alternate" reversed fsub | |
988 | |
989 void fsubrp(int i = 1); | |
990 | |
991 void ftan(); | |
992 | |
993 void ftst(); | |
994 | |
995 void fucomi(int i = 1); | |
996 void fucomip(int i = 1); | |
997 | |
998 void fwait(); | |
999 | |
1000 void fxch(int i = 1); | |
1001 | |
1002 void fxrstor(Address src); | |
1003 | |
1004 void fxsave(Address dst); | |
1005 | |
1006 void fyl2x(); | |
1007 | |
1008 void hlt(); | |
1009 | |
1010 void idivl(Register src); | |
1011 | |
1012 void idivq(Register src); | |
1013 | |
1014 void imull(Register dst, Register src); | |
1015 void imull(Register dst, Register src, int value); | |
1016 | |
1017 void imulq(Register dst, Register src); | |
1018 void imulq(Register dst, Register src, int value); | |
1019 | |
0 | 1020 |
1021 // jcc is the generic conditional branch generator to run- | |
1022 // time routines, jcc is used for branches to labels. jcc | |
1023 // takes a branch opcode (cc) and a label (L) and generates | |
1024 // either a backward branch or a forward branch and links it | |
1025 // to the label fixup chain. Usage: | |
1026 // | |
1027 // Label L; // unbound label | |
1028 // jcc(cc, L); // forward branch to unbound label | |
1029 // bind(L); // bind label to the current pc | |
1030 // jcc(cc, L); // backward branch to bound label | |
1031 // bind(L); // illegal: a label may be bound only once | |
1032 // | |
1033 // Note: The same Label can be used for forward and backward branches | |
1034 // but it may be bound only once. | |
1035 | |
1036 void jcc(Condition cc, Label& L, | |
1037 relocInfo::relocType rtype = relocInfo::none); | |
1038 | |
1039 // Conditional jump to a 8-bit offset to L. | |
1040 // WARNING: be very careful using this for forward jumps. If the label is | |
1041 // not bound within an 8-bit offset of this instruction, a run-time error | |
1042 // will occur. | |
1043 void jccb(Condition cc, Label& L); | |
1044 | |
304 | 1045 void jmp(Address entry); // pc <- entry |
1046 | |
1047 // Label operations & relative jumps (PPUM Appendix D) | |
1048 void jmp(Label& L, relocInfo::relocType rtype = relocInfo::none); // unconditional jump to L | |
1049 | |
1050 void jmp(Register entry); // pc <- entry | |
1051 | |
1052 // Unconditional 8-bit offset jump to L. | |
1053 // WARNING: be very careful using this for forward jumps. If the label is | |
1054 // not bound within an 8-bit offset of this instruction, a run-time error | |
1055 // will occur. | |
1056 void jmpb(Label& L); | |
1057 | |
1058 void ldmxcsr( Address src ); | |
1059 | |
1060 void leal(Register dst, Address src); | |
1061 | |
1062 void leaq(Register dst, Address src); | |
1063 | |
1064 void lfence() { | |
1065 emit_byte(0x0F); | |
1066 emit_byte(0xAE); | |
1067 emit_byte(0xE8); | |
1068 } | |
1069 | |
1070 void lock(); | |
1071 | |
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1072 void lzcntl(Register dst, Register src); |
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1073 |
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1074 #ifdef _LP64 |
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1075 void lzcntq(Register dst, Register src); |
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1076 #endif |
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1077 |
304 | 1078 enum Membar_mask_bits { |
1079 StoreStore = 1 << 3, | |
1080 LoadStore = 1 << 2, | |
1081 StoreLoad = 1 << 1, | |
1082 LoadLoad = 1 << 0 | |
1083 }; | |
1084 | |
671
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1085 // Serializes memory and blows flags |
304 | 1086 void membar(Membar_mask_bits order_constraint) { |
671
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1087 if (os::is_MP()) { |
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1088 // We only have to handle StoreLoad |
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1089 if (order_constraint & StoreLoad) { |
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1090 // All usable chips support "locked" instructions which suffice |
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1091 // as barriers, and are much faster than the alternative of |
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1092 // using cpuid instruction. We use here a locked add [esp],0. |
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1093 // This is conveniently otherwise a no-op except for blowing |
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1094 // flags. |
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1095 // Any change to this code may need to revisit other places in |
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1096 // the code where this idiom is used, in particular the |
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1097 // orderAccess code. |
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1098 lock(); |
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1099 addl(Address(rsp, 0), 0);// Assert the lock# signal here |
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1100 } |
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1101 } |
304 | 1102 } |
1103 | |
1104 void mfence(); | |
1105 | |
1106 // Moves | |
1107 | |
1108 void mov64(Register dst, int64_t imm64); | |
1109 | |
1110 void movb(Address dst, Register src); | |
1111 void movb(Address dst, int imm8); | |
1112 void movb(Register dst, Address src); | |
1113 | |
1114 void movdl(XMMRegister dst, Register src); | |
1115 void movdl(Register dst, XMMRegister src); | |
1116 | |
1117 // Move Double Quadword | |
1118 void movdq(XMMRegister dst, Register src); | |
1119 void movdq(Register dst, XMMRegister src); | |
1120 | |
1121 // Move Aligned Double Quadword | |
1122 void movdqa(Address dst, XMMRegister src); | |
1123 void movdqa(XMMRegister dst, Address src); | |
1124 void movdqa(XMMRegister dst, XMMRegister src); | |
1125 | |
405 | 1126 // Move Unaligned Double Quadword |
1127 void movdqu(Address dst, XMMRegister src); | |
1128 void movdqu(XMMRegister dst, Address src); | |
1129 void movdqu(XMMRegister dst, XMMRegister src); | |
1130 | |
304 | 1131 void movl(Register dst, int32_t imm32); |
1132 void movl(Address dst, int32_t imm32); | |
1133 void movl(Register dst, Register src); | |
1134 void movl(Register dst, Address src); | |
1135 void movl(Address dst, Register src); | |
1136 | |
1137 // These dummies prevent using movl from converting a zero (like NULL) into Register | |
1138 // by giving the compiler two choices it can't resolve | |
1139 | |
1140 void movl(Address dst, void* junk); | |
1141 void movl(Register dst, void* junk); | |
1142 | |
1143 #ifdef _LP64 | |
1144 void movq(Register dst, Register src); | |
1145 void movq(Register dst, Address src); | |
1146 void movq(Address dst, Register src); | |
1147 #endif | |
1148 | |
1149 void movq(Address dst, MMXRegister src ); | |
1150 void movq(MMXRegister dst, Address src ); | |
1151 | |
1152 #ifdef _LP64 | |
1153 // These dummies prevent using movq from converting a zero (like NULL) into Register | |
1154 // by giving the compiler two choices it can't resolve | |
1155 | |
1156 void movq(Address dst, void* dummy); | |
1157 void movq(Register dst, void* dummy); | |
1158 #endif | |
1159 | |
1160 // Move Quadword | |
1161 void movq(Address dst, XMMRegister src); | |
1162 void movq(XMMRegister dst, Address src); | |
1163 | |
1164 void movsbl(Register dst, Address src); | |
1165 void movsbl(Register dst, Register src); | |
1166 | |
1167 #ifdef _LP64 | |
624 | 1168 void movsbq(Register dst, Address src); |
1169 void movsbq(Register dst, Register src); | |
1170 | |
304 | 1171 // Move signed 32bit immediate to 64bit extending sign |
1172 void movslq(Address dst, int32_t imm64); | |
1173 void movslq(Register dst, int32_t imm64); | |
1174 | |
1175 void movslq(Register dst, Address src); | |
1176 void movslq(Register dst, Register src); | |
1177 void movslq(Register dst, void* src); // Dummy declaration to cause NULL to be ambiguous | |
1178 #endif | |
1179 | |
1180 void movswl(Register dst, Address src); | |
1181 void movswl(Register dst, Register src); | |
1182 | |
624 | 1183 #ifdef _LP64 |
1184 void movswq(Register dst, Address src); | |
1185 void movswq(Register dst, Register src); | |
1186 #endif | |
1187 | |
304 | 1188 void movw(Address dst, int imm16); |
1189 void movw(Register dst, Address src); | |
1190 void movw(Address dst, Register src); | |
1191 | |
1192 void movzbl(Register dst, Address src); | |
1193 void movzbl(Register dst, Register src); | |
1194 | |
624 | 1195 #ifdef _LP64 |
1196 void movzbq(Register dst, Address src); | |
1197 void movzbq(Register dst, Register src); | |
1198 #endif | |
1199 | |
304 | 1200 void movzwl(Register dst, Address src); |
1201 void movzwl(Register dst, Register src); | |
1202 | |
624 | 1203 #ifdef _LP64 |
1204 void movzwq(Register dst, Address src); | |
1205 void movzwq(Register dst, Register src); | |
1206 #endif | |
1207 | |
304 | 1208 void mull(Address src); |
1209 void mull(Register src); | |
1210 | |
1211 // Multiply Scalar Double-Precision Floating-Point Values | |
1212 void mulsd(XMMRegister dst, Address src); | |
1213 void mulsd(XMMRegister dst, XMMRegister src); | |
1214 | |
1215 // Multiply Scalar Single-Precision Floating-Point Values | |
1216 void mulss(XMMRegister dst, Address src); | |
1217 void mulss(XMMRegister dst, XMMRegister src); | |
1218 | |
1219 void negl(Register dst); | |
1220 | |
1221 #ifdef _LP64 | |
1222 void negq(Register dst); | |
1223 #endif | |
1224 | |
1225 void nop(int i = 1); | |
1226 | |
1227 void notl(Register dst); | |
1228 | |
1229 #ifdef _LP64 | |
1230 void notq(Register dst); | |
1231 #endif | |
1232 | |
1233 void orl(Address dst, int32_t imm32); | |
1234 void orl(Register dst, int32_t imm32); | |
1235 void orl(Register dst, Address src); | |
1236 void orl(Register dst, Register src); | |
1237 | |
1238 void orq(Address dst, int32_t imm32); | |
1239 void orq(Register dst, int32_t imm32); | |
1240 void orq(Register dst, Address src); | |
1241 void orq(Register dst, Register src); | |
1242 | |
681 | 1243 // SSE4.2 string instructions |
1244 void pcmpestri(XMMRegister xmm1, XMMRegister xmm2, int imm8); | |
1245 void pcmpestri(XMMRegister xmm1, Address src, int imm8); | |
1246 | |
1060 | 1247 #ifndef _LP64 // no 32bit push/pop on amd64 |
304 | 1248 void popl(Address dst); |
1060 | 1249 #endif |
304 | 1250 |
1251 #ifdef _LP64 | |
1252 void popq(Address dst); | |
1253 #endif | |
1254 | |
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1255 void popcntl(Register dst, Address src); |
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1256 void popcntl(Register dst, Register src); |
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1257 |
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1258 #ifdef _LP64 |
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1259 void popcntq(Register dst, Address src); |
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1260 void popcntq(Register dst, Register src); |
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1261 #endif |
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1262 |
304 | 1263 // Prefetches (SSE, SSE2, 3DNOW only) |
1264 | |
1265 void prefetchnta(Address src); | |
1266 void prefetchr(Address src); | |
1267 void prefetcht0(Address src); | |
1268 void prefetcht1(Address src); | |
1269 void prefetcht2(Address src); | |
1270 void prefetchw(Address src); | |
1271 | |
1272 // Shuffle Packed Doublewords | |
1273 void pshufd(XMMRegister dst, XMMRegister src, int mode); | |
1274 void pshufd(XMMRegister dst, Address src, int mode); | |
1275 | |
1276 // Shuffle Packed Low Words | |
1277 void pshuflw(XMMRegister dst, XMMRegister src, int mode); | |
1278 void pshuflw(XMMRegister dst, Address src, int mode); | |
1279 | |
1280 // Shift Right Logical Quadword Immediate | |
1281 void psrlq(XMMRegister dst, int shift); | |
1282 | |
681 | 1283 // Logical Compare Double Quadword |
1284 void ptest(XMMRegister dst, XMMRegister src); | |
1285 void ptest(XMMRegister dst, Address src); | |
1286 | |
304 | 1287 // Interleave Low Bytes |
1288 void punpcklbw(XMMRegister dst, XMMRegister src); | |
1289 | |
1060 | 1290 #ifndef _LP64 // no 32bit push/pop on amd64 |
304 | 1291 void pushl(Address src); |
1060 | 1292 #endif |
304 | 1293 |
1294 void pushq(Address src); | |
1295 | |
1296 // Xor Packed Byte Integer Values | |
1297 void pxor(XMMRegister dst, Address src); | |
1298 void pxor(XMMRegister dst, XMMRegister src); | |
1299 | |
1300 void rcll(Register dst, int imm8); | |
1301 | |
1302 void rclq(Register dst, int imm8); | |
1303 | |
1304 void ret(int imm16); | |
0 | 1305 |
1306 void sahf(); | |
1307 | |
304 | 1308 void sarl(Register dst, int imm8); |
1309 void sarl(Register dst); | |
1310 | |
1311 void sarq(Register dst, int imm8); | |
1312 void sarq(Register dst); | |
1313 | |
1314 void sbbl(Address dst, int32_t imm32); | |
1315 void sbbl(Register dst, int32_t imm32); | |
1316 void sbbl(Register dst, Address src); | |
1317 void sbbl(Register dst, Register src); | |
1318 | |
1319 void sbbq(Address dst, int32_t imm32); | |
1320 void sbbq(Register dst, int32_t imm32); | |
1321 void sbbq(Register dst, Address src); | |
1322 void sbbq(Register dst, Register src); | |
1323 | |
1324 void setb(Condition cc, Register dst); | |
1325 | |
1326 void shldl(Register dst, Register src); | |
1327 | |
1328 void shll(Register dst, int imm8); | |
1329 void shll(Register dst); | |
1330 | |
1331 void shlq(Register dst, int imm8); | |
1332 void shlq(Register dst); | |
1333 | |
1334 void shrdl(Register dst, Register src); | |
1335 | |
1336 void shrl(Register dst, int imm8); | |
1337 void shrl(Register dst); | |
1338 | |
1339 void shrq(Register dst, int imm8); | |
1340 void shrq(Register dst); | |
1341 | |
1342 void smovl(); // QQQ generic? | |
1343 | |
1344 // Compute Square Root of Scalar Double-Precision Floating-Point Value | |
1345 void sqrtsd(XMMRegister dst, Address src); | |
1346 void sqrtsd(XMMRegister dst, XMMRegister src); | |
1347 | |
1348 void std() { emit_byte(0xfd); } | |
1349 | |
1350 void stmxcsr( Address dst ); | |
1351 | |
1352 void subl(Address dst, int32_t imm32); | |
1353 void subl(Address dst, Register src); | |
1354 void subl(Register dst, int32_t imm32); | |
1355 void subl(Register dst, Address src); | |
1356 void subl(Register dst, Register src); | |
1357 | |
1358 void subq(Address dst, int32_t imm32); | |
1359 void subq(Address dst, Register src); | |
1360 void subq(Register dst, int32_t imm32); | |
1361 void subq(Register dst, Address src); | |
1362 void subq(Register dst, Register src); | |
1363 | |
1364 | |
1365 // Subtract Scalar Double-Precision Floating-Point Values | |
1366 void subsd(XMMRegister dst, Address src); | |
0 | 1367 void subsd(XMMRegister dst, XMMRegister src); |
1368 | |
304 | 1369 // Subtract Scalar Single-Precision Floating-Point Values |
1370 void subss(XMMRegister dst, Address src); | |
1371 void subss(XMMRegister dst, XMMRegister src); | |
1372 | |
1373 void testb(Register dst, int imm8); | |
1374 | |
1375 void testl(Register dst, int32_t imm32); | |
1376 void testl(Register dst, Register src); | |
1377 void testl(Register dst, Address src); | |
1378 | |
1379 void testq(Register dst, int32_t imm32); | |
1380 void testq(Register dst, Register src); | |
1381 | |
1382 | |
1383 // Unordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS | |
1384 void ucomisd(XMMRegister dst, Address src); | |
0 | 1385 void ucomisd(XMMRegister dst, XMMRegister src); |
1386 | |
304 | 1387 // Unordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS |
1388 void ucomiss(XMMRegister dst, Address src); | |
1389 void ucomiss(XMMRegister dst, XMMRegister src); | |
1390 | |
1391 void xaddl(Address dst, Register src); | |
1392 | |
1393 void xaddq(Address dst, Register src); | |
1394 | |
1395 void xchgl(Register reg, Address adr); | |
1396 void xchgl(Register dst, Register src); | |
1397 | |
1398 void xchgq(Register reg, Address adr); | |
1399 void xchgq(Register dst, Register src); | |
1400 | |
1401 void xorl(Register dst, int32_t imm32); | |
1402 void xorl(Register dst, Address src); | |
1403 void xorl(Register dst, Register src); | |
1404 | |
1405 void xorq(Register dst, Address src); | |
1406 void xorq(Register dst, Register src); | |
1407 | |
1408 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values | |
1409 void xorpd(XMMRegister dst, Address src); | |
1410 void xorpd(XMMRegister dst, XMMRegister src); | |
1411 | |
1412 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values | |
1413 void xorps(XMMRegister dst, Address src); | |
0 | 1414 void xorps(XMMRegister dst, XMMRegister src); |
304 | 1415 |
1416 void set_byte_if_not_zero(Register dst); // sets reg to 1 if not zero, otherwise 0 | |
0 | 1417 }; |
1418 | |
1419 | |
1420 // MacroAssembler extends Assembler by frequently used macros. | |
1421 // | |
1422 // Instructions for which a 'better' code sequence exists depending | |
1423 // on arguments should also go in here. | |
1424 | |
1425 class MacroAssembler: public Assembler { | |
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1426 friend class LIR_Assembler; |
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1427 friend class Runtime1; // as_Address() |
0 | 1428 protected: |
1429 | |
1430 Address as_Address(AddressLiteral adr); | |
1431 Address as_Address(ArrayAddress adr); | |
1432 | |
1433 // Support for VM calls | |
1434 // | |
1435 // This is the base routine called by the different versions of call_VM_leaf. The interpreter | |
1436 // may customize this version by overriding it for its purposes (e.g., to save/restore | |
1437 // additional registers when doing a VM call). | |
1438 #ifdef CC_INTERP | |
1439 // c++ interpreter never wants to use interp_masm version of call_VM | |
1440 #define VIRTUAL | |
1441 #else | |
1442 #define VIRTUAL virtual | |
1443 #endif | |
1444 | |
1445 VIRTUAL void call_VM_leaf_base( | |
1446 address entry_point, // the entry point | |
1447 int number_of_arguments // the number of arguments to pop after the call | |
1448 ); | |
1449 | |
1450 // This is the base routine called by the different versions of call_VM. The interpreter | |
1451 // may customize this version by overriding it for its purposes (e.g., to save/restore | |
1452 // additional registers when doing a VM call). | |
1453 // | |
1454 // If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base | |
1455 // returns the register which contains the thread upon return. If a thread register has been | |
1456 // specified, the return value will correspond to that register. If no last_java_sp is specified | |
1457 // (noreg) than rsp will be used instead. | |
1458 VIRTUAL void call_VM_base( // returns the register containing the thread upon return | |
1459 Register oop_result, // where an oop-result ends up if any; use noreg otherwise | |
1460 Register java_thread, // the thread if computed before ; use noreg otherwise | |
1461 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise | |
1462 address entry_point, // the entry point | |
1463 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call | |
1464 bool check_exceptions // whether to check for pending exceptions after return | |
1465 ); | |
1466 | |
1467 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code. | |
1468 // The implementation is only non-empty for the InterpreterMacroAssembler, | |
1469 // as only the interpreter handles PopFrame and ForceEarlyReturn requests. | |
1470 virtual void check_and_handle_popframe(Register java_thread); | |
1471 virtual void check_and_handle_earlyret(Register java_thread); | |
1472 | |
1473 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true); | |
1474 | |
1475 // helpers for FPU flag access | |
1476 // tmp is a temporary register, if none is available use noreg | |
1477 void save_rax (Register tmp); | |
1478 void restore_rax(Register tmp); | |
1479 | |
1480 public: | |
1481 MacroAssembler(CodeBuffer* code) : Assembler(code) {} | |
1482 | |
1483 // Support for NULL-checks | |
1484 // | |
1485 // Generates code that causes a NULL OS exception if the content of reg is NULL. | |
1486 // If the accessed location is M[reg + offset] and the offset is known, provide the | |
1487 // offset. No explicit code generation is needed if the offset is within a certain | |
1488 // range (0 <= offset <= page_size). | |
1489 | |
1490 void null_check(Register reg, int offset = -1); | |
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1491 static bool needs_explicit_null_check(intptr_t offset); |
0 | 1492 |
1493 // Required platform-specific helpers for Label::patch_instructions. | |
1494 // They _shadow_ the declarations in AbstractAssembler, which are undefined. | |
1495 void pd_patch_instruction(address branch, address target); | |
1496 #ifndef PRODUCT | |
1497 static void pd_print_patched_instruction(address branch); | |
1498 #endif | |
1499 | |
1500 // The following 4 methods return the offset of the appropriate move instruction | |
1501 | |
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1502 // Support for fast byte/short loading with zero extension (depending on particular CPU) |
0 | 1503 int load_unsigned_byte(Register dst, Address src); |
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1504 int load_unsigned_short(Register dst, Address src); |
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1505 |
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1506 // Support for fast byte/short loading with sign extension (depending on particular CPU) |
0 | 1507 int load_signed_byte(Register dst, Address src); |
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1508 int load_signed_short(Register dst, Address src); |
0 | 1509 |
1510 // Support for sign-extension (hi:lo = extend_sign(lo)) | |
1511 void extend_sign(Register hi, Register lo); | |
1512 | |
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1513 // Loading values by size and signed-ness |
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1514 void load_sized_value(Register dst, Address src, int size_in_bytes, bool is_signed); |
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1515 |
0 | 1516 // Support for inc/dec with optimal instruction selection depending on value |
304 | 1517 |
1518 void increment(Register reg, int value = 1) { LP64_ONLY(incrementq(reg, value)) NOT_LP64(incrementl(reg, value)) ; } | |
1519 void decrement(Register reg, int value = 1) { LP64_ONLY(decrementq(reg, value)) NOT_LP64(decrementl(reg, value)) ; } | |
1520 | |
1521 void decrementl(Address dst, int value = 1); | |
1522 void decrementl(Register reg, int value = 1); | |
1523 | |
1524 void decrementq(Register reg, int value = 1); | |
1525 void decrementq(Address dst, int value = 1); | |
1526 | |
1527 void incrementl(Address dst, int value = 1); | |
1528 void incrementl(Register reg, int value = 1); | |
1529 | |
1530 void incrementq(Register reg, int value = 1); | |
1531 void incrementq(Address dst, int value = 1); | |
1532 | |
0 | 1533 |
1534 // Support optimal SSE move instructions. | |
1535 void movflt(XMMRegister dst, XMMRegister src) { | |
1536 if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; } | |
1537 else { movss (dst, src); return; } | |
1538 } | |
1539 void movflt(XMMRegister dst, Address src) { movss(dst, src); } | |
1540 void movflt(XMMRegister dst, AddressLiteral src); | |
1541 void movflt(Address dst, XMMRegister src) { movss(dst, src); } | |
1542 | |
1543 void movdbl(XMMRegister dst, XMMRegister src) { | |
1544 if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; } | |
1545 else { movsd (dst, src); return; } | |
1546 } | |
1547 | |
1548 void movdbl(XMMRegister dst, AddressLiteral src); | |
1549 | |
1550 void movdbl(XMMRegister dst, Address src) { | |
1551 if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; } | |
1552 else { movlpd(dst, src); return; } | |
1553 } | |
1554 void movdbl(Address dst, XMMRegister src) { movsd(dst, src); } | |
1555 | |
304 | 1556 void incrementl(AddressLiteral dst); |
1557 void incrementl(ArrayAddress dst); | |
0 | 1558 |
1559 // Alignment | |
1560 void align(int modulus); | |
1561 | |
1562 // Misc | |
1563 void fat_nop(); // 5 byte nop | |
1564 | |
1565 // Stack frame creation/removal | |
1566 void enter(); | |
1567 void leave(); | |
1568 | |
1569 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information) | |
1570 // The pointer will be loaded into the thread register. | |
1571 void get_thread(Register thread); | |
1572 | |
362 | 1573 |
0 | 1574 // Support for VM calls |
1575 // | |
1576 // It is imperative that all calls into the VM are handled via the call_VM macros. | |
1577 // They make sure that the stack linkage is setup correctly. call_VM's correspond | |
1578 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points. | |
1579 | |
304 | 1580 |
1581 void call_VM(Register oop_result, | |
1582 address entry_point, | |
1583 bool check_exceptions = true); | |
1584 void call_VM(Register oop_result, | |
1585 address entry_point, | |
1586 Register arg_1, | |
1587 bool check_exceptions = true); | |
1588 void call_VM(Register oop_result, | |
1589 address entry_point, | |
1590 Register arg_1, Register arg_2, | |
1591 bool check_exceptions = true); | |
1592 void call_VM(Register oop_result, | |
1593 address entry_point, | |
1594 Register arg_1, Register arg_2, Register arg_3, | |
1595 bool check_exceptions = true); | |
1596 | |
1597 // Overloadings with last_Java_sp | |
1598 void call_VM(Register oop_result, | |
1599 Register last_java_sp, | |
1600 address entry_point, | |
1601 int number_of_arguments = 0, | |
1602 bool check_exceptions = true); | |
1603 void call_VM(Register oop_result, | |
1604 Register last_java_sp, | |
1605 address entry_point, | |
1606 Register arg_1, bool | |
1607 check_exceptions = true); | |
1608 void call_VM(Register oop_result, | |
1609 Register last_java_sp, | |
1610 address entry_point, | |
1611 Register arg_1, Register arg_2, | |
1612 bool check_exceptions = true); | |
1613 void call_VM(Register oop_result, | |
1614 Register last_java_sp, | |
1615 address entry_point, | |
1616 Register arg_1, Register arg_2, Register arg_3, | |
1617 bool check_exceptions = true); | |
1618 | |
1619 void call_VM_leaf(address entry_point, | |
1620 int number_of_arguments = 0); | |
1621 void call_VM_leaf(address entry_point, | |
1622 Register arg_1); | |
1623 void call_VM_leaf(address entry_point, | |
1624 Register arg_1, Register arg_2); | |
1625 void call_VM_leaf(address entry_point, | |
1626 Register arg_1, Register arg_2, Register arg_3); | |
0 | 1627 |
1628 // last Java Frame (fills frame anchor) | |
304 | 1629 void set_last_Java_frame(Register thread, |
1630 Register last_java_sp, | |
1631 Register last_java_fp, | |
1632 address last_java_pc); | |
1633 | |
1634 // thread in the default location (r15_thread on 64bit) | |
1635 void set_last_Java_frame(Register last_java_sp, | |
1636 Register last_java_fp, | |
1637 address last_java_pc); | |
1638 | |
0 | 1639 void reset_last_Java_frame(Register thread, bool clear_fp, bool clear_pc); |
1640 | |
304 | 1641 // thread in the default location (r15_thread on 64bit) |
1642 void reset_last_Java_frame(bool clear_fp, bool clear_pc); | |
1643 | |
0 | 1644 // Stores |
1645 void store_check(Register obj); // store check for obj - register is destroyed afterwards | |
1646 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed) | |
1647 | |
362 | 1648 void g1_write_barrier_pre(Register obj, |
1649 #ifndef _LP64 | |
1650 Register thread, | |
1651 #endif | |
1652 Register tmp, | |
1653 Register tmp2, | |
1654 bool tosca_live); | |
1655 void g1_write_barrier_post(Register store_addr, | |
1656 Register new_val, | |
1657 #ifndef _LP64 | |
1658 Register thread, | |
1659 #endif | |
1660 Register tmp, | |
1661 Register tmp2); | |
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1662 |
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1663 |
0 | 1664 // split store_check(Register obj) to enhance instruction interleaving |
1665 void store_check_part_1(Register obj); | |
1666 void store_check_part_2(Register obj); | |
1667 | |
1668 // C 'boolean' to Java boolean: x == 0 ? 0 : 1 | |
1669 void c2bool(Register x); | |
1670 | |
1671 // C++ bool manipulation | |
1672 | |
1673 void movbool(Register dst, Address src); | |
1674 void movbool(Address dst, bool boolconst); | |
1675 void movbool(Address dst, Register src); | |
1676 void testbool(Register dst); | |
1677 | |
304 | 1678 // oop manipulations |
1679 void load_klass(Register dst, Register src); | |
1680 void store_klass(Register dst, Register src); | |
1681 | |
1682 void load_prototype_header(Register dst, Register src); | |
1683 | |
1684 #ifdef _LP64 | |
1685 void store_klass_gap(Register dst, Register src); | |
1686 | |
1687 void load_heap_oop(Register dst, Address src); | |
1688 void store_heap_oop(Address dst, Register src); | |
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1689 |
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1690 // This dummy is to prevent a call to store_heap_oop from |
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1691 // converting a zero (like NULL) into a Register by giving |
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1692 // the compiler two choices it can't resolve |
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1693 |
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1694 void store_heap_oop(Address dst, void* dummy); |
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1695 |
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1696 // Used for storing NULL. All other oop constants should be |
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1697 // stored using routines that take a jobject. |
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1698 void store_heap_oop_null(Address dst); |
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1699 |
304 | 1700 void encode_heap_oop(Register r); |
1701 void decode_heap_oop(Register r); | |
1702 void encode_heap_oop_not_null(Register r); | |
1703 void decode_heap_oop_not_null(Register r); | |
1704 void encode_heap_oop_not_null(Register dst, Register src); | |
1705 void decode_heap_oop_not_null(Register dst, Register src); | |
1706 | |
1707 void set_narrow_oop(Register dst, jobject obj); | |
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1708 void set_narrow_oop(Address dst, jobject obj); |
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1709 void cmp_narrow_oop(Register dst, jobject obj); |
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1710 void cmp_narrow_oop(Address dst, jobject obj); |
304 | 1711 |
1712 // if heap base register is used - reinit it with the correct value | |
1713 void reinit_heapbase(); | |
1714 #endif // _LP64 | |
1715 | |
1716 // Int division/remainder for Java | |
0 | 1717 // (as idivl, but checks for special case as described in JVM spec.) |
1718 // returns idivl instruction offset for implicit exception handling | |
1719 int corrected_idivl(Register reg); | |
1720 | |
304 | 1721 // Long division/remainder for Java |
1722 // (as idivq, but checks for special case as described in JVM spec.) | |
1723 // returns idivq instruction offset for implicit exception handling | |
1724 int corrected_idivq(Register reg); | |
1725 | |
0 | 1726 void int3(); |
1727 | |
304 | 1728 // Long operation macros for a 32bit cpu |
0 | 1729 // Long negation for Java |
1730 void lneg(Register hi, Register lo); | |
1731 | |
1732 // Long multiplication for Java | |
304 | 1733 // (destroys contents of eax, ebx, ecx and edx) |
0 | 1734 void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y |
1735 | |
1736 // Long shifts for Java | |
1737 // (semantics as described in JVM spec.) | |
1738 void lshl(Register hi, Register lo); // hi:lo << (rcx & 0x3f) | |
1739 void lshr(Register hi, Register lo, bool sign_extension = false); // hi:lo >> (rcx & 0x3f) | |
1740 | |
1741 // Long compare for Java | |
1742 // (semantics as described in JVM spec.) | |
1743 void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y) | |
1744 | |
304 | 1745 |
1746 // misc | |
1747 | |
1748 // Sign extension | |
1749 void sign_extend_short(Register reg); | |
1750 void sign_extend_byte(Register reg); | |
1751 | |
1752 // Division by power of 2, rounding towards 0 | |
1753 void division_with_shift(Register reg, int shift_value); | |
1754 | |
0 | 1755 // Compares the top-most stack entries on the FPU stack and sets the eflags as follows: |
1756 // | |
1757 // CF (corresponds to C0) if x < y | |
1758 // PF (corresponds to C2) if unordered | |
1759 // ZF (corresponds to C3) if x = y | |
1760 // | |
1761 // The arguments are in reversed order on the stack (i.e., top of stack is first argument). | |
1762 // tmp is a temporary register, if none is available use noreg (only matters for non-P6 code) | |
1763 void fcmp(Register tmp); | |
1764 // Variant of the above which allows y to be further down the stack | |
1765 // and which only pops x and y if specified. If pop_right is | |
1766 // specified then pop_left must also be specified. | |
1767 void fcmp(Register tmp, int index, bool pop_left, bool pop_right); | |
1768 | |
1769 // Floating-point comparison for Java | |
1770 // Compares the top-most stack entries on the FPU stack and stores the result in dst. | |
1771 // The arguments are in reversed order on the stack (i.e., top of stack is first argument). | |
1772 // (semantics as described in JVM spec.) | |
1773 void fcmp2int(Register dst, bool unordered_is_less); | |
1774 // Variant of the above which allows y to be further down the stack | |
1775 // and which only pops x and y if specified. If pop_right is | |
1776 // specified then pop_left must also be specified. | |
1777 void fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right); | |
1778 | |
1779 // Floating-point remainder for Java (ST0 = ST0 fremr ST1, ST1 is empty afterwards) | |
1780 // tmp is a temporary register, if none is available use noreg | |
1781 void fremr(Register tmp); | |
1782 | |
1783 | |
1784 // same as fcmp2int, but using SSE2 | |
1785 void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less); | |
1786 void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less); | |
1787 | |
1788 // Inlined sin/cos generator for Java; must not use CPU instruction | |
1789 // directly on Intel as it does not have high enough precision | |
1790 // outside of the range [-pi/4, pi/4]. Extra argument indicate the | |
1791 // number of FPU stack slots in use; all but the topmost will | |
1792 // require saving if a slow case is necessary. Assumes argument is | |
1793 // on FP TOS; result is on FP TOS. No cpu registers are changed by | |
1794 // this code. | |
1795 void trigfunc(char trig, int num_fpu_regs_in_use = 1); | |
1796 | |
1797 // branch to L if FPU flag C2 is set/not set | |
1798 // tmp is a temporary register, if none is available use noreg | |
1799 void jC2 (Register tmp, Label& L); | |
1800 void jnC2(Register tmp, Label& L); | |
1801 | |
1802 // Pop ST (ffree & fincstp combined) | |
1803 void fpop(); | |
1804 | |
1805 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack | |
1806 void push_fTOS(); | |
1807 | |
1808 // pops double TOS element from CPU stack and pushes on FPU stack | |
1809 void pop_fTOS(); | |
1810 | |
1811 void empty_FPU_stack(); | |
1812 | |
1813 void push_IU_state(); | |
1814 void pop_IU_state(); | |
1815 | |
1816 void push_FPU_state(); | |
1817 void pop_FPU_state(); | |
1818 | |
1819 void push_CPU_state(); | |
1820 void pop_CPU_state(); | |
1821 | |
1822 // Round up to a power of two | |
1823 void round_to(Register reg, int modulus); | |
1824 | |
1825 // Callee saved registers handling | |
1826 void push_callee_saved_registers(); | |
1827 void pop_callee_saved_registers(); | |
1828 | |
1829 // allocation | |
1830 void eden_allocate( | |
1831 Register obj, // result: pointer to object after successful allocation | |
1832 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise | |
1833 int con_size_in_bytes, // object size in bytes if known at compile time | |
1834 Register t1, // temp register | |
1835 Label& slow_case // continuation point if fast allocation fails | |
1836 ); | |
1837 void tlab_allocate( | |
1838 Register obj, // result: pointer to object after successful allocation | |
1839 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise | |
1840 int con_size_in_bytes, // object size in bytes if known at compile time | |
1841 Register t1, // temp register | |
1842 Register t2, // temp register | |
1843 Label& slow_case // continuation point if fast allocation fails | |
1844 ); | |
1845 void tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case); | |
1846 | |
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1847 // interface method calling |
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1848 void lookup_interface_method(Register recv_klass, |
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1849 Register intf_klass, |
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1850 RegisterOrConstant itable_index, |
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1851 Register method_result, |
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1852 Register scan_temp, |
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1853 Label& no_such_interface); |
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1854 |
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1855 // Test sub_klass against super_klass, with fast and slow paths. |
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1856 |
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1857 // The fast path produces a tri-state answer: yes / no / maybe-slow. |
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1858 // One of the three labels can be NULL, meaning take the fall-through. |
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1859 // If super_check_offset is -1, the value is loaded up from super_klass. |
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1860 // No registers are killed, except temp_reg. |
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1861 void check_klass_subtype_fast_path(Register sub_klass, |
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1862 Register super_klass, |
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1863 Register temp_reg, |
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1864 Label* L_success, |
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1865 Label* L_failure, |
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1866 Label* L_slow_path, |
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1867 RegisterOrConstant super_check_offset = RegisterOrConstant(-1)); |
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1868 |
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1869 // The rest of the type check; must be wired to a corresponding fast path. |
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1870 // It does not repeat the fast path logic, so don't use it standalone. |
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1871 // The temp_reg and temp2_reg can be noreg, if no temps are available. |
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1872 // Updates the sub's secondary super cache as necessary. |
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1873 // If set_cond_codes, condition codes will be Z on success, NZ on failure. |
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1874 void check_klass_subtype_slow_path(Register sub_klass, |
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1875 Register super_klass, |
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1876 Register temp_reg, |
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1877 Register temp2_reg, |
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1878 Label* L_success, |
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1879 Label* L_failure, |
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1880 bool set_cond_codes = false); |
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1881 |
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1882 // Simplified, combined version, good for typical uses. |
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1883 // Falls through on failure. |
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1884 void check_klass_subtype(Register sub_klass, |
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1885 Register super_klass, |
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1886 Register temp_reg, |
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1887 Label& L_success); |
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1888 |
710 | 1889 // method handles (JSR 292) |
1890 void check_method_handle_type(Register mtype_reg, Register mh_reg, | |
1891 Register temp_reg, | |
1892 Label& wrong_method_type); | |
1893 void load_method_handle_vmslots(Register vmslots_reg, Register mh_reg, | |
1894 Register temp_reg); | |
1895 void jump_to_method_handle_entry(Register mh_reg, Register temp_reg); | |
1896 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0); | |
1897 | |
1898 | |
0 | 1899 //---- |
1900 void set_word_if_not_zero(Register reg); // sets reg to 1 if not zero, otherwise 0 | |
1901 | |
1902 // Debugging | |
304 | 1903 |
1904 // only if +VerifyOops | |
1905 void verify_oop(Register reg, const char* s = "broken oop"); | |
0 | 1906 void verify_oop_addr(Address addr, const char * s = "broken oop addr"); |
1907 | |
304 | 1908 // only if +VerifyFPU |
1909 void verify_FPU(int stack_depth, const char* s = "illegal FPU state"); | |
1910 | |
1911 // prints msg, dumps registers and stops execution | |
1912 void stop(const char* msg); | |
1913 | |
1914 // prints msg and continues | |
1915 void warn(const char* msg); | |
1916 | |
1917 static void debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg); | |
1918 static void debug64(char* msg, int64_t pc, int64_t regs[]); | |
1919 | |
0 | 1920 void os_breakpoint(); |
304 | 1921 |
0 | 1922 void untested() { stop("untested"); } |
304 | 1923 |
0 | 1924 void unimplemented(const char* what = "") { char* b = new char[1024]; jio_snprintf(b, sizeof(b), "unimplemented: %s", what); stop(b); } |
304 | 1925 |
0 | 1926 void should_not_reach_here() { stop("should not reach here"); } |
304 | 1927 |
0 | 1928 void print_CPU_state(); |
1929 | |
1930 // Stack overflow checking | |
1931 void bang_stack_with_offset(int offset) { | |
1932 // stack grows down, caller passes positive offset | |
1933 assert(offset > 0, "must bang with negative offset"); | |
1934 movl(Address(rsp, (-offset)), rax); | |
1935 } | |
1936 | |
1937 // Writes to stack successive pages until offset reached to check for | |
1938 // stack overflow + shadow pages. Also, clobbers tmp | |
1939 void bang_stack_size(Register size, Register tmp); | |
1940 | |
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1941 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr, |
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1942 Register tmp, |
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1943 int offset); |
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1944 |
0 | 1945 // Support for serializing memory accesses between threads |
1946 void serialize_memory(Register thread, Register tmp); | |
1947 | |
1948 void verify_tlab(); | |
1949 | |
1950 // Biased locking support | |
1951 // lock_reg and obj_reg must be loaded up with the appropriate values. | |
1952 // swap_reg must be rax, and is killed. | |
1953 // tmp_reg is optional. If it is supplied (i.e., != noreg) it will | |
1954 // be killed; if not supplied, push/pop will be used internally to | |
1955 // allocate a temporary (inefficient, avoid if possible). | |
1956 // Optional slow case is for implementations (interpreter and C1) which branch to | |
1957 // slow case directly. Leaves condition codes set for C2's Fast_Lock node. | |
1958 // Returns offset of first potentially-faulting instruction for null | |
1959 // check info (currently consumed only by C1). If | |
1960 // swap_reg_contains_mark is true then returns -1 as it is assumed | |
1961 // the calling code has already passed any potential faults. | |
420
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1962 int biased_locking_enter(Register lock_reg, Register obj_reg, |
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1963 Register swap_reg, Register tmp_reg, |
0 | 1964 bool swap_reg_contains_mark, |
1965 Label& done, Label* slow_case = NULL, | |
1966 BiasedLockingCounters* counters = NULL); | |
1967 void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done); | |
1968 | |
1969 | |
1970 Condition negate_condition(Condition cond); | |
1971 | |
1972 // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit | |
1973 // operands. In general the names are modified to avoid hiding the instruction in Assembler | |
1974 // so that we don't need to implement all the varieties in the Assembler with trivial wrappers | |
1975 // here in MacroAssembler. The major exception to this rule is call | |
1976 | |
1977 // Arithmetics | |
1978 | |
304 | 1979 |
1980 void addptr(Address dst, int32_t src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)) ; } | |
1981 void addptr(Address dst, Register src); | |
1982 | |
1983 void addptr(Register dst, Address src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); } | |
1984 void addptr(Register dst, int32_t src); | |
1985 void addptr(Register dst, Register src); | |
1986 | |
1987 void andptr(Register dst, int32_t src); | |
1988 void andptr(Register src1, Register src2) { LP64_ONLY(andq(src1, src2)) NOT_LP64(andl(src1, src2)) ; } | |
1989 | |
1990 void cmp8(AddressLiteral src1, int imm); | |
1991 | |
1992 // renamed to drag out the casting of address to int32_t/intptr_t | |
0 | 1993 void cmp32(Register src1, int32_t imm); |
1994 | |
1995 void cmp32(AddressLiteral src1, int32_t imm); | |
1996 // compare reg - mem, or reg - &mem | |
1997 void cmp32(Register src1, AddressLiteral src2); | |
1998 | |
1999 void cmp32(Register src1, Address src2); | |
2000 | |
304 | 2001 #ifndef _LP64 |
2002 void cmpoop(Address dst, jobject obj); | |
2003 void cmpoop(Register dst, jobject obj); | |
2004 #endif // _LP64 | |
2005 | |
0 | 2006 // NOTE src2 must be the lval. This is NOT an mem-mem compare |
2007 void cmpptr(Address src1, AddressLiteral src2); | |
2008 | |
2009 void cmpptr(Register src1, AddressLiteral src2); | |
2010 | |
304 | 2011 void cmpptr(Register src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } |
2012 void cmpptr(Register src1, Address src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } | |
2013 // void cmpptr(Address src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } | |
2014 | |
2015 void cmpptr(Register src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } | |
2016 void cmpptr(Address src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } | |
2017 | |
2018 // cmp64 to avoild hiding cmpq | |
2019 void cmp64(Register src1, AddressLiteral src); | |
2020 | |
2021 void cmpxchgptr(Register reg, Address adr); | |
2022 | |
2023 void locked_cmpxchgptr(Register reg, AddressLiteral adr); | |
2024 | |
2025 | |
2026 void imulptr(Register dst, Register src) { LP64_ONLY(imulq(dst, src)) NOT_LP64(imull(dst, src)); } | |
2027 | |
2028 | |
2029 void negptr(Register dst) { LP64_ONLY(negq(dst)) NOT_LP64(negl(dst)); } | |
2030 | |
2031 void notptr(Register dst) { LP64_ONLY(notq(dst)) NOT_LP64(notl(dst)); } | |
2032 | |
2033 void shlptr(Register dst, int32_t shift); | |
2034 void shlptr(Register dst) { LP64_ONLY(shlq(dst)) NOT_LP64(shll(dst)); } | |
2035 | |
2036 void shrptr(Register dst, int32_t shift); | |
2037 void shrptr(Register dst) { LP64_ONLY(shrq(dst)) NOT_LP64(shrl(dst)); } | |
2038 | |
2039 void sarptr(Register dst) { LP64_ONLY(sarq(dst)) NOT_LP64(sarl(dst)); } | |
2040 void sarptr(Register dst, int32_t src) { LP64_ONLY(sarq(dst, src)) NOT_LP64(sarl(dst, src)); } | |
2041 | |
2042 void subptr(Address dst, int32_t src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); } | |
2043 | |
2044 void subptr(Register dst, Address src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); } | |
2045 void subptr(Register dst, int32_t src); | |
2046 void subptr(Register dst, Register src); | |
2047 | |
2048 | |
2049 void sbbptr(Address dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); } | |
2050 void sbbptr(Register dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); } | |
2051 | |
2052 void xchgptr(Register src1, Register src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; } | |
2053 void xchgptr(Register src1, Address src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; } | |
2054 | |
2055 void xaddptr(Address src1, Register src2) { LP64_ONLY(xaddq(src1, src2)) NOT_LP64(xaddl(src1, src2)) ; } | |
2056 | |
2057 | |
0 | 2058 |
2059 // Helper functions for statistics gathering. | |
2060 // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes. | |
2061 void cond_inc32(Condition cond, AddressLiteral counter_addr); | |
2062 // Unconditional atomic increment. | |
2063 void atomic_incl(AddressLiteral counter_addr); | |
2064 | |
2065 void lea(Register dst, AddressLiteral adr); | |
2066 void lea(Address dst, AddressLiteral adr); | |
304 | 2067 void lea(Register dst, Address adr) { Assembler::lea(dst, adr); } |
2068 | |
2069 void leal32(Register dst, Address src) { leal(dst, src); } | |
2070 | |
2071 void test32(Register src1, AddressLiteral src2); | |
2072 | |
2073 void orptr(Register dst, Address src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); } | |
2074 void orptr(Register dst, Register src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); } | |
2075 void orptr(Register dst, int32_t src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); } | |
2076 | |
2077 void testptr(Register src, int32_t imm32) { LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); } | |
2078 void testptr(Register src1, Register src2); | |
2079 | |
2080 void xorptr(Register dst, Register src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); } | |
2081 void xorptr(Register dst, Address src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); } | |
0 | 2082 |
2083 // Calls | |
2084 | |
2085 void call(Label& L, relocInfo::relocType rtype); | |
2086 void call(Register entry); | |
2087 | |
2088 // NOTE: this call tranfers to the effective address of entry NOT | |
2089 // the address contained by entry. This is because this is more natural | |
2090 // for jumps/calls. | |
2091 void call(AddressLiteral entry); | |
2092 | |
2093 // Jumps | |
2094 | |
2095 // NOTE: these jumps tranfer to the effective address of dst NOT | |
2096 // the address contained by dst. This is because this is more natural | |
2097 // for jumps/calls. | |
2098 void jump(AddressLiteral dst); | |
2099 void jump_cc(Condition cc, AddressLiteral dst); | |
2100 | |
2101 // 32bit can do a case table jump in one instruction but we no longer allow the base | |
2102 // to be installed in the Address class. This jump will tranfers to the address | |
2103 // contained in the location described by entry (not the address of entry) | |
2104 void jump(ArrayAddress entry); | |
2105 | |
2106 // Floating | |
2107 | |
2108 void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); } | |
2109 void andpd(XMMRegister dst, AddressLiteral src); | |
2110 | |
2111 void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); } | |
2112 void comiss(XMMRegister dst, AddressLiteral src); | |
2113 | |
2114 void comisd(XMMRegister dst, Address src) { Assembler::comisd(dst, src); } | |
2115 void comisd(XMMRegister dst, AddressLiteral src); | |
2116 | |
2117 void fldcw(Address src) { Assembler::fldcw(src); } | |
2118 void fldcw(AddressLiteral src); | |
2119 | |
2120 void fld_s(int index) { Assembler::fld_s(index); } | |
2121 void fld_s(Address src) { Assembler::fld_s(src); } | |
2122 void fld_s(AddressLiteral src); | |
2123 | |
2124 void fld_d(Address src) { Assembler::fld_d(src); } | |
2125 void fld_d(AddressLiteral src); | |
2126 | |
2127 void fld_x(Address src) { Assembler::fld_x(src); } | |
2128 void fld_x(AddressLiteral src); | |
2129 | |
2130 void ldmxcsr(Address src) { Assembler::ldmxcsr(src); } | |
2131 void ldmxcsr(AddressLiteral src); | |
2132 | |
304 | 2133 private: |
2134 // these are private because users should be doing movflt/movdbl | |
2135 | |
0 | 2136 void movss(Address dst, XMMRegister src) { Assembler::movss(dst, src); } |
2137 void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); } | |
2138 void movss(XMMRegister dst, Address src) { Assembler::movss(dst, src); } | |
2139 void movss(XMMRegister dst, AddressLiteral src); | |
2140 | |
304 | 2141 void movlpd(XMMRegister dst, Address src) {Assembler::movlpd(dst, src); } |
2142 void movlpd(XMMRegister dst, AddressLiteral src); | |
2143 | |
2144 public: | |
2145 | |
0 | 2146 void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); } |
2147 void movsd(Address dst, XMMRegister src) { Assembler::movsd(dst, src); } | |
2148 void movsd(XMMRegister dst, Address src) { Assembler::movsd(dst, src); } | |
2149 void movsd(XMMRegister dst, AddressLiteral src); | |
2150 | |
2151 void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); } | |
2152 void ucomiss(XMMRegister dst, Address src) { Assembler::ucomiss(dst, src); } | |
2153 void ucomiss(XMMRegister dst, AddressLiteral src); | |
2154 | |
2155 void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); } | |
2156 void ucomisd(XMMRegister dst, Address src) { Assembler::ucomisd(dst, src); } | |
2157 void ucomisd(XMMRegister dst, AddressLiteral src); | |
2158 | |
2159 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values | |
2160 void xorpd(XMMRegister dst, XMMRegister src) { Assembler::xorpd(dst, src); } | |
2161 void xorpd(XMMRegister dst, Address src) { Assembler::xorpd(dst, src); } | |
2162 void xorpd(XMMRegister dst, AddressLiteral src); | |
2163 | |
2164 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values | |
2165 void xorps(XMMRegister dst, XMMRegister src) { Assembler::xorps(dst, src); } | |
2166 void xorps(XMMRegister dst, Address src) { Assembler::xorps(dst, src); } | |
2167 void xorps(XMMRegister dst, AddressLiteral src); | |
2168 | |
2169 // Data | |
2170 | |
304 | 2171 void cmov(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmovl(cc, dst, src)); } |
2172 | |
2173 void cmovptr(Condition cc, Register dst, Address src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmovl(cc, dst, src)); } | |
2174 void cmovptr(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmovl(cc, dst, src)); } | |
2175 | |
0 | 2176 void movoop(Register dst, jobject obj); |
2177 void movoop(Address dst, jobject obj); | |
2178 | |
2179 void movptr(ArrayAddress dst, Register src); | |
2180 // can this do an lea? | |
2181 void movptr(Register dst, ArrayAddress src); | |
2182 | |
304 | 2183 void movptr(Register dst, Address src); |
2184 | |
0 | 2185 void movptr(Register dst, AddressLiteral src); |
2186 | |
304 | 2187 void movptr(Register dst, intptr_t src); |
2188 void movptr(Register dst, Register src); | |
2189 void movptr(Address dst, intptr_t src); | |
2190 | |
2191 void movptr(Address dst, Register src); | |
2192 | |
2193 #ifdef _LP64 | |
2194 // Generally the next two are only used for moving NULL | |
2195 // Although there are situations in initializing the mark word where | |
2196 // they could be used. They are dangerous. | |
2197 | |
2198 // They only exist on LP64 so that int32_t and intptr_t are not the same | |
2199 // and we have ambiguous declarations. | |
2200 | |
2201 void movptr(Address dst, int32_t imm32); | |
2202 void movptr(Register dst, int32_t imm32); | |
2203 #endif // _LP64 | |
2204 | |
0 | 2205 // to avoid hiding movl |
2206 void mov32(AddressLiteral dst, Register src); | |
2207 void mov32(Register dst, AddressLiteral src); | |
304 | 2208 |
0 | 2209 // to avoid hiding movb |
2210 void movbyte(ArrayAddress dst, int src); | |
2211 | |
2212 // Can push value or effective address | |
2213 void pushptr(AddressLiteral src); | |
2214 | |
304 | 2215 void pushptr(Address src) { LP64_ONLY(pushq(src)) NOT_LP64(pushl(src)); } |
2216 void popptr(Address src) { LP64_ONLY(popq(src)) NOT_LP64(popl(src)); } | |
2217 | |
2218 void pushoop(jobject obj); | |
2219 | |
2220 // sign extend as need a l to ptr sized element | |
2221 void movl2ptr(Register dst, Address src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src)); } | |
2222 void movl2ptr(Register dst, Register src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(if (dst != src) movl(dst, src)); } | |
2223 | |
986
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2224 // IndexOf strings. |
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2225 void string_indexof(Register str1, Register str2, |
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2226 Register cnt1, Register cnt2, Register result, |
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2227 XMMRegister vec, Register tmp); |
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2228 |
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2229 // Compare strings. |
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2230 void string_compare(Register str1, Register str2, |
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2231 Register cnt1, Register cnt2, Register result, |
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2232 XMMRegister vec1, XMMRegister vec2); |
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2233 |
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2234 // Compare char[] arrays. |
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2235 void char_arrays_equals(bool is_array_equ, Register ary1, Register ary2, |
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2236 Register limit, Register result, Register chr, |
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2237 XMMRegister vec1, XMMRegister vec2); |
304 | 2238 |
0 | 2239 #undef VIRTUAL |
2240 | |
2241 }; | |
2242 | |
2243 /** | |
2244 * class SkipIfEqual: | |
2245 * | |
2246 * Instantiating this class will result in assembly code being output that will | |
2247 * jump around any code emitted between the creation of the instance and it's | |
2248 * automatic destruction at the end of a scope block, depending on the value of | |
2249 * the flag passed to the constructor, which will be checked at run-time. | |
2250 */ | |
2251 class SkipIfEqual { | |
2252 private: | |
2253 MacroAssembler* _masm; | |
2254 Label _label; | |
2255 | |
2256 public: | |
2257 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value); | |
2258 ~SkipIfEqual(); | |
2259 }; | |
2260 | |
2261 #ifdef ASSERT | |
2262 inline bool AbstractAssembler::pd_check_instruction_mark() { return true; } | |
2263 #endif |