Mercurial > hg > truffle
annotate src/cpu/x86/vm/vm_version_x86.cpp @ 2007:5ddfcf4b079e
7003554: (tiered) assert(is_null_object() || handle() != NULL) failed: cannot embed null pointer
Summary: C1 with profiling doesn't check whether the MDO has been really allocated, which can silently fail if the perm gen is full. The solution is to check if the allocation failed and bailout out of inlining or compilation.
Reviewed-by: kvn, never
author | iveresov |
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date | Thu, 02 Dec 2010 17:21:12 -0800 |
parents | f95d63e2154a |
children | 82de9bd880e3 |
rev | line source |
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585 | 1 /* |
1622 | 2 * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All Rights Reserved. |
585 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
4 * | |
5 * This code is free software; you can redistribute it and/or modify it | |
6 * under the terms of the GNU General Public License version 2 only, as | |
7 * published by the Free Software Foundation. | |
8 * | |
9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 * version 2 for more details (a copy is included in the LICENSE file that | |
13 * accompanied this code). | |
14 * | |
15 * You should have received a copy of the GNU General Public License version | |
16 * 2 along with this work; if not, write to the Free Software Foundation, | |
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
18 * | |
1552
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
585 | 22 * |
23 */ | |
24 | |
1972 | 25 #include "precompiled.hpp" |
26 #include "assembler_x86.inline.hpp" | |
27 #include "memory/resourceArea.hpp" | |
28 #include "runtime/java.hpp" | |
29 #include "runtime/stubCodeGenerator.hpp" | |
30 #include "vm_version_x86.hpp" | |
31 #ifdef TARGET_OS_FAMILY_linux | |
32 # include "os_linux.inline.hpp" | |
33 #endif | |
34 #ifdef TARGET_OS_FAMILY_solaris | |
35 # include "os_solaris.inline.hpp" | |
36 #endif | |
37 #ifdef TARGET_OS_FAMILY_windows | |
38 # include "os_windows.inline.hpp" | |
39 #endif | |
585 | 40 |
41 | |
42 int VM_Version::_cpu; | |
43 int VM_Version::_model; | |
44 int VM_Version::_stepping; | |
45 int VM_Version::_cpuFeatures; | |
46 const char* VM_Version::_features_str = ""; | |
47 VM_Version::CpuidInfo VM_Version::_cpuid_info = { 0, }; | |
48 | |
49 static BufferBlob* stub_blob; | |
1622 | 50 static const int stub_size = 400; |
585 | 51 |
52 extern "C" { | |
53 typedef void (*getPsrInfo_stub_t)(void*); | |
54 } | |
55 static getPsrInfo_stub_t getPsrInfo_stub = NULL; | |
56 | |
57 | |
58 class VM_Version_StubGenerator: public StubCodeGenerator { | |
59 public: | |
60 | |
61 VM_Version_StubGenerator(CodeBuffer *c) : StubCodeGenerator(c) {} | |
62 | |
63 address generate_getPsrInfo() { | |
64 // Flags to test CPU type. | |
65 const uint32_t EFL_AC = 0x40000; | |
66 const uint32_t EFL_ID = 0x200000; | |
67 // Values for when we don't have a CPUID instruction. | |
68 const int CPU_FAMILY_SHIFT = 8; | |
69 const uint32_t CPU_FAMILY_386 = (3 << CPU_FAMILY_SHIFT); | |
70 const uint32_t CPU_FAMILY_486 = (4 << CPU_FAMILY_SHIFT); | |
71 | |
1622 | 72 Label detect_486, cpu486, detect_586, std_cpuid1, std_cpuid4; |
585 | 73 Label ext_cpuid1, ext_cpuid5, done; |
74 | |
75 StubCodeMark mark(this, "VM_Version", "getPsrInfo_stub"); | |
76 # define __ _masm-> | |
77 | |
78 address start = __ pc(); | |
79 | |
80 // | |
81 // void getPsrInfo(VM_Version::CpuidInfo* cpuid_info); | |
82 // | |
83 // LP64: rcx and rdx are first and second argument registers on windows | |
84 | |
85 __ push(rbp); | |
86 #ifdef _LP64 | |
87 __ mov(rbp, c_rarg0); // cpuid_info address | |
88 #else | |
89 __ movptr(rbp, Address(rsp, 8)); // cpuid_info address | |
90 #endif | |
91 __ push(rbx); | |
92 __ push(rsi); | |
93 __ pushf(); // preserve rbx, and flags | |
94 __ pop(rax); | |
95 __ push(rax); | |
96 __ mov(rcx, rax); | |
97 // | |
98 // if we are unable to change the AC flag, we have a 386 | |
99 // | |
100 __ xorl(rax, EFL_AC); | |
101 __ push(rax); | |
102 __ popf(); | |
103 __ pushf(); | |
104 __ pop(rax); | |
105 __ cmpptr(rax, rcx); | |
106 __ jccb(Assembler::notEqual, detect_486); | |
107 | |
108 __ movl(rax, CPU_FAMILY_386); | |
109 __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax); | |
110 __ jmp(done); | |
111 | |
112 // | |
113 // If we are unable to change the ID flag, we have a 486 which does | |
114 // not support the "cpuid" instruction. | |
115 // | |
116 __ bind(detect_486); | |
117 __ mov(rax, rcx); | |
118 __ xorl(rax, EFL_ID); | |
119 __ push(rax); | |
120 __ popf(); | |
121 __ pushf(); | |
122 __ pop(rax); | |
123 __ cmpptr(rcx, rax); | |
124 __ jccb(Assembler::notEqual, detect_586); | |
125 | |
126 __ bind(cpu486); | |
127 __ movl(rax, CPU_FAMILY_486); | |
128 __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax); | |
129 __ jmp(done); | |
130 | |
131 // | |
132 // At this point, we have a chip which supports the "cpuid" instruction | |
133 // | |
134 __ bind(detect_586); | |
135 __ xorl(rax, rax); | |
136 __ cpuid(); | |
137 __ orl(rax, rax); | |
138 __ jcc(Assembler::equal, cpu486); // if cpuid doesn't support an input | |
139 // value of at least 1, we give up and | |
140 // assume a 486 | |
141 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); | |
142 __ movl(Address(rsi, 0), rax); | |
143 __ movl(Address(rsi, 4), rbx); | |
144 __ movl(Address(rsi, 8), rcx); | |
145 __ movl(Address(rsi,12), rdx); | |
146 | |
1622 | 147 __ cmpl(rax, 0xa); // Is cpuid(0xB) supported? |
148 __ jccb(Assembler::belowEqual, std_cpuid4); | |
149 | |
150 // | |
151 // cpuid(0xB) Processor Topology | |
152 // | |
153 __ movl(rax, 0xb); | |
154 __ xorl(rcx, rcx); // Threads level | |
155 __ cpuid(); | |
156 | |
157 __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB0_offset()))); | |
158 __ movl(Address(rsi, 0), rax); | |
159 __ movl(Address(rsi, 4), rbx); | |
160 __ movl(Address(rsi, 8), rcx); | |
161 __ movl(Address(rsi,12), rdx); | |
162 | |
163 __ movl(rax, 0xb); | |
164 __ movl(rcx, 1); // Cores level | |
165 __ cpuid(); | |
166 __ push(rax); | |
167 __ andl(rax, 0x1f); // Determine if valid topology level | |
168 __ orl(rax, rbx); // eax[4:0] | ebx[0:15] == 0 indicates invalid level | |
169 __ andl(rax, 0xffff); | |
170 __ pop(rax); | |
171 __ jccb(Assembler::equal, std_cpuid4); | |
172 | |
173 __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB1_offset()))); | |
174 __ movl(Address(rsi, 0), rax); | |
175 __ movl(Address(rsi, 4), rbx); | |
176 __ movl(Address(rsi, 8), rcx); | |
177 __ movl(Address(rsi,12), rdx); | |
178 | |
179 __ movl(rax, 0xb); | |
180 __ movl(rcx, 2); // Packages level | |
181 __ cpuid(); | |
182 __ push(rax); | |
183 __ andl(rax, 0x1f); // Determine if valid topology level | |
184 __ orl(rax, rbx); // eax[4:0] | ebx[0:15] == 0 indicates invalid level | |
185 __ andl(rax, 0xffff); | |
186 __ pop(rax); | |
187 __ jccb(Assembler::equal, std_cpuid4); | |
188 | |
189 __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB2_offset()))); | |
190 __ movl(Address(rsi, 0), rax); | |
191 __ movl(Address(rsi, 4), rbx); | |
192 __ movl(Address(rsi, 8), rcx); | |
193 __ movl(Address(rsi,12), rdx); | |
585 | 194 |
195 // | |
196 // cpuid(0x4) Deterministic cache params | |
197 // | |
1622 | 198 __ bind(std_cpuid4); |
585 | 199 __ movl(rax, 4); |
1622 | 200 __ cmpl(rax, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); // Is cpuid(0x4) supported? |
201 __ jccb(Assembler::greater, std_cpuid1); | |
202 | |
585 | 203 __ xorl(rcx, rcx); // L1 cache |
204 __ cpuid(); | |
205 __ push(rax); | |
206 __ andl(rax, 0x1f); // Determine if valid cache parameters used | |
207 __ orl(rax, rax); // eax[4:0] == 0 indicates invalid cache | |
208 __ pop(rax); | |
209 __ jccb(Assembler::equal, std_cpuid1); | |
210 | |
211 __ lea(rsi, Address(rbp, in_bytes(VM_Version::dcp_cpuid4_offset()))); | |
212 __ movl(Address(rsi, 0), rax); | |
213 __ movl(Address(rsi, 4), rbx); | |
214 __ movl(Address(rsi, 8), rcx); | |
215 __ movl(Address(rsi,12), rdx); | |
216 | |
217 // | |
218 // Standard cpuid(0x1) | |
219 // | |
220 __ bind(std_cpuid1); | |
221 __ movl(rax, 1); | |
222 __ cpuid(); | |
223 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset()))); | |
224 __ movl(Address(rsi, 0), rax); | |
225 __ movl(Address(rsi, 4), rbx); | |
226 __ movl(Address(rsi, 8), rcx); | |
227 __ movl(Address(rsi,12), rdx); | |
228 | |
229 __ movl(rax, 0x80000000); | |
230 __ cpuid(); | |
231 __ cmpl(rax, 0x80000000); // Is cpuid(0x80000001) supported? | |
232 __ jcc(Assembler::belowEqual, done); | |
233 __ cmpl(rax, 0x80000004); // Is cpuid(0x80000005) supported? | |
234 __ jccb(Assembler::belowEqual, ext_cpuid1); | |
235 __ cmpl(rax, 0x80000007); // Is cpuid(0x80000008) supported? | |
236 __ jccb(Assembler::belowEqual, ext_cpuid5); | |
237 // | |
238 // Extended cpuid(0x80000008) | |
239 // | |
240 __ movl(rax, 0x80000008); | |
241 __ cpuid(); | |
242 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid8_offset()))); | |
243 __ movl(Address(rsi, 0), rax); | |
244 __ movl(Address(rsi, 4), rbx); | |
245 __ movl(Address(rsi, 8), rcx); | |
246 __ movl(Address(rsi,12), rdx); | |
247 | |
248 // | |
249 // Extended cpuid(0x80000005) | |
250 // | |
251 __ bind(ext_cpuid5); | |
252 __ movl(rax, 0x80000005); | |
253 __ cpuid(); | |
254 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid5_offset()))); | |
255 __ movl(Address(rsi, 0), rax); | |
256 __ movl(Address(rsi, 4), rbx); | |
257 __ movl(Address(rsi, 8), rcx); | |
258 __ movl(Address(rsi,12), rdx); | |
259 | |
260 // | |
261 // Extended cpuid(0x80000001) | |
262 // | |
263 __ bind(ext_cpuid1); | |
264 __ movl(rax, 0x80000001); | |
265 __ cpuid(); | |
266 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid1_offset()))); | |
267 __ movl(Address(rsi, 0), rax); | |
268 __ movl(Address(rsi, 4), rbx); | |
269 __ movl(Address(rsi, 8), rcx); | |
270 __ movl(Address(rsi,12), rdx); | |
271 | |
272 // | |
273 // return | |
274 // | |
275 __ bind(done); | |
276 __ popf(); | |
277 __ pop(rsi); | |
278 __ pop(rbx); | |
279 __ pop(rbp); | |
280 __ ret(0); | |
281 | |
282 # undef __ | |
283 | |
284 return start; | |
285 }; | |
286 }; | |
287 | |
288 | |
289 void VM_Version::get_processor_features() { | |
290 | |
291 _cpu = 4; // 486 by default | |
292 _model = 0; | |
293 _stepping = 0; | |
294 _cpuFeatures = 0; | |
295 _logical_processors_per_package = 1; | |
296 | |
297 if (!Use486InstrsOnly) { | |
298 // Get raw processor info | |
299 getPsrInfo_stub(&_cpuid_info); | |
300 assert_is_initialized(); | |
301 _cpu = extended_cpu_family(); | |
302 _model = extended_cpu_model(); | |
303 _stepping = cpu_stepping(); | |
304 | |
305 if (cpu_family() > 4) { // it supports CPUID | |
306 _cpuFeatures = feature_flags(); | |
307 // Logical processors are only available on P4s and above, | |
308 // and only if hyperthreading is available. | |
309 _logical_processors_per_package = logical_processor_count(); | |
310 } | |
311 } | |
312 | |
313 _supports_cx8 = supports_cmpxchg8(); | |
314 | |
315 #ifdef _LP64 | |
316 // OS should support SSE for x64 and hardware should support at least SSE2. | |
317 if (!VM_Version::supports_sse2()) { | |
318 vm_exit_during_initialization("Unknown x64 processor: SSE2 not supported"); | |
319 } | |
1060 | 320 // in 64 bit the use of SSE2 is the minimum |
321 if (UseSSE < 2) UseSSE = 2; | |
585 | 322 #endif |
323 | |
324 // If the OS doesn't support SSE, we can't use this feature even if the HW does | |
325 if (!os::supports_sse()) | |
326 _cpuFeatures &= ~(CPU_SSE|CPU_SSE2|CPU_SSE3|CPU_SSSE3|CPU_SSE4A|CPU_SSE4_1|CPU_SSE4_2); | |
327 | |
328 if (UseSSE < 4) { | |
329 _cpuFeatures &= ~CPU_SSE4_1; | |
330 _cpuFeatures &= ~CPU_SSE4_2; | |
331 } | |
332 | |
333 if (UseSSE < 3) { | |
334 _cpuFeatures &= ~CPU_SSE3; | |
335 _cpuFeatures &= ~CPU_SSSE3; | |
336 _cpuFeatures &= ~CPU_SSE4A; | |
337 } | |
338 | |
339 if (UseSSE < 2) | |
340 _cpuFeatures &= ~CPU_SSE2; | |
341 | |
342 if (UseSSE < 1) | |
343 _cpuFeatures &= ~CPU_SSE; | |
344 | |
345 if (logical_processors_per_package() == 1) { | |
346 // HT processor could be installed on a system which doesn't support HT. | |
347 _cpuFeatures &= ~CPU_HT; | |
348 } | |
349 | |
350 char buf[256]; | |
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351 jio_snprintf(buf, sizeof(buf), "(%u cores per cpu, %u threads per core) family %d model %d stepping %d%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s", |
585 | 352 cores_per_cpu(), threads_per_core(), |
353 cpu_family(), _model, _stepping, | |
354 (supports_cmov() ? ", cmov" : ""), | |
355 (supports_cmpxchg8() ? ", cx8" : ""), | |
356 (supports_fxsr() ? ", fxsr" : ""), | |
357 (supports_mmx() ? ", mmx" : ""), | |
358 (supports_sse() ? ", sse" : ""), | |
359 (supports_sse2() ? ", sse2" : ""), | |
360 (supports_sse3() ? ", sse3" : ""), | |
361 (supports_ssse3()? ", ssse3": ""), | |
362 (supports_sse4_1() ? ", sse4.1" : ""), | |
363 (supports_sse4_2() ? ", sse4.2" : ""), | |
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364 (supports_popcnt() ? ", popcnt" : ""), |
585 | 365 (supports_mmx_ext() ? ", mmxext" : ""), |
366 (supports_3dnow() ? ", 3dnow" : ""), | |
367 (supports_3dnow2() ? ", 3dnowext" : ""), | |
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368 (supports_lzcnt() ? ", lzcnt": ""), |
585 | 369 (supports_sse4a() ? ", sse4a": ""), |
370 (supports_ht() ? ", ht": "")); | |
371 _features_str = strdup(buf); | |
372 | |
373 // UseSSE is set to the smaller of what hardware supports and what | |
374 // the command line requires. I.e., you cannot set UseSSE to 2 on | |
375 // older Pentiums which do not support it. | |
376 if( UseSSE > 4 ) UseSSE=4; | |
377 if( UseSSE < 0 ) UseSSE=0; | |
378 if( !supports_sse4_1() ) // Drop to 3 if no SSE4 support | |
379 UseSSE = MIN2((intx)3,UseSSE); | |
380 if( !supports_sse3() ) // Drop to 2 if no SSE3 support | |
381 UseSSE = MIN2((intx)2,UseSSE); | |
382 if( !supports_sse2() ) // Drop to 1 if no SSE2 support | |
383 UseSSE = MIN2((intx)1,UseSSE); | |
384 if( !supports_sse () ) // Drop to 0 if no SSE support | |
385 UseSSE = 0; | |
386 | |
387 // On new cpus instructions which update whole XMM register should be used | |
388 // to prevent partial register stall due to dependencies on high half. | |
389 // | |
390 // UseXmmLoadAndClearUpper == true --> movsd(xmm, mem) | |
391 // UseXmmLoadAndClearUpper == false --> movlpd(xmm, mem) | |
392 // UseXmmRegToRegMoveAll == true --> movaps(xmm, xmm), movapd(xmm, xmm). | |
393 // UseXmmRegToRegMoveAll == false --> movss(xmm, xmm), movsd(xmm, xmm). | |
394 | |
395 if( is_amd() ) { // AMD cpus specific settings | |
396 if( supports_sse2() && FLAG_IS_DEFAULT(UseAddressNop) ) { | |
397 // Use it on new AMD cpus starting from Opteron. | |
398 UseAddressNop = true; | |
399 } | |
400 if( supports_sse2() && FLAG_IS_DEFAULT(UseNewLongLShift) ) { | |
401 // Use it on new AMD cpus starting from Opteron. | |
402 UseNewLongLShift = true; | |
403 } | |
404 if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) { | |
405 if( supports_sse4a() ) { | |
406 UseXmmLoadAndClearUpper = true; // use movsd only on '10h' Opteron | |
407 } else { | |
408 UseXmmLoadAndClearUpper = false; | |
409 } | |
410 } | |
411 if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) { | |
412 if( supports_sse4a() ) { | |
413 UseXmmRegToRegMoveAll = true; // use movaps, movapd only on '10h' | |
414 } else { | |
415 UseXmmRegToRegMoveAll = false; | |
416 } | |
417 } | |
418 if( FLAG_IS_DEFAULT(UseXmmI2F) ) { | |
419 if( supports_sse4a() ) { | |
420 UseXmmI2F = true; | |
421 } else { | |
422 UseXmmI2F = false; | |
423 } | |
424 } | |
425 if( FLAG_IS_DEFAULT(UseXmmI2D) ) { | |
426 if( supports_sse4a() ) { | |
427 UseXmmI2D = true; | |
428 } else { | |
429 UseXmmI2D = false; | |
430 } | |
431 } | |
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432 |
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433 // Use count leading zeros count instruction if available. |
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434 if (supports_lzcnt()) { |
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435 if (FLAG_IS_DEFAULT(UseCountLeadingZerosInstruction)) { |
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436 UseCountLeadingZerosInstruction = true; |
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437 } |
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438 } |
585 | 439 } |
440 | |
441 if( is_intel() ) { // Intel cpus specific settings | |
442 if( FLAG_IS_DEFAULT(UseStoreImmI16) ) { | |
443 UseStoreImmI16 = false; // don't use it on Intel cpus | |
444 } | |
445 if( cpu_family() == 6 || cpu_family() == 15 ) { | |
446 if( FLAG_IS_DEFAULT(UseAddressNop) ) { | |
447 // Use it on all Intel cpus starting from PentiumPro | |
448 UseAddressNop = true; | |
449 } | |
450 } | |
451 if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) { | |
452 UseXmmLoadAndClearUpper = true; // use movsd on all Intel cpus | |
453 } | |
454 if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) { | |
455 if( supports_sse3() ) { | |
456 UseXmmRegToRegMoveAll = true; // use movaps, movapd on new Intel cpus | |
457 } else { | |
458 UseXmmRegToRegMoveAll = false; | |
459 } | |
460 } | |
461 if( cpu_family() == 6 && supports_sse3() ) { // New Intel cpus | |
462 #ifdef COMPILER2 | |
463 if( FLAG_IS_DEFAULT(MaxLoopPad) ) { | |
464 // For new Intel cpus do the next optimization: | |
465 // don't align the beginning of a loop if there are enough instructions | |
466 // left (NumberOfLoopInstrToAlign defined in c2_globals.hpp) | |
467 // in current fetch line (OptoLoopAlignment) or the padding | |
468 // is big (> MaxLoopPad). | |
469 // Set MaxLoopPad to 11 for new Intel cpus to reduce number of | |
470 // generated NOP instructions. 11 is the largest size of one | |
471 // address NOP instruction '0F 1F' (see Assembler::nop(i)). | |
472 MaxLoopPad = 11; | |
473 } | |
474 #endif // COMPILER2 | |
475 if( FLAG_IS_DEFAULT(UseXMMForArrayCopy) ) { | |
476 UseXMMForArrayCopy = true; // use SSE2 movq on new Intel cpus | |
477 } | |
478 if( supports_sse4_2() && supports_ht() ) { // Newest Intel cpus | |
479 if( FLAG_IS_DEFAULT(UseUnalignedLoadStores) && UseXMMForArrayCopy ) { | |
480 UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus | |
481 } | |
482 } | |
681 | 483 if( supports_sse4_2() && UseSSE >= 4 ) { |
484 if( FLAG_IS_DEFAULT(UseSSE42Intrinsics)) { | |
485 UseSSE42Intrinsics = true; | |
486 } | |
487 } | |
585 | 488 } |
489 } | |
490 | |
643
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491 // Use population count instruction if available. |
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492 if (supports_popcnt()) { |
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493 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) { |
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494 UsePopCountInstruction = true; |
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495 } |
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496 } |
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497 |
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498 #ifdef COMPILER2 |
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499 if (UseFPUForSpilling) { |
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500 if (UseSSE < 2) { |
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501 // Only supported with SSE2+ |
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502 FLAG_SET_DEFAULT(UseFPUForSpilling, false); |
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503 } |
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504 } |
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505 #endif |
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506 |
585 | 507 assert(0 <= ReadPrefetchInstr && ReadPrefetchInstr <= 3, "invalid value"); |
508 assert(0 <= AllocatePrefetchInstr && AllocatePrefetchInstr <= 3, "invalid value"); | |
509 | |
510 // set valid Prefetch instruction | |
511 if( ReadPrefetchInstr < 0 ) ReadPrefetchInstr = 0; | |
512 if( ReadPrefetchInstr > 3 ) ReadPrefetchInstr = 3; | |
513 if( ReadPrefetchInstr == 3 && !supports_3dnow() ) ReadPrefetchInstr = 0; | |
514 if( !supports_sse() && supports_3dnow() ) ReadPrefetchInstr = 3; | |
515 | |
516 if( AllocatePrefetchInstr < 0 ) AllocatePrefetchInstr = 0; | |
517 if( AllocatePrefetchInstr > 3 ) AllocatePrefetchInstr = 3; | |
518 if( AllocatePrefetchInstr == 3 && !supports_3dnow() ) AllocatePrefetchInstr=0; | |
519 if( !supports_sse() && supports_3dnow() ) AllocatePrefetchInstr = 3; | |
520 | |
521 // Allocation prefetch settings | |
522 intx cache_line_size = L1_data_cache_line_size(); | |
523 if( cache_line_size > AllocatePrefetchStepSize ) | |
524 AllocatePrefetchStepSize = cache_line_size; | |
525 if( FLAG_IS_DEFAULT(AllocatePrefetchLines) ) | |
526 AllocatePrefetchLines = 3; // Optimistic value | |
527 assert(AllocatePrefetchLines > 0, "invalid value"); | |
528 if( AllocatePrefetchLines < 1 ) // set valid value in product VM | |
529 AllocatePrefetchLines = 1; // Conservative value | |
530 | |
531 AllocatePrefetchDistance = allocate_prefetch_distance(); | |
532 AllocatePrefetchStyle = allocate_prefetch_style(); | |
533 | |
1622 | 534 if( is_intel() && cpu_family() == 6 && supports_sse3() ) { |
535 if( AllocatePrefetchStyle == 2 ) { // watermark prefetching on Core | |
585 | 536 #ifdef _LP64 |
1622 | 537 AllocatePrefetchDistance = 384; |
585 | 538 #else |
1622 | 539 AllocatePrefetchDistance = 320; |
585 | 540 #endif |
1622 | 541 } |
542 if( supports_sse4_2() && supports_ht() ) { // Nehalem based cpus | |
543 AllocatePrefetchDistance = 192; | |
544 AllocatePrefetchLines = 4; | |
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545 #ifdef COMPILER2 |
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546 if (AggressiveOpts && FLAG_IS_DEFAULT(UseFPUForSpilling)) { |
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547 FLAG_SET_DEFAULT(UseFPUForSpilling, true); |
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548 } |
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549 #endif |
1622 | 550 } |
585 | 551 } |
552 assert(AllocatePrefetchDistance % AllocatePrefetchStepSize == 0, "invalid value"); | |
553 | |
554 #ifdef _LP64 | |
555 // Prefetch settings | |
556 PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes(); | |
557 PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes(); | |
558 PrefetchFieldsAhead = prefetch_fields_ahead(); | |
559 #endif | |
560 | |
561 #ifndef PRODUCT | |
562 if (PrintMiscellaneous && Verbose) { | |
563 tty->print_cr("Logical CPUs per core: %u", | |
564 logical_processors_per_package()); | |
565 tty->print_cr("UseSSE=%d",UseSSE); | |
566 tty->print("Allocation: "); | |
567 if (AllocatePrefetchStyle <= 0 || UseSSE == 0 && !supports_3dnow()) { | |
568 tty->print_cr("no prefetching"); | |
569 } else { | |
570 if (UseSSE == 0 && supports_3dnow()) { | |
571 tty->print("PREFETCHW"); | |
572 } else if (UseSSE >= 1) { | |
573 if (AllocatePrefetchInstr == 0) { | |
574 tty->print("PREFETCHNTA"); | |
575 } else if (AllocatePrefetchInstr == 1) { | |
576 tty->print("PREFETCHT0"); | |
577 } else if (AllocatePrefetchInstr == 2) { | |
578 tty->print("PREFETCHT2"); | |
579 } else if (AllocatePrefetchInstr == 3) { | |
580 tty->print("PREFETCHW"); | |
581 } | |
582 } | |
583 if (AllocatePrefetchLines > 1) { | |
584 tty->print_cr(" %d, %d lines with step %d bytes", AllocatePrefetchDistance, AllocatePrefetchLines, AllocatePrefetchStepSize); | |
585 } else { | |
586 tty->print_cr(" %d, one line", AllocatePrefetchDistance); | |
587 } | |
588 } | |
589 | |
590 if (PrefetchCopyIntervalInBytes > 0) { | |
591 tty->print_cr("PrefetchCopyIntervalInBytes %d", PrefetchCopyIntervalInBytes); | |
592 } | |
593 if (PrefetchScanIntervalInBytes > 0) { | |
594 tty->print_cr("PrefetchScanIntervalInBytes %d", PrefetchScanIntervalInBytes); | |
595 } | |
596 if (PrefetchFieldsAhead > 0) { | |
597 tty->print_cr("PrefetchFieldsAhead %d", PrefetchFieldsAhead); | |
598 } | |
599 } | |
600 #endif // !PRODUCT | |
601 } | |
602 | |
603 void VM_Version::initialize() { | |
604 ResourceMark rm; | |
605 // Making this stub must be FIRST use of assembler | |
606 | |
607 stub_blob = BufferBlob::create("getPsrInfo_stub", stub_size); | |
608 if (stub_blob == NULL) { | |
609 vm_exit_during_initialization("Unable to allocate getPsrInfo_stub"); | |
610 } | |
1748 | 611 CodeBuffer c(stub_blob); |
585 | 612 VM_Version_StubGenerator g(&c); |
613 getPsrInfo_stub = CAST_TO_FN_PTR(getPsrInfo_stub_t, | |
614 g.generate_getPsrInfo()); | |
615 | |
616 get_processor_features(); | |
617 } |