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annotate graal/com.oracle.graal.lir.amd64/src/com/oracle/graal/lir/amd64/AMD64SignExtendOp.java @ 21708:6df25b1418be

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moved com.oracle.asm.** to jvmci-util.jar (JBS:GRAAL-53)
author Doug Simon <doug.simon@oracle.com>
date Wed, 03 Jun 2015 18:06:44 +0200
parents 5024c80224c7
children d915361cc3a1
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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89c729e9e0a4 Refactoring of AMD64 code generation.
Roland Schatz <roland.schatz@oracle.com>
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1 /*
89c729e9e0a4 Refactoring of AMD64 code generation.
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2 * Copyright (c) 2015, 2015, Oracle and/or its affiliates. All rights reserved.
89c729e9e0a4 Refactoring of AMD64 code generation.
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3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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4 *
89c729e9e0a4 Refactoring of AMD64 code generation.
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5 * This code is free software; you can redistribute it and/or modify it
89c729e9e0a4 Refactoring of AMD64 code generation.
Roland Schatz <roland.schatz@oracle.com>
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6 * under the terms of the GNU General Public License version 2 only, as
89c729e9e0a4 Refactoring of AMD64 code generation.
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7 * published by the Free Software Foundation.
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8 *
89c729e9e0a4 Refactoring of AMD64 code generation.
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9 * This code is distributed in the hope that it will be useful, but WITHOUT
89c729e9e0a4 Refactoring of AMD64 code generation.
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
89c729e9e0a4 Refactoring of AMD64 code generation.
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
89c729e9e0a4 Refactoring of AMD64 code generation.
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12 * version 2 for more details (a copy is included in the LICENSE file that
89c729e9e0a4 Refactoring of AMD64 code generation.
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13 * accompanied this code).
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14 *
89c729e9e0a4 Refactoring of AMD64 code generation.
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15 * You should have received a copy of the GNU General Public License version
89c729e9e0a4 Refactoring of AMD64 code generation.
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16 * 2 along with this work; if not, write to the Free Software Foundation,
89c729e9e0a4 Refactoring of AMD64 code generation.
Roland Schatz <roland.schatz@oracle.com>
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17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
89c729e9e0a4 Refactoring of AMD64 code generation.
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18 *
89c729e9e0a4 Refactoring of AMD64 code generation.
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
89c729e9e0a4 Refactoring of AMD64 code generation.
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20 * or visit www.oracle.com if you need additional information or have any
89c729e9e0a4 Refactoring of AMD64 code generation.
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21 * questions.
89c729e9e0a4 Refactoring of AMD64 code generation.
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22 */
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23 package com.oracle.graal.lir.amd64;
89c729e9e0a4 Refactoring of AMD64 code generation.
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24
21673
5024c80224c7 moved com.oracle.graal.[amd64|sparc] to com.oracle.jvmci.[amd64|sparc] (JBS:GRAAL-53)
Doug Simon <doug.simon@oracle.com>
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25 import com.oracle.jvmci.amd64.*;
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26 import com.oracle.jvmci.asm.amd64.*;
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27 import com.oracle.jvmci.asm.amd64.AMD64Assembler.*;
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48c1ebd24120 renamed com.oracle.graal.api[meta|code] modules to com.oracle.jvmci.[meta|code] (JBS:GRAAL-53)
Doug Simon <doug.simon@oracle.com>
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28 import com.oracle.jvmci.meta.AllocatableValue;
48c1ebd24120 renamed com.oracle.graal.api[meta|code] modules to com.oracle.jvmci.[meta|code] (JBS:GRAAL-53)
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29 import com.oracle.jvmci.meta.LIRKind;
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5024c80224c7 moved com.oracle.graal.[amd64|sparc] to com.oracle.jvmci.[amd64|sparc] (JBS:GRAAL-53)
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30
21708
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31 import static com.oracle.jvmci.asm.amd64.AMD64Assembler.OperandSize.*;
21556
48c1ebd24120 renamed com.oracle.graal.api[meta|code] modules to com.oracle.jvmci.[meta|code] (JBS:GRAAL-53)
Doug Simon <doug.simon@oracle.com>
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32 import static com.oracle.jvmci.code.ValueUtil.*;
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89c729e9e0a4 Refactoring of AMD64 code generation.
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33 import static com.oracle.graal.lir.LIRInstruction.OperandFlag.*;
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34
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35 import com.oracle.graal.lir.*;
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36 import com.oracle.graal.lir.asm.*;
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37
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38 @Opcode("CDQ")
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39 public class AMD64SignExtendOp extends AMD64LIRInstruction {
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40 public static final LIRInstructionClass<AMD64SignExtendOp> TYPE = LIRInstructionClass.create(AMD64SignExtendOp.class);
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41
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42 private final OperandSize size;
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43
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44 @Def({REG}) protected AllocatableValue highResult;
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45 @Def({REG}) protected AllocatableValue lowResult;
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46
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47 @Use({REG}) protected AllocatableValue input;
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48
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49 public AMD64SignExtendOp(OperandSize size, LIRKind resultKind, AllocatableValue input) {
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50 super(TYPE);
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51 this.size = size;
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52
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53 this.highResult = AMD64.rdx.asValue(resultKind);
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54 this.lowResult = AMD64.rax.asValue(resultKind);
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55 this.input = input;
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56 }
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57
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58 public AllocatableValue getHighResult() {
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59 return highResult;
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60 }
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61
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62 public AllocatableValue getLowResult() {
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63 return lowResult;
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64 }
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65
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66 @Override
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67 public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
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68 if (size == DWORD) {
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69 masm.cdql();
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70 } else {
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71 assert size == QWORD;
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72 masm.cdqq();
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73 }
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74 }
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75
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76 @Override
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77 public void verify() {
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78 assert asRegister(highResult).equals(AMD64.rdx);
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79 assert asRegister(lowResult).equals(AMD64.rax);
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80 assert asRegister(input).equals(AMD64.rax);
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81 }
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82 }