Mercurial > hg > truffle
annotate src/cpu/sparc/vm/sharedRuntime_sparc.cpp @ 4966:701a83c86f28
7120481: storeStore barrier in constructor with final field
Summary: Issue storestore barrier before constructor return if the constructor write final field.
Reviewed-by: dholmes, jrose, roland, coleenp
Contributed-by: Jiangli Zhou <jiangli.zhou@oracle.com>
author | jiangli |
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date | Tue, 21 Feb 2012 13:14:55 -0500 |
parents | 0382d2b469b2 |
children | 931e5f39e365 |
rev | line source |
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0 | 1 /* |
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2 * Copyright (c) 2003, 2012, Oracle and/or its affiliates. All rights reserved. |
0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
4 * | |
5 * This code is free software; you can redistribute it and/or modify it | |
6 * under the terms of the GNU General Public License version 2 only, as | |
7 * published by the Free Software Foundation. | |
8 * | |
9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 * version 2 for more details (a copy is included in the LICENSE file that | |
13 * accompanied this code). | |
14 * | |
15 * You should have received a copy of the GNU General Public License version | |
16 * 2 along with this work; if not, write to the Free Software Foundation, | |
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
18 * | |
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
0 | 22 * |
23 */ | |
24 | |
1972 | 25 #include "precompiled.hpp" |
26 #include "asm/assembler.hpp" | |
27 #include "assembler_sparc.inline.hpp" | |
28 #include "code/debugInfoRec.hpp" | |
29 #include "code/icBuffer.hpp" | |
30 #include "code/vtableStubs.hpp" | |
31 #include "interpreter/interpreter.hpp" | |
32 #include "oops/compiledICHolderOop.hpp" | |
33 #include "prims/jvmtiRedefineClassesTrace.hpp" | |
34 #include "runtime/sharedRuntime.hpp" | |
35 #include "runtime/vframeArray.hpp" | |
36 #include "vmreg_sparc.inline.hpp" | |
37 #ifdef COMPILER1 | |
38 #include "c1/c1_Runtime1.hpp" | |
39 #endif | |
40 #ifdef COMPILER2 | |
41 #include "opto/runtime.hpp" | |
42 #endif | |
43 #ifdef SHARK | |
44 #include "compiler/compileBroker.hpp" | |
45 #include "shark/sharkCompiler.hpp" | |
46 #endif | |
0 | 47 |
48 #define __ masm-> | |
49 | |
50 | |
51 class RegisterSaver { | |
52 | |
53 // Used for saving volatile registers. This is Gregs, Fregs, I/L/O. | |
54 // The Oregs are problematic. In the 32bit build the compiler can | |
55 // have O registers live with 64 bit quantities. A window save will | |
56 // cut the heads off of the registers. We have to do a very extensive | |
57 // stack dance to save and restore these properly. | |
58 | |
59 // Note that the Oregs problem only exists if we block at either a polling | |
60 // page exception a compiled code safepoint that was not originally a call | |
61 // or deoptimize following one of these kinds of safepoints. | |
62 | |
63 // Lots of registers to save. For all builds, a window save will preserve | |
64 // the %i and %l registers. For the 32-bit longs-in-two entries and 64-bit | |
65 // builds a window-save will preserve the %o registers. In the LION build | |
66 // we need to save the 64-bit %o registers which requires we save them | |
67 // before the window-save (as then they become %i registers and get their | |
68 // heads chopped off on interrupt). We have to save some %g registers here | |
69 // as well. | |
70 enum { | |
71 // This frame's save area. Includes extra space for the native call: | |
72 // vararg's layout space and the like. Briefly holds the caller's | |
73 // register save area. | |
74 call_args_area = frame::register_save_words_sp_offset + | |
75 frame::memory_parameter_word_sp_offset*wordSize, | |
76 // Make sure save locations are always 8 byte aligned. | |
77 // can't use round_to because it doesn't produce compile time constant | |
78 start_of_extra_save_area = ((call_args_area + 7) & ~7), | |
79 g1_offset = start_of_extra_save_area, // g-regs needing saving | |
80 g3_offset = g1_offset+8, | |
81 g4_offset = g3_offset+8, | |
82 g5_offset = g4_offset+8, | |
83 o0_offset = g5_offset+8, | |
84 o1_offset = o0_offset+8, | |
85 o2_offset = o1_offset+8, | |
86 o3_offset = o2_offset+8, | |
87 o4_offset = o3_offset+8, | |
88 o5_offset = o4_offset+8, | |
89 start_of_flags_save_area = o5_offset+8, | |
90 ccr_offset = start_of_flags_save_area, | |
91 fsr_offset = ccr_offset + 8, | |
92 d00_offset = fsr_offset+8, // Start of float save area | |
93 register_save_size = d00_offset+8*32 | |
94 }; | |
95 | |
96 | |
97 public: | |
98 | |
99 static int Oexception_offset() { return o0_offset; }; | |
100 static int G3_offset() { return g3_offset; }; | |
101 static int G5_offset() { return g5_offset; }; | |
102 static OopMap* save_live_registers(MacroAssembler* masm, int additional_frame_words, int* total_frame_words); | |
103 static void restore_live_registers(MacroAssembler* masm); | |
104 | |
105 // During deoptimization only the result register need to be restored | |
106 // all the other values have already been extracted. | |
107 | |
108 static void restore_result_registers(MacroAssembler* masm); | |
109 }; | |
110 | |
111 OopMap* RegisterSaver::save_live_registers(MacroAssembler* masm, int additional_frame_words, int* total_frame_words) { | |
112 // Record volatile registers as callee-save values in an OopMap so their save locations will be | |
113 // propagated to the caller frame's RegisterMap during StackFrameStream construction (needed for | |
114 // deoptimization; see compiledVFrame::create_stack_value). The caller's I, L and O registers | |
115 // are saved in register windows - I's and L's in the caller's frame and O's in the stub frame | |
116 // (as the stub's I's) when the runtime routine called by the stub creates its frame. | |
117 int i; | |
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118 // Always make the frame size 16 byte aligned. |
0 | 119 int frame_size = round_to(additional_frame_words + register_save_size, 16); |
120 // OopMap frame size is in c2 stack slots (sizeof(jint)) not bytes or words | |
121 int frame_size_in_slots = frame_size / sizeof(jint); | |
122 // CodeBlob frame size is in words. | |
123 *total_frame_words = frame_size / wordSize; | |
124 // OopMap* map = new OopMap(*total_frame_words, 0); | |
125 OopMap* map = new OopMap(frame_size_in_slots, 0); | |
126 | |
127 #if !defined(_LP64) | |
128 | |
129 // Save 64-bit O registers; they will get their heads chopped off on a 'save'. | |
130 __ stx(O0, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8); | |
131 __ stx(O1, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8); | |
132 __ stx(O2, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+2*8); | |
133 __ stx(O3, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+3*8); | |
134 __ stx(O4, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+4*8); | |
135 __ stx(O5, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+5*8); | |
136 #endif /* _LP64 */ | |
137 | |
138 __ save(SP, -frame_size, SP); | |
139 | |
140 #ifndef _LP64 | |
141 // Reload the 64 bit Oregs. Although they are now Iregs we load them | |
142 // to Oregs here to avoid interrupts cutting off their heads | |
143 | |
144 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8, O0); | |
145 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8, O1); | |
146 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+2*8, O2); | |
147 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+3*8, O3); | |
148 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+4*8, O4); | |
149 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+5*8, O5); | |
150 | |
151 __ stx(O0, SP, o0_offset+STACK_BIAS); | |
152 map->set_callee_saved(VMRegImpl::stack2reg((o0_offset + 4)>>2), O0->as_VMReg()); | |
153 | |
154 __ stx(O1, SP, o1_offset+STACK_BIAS); | |
155 | |
156 map->set_callee_saved(VMRegImpl::stack2reg((o1_offset + 4)>>2), O1->as_VMReg()); | |
157 | |
158 __ stx(O2, SP, o2_offset+STACK_BIAS); | |
159 map->set_callee_saved(VMRegImpl::stack2reg((o2_offset + 4)>>2), O2->as_VMReg()); | |
160 | |
161 __ stx(O3, SP, o3_offset+STACK_BIAS); | |
162 map->set_callee_saved(VMRegImpl::stack2reg((o3_offset + 4)>>2), O3->as_VMReg()); | |
163 | |
164 __ stx(O4, SP, o4_offset+STACK_BIAS); | |
165 map->set_callee_saved(VMRegImpl::stack2reg((o4_offset + 4)>>2), O4->as_VMReg()); | |
166 | |
167 __ stx(O5, SP, o5_offset+STACK_BIAS); | |
168 map->set_callee_saved(VMRegImpl::stack2reg((o5_offset + 4)>>2), O5->as_VMReg()); | |
169 #endif /* _LP64 */ | |
170 | |
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171 |
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172 #ifdef _LP64 |
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173 int debug_offset = 0; |
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174 #else |
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175 int debug_offset = 4; |
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176 #endif |
0 | 177 // Save the G's |
178 __ stx(G1, SP, g1_offset+STACK_BIAS); | |
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179 map->set_callee_saved(VMRegImpl::stack2reg((g1_offset + debug_offset)>>2), G1->as_VMReg()); |
0 | 180 |
181 __ stx(G3, SP, g3_offset+STACK_BIAS); | |
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182 map->set_callee_saved(VMRegImpl::stack2reg((g3_offset + debug_offset)>>2), G3->as_VMReg()); |
0 | 183 |
184 __ stx(G4, SP, g4_offset+STACK_BIAS); | |
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185 map->set_callee_saved(VMRegImpl::stack2reg((g4_offset + debug_offset)>>2), G4->as_VMReg()); |
0 | 186 |
187 __ stx(G5, SP, g5_offset+STACK_BIAS); | |
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188 map->set_callee_saved(VMRegImpl::stack2reg((g5_offset + debug_offset)>>2), G5->as_VMReg()); |
0 | 189 |
190 // This is really a waste but we'll keep things as they were for now | |
191 if (true) { | |
192 #ifndef _LP64 | |
193 map->set_callee_saved(VMRegImpl::stack2reg((o0_offset)>>2), O0->as_VMReg()->next()); | |
194 map->set_callee_saved(VMRegImpl::stack2reg((o1_offset)>>2), O1->as_VMReg()->next()); | |
195 map->set_callee_saved(VMRegImpl::stack2reg((o2_offset)>>2), O2->as_VMReg()->next()); | |
196 map->set_callee_saved(VMRegImpl::stack2reg((o3_offset)>>2), O3->as_VMReg()->next()); | |
197 map->set_callee_saved(VMRegImpl::stack2reg((o4_offset)>>2), O4->as_VMReg()->next()); | |
198 map->set_callee_saved(VMRegImpl::stack2reg((o5_offset)>>2), O5->as_VMReg()->next()); | |
199 map->set_callee_saved(VMRegImpl::stack2reg((g1_offset)>>2), G1->as_VMReg()->next()); | |
200 map->set_callee_saved(VMRegImpl::stack2reg((g3_offset)>>2), G3->as_VMReg()->next()); | |
201 map->set_callee_saved(VMRegImpl::stack2reg((g4_offset)>>2), G4->as_VMReg()->next()); | |
202 map->set_callee_saved(VMRegImpl::stack2reg((g5_offset)>>2), G5->as_VMReg()->next()); | |
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203 #endif /* _LP64 */ |
0 | 204 } |
205 | |
206 | |
207 // Save the flags | |
208 __ rdccr( G5 ); | |
209 __ stx(G5, SP, ccr_offset+STACK_BIAS); | |
210 __ stxfsr(SP, fsr_offset+STACK_BIAS); | |
211 | |
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212 // Save all the FP registers: 32 doubles (32 floats correspond to the 2 halves of the first 16 doubles) |
0 | 213 int offset = d00_offset; |
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214 for( int i=0; i<FloatRegisterImpl::number_of_registers; i+=2 ) { |
0 | 215 FloatRegister f = as_FloatRegister(i); |
216 __ stf(FloatRegisterImpl::D, f, SP, offset+STACK_BIAS); | |
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217 // Record as callee saved both halves of double registers (2 float registers). |
0 | 218 map->set_callee_saved(VMRegImpl::stack2reg(offset>>2), f->as_VMReg()); |
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219 map->set_callee_saved(VMRegImpl::stack2reg((offset + sizeof(float))>>2), f->as_VMReg()->next()); |
0 | 220 offset += sizeof(double); |
221 } | |
222 | |
223 // And we're done. | |
224 | |
225 return map; | |
226 } | |
227 | |
228 | |
229 // Pop the current frame and restore all the registers that we | |
230 // saved. | |
231 void RegisterSaver::restore_live_registers(MacroAssembler* masm) { | |
232 | |
233 // Restore all the FP registers | |
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234 for( int i=0; i<FloatRegisterImpl::number_of_registers; i+=2 ) { |
0 | 235 __ ldf(FloatRegisterImpl::D, SP, d00_offset+i*sizeof(float)+STACK_BIAS, as_FloatRegister(i)); |
236 } | |
237 | |
238 __ ldx(SP, ccr_offset+STACK_BIAS, G1); | |
239 __ wrccr (G1) ; | |
240 | |
241 // Restore the G's | |
242 // Note that G2 (AKA GThread) must be saved and restored separately. | |
243 // TODO-FIXME: save and restore some of the other ASRs, viz., %asi and %gsr. | |
244 | |
245 __ ldx(SP, g1_offset+STACK_BIAS, G1); | |
246 __ ldx(SP, g3_offset+STACK_BIAS, G3); | |
247 __ ldx(SP, g4_offset+STACK_BIAS, G4); | |
248 __ ldx(SP, g5_offset+STACK_BIAS, G5); | |
249 | |
250 | |
251 #if !defined(_LP64) | |
252 // Restore the 64-bit O's. | |
253 __ ldx(SP, o0_offset+STACK_BIAS, O0); | |
254 __ ldx(SP, o1_offset+STACK_BIAS, O1); | |
255 __ ldx(SP, o2_offset+STACK_BIAS, O2); | |
256 __ ldx(SP, o3_offset+STACK_BIAS, O3); | |
257 __ ldx(SP, o4_offset+STACK_BIAS, O4); | |
258 __ ldx(SP, o5_offset+STACK_BIAS, O5); | |
259 | |
260 // And temporarily place them in TLS | |
261 | |
262 __ stx(O0, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8); | |
263 __ stx(O1, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8); | |
264 __ stx(O2, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+2*8); | |
265 __ stx(O3, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+3*8); | |
266 __ stx(O4, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+4*8); | |
267 __ stx(O5, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+5*8); | |
268 #endif /* _LP64 */ | |
269 | |
270 // Restore flags | |
271 | |
272 __ ldxfsr(SP, fsr_offset+STACK_BIAS); | |
273 | |
274 __ restore(); | |
275 | |
276 #if !defined(_LP64) | |
277 // Now reload the 64bit Oregs after we've restore the window. | |
278 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8, O0); | |
279 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8, O1); | |
280 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+2*8, O2); | |
281 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+3*8, O3); | |
282 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+4*8, O4); | |
283 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+5*8, O5); | |
284 #endif /* _LP64 */ | |
285 | |
286 } | |
287 | |
288 // Pop the current frame and restore the registers that might be holding | |
289 // a result. | |
290 void RegisterSaver::restore_result_registers(MacroAssembler* masm) { | |
291 | |
292 #if !defined(_LP64) | |
293 // 32bit build returns longs in G1 | |
294 __ ldx(SP, g1_offset+STACK_BIAS, G1); | |
295 | |
296 // Retrieve the 64-bit O's. | |
297 __ ldx(SP, o0_offset+STACK_BIAS, O0); | |
298 __ ldx(SP, o1_offset+STACK_BIAS, O1); | |
299 // and save to TLS | |
300 __ stx(O0, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8); | |
301 __ stx(O1, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8); | |
302 #endif /* _LP64 */ | |
303 | |
304 __ ldf(FloatRegisterImpl::D, SP, d00_offset+STACK_BIAS, as_FloatRegister(0)); | |
305 | |
306 __ restore(); | |
307 | |
308 #if !defined(_LP64) | |
309 // Now reload the 64bit Oregs after we've restore the window. | |
310 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8, O0); | |
311 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8, O1); | |
312 #endif /* _LP64 */ | |
313 | |
314 } | |
315 | |
316 // The java_calling_convention describes stack locations as ideal slots on | |
317 // a frame with no abi restrictions. Since we must observe abi restrictions | |
318 // (like the placement of the register window) the slots must be biased by | |
319 // the following value. | |
320 static int reg2offset(VMReg r) { | |
321 return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size; | |
322 } | |
323 | |
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324 static VMRegPair reg64_to_VMRegPair(Register r) { |
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325 VMRegPair ret; |
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326 if (wordSize == 8) { |
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327 ret.set2(r->as_VMReg()); |
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328 } else { |
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329 ret.set_pair(r->successor()->as_VMReg(), r->as_VMReg()); |
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330 } |
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331 return ret; |
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332 } |
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333 |
0 | 334 // --------------------------------------------------------------------------- |
335 // Read the array of BasicTypes from a signature, and compute where the | |
336 // arguments should go. Values in the VMRegPair regs array refer to 4-byte (VMRegImpl::stack_slot_size) | |
337 // quantities. Values less than VMRegImpl::stack0 are registers, those above | |
338 // refer to 4-byte stack slots. All stack slots are based off of the window | |
339 // top. VMRegImpl::stack0 refers to the first slot past the 16-word window, | |
340 // and VMRegImpl::stack0+1 refers to the memory word 4-byes higher. Register | |
341 // values 0-63 (up to RegisterImpl::number_of_registers) are the 64-bit | |
342 // integer registers. Values 64-95 are the (32-bit only) float registers. | |
343 // Each 32-bit quantity is given its own number, so the integer registers | |
344 // (in either 32- or 64-bit builds) use 2 numbers. For example, there is | |
345 // an O0-low and an O0-high. Essentially, all int register numbers are doubled. | |
346 | |
347 // Register results are passed in O0-O5, for outgoing call arguments. To | |
348 // convert to incoming arguments, convert all O's to I's. The regs array | |
349 // refer to the low and hi 32-bit words of 64-bit registers or stack slots. | |
350 // If the regs[].second() field is set to VMRegImpl::Bad(), it means it's unused (a | |
351 // 32-bit value was passed). If both are VMRegImpl::Bad(), it means no value was | |
352 // passed (used as a placeholder for the other half of longs and doubles in | |
353 // the 64-bit build). regs[].second() is either VMRegImpl::Bad() or regs[].second() is | |
354 // regs[].first()+1 (regs[].first() may be misaligned in the C calling convention). | |
355 // Sparc never passes a value in regs[].second() but not regs[].first() (regs[].first() | |
356 // == VMRegImpl::Bad() && regs[].second() != VMRegImpl::Bad()) nor unrelated values in the | |
357 // same VMRegPair. | |
358 | |
359 // Note: the INPUTS in sig_bt are in units of Java argument words, which are | |
360 // either 32-bit or 64-bit depending on the build. The OUTPUTS are in 32-bit | |
361 // units regardless of build. | |
362 | |
363 | |
364 // --------------------------------------------------------------------------- | |
365 // The compiled Java calling convention. The Java convention always passes | |
366 // 64-bit values in adjacent aligned locations (either registers or stack), | |
367 // floats in float registers and doubles in aligned float pairs. Values are | |
368 // packed in the registers. There is no backing varargs store for values in | |
369 // registers. In the 32-bit build, longs are passed in G1 and G4 (cannot be | |
370 // passed in I's, because longs in I's get their heads chopped off at | |
371 // interrupt). | |
372 int SharedRuntime::java_calling_convention(const BasicType *sig_bt, | |
373 VMRegPair *regs, | |
374 int total_args_passed, | |
375 int is_outgoing) { | |
376 assert(F31->as_VMReg()->is_reg(), "overlapping stack/register numbers"); | |
377 | |
378 // Convention is to pack the first 6 int/oop args into the first 6 registers | |
379 // (I0-I5), extras spill to the stack. Then pack the first 8 float args | |
380 // into F0-F7, extras spill to the stack. Then pad all register sets to | |
381 // align. Then put longs and doubles into the same registers as they fit, | |
382 // else spill to the stack. | |
383 const int int_reg_max = SPARC_ARGS_IN_REGS_NUM; | |
384 const int flt_reg_max = 8; | |
385 // | |
386 // Where 32-bit 1-reg longs start being passed | |
387 // In tiered we must pass on stack because c1 can't use a "pair" in a single reg. | |
388 // So make it look like we've filled all the G regs that c2 wants to use. | |
389 Register g_reg = TieredCompilation ? noreg : G1; | |
390 | |
391 // Count int/oop and float args. See how many stack slots we'll need and | |
392 // where the longs & doubles will go. | |
393 int int_reg_cnt = 0; | |
394 int flt_reg_cnt = 0; | |
395 // int stk_reg_pairs = frame::register_save_words*(wordSize>>2); | |
396 // int stk_reg_pairs = SharedRuntime::out_preserve_stack_slots(); | |
397 int stk_reg_pairs = 0; | |
398 for (int i = 0; i < total_args_passed; i++) { | |
399 switch (sig_bt[i]) { | |
400 case T_LONG: // LP64, longs compete with int args | |
401 assert(sig_bt[i+1] == T_VOID, ""); | |
402 #ifdef _LP64 | |
403 if (int_reg_cnt < int_reg_max) int_reg_cnt++; | |
404 #endif | |
405 break; | |
406 case T_OBJECT: | |
407 case T_ARRAY: | |
408 case T_ADDRESS: // Used, e.g., in slow-path locking for the lock's stack address | |
409 if (int_reg_cnt < int_reg_max) int_reg_cnt++; | |
410 #ifndef _LP64 | |
411 else stk_reg_pairs++; | |
412 #endif | |
413 break; | |
414 case T_INT: | |
415 case T_SHORT: | |
416 case T_CHAR: | |
417 case T_BYTE: | |
418 case T_BOOLEAN: | |
419 if (int_reg_cnt < int_reg_max) int_reg_cnt++; | |
420 else stk_reg_pairs++; | |
421 break; | |
422 case T_FLOAT: | |
423 if (flt_reg_cnt < flt_reg_max) flt_reg_cnt++; | |
424 else stk_reg_pairs++; | |
425 break; | |
426 case T_DOUBLE: | |
427 assert(sig_bt[i+1] == T_VOID, ""); | |
428 break; | |
429 case T_VOID: | |
430 break; | |
431 default: | |
432 ShouldNotReachHere(); | |
433 } | |
434 } | |
435 | |
436 // This is where the longs/doubles start on the stack. | |
437 stk_reg_pairs = (stk_reg_pairs+1) & ~1; // Round | |
438 | |
439 int int_reg_pairs = (int_reg_cnt+1) & ~1; // 32-bit 2-reg longs only | |
440 int flt_reg_pairs = (flt_reg_cnt+1) & ~1; | |
441 | |
442 // int stk_reg = frame::register_save_words*(wordSize>>2); | |
443 // int stk_reg = SharedRuntime::out_preserve_stack_slots(); | |
444 int stk_reg = 0; | |
445 int int_reg = 0; | |
446 int flt_reg = 0; | |
447 | |
448 // Now do the signature layout | |
449 for (int i = 0; i < total_args_passed; i++) { | |
450 switch (sig_bt[i]) { | |
451 case T_INT: | |
452 case T_SHORT: | |
453 case T_CHAR: | |
454 case T_BYTE: | |
455 case T_BOOLEAN: | |
456 #ifndef _LP64 | |
457 case T_OBJECT: | |
458 case T_ARRAY: | |
459 case T_ADDRESS: // Used, e.g., in slow-path locking for the lock's stack address | |
460 #endif // _LP64 | |
461 if (int_reg < int_reg_max) { | |
462 Register r = is_outgoing ? as_oRegister(int_reg++) : as_iRegister(int_reg++); | |
463 regs[i].set1(r->as_VMReg()); | |
464 } else { | |
465 regs[i].set1(VMRegImpl::stack2reg(stk_reg++)); | |
466 } | |
467 break; | |
468 | |
469 #ifdef _LP64 | |
470 case T_OBJECT: | |
471 case T_ARRAY: | |
472 case T_ADDRESS: // Used, e.g., in slow-path locking for the lock's stack address | |
473 if (int_reg < int_reg_max) { | |
474 Register r = is_outgoing ? as_oRegister(int_reg++) : as_iRegister(int_reg++); | |
475 regs[i].set2(r->as_VMReg()); | |
476 } else { | |
477 regs[i].set2(VMRegImpl::stack2reg(stk_reg_pairs)); | |
478 stk_reg_pairs += 2; | |
479 } | |
480 break; | |
481 #endif // _LP64 | |
482 | |
483 case T_LONG: | |
484 assert(sig_bt[i+1] == T_VOID, "expecting VOID in other half"); | |
485 #ifdef _LP64 | |
486 if (int_reg < int_reg_max) { | |
487 Register r = is_outgoing ? as_oRegister(int_reg++) : as_iRegister(int_reg++); | |
488 regs[i].set2(r->as_VMReg()); | |
489 } else { | |
490 regs[i].set2(VMRegImpl::stack2reg(stk_reg_pairs)); | |
491 stk_reg_pairs += 2; | |
492 } | |
493 #else | |
304 | 494 #ifdef COMPILER2 |
0 | 495 // For 32-bit build, can't pass longs in O-regs because they become |
496 // I-regs and get trashed. Use G-regs instead. G1 and G4 are almost | |
497 // spare and available. This convention isn't used by the Sparc ABI or | |
498 // anywhere else. If we're tiered then we don't use G-regs because c1 | |
304 | 499 // can't deal with them as a "pair". (Tiered makes this code think g's are filled) |
0 | 500 // G0: zero |
501 // G1: 1st Long arg | |
502 // G2: global allocated to TLS | |
503 // G3: used in inline cache check | |
504 // G4: 2nd Long arg | |
505 // G5: used in inline cache check | |
506 // G6: used by OS | |
507 // G7: used by OS | |
508 | |
509 if (g_reg == G1) { | |
510 regs[i].set2(G1->as_VMReg()); // This long arg in G1 | |
511 g_reg = G4; // Where the next arg goes | |
512 } else if (g_reg == G4) { | |
513 regs[i].set2(G4->as_VMReg()); // The 2nd long arg in G4 | |
514 g_reg = noreg; // No more longs in registers | |
515 } else { | |
516 regs[i].set2(VMRegImpl::stack2reg(stk_reg_pairs)); | |
517 stk_reg_pairs += 2; | |
518 } | |
519 #else // COMPILER2 | |
520 if (int_reg_pairs + 1 < int_reg_max) { | |
521 if (is_outgoing) { | |
522 regs[i].set_pair(as_oRegister(int_reg_pairs + 1)->as_VMReg(), as_oRegister(int_reg_pairs)->as_VMReg()); | |
523 } else { | |
524 regs[i].set_pair(as_iRegister(int_reg_pairs + 1)->as_VMReg(), as_iRegister(int_reg_pairs)->as_VMReg()); | |
525 } | |
526 int_reg_pairs += 2; | |
527 } else { | |
528 regs[i].set2(VMRegImpl::stack2reg(stk_reg_pairs)); | |
529 stk_reg_pairs += 2; | |
530 } | |
531 #endif // COMPILER2 | |
304 | 532 #endif // _LP64 |
0 | 533 break; |
534 | |
535 case T_FLOAT: | |
536 if (flt_reg < flt_reg_max) regs[i].set1(as_FloatRegister(flt_reg++)->as_VMReg()); | |
537 else regs[i].set1( VMRegImpl::stack2reg(stk_reg++)); | |
538 break; | |
539 case T_DOUBLE: | |
540 assert(sig_bt[i+1] == T_VOID, "expecting half"); | |
541 if (flt_reg_pairs + 1 < flt_reg_max) { | |
542 regs[i].set2(as_FloatRegister(flt_reg_pairs)->as_VMReg()); | |
543 flt_reg_pairs += 2; | |
544 } else { | |
545 regs[i].set2(VMRegImpl::stack2reg(stk_reg_pairs)); | |
546 stk_reg_pairs += 2; | |
547 } | |
548 break; | |
549 case T_VOID: regs[i].set_bad(); break; // Halves of longs & doubles | |
550 default: | |
551 ShouldNotReachHere(); | |
552 } | |
553 } | |
554 | |
555 // retun the amount of stack space these arguments will need. | |
556 return stk_reg_pairs; | |
557 | |
558 } | |
559 | |
1006
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560 // Helper class mostly to avoid passing masm everywhere, and handle |
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561 // store displacement overflow logic. |
0 | 562 class AdapterGenerator { |
563 MacroAssembler *masm; | |
564 Register Rdisp; | |
565 void set_Rdisp(Register r) { Rdisp = r; } | |
566 | |
567 void patch_callers_callsite(); | |
568 | |
569 // base+st_off points to top of argument | |
1506 | 570 int arg_offset(const int st_off) { return st_off; } |
0 | 571 int next_arg_offset(const int st_off) { |
1506 | 572 return st_off - Interpreter::stackElementSize; |
1006
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573 } |
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574 |
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575 // Argument slot values may be loaded first into a register because |
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576 // they might not fit into displacement. |
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577 RegisterOrConstant arg_slot(const int st_off); |
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578 RegisterOrConstant next_arg_slot(const int st_off); |
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579 |
0 | 580 // Stores long into offset pointed to by base |
581 void store_c2i_long(Register r, Register base, | |
582 const int st_off, bool is_stack); | |
583 void store_c2i_object(Register r, Register base, | |
584 const int st_off); | |
585 void store_c2i_int(Register r, Register base, | |
586 const int st_off); | |
587 void store_c2i_double(VMReg r_2, | |
588 VMReg r_1, Register base, const int st_off); | |
589 void store_c2i_float(FloatRegister f, Register base, | |
590 const int st_off); | |
591 | |
592 public: | |
593 void gen_c2i_adapter(int total_args_passed, | |
594 // VMReg max_arg, | |
595 int comp_args_on_stack, // VMRegStackSlots | |
596 const BasicType *sig_bt, | |
597 const VMRegPair *regs, | |
598 Label& skip_fixup); | |
599 void gen_i2c_adapter(int total_args_passed, | |
600 // VMReg max_arg, | |
601 int comp_args_on_stack, // VMRegStackSlots | |
602 const BasicType *sig_bt, | |
603 const VMRegPair *regs); | |
604 | |
605 AdapterGenerator(MacroAssembler *_masm) : masm(_masm) {} | |
606 }; | |
607 | |
608 | |
609 // Patch the callers callsite with entry to compiled code if it exists. | |
610 void AdapterGenerator::patch_callers_callsite() { | |
611 Label L; | |
612 __ ld_ptr(G5_method, in_bytes(methodOopDesc::code_offset()), G3_scratch); | |
3839 | 613 __ br_null(G3_scratch, false, Assembler::pt, L); |
0 | 614 // Schedule the branch target address early. |
615 __ delayed()->ld_ptr(G5_method, in_bytes(methodOopDesc::interpreter_entry_offset()), G3_scratch); | |
616 // Call into the VM to patch the caller, then jump to compiled callee | |
617 __ save_frame(4); // Args in compiled layout; do not blow them | |
618 | |
619 // Must save all the live Gregs the list is: | |
620 // G1: 1st Long arg (32bit build) | |
621 // G2: global allocated to TLS | |
622 // G3: used in inline cache check (scratch) | |
623 // G4: 2nd Long arg (32bit build); | |
624 // G5: used in inline cache check (methodOop) | |
625 | |
626 // The longs must go to the stack by hand since in the 32 bit build they can be trashed by window ops. | |
627 | |
628 #ifdef _LP64 | |
629 // mov(s,d) | |
630 __ mov(G1, L1); | |
631 __ mov(G4, L4); | |
632 __ mov(G5_method, L5); | |
633 __ mov(G5_method, O0); // VM needs target method | |
634 __ mov(I7, O1); // VM needs caller's callsite | |
635 // Must be a leaf call... | |
636 // can be very far once the blob has been relocated | |
727 | 637 AddressLiteral dest(CAST_FROM_FN_PTR(address, SharedRuntime::fixup_callers_callsite)); |
0 | 638 __ relocate(relocInfo::runtime_call_type); |
727 | 639 __ jumpl_to(dest, O7, O7); |
0 | 640 __ delayed()->mov(G2_thread, L7_thread_cache); |
641 __ mov(L7_thread_cache, G2_thread); | |
642 __ mov(L1, G1); | |
643 __ mov(L4, G4); | |
644 __ mov(L5, G5_method); | |
645 #else | |
646 __ stx(G1, FP, -8 + STACK_BIAS); | |
647 __ stx(G4, FP, -16 + STACK_BIAS); | |
648 __ mov(G5_method, L5); | |
649 __ mov(G5_method, O0); // VM needs target method | |
650 __ mov(I7, O1); // VM needs caller's callsite | |
651 // Must be a leaf call... | |
652 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::fixup_callers_callsite), relocInfo::runtime_call_type); | |
653 __ delayed()->mov(G2_thread, L7_thread_cache); | |
654 __ mov(L7_thread_cache, G2_thread); | |
655 __ ldx(FP, -8 + STACK_BIAS, G1); | |
656 __ ldx(FP, -16 + STACK_BIAS, G4); | |
657 __ mov(L5, G5_method); | |
658 __ ld_ptr(G5_method, in_bytes(methodOopDesc::interpreter_entry_offset()), G3_scratch); | |
659 #endif /* _LP64 */ | |
660 | |
661 __ restore(); // Restore args | |
662 __ bind(L); | |
663 } | |
664 | |
1006
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665 |
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666 RegisterOrConstant AdapterGenerator::arg_slot(const int st_off) { |
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667 RegisterOrConstant roc(arg_offset(st_off)); |
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668 return __ ensure_simm13_or_reg(roc, Rdisp); |
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669 } |
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670 |
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671 RegisterOrConstant AdapterGenerator::next_arg_slot(const int st_off) { |
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672 RegisterOrConstant roc(next_arg_offset(st_off)); |
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673 return __ ensure_simm13_or_reg(roc, Rdisp); |
0 | 674 } |
675 | |
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676 |
0 | 677 // Stores long into offset pointed to by base |
678 void AdapterGenerator::store_c2i_long(Register r, Register base, | |
679 const int st_off, bool is_stack) { | |
680 #ifdef _LP64 | |
681 // In V9, longs are given 2 64-bit slots in the interpreter, but the | |
682 // data is passed in only 1 slot. | |
683 __ stx(r, base, next_arg_slot(st_off)); | |
684 #else | |
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685 #ifdef COMPILER2 |
0 | 686 // Misaligned store of 64-bit data |
687 __ stw(r, base, arg_slot(st_off)); // lo bits | |
688 __ srlx(r, 32, r); | |
689 __ stw(r, base, next_arg_slot(st_off)); // hi bits | |
690 #else | |
691 if (is_stack) { | |
692 // Misaligned store of 64-bit data | |
693 __ stw(r, base, arg_slot(st_off)); // lo bits | |
694 __ srlx(r, 32, r); | |
695 __ stw(r, base, next_arg_slot(st_off)); // hi bits | |
696 } else { | |
697 __ stw(r->successor(), base, arg_slot(st_off) ); // lo bits | |
698 __ stw(r , base, next_arg_slot(st_off)); // hi bits | |
699 } | |
700 #endif // COMPILER2 | |
342
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701 #endif // _LP64 |
0 | 702 } |
703 | |
704 void AdapterGenerator::store_c2i_object(Register r, Register base, | |
705 const int st_off) { | |
706 __ st_ptr (r, base, arg_slot(st_off)); | |
707 } | |
708 | |
709 void AdapterGenerator::store_c2i_int(Register r, Register base, | |
710 const int st_off) { | |
711 __ st (r, base, arg_slot(st_off)); | |
712 } | |
713 | |
714 // Stores into offset pointed to by base | |
715 void AdapterGenerator::store_c2i_double(VMReg r_2, | |
716 VMReg r_1, Register base, const int st_off) { | |
717 #ifdef _LP64 | |
718 // In V9, doubles are given 2 64-bit slots in the interpreter, but the | |
719 // data is passed in only 1 slot. | |
720 __ stf(FloatRegisterImpl::D, r_1->as_FloatRegister(), base, next_arg_slot(st_off)); | |
721 #else | |
722 // Need to marshal 64-bit value from misaligned Lesp loads | |
723 __ stf(FloatRegisterImpl::S, r_1->as_FloatRegister(), base, next_arg_slot(st_off)); | |
724 __ stf(FloatRegisterImpl::S, r_2->as_FloatRegister(), base, arg_slot(st_off) ); | |
725 #endif | |
726 } | |
727 | |
728 void AdapterGenerator::store_c2i_float(FloatRegister f, Register base, | |
729 const int st_off) { | |
730 __ stf(FloatRegisterImpl::S, f, base, arg_slot(st_off)); | |
731 } | |
732 | |
733 void AdapterGenerator::gen_c2i_adapter( | |
734 int total_args_passed, | |
735 // VMReg max_arg, | |
736 int comp_args_on_stack, // VMRegStackSlots | |
737 const BasicType *sig_bt, | |
738 const VMRegPair *regs, | |
739 Label& skip_fixup) { | |
740 | |
741 // Before we get into the guts of the C2I adapter, see if we should be here | |
742 // at all. We've come from compiled code and are attempting to jump to the | |
743 // interpreter, which means the caller made a static call to get here | |
744 // (vcalls always get a compiled target if there is one). Check for a | |
745 // compiled target. If there is one, we need to patch the caller's call. | |
746 // However we will run interpreted if we come thru here. The next pass | |
747 // thru the call site will run compiled. If we ran compiled here then | |
748 // we can (theorectically) do endless i2c->c2i->i2c transitions during | |
749 // deopt/uncommon trap cycles. If we always go interpreted here then | |
750 // we can have at most one and don't need to play any tricks to keep | |
751 // from endlessly growing the stack. | |
752 // | |
753 // Actually if we detected that we had an i2c->c2i transition here we | |
754 // ought to be able to reset the world back to the state of the interpreted | |
755 // call and not bother building another interpreter arg area. We don't | |
756 // do that at this point. | |
757 | |
758 patch_callers_callsite(); | |
759 | |
760 __ bind(skip_fixup); | |
761 | |
762 // Since all args are passed on the stack, total_args_passed*wordSize is the | |
763 // space we need. Add in varargs area needed by the interpreter. Round up | |
764 // to stack alignment. | |
1506 | 765 const int arg_size = total_args_passed * Interpreter::stackElementSize; |
0 | 766 const int varargs_area = |
767 (frame::varargs_offset - frame::register_save_words)*wordSize; | |
768 const int extraspace = round_to(arg_size + varargs_area, 2*wordSize); | |
769 | |
770 int bias = STACK_BIAS; | |
771 const int interp_arg_offset = frame::varargs_offset*wordSize + | |
1506 | 772 (total_args_passed-1)*Interpreter::stackElementSize; |
0 | 773 |
774 Register base = SP; | |
775 | |
776 #ifdef _LP64 | |
777 // In the 64bit build because of wider slots and STACKBIAS we can run | |
778 // out of bits in the displacement to do loads and stores. Use g3 as | |
779 // temporary displacement. | |
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780 if (!Assembler::is_simm13(extraspace)) { |
0 | 781 __ set(extraspace, G3_scratch); |
782 __ sub(SP, G3_scratch, SP); | |
783 } else { | |
784 __ sub(SP, extraspace, SP); | |
785 } | |
786 set_Rdisp(G3_scratch); | |
787 #else | |
788 __ sub(SP, extraspace, SP); | |
789 #endif // _LP64 | |
790 | |
791 // First write G1 (if used) to where ever it must go | |
792 for (int i=0; i<total_args_passed; i++) { | |
1506 | 793 const int st_off = interp_arg_offset - (i*Interpreter::stackElementSize) + bias; |
0 | 794 VMReg r_1 = regs[i].first(); |
795 VMReg r_2 = regs[i].second(); | |
796 if (r_1 == G1_scratch->as_VMReg()) { | |
797 if (sig_bt[i] == T_OBJECT || sig_bt[i] == T_ARRAY) { | |
798 store_c2i_object(G1_scratch, base, st_off); | |
799 } else if (sig_bt[i] == T_LONG) { | |
800 assert(!TieredCompilation, "should not use register args for longs"); | |
801 store_c2i_long(G1_scratch, base, st_off, false); | |
802 } else { | |
803 store_c2i_int(G1_scratch, base, st_off); | |
804 } | |
805 } | |
806 } | |
807 | |
808 // Now write the args into the outgoing interpreter space | |
809 for (int i=0; i<total_args_passed; i++) { | |
1506 | 810 const int st_off = interp_arg_offset - (i*Interpreter::stackElementSize) + bias; |
0 | 811 VMReg r_1 = regs[i].first(); |
812 VMReg r_2 = regs[i].second(); | |
813 if (!r_1->is_valid()) { | |
814 assert(!r_2->is_valid(), ""); | |
815 continue; | |
816 } | |
817 // Skip G1 if found as we did it first in order to free it up | |
818 if (r_1 == G1_scratch->as_VMReg()) { | |
819 continue; | |
820 } | |
821 #ifdef ASSERT | |
822 bool G1_forced = false; | |
823 #endif // ASSERT | |
824 if (r_1->is_stack()) { // Pretend stack targets are loaded into G1 | |
825 #ifdef _LP64 | |
826 Register ld_off = Rdisp; | |
827 __ set(reg2offset(r_1) + extraspace + bias, ld_off); | |
828 #else | |
829 int ld_off = reg2offset(r_1) + extraspace + bias; | |
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830 #endif // _LP64 |
0 | 831 #ifdef ASSERT |
832 G1_forced = true; | |
833 #endif // ASSERT | |
834 r_1 = G1_scratch->as_VMReg();// as part of the load/store shuffle | |
835 if (!r_2->is_valid()) __ ld (base, ld_off, G1_scratch); | |
836 else __ ldx(base, ld_off, G1_scratch); | |
837 } | |
838 | |
839 if (r_1->is_Register()) { | |
840 Register r = r_1->as_Register()->after_restore(); | |
841 if (sig_bt[i] == T_OBJECT || sig_bt[i] == T_ARRAY) { | |
842 store_c2i_object(r, base, st_off); | |
843 } else if (sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) { | |
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844 #ifndef _LP64 |
0 | 845 if (TieredCompilation) { |
846 assert(G1_forced || sig_bt[i] != T_LONG, "should not use register args for longs"); | |
847 } | |
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848 #endif // _LP64 |
0 | 849 store_c2i_long(r, base, st_off, r_2->is_stack()); |
850 } else { | |
851 store_c2i_int(r, base, st_off); | |
852 } | |
853 } else { | |
854 assert(r_1->is_FloatRegister(), ""); | |
855 if (sig_bt[i] == T_FLOAT) { | |
856 store_c2i_float(r_1->as_FloatRegister(), base, st_off); | |
857 } else { | |
858 assert(sig_bt[i] == T_DOUBLE, "wrong type"); | |
859 store_c2i_double(r_2, r_1, base, st_off); | |
860 } | |
861 } | |
862 } | |
863 | |
864 #ifdef _LP64 | |
865 // Need to reload G3_scratch, used for temporary displacements. | |
866 __ ld_ptr(G5_method, in_bytes(methodOopDesc::interpreter_entry_offset()), G3_scratch); | |
867 | |
868 // Pass O5_savedSP as an argument to the interpreter. | |
869 // The interpreter will restore SP to this value before returning. | |
870 __ set(extraspace, G1); | |
871 __ add(SP, G1, O5_savedSP); | |
872 #else | |
873 // Pass O5_savedSP as an argument to the interpreter. | |
874 // The interpreter will restore SP to this value before returning. | |
875 __ add(SP, extraspace, O5_savedSP); | |
876 #endif // _LP64 | |
877 | |
878 __ mov((frame::varargs_offset)*wordSize - | |
1506 | 879 1*Interpreter::stackElementSize+bias+BytesPerWord, G1); |
0 | 880 // Jump to the interpreter just as if interpreter was doing it. |
881 __ jmpl(G3_scratch, 0, G0); | |
882 // Setup Lesp for the call. Cannot actually set Lesp as the current Lesp | |
883 // (really L0) is in use by the compiled frame as a generic temp. However, | |
884 // the interpreter does not know where its args are without some kind of | |
885 // arg pointer being passed in. Pass it in Gargs. | |
886 __ delayed()->add(SP, G1, Gargs); | |
887 } | |
888 | |
889 void AdapterGenerator::gen_i2c_adapter( | |
890 int total_args_passed, | |
891 // VMReg max_arg, | |
892 int comp_args_on_stack, // VMRegStackSlots | |
893 const BasicType *sig_bt, | |
894 const VMRegPair *regs) { | |
895 | |
896 // Generate an I2C adapter: adjust the I-frame to make space for the C-frame | |
897 // layout. Lesp was saved by the calling I-frame and will be restored on | |
898 // return. Meanwhile, outgoing arg space is all owned by the callee | |
899 // C-frame, so we can mangle it at will. After adjusting the frame size, | |
900 // hoist register arguments and repack other args according to the compiled | |
901 // code convention. Finally, end in a jump to the compiled code. The entry | |
902 // point address is the start of the buffer. | |
903 | |
904 // We will only enter here from an interpreted frame and never from after | |
905 // passing thru a c2i. Azul allowed this but we do not. If we lose the | |
906 // race and use a c2i we will remain interpreted for the race loser(s). | |
907 // This removes all sorts of headaches on the x86 side and also eliminates | |
908 // the possibility of having c2i -> i2c -> c2i -> ... endless transitions. | |
909 | |
910 // As you can see from the list of inputs & outputs there are not a lot | |
911 // of temp registers to work with: mostly G1, G3 & G4. | |
912 | |
913 // Inputs: | |
914 // G2_thread - TLS | |
915 // G5_method - Method oop | |
710 | 916 // G4 (Gargs) - Pointer to interpreter's args |
917 // O0..O4 - free for scratch | |
918 // O5_savedSP - Caller's saved SP, to be restored if needed | |
0 | 919 // O6 - Current SP! |
920 // O7 - Valid return address | |
710 | 921 // L0-L7, I0-I7 - Caller's temps (no frame pushed yet) |
0 | 922 |
923 // Outputs: | |
924 // G2_thread - TLS | |
925 // G1, G4 - Outgoing long args in 32-bit build | |
926 // O0-O5 - Outgoing args in compiled layout | |
927 // O6 - Adjusted or restored SP | |
928 // O7 - Valid return address | |
1564 | 929 // L0-L7, I0-I7 - Caller's temps (no frame pushed yet) |
0 | 930 // F0-F7 - more outgoing args |
931 | |
932 | |
710 | 933 // Gargs is the incoming argument base, and also an outgoing argument. |
0 | 934 __ sub(Gargs, BytesPerWord, Gargs); |
935 | |
936 // ON ENTRY TO THE CODE WE ARE MAKING, WE HAVE AN INTERPRETED FRAME | |
937 // WITH O7 HOLDING A VALID RETURN PC | |
938 // | |
939 // | | | |
940 // : java stack : | |
941 // | | | |
942 // +--------------+ <--- start of outgoing args | |
943 // | receiver | | | |
944 // : rest of args : |---size is java-arg-words | |
945 // | | | | |
946 // +--------------+ <--- O4_args (misaligned) and Lesp if prior is not C2I | |
947 // | | | | |
948 // : unused : |---Space for max Java stack, plus stack alignment | |
949 // | | | | |
950 // +--------------+ <--- SP + 16*wordsize | |
951 // | | | |
952 // : window : | |
953 // | | | |
954 // +--------------+ <--- SP | |
955 | |
956 // WE REPACK THE STACK. We use the common calling convention layout as | |
957 // discovered by calling SharedRuntime::calling_convention. We assume it | |
958 // causes an arbitrary shuffle of memory, which may require some register | |
959 // temps to do the shuffle. We hope for (and optimize for) the case where | |
960 // temps are not needed. We may have to resize the stack slightly, in case | |
961 // we need alignment padding (32-bit interpreter can pass longs & doubles | |
962 // misaligned, but the compilers expect them aligned). | |
963 // | |
964 // | | | |
965 // : java stack : | |
966 // | | | |
967 // +--------------+ <--- start of outgoing args | |
968 // | pad, align | | | |
969 // +--------------+ | | |
970 // | ints, floats | |---Outgoing stack args, packed low. | |
971 // +--------------+ | First few args in registers. | |
972 // : doubles : | | |
973 // | longs | | | |
974 // +--------------+ <--- SP' + 16*wordsize | |
975 // | | | |
976 // : window : | |
977 // | | | |
978 // +--------------+ <--- SP' | |
979 | |
980 // ON EXIT FROM THE CODE WE ARE MAKING, WE STILL HAVE AN INTERPRETED FRAME | |
981 // WITH O7 HOLDING A VALID RETURN PC - ITS JUST THAT THE ARGS ARE NOW SETUP | |
982 // FOR COMPILED CODE AND THE FRAME SLIGHTLY GROWN. | |
983 | |
984 // Cut-out for having no stack args. Since up to 6 args are passed | |
985 // in registers, we will commonly have no stack args. | |
986 if (comp_args_on_stack > 0) { | |
987 | |
988 // Convert VMReg stack slots to words. | |
989 int comp_words_on_stack = round_to(comp_args_on_stack*VMRegImpl::stack_slot_size, wordSize)>>LogBytesPerWord; | |
990 // Round up to miminum stack alignment, in wordSize | |
991 comp_words_on_stack = round_to(comp_words_on_stack, 2); | |
992 // Now compute the distance from Lesp to SP. This calculation does not | |
993 // include the space for total_args_passed because Lesp has not yet popped | |
994 // the arguments. | |
995 __ sub(SP, (comp_words_on_stack)*wordSize, SP); | |
996 } | |
997 | |
998 // Will jump to the compiled code just as if compiled code was doing it. | |
999 // Pre-load the register-jump target early, to schedule it better. | |
1000 __ ld_ptr(G5_method, in_bytes(methodOopDesc::from_compiled_offset()), G3); | |
1001 | |
1002 // Now generate the shuffle code. Pick up all register args and move the | |
1003 // rest through G1_scratch. | |
1004 for (int i=0; i<total_args_passed; i++) { | |
1005 if (sig_bt[i] == T_VOID) { | |
1006 // Longs and doubles are passed in native word order, but misaligned | |
1007 // in the 32-bit build. | |
1008 assert(i > 0 && (sig_bt[i-1] == T_LONG || sig_bt[i-1] == T_DOUBLE), "missing half"); | |
1009 continue; | |
1010 } | |
1011 | |
1012 // Pick up 0, 1 or 2 words from Lesp+offset. Assume mis-aligned in the | |
1013 // 32-bit build and aligned in the 64-bit build. Look for the obvious | |
1014 // ldx/lddf optimizations. | |
1015 | |
1016 // Load in argument order going down. | |
1506 | 1017 const int ld_off = (total_args_passed-i)*Interpreter::stackElementSize; |
0 | 1018 set_Rdisp(G1_scratch); |
1019 | |
1020 VMReg r_1 = regs[i].first(); | |
1021 VMReg r_2 = regs[i].second(); | |
1022 if (!r_1->is_valid()) { | |
1023 assert(!r_2->is_valid(), ""); | |
1024 continue; | |
1025 } | |
1026 if (r_1->is_stack()) { // Pretend stack targets are loaded into F8/F9 | |
1027 r_1 = F8->as_VMReg(); // as part of the load/store shuffle | |
1028 if (r_2->is_valid()) r_2 = r_1->next(); | |
1029 } | |
1030 if (r_1->is_Register()) { // Register argument | |
1031 Register r = r_1->as_Register()->after_restore(); | |
1032 if (!r_2->is_valid()) { | |
1033 __ ld(Gargs, arg_slot(ld_off), r); | |
1034 } else { | |
1035 #ifdef _LP64 | |
1036 // In V9, longs are given 2 64-bit slots in the interpreter, but the | |
1037 // data is passed in only 1 slot. | |
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1038 RegisterOrConstant slot = (sig_bt[i] == T_LONG) ? |
0 | 1039 next_arg_slot(ld_off) : arg_slot(ld_off); |
1040 __ ldx(Gargs, slot, r); | |
1041 #else | |
1042 // Need to load a 64-bit value into G1/G4, but G1/G4 is being used in the | |
1043 // stack shuffle. Load the first 2 longs into G1/G4 later. | |
1044 #endif | |
1045 } | |
1046 } else { | |
1047 assert(r_1->is_FloatRegister(), ""); | |
1048 if (!r_2->is_valid()) { | |
1049 __ ldf(FloatRegisterImpl::S, Gargs, arg_slot(ld_off), r_1->as_FloatRegister()); | |
1050 } else { | |
1051 #ifdef _LP64 | |
1052 // In V9, doubles are given 2 64-bit slots in the interpreter, but the | |
1053 // data is passed in only 1 slot. This code also handles longs that | |
1054 // are passed on the stack, but need a stack-to-stack move through a | |
1055 // spare float register. | |
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1056 RegisterOrConstant slot = (sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) ? |
0 | 1057 next_arg_slot(ld_off) : arg_slot(ld_off); |
1058 __ ldf(FloatRegisterImpl::D, Gargs, slot, r_1->as_FloatRegister()); | |
1059 #else | |
1060 // Need to marshal 64-bit value from misaligned Lesp loads | |
1061 __ ldf(FloatRegisterImpl::S, Gargs, next_arg_slot(ld_off), r_1->as_FloatRegister()); | |
1062 __ ldf(FloatRegisterImpl::S, Gargs, arg_slot(ld_off), r_2->as_FloatRegister()); | |
1063 #endif | |
1064 } | |
1065 } | |
1066 // Was the argument really intended to be on the stack, but was loaded | |
1067 // into F8/F9? | |
1068 if (regs[i].first()->is_stack()) { | |
1069 assert(r_1->as_FloatRegister() == F8, "fix this code"); | |
1070 // Convert stack slot to an SP offset | |
1071 int st_off = reg2offset(regs[i].first()) + STACK_BIAS; | |
1072 // Store down the shuffled stack word. Target address _is_ aligned. | |
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1073 RegisterOrConstant slot = __ ensure_simm13_or_reg(st_off, Rdisp); |
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1074 if (!r_2->is_valid()) __ stf(FloatRegisterImpl::S, r_1->as_FloatRegister(), SP, slot); |
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1075 else __ stf(FloatRegisterImpl::D, r_1->as_FloatRegister(), SP, slot); |
0 | 1076 } |
1077 } | |
1078 bool made_space = false; | |
1079 #ifndef _LP64 | |
1080 // May need to pick up a few long args in G1/G4 | |
1081 bool g4_crushed = false; | |
1082 bool g3_crushed = false; | |
1083 for (int i=0; i<total_args_passed; i++) { | |
1084 if (regs[i].first()->is_Register() && regs[i].second()->is_valid()) { | |
1085 // Load in argument order going down | |
1506 | 1086 int ld_off = (total_args_passed-i)*Interpreter::stackElementSize; |
0 | 1087 // Need to marshal 64-bit value from misaligned Lesp loads |
1088 Register r = regs[i].first()->as_Register()->after_restore(); | |
1089 if (r == G1 || r == G4) { | |
1090 assert(!g4_crushed, "ordering problem"); | |
1091 if (r == G4){ | |
1092 g4_crushed = true; | |
1093 __ lduw(Gargs, arg_slot(ld_off) , G3_scratch); // Load lo bits | |
1094 __ ld (Gargs, next_arg_slot(ld_off), r); // Load hi bits | |
1095 } else { | |
1096 // better schedule this way | |
1097 __ ld (Gargs, next_arg_slot(ld_off), r); // Load hi bits | |
1098 __ lduw(Gargs, arg_slot(ld_off) , G3_scratch); // Load lo bits | |
1099 } | |
1100 g3_crushed = true; | |
1101 __ sllx(r, 32, r); | |
1102 __ or3(G3_scratch, r, r); | |
1103 } else { | |
1104 assert(r->is_out(), "longs passed in two O registers"); | |
1105 __ ld (Gargs, arg_slot(ld_off) , r->successor()); // Load lo bits | |
1106 __ ld (Gargs, next_arg_slot(ld_off), r); // Load hi bits | |
1107 } | |
1108 } | |
1109 } | |
1110 #endif | |
1111 | |
1112 // Jump to the compiled code just as if compiled code was doing it. | |
1113 // | |
1114 #ifndef _LP64 | |
1115 if (g3_crushed) { | |
1116 // Rats load was wasted, at least it is in cache... | |
727 | 1117 __ ld_ptr(G5_method, methodOopDesc::from_compiled_offset(), G3); |
0 | 1118 } |
1119 #endif /* _LP64 */ | |
1120 | |
1121 // 6243940 We might end up in handle_wrong_method if | |
1122 // the callee is deoptimized as we race thru here. If that | |
1123 // happens we don't want to take a safepoint because the | |
1124 // caller frame will look interpreted and arguments are now | |
1125 // "compiled" so it is much better to make this transition | |
1126 // invisible to the stack walking code. Unfortunately if | |
1127 // we try and find the callee by normal means a safepoint | |
1128 // is possible. So we stash the desired callee in the thread | |
1129 // and the vm will find there should this case occur. | |
727 | 1130 Address callee_target_addr(G2_thread, JavaThread::callee_target_offset()); |
0 | 1131 __ st_ptr(G5_method, callee_target_addr); |
1132 | |
1133 if (StressNonEntrant) { | |
1134 // Open a big window for deopt failure | |
1135 __ save_frame(0); | |
1136 __ mov(G0, L0); | |
1137 Label loop; | |
1138 __ bind(loop); | |
1139 __ sub(L0, 1, L0); | |
3839 | 1140 __ br_null_short(L0, Assembler::pt, loop); |
0 | 1141 |
1142 __ restore(); | |
1143 } | |
1144 | |
1145 | |
1146 __ jmpl(G3, 0, G0); | |
1147 __ delayed()->nop(); | |
1148 } | |
1149 | |
1150 // --------------------------------------------------------------- | |
1151 AdapterHandlerEntry* SharedRuntime::generate_i2c2i_adapters(MacroAssembler *masm, | |
1152 int total_args_passed, | |
1153 // VMReg max_arg, | |
1154 int comp_args_on_stack, // VMRegStackSlots | |
1155 const BasicType *sig_bt, | |
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1156 const VMRegPair *regs, |
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1157 AdapterFingerPrint* fingerprint) { |
0 | 1158 address i2c_entry = __ pc(); |
1159 | |
1160 AdapterGenerator agen(masm); | |
1161 | |
1162 agen.gen_i2c_adapter(total_args_passed, comp_args_on_stack, sig_bt, regs); | |
1163 | |
1164 | |
1165 // ------------------------------------------------------------------------- | |
1166 // Generate a C2I adapter. On entry we know G5 holds the methodOop. The | |
1167 // args start out packed in the compiled layout. They need to be unpacked | |
1168 // into the interpreter layout. This will almost always require some stack | |
1169 // space. We grow the current (compiled) stack, then repack the args. We | |
1170 // finally end in a jump to the generic interpreter entry point. On exit | |
1171 // from the interpreter, the interpreter will restore our SP (lest the | |
1172 // compiled code, which relys solely on SP and not FP, get sick). | |
1173 | |
1174 address c2i_unverified_entry = __ pc(); | |
1175 Label skip_fixup; | |
1176 { | |
1177 #if !defined(_LP64) && defined(COMPILER2) | |
1178 Register R_temp = L0; // another scratch register | |
1179 #else | |
1180 Register R_temp = G1; // another scratch register | |
1181 #endif | |
1182 | |
727 | 1183 AddressLiteral ic_miss(SharedRuntime::get_ic_miss_stub()); |
0 | 1184 |
1185 __ verify_oop(O0); | |
1186 __ verify_oop(G5_method); | |
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1187 __ load_klass(O0, G3_scratch); |
0 | 1188 __ verify_oop(G3_scratch); |
1189 | |
1190 #if !defined(_LP64) && defined(COMPILER2) | |
1191 __ save(SP, -frame::register_save_words*wordSize, SP); | |
1192 __ ld_ptr(G5_method, compiledICHolderOopDesc::holder_klass_offset(), R_temp); | |
1193 __ verify_oop(R_temp); | |
1194 __ cmp(G3_scratch, R_temp); | |
1195 __ restore(); | |
1196 #else | |
1197 __ ld_ptr(G5_method, compiledICHolderOopDesc::holder_klass_offset(), R_temp); | |
1198 __ verify_oop(R_temp); | |
1199 __ cmp(G3_scratch, R_temp); | |
1200 #endif | |
1201 | |
1202 Label ok, ok2; | |
1203 __ brx(Assembler::equal, false, Assembler::pt, ok); | |
1204 __ delayed()->ld_ptr(G5_method, compiledICHolderOopDesc::holder_method_offset(), G5_method); | |
727 | 1205 __ jump_to(ic_miss, G3_scratch); |
0 | 1206 __ delayed()->nop(); |
1207 | |
1208 __ bind(ok); | |
1209 // Method might have been compiled since the call site was patched to | |
1210 // interpreted if that is the case treat it as a miss so we can get | |
1211 // the call site corrected. | |
1212 __ ld_ptr(G5_method, in_bytes(methodOopDesc::code_offset()), G3_scratch); | |
1213 __ bind(ok2); | |
3839 | 1214 __ br_null(G3_scratch, false, Assembler::pt, skip_fixup); |
0 | 1215 __ delayed()->ld_ptr(G5_method, in_bytes(methodOopDesc::interpreter_entry_offset()), G3_scratch); |
727 | 1216 __ jump_to(ic_miss, G3_scratch); |
0 | 1217 __ delayed()->nop(); |
1218 | |
1219 } | |
1220 | |
1221 address c2i_entry = __ pc(); | |
1222 | |
1223 agen.gen_c2i_adapter(total_args_passed, comp_args_on_stack, sig_bt, regs, skip_fixup); | |
1224 | |
1225 __ flush(); | |
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1226 return AdapterHandlerLibrary::new_entry(fingerprint, i2c_entry, c2i_entry, c2i_unverified_entry); |
0 | 1227 |
1228 } | |
1229 | |
1230 // Helper function for native calling conventions | |
1231 static VMReg int_stk_helper( int i ) { | |
1232 // Bias any stack based VMReg we get by ignoring the window area | |
1233 // but not the register parameter save area. | |
1234 // | |
1235 // This is strange for the following reasons. We'd normally expect | |
1236 // the calling convention to return an VMReg for a stack slot | |
1237 // completely ignoring any abi reserved area. C2 thinks of that | |
1238 // abi area as only out_preserve_stack_slots. This does not include | |
1239 // the area allocated by the C abi to store down integer arguments | |
1240 // because the java calling convention does not use it. So | |
1241 // since c2 assumes that there are only out_preserve_stack_slots | |
1242 // to bias the optoregs (which impacts VMRegs) when actually referencing any actual stack | |
1243 // location the c calling convention must add in this bias amount | |
1244 // to make up for the fact that the out_preserve_stack_slots is | |
1245 // insufficient for C calls. What a mess. I sure hope those 6 | |
1246 // stack words were worth it on every java call! | |
1247 | |
1248 // Another way of cleaning this up would be for out_preserve_stack_slots | |
1249 // to take a parameter to say whether it was C or java calling conventions. | |
1250 // Then things might look a little better (but not much). | |
1251 | |
1252 int mem_parm_offset = i - SPARC_ARGS_IN_REGS_NUM; | |
1253 if( mem_parm_offset < 0 ) { | |
1254 return as_oRegister(i)->as_VMReg(); | |
1255 } else { | |
1256 int actual_offset = (mem_parm_offset + frame::memory_parameter_word_sp_offset) * VMRegImpl::slots_per_word; | |
1257 // Now return a biased offset that will be correct when out_preserve_slots is added back in | |
1258 return VMRegImpl::stack2reg(actual_offset - SharedRuntime::out_preserve_stack_slots()); | |
1259 } | |
1260 } | |
1261 | |
1262 | |
1263 int SharedRuntime::c_calling_convention(const BasicType *sig_bt, | |
1264 VMRegPair *regs, | |
1265 int total_args_passed) { | |
1266 | |
1267 // Return the number of VMReg stack_slots needed for the args. | |
1268 // This value does not include an abi space (like register window | |
1269 // save area). | |
1270 | |
1271 // The native convention is V8 if !LP64 | |
1272 // The LP64 convention is the V9 convention which is slightly more sane. | |
1273 | |
1274 // We return the amount of VMReg stack slots we need to reserve for all | |
1275 // the arguments NOT counting out_preserve_stack_slots. Since we always | |
1276 // have space for storing at least 6 registers to memory we start with that. | |
1277 // See int_stk_helper for a further discussion. | |
1278 int max_stack_slots = (frame::varargs_offset * VMRegImpl::slots_per_word) - SharedRuntime::out_preserve_stack_slots(); | |
1279 | |
1280 #ifdef _LP64 | |
1281 // V9 convention: All things "as-if" on double-wide stack slots. | |
1282 // Hoist any int/ptr/long's in the first 6 to int regs. | |
1283 // Hoist any flt/dbl's in the first 16 dbl regs. | |
1284 int j = 0; // Count of actual args, not HALVES | |
1285 for( int i=0; i<total_args_passed; i++, j++ ) { | |
1286 switch( sig_bt[i] ) { | |
1287 case T_BOOLEAN: | |
1288 case T_BYTE: | |
1289 case T_CHAR: | |
1290 case T_INT: | |
1291 case T_SHORT: | |
1292 regs[i].set1( int_stk_helper( j ) ); break; | |
1293 case T_LONG: | |
1294 assert( sig_bt[i+1] == T_VOID, "expecting half" ); | |
1295 case T_ADDRESS: // raw pointers, like current thread, for VM calls | |
1296 case T_ARRAY: | |
1297 case T_OBJECT: | |
1298 regs[i].set2( int_stk_helper( j ) ); | |
1299 break; | |
1300 case T_FLOAT: | |
1301 if ( j < 16 ) { | |
1302 // V9ism: floats go in ODD registers | |
1303 regs[i].set1(as_FloatRegister(1 + (j<<1))->as_VMReg()); | |
1304 } else { | |
1305 // V9ism: floats go in ODD stack slot | |
1306 regs[i].set1(VMRegImpl::stack2reg(1 + (j<<1))); | |
1307 } | |
1308 break; | |
1309 case T_DOUBLE: | |
1310 assert( sig_bt[i+1] == T_VOID, "expecting half" ); | |
1311 if ( j < 16 ) { | |
1312 // V9ism: doubles go in EVEN/ODD regs | |
1313 regs[i].set2(as_FloatRegister(j<<1)->as_VMReg()); | |
1314 } else { | |
1315 // V9ism: doubles go in EVEN/ODD stack slots | |
1316 regs[i].set2(VMRegImpl::stack2reg(j<<1)); | |
1317 } | |
1318 break; | |
1319 case T_VOID: regs[i].set_bad(); j--; break; // Do not count HALVES | |
1320 default: | |
1321 ShouldNotReachHere(); | |
1322 } | |
1323 if (regs[i].first()->is_stack()) { | |
1324 int off = regs[i].first()->reg2stack(); | |
1325 if (off > max_stack_slots) max_stack_slots = off; | |
1326 } | |
1327 if (regs[i].second()->is_stack()) { | |
1328 int off = regs[i].second()->reg2stack(); | |
1329 if (off > max_stack_slots) max_stack_slots = off; | |
1330 } | |
1331 } | |
1332 | |
1333 #else // _LP64 | |
1334 // V8 convention: first 6 things in O-regs, rest on stack. | |
1335 // Alignment is willy-nilly. | |
1336 for( int i=0; i<total_args_passed; i++ ) { | |
1337 switch( sig_bt[i] ) { | |
1338 case T_ADDRESS: // raw pointers, like current thread, for VM calls | |
1339 case T_ARRAY: | |
1340 case T_BOOLEAN: | |
1341 case T_BYTE: | |
1342 case T_CHAR: | |
1343 case T_FLOAT: | |
1344 case T_INT: | |
1345 case T_OBJECT: | |
1346 case T_SHORT: | |
1347 regs[i].set1( int_stk_helper( i ) ); | |
1348 break; | |
1349 case T_DOUBLE: | |
1350 case T_LONG: | |
1351 assert( sig_bt[i+1] == T_VOID, "expecting half" ); | |
1352 regs[i].set_pair( int_stk_helper( i+1 ), int_stk_helper( i ) ); | |
1353 break; | |
1354 case T_VOID: regs[i].set_bad(); break; | |
1355 default: | |
1356 ShouldNotReachHere(); | |
1357 } | |
1358 if (regs[i].first()->is_stack()) { | |
1359 int off = regs[i].first()->reg2stack(); | |
1360 if (off > max_stack_slots) max_stack_slots = off; | |
1361 } | |
1362 if (regs[i].second()->is_stack()) { | |
1363 int off = regs[i].second()->reg2stack(); | |
1364 if (off > max_stack_slots) max_stack_slots = off; | |
1365 } | |
1366 } | |
1367 #endif // _LP64 | |
1368 | |
1369 return round_to(max_stack_slots + 1, 2); | |
1370 | |
1371 } | |
1372 | |
1373 | |
1374 // --------------------------------------------------------------------------- | |
1375 void SharedRuntime::save_native_result(MacroAssembler *masm, BasicType ret_type, int frame_slots) { | |
1376 switch (ret_type) { | |
1377 case T_FLOAT: | |
1378 __ stf(FloatRegisterImpl::S, F0, SP, frame_slots*VMRegImpl::stack_slot_size - 4+STACK_BIAS); | |
1379 break; | |
1380 case T_DOUBLE: | |
1381 __ stf(FloatRegisterImpl::D, F0, SP, frame_slots*VMRegImpl::stack_slot_size - 8+STACK_BIAS); | |
1382 break; | |
1383 } | |
1384 } | |
1385 | |
1386 void SharedRuntime::restore_native_result(MacroAssembler *masm, BasicType ret_type, int frame_slots) { | |
1387 switch (ret_type) { | |
1388 case T_FLOAT: | |
1389 __ ldf(FloatRegisterImpl::S, SP, frame_slots*VMRegImpl::stack_slot_size - 4+STACK_BIAS, F0); | |
1390 break; | |
1391 case T_DOUBLE: | |
1392 __ ldf(FloatRegisterImpl::D, SP, frame_slots*VMRegImpl::stack_slot_size - 8+STACK_BIAS, F0); | |
1393 break; | |
1394 } | |
1395 } | |
1396 | |
1397 // Check and forward and pending exception. Thread is stored in | |
1398 // L7_thread_cache and possibly NOT in G2_thread. Since this is a native call, there | |
1399 // is no exception handler. We merely pop this frame off and throw the | |
1400 // exception in the caller's frame. | |
1401 static void check_forward_pending_exception(MacroAssembler *masm, Register Rex_oop) { | |
1402 Label L; | |
1403 __ br_null(Rex_oop, false, Assembler::pt, L); | |
1404 __ delayed()->mov(L7_thread_cache, G2_thread); // restore in case we have exception | |
1405 // Since this is a native call, we *know* the proper exception handler | |
1406 // without calling into the VM: it's the empty function. Just pop this | |
1407 // frame and then jump to forward_exception_entry; O7 will contain the | |
1408 // native caller's return PC. | |
727 | 1409 AddressLiteral exception_entry(StubRoutines::forward_exception_entry()); |
1410 __ jump_to(exception_entry, G3_scratch); | |
0 | 1411 __ delayed()->restore(); // Pop this frame off. |
1412 __ bind(L); | |
1413 } | |
1414 | |
1415 // A simple move of integer like type | |
1416 static void simple_move32(MacroAssembler* masm, VMRegPair src, VMRegPair dst) { | |
1417 if (src.first()->is_stack()) { | |
1418 if (dst.first()->is_stack()) { | |
1419 // stack to stack | |
1420 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, L5); | |
1421 __ st(L5, SP, reg2offset(dst.first()) + STACK_BIAS); | |
1422 } else { | |
1423 // stack to reg | |
1424 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register()); | |
1425 } | |
1426 } else if (dst.first()->is_stack()) { | |
1427 // reg to stack | |
1428 __ st(src.first()->as_Register(), SP, reg2offset(dst.first()) + STACK_BIAS); | |
1429 } else { | |
1430 __ mov(src.first()->as_Register(), dst.first()->as_Register()); | |
1431 } | |
1432 } | |
1433 | |
1434 // On 64 bit we will store integer like items to the stack as | |
1435 // 64 bits items (sparc abi) even though java would only store | |
1436 // 32bits for a parameter. On 32bit it will simply be 32 bits | |
1437 // So this routine will do 32->32 on 32bit and 32->64 on 64bit | |
1438 static void move32_64(MacroAssembler* masm, VMRegPair src, VMRegPair dst) { | |
1439 if (src.first()->is_stack()) { | |
1440 if (dst.first()->is_stack()) { | |
1441 // stack to stack | |
1442 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, L5); | |
1443 __ st_ptr(L5, SP, reg2offset(dst.first()) + STACK_BIAS); | |
1444 } else { | |
1445 // stack to reg | |
1446 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register()); | |
1447 } | |
1448 } else if (dst.first()->is_stack()) { | |
1449 // reg to stack | |
1450 __ st_ptr(src.first()->as_Register(), SP, reg2offset(dst.first()) + STACK_BIAS); | |
1451 } else { | |
1452 __ mov(src.first()->as_Register(), dst.first()->as_Register()); | |
1453 } | |
1454 } | |
1455 | |
1456 | |
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1457 static void move_ptr(MacroAssembler* masm, VMRegPair src, VMRegPair dst) { |
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1458 if (src.first()->is_stack()) { |
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1459 if (dst.first()->is_stack()) { |
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1460 // stack to stack |
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1461 __ ld_ptr(FP, reg2offset(src.first()) + STACK_BIAS, L5); |
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1462 __ st_ptr(L5, SP, reg2offset(dst.first()) + STACK_BIAS); |
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1463 } else { |
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1464 // stack to reg |
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1465 __ ld_ptr(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register()); |
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1466 } |
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1467 } else if (dst.first()->is_stack()) { |
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1468 // reg to stack |
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1469 __ st_ptr(src.first()->as_Register(), SP, reg2offset(dst.first()) + STACK_BIAS); |
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1470 } else { |
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1471 __ mov(src.first()->as_Register(), dst.first()->as_Register()); |
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1472 } |
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1473 } |
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1474 |
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1475 |
0 | 1476 // An oop arg. Must pass a handle not the oop itself |
1477 static void object_move(MacroAssembler* masm, | |
1478 OopMap* map, | |
1479 int oop_handle_offset, | |
1480 int framesize_in_slots, | |
1481 VMRegPair src, | |
1482 VMRegPair dst, | |
1483 bool is_receiver, | |
1484 int* receiver_offset) { | |
1485 | |
1486 // must pass a handle. First figure out the location we use as a handle | |
1487 | |
1488 if (src.first()->is_stack()) { | |
1489 // Oop is already on the stack | |
1490 Register rHandle = dst.first()->is_stack() ? L5 : dst.first()->as_Register(); | |
1491 __ add(FP, reg2offset(src.first()) + STACK_BIAS, rHandle); | |
1492 __ ld_ptr(rHandle, 0, L4); | |
1493 #ifdef _LP64 | |
1494 __ movr( Assembler::rc_z, L4, G0, rHandle ); | |
1495 #else | |
1496 __ tst( L4 ); | |
1497 __ movcc( Assembler::zero, false, Assembler::icc, G0, rHandle ); | |
1498 #endif | |
1499 if (dst.first()->is_stack()) { | |
1500 __ st_ptr(rHandle, SP, reg2offset(dst.first()) + STACK_BIAS); | |
1501 } | |
1502 int offset_in_older_frame = src.first()->reg2stack() + SharedRuntime::out_preserve_stack_slots(); | |
1503 if (is_receiver) { | |
1504 *receiver_offset = (offset_in_older_frame + framesize_in_slots) * VMRegImpl::stack_slot_size; | |
1505 } | |
1506 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + framesize_in_slots)); | |
1507 } else { | |
1508 // Oop is in an input register pass we must flush it to the stack | |
1509 const Register rOop = src.first()->as_Register(); | |
1510 const Register rHandle = L5; | |
1511 int oop_slot = rOop->input_number() * VMRegImpl::slots_per_word + oop_handle_offset; | |
1512 int offset = oop_slot*VMRegImpl::stack_slot_size; | |
1513 Label skip; | |
1514 __ st_ptr(rOop, SP, offset + STACK_BIAS); | |
1515 if (is_receiver) { | |
1516 *receiver_offset = oop_slot * VMRegImpl::stack_slot_size; | |
1517 } | |
1518 map->set_oop(VMRegImpl::stack2reg(oop_slot)); | |
1519 __ add(SP, offset + STACK_BIAS, rHandle); | |
1520 #ifdef _LP64 | |
1521 __ movr( Assembler::rc_z, rOop, G0, rHandle ); | |
1522 #else | |
1523 __ tst( rOop ); | |
1524 __ movcc( Assembler::zero, false, Assembler::icc, G0, rHandle ); | |
1525 #endif | |
1526 | |
1527 if (dst.first()->is_stack()) { | |
1528 __ st_ptr(rHandle, SP, reg2offset(dst.first()) + STACK_BIAS); | |
1529 } else { | |
1530 __ mov(rHandle, dst.first()->as_Register()); | |
1531 } | |
1532 } | |
1533 } | |
1534 | |
1535 // A float arg may have to do float reg int reg conversion | |
1536 static void float_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) { | |
1537 assert(!src.second()->is_valid() && !dst.second()->is_valid(), "bad float_move"); | |
1538 | |
1539 if (src.first()->is_stack()) { | |
1540 if (dst.first()->is_stack()) { | |
1541 // stack to stack the easiest of the bunch | |
1542 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, L5); | |
1543 __ st(L5, SP, reg2offset(dst.first()) + STACK_BIAS); | |
1544 } else { | |
1545 // stack to reg | |
1546 if (dst.first()->is_Register()) { | |
1547 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register()); | |
1548 } else { | |
1549 __ ldf(FloatRegisterImpl::S, FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_FloatRegister()); | |
1550 } | |
1551 } | |
1552 } else if (dst.first()->is_stack()) { | |
1553 // reg to stack | |
1554 if (src.first()->is_Register()) { | |
1555 __ st(src.first()->as_Register(), SP, reg2offset(dst.first()) + STACK_BIAS); | |
1556 } else { | |
1557 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(), SP, reg2offset(dst.first()) + STACK_BIAS); | |
1558 } | |
1559 } else { | |
1560 // reg to reg | |
1561 if (src.first()->is_Register()) { | |
1562 if (dst.first()->is_Register()) { | |
1563 // gpr -> gpr | |
1564 __ mov(src.first()->as_Register(), dst.first()->as_Register()); | |
1565 } else { | |
1566 // gpr -> fpr | |
1567 __ st(src.first()->as_Register(), FP, -4 + STACK_BIAS); | |
1568 __ ldf(FloatRegisterImpl::S, FP, -4 + STACK_BIAS, dst.first()->as_FloatRegister()); | |
1569 } | |
1570 } else if (dst.first()->is_Register()) { | |
1571 // fpr -> gpr | |
1572 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(), FP, -4 + STACK_BIAS); | |
1573 __ ld(FP, -4 + STACK_BIAS, dst.first()->as_Register()); | |
1574 } else { | |
1575 // fpr -> fpr | |
1576 // In theory these overlap but the ordering is such that this is likely a nop | |
1577 if ( src.first() != dst.first()) { | |
1578 __ fmov(FloatRegisterImpl::S, src.first()->as_FloatRegister(), dst.first()->as_FloatRegister()); | |
1579 } | |
1580 } | |
1581 } | |
1582 } | |
1583 | |
1584 static void split_long_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) { | |
1585 VMRegPair src_lo(src.first()); | |
1586 VMRegPair src_hi(src.second()); | |
1587 VMRegPair dst_lo(dst.first()); | |
1588 VMRegPair dst_hi(dst.second()); | |
1589 simple_move32(masm, src_lo, dst_lo); | |
1590 simple_move32(masm, src_hi, dst_hi); | |
1591 } | |
1592 | |
1593 // A long move | |
1594 static void long_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) { | |
1595 | |
1596 // Do the simple ones here else do two int moves | |
1597 if (src.is_single_phys_reg() ) { | |
1598 if (dst.is_single_phys_reg()) { | |
1599 __ mov(src.first()->as_Register(), dst.first()->as_Register()); | |
1600 } else { | |
1601 // split src into two separate registers | |
1602 // Remember hi means hi address or lsw on sparc | |
1603 // Move msw to lsw | |
1604 if (dst.second()->is_reg()) { | |
1605 // MSW -> MSW | |
1606 __ srax(src.first()->as_Register(), 32, dst.first()->as_Register()); | |
1607 // Now LSW -> LSW | |
1608 // this will only move lo -> lo and ignore hi | |
1609 VMRegPair split(dst.second()); | |
1610 simple_move32(masm, src, split); | |
1611 } else { | |
1612 VMRegPair split(src.first(), L4->as_VMReg()); | |
1613 // MSW -> MSW (lo ie. first word) | |
1614 __ srax(src.first()->as_Register(), 32, L4); | |
1615 split_long_move(masm, split, dst); | |
1616 } | |
1617 } | |
1618 } else if (dst.is_single_phys_reg()) { | |
1619 if (src.is_adjacent_aligned_on_stack(2)) { | |
304 | 1620 __ ldx(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register()); |
0 | 1621 } else { |
1622 // dst is a single reg. | |
1623 // Remember lo is low address not msb for stack slots | |
1624 // and lo is the "real" register for registers | |
1625 // src is | |
1626 | |
1627 VMRegPair split; | |
1628 | |
1629 if (src.first()->is_reg()) { | |
1630 // src.lo (msw) is a reg, src.hi is stk/reg | |
1631 // we will move: src.hi (LSW) -> dst.lo, src.lo (MSW) -> src.lo [the MSW is in the LSW of the reg] | |
1632 split.set_pair(dst.first(), src.first()); | |
1633 } else { | |
1634 // msw is stack move to L5 | |
1635 // lsw is stack move to dst.lo (real reg) | |
1636 // we will move: src.hi (LSW) -> dst.lo, src.lo (MSW) -> L5 | |
1637 split.set_pair(dst.first(), L5->as_VMReg()); | |
1638 } | |
1639 | |
1640 // src.lo -> src.lo/L5, src.hi -> dst.lo (the real reg) | |
1641 // msw -> src.lo/L5, lsw -> dst.lo | |
1642 split_long_move(masm, src, split); | |
1643 | |
1644 // So dst now has the low order correct position the | |
1645 // msw half | |
1646 __ sllx(split.first()->as_Register(), 32, L5); | |
1647 | |
1648 const Register d = dst.first()->as_Register(); | |
1649 __ or3(L5, d, d); | |
1650 } | |
1651 } else { | |
1652 // For LP64 we can probably do better. | |
1653 split_long_move(masm, src, dst); | |
1654 } | |
1655 } | |
1656 | |
1657 // A double move | |
1658 static void double_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) { | |
1659 | |
1660 // The painful thing here is that like long_move a VMRegPair might be | |
1661 // 1: a single physical register | |
1662 // 2: two physical registers (v8) | |
1663 // 3: a physical reg [lo] and a stack slot [hi] (v8) | |
1664 // 4: two stack slots | |
1665 | |
1666 // Since src is always a java calling convention we know that the src pair | |
1667 // is always either all registers or all stack (and aligned?) | |
1668 | |
1669 // in a register [lo] and a stack slot [hi] | |
1670 if (src.first()->is_stack()) { | |
1671 if (dst.first()->is_stack()) { | |
1672 // stack to stack the easiest of the bunch | |
1673 // ought to be a way to do this where if alignment is ok we use ldd/std when possible | |
1674 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, L5); | |
1675 __ ld(FP, reg2offset(src.second()) + STACK_BIAS, L4); | |
1676 __ st(L5, SP, reg2offset(dst.first()) + STACK_BIAS); | |
1677 __ st(L4, SP, reg2offset(dst.second()) + STACK_BIAS); | |
1678 } else { | |
1679 // stack to reg | |
1680 if (dst.second()->is_stack()) { | |
1681 // stack -> reg, stack -> stack | |
1682 __ ld(FP, reg2offset(src.second()) + STACK_BIAS, L4); | |
1683 if (dst.first()->is_Register()) { | |
1684 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register()); | |
1685 } else { | |
1686 __ ldf(FloatRegisterImpl::S, FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_FloatRegister()); | |
1687 } | |
1688 // This was missing. (very rare case) | |
1689 __ st(L4, SP, reg2offset(dst.second()) + STACK_BIAS); | |
1690 } else { | |
1691 // stack -> reg | |
1692 // Eventually optimize for alignment QQQ | |
1693 if (dst.first()->is_Register()) { | |
1694 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register()); | |
1695 __ ld(FP, reg2offset(src.second()) + STACK_BIAS, dst.second()->as_Register()); | |
1696 } else { | |
1697 __ ldf(FloatRegisterImpl::S, FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_FloatRegister()); | |
1698 __ ldf(FloatRegisterImpl::S, FP, reg2offset(src.second()) + STACK_BIAS, dst.second()->as_FloatRegister()); | |
1699 } | |
1700 } | |
1701 } | |
1702 } else if (dst.first()->is_stack()) { | |
1703 // reg to stack | |
1704 if (src.first()->is_Register()) { | |
1705 // Eventually optimize for alignment QQQ | |
1706 __ st(src.first()->as_Register(), SP, reg2offset(dst.first()) + STACK_BIAS); | |
1707 if (src.second()->is_stack()) { | |
1708 __ ld(FP, reg2offset(src.second()) + STACK_BIAS, L4); | |
1709 __ st(L4, SP, reg2offset(dst.second()) + STACK_BIAS); | |
1710 } else { | |
1711 __ st(src.second()->as_Register(), SP, reg2offset(dst.second()) + STACK_BIAS); | |
1712 } | |
1713 } else { | |
1714 // fpr to stack | |
1715 if (src.second()->is_stack()) { | |
1716 ShouldNotReachHere(); | |
1717 } else { | |
1718 // Is the stack aligned? | |
1719 if (reg2offset(dst.first()) & 0x7) { | |
1720 // No do as pairs | |
1721 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(), SP, reg2offset(dst.first()) + STACK_BIAS); | |
1722 __ stf(FloatRegisterImpl::S, src.second()->as_FloatRegister(), SP, reg2offset(dst.second()) + STACK_BIAS); | |
1723 } else { | |
1724 __ stf(FloatRegisterImpl::D, src.first()->as_FloatRegister(), SP, reg2offset(dst.first()) + STACK_BIAS); | |
1725 } | |
1726 } | |
1727 } | |
1728 } else { | |
1729 // reg to reg | |
1730 if (src.first()->is_Register()) { | |
1731 if (dst.first()->is_Register()) { | |
1732 // gpr -> gpr | |
1733 __ mov(src.first()->as_Register(), dst.first()->as_Register()); | |
1734 __ mov(src.second()->as_Register(), dst.second()->as_Register()); | |
1735 } else { | |
1736 // gpr -> fpr | |
1737 // ought to be able to do a single store | |
1738 __ stx(src.first()->as_Register(), FP, -8 + STACK_BIAS); | |
1739 __ stx(src.second()->as_Register(), FP, -4 + STACK_BIAS); | |
1740 // ought to be able to do a single load | |
1741 __ ldf(FloatRegisterImpl::S, FP, -8 + STACK_BIAS, dst.first()->as_FloatRegister()); | |
1742 __ ldf(FloatRegisterImpl::S, FP, -4 + STACK_BIAS, dst.second()->as_FloatRegister()); | |
1743 } | |
1744 } else if (dst.first()->is_Register()) { | |
1745 // fpr -> gpr | |
1746 // ought to be able to do a single store | |
1747 __ stf(FloatRegisterImpl::D, src.first()->as_FloatRegister(), FP, -8 + STACK_BIAS); | |
1748 // ought to be able to do a single load | |
1749 // REMEMBER first() is low address not LSB | |
1750 __ ld(FP, -8 + STACK_BIAS, dst.first()->as_Register()); | |
1751 if (dst.second()->is_Register()) { | |
1752 __ ld(FP, -4 + STACK_BIAS, dst.second()->as_Register()); | |
1753 } else { | |
1754 __ ld(FP, -4 + STACK_BIAS, L4); | |
1755 __ st(L4, SP, reg2offset(dst.second()) + STACK_BIAS); | |
1756 } | |
1757 } else { | |
1758 // fpr -> fpr | |
1759 // In theory these overlap but the ordering is such that this is likely a nop | |
1760 if ( src.first() != dst.first()) { | |
1761 __ fmov(FloatRegisterImpl::D, src.first()->as_FloatRegister(), dst.first()->as_FloatRegister()); | |
1762 } | |
1763 } | |
1764 } | |
1765 } | |
1766 | |
1767 // Creates an inner frame if one hasn't already been created, and | |
1768 // saves a copy of the thread in L7_thread_cache | |
1769 static void create_inner_frame(MacroAssembler* masm, bool* already_created) { | |
1770 if (!*already_created) { | |
1771 __ save_frame(0); | |
1772 // Save thread in L7 (INNER FRAME); it crosses a bunch of VM calls below | |
1773 // Don't use save_thread because it smashes G2 and we merely want to save a | |
1774 // copy | |
1775 __ mov(G2_thread, L7_thread_cache); | |
1776 *already_created = true; | |
1777 } | |
1778 } | |
1779 | |
4873
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1780 |
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1781 static void save_or_restore_arguments(MacroAssembler* masm, |
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1782 const int stack_slots, |
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1783 const int total_in_args, |
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1784 const int arg_save_area, |
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1785 OopMap* map, |
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1786 VMRegPair* in_regs, |
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1787 BasicType* in_sig_bt) { |
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1788 // if map is non-NULL then the code should store the values, |
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1789 // otherwise it should load them. |
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1790 if (map != NULL) { |
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1791 // Fill in the map |
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1792 for (int i = 0; i < total_in_args; i++) { |
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1793 if (in_sig_bt[i] == T_ARRAY) { |
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1794 if (in_regs[i].first()->is_stack()) { |
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1795 int offset_in_older_frame = in_regs[i].first()->reg2stack() + SharedRuntime::out_preserve_stack_slots(); |
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1796 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + stack_slots)); |
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1797 } else if (in_regs[i].first()->is_Register()) { |
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1798 map->set_oop(in_regs[i].first()); |
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1799 } else { |
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1800 ShouldNotReachHere(); |
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1801 } |
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1802 } |
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1803 } |
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1804 } |
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1805 |
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1806 // Save or restore double word values |
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1807 int handle_index = 0; |
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1808 for (int i = 0; i < total_in_args; i++) { |
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1809 int slot = handle_index + arg_save_area; |
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1810 int offset = slot * VMRegImpl::stack_slot_size; |
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1811 if (in_sig_bt[i] == T_LONG && in_regs[i].first()->is_Register()) { |
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1812 const Register reg = in_regs[i].first()->as_Register(); |
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1813 if (reg->is_global()) { |
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1814 handle_index += 2; |
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1815 assert(handle_index <= stack_slots, "overflow"); |
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1816 if (map != NULL) { |
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1817 __ stx(reg, SP, offset + STACK_BIAS); |
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1818 } else { |
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1819 __ ldx(SP, offset + STACK_BIAS, reg); |
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1820 } |
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1821 } |
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1822 } else if (in_sig_bt[i] == T_DOUBLE && in_regs[i].first()->is_FloatRegister()) { |
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1823 handle_index += 2; |
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1824 assert(handle_index <= stack_slots, "overflow"); |
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1825 if (map != NULL) { |
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1826 __ stf(FloatRegisterImpl::D, in_regs[i].first()->as_FloatRegister(), SP, offset + STACK_BIAS); |
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1827 } else { |
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1828 __ ldf(FloatRegisterImpl::D, SP, offset + STACK_BIAS, in_regs[i].first()->as_FloatRegister()); |
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1829 } |
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1830 } |
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1831 } |
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1832 // Save floats |
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1833 for (int i = 0; i < total_in_args; i++) { |
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1834 int slot = handle_index + arg_save_area; |
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1835 int offset = slot * VMRegImpl::stack_slot_size; |
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1836 if (in_sig_bt[i] == T_FLOAT && in_regs[i].first()->is_FloatRegister()) { |
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1837 handle_index++; |
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1838 assert(handle_index <= stack_slots, "overflow"); |
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1839 if (map != NULL) { |
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1840 __ stf(FloatRegisterImpl::S, in_regs[i].first()->as_FloatRegister(), SP, offset + STACK_BIAS); |
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1841 } else { |
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1842 __ ldf(FloatRegisterImpl::S, SP, offset + STACK_BIAS, in_regs[i].first()->as_FloatRegister()); |
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1843 } |
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1844 } |
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1845 } |
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1846 |
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1847 } |
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1848 |
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1849 |
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1850 // Check GC_locker::needs_gc and enter the runtime if it's true. This |
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1851 // keeps a new JNI critical region from starting until a GC has been |
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1852 // forced. Save down any oops in registers and describe them in an |
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1853 // OopMap. |
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1854 static void check_needs_gc_for_critical_native(MacroAssembler* masm, |
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1855 const int stack_slots, |
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1856 const int total_in_args, |
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1857 const int arg_save_area, |
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1858 OopMapSet* oop_maps, |
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1859 VMRegPair* in_regs, |
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1860 BasicType* in_sig_bt) { |
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1861 __ block_comment("check GC_locker::needs_gc"); |
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1862 Label cont; |
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1863 AddressLiteral sync_state(GC_locker::needs_gc_address()); |
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1864 __ load_bool_contents(sync_state, G3_scratch); |
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1865 __ cmp_zero_and_br(Assembler::equal, G3_scratch, cont); |
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1866 __ delayed()->nop(); |
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1867 |
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1868 // Save down any values that are live in registers and call into the |
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1869 // runtime to halt for a GC |
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1870 OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/); |
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1871 save_or_restore_arguments(masm, stack_slots, total_in_args, |
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1872 arg_save_area, map, in_regs, in_sig_bt); |
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1873 |
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1874 __ mov(G2_thread, L7_thread_cache); |
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1875 |
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1876 __ set_last_Java_frame(SP, noreg); |
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1877 |
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1878 __ block_comment("block_for_jni_critical"); |
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1879 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::block_for_jni_critical), relocInfo::runtime_call_type); |
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1880 __ delayed()->mov(L7_thread_cache, O0); |
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1881 oop_maps->add_gc_map( __ offset(), map); |
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1882 |
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1883 __ restore_thread(L7_thread_cache); // restore G2_thread |
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1884 __ reset_last_Java_frame(); |
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1885 |
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1886 // Reload all the register arguments |
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1887 save_or_restore_arguments(masm, stack_slots, total_in_args, |
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1888 arg_save_area, NULL, in_regs, in_sig_bt); |
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1889 |
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1890 __ bind(cont); |
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1891 #ifdef ASSERT |
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1892 if (StressCriticalJNINatives) { |
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1893 // Stress register saving |
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1894 OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/); |
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1895 save_or_restore_arguments(masm, stack_slots, total_in_args, |
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1896 arg_save_area, map, in_regs, in_sig_bt); |
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1897 // Destroy argument registers |
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1898 for (int i = 0; i < total_in_args; i++) { |
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1899 if (in_regs[i].first()->is_Register()) { |
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1900 const Register reg = in_regs[i].first()->as_Register(); |
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1901 if (reg->is_global()) { |
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1902 __ mov(G0, reg); |
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1903 } |
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1904 } else if (in_regs[i].first()->is_FloatRegister()) { |
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1905 __ fneg(FloatRegisterImpl::D, in_regs[i].first()->as_FloatRegister(), in_regs[i].first()->as_FloatRegister()); |
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1906 } |
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1907 } |
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1908 |
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1909 save_or_restore_arguments(masm, stack_slots, total_in_args, |
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1910 arg_save_area, NULL, in_regs, in_sig_bt); |
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1911 } |
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1912 #endif |
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1913 } |
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1914 |
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1915 // Unpack an array argument into a pointer to the body and the length |
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1916 // if the array is non-null, otherwise pass 0 for both. |
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1917 static void unpack_array_argument(MacroAssembler* masm, VMRegPair reg, BasicType in_elem_type, VMRegPair body_arg, VMRegPair length_arg) { |
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1918 // Pass the length, ptr pair |
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1919 Label is_null, done; |
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1920 if (reg.first()->is_stack()) { |
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1921 VMRegPair tmp = reg64_to_VMRegPair(L2); |
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1922 // Load the arg up from the stack |
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1923 move_ptr(masm, reg, tmp); |
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1924 reg = tmp; |
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1925 } |
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1926 __ cmp(reg.first()->as_Register(), G0); |
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1927 __ brx(Assembler::equal, false, Assembler::pt, is_null); |
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1928 __ delayed()->add(reg.first()->as_Register(), arrayOopDesc::base_offset_in_bytes(in_elem_type), L4); |
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1929 move_ptr(masm, reg64_to_VMRegPair(L4), body_arg); |
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1930 __ ld(reg.first()->as_Register(), arrayOopDesc::length_offset_in_bytes(), L4); |
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1931 move32_64(masm, reg64_to_VMRegPair(L4), length_arg); |
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1932 __ ba_short(done); |
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1933 __ bind(is_null); |
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1934 // Pass zeros |
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1935 move_ptr(masm, reg64_to_VMRegPair(G0), body_arg); |
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1936 move32_64(masm, reg64_to_VMRegPair(G0), length_arg); |
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1937 __ bind(done); |
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1938 } |
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1939 |
0 | 1940 // --------------------------------------------------------------------------- |
1941 // Generate a native wrapper for a given method. The method takes arguments | |
1942 // in the Java compiled code convention, marshals them to the native | |
1943 // convention (handlizes oops, etc), transitions to native, makes the call, | |
1944 // returns to java state (possibly blocking), unhandlizes any result and | |
1945 // returns. | |
1946 nmethod *SharedRuntime::generate_native_wrapper(MacroAssembler* masm, | |
1947 methodHandle method, | |
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1948 int compile_id, |
0 | 1949 int total_in_args, |
1950 int comp_args_on_stack, // in VMRegStackSlots | |
1951 BasicType *in_sig_bt, | |
1952 VMRegPair *in_regs, | |
1953 BasicType ret_type) { | |
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1954 bool is_critical_native = true; |
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1955 address native_func = method->critical_native_function(); |
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1956 if (native_func == NULL) { |
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1957 native_func = method->native_function(); |
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1958 is_critical_native = false; |
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1959 } |
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1960 assert(native_func != NULL, "must have function"); |
0 | 1961 |
1962 // Native nmethod wrappers never take possesion of the oop arguments. | |
1963 // So the caller will gc the arguments. The only thing we need an | |
1964 // oopMap for is if the call is static | |
1965 // | |
1966 // An OopMap for lock (and class if static), and one for the VM call itself | |
1967 OopMapSet *oop_maps = new OopMapSet(); | |
1968 intptr_t start = (intptr_t)__ pc(); | |
1969 | |
1970 // First thing make an ic check to see if we should even be here | |
1971 { | |
1972 Label L; | |
1973 const Register temp_reg = G3_scratch; | |
727 | 1974 AddressLiteral ic_miss(SharedRuntime::get_ic_miss_stub()); |
0 | 1975 __ verify_oop(O0); |
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1976 __ load_klass(O0, temp_reg); |
3839 | 1977 __ cmp_and_brx_short(temp_reg, G5_inline_cache_reg, Assembler::equal, Assembler::pt, L); |
0 | 1978 |
727 | 1979 __ jump_to(ic_miss, temp_reg); |
0 | 1980 __ delayed()->nop(); |
1981 __ align(CodeEntryAlignment); | |
1982 __ bind(L); | |
1983 } | |
1984 | |
1985 int vep_offset = ((intptr_t)__ pc()) - start; | |
1986 | |
1987 #ifdef COMPILER1 | |
1988 if (InlineObjectHash && method->intrinsic_id() == vmIntrinsics::_hashCode) { | |
1989 // Object.hashCode can pull the hashCode from the header word | |
1990 // instead of doing a full VM transition once it's been computed. | |
1991 // Since hashCode is usually polymorphic at call sites we can't do | |
1992 // this optimization at the call site without a lot of work. | |
1993 Label slowCase; | |
1994 Register receiver = O0; | |
1995 Register result = O0; | |
1996 Register header = G3_scratch; | |
1997 Register hash = G3_scratch; // overwrite header value with hash value | |
1998 Register mask = G1; // to get hash field from header | |
1999 | |
2000 // Read the header and build a mask to get its hash field. Give up if the object is not unlocked. | |
2001 // We depend on hash_mask being at most 32 bits and avoid the use of | |
2002 // hash_mask_in_place because it could be larger than 32 bits in a 64-bit | |
2003 // vm: see markOop.hpp. | |
2004 __ ld_ptr(receiver, oopDesc::mark_offset_in_bytes(), header); | |
2005 __ sethi(markOopDesc::hash_mask, mask); | |
2006 __ btst(markOopDesc::unlocked_value, header); | |
2007 __ br(Assembler::zero, false, Assembler::pn, slowCase); | |
2008 if (UseBiasedLocking) { | |
2009 // Check if biased and fall through to runtime if so | |
2010 __ delayed()->nop(); | |
2011 __ btst(markOopDesc::biased_lock_bit_in_place, header); | |
2012 __ br(Assembler::notZero, false, Assembler::pn, slowCase); | |
2013 } | |
2014 __ delayed()->or3(mask, markOopDesc::hash_mask & 0x3ff, mask); | |
2015 | |
2016 // Check for a valid (non-zero) hash code and get its value. | |
2017 #ifdef _LP64 | |
2018 __ srlx(header, markOopDesc::hash_shift, hash); | |
2019 #else | |
2020 __ srl(header, markOopDesc::hash_shift, hash); | |
2021 #endif | |
2022 __ andcc(hash, mask, hash); | |
2023 __ br(Assembler::equal, false, Assembler::pn, slowCase); | |
2024 __ delayed()->nop(); | |
2025 | |
2026 // leaf return. | |
2027 __ retl(); | |
2028 __ delayed()->mov(hash, result); | |
2029 __ bind(slowCase); | |
2030 } | |
2031 #endif // COMPILER1 | |
2032 | |
2033 | |
2034 // We have received a description of where all the java arg are located | |
2035 // on entry to the wrapper. We need to convert these args to where | |
2036 // the jni function will expect them. To figure out where they go | |
2037 // we convert the java signature to a C signature by inserting | |
2038 // the hidden arguments as arg[0] and possibly arg[1] (static method) | |
2039 | |
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2040 int total_c_args = total_in_args; |
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2041 int total_save_slots = 6 * VMRegImpl::slots_per_word; |
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2042 if (!is_critical_native) { |
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2043 total_c_args += 1; |
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2044 if (method->is_static()) { |
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2045 total_c_args++; |
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2046 } |
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2047 } else { |
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2048 for (int i = 0; i < total_in_args; i++) { |
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2049 if (in_sig_bt[i] == T_ARRAY) { |
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2050 // These have to be saved and restored across the safepoint |
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2051 total_c_args++; |
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2052 } |
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2053 } |
0 | 2054 } |
2055 | |
2056 BasicType* out_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_c_args); | |
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2057 VMRegPair* out_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_c_args); |
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2058 BasicType* in_elem_bt = NULL; |
0 | 2059 |
2060 int argc = 0; | |
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2061 if (!is_critical_native) { |
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2062 out_sig_bt[argc++] = T_ADDRESS; |
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2063 if (method->is_static()) { |
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2064 out_sig_bt[argc++] = T_OBJECT; |
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2065 } |
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2066 |
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2067 for (int i = 0; i < total_in_args ; i++ ) { |
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2068 out_sig_bt[argc++] = in_sig_bt[i]; |
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2069 } |
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2070 } else { |
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2071 Thread* THREAD = Thread::current(); |
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2072 in_elem_bt = NEW_RESOURCE_ARRAY(BasicType, total_in_args); |
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2073 SignatureStream ss(method->signature()); |
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2074 for (int i = 0; i < total_in_args ; i++ ) { |
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2075 if (in_sig_bt[i] == T_ARRAY) { |
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2076 // Arrays are passed as int, elem* pair |
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2077 out_sig_bt[argc++] = T_INT; |
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2078 out_sig_bt[argc++] = T_ADDRESS; |
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2079 Symbol* atype = ss.as_symbol(CHECK_NULL); |
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2080 const char* at = atype->as_C_string(); |
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2081 if (strlen(at) == 2) { |
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2082 assert(at[0] == '[', "must be"); |
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2083 switch (at[1]) { |
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2084 case 'B': in_elem_bt[i] = T_BYTE; break; |
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2085 case 'C': in_elem_bt[i] = T_CHAR; break; |
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2086 case 'D': in_elem_bt[i] = T_DOUBLE; break; |
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2087 case 'F': in_elem_bt[i] = T_FLOAT; break; |
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2088 case 'I': in_elem_bt[i] = T_INT; break; |
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2089 case 'J': in_elem_bt[i] = T_LONG; break; |
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2090 case 'S': in_elem_bt[i] = T_SHORT; break; |
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2091 case 'Z': in_elem_bt[i] = T_BOOLEAN; break; |
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2092 default: ShouldNotReachHere(); |
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2093 } |
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2094 } |
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2095 } else { |
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2096 out_sig_bt[argc++] = in_sig_bt[i]; |
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2097 in_elem_bt[i] = T_VOID; |
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2098 } |
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2099 if (in_sig_bt[i] != T_VOID) { |
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2100 assert(in_sig_bt[i] == ss.type(), "must match"); |
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2101 ss.next(); |
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2102 } |
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2103 } |
0 | 2104 } |
2105 | |
2106 // Now figure out where the args must be stored and how much stack space | |
2107 // they require (neglecting out_preserve_stack_slots but space for storing | |
2108 // the 1st six register arguments). It's weird see int_stk_helper. | |
2109 // | |
2110 int out_arg_slots; | |
2111 out_arg_slots = c_calling_convention(out_sig_bt, out_regs, total_c_args); | |
2112 | |
4873
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2113 if (is_critical_native) { |
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2114 // Critical natives may have to call out so they need a save area |
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2115 // for register arguments. |
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2116 int double_slots = 0; |
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2117 int single_slots = 0; |
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2118 for ( int i = 0; i < total_in_args; i++) { |
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2119 if (in_regs[i].first()->is_Register()) { |
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2120 const Register reg = in_regs[i].first()->as_Register(); |
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2121 switch (in_sig_bt[i]) { |
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2122 case T_ARRAY: |
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2123 case T_BOOLEAN: |
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2124 case T_BYTE: |
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2125 case T_SHORT: |
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2126 case T_CHAR: |
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2127 case T_INT: assert(reg->is_in(), "don't need to save these"); break; |
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2128 case T_LONG: if (reg->is_global()) double_slots++; break; |
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2129 default: ShouldNotReachHere(); |
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2130 } |
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2131 } else if (in_regs[i].first()->is_FloatRegister()) { |
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2132 switch (in_sig_bt[i]) { |
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2133 case T_FLOAT: single_slots++; break; |
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2134 case T_DOUBLE: double_slots++; break; |
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2135 default: ShouldNotReachHere(); |
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2136 } |
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2137 } |
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2138 } |
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2139 total_save_slots = double_slots * 2 + single_slots; |
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2140 } |
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2141 |
0 | 2142 // Compute framesize for the wrapper. We need to handlize all oops in |
2143 // registers. We must create space for them here that is disjoint from | |
2144 // the windowed save area because we have no control over when we might | |
2145 // flush the window again and overwrite values that gc has since modified. | |
2146 // (The live window race) | |
2147 // | |
2148 // We always just allocate 6 word for storing down these object. This allow | |
2149 // us to simply record the base and use the Ireg number to decide which | |
2150 // slot to use. (Note that the reg number is the inbound number not the | |
2151 // outbound number). | |
2152 // We must shuffle args to match the native convention, and include var-args space. | |
2153 | |
2154 // Calculate the total number of stack slots we will need. | |
2155 | |
2156 // First count the abi requirement plus all of the outgoing args | |
2157 int stack_slots = SharedRuntime::out_preserve_stack_slots() + out_arg_slots; | |
2158 | |
2159 // Now the space for the inbound oop handle area | |
2160 | |
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2161 int oop_handle_offset = round_to(stack_slots, 2); |
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2162 stack_slots += total_save_slots; |
0 | 2163 |
2164 // Now any space we need for handlizing a klass if static method | |
2165 | |
2166 int klass_slot_offset = 0; | |
2167 int klass_offset = -1; | |
2168 int lock_slot_offset = 0; | |
2169 bool is_static = false; | |
2170 | |
2171 if (method->is_static()) { | |
2172 klass_slot_offset = stack_slots; | |
2173 stack_slots += VMRegImpl::slots_per_word; | |
2174 klass_offset = klass_slot_offset * VMRegImpl::stack_slot_size; | |
2175 is_static = true; | |
2176 } | |
2177 | |
2178 // Plus a lock if needed | |
2179 | |
2180 if (method->is_synchronized()) { | |
2181 lock_slot_offset = stack_slots; | |
2182 stack_slots += VMRegImpl::slots_per_word; | |
2183 } | |
2184 | |
2185 // Now a place to save return value or as a temporary for any gpr -> fpr moves | |
2186 stack_slots += 2; | |
2187 | |
2188 // Ok The space we have allocated will look like: | |
2189 // | |
2190 // | |
2191 // FP-> | | | |
2192 // |---------------------| | |
2193 // | 2 slots for moves | | |
2194 // |---------------------| | |
2195 // | lock box (if sync) | | |
2196 // |---------------------| <- lock_slot_offset | |
2197 // | klass (if static) | | |
2198 // |---------------------| <- klass_slot_offset | |
2199 // | oopHandle area | | |
2200 // |---------------------| <- oop_handle_offset | |
2201 // | outbound memory | | |
2202 // | based arguments | | |
2203 // | | | |
2204 // |---------------------| | |
2205 // | vararg area | | |
2206 // |---------------------| | |
2207 // | | | |
2208 // SP-> | out_preserved_slots | | |
2209 // | |
2210 // | |
2211 | |
2212 | |
2213 // Now compute actual number of stack words we need rounding to make | |
2214 // stack properly aligned. | |
2215 stack_slots = round_to(stack_slots, 2 * VMRegImpl::slots_per_word); | |
2216 | |
2217 int stack_size = stack_slots * VMRegImpl::stack_slot_size; | |
2218 | |
2219 // Generate stack overflow check before creating frame | |
2220 __ generate_stack_overflow_check(stack_size); | |
2221 | |
2222 // Generate a new frame for the wrapper. | |
2223 __ save(SP, -stack_size, SP); | |
2224 | |
2225 int frame_complete = ((intptr_t)__ pc()) - start; | |
2226 | |
2227 __ verify_thread(); | |
2228 | |
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2229 if (is_critical_native) { |
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2230 check_needs_gc_for_critical_native(masm, stack_slots, total_in_args, |
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2231 oop_handle_offset, oop_maps, in_regs, in_sig_bt); |
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2232 } |
0 | 2233 |
2234 // | |
2235 // We immediately shuffle the arguments so that any vm call we have to | |
2236 // make from here on out (sync slow path, jvmti, etc.) we will have | |
2237 // captured the oops from our caller and have a valid oopMap for | |
2238 // them. | |
2239 | |
2240 // ----------------- | |
2241 // The Grand Shuffle | |
2242 // | |
2243 // Natives require 1 or 2 extra arguments over the normal ones: the JNIEnv* | |
2244 // (derived from JavaThread* which is in L7_thread_cache) and, if static, | |
2245 // the class mirror instead of a receiver. This pretty much guarantees that | |
2246 // register layout will not match. We ignore these extra arguments during | |
2247 // the shuffle. The shuffle is described by the two calling convention | |
2248 // vectors we have in our possession. We simply walk the java vector to | |
2249 // get the source locations and the c vector to get the destinations. | |
2250 // Because we have a new window and the argument registers are completely | |
2251 // disjoint ( I0 -> O1, I1 -> O2, ...) we have nothing to worry about | |
2252 // here. | |
2253 | |
2254 // This is a trick. We double the stack slots so we can claim | |
2255 // the oops in the caller's frame. Since we are sure to have | |
2256 // more args than the caller doubling is enough to make | |
2257 // sure we can capture all the incoming oop args from the | |
2258 // caller. | |
2259 // | |
2260 OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/); | |
2261 // Record sp-based slot for receiver on stack for non-static methods | |
2262 int receiver_offset = -1; | |
2263 | |
2264 // We move the arguments backward because the floating point registers | |
2265 // destination will always be to a register with a greater or equal register | |
2266 // number or the stack. | |
2267 | |
2268 #ifdef ASSERT | |
2269 bool reg_destroyed[RegisterImpl::number_of_registers]; | |
2270 bool freg_destroyed[FloatRegisterImpl::number_of_registers]; | |
2271 for ( int r = 0 ; r < RegisterImpl::number_of_registers ; r++ ) { | |
2272 reg_destroyed[r] = false; | |
2273 } | |
2274 for ( int f = 0 ; f < FloatRegisterImpl::number_of_registers ; f++ ) { | |
2275 freg_destroyed[f] = false; | |
2276 } | |
2277 | |
2278 #endif /* ASSERT */ | |
2279 | |
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2280 for ( int i = total_in_args - 1, c_arg = total_c_args - 1; i >= 0 ; i--, c_arg-- ) { |
0 | 2281 |
2282 #ifdef ASSERT | |
2283 if (in_regs[i].first()->is_Register()) { | |
2284 assert(!reg_destroyed[in_regs[i].first()->as_Register()->encoding()], "ack!"); | |
2285 } else if (in_regs[i].first()->is_FloatRegister()) { | |
2286 assert(!freg_destroyed[in_regs[i].first()->as_FloatRegister()->encoding(FloatRegisterImpl::S)], "ack!"); | |
2287 } | |
2288 if (out_regs[c_arg].first()->is_Register()) { | |
2289 reg_destroyed[out_regs[c_arg].first()->as_Register()->encoding()] = true; | |
2290 } else if (out_regs[c_arg].first()->is_FloatRegister()) { | |
2291 freg_destroyed[out_regs[c_arg].first()->as_FloatRegister()->encoding(FloatRegisterImpl::S)] = true; | |
2292 } | |
2293 #endif /* ASSERT */ | |
2294 | |
2295 switch (in_sig_bt[i]) { | |
2296 case T_ARRAY: | |
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2297 if (is_critical_native) { |
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2298 unpack_array_argument(masm, in_regs[i], in_elem_bt[i], out_regs[c_arg], out_regs[c_arg - 1]); |
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2299 c_arg--; |
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2300 break; |
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2301 } |
0 | 2302 case T_OBJECT: |
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2303 assert(!is_critical_native, "no oop arguments"); |
0 | 2304 object_move(masm, map, oop_handle_offset, stack_slots, in_regs[i], out_regs[c_arg], |
2305 ((i == 0) && (!is_static)), | |
2306 &receiver_offset); | |
2307 break; | |
2308 case T_VOID: | |
2309 break; | |
2310 | |
2311 case T_FLOAT: | |
2312 float_move(masm, in_regs[i], out_regs[c_arg]); | |
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2313 break; |
0 | 2314 |
2315 case T_DOUBLE: | |
2316 assert( i + 1 < total_in_args && | |
2317 in_sig_bt[i + 1] == T_VOID && | |
2318 out_sig_bt[c_arg+1] == T_VOID, "bad arg list"); | |
2319 double_move(masm, in_regs[i], out_regs[c_arg]); | |
2320 break; | |
2321 | |
2322 case T_LONG : | |
2323 long_move(masm, in_regs[i], out_regs[c_arg]); | |
2324 break; | |
2325 | |
2326 case T_ADDRESS: assert(false, "found T_ADDRESS in java args"); | |
2327 | |
2328 default: | |
2329 move32_64(masm, in_regs[i], out_regs[c_arg]); | |
2330 } | |
2331 } | |
2332 | |
2333 // Pre-load a static method's oop into O1. Used both by locking code and | |
2334 // the normal JNI call code. | |
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|
2335 if (method->is_static() && !is_critical_native) { |
0 | 2336 __ set_oop_constant(JNIHandles::make_local(Klass::cast(method->method_holder())->java_mirror()), O1); |
2337 | |
2338 // Now handlize the static class mirror in O1. It's known not-null. | |
2339 __ st_ptr(O1, SP, klass_offset + STACK_BIAS); | |
2340 map->set_oop(VMRegImpl::stack2reg(klass_slot_offset)); | |
2341 __ add(SP, klass_offset + STACK_BIAS, O1); | |
2342 } | |
2343 | |
2344 | |
2345 const Register L6_handle = L6; | |
2346 | |
2347 if (method->is_synchronized()) { | |
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2348 assert(!is_critical_native, "unhandled"); |
0 | 2349 __ mov(O1, L6_handle); |
2350 } | |
2351 | |
2352 // We have all of the arguments setup at this point. We MUST NOT touch any Oregs | |
2353 // except O6/O7. So if we must call out we must push a new frame. We immediately | |
2354 // push a new frame and flush the windows. | |
2355 #ifdef _LP64 | |
2356 intptr_t thepc = (intptr_t) __ pc(); | |
2357 { | |
2358 address here = __ pc(); | |
2359 // Call the next instruction | |
2360 __ call(here + 8, relocInfo::none); | |
2361 __ delayed()->nop(); | |
2362 } | |
2363 #else | |
2364 intptr_t thepc = __ load_pc_address(O7, 0); | |
2365 #endif /* _LP64 */ | |
2366 | |
2367 // We use the same pc/oopMap repeatedly when we call out | |
2368 oop_maps->add_gc_map(thepc - start, map); | |
2369 | |
2370 // O7 now has the pc loaded that we will use when we finally call to native. | |
2371 | |
2372 // Save thread in L7; it crosses a bunch of VM calls below | |
2373 // Don't use save_thread because it smashes G2 and we merely | |
2374 // want to save a copy | |
2375 __ mov(G2_thread, L7_thread_cache); | |
2376 | |
2377 | |
2378 // If we create an inner frame once is plenty | |
2379 // when we create it we must also save G2_thread | |
2380 bool inner_frame_created = false; | |
2381 | |
2382 // dtrace method entry support | |
2383 { | |
2384 SkipIfEqual skip_if( | |
2385 masm, G3_scratch, &DTraceMethodProbes, Assembler::zero); | |
2386 // create inner frame | |
2387 __ save_frame(0); | |
2388 __ mov(G2_thread, L7_thread_cache); | |
2389 __ set_oop_constant(JNIHandles::make_local(method()), O1); | |
2390 __ call_VM_leaf(L7_thread_cache, | |
2391 CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_entry), | |
2392 G2_thread, O1); | |
2393 __ restore(); | |
2394 } | |
2395 | |
610
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2396 // RedefineClasses() tracing support for obsolete method entry |
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2397 if (RC_TRACE_IN_RANGE(0x00001000, 0x00002000)) { |
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2398 // create inner frame |
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2399 __ save_frame(0); |
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2400 __ mov(G2_thread, L7_thread_cache); |
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2401 __ set_oop_constant(JNIHandles::make_local(method()), O1); |
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2402 __ call_VM_leaf(L7_thread_cache, |
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2403 CAST_FROM_FN_PTR(address, SharedRuntime::rc_trace_method_entry), |
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2404 G2_thread, O1); |
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2405 __ restore(); |
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2406 } |
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2407 |
0 | 2408 // We are in the jni frame unless saved_frame is true in which case |
2409 // we are in one frame deeper (the "inner" frame). If we are in the | |
2410 // "inner" frames the args are in the Iregs and if the jni frame then | |
2411 // they are in the Oregs. | |
2412 // If we ever need to go to the VM (for locking, jvmti) then | |
2413 // we will always be in the "inner" frame. | |
2414 | |
2415 // Lock a synchronized method | |
2416 int lock_offset = -1; // Set if locked | |
2417 if (method->is_synchronized()) { | |
2418 Register Roop = O1; | |
2419 const Register L3_box = L3; | |
2420 | |
2421 create_inner_frame(masm, &inner_frame_created); | |
2422 | |
2423 __ ld_ptr(I1, 0, O1); | |
2424 Label done; | |
2425 | |
2426 lock_offset = (lock_slot_offset * VMRegImpl::stack_slot_size); | |
2427 __ add(FP, lock_offset+STACK_BIAS, L3_box); | |
2428 #ifdef ASSERT | |
2429 if (UseBiasedLocking) { | |
2430 // making the box point to itself will make it clear it went unused | |
2431 // but also be obviously invalid | |
2432 __ st_ptr(L3_box, L3_box, 0); | |
2433 } | |
2434 #endif // ASSERT | |
2435 // | |
2436 // Compiler_lock_object (Roop, Rmark, Rbox, Rscratch) -- kills Rmark, Rbox, Rscratch | |
2437 // | |
2438 __ compiler_lock_object(Roop, L1, L3_box, L2); | |
2439 __ br(Assembler::equal, false, Assembler::pt, done); | |
2440 __ delayed() -> add(FP, lock_offset+STACK_BIAS, L3_box); | |
2441 | |
2442 | |
2443 // None of the above fast optimizations worked so we have to get into the | |
2444 // slow case of monitor enter. Inline a special case of call_VM that | |
2445 // disallows any pending_exception. | |
2446 __ mov(Roop, O0); // Need oop in O0 | |
2447 __ mov(L3_box, O1); | |
2448 | |
2449 // Record last_Java_sp, in case the VM code releases the JVM lock. | |
2450 | |
2451 __ set_last_Java_frame(FP, I7); | |
2452 | |
2453 // do the call | |
2454 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::complete_monitor_locking_C), relocInfo::runtime_call_type); | |
2455 __ delayed()->mov(L7_thread_cache, O2); | |
2456 | |
2457 __ restore_thread(L7_thread_cache); // restore G2_thread | |
2458 __ reset_last_Java_frame(); | |
2459 | |
2460 #ifdef ASSERT | |
2461 { Label L; | |
2462 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), O0); | |
3839 | 2463 __ br_null_short(O0, Assembler::pt, L); |
0 | 2464 __ stop("no pending exception allowed on exit from IR::monitorenter"); |
2465 __ bind(L); | |
2466 } | |
2467 #endif | |
2468 __ bind(done); | |
2469 } | |
2470 | |
2471 | |
2472 // Finally just about ready to make the JNI call | |
2473 | |
2474 __ flush_windows(); | |
2475 if (inner_frame_created) { | |
2476 __ restore(); | |
2477 } else { | |
2478 // Store only what we need from this frame | |
2479 // QQQ I think that non-v9 (like we care) we don't need these saves | |
2480 // either as the flush traps and the current window goes too. | |
2481 __ st_ptr(FP, SP, FP->sp_offset_in_saved_window()*wordSize + STACK_BIAS); | |
2482 __ st_ptr(I7, SP, I7->sp_offset_in_saved_window()*wordSize + STACK_BIAS); | |
2483 } | |
2484 | |
2485 // get JNIEnv* which is first argument to native | |
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2486 if (!is_critical_native) { |
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2487 __ add(G2_thread, in_bytes(JavaThread::jni_environment_offset()), O0); |
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2488 } |
0 | 2489 |
2490 // Use that pc we placed in O7 a while back as the current frame anchor | |
2491 __ set_last_Java_frame(SP, O7); | |
2492 | |
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2493 // We flushed the windows ages ago now mark them as flushed before transitioning. |
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2494 __ set(JavaFrameAnchor::flushed, G3_scratch); |
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2495 __ st(G3_scratch, G2_thread, JavaThread::frame_anchor_offset() + JavaFrameAnchor::flags_offset()); |
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2496 |
0 | 2497 // Transition from _thread_in_Java to _thread_in_native. |
2498 __ set(_thread_in_native, G3_scratch); | |
2499 | |
2500 #ifdef _LP64 | |
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2501 AddressLiteral dest(native_func); |
0 | 2502 __ relocate(relocInfo::runtime_call_type); |
727 | 2503 __ jumpl_to(dest, O7, O7); |
0 | 2504 #else |
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2505 __ call(native_func, relocInfo::runtime_call_type); |
0 | 2506 #endif |
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2507 __ delayed()->st(G3_scratch, G2_thread, JavaThread::thread_state_offset()); |
0 | 2508 |
2509 __ restore_thread(L7_thread_cache); // restore G2_thread | |
2510 | |
2511 // Unpack native results. For int-types, we do any needed sign-extension | |
2512 // and move things into I0. The return value there will survive any VM | |
2513 // calls for blocking or unlocking. An FP or OOP result (handle) is done | |
2514 // specially in the slow-path code. | |
2515 switch (ret_type) { | |
2516 case T_VOID: break; // Nothing to do! | |
2517 case T_FLOAT: break; // Got it where we want it (unless slow-path) | |
2518 case T_DOUBLE: break; // Got it where we want it (unless slow-path) | |
2519 // In 64 bits build result is in O0, in O0, O1 in 32bit build | |
2520 case T_LONG: | |
2521 #ifndef _LP64 | |
2522 __ mov(O1, I1); | |
2523 #endif | |
2524 // Fall thru | |
2525 case T_OBJECT: // Really a handle | |
2526 case T_ARRAY: | |
2527 case T_INT: | |
2528 __ mov(O0, I0); | |
2529 break; | |
2530 case T_BOOLEAN: __ subcc(G0, O0, G0); __ addc(G0, 0, I0); break; // !0 => true; 0 => false | |
2531 case T_BYTE : __ sll(O0, 24, O0); __ sra(O0, 24, I0); break; | |
2532 case T_CHAR : __ sll(O0, 16, O0); __ srl(O0, 16, I0); break; // cannot use and3, 0xFFFF too big as immediate value! | |
2533 case T_SHORT : __ sll(O0, 16, O0); __ sra(O0, 16, I0); break; | |
2534 break; // Cannot de-handlize until after reclaiming jvm_lock | |
2535 default: | |
2536 ShouldNotReachHere(); | |
2537 } | |
2538 | |
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2539 Label after_transition; |
0 | 2540 // must we block? |
2541 | |
2542 // Block, if necessary, before resuming in _thread_in_Java state. | |
2543 // In order for GC to work, don't clear the last_Java_sp until after blocking. | |
2544 { Label no_block; | |
727 | 2545 AddressLiteral sync_state(SafepointSynchronize::address_of_state()); |
0 | 2546 |
2547 // Switch thread to "native transition" state before reading the synchronization state. | |
2548 // This additional state is necessary because reading and testing the synchronization | |
2549 // state is not atomic w.r.t. GC, as this scenario demonstrates: | |
2550 // Java thread A, in _thread_in_native state, loads _not_synchronized and is preempted. | |
2551 // VM thread changes sync state to synchronizing and suspends threads for GC. | |
2552 // Thread A is resumed to finish this native method, but doesn't block here since it | |
2553 // didn't see any synchronization is progress, and escapes. | |
2554 __ set(_thread_in_native_trans, G3_scratch); | |
727 | 2555 __ st(G3_scratch, G2_thread, JavaThread::thread_state_offset()); |
0 | 2556 if(os::is_MP()) { |
2557 if (UseMembar) { | |
2558 // Force this write out before the read below | |
2559 __ membar(Assembler::StoreLoad); | |
2560 } else { | |
2561 // Write serialization page so VM thread can do a pseudo remote membar. | |
2562 // We use the current thread pointer to calculate a thread specific | |
2563 // offset to write to within the page. This minimizes bus traffic | |
2564 // due to cache line collision. | |
2565 __ serialize_memory(G2_thread, G1_scratch, G3_scratch); | |
2566 } | |
2567 } | |
2568 __ load_contents(sync_state, G3_scratch); | |
2569 __ cmp(G3_scratch, SafepointSynchronize::_not_synchronized); | |
2570 | |
2571 Label L; | |
727 | 2572 Address suspend_state(G2_thread, JavaThread::suspend_flags_offset()); |
0 | 2573 __ br(Assembler::notEqual, false, Assembler::pn, L); |
727 | 2574 __ delayed()->ld(suspend_state, G3_scratch); |
3839 | 2575 __ cmp_and_br_short(G3_scratch, 0, Assembler::equal, Assembler::pt, no_block); |
0 | 2576 __ bind(L); |
2577 | |
2578 // Block. Save any potential method result value before the operation and | |
2579 // use a leaf call to leave the last_Java_frame setup undisturbed. Doing this | |
2580 // lets us share the oopMap we used when we went native rather the create | |
2581 // a distinct one for this pc | |
2582 // | |
2583 save_native_result(masm, ret_type, stack_slots); | |
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2584 if (!is_critical_native) { |
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2585 __ call_VM_leaf(L7_thread_cache, |
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2586 CAST_FROM_FN_PTR(address, JavaThread::check_special_condition_for_native_trans), |
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2587 G2_thread); |
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2588 } else { |
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2589 __ call_VM_leaf(L7_thread_cache, |
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2590 CAST_FROM_FN_PTR(address, JavaThread::check_special_condition_for_native_trans_and_transition), |
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2591 G2_thread); |
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2592 } |
0 | 2593 |
2594 // Restore any method result value | |
2595 restore_native_result(masm, ret_type, stack_slots); | |
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2596 |
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2597 if (is_critical_native) { |
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2598 // The call above performed the transition to thread_in_Java so |
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2599 // skip the transition logic below. |
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2600 __ ba(after_transition); |
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2601 __ delayed()->nop(); |
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2602 } |
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2603 |
0 | 2604 __ bind(no_block); |
2605 } | |
2606 | |
2607 // thread state is thread_in_native_trans. Any safepoint blocking has already | |
2608 // happened so we can now change state to _thread_in_Java. | |
2609 __ set(_thread_in_Java, G3_scratch); | |
727 | 2610 __ st(G3_scratch, G2_thread, JavaThread::thread_state_offset()); |
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2611 __ bind(after_transition); |
0 | 2612 |
2613 Label no_reguard; | |
727 | 2614 __ ld(G2_thread, JavaThread::stack_guard_state_offset(), G3_scratch); |
3839 | 2615 __ cmp_and_br_short(G3_scratch, JavaThread::stack_guard_yellow_disabled, Assembler::notEqual, Assembler::pt, no_reguard); |
0 | 2616 |
2617 save_native_result(masm, ret_type, stack_slots); | |
2618 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::reguard_yellow_pages)); | |
2619 __ delayed()->nop(); | |
2620 | |
2621 __ restore_thread(L7_thread_cache); // restore G2_thread | |
2622 restore_native_result(masm, ret_type, stack_slots); | |
2623 | |
2624 __ bind(no_reguard); | |
2625 | |
2626 // Handle possible exception (will unlock if necessary) | |
2627 | |
2628 // native result if any is live in freg or I0 (and I1 if long and 32bit vm) | |
2629 | |
2630 // Unlock | |
2631 if (method->is_synchronized()) { | |
2632 Label done; | |
2633 Register I2_ex_oop = I2; | |
2634 const Register L3_box = L3; | |
2635 // Get locked oop from the handle we passed to jni | |
2636 __ ld_ptr(L6_handle, 0, L4); | |
2637 __ add(SP, lock_offset+STACK_BIAS, L3_box); | |
2638 // Must save pending exception around the slow-path VM call. Since it's a | |
2639 // leaf call, the pending exception (if any) can be kept in a register. | |
2640 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), I2_ex_oop); | |
2641 // Now unlock | |
2642 // (Roop, Rmark, Rbox, Rscratch) | |
2643 __ compiler_unlock_object(L4, L1, L3_box, L2); | |
2644 __ br(Assembler::equal, false, Assembler::pt, done); | |
2645 __ delayed()-> add(SP, lock_offset+STACK_BIAS, L3_box); | |
2646 | |
2647 // save and restore any potential method result value around the unlocking | |
2648 // operation. Will save in I0 (or stack for FP returns). | |
2649 save_native_result(masm, ret_type, stack_slots); | |
2650 | |
2651 // Must clear pending-exception before re-entering the VM. Since this is | |
2652 // a leaf call, pending-exception-oop can be safely kept in a register. | |
2653 __ st_ptr(G0, G2_thread, in_bytes(Thread::pending_exception_offset())); | |
2654 | |
2655 // slow case of monitor enter. Inline a special case of call_VM that | |
2656 // disallows any pending_exception. | |
2657 __ mov(L3_box, O1); | |
2658 | |
2659 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::complete_monitor_unlocking_C), relocInfo::runtime_call_type); | |
2660 __ delayed()->mov(L4, O0); // Need oop in O0 | |
2661 | |
2662 __ restore_thread(L7_thread_cache); // restore G2_thread | |
2663 | |
2664 #ifdef ASSERT | |
2665 { Label L; | |
2666 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), O0); | |
3839 | 2667 __ br_null_short(O0, Assembler::pt, L); |
0 | 2668 __ stop("no pending exception allowed on exit from IR::monitorexit"); |
2669 __ bind(L); | |
2670 } | |
2671 #endif | |
2672 restore_native_result(masm, ret_type, stack_slots); | |
2673 // check_forward_pending_exception jump to forward_exception if any pending | |
2674 // exception is set. The forward_exception routine expects to see the | |
2675 // exception in pending_exception and not in a register. Kind of clumsy, | |
2676 // since all folks who branch to forward_exception must have tested | |
2677 // pending_exception first and hence have it in a register already. | |
2678 __ st_ptr(I2_ex_oop, G2_thread, in_bytes(Thread::pending_exception_offset())); | |
2679 __ bind(done); | |
2680 } | |
2681 | |
2682 // Tell dtrace about this method exit | |
2683 { | |
2684 SkipIfEqual skip_if( | |
2685 masm, G3_scratch, &DTraceMethodProbes, Assembler::zero); | |
2686 save_native_result(masm, ret_type, stack_slots); | |
2687 __ set_oop_constant(JNIHandles::make_local(method()), O1); | |
2688 __ call_VM_leaf(L7_thread_cache, | |
2689 CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit), | |
2690 G2_thread, O1); | |
2691 restore_native_result(masm, ret_type, stack_slots); | |
2692 } | |
2693 | |
2694 // Clear "last Java frame" SP and PC. | |
2695 __ verify_thread(); // G2_thread must be correct | |
2696 __ reset_last_Java_frame(); | |
2697 | |
2698 // Unpack oop result | |
2699 if (ret_type == T_OBJECT || ret_type == T_ARRAY) { | |
2700 Label L; | |
2701 __ addcc(G0, I0, G0); | |
2702 __ brx(Assembler::notZero, true, Assembler::pt, L); | |
2703 __ delayed()->ld_ptr(I0, 0, I0); | |
2704 __ mov(G0, I0); | |
2705 __ bind(L); | |
2706 __ verify_oop(I0); | |
2707 } | |
2708 | |
4873
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2709 if (!is_critical_native) { |
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|
2710 // reset handle block |
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2711 __ ld_ptr(G2_thread, in_bytes(JavaThread::active_handles_offset()), L5); |
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2712 __ st_ptr(G0, L5, JNIHandleBlock::top_offset_in_bytes()); |
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2713 |
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2714 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), G3_scratch); |
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2715 check_forward_pending_exception(masm, G3_scratch); |
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2716 } |
0 | 2717 |
2718 | |
2719 // Return | |
2720 | |
2721 #ifndef _LP64 | |
2722 if (ret_type == T_LONG) { | |
2723 | |
2724 // Must leave proper result in O0,O1 and G1 (c2/tiered only) | |
2725 __ sllx(I0, 32, G1); // Shift bits into high G1 | |
2726 __ srl (I1, 0, I1); // Zero extend O1 (harmless?) | |
2727 __ or3 (I1, G1, G1); // OR 64 bits into G1 | |
2728 } | |
2729 #endif | |
2730 | |
2731 __ ret(); | |
2732 __ delayed()->restore(); | |
2733 | |
2734 __ flush(); | |
2735 | |
2736 nmethod *nm = nmethod::new_native_nmethod(method, | |
2405
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2737 compile_id, |
0 | 2738 masm->code(), |
2739 vep_offset, | |
2740 frame_complete, | |
2741 stack_slots / VMRegImpl::slots_per_word, | |
2742 (is_static ? in_ByteSize(klass_offset) : in_ByteSize(receiver_offset)), | |
2743 in_ByteSize(lock_offset), | |
2744 oop_maps); | |
4873
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2745 |
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2746 if (is_critical_native) { |
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2747 nm->set_lazy_critical_native(true); |
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2748 } |
0 | 2749 return nm; |
2750 | |
2751 } | |
2752 | |
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2753 #ifdef HAVE_DTRACE_H |
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2754 // --------------------------------------------------------------------------- |
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2755 // Generate a dtrace nmethod for a given signature. The method takes arguments |
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2756 // in the Java compiled code convention, marshals them to the native |
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2757 // abi and then leaves nops at the position you would expect to call a native |
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2758 // function. When the probe is enabled the nops are replaced with a trap |
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2759 // instruction that dtrace inserts and the trace will cause a notification |
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2760 // to dtrace. |
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2761 // |
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2762 // The probes are only able to take primitive types and java/lang/String as |
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2763 // arguments. No other java types are allowed. Strings are converted to utf8 |
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2764 // strings so that from dtrace point of view java strings are converted to C |
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2765 // strings. There is an arbitrary fixed limit on the total space that a method |
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2766 // can use for converting the strings. (256 chars per string in the signature). |
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2767 // So any java string larger then this is truncated. |
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2768 |
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2769 static int fp_offset[ConcreteRegisterImpl::number_of_registers] = { 0 }; |
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2770 static bool offsets_initialized = false; |
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2771 |
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2772 nmethod *SharedRuntime::generate_dtrace_nmethod( |
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2773 MacroAssembler *masm, methodHandle method) { |
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2774 |
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2775 |
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2776 // generate_dtrace_nmethod is guarded by a mutex so we are sure to |
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2777 // be single threaded in this method. |
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2778 assert(AdapterHandlerLibrary_lock->owned_by_self(), "must be"); |
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2779 |
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2780 // Fill in the signature array, for the calling-convention call. |
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2781 int total_args_passed = method->size_of_parameters(); |
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2782 |
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2783 BasicType* in_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_args_passed); |
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2784 VMRegPair *in_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_args_passed); |
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2785 |
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2786 // The signature we are going to use for the trap that dtrace will see |
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2787 // java/lang/String is converted. We drop "this" and any other object |
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2788 // is converted to NULL. (A one-slot java/lang/Long object reference |
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2789 // is converted to a two-slot long, which is why we double the allocation). |
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2790 BasicType* out_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_args_passed * 2); |
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2791 VMRegPair* out_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_args_passed * 2); |
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2792 |
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2793 int i=0; |
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2794 int total_strings = 0; |
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2795 int first_arg_to_pass = 0; |
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2796 int total_c_args = 0; |
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2797 |
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2798 // Skip the receiver as dtrace doesn't want to see it |
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2799 if( !method->is_static() ) { |
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2800 in_sig_bt[i++] = T_OBJECT; |
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2801 first_arg_to_pass = 1; |
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2802 } |
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2803 |
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2804 SignatureStream ss(method->signature()); |
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2805 for ( ; !ss.at_return_type(); ss.next()) { |
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2806 BasicType bt = ss.type(); |
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2807 in_sig_bt[i++] = bt; // Collect remaining bits of signature |
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2808 out_sig_bt[total_c_args++] = bt; |
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2809 if( bt == T_OBJECT) { |
2177
3582bf76420e
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2810 Symbol* s = ss.as_symbol_or_null(); |
116
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2811 if (s == vmSymbols::java_lang_String()) { |
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2812 total_strings++; |
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2813 out_sig_bt[total_c_args-1] = T_ADDRESS; |
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2814 } else if (s == vmSymbols::java_lang_Boolean() || |
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2815 s == vmSymbols::java_lang_Byte()) { |
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2816 out_sig_bt[total_c_args-1] = T_BYTE; |
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2817 } else if (s == vmSymbols::java_lang_Character() || |
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2818 s == vmSymbols::java_lang_Short()) { |
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2819 out_sig_bt[total_c_args-1] = T_SHORT; |
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2820 } else if (s == vmSymbols::java_lang_Integer() || |
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2821 s == vmSymbols::java_lang_Float()) { |
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2822 out_sig_bt[total_c_args-1] = T_INT; |
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2823 } else if (s == vmSymbols::java_lang_Long() || |
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2824 s == vmSymbols::java_lang_Double()) { |
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2825 out_sig_bt[total_c_args-1] = T_LONG; |
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2826 out_sig_bt[total_c_args++] = T_VOID; |
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2827 } |
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2828 } else if ( bt == T_LONG || bt == T_DOUBLE ) { |
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2829 in_sig_bt[i++] = T_VOID; // Longs & doubles take 2 Java slots |
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2830 // We convert double to long |
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2831 out_sig_bt[total_c_args-1] = T_LONG; |
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2832 out_sig_bt[total_c_args++] = T_VOID; |
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2833 } else if ( bt == T_FLOAT) { |
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2834 // We convert float to int |
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2835 out_sig_bt[total_c_args-1] = T_INT; |
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2836 } |
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|
2837 } |
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|
2838 |
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2839 assert(i==total_args_passed, "validly parsed signature"); |
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2840 |
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2841 // Now get the compiled-Java layout as input arguments |
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2842 int comp_args_on_stack; |
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2843 comp_args_on_stack = SharedRuntime::java_calling_convention( |
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2844 in_sig_bt, in_regs, total_args_passed, false); |
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2845 |
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2846 // We have received a description of where all the java arg are located |
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2847 // on entry to the wrapper. We need to convert these args to where |
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2848 // the a native (non-jni) function would expect them. To figure out |
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2849 // where they go we convert the java signature to a C signature and remove |
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2850 // T_VOID for any long/double we might have received. |
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2851 |
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2852 |
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2853 // Now figure out where the args must be stored and how much stack space |
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2854 // they require (neglecting out_preserve_stack_slots but space for storing |
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2855 // the 1st six register arguments). It's weird see int_stk_helper. |
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2856 // |
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2857 int out_arg_slots; |
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2858 out_arg_slots = c_calling_convention(out_sig_bt, out_regs, total_c_args); |
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2859 |
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2860 // Calculate the total number of stack slots we will need. |
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2861 |
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2862 // First count the abi requirement plus all of the outgoing args |
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2863 int stack_slots = SharedRuntime::out_preserve_stack_slots() + out_arg_slots; |
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2864 |
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2865 // Plus a temp for possible converion of float/double/long register args |
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2866 |
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2867 int conversion_temp = stack_slots; |
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2868 stack_slots += 2; |
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2869 |
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2870 |
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2871 // Now space for the string(s) we must convert |
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2872 |
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2873 int string_locs = stack_slots; |
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2874 stack_slots += total_strings * |
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2875 (max_dtrace_string_size / VMRegImpl::stack_slot_size); |
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2876 |
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2877 // Ok The space we have allocated will look like: |
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2878 // |
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2879 // |
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2880 // FP-> | | |
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2881 // |---------------------| |
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2882 // | string[n] | |
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2883 // |---------------------| <- string_locs[n] |
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2884 // | string[n-1] | |
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2885 // |---------------------| <- string_locs[n-1] |
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2886 // | ... | |
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2887 // | ... | |
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2888 // |---------------------| <- string_locs[1] |
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2889 // | string[0] | |
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2890 // |---------------------| <- string_locs[0] |
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2891 // | temp | |
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2892 // |---------------------| <- conversion_temp |
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2893 // | outbound memory | |
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2894 // | based arguments | |
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2895 // | | |
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2896 // |---------------------| |
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2897 // | | |
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2898 // SP-> | out_preserved_slots | |
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2899 // |
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2900 // |
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2901 |
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2902 // Now compute actual number of stack words we need rounding to make |
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2903 // stack properly aligned. |
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2904 stack_slots = round_to(stack_slots, 4 * VMRegImpl::slots_per_word); |
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2905 |
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2906 int stack_size = stack_slots * VMRegImpl::stack_slot_size; |
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2907 |
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2908 intptr_t start = (intptr_t)__ pc(); |
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2909 |
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2910 // First thing make an ic check to see if we should even be here |
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2911 |
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2912 { |
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2913 Label L; |
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2914 const Register temp_reg = G3_scratch; |
727 | 2915 AddressLiteral ic_miss(SharedRuntime::get_ic_miss_stub()); |
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2916 __ verify_oop(O0); |
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2917 __ ld_ptr(O0, oopDesc::klass_offset_in_bytes(), temp_reg); |
3839 | 2918 __ cmp_and_brx_short(temp_reg, G5_inline_cache_reg, Assembler::equal, Assembler::pt, L); |
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2919 |
727 | 2920 __ jump_to(ic_miss, temp_reg); |
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2921 __ delayed()->nop(); |
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2922 __ align(CodeEntryAlignment); |
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2923 __ bind(L); |
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2924 } |
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2925 |
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2926 int vep_offset = ((intptr_t)__ pc()) - start; |
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2927 |
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2928 |
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2929 // The instruction at the verified entry point must be 5 bytes or longer |
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2930 // because it can be patched on the fly by make_non_entrant. The stack bang |
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2931 // instruction fits that requirement. |
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2932 |
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2933 // Generate stack overflow check before creating frame |
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2934 __ generate_stack_overflow_check(stack_size); |
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2935 |
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2936 assert(((intptr_t)__ pc() - start - vep_offset) >= 5, |
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2937 "valid size for make_non_entrant"); |
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2938 |
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2939 // Generate a new frame for the wrapper. |
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2940 __ save(SP, -stack_size, SP); |
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2941 |
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2942 // Frame is now completed as far a size and linkage. |
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2943 |
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2944 int frame_complete = ((intptr_t)__ pc()) - start; |
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2945 |
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2946 #ifdef ASSERT |
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2947 bool reg_destroyed[RegisterImpl::number_of_registers]; |
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2948 bool freg_destroyed[FloatRegisterImpl::number_of_registers]; |
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2949 for ( int r = 0 ; r < RegisterImpl::number_of_registers ; r++ ) { |
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2950 reg_destroyed[r] = false; |
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2951 } |
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2952 for ( int f = 0 ; f < FloatRegisterImpl::number_of_registers ; f++ ) { |
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2953 freg_destroyed[f] = false; |
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2954 } |
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2955 |
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2956 #endif /* ASSERT */ |
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2957 |
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2958 VMRegPair zero; |
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2959 const Register g0 = G0; // without this we get a compiler warning (why??) |
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2960 zero.set2(g0->as_VMReg()); |
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2961 |
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2962 int c_arg, j_arg; |
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2963 |
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2964 Register conversion_off = noreg; |
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2965 |
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2966 for (j_arg = first_arg_to_pass, c_arg = 0 ; |
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2967 j_arg < total_args_passed ; j_arg++, c_arg++ ) { |
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2968 |
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2969 VMRegPair src = in_regs[j_arg]; |
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2970 VMRegPair dst = out_regs[c_arg]; |
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2971 |
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|
2972 #ifdef ASSERT |
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|
2973 if (src.first()->is_Register()) { |
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2974 assert(!reg_destroyed[src.first()->as_Register()->encoding()], "ack!"); |
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2975 } else if (src.first()->is_FloatRegister()) { |
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2976 assert(!freg_destroyed[src.first()->as_FloatRegister()->encoding( |
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2977 FloatRegisterImpl::S)], "ack!"); |
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|
2978 } |
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|
2979 if (dst.first()->is_Register()) { |
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2980 reg_destroyed[dst.first()->as_Register()->encoding()] = true; |
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2981 } else if (dst.first()->is_FloatRegister()) { |
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2982 freg_destroyed[dst.first()->as_FloatRegister()->encoding( |
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2983 FloatRegisterImpl::S)] = true; |
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|
2984 } |
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|
2985 #endif /* ASSERT */ |
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|
2986 |
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|
2987 switch (in_sig_bt[j_arg]) { |
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|
2988 case T_ARRAY: |
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kamg
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diff
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|
2989 case T_OBJECT: |
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|
2990 { |
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|
2991 if (out_sig_bt[c_arg] == T_BYTE || out_sig_bt[c_arg] == T_SHORT || |
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2992 out_sig_bt[c_arg] == T_INT || out_sig_bt[c_arg] == T_LONG) { |
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2993 // need to unbox a one-slot value |
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2994 Register in_reg = L0; |
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2995 Register tmp = L2; |
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2996 if ( src.first()->is_reg() ) { |
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2997 in_reg = src.first()->as_Register(); |
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|
2998 } else { |
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|
2999 assert(Assembler::is_simm13(reg2offset(src.first()) + STACK_BIAS), |
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|
3000 "must be"); |
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|
3001 __ ld_ptr(FP, reg2offset(src.first()) + STACK_BIAS, in_reg); |
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|
3002 } |
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|
3003 // If the final destination is an acceptable register |
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diff
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|
3004 if ( dst.first()->is_reg() ) { |
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|
3005 if ( dst.is_single_phys_reg() || out_sig_bt[c_arg] != T_LONG ) { |
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|
3006 tmp = dst.first()->as_Register(); |
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diff
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|
3007 } |
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kamg
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113
diff
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|
3008 } |
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kamg
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113
diff
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|
3009 |
018d5b58dd4f
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kamg
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113
diff
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|
3010 Label skipUnbox; |
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113
diff
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|
3011 if ( wordSize == 4 && out_sig_bt[c_arg] == T_LONG ) { |
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|
3012 __ mov(G0, tmp->successor()); |
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113
diff
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|
3013 } |
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diff
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|
3014 __ br_null(in_reg, true, Assembler::pn, skipUnbox); |
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113
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|
3015 __ delayed()->mov(G0, tmp); |
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|
3016 |
165
437d03ea40b1
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kvn
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diff
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|
3017 BasicType bt = out_sig_bt[c_arg]; |
437d03ea40b1
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|
3018 int box_offset = java_lang_boxing_object::value_offset_in_bytes(bt); |
437d03ea40b1
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|
3019 switch (bt) { |
116
018d5b58dd4f
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|
3020 case T_BYTE: |
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diff
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|
3021 __ ldub(in_reg, box_offset, tmp); break; |
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kamg
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113
diff
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|
3022 case T_SHORT: |
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6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
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diff
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|
3023 __ lduh(in_reg, box_offset, tmp); break; |
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kamg
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113
diff
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|
3024 case T_INT: |
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kamg
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diff
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|
3025 __ ld(in_reg, box_offset, tmp); break; |
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kamg
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113
diff
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|
3026 case T_LONG: |
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6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
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diff
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|
3027 __ ld_long(in_reg, box_offset, tmp); break; |
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kamg
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113
diff
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|
3028 default: ShouldNotReachHere(); |
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113
diff
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|
3029 } |
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kamg
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113
diff
changeset
|
3030 |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
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113
diff
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|
3031 __ bind(skipUnbox); |
018d5b58dd4f
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kamg
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113
diff
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|
3032 // If tmp wasn't final destination copy to final destination |
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113
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|
3033 if (tmp == L2) { |
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|
3034 VMRegPair tmp_as_VM = reg64_to_VMRegPair(L2); |
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kamg
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|
3035 if (out_sig_bt[c_arg] == T_LONG) { |
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|
3036 long_move(masm, tmp_as_VM, dst); |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
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113
diff
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|
3037 } else { |
018d5b58dd4f
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113
diff
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|
3038 move32_64(masm, tmp_as_VM, out_regs[c_arg]); |
018d5b58dd4f
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kamg
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113
diff
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|
3039 } |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3040 } |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
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|
3041 if (out_sig_bt[c_arg] == T_LONG) { |
018d5b58dd4f
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kamg
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113
diff
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|
3042 assert(out_sig_bt[c_arg+1] == T_VOID, "must be"); |
018d5b58dd4f
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kamg
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113
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|
3043 ++c_arg; // move over the T_VOID to keep the loop indices in sync |
018d5b58dd4f
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kamg
parents:
113
diff
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|
3044 } |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
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|
3045 } else if (out_sig_bt[c_arg] == T_ADDRESS) { |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
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113
diff
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|
3046 Register s = |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
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113
diff
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|
3047 src.first()->is_reg() ? src.first()->as_Register() : L2; |
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kamg
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113
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|
3048 Register d = |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
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113
diff
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|
3049 dst.first()->is_reg() ? dst.first()->as_Register() : L2; |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
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|
3050 |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
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113
diff
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|
3051 // We store the oop now so that the conversion pass can reach |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
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113
diff
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|
3052 // while in the inner frame. This will be the only store if |
018d5b58dd4f
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|
3053 // the oop is NULL. |
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113
diff
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|
3054 if (s != L2) { |
018d5b58dd4f
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kamg
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113
diff
changeset
|
3055 // src is register |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
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113
diff
changeset
|
3056 if (d != L2) { |
018d5b58dd4f
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kamg
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113
diff
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|
3057 // dst is register |
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6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
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113
diff
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|
3058 __ mov(s, d); |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
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113
diff
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|
3059 } else { |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3060 assert(Assembler::is_simm13(reg2offset(dst.first()) + |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
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113
diff
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|
3061 STACK_BIAS), "must be"); |
018d5b58dd4f
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113
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|
3062 __ st_ptr(s, SP, reg2offset(dst.first()) + STACK_BIAS); |
018d5b58dd4f
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kamg
parents:
113
diff
changeset
|
3063 } |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3064 } else { |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3065 // src not a register |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
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113
diff
changeset
|
3066 assert(Assembler::is_simm13(reg2offset(src.first()) + |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
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113
diff
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|
3067 STACK_BIAS), "must be"); |
018d5b58dd4f
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113
diff
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|
3068 __ ld_ptr(FP, reg2offset(src.first()) + STACK_BIAS, d); |
018d5b58dd4f
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kamg
parents:
113
diff
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|
3069 if (d == L2) { |
018d5b58dd4f
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113
diff
changeset
|
3070 assert(Assembler::is_simm13(reg2offset(dst.first()) + |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
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113
diff
changeset
|
3071 STACK_BIAS), "must be"); |
018d5b58dd4f
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113
diff
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|
3072 __ st_ptr(d, SP, reg2offset(dst.first()) + STACK_BIAS); |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3073 } |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3074 } |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3075 } else if (out_sig_bt[c_arg] != T_VOID) { |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
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113
diff
changeset
|
3076 // Convert the arg to NULL |
018d5b58dd4f
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kamg
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113
diff
changeset
|
3077 if (dst.first()->is_reg()) { |
018d5b58dd4f
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113
diff
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|
3078 __ mov(G0, dst.first()->as_Register()); |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3079 } else { |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3080 assert(Assembler::is_simm13(reg2offset(dst.first()) + |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
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113
diff
changeset
|
3081 STACK_BIAS), "must be"); |
018d5b58dd4f
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113
diff
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|
3082 __ st_ptr(G0, SP, reg2offset(dst.first()) + STACK_BIAS); |
018d5b58dd4f
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kamg
parents:
113
diff
changeset
|
3083 } |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3084 } |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3085 } |
018d5b58dd4f
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kamg
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113
diff
changeset
|
3086 break; |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3087 case T_VOID: |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3088 break; |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3089 |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3090 case T_FLOAT: |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3091 if (src.first()->is_stack()) { |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3092 // Stack to stack/reg is simple |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3093 move32_64(masm, src, dst); |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3094 } else { |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3095 if (dst.first()->is_reg()) { |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3096 // freg -> reg |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3097 int off = |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3098 STACK_BIAS + conversion_temp * VMRegImpl::stack_slot_size; |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3099 Register d = dst.first()->as_Register(); |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3100 if (Assembler::is_simm13(off)) { |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3101 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(), |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3102 SP, off); |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3103 __ ld(SP, off, d); |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3104 } else { |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3105 if (conversion_off == noreg) { |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3106 __ set(off, L6); |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3107 conversion_off = L6; |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3108 } |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3109 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(), |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3110 SP, conversion_off); |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3111 __ ld(SP, conversion_off , d); |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3112 } |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3113 } else { |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3114 // freg -> mem |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3115 int off = STACK_BIAS + reg2offset(dst.first()); |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3116 if (Assembler::is_simm13(off)) { |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3117 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(), |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3118 SP, off); |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3119 } else { |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3120 if (conversion_off == noreg) { |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3121 __ set(off, L6); |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3122 conversion_off = L6; |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3123 } |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3124 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(), |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3125 SP, conversion_off); |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3126 } |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3127 } |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3128 } |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3129 break; |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3130 |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3131 case T_DOUBLE: |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3132 assert( j_arg + 1 < total_args_passed && |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3133 in_sig_bt[j_arg + 1] == T_VOID && |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3134 out_sig_bt[c_arg+1] == T_VOID, "bad arg list"); |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3135 if (src.first()->is_stack()) { |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3136 // Stack to stack/reg is simple |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3137 long_move(masm, src, dst); |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3138 } else { |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3139 Register d = dst.first()->is_reg() ? dst.first()->as_Register() : L2; |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3140 |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3141 // Destination could be an odd reg on 32bit in which case |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3142 // we can't load direct to the destination. |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3143 |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3144 if (!d->is_even() && wordSize == 4) { |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3145 d = L2; |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3146 } |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3147 int off = STACK_BIAS + conversion_temp * VMRegImpl::stack_slot_size; |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3148 if (Assembler::is_simm13(off)) { |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3149 __ stf(FloatRegisterImpl::D, src.first()->as_FloatRegister(), |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3150 SP, off); |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3151 __ ld_long(SP, off, d); |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3152 } else { |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3153 if (conversion_off == noreg) { |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3154 __ set(off, L6); |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3155 conversion_off = L6; |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3156 } |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3157 __ stf(FloatRegisterImpl::D, src.first()->as_FloatRegister(), |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3158 SP, conversion_off); |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3159 __ ld_long(SP, conversion_off, d); |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3160 } |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3161 if (d == L2) { |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3162 long_move(masm, reg64_to_VMRegPair(L2), dst); |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3163 } |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3164 } |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3165 break; |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3166 |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3167 case T_LONG : |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3168 // 32bit can't do a split move of something like g1 -> O0, O1 |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3169 // so use a memory temp |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3170 if (src.is_single_phys_reg() && wordSize == 4) { |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3171 Register tmp = L2; |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3172 if (dst.first()->is_reg() && |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3173 (wordSize == 8 || dst.first()->as_Register()->is_even())) { |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3174 tmp = dst.first()->as_Register(); |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3175 } |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3176 |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3177 int off = STACK_BIAS + conversion_temp * VMRegImpl::stack_slot_size; |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3178 if (Assembler::is_simm13(off)) { |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3179 __ stx(src.first()->as_Register(), SP, off); |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3180 __ ld_long(SP, off, tmp); |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3181 } else { |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3182 if (conversion_off == noreg) { |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3183 __ set(off, L6); |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3184 conversion_off = L6; |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3185 } |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3186 __ stx(src.first()->as_Register(), SP, conversion_off); |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3187 __ ld_long(SP, conversion_off, tmp); |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3188 } |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3189 |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3190 if (tmp == L2) { |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3191 long_move(masm, reg64_to_VMRegPair(L2), dst); |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3192 } |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3193 } else { |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3194 long_move(masm, src, dst); |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3195 } |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3196 break; |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3197 |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3198 case T_ADDRESS: assert(false, "found T_ADDRESS in java args"); |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3199 |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3200 default: |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3201 move32_64(masm, src, dst); |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3202 } |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3203 } |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3204 |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3205 |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3206 // If we have any strings we must store any register based arg to the stack |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3207 // This includes any still live xmm registers too. |
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
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3208 |
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3209 if (total_strings > 0 ) { |
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3210 |
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3211 // protect all the arg registers |
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3212 __ save_frame(0); |
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3213 __ mov(G2_thread, L7_thread_cache); |
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3214 const Register L2_string_off = L2; |
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3215 |
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3216 // Get first string offset |
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3217 __ set(string_locs * VMRegImpl::stack_slot_size, L2_string_off); |
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3218 |
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3219 for (c_arg = 0 ; c_arg < total_c_args ; c_arg++ ) { |
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3220 if (out_sig_bt[c_arg] == T_ADDRESS) { |
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3221 |
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3222 VMRegPair dst = out_regs[c_arg]; |
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3223 const Register d = dst.first()->is_reg() ? |
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3224 dst.first()->as_Register()->after_save() : noreg; |
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3225 |
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3226 // It's a string the oop and it was already copied to the out arg |
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3227 // position |
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3228 if (d != noreg) { |
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3229 __ mov(d, O0); |
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3230 } else { |
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3231 assert(Assembler::is_simm13(reg2offset(dst.first()) + STACK_BIAS), |
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3232 "must be"); |
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3233 __ ld_ptr(FP, reg2offset(dst.first()) + STACK_BIAS, O0); |
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3234 } |
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3235 Label skip; |
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3236 |
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3237 __ br_null(O0, false, Assembler::pn, skip); |
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3238 __ delayed()->add(FP, L2_string_off, O1); |
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3239 |
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3240 if (d != noreg) { |
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3241 __ mov(O1, d); |
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3242 } else { |
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3243 assert(Assembler::is_simm13(reg2offset(dst.first()) + STACK_BIAS), |
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3244 "must be"); |
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3245 __ st_ptr(O1, FP, reg2offset(dst.first()) + STACK_BIAS); |
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3246 } |
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3247 |
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3248 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::get_utf), |
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3249 relocInfo::runtime_call_type); |
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3250 __ delayed()->add(L2_string_off, max_dtrace_string_size, L2_string_off); |
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3251 |
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3252 __ bind(skip); |
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3253 |
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3254 } |
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3255 |
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3256 } |
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3257 __ mov(L7_thread_cache, G2_thread); |
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3258 __ restore(); |
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3259 |
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3260 } |
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3261 |
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3262 |
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3263 // Ok now we are done. Need to place the nop that dtrace wants in order to |
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3264 // patch in the trap |
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3265 |
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3266 int patch_offset = ((intptr_t)__ pc()) - start; |
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3267 |
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3268 __ nop(); |
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3269 |
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3270 |
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3271 // Return |
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3272 |
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3273 __ ret(); |
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3274 __ delayed()->restore(); |
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3275 |
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3276 __ flush(); |
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3277 |
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3278 nmethod *nm = nmethod::new_dtrace_nmethod( |
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3279 method, masm->code(), vep_offset, patch_offset, frame_complete, |
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3280 stack_slots / VMRegImpl::slots_per_word); |
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3281 return nm; |
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3282 |
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3283 } |
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3284 |
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3285 #endif // HAVE_DTRACE_H |
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3286 |
0 | 3287 // this function returns the adjust size (in number of words) to a c2i adapter |
3288 // activation for use during deoptimization | |
3289 int Deoptimization::last_frame_adjust(int callee_parameters, int callee_locals) { | |
3290 assert(callee_locals >= callee_parameters, | |
3291 "test and remove; got more parms than locals"); | |
3292 if (callee_locals < callee_parameters) | |
3293 return 0; // No adjustment for negative locals | |
1506 | 3294 int diff = (callee_locals - callee_parameters) * Interpreter::stackElementWords; |
0 | 3295 return round_to(diff, WordsPerLong); |
3296 } | |
3297 | |
3298 // "Top of Stack" slots that may be unused by the calling convention but must | |
3299 // otherwise be preserved. | |
3300 // On Intel these are not necessary and the value can be zero. | |
3301 // On Sparc this describes the words reserved for storing a register window | |
3302 // when an interrupt occurs. | |
3303 uint SharedRuntime::out_preserve_stack_slots() { | |
3304 return frame::register_save_words * VMRegImpl::slots_per_word; | |
3305 } | |
3306 | |
3307 static void gen_new_frame(MacroAssembler* masm, bool deopt) { | |
3308 // | |
3309 // Common out the new frame generation for deopt and uncommon trap | |
3310 // | |
3311 Register G3pcs = G3_scratch; // Array of new pcs (input) | |
3312 Register Oreturn0 = O0; | |
3313 Register Oreturn1 = O1; | |
3314 Register O2UnrollBlock = O2; | |
3315 Register O3array = O3; // Array of frame sizes (input) | |
3316 Register O4array_size = O4; // number of frames (input) | |
3317 Register O7frame_size = O7; // number of frames (input) | |
3318 | |
3319 __ ld_ptr(O3array, 0, O7frame_size); | |
3320 __ sub(G0, O7frame_size, O7frame_size); | |
3321 __ save(SP, O7frame_size, SP); | |
3322 __ ld_ptr(G3pcs, 0, I7); // load frame's new pc | |
3323 | |
3324 #ifdef ASSERT | |
3325 // make sure that the frames are aligned properly | |
3326 #ifndef _LP64 | |
3327 __ btst(wordSize*2-1, SP); | |
3328 __ breakpoint_trap(Assembler::notZero); | |
3329 #endif | |
3330 #endif | |
3331 | |
3332 // Deopt needs to pass some extra live values from frame to frame | |
3333 | |
3334 if (deopt) { | |
3335 __ mov(Oreturn0->after_save(), Oreturn0); | |
3336 __ mov(Oreturn1->after_save(), Oreturn1); | |
3337 } | |
3338 | |
3339 __ mov(O4array_size->after_save(), O4array_size); | |
3340 __ sub(O4array_size, 1, O4array_size); | |
3341 __ mov(O3array->after_save(), O3array); | |
3342 __ mov(O2UnrollBlock->after_save(), O2UnrollBlock); | |
3343 __ add(G3pcs, wordSize, G3pcs); // point to next pc value | |
3344 | |
3345 #ifdef ASSERT | |
3346 // trash registers to show a clear pattern in backtraces | |
3347 __ set(0xDEAD0000, I0); | |
3348 __ add(I0, 2, I1); | |
3349 __ add(I0, 4, I2); | |
3350 __ add(I0, 6, I3); | |
3351 __ add(I0, 8, I4); | |
3352 // Don't touch I5 could have valuable savedSP | |
3353 __ set(0xDEADBEEF, L0); | |
3354 __ mov(L0, L1); | |
3355 __ mov(L0, L2); | |
3356 __ mov(L0, L3); | |
3357 __ mov(L0, L4); | |
3358 __ mov(L0, L5); | |
3359 | |
3360 // trash the return value as there is nothing to return yet | |
3361 __ set(0xDEAD0001, O7); | |
3362 #endif | |
3363 | |
3364 __ mov(SP, O5_savedSP); | |
3365 } | |
3366 | |
3367 | |
3368 static void make_new_frames(MacroAssembler* masm, bool deopt) { | |
3369 // | |
3370 // loop through the UnrollBlock info and create new frames | |
3371 // | |
3372 Register G3pcs = G3_scratch; | |
3373 Register Oreturn0 = O0; | |
3374 Register Oreturn1 = O1; | |
3375 Register O2UnrollBlock = O2; | |
3376 Register O3array = O3; | |
3377 Register O4array_size = O4; | |
3378 Label loop; | |
3379 | |
3380 // Before we make new frames, check to see if stack is available. | |
3381 // Do this after the caller's return address is on top of stack | |
3382 if (UseStackBanging) { | |
3383 // Get total frame size for interpreted frames | |
727 | 3384 __ ld(O2UnrollBlock, Deoptimization::UnrollBlock::total_frame_sizes_offset_in_bytes(), O4); |
0 | 3385 __ bang_stack_size(O4, O3, G3_scratch); |
3386 } | |
3387 | |
727 | 3388 __ ld(O2UnrollBlock, Deoptimization::UnrollBlock::number_of_frames_offset_in_bytes(), O4array_size); |
3389 __ ld_ptr(O2UnrollBlock, Deoptimization::UnrollBlock::frame_pcs_offset_in_bytes(), G3pcs); | |
3390 __ ld_ptr(O2UnrollBlock, Deoptimization::UnrollBlock::frame_sizes_offset_in_bytes(), O3array); | |
0 | 3391 |
3392 // Adjust old interpreter frame to make space for new frame's extra java locals | |
3393 // | |
3394 // We capture the original sp for the transition frame only because it is needed in | |
3395 // order to properly calculate interpreter_sp_adjustment. Even though in real life | |
3396 // every interpreter frame captures a savedSP it is only needed at the transition | |
3397 // (fortunately). If we had to have it correct everywhere then we would need to | |
3398 // be told the sp_adjustment for each frame we create. If the frame size array | |
3399 // were to have twice the frame count entries then we could have pairs [sp_adjustment, frame_size] | |
3400 // for each frame we create and keep up the illusion every where. | |
3401 // | |
3402 | |
727 | 3403 __ ld(O2UnrollBlock, Deoptimization::UnrollBlock::caller_adjustment_offset_in_bytes(), O7); |
0 | 3404 __ mov(SP, O5_savedSP); // remember initial sender's original sp before adjustment |
3405 __ sub(SP, O7, SP); | |
3406 | |
3407 #ifdef ASSERT | |
3408 // make sure that there is at least one entry in the array | |
3409 __ tst(O4array_size); | |
3410 __ breakpoint_trap(Assembler::zero); | |
3411 #endif | |
3412 | |
3413 // Now push the new interpreter frames | |
3414 __ bind(loop); | |
3415 | |
3416 // allocate a new frame, filling the registers | |
3417 | |
3418 gen_new_frame(masm, deopt); // allocate an interpreter frame | |
3419 | |
3839 | 3420 __ cmp_zero_and_br(Assembler::notZero, O4array_size, loop); |
0 | 3421 __ delayed()->add(O3array, wordSize, O3array); |
3422 __ ld_ptr(G3pcs, 0, O7); // load final frame new pc | |
3423 | |
3424 } | |
3425 | |
3426 //------------------------------generate_deopt_blob---------------------------- | |
3427 // Ought to generate an ideal graph & compile, but here's some SPARC ASM | |
3428 // instead. | |
3429 void SharedRuntime::generate_deopt_blob() { | |
3430 // allocate space for the code | |
3431 ResourceMark rm; | |
3432 // setup code generation tools | |
3433 int pad = VerifyThread ? 512 : 0;// Extra slop space for more verify code | |
3434 #ifdef _LP64 | |
3435 CodeBuffer buffer("deopt_blob", 2100+pad, 512); | |
3436 #else | |
3437 // Measured 8/7/03 at 1212 in 32bit debug build (no VerifyThread) | |
3438 // Measured 8/7/03 at 1396 in 32bit debug build (VerifyThread) | |
3439 CodeBuffer buffer("deopt_blob", 1600+pad, 512); | |
3440 #endif /* _LP64 */ | |
3441 MacroAssembler* masm = new MacroAssembler(&buffer); | |
3442 FloatRegister Freturn0 = F0; | |
3443 Register Greturn1 = G1; | |
3444 Register Oreturn0 = O0; | |
3445 Register Oreturn1 = O1; | |
3446 Register O2UnrollBlock = O2; | |
1037 | 3447 Register L0deopt_mode = L0; |
3448 Register G4deopt_mode = G4_scratch; | |
0 | 3449 int frame_size_words; |
727 | 3450 Address saved_Freturn0_addr(FP, -sizeof(double) + STACK_BIAS); |
0 | 3451 #if !defined(_LP64) && defined(COMPILER2) |
727 | 3452 Address saved_Greturn1_addr(FP, -sizeof(double) -sizeof(jlong) + STACK_BIAS); |
0 | 3453 #endif |
3454 Label cont; | |
3455 | |
3456 OopMapSet *oop_maps = new OopMapSet(); | |
3457 | |
3458 // | |
3459 // This is the entry point for code which is returning to a de-optimized | |
3460 // frame. | |
3461 // The steps taken by this frame are as follows: | |
3462 // - push a dummy "register_save" and save the return values (O0, O1, F0/F1, G1) | |
3463 // and all potentially live registers (at a pollpoint many registers can be live). | |
3464 // | |
3465 // - call the C routine: Deoptimization::fetch_unroll_info (this function | |
3466 // returns information about the number and size of interpreter frames | |
3467 // which are equivalent to the frame which is being deoptimized) | |
3468 // - deallocate the unpack frame, restoring only results values. Other | |
3469 // volatile registers will now be captured in the vframeArray as needed. | |
3470 // - deallocate the deoptimization frame | |
3471 // - in a loop using the information returned in the previous step | |
3472 // push new interpreter frames (take care to propagate the return | |
3473 // values through each new frame pushed) | |
3474 // - create a dummy "unpack_frame" and save the return values (O0, O1, F0) | |
3475 // - call the C routine: Deoptimization::unpack_frames (this function | |
3476 // lays out values on the interpreter frame which was just created) | |
3477 // - deallocate the dummy unpack_frame | |
3478 // - ensure that all the return values are correctly set and then do | |
3479 // a return to the interpreter entry point | |
3480 // | |
3481 // Refer to the following methods for more information: | |
3482 // - Deoptimization::fetch_unroll_info | |
3483 // - Deoptimization::unpack_frames | |
3484 | |
3485 OopMap* map = NULL; | |
3486 | |
3487 int start = __ offset(); | |
3488 | |
3489 // restore G2, the trampoline destroyed it | |
3490 __ get_thread(); | |
3491 | |
3492 // On entry we have been called by the deoptimized nmethod with a call that | |
3493 // replaced the original call (or safepoint polling location) so the deoptimizing | |
3494 // pc is now in O7. Return values are still in the expected places | |
3495 | |
3496 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_words); | |
3839 | 3497 __ ba(cont); |
1037 | 3498 __ delayed()->mov(Deoptimization::Unpack_deopt, L0deopt_mode); |
0 | 3499 |
3500 int exception_offset = __ offset() - start; | |
3501 | |
3502 // restore G2, the trampoline destroyed it | |
3503 __ get_thread(); | |
3504 | |
3505 // On entry we have been jumped to by the exception handler (or exception_blob | |
3506 // for server). O0 contains the exception oop and O7 contains the original | |
3507 // exception pc. So if we push a frame here it will look to the | |
3508 // stack walking code (fetch_unroll_info) just like a normal call so | |
3509 // state will be extracted normally. | |
3510 | |
3511 // save exception oop in JavaThread and fall through into the | |
3512 // exception_in_tls case since they are handled in same way except | |
3513 // for where the pending exception is kept. | |
727 | 3514 __ st_ptr(Oexception, G2_thread, JavaThread::exception_oop_offset()); |
0 | 3515 |
3516 // | |
3517 // Vanilla deoptimization with an exception pending in exception_oop | |
3518 // | |
3519 int exception_in_tls_offset = __ offset() - start; | |
3520 | |
3521 // No need to update oop_map as each call to save_live_registers will produce identical oopmap | |
3522 (void) RegisterSaver::save_live_registers(masm, 0, &frame_size_words); | |
3523 | |
3524 // Restore G2_thread | |
3525 __ get_thread(); | |
3526 | |
3527 #ifdef ASSERT | |
3528 { | |
3529 // verify that there is really an exception oop in exception_oop | |
3530 Label has_exception; | |
727 | 3531 __ ld_ptr(G2_thread, JavaThread::exception_oop_offset(), Oexception); |
3839 | 3532 __ br_notnull_short(Oexception, Assembler::pt, has_exception); |
0 | 3533 __ stop("no exception in thread"); |
3534 __ bind(has_exception); | |
3535 | |
3536 // verify that there is no pending exception | |
3537 Label no_pending_exception; | |
727 | 3538 Address exception_addr(G2_thread, Thread::pending_exception_offset()); |
0 | 3539 __ ld_ptr(exception_addr, Oexception); |
3839 | 3540 __ br_null_short(Oexception, Assembler::pt, no_pending_exception); |
0 | 3541 __ stop("must not have pending exception here"); |
3542 __ bind(no_pending_exception); | |
3543 } | |
3544 #endif | |
3545 | |
3839 | 3546 __ ba(cont); |
1037 | 3547 __ delayed()->mov(Deoptimization::Unpack_exception, L0deopt_mode);; |
0 | 3548 |
3549 // | |
3550 // Reexecute entry, similar to c2 uncommon trap | |
3551 // | |
3552 int reexecute_offset = __ offset() - start; | |
3553 | |
3554 // No need to update oop_map as each call to save_live_registers will produce identical oopmap | |
3555 (void) RegisterSaver::save_live_registers(masm, 0, &frame_size_words); | |
3556 | |
1037 | 3557 __ mov(Deoptimization::Unpack_reexecute, L0deopt_mode); |
0 | 3558 |
3559 __ bind(cont); | |
3560 | |
3561 __ set_last_Java_frame(SP, noreg); | |
3562 | |
3563 // do the call by hand so we can get the oopmap | |
3564 | |
3565 __ mov(G2_thread, L7_thread_cache); | |
3566 __ call(CAST_FROM_FN_PTR(address, Deoptimization::fetch_unroll_info), relocInfo::runtime_call_type); | |
3567 __ delayed()->mov(G2_thread, O0); | |
3568 | |
3569 // Set an oopmap for the call site this describes all our saved volatile registers | |
3570 | |
3571 oop_maps->add_gc_map( __ offset()-start, map); | |
3572 | |
3573 __ mov(L7_thread_cache, G2_thread); | |
3574 | |
3575 __ reset_last_Java_frame(); | |
3576 | |
3577 // NOTE: we know that only O0/O1 will be reloaded by restore_result_registers | |
3578 // so this move will survive | |
3579 | |
1037 | 3580 __ mov(L0deopt_mode, G4deopt_mode); |
0 | 3581 |
3582 __ mov(O0, O2UnrollBlock->after_save()); | |
3583 | |
3584 RegisterSaver::restore_result_registers(masm); | |
3585 | |
3586 Label noException; | |
3839 | 3587 __ cmp_and_br_short(G4deopt_mode, Deoptimization::Unpack_exception, Assembler::notEqual, Assembler::pt, noException); |
0 | 3588 |
3589 // Move the pending exception from exception_oop to Oexception so | |
3590 // the pending exception will be picked up the interpreter. | |
3591 __ ld_ptr(G2_thread, in_bytes(JavaThread::exception_oop_offset()), Oexception); | |
3592 __ st_ptr(G0, G2_thread, in_bytes(JavaThread::exception_oop_offset())); | |
3593 __ bind(noException); | |
3594 | |
3595 // deallocate the deoptimization frame taking care to preserve the return values | |
3596 __ mov(Oreturn0, Oreturn0->after_save()); | |
3597 __ mov(Oreturn1, Oreturn1->after_save()); | |
3598 __ mov(O2UnrollBlock, O2UnrollBlock->after_save()); | |
3599 __ restore(); | |
3600 | |
3601 // Allocate new interpreter frame(s) and possible c2i adapter frame | |
3602 | |
3603 make_new_frames(masm, true); | |
3604 | |
3605 // push a dummy "unpack_frame" taking care of float return values and | |
3606 // call Deoptimization::unpack_frames to have the unpacker layout | |
3607 // information in the interpreter frames just created and then return | |
3608 // to the interpreter entry point | |
3609 __ save(SP, -frame_size_words*wordSize, SP); | |
3610 __ stf(FloatRegisterImpl::D, Freturn0, saved_Freturn0_addr); | |
3611 #if !defined(_LP64) | |
3612 #if defined(COMPILER2) | |
1783 | 3613 // 32-bit 1-register longs return longs in G1 |
3614 __ stx(Greturn1, saved_Greturn1_addr); | |
0 | 3615 #endif |
3616 __ set_last_Java_frame(SP, noreg); | |
1037 | 3617 __ call_VM_leaf(L7_thread_cache, CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames), G2_thread, G4deopt_mode); |
0 | 3618 #else |
3619 // LP64 uses g4 in set_last_Java_frame | |
1037 | 3620 __ mov(G4deopt_mode, O1); |
0 | 3621 __ set_last_Java_frame(SP, G0); |
3622 __ call_VM_leaf(L7_thread_cache, CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames), G2_thread, O1); | |
3623 #endif | |
3624 __ reset_last_Java_frame(); | |
3625 __ ldf(FloatRegisterImpl::D, saved_Freturn0_addr, Freturn0); | |
3626 | |
3627 #if !defined(_LP64) && defined(COMPILER2) | |
3628 // In 32 bit, C2 returns longs in G1 so restore the saved G1 into | |
1783 | 3629 // I0/I1 if the return value is long. |
3630 Label not_long; | |
3839 | 3631 __ cmp_and_br_short(O0,T_LONG, Assembler::notEqual, Assembler::pt, not_long); |
1783 | 3632 __ ldd(saved_Greturn1_addr,I0); |
3633 __ bind(not_long); | |
0 | 3634 #endif |
3635 __ ret(); | |
3636 __ delayed()->restore(); | |
3637 | |
3638 masm->flush(); | |
3639 _deopt_blob = DeoptimizationBlob::create(&buffer, oop_maps, 0, exception_offset, reexecute_offset, frame_size_words); | |
3640 _deopt_blob->set_unpack_with_exception_in_tls_offset(exception_in_tls_offset); | |
3641 } | |
3642 | |
3643 #ifdef COMPILER2 | |
3644 | |
3645 //------------------------------generate_uncommon_trap_blob-------------------- | |
3646 // Ought to generate an ideal graph & compile, but here's some SPARC ASM | |
3647 // instead. | |
3648 void SharedRuntime::generate_uncommon_trap_blob() { | |
3649 // allocate space for the code | |
3650 ResourceMark rm; | |
3651 // setup code generation tools | |
3652 int pad = VerifyThread ? 512 : 0; | |
3653 #ifdef _LP64 | |
3654 CodeBuffer buffer("uncommon_trap_blob", 2700+pad, 512); | |
3655 #else | |
3656 // Measured 8/7/03 at 660 in 32bit debug build (no VerifyThread) | |
3657 // Measured 8/7/03 at 1028 in 32bit debug build (VerifyThread) | |
3658 CodeBuffer buffer("uncommon_trap_blob", 2000+pad, 512); | |
3659 #endif | |
3660 MacroAssembler* masm = new MacroAssembler(&buffer); | |
3661 Register O2UnrollBlock = O2; | |
3662 Register O2klass_index = O2; | |
3663 | |
3664 // | |
3665 // This is the entry point for all traps the compiler takes when it thinks | |
3666 // it cannot handle further execution of compilation code. The frame is | |
3667 // deoptimized in these cases and converted into interpreter frames for | |
3668 // execution | |
3669 // The steps taken by this frame are as follows: | |
3670 // - push a fake "unpack_frame" | |
3671 // - call the C routine Deoptimization::uncommon_trap (this function | |
3672 // packs the current compiled frame into vframe arrays and returns | |
3673 // information about the number and size of interpreter frames which | |
3674 // are equivalent to the frame which is being deoptimized) | |
3675 // - deallocate the "unpack_frame" | |
3676 // - deallocate the deoptimization frame | |
3677 // - in a loop using the information returned in the previous step | |
3678 // push interpreter frames; | |
3679 // - create a dummy "unpack_frame" | |
3680 // - call the C routine: Deoptimization::unpack_frames (this function | |
3681 // lays out values on the interpreter frame which was just created) | |
3682 // - deallocate the dummy unpack_frame | |
3683 // - return to the interpreter entry point | |
3684 // | |
3685 // Refer to the following methods for more information: | |
3686 // - Deoptimization::uncommon_trap | |
3687 // - Deoptimization::unpack_frame | |
3688 | |
3689 // the unloaded class index is in O0 (first parameter to this blob) | |
3690 | |
3691 // push a dummy "unpack_frame" | |
3692 // and call Deoptimization::uncommon_trap to pack the compiled frame into | |
3693 // vframe array and return the UnrollBlock information | |
3694 __ save_frame(0); | |
3695 __ set_last_Java_frame(SP, noreg); | |
3696 __ mov(I0, O2klass_index); | |
3697 __ call_VM_leaf(L7_thread_cache, CAST_FROM_FN_PTR(address, Deoptimization::uncommon_trap), G2_thread, O2klass_index); | |
3698 __ reset_last_Java_frame(); | |
3699 __ mov(O0, O2UnrollBlock->after_save()); | |
3700 __ restore(); | |
3701 | |
3702 // deallocate the deoptimized frame taking care to preserve the return values | |
3703 __ mov(O2UnrollBlock, O2UnrollBlock->after_save()); | |
3704 __ restore(); | |
3705 | |
3706 // Allocate new interpreter frame(s) and possible c2i adapter frame | |
3707 | |
3708 make_new_frames(masm, false); | |
3709 | |
3710 // push a dummy "unpack_frame" taking care of float return values and | |
3711 // call Deoptimization::unpack_frames to have the unpacker layout | |
3712 // information in the interpreter frames just created and then return | |
3713 // to the interpreter entry point | |
3714 __ save_frame(0); | |
3715 __ set_last_Java_frame(SP, noreg); | |
3716 __ mov(Deoptimization::Unpack_uncommon_trap, O3); // indicate it is the uncommon trap case | |
3717 __ call_VM_leaf(L7_thread_cache, CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames), G2_thread, O3); | |
3718 __ reset_last_Java_frame(); | |
3719 __ ret(); | |
3720 __ delayed()->restore(); | |
3721 | |
3722 masm->flush(); | |
3723 _uncommon_trap_blob = UncommonTrapBlob::create(&buffer, NULL, __ total_frame_size_in_bytes(0)/wordSize); | |
3724 } | |
3725 | |
3726 #endif // COMPILER2 | |
3727 | |
3728 //------------------------------generate_handler_blob------------------- | |
3729 // | |
3730 // Generate a special Compile2Runtime blob that saves all registers, and sets | |
3731 // up an OopMap. | |
3732 // | |
3733 // This blob is jumped to (via a breakpoint and the signal handler) from a | |
3734 // safepoint in compiled code. On entry to this blob, O7 contains the | |
3735 // address in the original nmethod at which we should resume normal execution. | |
3736 // Thus, this blob looks like a subroutine which must preserve lots of | |
3737 // registers and return normally. Note that O7 is never register-allocated, | |
3738 // so it is guaranteed to be free here. | |
3739 // | |
3740 | |
3741 // The hardest part of what this blob must do is to save the 64-bit %o | |
3742 // registers in the 32-bit build. A simple 'save' turn the %o's to %i's and | |
3743 // an interrupt will chop off their heads. Making space in the caller's frame | |
3744 // first will let us save the 64-bit %o's before save'ing, but we cannot hand | |
3745 // the adjusted FP off to the GC stack-crawler: this will modify the caller's | |
3746 // SP and mess up HIS OopMaps. So we first adjust the caller's SP, then save | |
3747 // the 64-bit %o's, then do a save, then fixup the caller's SP (our FP). | |
3748 // Tricky, tricky, tricky... | |
3749 | |
3753
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3750 SafepointBlob* SharedRuntime::generate_handler_blob(address call_ptr, bool cause_return) { |
0 | 3751 assert (StubRoutines::forward_exception_entry() != NULL, "must be generated before"); |
3752 | |
3753 // allocate space for the code | |
3754 ResourceMark rm; | |
3755 // setup code generation tools | |
3756 // Measured 8/7/03 at 896 in 32bit debug build (no VerifyThread) | |
3757 // Measured 8/7/03 at 1080 in 32bit debug build (VerifyThread) | |
3758 // even larger with TraceJumps | |
3759 int pad = TraceJumps ? 512 : 0; | |
3760 CodeBuffer buffer("handler_blob", 1600 + pad, 512); | |
3761 MacroAssembler* masm = new MacroAssembler(&buffer); | |
3762 int frame_size_words; | |
3763 OopMapSet *oop_maps = new OopMapSet(); | |
3764 OopMap* map = NULL; | |
3765 | |
3766 int start = __ offset(); | |
3767 | |
3768 // If this causes a return before the processing, then do a "restore" | |
3769 if (cause_return) { | |
3770 __ restore(); | |
3771 } else { | |
3772 // Make it look like we were called via the poll | |
3773 // so that frame constructor always sees a valid return address | |
3774 __ ld_ptr(G2_thread, in_bytes(JavaThread::saved_exception_pc_offset()), O7); | |
3775 __ sub(O7, frame::pc_return_offset, O7); | |
3776 } | |
3777 | |
3778 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_words); | |
3779 | |
3780 // setup last_Java_sp (blows G4) | |
3781 __ set_last_Java_frame(SP, noreg); | |
3782 | |
3783 // call into the runtime to handle illegal instructions exception | |
3784 // Do not use call_VM_leaf, because we need to make a GC map at this call site. | |
3785 __ mov(G2_thread, O0); | |
3786 __ save_thread(L7_thread_cache); | |
3787 __ call(call_ptr); | |
3788 __ delayed()->nop(); | |
3789 | |
3790 // Set an oopmap for the call site. | |
3791 // We need this not only for callee-saved registers, but also for volatile | |
3792 // registers that the compiler might be keeping live across a safepoint. | |
3793 | |
3794 oop_maps->add_gc_map( __ offset() - start, map); | |
3795 | |
3796 __ restore_thread(L7_thread_cache); | |
3797 // clear last_Java_sp | |
3798 __ reset_last_Java_frame(); | |
3799 | |
3800 // Check for exceptions | |
3801 Label pending; | |
3802 | |
3803 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), O1); | |
3839 | 3804 __ br_notnull_short(O1, Assembler::pn, pending); |
0 | 3805 |
3806 RegisterSaver::restore_live_registers(masm); | |
3807 | |
3808 // We are back the the original state on entry and ready to go. | |
3809 | |
3810 __ retl(); | |
3811 __ delayed()->nop(); | |
3812 | |
3813 // Pending exception after the safepoint | |
3814 | |
3815 __ bind(pending); | |
3816 | |
3817 RegisterSaver::restore_live_registers(masm); | |
3818 | |
3819 // We are back the the original state on entry. | |
3820 | |
3821 // Tail-call forward_exception_entry, with the issuing PC in O7, | |
3822 // so it looks like the original nmethod called forward_exception_entry. | |
3823 __ set((intptr_t)StubRoutines::forward_exception_entry(), O0); | |
3824 __ JMP(O0, 0); | |
3825 __ delayed()->nop(); | |
3826 | |
3827 // ------------- | |
3828 // make sure all code is generated | |
3829 masm->flush(); | |
3830 | |
3831 // return exception blob | |
3832 return SafepointBlob::create(&buffer, oop_maps, frame_size_words); | |
3833 } | |
3834 | |
3835 // | |
3836 // generate_resolve_blob - call resolution (static/virtual/opt-virtual/ic-miss | |
3837 // | |
3838 // Generate a stub that calls into vm to find out the proper destination | |
3839 // of a java call. All the argument registers are live at this point | |
3840 // but since this is generic code we don't know what they are and the caller | |
3841 // must do any gc of the args. | |
3842 // | |
3753
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3843 RuntimeStub* SharedRuntime::generate_resolve_blob(address destination, const char* name) { |
0 | 3844 assert (StubRoutines::forward_exception_entry() != NULL, "must be generated before"); |
3845 | |
3846 // allocate space for the code | |
3847 ResourceMark rm; | |
3848 // setup code generation tools | |
3849 // Measured 8/7/03 at 896 in 32bit debug build (no VerifyThread) | |
3850 // Measured 8/7/03 at 1080 in 32bit debug build (VerifyThread) | |
3851 // even larger with TraceJumps | |
3852 int pad = TraceJumps ? 512 : 0; | |
3853 CodeBuffer buffer(name, 1600 + pad, 512); | |
3854 MacroAssembler* masm = new MacroAssembler(&buffer); | |
3855 int frame_size_words; | |
3856 OopMapSet *oop_maps = new OopMapSet(); | |
3857 OopMap* map = NULL; | |
3858 | |
3859 int start = __ offset(); | |
3860 | |
3861 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_words); | |
3862 | |
3863 int frame_complete = __ offset(); | |
3864 | |
3865 // setup last_Java_sp (blows G4) | |
3866 __ set_last_Java_frame(SP, noreg); | |
3867 | |
3868 // call into the runtime to handle illegal instructions exception | |
3869 // Do not use call_VM_leaf, because we need to make a GC map at this call site. | |
3870 __ mov(G2_thread, O0); | |
3871 __ save_thread(L7_thread_cache); | |
3872 __ call(destination, relocInfo::runtime_call_type); | |
3873 __ delayed()->nop(); | |
3874 | |
3875 // O0 contains the address we are going to jump to assuming no exception got installed | |
3876 | |
3877 // Set an oopmap for the call site. | |
3878 // We need this not only for callee-saved registers, but also for volatile | |
3879 // registers that the compiler might be keeping live across a safepoint. | |
3880 | |
3881 oop_maps->add_gc_map( __ offset() - start, map); | |
3882 | |
3883 __ restore_thread(L7_thread_cache); | |
3884 // clear last_Java_sp | |
3885 __ reset_last_Java_frame(); | |
3886 | |
3887 // Check for exceptions | |
3888 Label pending; | |
3889 | |
3890 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), O1); | |
3839 | 3891 __ br_notnull_short(O1, Assembler::pn, pending); |
0 | 3892 |
3893 // get the returned methodOop | |
3894 | |
3895 __ get_vm_result(G5_method); | |
3896 __ stx(G5_method, SP, RegisterSaver::G5_offset()+STACK_BIAS); | |
3897 | |
3898 // O0 is where we want to jump, overwrite G3 which is saved and scratch | |
3899 | |
3900 __ stx(O0, SP, RegisterSaver::G3_offset()+STACK_BIAS); | |
3901 | |
3902 RegisterSaver::restore_live_registers(masm); | |
3903 | |
3904 // We are back the the original state on entry and ready to go. | |
3905 | |
3906 __ JMP(G3, 0); | |
3907 __ delayed()->nop(); | |
3908 | |
3909 // Pending exception after the safepoint | |
3910 | |
3911 __ bind(pending); | |
3912 | |
3913 RegisterSaver::restore_live_registers(masm); | |
3914 | |
3915 // We are back the the original state on entry. | |
3916 | |
3917 // Tail-call forward_exception_entry, with the issuing PC in O7, | |
3918 // so it looks like the original nmethod called forward_exception_entry. | |
3919 __ set((intptr_t)StubRoutines::forward_exception_entry(), O0); | |
3920 __ JMP(O0, 0); | |
3921 __ delayed()->nop(); | |
3922 | |
3923 // ------------- | |
3924 // make sure all code is generated | |
3925 masm->flush(); | |
3926 | |
3927 // return the blob | |
3928 // frame_size_words or bytes?? | |
3929 return RuntimeStub::new_runtime_stub(name, &buffer, frame_complete, frame_size_words, oop_maps, true); | |
3930 } |