Mercurial > hg > truffle
annotate src/cpu/x86/vm/vm_version_x86.cpp @ 4749:7ab5f6318694
7125934: Add a fast unordered timestamp capability to Hotspot on x86/x64
Summary: Add rdtsc detection and inline generation.
Reviewed-by: kamg, dholmes
Contributed-by: karen.kinnear@oracle.com
author | phh |
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date | Sun, 01 Jan 2012 11:17:59 -0500 |
parents | f08d439fab8c |
children | 22cee0ee8927 |
rev | line source |
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585 | 1 /* |
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2 * Copyright (c) 1997, 2011, Oracle and/or its affiliates. All rights reserved. |
585 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
4 * | |
5 * This code is free software; you can redistribute it and/or modify it | |
6 * under the terms of the GNU General Public License version 2 only, as | |
7 * published by the Free Software Foundation. | |
8 * | |
9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 * version 2 for more details (a copy is included in the LICENSE file that | |
13 * accompanied this code). | |
14 * | |
15 * You should have received a copy of the GNU General Public License version | |
16 * 2 along with this work; if not, write to the Free Software Foundation, | |
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
18 * | |
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
585 | 22 * |
23 */ | |
24 | |
1972 | 25 #include "precompiled.hpp" |
26 #include "assembler_x86.inline.hpp" | |
27 #include "memory/resourceArea.hpp" | |
28 #include "runtime/java.hpp" | |
29 #include "runtime/stubCodeGenerator.hpp" | |
30 #include "vm_version_x86.hpp" | |
31 #ifdef TARGET_OS_FAMILY_linux | |
32 # include "os_linux.inline.hpp" | |
33 #endif | |
34 #ifdef TARGET_OS_FAMILY_solaris | |
35 # include "os_solaris.inline.hpp" | |
36 #endif | |
37 #ifdef TARGET_OS_FAMILY_windows | |
38 # include "os_windows.inline.hpp" | |
39 #endif | |
3960 | 40 #ifdef TARGET_OS_FAMILY_bsd |
41 # include "os_bsd.inline.hpp" | |
42 #endif | |
585 | 43 |
44 | |
45 int VM_Version::_cpu; | |
46 int VM_Version::_model; | |
47 int VM_Version::_stepping; | |
48 int VM_Version::_cpuFeatures; | |
49 const char* VM_Version::_features_str = ""; | |
50 VM_Version::CpuidInfo VM_Version::_cpuid_info = { 0, }; | |
51 | |
52 static BufferBlob* stub_blob; | |
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53 static const int stub_size = 500; |
585 | 54 |
55 extern "C" { | |
56 typedef void (*getPsrInfo_stub_t)(void*); | |
57 } | |
58 static getPsrInfo_stub_t getPsrInfo_stub = NULL; | |
59 | |
60 | |
61 class VM_Version_StubGenerator: public StubCodeGenerator { | |
62 public: | |
63 | |
64 VM_Version_StubGenerator(CodeBuffer *c) : StubCodeGenerator(c) {} | |
65 | |
66 address generate_getPsrInfo() { | |
67 // Flags to test CPU type. | |
68 const uint32_t EFL_AC = 0x40000; | |
69 const uint32_t EFL_ID = 0x200000; | |
70 // Values for when we don't have a CPUID instruction. | |
71 const int CPU_FAMILY_SHIFT = 8; | |
72 const uint32_t CPU_FAMILY_386 = (3 << CPU_FAMILY_SHIFT); | |
73 const uint32_t CPU_FAMILY_486 = (4 << CPU_FAMILY_SHIFT); | |
74 | |
1622 | 75 Label detect_486, cpu486, detect_586, std_cpuid1, std_cpuid4; |
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76 Label ext_cpuid1, ext_cpuid5, ext_cpuid7, done; |
585 | 77 |
78 StubCodeMark mark(this, "VM_Version", "getPsrInfo_stub"); | |
79 # define __ _masm-> | |
80 | |
81 address start = __ pc(); | |
82 | |
83 // | |
84 // void getPsrInfo(VM_Version::CpuidInfo* cpuid_info); | |
85 // | |
86 // LP64: rcx and rdx are first and second argument registers on windows | |
87 | |
88 __ push(rbp); | |
89 #ifdef _LP64 | |
90 __ mov(rbp, c_rarg0); // cpuid_info address | |
91 #else | |
92 __ movptr(rbp, Address(rsp, 8)); // cpuid_info address | |
93 #endif | |
94 __ push(rbx); | |
95 __ push(rsi); | |
96 __ pushf(); // preserve rbx, and flags | |
97 __ pop(rax); | |
98 __ push(rax); | |
99 __ mov(rcx, rax); | |
100 // | |
101 // if we are unable to change the AC flag, we have a 386 | |
102 // | |
103 __ xorl(rax, EFL_AC); | |
104 __ push(rax); | |
105 __ popf(); | |
106 __ pushf(); | |
107 __ pop(rax); | |
108 __ cmpptr(rax, rcx); | |
109 __ jccb(Assembler::notEqual, detect_486); | |
110 | |
111 __ movl(rax, CPU_FAMILY_386); | |
112 __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax); | |
113 __ jmp(done); | |
114 | |
115 // | |
116 // If we are unable to change the ID flag, we have a 486 which does | |
117 // not support the "cpuid" instruction. | |
118 // | |
119 __ bind(detect_486); | |
120 __ mov(rax, rcx); | |
121 __ xorl(rax, EFL_ID); | |
122 __ push(rax); | |
123 __ popf(); | |
124 __ pushf(); | |
125 __ pop(rax); | |
126 __ cmpptr(rcx, rax); | |
127 __ jccb(Assembler::notEqual, detect_586); | |
128 | |
129 __ bind(cpu486); | |
130 __ movl(rax, CPU_FAMILY_486); | |
131 __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax); | |
132 __ jmp(done); | |
133 | |
134 // | |
135 // At this point, we have a chip which supports the "cpuid" instruction | |
136 // | |
137 __ bind(detect_586); | |
138 __ xorl(rax, rax); | |
139 __ cpuid(); | |
140 __ orl(rax, rax); | |
141 __ jcc(Assembler::equal, cpu486); // if cpuid doesn't support an input | |
142 // value of at least 1, we give up and | |
143 // assume a 486 | |
144 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); | |
145 __ movl(Address(rsi, 0), rax); | |
146 __ movl(Address(rsi, 4), rbx); | |
147 __ movl(Address(rsi, 8), rcx); | |
148 __ movl(Address(rsi,12), rdx); | |
149 | |
1622 | 150 __ cmpl(rax, 0xa); // Is cpuid(0xB) supported? |
151 __ jccb(Assembler::belowEqual, std_cpuid4); | |
152 | |
153 // | |
154 // cpuid(0xB) Processor Topology | |
155 // | |
156 __ movl(rax, 0xb); | |
157 __ xorl(rcx, rcx); // Threads level | |
158 __ cpuid(); | |
159 | |
160 __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB0_offset()))); | |
161 __ movl(Address(rsi, 0), rax); | |
162 __ movl(Address(rsi, 4), rbx); | |
163 __ movl(Address(rsi, 8), rcx); | |
164 __ movl(Address(rsi,12), rdx); | |
165 | |
166 __ movl(rax, 0xb); | |
167 __ movl(rcx, 1); // Cores level | |
168 __ cpuid(); | |
169 __ push(rax); | |
170 __ andl(rax, 0x1f); // Determine if valid topology level | |
171 __ orl(rax, rbx); // eax[4:0] | ebx[0:15] == 0 indicates invalid level | |
172 __ andl(rax, 0xffff); | |
173 __ pop(rax); | |
174 __ jccb(Assembler::equal, std_cpuid4); | |
175 | |
176 __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB1_offset()))); | |
177 __ movl(Address(rsi, 0), rax); | |
178 __ movl(Address(rsi, 4), rbx); | |
179 __ movl(Address(rsi, 8), rcx); | |
180 __ movl(Address(rsi,12), rdx); | |
181 | |
182 __ movl(rax, 0xb); | |
183 __ movl(rcx, 2); // Packages level | |
184 __ cpuid(); | |
185 __ push(rax); | |
186 __ andl(rax, 0x1f); // Determine if valid topology level | |
187 __ orl(rax, rbx); // eax[4:0] | ebx[0:15] == 0 indicates invalid level | |
188 __ andl(rax, 0xffff); | |
189 __ pop(rax); | |
190 __ jccb(Assembler::equal, std_cpuid4); | |
191 | |
192 __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB2_offset()))); | |
193 __ movl(Address(rsi, 0), rax); | |
194 __ movl(Address(rsi, 4), rbx); | |
195 __ movl(Address(rsi, 8), rcx); | |
196 __ movl(Address(rsi,12), rdx); | |
585 | 197 |
198 // | |
199 // cpuid(0x4) Deterministic cache params | |
200 // | |
1622 | 201 __ bind(std_cpuid4); |
585 | 202 __ movl(rax, 4); |
1622 | 203 __ cmpl(rax, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); // Is cpuid(0x4) supported? |
204 __ jccb(Assembler::greater, std_cpuid1); | |
205 | |
585 | 206 __ xorl(rcx, rcx); // L1 cache |
207 __ cpuid(); | |
208 __ push(rax); | |
209 __ andl(rax, 0x1f); // Determine if valid cache parameters used | |
210 __ orl(rax, rax); // eax[4:0] == 0 indicates invalid cache | |
211 __ pop(rax); | |
212 __ jccb(Assembler::equal, std_cpuid1); | |
213 | |
214 __ lea(rsi, Address(rbp, in_bytes(VM_Version::dcp_cpuid4_offset()))); | |
215 __ movl(Address(rsi, 0), rax); | |
216 __ movl(Address(rsi, 4), rbx); | |
217 __ movl(Address(rsi, 8), rcx); | |
218 __ movl(Address(rsi,12), rdx); | |
219 | |
220 // | |
221 // Standard cpuid(0x1) | |
222 // | |
223 __ bind(std_cpuid1); | |
224 __ movl(rax, 1); | |
225 __ cpuid(); | |
226 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset()))); | |
227 __ movl(Address(rsi, 0), rax); | |
228 __ movl(Address(rsi, 4), rbx); | |
229 __ movl(Address(rsi, 8), rcx); | |
230 __ movl(Address(rsi,12), rdx); | |
231 | |
232 __ movl(rax, 0x80000000); | |
233 __ cpuid(); | |
234 __ cmpl(rax, 0x80000000); // Is cpuid(0x80000001) supported? | |
235 __ jcc(Assembler::belowEqual, done); | |
236 __ cmpl(rax, 0x80000004); // Is cpuid(0x80000005) supported? | |
237 __ jccb(Assembler::belowEqual, ext_cpuid1); | |
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238 __ cmpl(rax, 0x80000006); // Is cpuid(0x80000007) supported? |
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239 __ jccb(Assembler::belowEqual, ext_cpuid5); |
585 | 240 __ cmpl(rax, 0x80000007); // Is cpuid(0x80000008) supported? |
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241 __ jccb(Assembler::belowEqual, ext_cpuid7); |
585 | 242 // |
243 // Extended cpuid(0x80000008) | |
244 // | |
245 __ movl(rax, 0x80000008); | |
246 __ cpuid(); | |
247 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid8_offset()))); | |
248 __ movl(Address(rsi, 0), rax); | |
249 __ movl(Address(rsi, 4), rbx); | |
250 __ movl(Address(rsi, 8), rcx); | |
251 __ movl(Address(rsi,12), rdx); | |
252 | |
253 // | |
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254 // Extended cpuid(0x80000007) |
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255 // |
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256 __ bind(ext_cpuid7); |
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257 __ movl(rax, 0x80000007); |
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258 __ cpuid(); |
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259 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid7_offset()))); |
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260 __ movl(Address(rsi, 0), rax); |
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261 __ movl(Address(rsi, 4), rbx); |
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262 __ movl(Address(rsi, 8), rcx); |
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263 __ movl(Address(rsi,12), rdx); |
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264 |
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265 // |
585 | 266 // Extended cpuid(0x80000005) |
267 // | |
268 __ bind(ext_cpuid5); | |
269 __ movl(rax, 0x80000005); | |
270 __ cpuid(); | |
271 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid5_offset()))); | |
272 __ movl(Address(rsi, 0), rax); | |
273 __ movl(Address(rsi, 4), rbx); | |
274 __ movl(Address(rsi, 8), rcx); | |
275 __ movl(Address(rsi,12), rdx); | |
276 | |
277 // | |
278 // Extended cpuid(0x80000001) | |
279 // | |
280 __ bind(ext_cpuid1); | |
281 __ movl(rax, 0x80000001); | |
282 __ cpuid(); | |
283 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid1_offset()))); | |
284 __ movl(Address(rsi, 0), rax); | |
285 __ movl(Address(rsi, 4), rbx); | |
286 __ movl(Address(rsi, 8), rcx); | |
287 __ movl(Address(rsi,12), rdx); | |
288 | |
289 // | |
290 // return | |
291 // | |
292 __ bind(done); | |
293 __ popf(); | |
294 __ pop(rsi); | |
295 __ pop(rbx); | |
296 __ pop(rbp); | |
297 __ ret(0); | |
298 | |
299 # undef __ | |
300 | |
301 return start; | |
302 }; | |
303 }; | |
304 | |
305 | |
306 void VM_Version::get_processor_features() { | |
307 | |
308 _cpu = 4; // 486 by default | |
309 _model = 0; | |
310 _stepping = 0; | |
311 _cpuFeatures = 0; | |
312 _logical_processors_per_package = 1; | |
313 | |
314 if (!Use486InstrsOnly) { | |
315 // Get raw processor info | |
316 getPsrInfo_stub(&_cpuid_info); | |
317 assert_is_initialized(); | |
318 _cpu = extended_cpu_family(); | |
319 _model = extended_cpu_model(); | |
320 _stepping = cpu_stepping(); | |
321 | |
322 if (cpu_family() > 4) { // it supports CPUID | |
323 _cpuFeatures = feature_flags(); | |
324 // Logical processors are only available on P4s and above, | |
325 // and only if hyperthreading is available. | |
326 _logical_processors_per_package = logical_processor_count(); | |
327 } | |
328 } | |
329 | |
330 _supports_cx8 = supports_cmpxchg8(); | |
331 | |
332 #ifdef _LP64 | |
333 // OS should support SSE for x64 and hardware should support at least SSE2. | |
334 if (!VM_Version::supports_sse2()) { | |
335 vm_exit_during_initialization("Unknown x64 processor: SSE2 not supported"); | |
336 } | |
1060 | 337 // in 64 bit the use of SSE2 is the minimum |
338 if (UseSSE < 2) UseSSE = 2; | |
585 | 339 #endif |
340 | |
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341 #ifdef AMD64 |
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342 // flush_icache_stub have to be generated first. |
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343 // That is why Icache line size is hard coded in ICache class, |
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344 // see icache_x86.hpp. It is also the reason why we can't use |
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345 // clflush instruction in 32-bit VM since it could be running |
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346 // on CPU which does not support it. |
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347 // |
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348 // The only thing we can do is to verify that flushed |
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349 // ICache::line_size has correct value. |
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350 guarantee(_cpuid_info.std_cpuid1_edx.bits.clflush != 0, "clflush is not supported"); |
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351 // clflush_size is size in quadwords (8 bytes). |
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352 guarantee(_cpuid_info.std_cpuid1_ebx.bits.clflush_size == 8, "such clflush size is not supported"); |
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353 #endif |
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354 |
585 | 355 // If the OS doesn't support SSE, we can't use this feature even if the HW does |
356 if (!os::supports_sse()) | |
357 _cpuFeatures &= ~(CPU_SSE|CPU_SSE2|CPU_SSE3|CPU_SSSE3|CPU_SSE4A|CPU_SSE4_1|CPU_SSE4_2); | |
358 | |
359 if (UseSSE < 4) { | |
360 _cpuFeatures &= ~CPU_SSE4_1; | |
361 _cpuFeatures &= ~CPU_SSE4_2; | |
362 } | |
363 | |
364 if (UseSSE < 3) { | |
365 _cpuFeatures &= ~CPU_SSE3; | |
366 _cpuFeatures &= ~CPU_SSSE3; | |
367 _cpuFeatures &= ~CPU_SSE4A; | |
368 } | |
369 | |
370 if (UseSSE < 2) | |
371 _cpuFeatures &= ~CPU_SSE2; | |
372 | |
373 if (UseSSE < 1) | |
374 _cpuFeatures &= ~CPU_SSE; | |
375 | |
376 if (logical_processors_per_package() == 1) { | |
377 // HT processor could be installed on a system which doesn't support HT. | |
378 _cpuFeatures &= ~CPU_HT; | |
379 } | |
380 | |
381 char buf[256]; | |
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382 jio_snprintf(buf, sizeof(buf), "(%u cores per cpu, %u threads per core) family %d model %d stepping %d%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s", |
585 | 383 cores_per_cpu(), threads_per_core(), |
384 cpu_family(), _model, _stepping, | |
385 (supports_cmov() ? ", cmov" : ""), | |
386 (supports_cmpxchg8() ? ", cx8" : ""), | |
387 (supports_fxsr() ? ", fxsr" : ""), | |
388 (supports_mmx() ? ", mmx" : ""), | |
389 (supports_sse() ? ", sse" : ""), | |
390 (supports_sse2() ? ", sse2" : ""), | |
391 (supports_sse3() ? ", sse3" : ""), | |
392 (supports_ssse3()? ", ssse3": ""), | |
393 (supports_sse4_1() ? ", sse4.1" : ""), | |
394 (supports_sse4_2() ? ", sse4.2" : ""), | |
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395 (supports_popcnt() ? ", popcnt" : ""), |
585 | 396 (supports_mmx_ext() ? ", mmxext" : ""), |
2479 | 397 (supports_3dnow_prefetch() ? ", 3dnowpref" : ""), |
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398 (supports_lzcnt() ? ", lzcnt": ""), |
585 | 399 (supports_sse4a() ? ", sse4a": ""), |
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400 (supports_ht() ? ", ht": ""), |
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401 (supports_tsc() ? ", tsc": ""), |
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402 (supports_tscinv_bit() ? ", tscinvbit": ""), |
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403 (supports_tscinv() ? ", tscinv": "")); |
585 | 404 _features_str = strdup(buf); |
405 | |
406 // UseSSE is set to the smaller of what hardware supports and what | |
407 // the command line requires. I.e., you cannot set UseSSE to 2 on | |
408 // older Pentiums which do not support it. | |
409 if( UseSSE > 4 ) UseSSE=4; | |
410 if( UseSSE < 0 ) UseSSE=0; | |
411 if( !supports_sse4_1() ) // Drop to 3 if no SSE4 support | |
412 UseSSE = MIN2((intx)3,UseSSE); | |
413 if( !supports_sse3() ) // Drop to 2 if no SSE3 support | |
414 UseSSE = MIN2((intx)2,UseSSE); | |
415 if( !supports_sse2() ) // Drop to 1 if no SSE2 support | |
416 UseSSE = MIN2((intx)1,UseSSE); | |
417 if( !supports_sse () ) // Drop to 0 if no SSE support | |
418 UseSSE = 0; | |
419 | |
420 // On new cpus instructions which update whole XMM register should be used | |
421 // to prevent partial register stall due to dependencies on high half. | |
422 // | |
423 // UseXmmLoadAndClearUpper == true --> movsd(xmm, mem) | |
424 // UseXmmLoadAndClearUpper == false --> movlpd(xmm, mem) | |
425 // UseXmmRegToRegMoveAll == true --> movaps(xmm, xmm), movapd(xmm, xmm). | |
426 // UseXmmRegToRegMoveAll == false --> movss(xmm, xmm), movsd(xmm, xmm). | |
427 | |
428 if( is_amd() ) { // AMD cpus specific settings | |
429 if( supports_sse2() && FLAG_IS_DEFAULT(UseAddressNop) ) { | |
430 // Use it on new AMD cpus starting from Opteron. | |
431 UseAddressNop = true; | |
432 } | |
433 if( supports_sse2() && FLAG_IS_DEFAULT(UseNewLongLShift) ) { | |
434 // Use it on new AMD cpus starting from Opteron. | |
435 UseNewLongLShift = true; | |
436 } | |
437 if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) { | |
438 if( supports_sse4a() ) { | |
439 UseXmmLoadAndClearUpper = true; // use movsd only on '10h' Opteron | |
440 } else { | |
441 UseXmmLoadAndClearUpper = false; | |
442 } | |
443 } | |
444 if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) { | |
445 if( supports_sse4a() ) { | |
446 UseXmmRegToRegMoveAll = true; // use movaps, movapd only on '10h' | |
447 } else { | |
448 UseXmmRegToRegMoveAll = false; | |
449 } | |
450 } | |
451 if( FLAG_IS_DEFAULT(UseXmmI2F) ) { | |
452 if( supports_sse4a() ) { | |
453 UseXmmI2F = true; | |
454 } else { | |
455 UseXmmI2F = false; | |
456 } | |
457 } | |
458 if( FLAG_IS_DEFAULT(UseXmmI2D) ) { | |
459 if( supports_sse4a() ) { | |
460 UseXmmI2D = true; | |
461 } else { | |
462 UseXmmI2D = false; | |
463 } | |
464 } | |
2406 | 465 if( FLAG_IS_DEFAULT(UseSSE42Intrinsics) ) { |
466 if( supports_sse4_2() && UseSSE >= 4 ) { | |
467 UseSSE42Intrinsics = true; | |
468 } | |
469 } | |
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470 |
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471 // Use count leading zeros count instruction if available. |
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472 if (supports_lzcnt()) { |
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473 if (FLAG_IS_DEFAULT(UseCountLeadingZerosInstruction)) { |
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474 UseCountLeadingZerosInstruction = true; |
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475 } |
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476 } |
2358 | 477 |
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478 // some defaults for AMD family 15h |
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479 if ( cpu_family() == 0x15 ) { |
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480 // On family 15h processors default is no sw prefetch |
2358 | 481 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) { |
482 AllocatePrefetchStyle = 0; | |
483 } | |
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484 // Also, if some other prefetch style is specified, default instruction type is PREFETCHW |
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485 if (FLAG_IS_DEFAULT(AllocatePrefetchInstr)) { |
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486 AllocatePrefetchInstr = 3; |
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487 } |
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488 // On family 15h processors use XMM and UnalignedLoadStores for Array Copy |
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489 if( FLAG_IS_DEFAULT(UseXMMForArrayCopy) ) { |
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490 UseXMMForArrayCopy = true; |
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491 } |
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492 if( FLAG_IS_DEFAULT(UseUnalignedLoadStores) && UseXMMForArrayCopy ) { |
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493 UseUnalignedLoadStores = true; |
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494 } |
2358 | 495 } |
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496 |
585 | 497 } |
498 | |
499 if( is_intel() ) { // Intel cpus specific settings | |
500 if( FLAG_IS_DEFAULT(UseStoreImmI16) ) { | |
501 UseStoreImmI16 = false; // don't use it on Intel cpus | |
502 } | |
503 if( cpu_family() == 6 || cpu_family() == 15 ) { | |
504 if( FLAG_IS_DEFAULT(UseAddressNop) ) { | |
505 // Use it on all Intel cpus starting from PentiumPro | |
506 UseAddressNop = true; | |
507 } | |
508 } | |
509 if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) { | |
510 UseXmmLoadAndClearUpper = true; // use movsd on all Intel cpus | |
511 } | |
512 if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) { | |
513 if( supports_sse3() ) { | |
514 UseXmmRegToRegMoveAll = true; // use movaps, movapd on new Intel cpus | |
515 } else { | |
516 UseXmmRegToRegMoveAll = false; | |
517 } | |
518 } | |
519 if( cpu_family() == 6 && supports_sse3() ) { // New Intel cpus | |
520 #ifdef COMPILER2 | |
521 if( FLAG_IS_DEFAULT(MaxLoopPad) ) { | |
522 // For new Intel cpus do the next optimization: | |
523 // don't align the beginning of a loop if there are enough instructions | |
524 // left (NumberOfLoopInstrToAlign defined in c2_globals.hpp) | |
525 // in current fetch line (OptoLoopAlignment) or the padding | |
526 // is big (> MaxLoopPad). | |
527 // Set MaxLoopPad to 11 for new Intel cpus to reduce number of | |
528 // generated NOP instructions. 11 is the largest size of one | |
529 // address NOP instruction '0F 1F' (see Assembler::nop(i)). | |
530 MaxLoopPad = 11; | |
531 } | |
532 #endif // COMPILER2 | |
533 if( FLAG_IS_DEFAULT(UseXMMForArrayCopy) ) { | |
534 UseXMMForArrayCopy = true; // use SSE2 movq on new Intel cpus | |
535 } | |
536 if( supports_sse4_2() && supports_ht() ) { // Newest Intel cpus | |
537 if( FLAG_IS_DEFAULT(UseUnalignedLoadStores) && UseXMMForArrayCopy ) { | |
538 UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus | |
539 } | |
540 } | |
681 | 541 if( supports_sse4_2() && UseSSE >= 4 ) { |
542 if( FLAG_IS_DEFAULT(UseSSE42Intrinsics)) { | |
543 UseSSE42Intrinsics = true; | |
544 } | |
545 } | |
585 | 546 } |
547 } | |
548 | |
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549 // Use population count instruction if available. |
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550 if (supports_popcnt()) { |
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551 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) { |
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552 UsePopCountInstruction = true; |
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553 } |
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554 } |
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555 |
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556 #ifdef COMPILER2 |
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557 if (UseFPUForSpilling) { |
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558 if (UseSSE < 2) { |
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559 // Only supported with SSE2+ |
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560 FLAG_SET_DEFAULT(UseFPUForSpilling, false); |
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561 } |
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562 } |
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563 #endif |
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564 |
585 | 565 assert(0 <= ReadPrefetchInstr && ReadPrefetchInstr <= 3, "invalid value"); |
566 assert(0 <= AllocatePrefetchInstr && AllocatePrefetchInstr <= 3, "invalid value"); | |
567 | |
568 // set valid Prefetch instruction | |
569 if( ReadPrefetchInstr < 0 ) ReadPrefetchInstr = 0; | |
570 if( ReadPrefetchInstr > 3 ) ReadPrefetchInstr = 3; | |
2479 | 571 if( ReadPrefetchInstr == 3 && !supports_3dnow_prefetch() ) ReadPrefetchInstr = 0; |
572 if( !supports_sse() && supports_3dnow_prefetch() ) ReadPrefetchInstr = 3; | |
585 | 573 |
574 if( AllocatePrefetchInstr < 0 ) AllocatePrefetchInstr = 0; | |
575 if( AllocatePrefetchInstr > 3 ) AllocatePrefetchInstr = 3; | |
2479 | 576 if( AllocatePrefetchInstr == 3 && !supports_3dnow_prefetch() ) AllocatePrefetchInstr=0; |
577 if( !supports_sse() && supports_3dnow_prefetch() ) AllocatePrefetchInstr = 3; | |
585 | 578 |
579 // Allocation prefetch settings | |
3854 | 580 intx cache_line_size = prefetch_data_size(); |
585 | 581 if( cache_line_size > AllocatePrefetchStepSize ) |
582 AllocatePrefetchStepSize = cache_line_size; | |
3854 | 583 |
585 | 584 assert(AllocatePrefetchLines > 0, "invalid value"); |
3854 | 585 if( AllocatePrefetchLines < 1 ) // set valid value in product VM |
586 AllocatePrefetchLines = 3; | |
587 assert(AllocateInstancePrefetchLines > 0, "invalid value"); | |
588 if( AllocateInstancePrefetchLines < 1 ) // set valid value in product VM | |
589 AllocateInstancePrefetchLines = 1; | |
585 | 590 |
591 AllocatePrefetchDistance = allocate_prefetch_distance(); | |
592 AllocatePrefetchStyle = allocate_prefetch_style(); | |
593 | |
1622 | 594 if( is_intel() && cpu_family() == 6 && supports_sse3() ) { |
595 if( AllocatePrefetchStyle == 2 ) { // watermark prefetching on Core | |
585 | 596 #ifdef _LP64 |
1622 | 597 AllocatePrefetchDistance = 384; |
585 | 598 #else |
1622 | 599 AllocatePrefetchDistance = 320; |
585 | 600 #endif |
1622 | 601 } |
602 if( supports_sse4_2() && supports_ht() ) { // Nehalem based cpus | |
603 AllocatePrefetchDistance = 192; | |
604 AllocatePrefetchLines = 4; | |
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605 #ifdef COMPILER2 |
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606 if (AggressiveOpts && FLAG_IS_DEFAULT(UseFPUForSpilling)) { |
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607 FLAG_SET_DEFAULT(UseFPUForSpilling, true); |
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608 } |
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609 #endif |
1622 | 610 } |
585 | 611 } |
612 assert(AllocatePrefetchDistance % AllocatePrefetchStepSize == 0, "invalid value"); | |
613 | |
614 #ifdef _LP64 | |
615 // Prefetch settings | |
616 PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes(); | |
617 PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes(); | |
618 PrefetchFieldsAhead = prefetch_fields_ahead(); | |
619 #endif | |
620 | |
621 #ifndef PRODUCT | |
622 if (PrintMiscellaneous && Verbose) { | |
623 tty->print_cr("Logical CPUs per core: %u", | |
624 logical_processors_per_package()); | |
625 tty->print_cr("UseSSE=%d",UseSSE); | |
3854 | 626 tty->print("Allocation"); |
2479 | 627 if (AllocatePrefetchStyle <= 0 || UseSSE == 0 && !supports_3dnow_prefetch()) { |
3854 | 628 tty->print_cr(": no prefetching"); |
585 | 629 } else { |
3854 | 630 tty->print(" prefetching: "); |
2479 | 631 if (UseSSE == 0 && supports_3dnow_prefetch()) { |
585 | 632 tty->print("PREFETCHW"); |
633 } else if (UseSSE >= 1) { | |
634 if (AllocatePrefetchInstr == 0) { | |
635 tty->print("PREFETCHNTA"); | |
636 } else if (AllocatePrefetchInstr == 1) { | |
637 tty->print("PREFETCHT0"); | |
638 } else if (AllocatePrefetchInstr == 2) { | |
639 tty->print("PREFETCHT2"); | |
640 } else if (AllocatePrefetchInstr == 3) { | |
641 tty->print("PREFETCHW"); | |
642 } | |
643 } | |
644 if (AllocatePrefetchLines > 1) { | |
3854 | 645 tty->print_cr(" at distance %d, %d lines of %d bytes", AllocatePrefetchDistance, AllocatePrefetchLines, AllocatePrefetchStepSize); |
585 | 646 } else { |
3854 | 647 tty->print_cr(" at distance %d, one line of %d bytes", AllocatePrefetchDistance, AllocatePrefetchStepSize); |
585 | 648 } |
649 } | |
650 | |
651 if (PrefetchCopyIntervalInBytes > 0) { | |
652 tty->print_cr("PrefetchCopyIntervalInBytes %d", PrefetchCopyIntervalInBytes); | |
653 } | |
654 if (PrefetchScanIntervalInBytes > 0) { | |
655 tty->print_cr("PrefetchScanIntervalInBytes %d", PrefetchScanIntervalInBytes); | |
656 } | |
657 if (PrefetchFieldsAhead > 0) { | |
658 tty->print_cr("PrefetchFieldsAhead %d", PrefetchFieldsAhead); | |
659 } | |
660 } | |
661 #endif // !PRODUCT | |
662 } | |
663 | |
664 void VM_Version::initialize() { | |
665 ResourceMark rm; | |
666 // Making this stub must be FIRST use of assembler | |
667 | |
668 stub_blob = BufferBlob::create("getPsrInfo_stub", stub_size); | |
669 if (stub_blob == NULL) { | |
670 vm_exit_during_initialization("Unable to allocate getPsrInfo_stub"); | |
671 } | |
1748 | 672 CodeBuffer c(stub_blob); |
585 | 673 VM_Version_StubGenerator g(&c); |
674 getPsrInfo_stub = CAST_TO_FN_PTR(getPsrInfo_stub_t, | |
675 g.generate_getPsrInfo()); | |
676 | |
677 get_processor_features(); | |
678 } |