Mercurial > hg > truffle
annotate src/cpu/sparc/vm/sparc.ad @ 181:823298b11afc
6709165: Tests hang or misbahve with HS 13.0-b01 on solaris-sparcv9
Reviewed-by: kvn, jrose
| author | never |
|---|---|
| date | Wed, 04 Jun 2008 21:56:27 -0700 |
| parents | 437d03ea40b1 |
| children | 44abbb0d4c18 |
| rev | line source |
|---|---|
| 0 | 1 // |
| 2 // Copyright 1998-2007 Sun Microsystems, Inc. All Rights Reserved. | |
| 3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
| 4 // | |
| 5 // This code is free software; you can redistribute it and/or modify it | |
| 6 // under the terms of the GNU General Public License version 2 only, as | |
| 7 // published by the Free Software Foundation. | |
| 8 // | |
| 9 // This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 // version 2 for more details (a copy is included in the LICENSE file that | |
| 13 // accompanied this code). | |
| 14 // | |
| 15 // You should have received a copy of the GNU General Public License version | |
| 16 // 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 // | |
| 19 // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
| 20 // CA 95054 USA or visit www.sun.com if you need additional information or | |
| 21 // have any questions. | |
| 22 // | |
| 23 // | |
| 24 | |
| 25 // SPARC Architecture Description File | |
| 26 | |
| 27 //----------REGISTER DEFINITION BLOCK------------------------------------------ | |
| 28 // This information is used by the matcher and the register allocator to | |
| 29 // describe individual registers and classes of registers within the target | |
| 30 // archtecture. | |
| 31 register %{ | |
| 32 //----------Architecture Description Register Definitions---------------------- | |
| 33 // General Registers | |
| 34 // "reg_def" name ( register save type, C convention save type, | |
| 35 // ideal register type, encoding, vm name ); | |
| 36 // Register Save Types: | |
| 37 // | |
| 38 // NS = No-Save: The register allocator assumes that these registers | |
| 39 // can be used without saving upon entry to the method, & | |
| 40 // that they do not need to be saved at call sites. | |
| 41 // | |
| 42 // SOC = Save-On-Call: The register allocator assumes that these registers | |
| 43 // can be used without saving upon entry to the method, | |
| 44 // but that they must be saved at call sites. | |
| 45 // | |
| 46 // SOE = Save-On-Entry: The register allocator assumes that these registers | |
| 47 // must be saved before using them upon entry to the | |
| 48 // method, but they do not need to be saved at call | |
| 49 // sites. | |
| 50 // | |
| 51 // AS = Always-Save: The register allocator assumes that these registers | |
| 52 // must be saved before using them upon entry to the | |
| 53 // method, & that they must be saved at call sites. | |
| 54 // | |
| 55 // Ideal Register Type is used to determine how to save & restore a | |
| 56 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get | |
| 57 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI. | |
| 58 // | |
| 59 // The encoding number is the actual bit-pattern placed into the opcodes. | |
| 60 | |
| 61 | |
| 62 // ---------------------------- | |
| 63 // Integer/Long Registers | |
| 64 // ---------------------------- | |
| 65 | |
| 66 // Need to expose the hi/lo aspect of 64-bit registers | |
| 67 // This register set is used for both the 64-bit build and | |
| 68 // the 32-bit build with 1-register longs. | |
| 69 | |
| 70 // Global Registers 0-7 | |
| 71 reg_def R_G0H( NS, NS, Op_RegI,128, G0->as_VMReg()->next()); | |
| 72 reg_def R_G0 ( NS, NS, Op_RegI, 0, G0->as_VMReg()); | |
| 73 reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next()); | |
| 74 reg_def R_G1 (SOC, SOC, Op_RegI, 1, G1->as_VMReg()); | |
| 75 reg_def R_G2H( NS, NS, Op_RegI,130, G2->as_VMReg()->next()); | |
| 76 reg_def R_G2 ( NS, NS, Op_RegI, 2, G2->as_VMReg()); | |
| 77 reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next()); | |
| 78 reg_def R_G3 (SOC, SOC, Op_RegI, 3, G3->as_VMReg()); | |
| 79 reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next()); | |
| 80 reg_def R_G4 (SOC, SOC, Op_RegI, 4, G4->as_VMReg()); | |
| 81 reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next()); | |
| 82 reg_def R_G5 (SOC, SOC, Op_RegI, 5, G5->as_VMReg()); | |
| 83 reg_def R_G6H( NS, NS, Op_RegI,134, G6->as_VMReg()->next()); | |
| 84 reg_def R_G6 ( NS, NS, Op_RegI, 6, G6->as_VMReg()); | |
| 85 reg_def R_G7H( NS, NS, Op_RegI,135, G7->as_VMReg()->next()); | |
| 86 reg_def R_G7 ( NS, NS, Op_RegI, 7, G7->as_VMReg()); | |
| 87 | |
| 88 // Output Registers 0-7 | |
| 89 reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next()); | |
| 90 reg_def R_O0 (SOC, SOC, Op_RegI, 8, O0->as_VMReg()); | |
| 91 reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next()); | |
| 92 reg_def R_O1 (SOC, SOC, Op_RegI, 9, O1->as_VMReg()); | |
| 93 reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next()); | |
| 94 reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg()); | |
| 95 reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next()); | |
| 96 reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg()); | |
| 97 reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next()); | |
| 98 reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg()); | |
| 99 reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next()); | |
| 100 reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg()); | |
| 101 reg_def R_SPH( NS, NS, Op_RegI,142, SP->as_VMReg()->next()); | |
| 102 reg_def R_SP ( NS, NS, Op_RegI, 14, SP->as_VMReg()); | |
| 103 reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next()); | |
| 104 reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg()); | |
| 105 | |
| 106 // Local Registers 0-7 | |
| 107 reg_def R_L0H( NS, NS, Op_RegI,144, L0->as_VMReg()->next()); | |
| 108 reg_def R_L0 ( NS, NS, Op_RegI, 16, L0->as_VMReg()); | |
| 109 reg_def R_L1H( NS, NS, Op_RegI,145, L1->as_VMReg()->next()); | |
| 110 reg_def R_L1 ( NS, NS, Op_RegI, 17, L1->as_VMReg()); | |
| 111 reg_def R_L2H( NS, NS, Op_RegI,146, L2->as_VMReg()->next()); | |
| 112 reg_def R_L2 ( NS, NS, Op_RegI, 18, L2->as_VMReg()); | |
| 113 reg_def R_L3H( NS, NS, Op_RegI,147, L3->as_VMReg()->next()); | |
| 114 reg_def R_L3 ( NS, NS, Op_RegI, 19, L3->as_VMReg()); | |
| 115 reg_def R_L4H( NS, NS, Op_RegI,148, L4->as_VMReg()->next()); | |
| 116 reg_def R_L4 ( NS, NS, Op_RegI, 20, L4->as_VMReg()); | |
| 117 reg_def R_L5H( NS, NS, Op_RegI,149, L5->as_VMReg()->next()); | |
| 118 reg_def R_L5 ( NS, NS, Op_RegI, 21, L5->as_VMReg()); | |
| 119 reg_def R_L6H( NS, NS, Op_RegI,150, L6->as_VMReg()->next()); | |
| 120 reg_def R_L6 ( NS, NS, Op_RegI, 22, L6->as_VMReg()); | |
| 121 reg_def R_L7H( NS, NS, Op_RegI,151, L7->as_VMReg()->next()); | |
| 122 reg_def R_L7 ( NS, NS, Op_RegI, 23, L7->as_VMReg()); | |
| 123 | |
| 124 // Input Registers 0-7 | |
| 125 reg_def R_I0H( NS, NS, Op_RegI,152, I0->as_VMReg()->next()); | |
| 126 reg_def R_I0 ( NS, NS, Op_RegI, 24, I0->as_VMReg()); | |
| 127 reg_def R_I1H( NS, NS, Op_RegI,153, I1->as_VMReg()->next()); | |
| 128 reg_def R_I1 ( NS, NS, Op_RegI, 25, I1->as_VMReg()); | |
| 129 reg_def R_I2H( NS, NS, Op_RegI,154, I2->as_VMReg()->next()); | |
| 130 reg_def R_I2 ( NS, NS, Op_RegI, 26, I2->as_VMReg()); | |
| 131 reg_def R_I3H( NS, NS, Op_RegI,155, I3->as_VMReg()->next()); | |
| 132 reg_def R_I3 ( NS, NS, Op_RegI, 27, I3->as_VMReg()); | |
| 133 reg_def R_I4H( NS, NS, Op_RegI,156, I4->as_VMReg()->next()); | |
| 134 reg_def R_I4 ( NS, NS, Op_RegI, 28, I4->as_VMReg()); | |
| 135 reg_def R_I5H( NS, NS, Op_RegI,157, I5->as_VMReg()->next()); | |
| 136 reg_def R_I5 ( NS, NS, Op_RegI, 29, I5->as_VMReg()); | |
| 137 reg_def R_FPH( NS, NS, Op_RegI,158, FP->as_VMReg()->next()); | |
| 138 reg_def R_FP ( NS, NS, Op_RegI, 30, FP->as_VMReg()); | |
| 139 reg_def R_I7H( NS, NS, Op_RegI,159, I7->as_VMReg()->next()); | |
| 140 reg_def R_I7 ( NS, NS, Op_RegI, 31, I7->as_VMReg()); | |
| 141 | |
| 142 // ---------------------------- | |
| 143 // Float/Double Registers | |
| 144 // ---------------------------- | |
| 145 | |
| 146 // Float Registers | |
| 147 reg_def R_F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg()); | |
| 148 reg_def R_F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg()); | |
| 149 reg_def R_F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg()); | |
| 150 reg_def R_F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg()); | |
| 151 reg_def R_F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg()); | |
| 152 reg_def R_F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg()); | |
| 153 reg_def R_F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg()); | |
| 154 reg_def R_F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg()); | |
| 155 reg_def R_F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg()); | |
| 156 reg_def R_F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg()); | |
| 157 reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg()); | |
| 158 reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg()); | |
| 159 reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg()); | |
| 160 reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg()); | |
| 161 reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg()); | |
| 162 reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg()); | |
| 163 reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg()); | |
| 164 reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg()); | |
| 165 reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg()); | |
| 166 reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg()); | |
| 167 reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg()); | |
| 168 reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg()); | |
| 169 reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg()); | |
| 170 reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg()); | |
| 171 reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg()); | |
| 172 reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg()); | |
| 173 reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg()); | |
| 174 reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg()); | |
| 175 reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg()); | |
| 176 reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg()); | |
| 177 reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg()); | |
| 178 reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg()); | |
| 179 | |
| 180 // Double Registers | |
| 181 // The rules of ADL require that double registers be defined in pairs. | |
| 182 // Each pair must be two 32-bit values, but not necessarily a pair of | |
| 183 // single float registers. In each pair, ADLC-assigned register numbers | |
| 184 // must be adjacent, with the lower number even. Finally, when the | |
| 185 // CPU stores such a register pair to memory, the word associated with | |
| 186 // the lower ADLC-assigned number must be stored to the lower address. | |
| 187 | |
| 188 // These definitions specify the actual bit encodings of the sparc | |
| 189 // double fp register numbers. FloatRegisterImpl in register_sparc.hpp | |
| 190 // wants 0-63, so we have to convert every time we want to use fp regs | |
| 191 // with the macroassembler, using reg_to_DoubleFloatRegister_object(). | |
| 192 // 255 is a flag meaning 'dont go here'. | |
| 193 // I believe we can't handle callee-save doubles D32 and up until | |
| 194 // the place in the sparc stack crawler that asserts on the 255 is | |
| 195 // fixed up. | |
| 196 reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg()); | |
| 197 reg_def R_D32 (SOC, SOC, Op_RegD, 1, F32->as_VMReg()->next()); | |
| 198 reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg()); | |
| 199 reg_def R_D34 (SOC, SOC, Op_RegD, 3, F34->as_VMReg()->next()); | |
| 200 reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg()); | |
| 201 reg_def R_D36 (SOC, SOC, Op_RegD, 5, F36->as_VMReg()->next()); | |
| 202 reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg()); | |
| 203 reg_def R_D38 (SOC, SOC, Op_RegD, 7, F38->as_VMReg()->next()); | |
| 204 reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg()); | |
| 205 reg_def R_D40 (SOC, SOC, Op_RegD, 9, F40->as_VMReg()->next()); | |
| 206 reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg()); | |
| 207 reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg()->next()); | |
| 208 reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg()); | |
| 209 reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg()->next()); | |
| 210 reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg()); | |
| 211 reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg()->next()); | |
| 212 reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg()); | |
| 213 reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg()->next()); | |
| 214 reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg()); | |
| 215 reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg()->next()); | |
| 216 reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg()); | |
| 217 reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg()->next()); | |
| 218 reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg()); | |
| 219 reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg()->next()); | |
| 220 reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg()); | |
| 221 reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg()->next()); | |
| 222 reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg()); | |
| 223 reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg()->next()); | |
| 224 reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg()); | |
| 225 reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg()->next()); | |
| 226 reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg()); | |
| 227 reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg()->next()); | |
| 228 | |
| 229 | |
| 230 // ---------------------------- | |
| 231 // Special Registers | |
| 232 // Condition Codes Flag Registers | |
| 233 // I tried to break out ICC and XCC but it's not very pretty. | |
| 234 // Every Sparc instruction which defs/kills one also kills the other. | |
| 235 // Hence every compare instruction which defs one kind of flags ends | |
| 236 // up needing a kill of the other. | |
| 237 reg_def CCR (SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad()); | |
| 238 | |
| 239 reg_def FCC0(SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad()); | |
| 240 reg_def FCC1(SOC, SOC, Op_RegFlags, 1, VMRegImpl::Bad()); | |
| 241 reg_def FCC2(SOC, SOC, Op_RegFlags, 2, VMRegImpl::Bad()); | |
| 242 reg_def FCC3(SOC, SOC, Op_RegFlags, 3, VMRegImpl::Bad()); | |
| 243 | |
| 244 // ---------------------------- | |
| 245 // Specify the enum values for the registers. These enums are only used by the | |
| 246 // OptoReg "class". We can convert these enum values at will to VMReg when needed | |
| 247 // for visibility to the rest of the vm. The order of this enum influences the | |
| 248 // register allocator so having the freedom to set this order and not be stuck | |
| 249 // with the order that is natural for the rest of the vm is worth it. | |
| 250 alloc_class chunk0( | |
| 251 R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H, | |
| 252 R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H, | |
| 253 R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H, | |
| 254 R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H); | |
| 255 | |
| 256 // Note that a register is not allocatable unless it is also mentioned | |
| 257 // in a widely-used reg_class below. Thus, R_G7 and R_G0 are outside i_reg. | |
| 258 | |
| 259 alloc_class chunk1( | |
| 260 // The first registers listed here are those most likely to be used | |
| 261 // as temporaries. We move F0..F7 away from the front of the list, | |
| 262 // to reduce the likelihood of interferences with parameters and | |
| 263 // return values. Likewise, we avoid using F0/F1 for parameters, | |
| 264 // since they are used for return values. | |
| 265 // This FPU fine-tuning is worth about 1% on the SPEC geomean. | |
| 266 R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, | |
| 267 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23, | |
| 268 R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31, | |
| 269 R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values | |
| 270 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x, | |
| 271 R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x, | |
| 272 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x, | |
| 273 R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x); | |
| 274 | |
| 275 alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3); | |
| 276 | |
| 277 //----------Architecture Description Register Classes-------------------------- | |
| 278 // Several register classes are automatically defined based upon information in | |
| 279 // this architecture description. | |
| 280 // 1) reg_class inline_cache_reg ( as defined in frame section ) | |
| 281 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section ) | |
| 282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ ) | |
| 283 // | |
| 284 | |
| 285 // G0 is not included in integer class since it has special meaning. | |
| 286 reg_class g0_reg(R_G0); | |
| 287 | |
| 288 // ---------------------------- | |
| 289 // Integer Register Classes | |
| 290 // ---------------------------- | |
| 291 // Exclusions from i_reg: | |
| 292 // R_G0: hardwired zero | |
| 293 // R_G2: reserved by HotSpot to the TLS register (invariant within Java) | |
| 294 // R_G6: reserved by Solaris ABI to tools | |
| 295 // R_G7: reserved by Solaris ABI to libthread | |
| 296 // R_O7: Used as a temp in many encodings | |
| 297 reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); | |
| 298 | |
| 299 // Class for all integer registers, except the G registers. This is used for | |
| 300 // encodings which use G registers as temps. The regular inputs to such | |
| 301 // instructions use a "notemp_" prefix, as a hack to ensure that the allocator | |
| 302 // will not put an input into a temp register. | |
| 303 reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); | |
| 304 | |
| 305 reg_class g1_regI(R_G1); | |
| 306 reg_class g3_regI(R_G3); | |
| 307 reg_class g4_regI(R_G4); | |
| 308 reg_class o0_regI(R_O0); | |
| 309 reg_class o7_regI(R_O7); | |
| 310 | |
| 311 // ---------------------------- | |
| 312 // Pointer Register Classes | |
| 313 // ---------------------------- | |
| 314 #ifdef _LP64 | |
| 315 // 64-bit build means 64-bit pointers means hi/lo pairs | |
| 316 reg_class ptr_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5, | |
| 317 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, | |
| 318 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, | |
| 319 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 ); | |
| 320 // Lock encodings use G3 and G4 internally | |
| 321 reg_class lock_ptr_reg( R_G1H,R_G1, R_G5H,R_G5, | |
| 322 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, | |
| 323 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, | |
| 324 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 ); | |
| 325 // Special class for storeP instructions, which can store SP or RPC to TLS. | |
| 326 // It is also used for memory addressing, allowing direct TLS addressing. | |
| 327 reg_class sp_ptr_reg( R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5, | |
| 328 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP, | |
| 329 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, | |
| 330 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP ); | |
| 331 // R_L7 is the lowest-priority callee-save (i.e., NS) register | |
| 332 // We use it to save R_G2 across calls out of Java. | |
| 333 reg_class l7_regP(R_L7H,R_L7); | |
| 334 | |
| 335 // Other special pointer regs | |
| 336 reg_class g1_regP(R_G1H,R_G1); | |
| 337 reg_class g2_regP(R_G2H,R_G2); | |
| 338 reg_class g3_regP(R_G3H,R_G3); | |
| 339 reg_class g4_regP(R_G4H,R_G4); | |
| 340 reg_class g5_regP(R_G5H,R_G5); | |
| 341 reg_class i0_regP(R_I0H,R_I0); | |
| 342 reg_class o0_regP(R_O0H,R_O0); | |
| 343 reg_class o1_regP(R_O1H,R_O1); | |
| 344 reg_class o2_regP(R_O2H,R_O2); | |
| 345 reg_class o7_regP(R_O7H,R_O7); | |
| 346 | |
| 347 #else // _LP64 | |
| 348 // 32-bit build means 32-bit pointers means 1 register. | |
| 349 reg_class ptr_reg( R_G1, R_G3,R_G4,R_G5, | |
| 350 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5, | |
| 351 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, | |
| 352 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); | |
| 353 // Lock encodings use G3 and G4 internally | |
| 354 reg_class lock_ptr_reg(R_G1, R_G5, | |
| 355 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5, | |
| 356 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, | |
| 357 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); | |
| 358 // Special class for storeP instructions, which can store SP or RPC to TLS. | |
| 359 // It is also used for memory addressing, allowing direct TLS addressing. | |
| 360 reg_class sp_ptr_reg( R_G1,R_G2,R_G3,R_G4,R_G5, | |
| 361 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_SP, | |
| 362 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, | |
| 363 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5,R_FP); | |
| 364 // R_L7 is the lowest-priority callee-save (i.e., NS) register | |
| 365 // We use it to save R_G2 across calls out of Java. | |
| 366 reg_class l7_regP(R_L7); | |
| 367 | |
| 368 // Other special pointer regs | |
| 369 reg_class g1_regP(R_G1); | |
| 370 reg_class g2_regP(R_G2); | |
| 371 reg_class g3_regP(R_G3); | |
| 372 reg_class g4_regP(R_G4); | |
| 373 reg_class g5_regP(R_G5); | |
| 374 reg_class i0_regP(R_I0); | |
| 375 reg_class o0_regP(R_O0); | |
| 376 reg_class o1_regP(R_O1); | |
| 377 reg_class o2_regP(R_O2); | |
| 378 reg_class o7_regP(R_O7); | |
| 379 #endif // _LP64 | |
| 380 | |
| 381 | |
| 382 // ---------------------------- | |
| 383 // Long Register Classes | |
| 384 // ---------------------------- | |
| 385 // Longs in 1 register. Aligned adjacent hi/lo pairs. | |
| 386 // Note: O7 is never in this class; it is sometimes used as an encoding temp. | |
| 387 reg_class long_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5 | |
| 388 ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5 | |
| 389 #ifdef _LP64 | |
| 390 // 64-bit, longs in 1 register: use all 64-bit integer registers | |
| 391 // 32-bit, longs in 1 register: cannot use I's and L's. Restrict to O's and G's. | |
| 392 ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7 | |
| 393 ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 | |
| 394 #endif // _LP64 | |
| 395 ); | |
| 396 | |
| 397 reg_class g1_regL(R_G1H,R_G1); | |
| 398 reg_class o2_regL(R_O2H,R_O2); | |
| 399 reg_class o7_regL(R_O7H,R_O7); | |
| 400 | |
| 401 // ---------------------------- | |
| 402 // Special Class for Condition Code Flags Register | |
| 403 reg_class int_flags(CCR); | |
| 404 reg_class float_flags(FCC0,FCC1,FCC2,FCC3); | |
| 405 reg_class float_flag0(FCC0); | |
| 406 | |
| 407 | |
| 408 // ---------------------------- | |
| 409 // Float Point Register Classes | |
| 410 // ---------------------------- | |
| 411 // Skip F30/F31, they are reserved for mem-mem copies | |
| 412 reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29); | |
| 413 | |
| 414 // Paired floating point registers--they show up in the same order as the floats, | |
| 415 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs. | |
| 416 reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, | |
| 417 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29, | |
| 418 /* Use extra V9 double registers; this AD file does not support V8 */ | |
| 419 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x, | |
| 420 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x | |
| 421 ); | |
| 422 | |
| 423 // Paired floating point registers--they show up in the same order as the floats, | |
| 424 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs. | |
| 425 // This class is usable for mis-aligned loads as happen in I2C adapters. | |
| 426 reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, | |
| 427 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31 ); | |
| 428 %} | |
| 429 | |
| 430 //----------DEFINITION BLOCK--------------------------------------------------- | |
| 431 // Define name --> value mappings to inform the ADLC of an integer valued name | |
| 432 // Current support includes integer values in the range [0, 0x7FFFFFFF] | |
| 433 // Format: | |
| 434 // int_def <name> ( <int_value>, <expression>); | |
| 435 // Generated Code in ad_<arch>.hpp | |
| 436 // #define <name> (<expression>) | |
| 437 // // value == <int_value> | |
| 438 // Generated code in ad_<arch>.cpp adlc_verification() | |
| 439 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>"); | |
| 440 // | |
| 441 definitions %{ | |
| 442 // The default cost (of an ALU instruction). | |
| 443 int_def DEFAULT_COST ( 100, 100); | |
| 444 int_def HUGE_COST (1000000, 1000000); | |
| 445 | |
| 446 // Memory refs are twice as expensive as run-of-the-mill. | |
| 447 int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2); | |
| 448 | |
| 449 // Branches are even more expensive. | |
| 450 int_def BRANCH_COST ( 300, DEFAULT_COST * 3); | |
| 451 int_def CALL_COST ( 300, DEFAULT_COST * 3); | |
| 452 %} | |
| 453 | |
| 454 | |
| 455 //----------SOURCE BLOCK------------------------------------------------------- | |
| 456 // This is a block of C++ code which provides values, functions, and | |
| 457 // definitions necessary in the rest of the architecture description | |
| 458 source_hpp %{ | |
| 459 // Must be visible to the DFA in dfa_sparc.cpp | |
| 460 extern bool can_branch_register( Node *bol, Node *cmp ); | |
| 461 | |
| 462 // Macros to extract hi & lo halves from a long pair. | |
| 463 // G0 is not part of any long pair, so assert on that. | |
| 464 // Prevents accidently using G1 instead of G0. | |
| 465 #define LONG_HI_REG(x) (x) | |
| 466 #define LONG_LO_REG(x) (x) | |
| 467 | |
| 468 %} | |
| 469 | |
| 470 source %{ | |
| 471 #define __ _masm. | |
| 472 | |
| 473 // tertiary op of a LoadP or StoreP encoding | |
| 474 #define REGP_OP true | |
| 475 | |
| 476 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding); | |
| 477 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding); | |
| 478 static Register reg_to_register_object(int register_encoding); | |
| 479 | |
| 480 // Used by the DFA in dfa_sparc.cpp. | |
| 481 // Check for being able to use a V9 branch-on-register. Requires a | |
| 482 // compare-vs-zero, equal/not-equal, of a value which was zero- or sign- | |
| 483 // extended. Doesn't work following an integer ADD, for example, because of | |
| 484 // overflow (-1 incremented yields 0 plus a carry in the high-order word). On | |
| 485 // 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and | |
| 486 // replace them with zero, which could become sign-extension in a different OS | |
| 487 // release. There's no obvious reason why an interrupt will ever fill these | |
| 488 // bits with non-zero junk (the registers are reloaded with standard LD | |
| 489 // instructions which either zero-fill or sign-fill). | |
| 490 bool can_branch_register( Node *bol, Node *cmp ) { | |
| 491 if( !BranchOnRegister ) return false; | |
| 492 #ifdef _LP64 | |
| 493 if( cmp->Opcode() == Op_CmpP ) | |
| 494 return true; // No problems with pointer compares | |
| 495 #endif | |
| 496 if( cmp->Opcode() == Op_CmpL ) | |
| 497 return true; // No problems with long compares | |
| 498 | |
| 499 if( !SparcV9RegsHiBitsZero ) return false; | |
| 500 if( bol->as_Bool()->_test._test != BoolTest::ne && | |
| 501 bol->as_Bool()->_test._test != BoolTest::eq ) | |
| 502 return false; | |
| 503 | |
| 504 // Check for comparing against a 'safe' value. Any operation which | |
| 505 // clears out the high word is safe. Thus, loads and certain shifts | |
| 506 // are safe, as are non-negative constants. Any operation which | |
| 507 // preserves zero bits in the high word is safe as long as each of its | |
| 508 // inputs are safe. Thus, phis and bitwise booleans are safe if their | |
| 509 // inputs are safe. At present, the only important case to recognize | |
| 510 // seems to be loads. Constants should fold away, and shifts & | |
| 511 // logicals can use the 'cc' forms. | |
| 512 Node *x = cmp->in(1); | |
| 513 if( x->is_Load() ) return true; | |
| 514 if( x->is_Phi() ) { | |
| 515 for( uint i = 1; i < x->req(); i++ ) | |
| 516 if( !x->in(i)->is_Load() ) | |
| 517 return false; | |
| 518 return true; | |
| 519 } | |
| 520 return false; | |
| 521 } | |
| 522 | |
| 523 // **************************************************************************** | |
| 524 | |
| 525 // REQUIRED FUNCTIONALITY | |
| 526 | |
| 527 // !!!!! Special hack to get all type of calls to specify the byte offset | |
| 528 // from the start of the call to the point where the return address | |
| 529 // will point. | |
| 530 // The "return address" is the address of the call instruction, plus 8. | |
| 531 | |
| 532 int MachCallStaticJavaNode::ret_addr_offset() { | |
| 533 return NativeCall::instruction_size; // call; delay slot | |
| 534 } | |
| 535 | |
| 536 int MachCallDynamicJavaNode::ret_addr_offset() { | |
| 537 int vtable_index = this->_vtable_index; | |
| 538 if (vtable_index < 0) { | |
| 539 // must be invalid_vtable_index, not nonvirtual_vtable_index | |
| 540 assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value"); | |
| 541 return (NativeMovConstReg::instruction_size + | |
| 542 NativeCall::instruction_size); // sethi; setlo; call; delay slot | |
| 543 } else { | |
| 544 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); | |
| 545 int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size(); | |
| 546 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes(); | |
|
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547 int klass_load_size; |
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548 if (UseCompressedOops) { |
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549 klass_load_size = 3*BytesPerInstWord; // see MacroAssembler::load_klass() |
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550 } else { |
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551 klass_load_size = 1*BytesPerInstWord; |
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552 } |
| 0 | 553 if( Assembler::is_simm13(v_off) ) { |
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554 return klass_load_size + |
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555 (2*BytesPerInstWord + // ld_ptr, ld_ptr |
| 0 | 556 NativeCall::instruction_size); // call; delay slot |
| 557 } else { | |
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558 return klass_load_size + |
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559 (4*BytesPerInstWord + // set_hi, set, ld_ptr, ld_ptr |
| 0 | 560 NativeCall::instruction_size); // call; delay slot |
| 561 } | |
| 562 } | |
| 563 } | |
| 564 | |
| 565 int MachCallRuntimeNode::ret_addr_offset() { | |
| 566 #ifdef _LP64 | |
| 567 return NativeFarCall::instruction_size; // farcall; delay slot | |
| 568 #else | |
| 569 return NativeCall::instruction_size; // call; delay slot | |
| 570 #endif | |
| 571 } | |
| 572 | |
| 573 // Indicate if the safepoint node needs the polling page as an input. | |
| 574 // Since Sparc does not have absolute addressing, it does. | |
| 575 bool SafePointNode::needs_polling_address_input() { | |
| 576 return true; | |
| 577 } | |
| 578 | |
| 579 // emit an interrupt that is caught by the debugger (for debugging compiler) | |
| 580 void emit_break(CodeBuffer &cbuf) { | |
| 581 MacroAssembler _masm(&cbuf); | |
| 582 __ breakpoint_trap(); | |
| 583 } | |
| 584 | |
| 585 #ifndef PRODUCT | |
| 586 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const { | |
| 587 st->print("TA"); | |
| 588 } | |
| 589 #endif | |
| 590 | |
| 591 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 592 emit_break(cbuf); | |
| 593 } | |
| 594 | |
| 595 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const { | |
| 596 return MachNode::size(ra_); | |
| 597 } | |
| 598 | |
| 599 // Traceable jump | |
| 600 void emit_jmpl(CodeBuffer &cbuf, int jump_target) { | |
| 601 MacroAssembler _masm(&cbuf); | |
| 602 Register rdest = reg_to_register_object(jump_target); | |
| 603 __ JMP(rdest, 0); | |
| 604 __ delayed()->nop(); | |
| 605 } | |
| 606 | |
| 607 // Traceable jump and set exception pc | |
| 608 void emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) { | |
| 609 MacroAssembler _masm(&cbuf); | |
| 610 Register rdest = reg_to_register_object(jump_target); | |
| 611 __ JMP(rdest, 0); | |
| 612 __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc ); | |
| 613 } | |
| 614 | |
| 615 void emit_nop(CodeBuffer &cbuf) { | |
| 616 MacroAssembler _masm(&cbuf); | |
| 617 __ nop(); | |
| 618 } | |
| 619 | |
| 620 void emit_illtrap(CodeBuffer &cbuf) { | |
| 621 MacroAssembler _masm(&cbuf); | |
| 622 __ illtrap(0); | |
| 623 } | |
| 624 | |
| 625 | |
| 626 intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) { | |
| 627 assert(n->rule() != loadUB_rule, ""); | |
| 628 | |
| 629 intptr_t offset = 0; | |
| 630 const TypePtr *adr_type = TYPE_PTR_SENTINAL; // Check for base==RegI, disp==immP | |
| 631 const Node* addr = n->get_base_and_disp(offset, adr_type); | |
| 632 assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP"); | |
| 633 assert(addr != NULL && addr != (Node*)-1, "invalid addr"); | |
| 634 assert(addr->bottom_type()->isa_oopptr() == atype, ""); | |
| 635 atype = atype->add_offset(offset); | |
| 636 assert(disp32 == offset, "wrong disp32"); | |
| 637 return atype->_offset; | |
| 638 } | |
| 639 | |
| 640 | |
| 641 intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) { | |
| 642 assert(n->rule() != loadUB_rule, ""); | |
| 643 | |
| 644 intptr_t offset = 0; | |
| 645 Node* addr = n->in(2); | |
| 646 assert(addr->bottom_type()->isa_oopptr() == atype, ""); | |
| 647 if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) { | |
| 648 Node* a = addr->in(2/*AddPNode::Address*/); | |
| 649 Node* o = addr->in(3/*AddPNode::Offset*/); | |
| 650 offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot; | |
| 651 atype = a->bottom_type()->is_ptr()->add_offset(offset); | |
| 652 assert(atype->isa_oop_ptr(), "still an oop"); | |
| 653 } | |
| 654 offset = atype->is_ptr()->_offset; | |
| 655 if (offset != Type::OffsetBot) offset += disp32; | |
| 656 return offset; | |
| 657 } | |
| 658 | |
| 659 // Standard Sparc opcode form2 field breakdown | |
| 660 static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) { | |
| 661 f0 &= (1<<19)-1; // Mask displacement to 19 bits | |
| 662 int op = (f30 << 30) | | |
| 663 (f29 << 29) | | |
| 664 (f25 << 25) | | |
| 665 (f22 << 22) | | |
| 666 (f20 << 20) | | |
| 667 (f19 << 19) | | |
| 668 (f0 << 0); | |
| 669 *((int*)(cbuf.code_end())) = op; | |
| 670 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
| 671 } | |
| 672 | |
| 673 // Standard Sparc opcode form2 field breakdown | |
| 674 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) { | |
| 675 f0 >>= 10; // Drop 10 bits | |
| 676 f0 &= (1<<22)-1; // Mask displacement to 22 bits | |
| 677 int op = (f30 << 30) | | |
| 678 (f25 << 25) | | |
| 679 (f22 << 22) | | |
| 680 (f0 << 0); | |
| 681 *((int*)(cbuf.code_end())) = op; | |
| 682 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
| 683 } | |
| 684 | |
| 685 // Standard Sparc opcode form3 field breakdown | |
| 686 static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) { | |
| 687 int op = (f30 << 30) | | |
| 688 (f25 << 25) | | |
| 689 (f19 << 19) | | |
| 690 (f14 << 14) | | |
| 691 (f5 << 5) | | |
| 692 (f0 << 0); | |
| 693 *((int*)(cbuf.code_end())) = op; | |
| 694 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
| 695 } | |
| 696 | |
| 697 // Standard Sparc opcode form3 field breakdown | |
| 698 static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) { | |
| 699 simm13 &= (1<<13)-1; // Mask to 13 bits | |
| 700 int op = (f30 << 30) | | |
| 701 (f25 << 25) | | |
| 702 (f19 << 19) | | |
| 703 (f14 << 14) | | |
| 704 (1 << 13) | // bit to indicate immediate-mode | |
| 705 (simm13<<0); | |
| 706 *((int*)(cbuf.code_end())) = op; | |
| 707 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
| 708 } | |
| 709 | |
| 710 static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) { | |
| 711 simm10 &= (1<<10)-1; // Mask to 10 bits | |
| 712 emit3_simm13(cbuf,f30,f25,f19,f14,simm10); | |
| 713 } | |
| 714 | |
| 715 #ifdef ASSERT | |
| 716 // Helper function for VerifyOops in emit_form3_mem_reg | |
| 717 void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) { | |
| 718 warning("VerifyOops encountered unexpected instruction:"); | |
| 719 n->dump(2); | |
| 720 warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]); | |
| 721 } | |
| 722 #endif | |
| 723 | |
| 724 | |
| 725 void emit_form3_mem_reg(CodeBuffer &cbuf, const MachNode* n, int primary, int tertiary, | |
| 726 int src1_enc, int disp32, int src2_enc, int dst_enc) { | |
| 727 | |
| 728 #ifdef ASSERT | |
| 729 // The following code implements the +VerifyOops feature. | |
| 730 // It verifies oop values which are loaded into or stored out of | |
| 731 // the current method activation. +VerifyOops complements techniques | |
| 732 // like ScavengeALot, because it eagerly inspects oops in transit, | |
| 733 // as they enter or leave the stack, as opposed to ScavengeALot, | |
| 734 // which inspects oops "at rest", in the stack or heap, at safepoints. | |
| 735 // For this reason, +VerifyOops can sometimes detect bugs very close | |
| 736 // to their point of creation. It can also serve as a cross-check | |
| 737 // on the validity of oop maps, when used toegether with ScavengeALot. | |
| 738 | |
| 739 // It would be good to verify oops at other points, especially | |
| 740 // when an oop is used as a base pointer for a load or store. | |
| 741 // This is presently difficult, because it is hard to know when | |
| 742 // a base address is biased or not. (If we had such information, | |
| 743 // it would be easy and useful to make a two-argument version of | |
| 744 // verify_oop which unbiases the base, and performs verification.) | |
| 745 | |
| 746 assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary"); | |
| 747 bool is_verified_oop_base = false; | |
| 748 bool is_verified_oop_load = false; | |
| 749 bool is_verified_oop_store = false; | |
| 750 int tmp_enc = -1; | |
| 751 if (VerifyOops && src1_enc != R_SP_enc) { | |
| 752 // classify the op, mainly for an assert check | |
| 753 int st_op = 0, ld_op = 0; | |
| 754 switch (primary) { | |
| 755 case Assembler::stb_op3: st_op = Op_StoreB; break; | |
| 756 case Assembler::sth_op3: st_op = Op_StoreC; break; | |
| 757 case Assembler::stx_op3: // may become StoreP or stay StoreI or StoreD0 | |
| 758 case Assembler::stw_op3: st_op = Op_StoreI; break; | |
| 759 case Assembler::std_op3: st_op = Op_StoreL; break; | |
| 760 case Assembler::stf_op3: st_op = Op_StoreF; break; | |
| 761 case Assembler::stdf_op3: st_op = Op_StoreD; break; | |
| 762 | |
| 763 case Assembler::ldsb_op3: ld_op = Op_LoadB; break; | |
| 764 case Assembler::lduh_op3: ld_op = Op_LoadC; break; | |
| 765 case Assembler::ldsh_op3: ld_op = Op_LoadS; break; | |
| 766 case Assembler::ldx_op3: // may become LoadP or stay LoadI | |
| 767 case Assembler::ldsw_op3: // may become LoadP or stay LoadI | |
| 768 case Assembler::lduw_op3: ld_op = Op_LoadI; break; | |
| 769 case Assembler::ldd_op3: ld_op = Op_LoadL; break; | |
| 770 case Assembler::ldf_op3: ld_op = Op_LoadF; break; | |
| 771 case Assembler::lddf_op3: ld_op = Op_LoadD; break; | |
| 772 case Assembler::ldub_op3: ld_op = Op_LoadB; break; | |
| 773 case Assembler::prefetch_op3: ld_op = Op_LoadI; break; | |
| 774 | |
| 775 default: ShouldNotReachHere(); | |
| 776 } | |
| 777 if (tertiary == REGP_OP) { | |
| 778 if (st_op == Op_StoreI) st_op = Op_StoreP; | |
| 779 else if (ld_op == Op_LoadI) ld_op = Op_LoadP; | |
| 780 else ShouldNotReachHere(); | |
| 781 if (st_op) { | |
| 782 // a store | |
| 783 // inputs are (0:control, 1:memory, 2:address, 3:value) | |
| 784 Node* n2 = n->in(3); | |
| 785 if (n2 != NULL) { | |
| 786 const Type* t = n2->bottom_type(); | |
| 787 is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false; | |
| 788 } | |
| 789 } else { | |
| 790 // a load | |
| 791 const Type* t = n->bottom_type(); | |
| 792 is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false; | |
| 793 } | |
| 794 } | |
| 795 | |
| 796 if (ld_op) { | |
| 797 // a Load | |
| 798 // inputs are (0:control, 1:memory, 2:address) | |
| 799 if (!(n->ideal_Opcode()==ld_op) && // Following are special cases | |
| 800 !(n->ideal_Opcode()==Op_LoadLLocked && ld_op==Op_LoadI) && | |
| 801 !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) && | |
| 802 !(n->ideal_Opcode()==Op_LoadI && ld_op==Op_LoadF) && | |
| 803 !(n->ideal_Opcode()==Op_LoadF && ld_op==Op_LoadI) && | |
| 804 !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) && | |
| 805 !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) && | |
| 806 !(n->ideal_Opcode()==Op_LoadL && ld_op==Op_LoadI) && | |
| 807 !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) && | |
| 808 !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) && | |
| 809 !(n->ideal_Opcode()==Op_ConvI2F && ld_op==Op_LoadF) && | |
| 810 !(n->ideal_Opcode()==Op_ConvI2D && ld_op==Op_LoadF) && | |
| 811 !(n->ideal_Opcode()==Op_PrefetchRead && ld_op==Op_LoadI) && | |
| 812 !(n->ideal_Opcode()==Op_PrefetchWrite && ld_op==Op_LoadI) && | |
| 813 !(n->rule() == loadUB_rule)) { | |
| 814 verify_oops_warning(n, n->ideal_Opcode(), ld_op); | |
| 815 } | |
| 816 } else if (st_op) { | |
| 817 // a Store | |
| 818 // inputs are (0:control, 1:memory, 2:address, 3:value) | |
| 819 if (!(n->ideal_Opcode()==st_op) && // Following are special cases | |
| 820 !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) && | |
| 821 !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) && | |
| 822 !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) && | |
| 823 !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) && | |
| 824 !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) { | |
| 825 verify_oops_warning(n, n->ideal_Opcode(), st_op); | |
| 826 } | |
| 827 } | |
| 828 | |
| 829 if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) { | |
| 830 Node* addr = n->in(2); | |
| 831 if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) { | |
| 832 const TypeOopPtr* atype = addr->bottom_type()->isa_instptr(); // %%% oopptr? | |
| 833 if (atype != NULL) { | |
| 834 intptr_t offset = get_offset_from_base(n, atype, disp32); | |
| 835 intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32); | |
| 836 if (offset != offset_2) { | |
| 837 get_offset_from_base(n, atype, disp32); | |
| 838 get_offset_from_base_2(n, atype, disp32); | |
| 839 } | |
| 840 assert(offset == offset_2, "different offsets"); | |
| 841 if (offset == disp32) { | |
| 842 // we now know that src1 is a true oop pointer | |
| 843 is_verified_oop_base = true; | |
| 844 if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) { | |
| 845 if( primary == Assembler::ldd_op3 ) { | |
| 846 is_verified_oop_base = false; // Cannot 'ldd' into O7 | |
| 847 } else { | |
| 848 tmp_enc = dst_enc; | |
| 849 dst_enc = R_O7_enc; // Load into O7; preserve source oop | |
| 850 assert(src1_enc != dst_enc, ""); | |
| 851 } | |
| 852 } | |
| 853 } | |
| 854 if (st_op && (( offset == oopDesc::klass_offset_in_bytes()) | |
| 855 || offset == oopDesc::mark_offset_in_bytes())) { | |
| 856 // loading the mark should not be allowed either, but | |
| 857 // we don't check this since it conflicts with InlineObjectHash | |
| 858 // usage of LoadINode to get the mark. We could keep the | |
| 859 // check if we create a new LoadMarkNode | |
| 860 // but do not verify the object before its header is initialized | |
| 861 ShouldNotReachHere(); | |
| 862 } | |
| 863 } | |
| 864 } | |
| 865 } | |
| 866 } | |
| 867 #endif | |
| 868 | |
| 869 uint instr; | |
| 870 instr = (Assembler::ldst_op << 30) | |
| 871 | (dst_enc << 25) | |
| 872 | (primary << 19) | |
| 873 | (src1_enc << 14); | |
| 874 | |
| 875 uint index = src2_enc; | |
| 876 int disp = disp32; | |
| 877 | |
| 878 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc) | |
| 879 disp += STACK_BIAS; | |
| 880 | |
| 881 // We should have a compiler bailout here rather than a guarantee. | |
| 882 // Better yet would be some mechanism to handle variable-size matches correctly. | |
| 883 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" ); | |
| 884 | |
| 885 if( disp == 0 ) { | |
| 886 // use reg-reg form | |
| 887 // bit 13 is already zero | |
| 888 instr |= index; | |
| 889 } else { | |
| 890 // use reg-imm form | |
| 891 instr |= 0x00002000; // set bit 13 to one | |
| 892 instr |= disp & 0x1FFF; | |
| 893 } | |
| 894 | |
| 895 uint *code = (uint*)cbuf.code_end(); | |
| 896 *code = instr; | |
| 897 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
| 898 | |
| 899 #ifdef ASSERT | |
| 900 { | |
| 901 MacroAssembler _masm(&cbuf); | |
| 902 if (is_verified_oop_base) { | |
| 903 __ verify_oop(reg_to_register_object(src1_enc)); | |
| 904 } | |
| 905 if (is_verified_oop_store) { | |
| 906 __ verify_oop(reg_to_register_object(dst_enc)); | |
| 907 } | |
| 908 if (tmp_enc != -1) { | |
| 909 __ mov(O7, reg_to_register_object(tmp_enc)); | |
| 910 } | |
| 911 if (is_verified_oop_load) { | |
| 912 __ verify_oop(reg_to_register_object(dst_enc)); | |
| 913 } | |
| 914 } | |
| 915 #endif | |
| 916 } | |
| 917 | |
| 918 void emit_form3_mem_reg_asi(CodeBuffer &cbuf, const MachNode* n, int primary, int tertiary, | |
| 919 int src1_enc, int disp32, int src2_enc, int dst_enc, int asi) { | |
| 920 | |
| 921 uint instr; | |
| 922 instr = (Assembler::ldst_op << 30) | |
| 923 | (dst_enc << 25) | |
| 924 | (primary << 19) | |
| 925 | (src1_enc << 14); | |
| 926 | |
| 927 int disp = disp32; | |
| 928 int index = src2_enc; | |
| 929 | |
| 930 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc) | |
| 931 disp += STACK_BIAS; | |
| 932 | |
| 933 // We should have a compiler bailout here rather than a guarantee. | |
| 934 // Better yet would be some mechanism to handle variable-size matches correctly. | |
| 935 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" ); | |
| 936 | |
| 937 if( disp != 0 ) { | |
| 938 // use reg-reg form | |
| 939 // set src2=R_O7 contains offset | |
| 940 index = R_O7_enc; | |
| 941 emit3_simm13( cbuf, Assembler::arith_op, index, Assembler::or_op3, 0, disp); | |
| 942 } | |
| 943 instr |= (asi << 5); | |
| 944 instr |= index; | |
| 945 uint *code = (uint*)cbuf.code_end(); | |
| 946 *code = instr; | |
| 947 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
| 948 } | |
| 949 | |
| 950 void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, relocInfo::relocType rtype, bool preserve_g2 = false, bool force_far_call = false) { | |
| 951 // The method which records debug information at every safepoint | |
| 952 // expects the call to be the first instruction in the snippet as | |
| 953 // it creates a PcDesc structure which tracks the offset of a call | |
| 954 // from the start of the codeBlob. This offset is computed as | |
| 955 // code_end() - code_begin() of the code which has been emitted | |
| 956 // so far. | |
| 957 // In this particular case we have skirted around the problem by | |
| 958 // putting the "mov" instruction in the delay slot but the problem | |
| 959 // may bite us again at some other point and a cleaner/generic | |
| 960 // solution using relocations would be needed. | |
| 961 MacroAssembler _masm(&cbuf); | |
| 962 __ set_inst_mark(); | |
| 963 | |
| 964 // We flush the current window just so that there is a valid stack copy | |
| 965 // the fact that the current window becomes active again instantly is | |
| 966 // not a problem there is nothing live in it. | |
| 967 | |
| 968 #ifdef ASSERT | |
| 969 int startpos = __ offset(); | |
| 970 #endif /* ASSERT */ | |
| 971 | |
| 972 #ifdef _LP64 | |
| 973 // Calls to the runtime or native may not be reachable from compiled code, | |
| 974 // so we generate the far call sequence on 64 bit sparc. | |
| 975 // This code sequence is relocatable to any address, even on LP64. | |
| 976 if ( force_far_call ) { | |
| 977 __ relocate(rtype); | |
| 978 Address dest(O7, (address)entry_point); | |
| 979 __ jumpl_to(dest, O7); | |
| 980 } | |
| 981 else | |
| 982 #endif | |
| 983 { | |
| 984 __ call((address)entry_point, rtype); | |
| 985 } | |
| 986 | |
| 987 if (preserve_g2) __ delayed()->mov(G2, L7); | |
| 988 else __ delayed()->nop(); | |
| 989 | |
| 990 if (preserve_g2) __ mov(L7, G2); | |
| 991 | |
| 992 #ifdef ASSERT | |
| 993 if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) { | |
| 994 #ifdef _LP64 | |
| 995 // Trash argument dump slots. | |
| 996 __ set(0xb0b8ac0db0b8ac0d, G1); | |
| 997 __ mov(G1, G5); | |
| 998 __ stx(G1, SP, STACK_BIAS + 0x80); | |
| 999 __ stx(G1, SP, STACK_BIAS + 0x88); | |
| 1000 __ stx(G1, SP, STACK_BIAS + 0x90); | |
| 1001 __ stx(G1, SP, STACK_BIAS + 0x98); | |
| 1002 __ stx(G1, SP, STACK_BIAS + 0xA0); | |
| 1003 __ stx(G1, SP, STACK_BIAS + 0xA8); | |
| 1004 #else // _LP64 | |
| 1005 // this is also a native call, so smash the first 7 stack locations, | |
| 1006 // and the various registers | |
| 1007 | |
| 1008 // Note: [SP+0x40] is sp[callee_aggregate_return_pointer_sp_offset], | |
| 1009 // while [SP+0x44..0x58] are the argument dump slots. | |
| 1010 __ set((intptr_t)0xbaadf00d, G1); | |
| 1011 __ mov(G1, G5); | |
| 1012 __ sllx(G1, 32, G1); | |
| 1013 __ or3(G1, G5, G1); | |
| 1014 __ mov(G1, G5); | |
| 1015 __ stx(G1, SP, 0x40); | |
| 1016 __ stx(G1, SP, 0x48); | |
| 1017 __ stx(G1, SP, 0x50); | |
| 1018 __ stw(G1, SP, 0x58); // Do not trash [SP+0x5C] which is a usable spill slot | |
| 1019 #endif // _LP64 | |
| 1020 } | |
| 1021 #endif /*ASSERT*/ | |
| 1022 } | |
| 1023 | |
| 1024 //============================================================================= | |
| 1025 // REQUIRED FUNCTIONALITY for encoding | |
| 1026 void emit_lo(CodeBuffer &cbuf, int val) { } | |
| 1027 void emit_hi(CodeBuffer &cbuf, int val) { } | |
| 1028 | |
| 1029 void emit_ptr(CodeBuffer &cbuf, intptr_t val, Register reg, bool ForceRelocatable) { | |
| 1030 MacroAssembler _masm(&cbuf); | |
| 1031 if (ForceRelocatable) { | |
| 1032 Address addr(reg, (address)val); | |
| 1033 __ sethi(addr, ForceRelocatable); | |
| 1034 __ add(addr, reg); | |
| 1035 } else { | |
| 1036 __ set(val, reg); | |
| 1037 } | |
| 1038 } | |
| 1039 | |
| 1040 | |
| 1041 //============================================================================= | |
| 1042 | |
| 1043 #ifndef PRODUCT | |
| 1044 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
| 1045 Compile* C = ra_->C; | |
| 1046 | |
| 1047 for (int i = 0; i < OptoPrologueNops; i++) { | |
| 1048 st->print_cr("NOP"); st->print("\t"); | |
| 1049 } | |
| 1050 | |
| 1051 if( VerifyThread ) { | |
| 1052 st->print_cr("Verify_Thread"); st->print("\t"); | |
| 1053 } | |
| 1054 | |
| 1055 size_t framesize = C->frame_slots() << LogBytesPerInt; | |
| 1056 | |
| 1057 // Calls to C2R adapters often do not accept exceptional returns. | |
| 1058 // We require that their callers must bang for them. But be careful, because | |
| 1059 // some VM calls (such as call site linkage) can use several kilobytes of | |
| 1060 // stack. But the stack safety zone should account for that. | |
| 1061 // See bugs 4446381, 4468289, 4497237. | |
| 1062 if (C->need_stack_bang(framesize)) { | |
| 1063 st->print_cr("! stack bang"); st->print("\t"); | |
| 1064 } | |
| 1065 | |
| 1066 if (Assembler::is_simm13(-framesize)) { | |
| 1067 st->print ("SAVE R_SP,-%d,R_SP",framesize); | |
| 1068 } else { | |
| 1069 st->print_cr("SETHI R_SP,hi%%(-%d),R_G3",framesize); st->print("\t"); | |
| 1070 st->print_cr("ADD R_G3,lo%%(-%d),R_G3",framesize); st->print("\t"); | |
| 1071 st->print ("SAVE R_SP,R_G3,R_SP"); | |
| 1072 } | |
| 1073 | |
| 1074 } | |
| 1075 #endif | |
| 1076 | |
| 1077 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1078 Compile* C = ra_->C; | |
| 1079 MacroAssembler _masm(&cbuf); | |
| 1080 | |
| 1081 for (int i = 0; i < OptoPrologueNops; i++) { | |
| 1082 __ nop(); | |
| 1083 } | |
| 1084 | |
| 1085 __ verify_thread(); | |
| 1086 | |
| 1087 size_t framesize = C->frame_slots() << LogBytesPerInt; | |
| 1088 assert(framesize >= 16*wordSize, "must have room for reg. save area"); | |
| 1089 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment"); | |
| 1090 | |
| 1091 // Calls to C2R adapters often do not accept exceptional returns. | |
| 1092 // We require that their callers must bang for them. But be careful, because | |
| 1093 // some VM calls (such as call site linkage) can use several kilobytes of | |
| 1094 // stack. But the stack safety zone should account for that. | |
| 1095 // See bugs 4446381, 4468289, 4497237. | |
| 1096 if (C->need_stack_bang(framesize)) { | |
| 1097 __ generate_stack_overflow_check(framesize); | |
| 1098 } | |
| 1099 | |
| 1100 if (Assembler::is_simm13(-framesize)) { | |
| 1101 __ save(SP, -framesize, SP); | |
| 1102 } else { | |
| 1103 __ sethi(-framesize & ~0x3ff, G3); | |
| 1104 __ add(G3, -framesize & 0x3ff, G3); | |
| 1105 __ save(SP, G3, SP); | |
| 1106 } | |
| 1107 C->set_frame_complete( __ offset() ); | |
| 1108 } | |
| 1109 | |
| 1110 uint MachPrologNode::size(PhaseRegAlloc *ra_) const { | |
| 1111 return MachNode::size(ra_); | |
| 1112 } | |
| 1113 | |
| 1114 int MachPrologNode::reloc() const { | |
| 1115 return 10; // a large enough number | |
| 1116 } | |
| 1117 | |
| 1118 //============================================================================= | |
| 1119 #ifndef PRODUCT | |
| 1120 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
| 1121 Compile* C = ra_->C; | |
| 1122 | |
| 1123 if( do_polling() && ra_->C->is_method_compilation() ) { | |
| 1124 st->print("SETHI #PollAddr,L0\t! Load Polling address\n\t"); | |
| 1125 #ifdef _LP64 | |
| 1126 st->print("LDX [L0],G0\t!Poll for Safepointing\n\t"); | |
| 1127 #else | |
| 1128 st->print("LDUW [L0],G0\t!Poll for Safepointing\n\t"); | |
| 1129 #endif | |
| 1130 } | |
| 1131 | |
| 1132 if( do_polling() ) | |
| 1133 st->print("RET\n\t"); | |
| 1134 | |
| 1135 st->print("RESTORE"); | |
| 1136 } | |
| 1137 #endif | |
| 1138 | |
| 1139 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1140 MacroAssembler _masm(&cbuf); | |
| 1141 Compile* C = ra_->C; | |
| 1142 | |
| 1143 __ verify_thread(); | |
| 1144 | |
| 1145 // If this does safepoint polling, then do it here | |
| 1146 if( do_polling() && ra_->C->is_method_compilation() ) { | |
| 1147 Address polling_page(L0, (address)os::get_polling_page()); | |
| 1148 __ sethi(polling_page, false); | |
| 1149 __ relocate(relocInfo::poll_return_type); | |
| 1150 __ ld_ptr( L0, 0, G0 ); | |
| 1151 } | |
| 1152 | |
| 1153 // If this is a return, then stuff the restore in the delay slot | |
| 1154 if( do_polling() ) { | |
| 1155 __ ret(); | |
| 1156 __ delayed()->restore(); | |
| 1157 } else { | |
| 1158 __ restore(); | |
| 1159 } | |
| 1160 } | |
| 1161 | |
| 1162 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const { | |
| 1163 return MachNode::size(ra_); | |
| 1164 } | |
| 1165 | |
| 1166 int MachEpilogNode::reloc() const { | |
| 1167 return 16; // a large enough number | |
| 1168 } | |
| 1169 | |
| 1170 const Pipeline * MachEpilogNode::pipeline() const { | |
| 1171 return MachNode::pipeline_class(); | |
| 1172 } | |
| 1173 | |
| 1174 int MachEpilogNode::safepoint_offset() const { | |
| 1175 assert( do_polling(), "no return for this epilog node"); | |
| 1176 return MacroAssembler::size_of_sethi(os::get_polling_page()); | |
| 1177 } | |
| 1178 | |
| 1179 //============================================================================= | |
| 1180 | |
| 1181 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack | |
| 1182 enum RC { rc_bad, rc_int, rc_float, rc_stack }; | |
| 1183 static enum RC rc_class( OptoReg::Name reg ) { | |
| 1184 if( !OptoReg::is_valid(reg) ) return rc_bad; | |
| 1185 if (OptoReg::is_stack(reg)) return rc_stack; | |
| 1186 VMReg r = OptoReg::as_VMReg(reg); | |
| 1187 if (r->is_Register()) return rc_int; | |
| 1188 assert(r->is_FloatRegister(), "must be"); | |
| 1189 return rc_float; | |
| 1190 } | |
| 1191 | |
| 1192 static int impl_helper( const MachNode *mach, CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size, outputStream* st ) { | |
| 1193 if( cbuf ) { | |
| 1194 // Better yet would be some mechanism to handle variable-size matches correctly | |
| 1195 if (!Assembler::is_simm13(offset + STACK_BIAS)) { | |
| 1196 ra_->C->record_method_not_compilable("unable to handle large constant offsets"); | |
| 1197 } else { | |
| 1198 emit_form3_mem_reg(*cbuf, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]); | |
| 1199 } | |
| 1200 } | |
| 1201 #ifndef PRODUCT | |
| 1202 else if( !do_size ) { | |
| 1203 if( size != 0 ) st->print("\n\t"); | |
| 1204 if( is_load ) st->print("%s [R_SP + #%d],R_%s\t! spill",op_str,offset,OptoReg::regname(reg)); | |
| 1205 else st->print("%s R_%s,[R_SP + #%d]\t! spill",op_str,OptoReg::regname(reg),offset); | |
| 1206 } | |
| 1207 #endif | |
| 1208 return size+4; | |
| 1209 } | |
| 1210 | |
| 1211 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int op1, int op2, const char *op_str, int size, outputStream* st ) { | |
| 1212 if( cbuf ) emit3( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src] ); | |
| 1213 #ifndef PRODUCT | |
| 1214 else if( !do_size ) { | |
| 1215 if( size != 0 ) st->print("\n\t"); | |
| 1216 st->print("%s R_%s,R_%s\t! spill",op_str,OptoReg::regname(src),OptoReg::regname(dst)); | |
| 1217 } | |
| 1218 #endif | |
| 1219 return size+4; | |
| 1220 } | |
| 1221 | |
| 1222 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, | |
| 1223 PhaseRegAlloc *ra_, | |
| 1224 bool do_size, | |
| 1225 outputStream* st ) const { | |
| 1226 // Get registers to move | |
| 1227 OptoReg::Name src_second = ra_->get_reg_second(in(1)); | |
| 1228 OptoReg::Name src_first = ra_->get_reg_first(in(1)); | |
| 1229 OptoReg::Name dst_second = ra_->get_reg_second(this ); | |
| 1230 OptoReg::Name dst_first = ra_->get_reg_first(this ); | |
| 1231 | |
| 1232 enum RC src_second_rc = rc_class(src_second); | |
| 1233 enum RC src_first_rc = rc_class(src_first); | |
| 1234 enum RC dst_second_rc = rc_class(dst_second); | |
| 1235 enum RC dst_first_rc = rc_class(dst_first); | |
| 1236 | |
| 1237 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" ); | |
| 1238 | |
| 1239 // Generate spill code! | |
| 1240 int size = 0; | |
| 1241 | |
| 1242 if( src_first == dst_first && src_second == dst_second ) | |
| 1243 return size; // Self copy, no move | |
| 1244 | |
| 1245 // -------------------------------------- | |
| 1246 // Check for mem-mem move. Load into unused float registers and fall into | |
| 1247 // the float-store case. | |
| 1248 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) { | |
| 1249 int offset = ra_->reg2offset(src_first); | |
| 1250 // Further check for aligned-adjacent pair, so we can use a double load | |
| 1251 if( (src_first&1)==0 && src_first+1 == src_second ) { | |
| 1252 src_second = OptoReg::Name(R_F31_num); | |
| 1253 src_second_rc = rc_float; | |
| 1254 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::lddf_op3,"LDDF",size, st); | |
| 1255 } else { | |
| 1256 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::ldf_op3 ,"LDF ",size, st); | |
| 1257 } | |
| 1258 src_first = OptoReg::Name(R_F30_num); | |
| 1259 src_first_rc = rc_float; | |
| 1260 } | |
| 1261 | |
| 1262 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { | |
| 1263 int offset = ra_->reg2offset(src_second); | |
| 1264 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F31_num,Assembler::ldf_op3,"LDF ",size, st); | |
| 1265 src_second = OptoReg::Name(R_F31_num); | |
| 1266 src_second_rc = rc_float; | |
| 1267 } | |
| 1268 | |
| 1269 // -------------------------------------- | |
| 1270 // Check for float->int copy; requires a trip through memory | |
| 1271 if( src_first_rc == rc_float && dst_first_rc == rc_int ) { | |
| 1272 int offset = frame::register_save_words*wordSize; | |
| 1273 if( cbuf ) { | |
| 1274 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16 ); | |
| 1275 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); | |
| 1276 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); | |
| 1277 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16 ); | |
| 1278 } | |
| 1279 #ifndef PRODUCT | |
| 1280 else if( !do_size ) { | |
| 1281 if( size != 0 ) st->print("\n\t"); | |
| 1282 st->print( "SUB R_SP,16,R_SP\n"); | |
| 1283 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); | |
| 1284 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); | |
| 1285 st->print("\tADD R_SP,16,R_SP\n"); | |
| 1286 } | |
| 1287 #endif | |
| 1288 size += 16; | |
| 1289 } | |
| 1290 | |
| 1291 // -------------------------------------- | |
| 1292 // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations. | |
| 1293 // In such cases, I have to do the big-endian swap. For aligned targets, the | |
| 1294 // hardware does the flop for me. Doubles are always aligned, so no problem | |
| 1295 // there. Misaligned sources only come from native-long-returns (handled | |
| 1296 // special below). | |
| 1297 #ifndef _LP64 | |
| 1298 if( src_first_rc == rc_int && // source is already big-endian | |
| 1299 src_second_rc != rc_bad && // 64-bit move | |
| 1300 ((dst_first&1)!=0 || dst_second != dst_first+1) ) { // misaligned dst | |
| 1301 assert( (src_first&1)==0 && src_second == src_first+1, "source must be aligned" ); | |
| 1302 // Do the big-endian flop. | |
| 1303 OptoReg::Name tmp = dst_first ; dst_first = dst_second ; dst_second = tmp ; | |
| 1304 enum RC tmp_rc = dst_first_rc; dst_first_rc = dst_second_rc; dst_second_rc = tmp_rc; | |
| 1305 } | |
| 1306 #endif | |
| 1307 | |
| 1308 // -------------------------------------- | |
| 1309 // Check for integer reg-reg copy | |
| 1310 if( src_first_rc == rc_int && dst_first_rc == rc_int ) { | |
| 1311 #ifndef _LP64 | |
| 1312 if( src_first == R_O0_num && src_second == R_O1_num ) { // Check for the evil O0/O1 native long-return case | |
| 1313 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value | |
| 1314 // as stored in memory. On a big-endian machine like SPARC, this means that the _second | |
| 1315 // operand contains the least significant word of the 64-bit value and vice versa. | |
| 1316 OptoReg::Name tmp = OptoReg::Name(R_O7_num); | |
| 1317 assert( (dst_first&1)==0 && dst_second == dst_first+1, "return a native O0/O1 long to an aligned-adjacent 64-bit reg" ); | |
| 1318 // Shift O0 left in-place, zero-extend O1, then OR them into the dst | |
| 1319 if( cbuf ) { | |
| 1320 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tmp], Assembler::sllx_op3, Matcher::_regEncode[src_first], 0x1020 ); | |
| 1321 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[src_second], Assembler::srl_op3, Matcher::_regEncode[src_second], 0x0000 ); | |
| 1322 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler:: or_op3, Matcher::_regEncode[tmp], 0, Matcher::_regEncode[src_second] ); | |
| 1323 #ifndef PRODUCT | |
| 1324 } else if( !do_size ) { | |
| 1325 if( size != 0 ) st->print("\n\t"); | |
| 1326 st->print("SLLX R_%s,32,R_%s\t! Move O0-first to O7-high\n\t", OptoReg::regname(src_first), OptoReg::regname(tmp)); | |
| 1327 st->print("SRL R_%s, 0,R_%s\t! Zero-extend O1\n\t", OptoReg::regname(src_second), OptoReg::regname(src_second)); | |
| 1328 st->print("OR R_%s,R_%s,R_%s\t! spill",OptoReg::regname(tmp), OptoReg::regname(src_second), OptoReg::regname(dst_first)); | |
| 1329 #endif | |
| 1330 } | |
| 1331 return size+12; | |
| 1332 } | |
| 1333 else if( dst_first == R_I0_num && dst_second == R_I1_num ) { | |
| 1334 // returning a long value in I0/I1 | |
| 1335 // a SpillCopy must be able to target a return instruction's reg_class | |
| 1336 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value | |
| 1337 // as stored in memory. On a big-endian machine like SPARC, this means that the _second | |
| 1338 // operand contains the least significant word of the 64-bit value and vice versa. | |
| 1339 OptoReg::Name tdest = dst_first; | |
| 1340 | |
| 1341 if (src_first == dst_first) { | |
| 1342 tdest = OptoReg::Name(R_O7_num); | |
| 1343 size += 4; | |
| 1344 } | |
| 1345 | |
| 1346 if( cbuf ) { | |
| 1347 assert( (src_first&1) == 0 && (src_first+1) == src_second, "return value was in an aligned-adjacent 64-bit reg"); | |
| 1348 // Shift value in upper 32-bits of src to lower 32-bits of I0; move lower 32-bits to I1 | |
| 1349 // ShrL_reg_imm6 | |
| 1350 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tdest], Assembler::srlx_op3, Matcher::_regEncode[src_second], 32 | 0x1000 ); | |
| 1351 // ShrR_reg_imm6 src, 0, dst | |
| 1352 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srl_op3, Matcher::_regEncode[src_first], 0x0000 ); | |
| 1353 if (tdest != dst_first) { | |
| 1354 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler::or_op3, 0/*G0*/, 0/*op2*/, Matcher::_regEncode[tdest] ); | |
| 1355 } | |
| 1356 } | |
| 1357 #ifndef PRODUCT | |
| 1358 else if( !do_size ) { | |
| 1359 if( size != 0 ) st->print("\n\t"); // %%%%% !!!!! | |
| 1360 st->print("SRLX R_%s,32,R_%s\t! Extract MSW\n\t",OptoReg::regname(src_second),OptoReg::regname(tdest)); | |
| 1361 st->print("SRL R_%s, 0,R_%s\t! Extract LSW\n\t",OptoReg::regname(src_first),OptoReg::regname(dst_second)); | |
| 1362 if (tdest != dst_first) { | |
| 1363 st->print("MOV R_%s,R_%s\t! spill\n\t", OptoReg::regname(tdest), OptoReg::regname(dst_first)); | |
| 1364 } | |
| 1365 } | |
| 1366 #endif // PRODUCT | |
| 1367 return size+8; | |
| 1368 } | |
| 1369 #endif // !_LP64 | |
| 1370 // Else normal reg-reg copy | |
| 1371 assert( src_second != dst_first, "smashed second before evacuating it" ); | |
| 1372 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::or_op3,0,"MOV ",size, st); | |
| 1373 assert( (src_first&1) == 0 && (dst_first&1) == 0, "never move second-halves of int registers" ); | |
| 1374 // This moves an aligned adjacent pair. | |
| 1375 // See if we are done. | |
| 1376 if( src_first+1 == src_second && dst_first+1 == dst_second ) | |
| 1377 return size; | |
| 1378 } | |
| 1379 | |
| 1380 // Check for integer store | |
| 1381 if( src_first_rc == rc_int && dst_first_rc == rc_stack ) { | |
| 1382 int offset = ra_->reg2offset(dst_first); | |
| 1383 // Further check for aligned-adjacent pair, so we can use a double store | |
| 1384 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
| 1385 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stx_op3,"STX ",size, st); | |
| 1386 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stw_op3,"STW ",size, st); | |
| 1387 } | |
| 1388 | |
| 1389 // Check for integer load | |
| 1390 if( dst_first_rc == rc_int && src_first_rc == rc_stack ) { | |
| 1391 int offset = ra_->reg2offset(src_first); | |
| 1392 // Further check for aligned-adjacent pair, so we can use a double load | |
| 1393 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
| 1394 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldx_op3 ,"LDX ",size, st); | |
| 1395 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); | |
| 1396 } | |
| 1397 | |
| 1398 // Check for float reg-reg copy | |
| 1399 if( src_first_rc == rc_float && dst_first_rc == rc_float ) { | |
| 1400 // Further check for aligned-adjacent pair, so we can use a double move | |
| 1401 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
| 1402 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovd_opf,"FMOVD",size, st); | |
| 1403 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovs_opf,"FMOVS",size, st); | |
| 1404 } | |
| 1405 | |
| 1406 // Check for float store | |
| 1407 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) { | |
| 1408 int offset = ra_->reg2offset(dst_first); | |
| 1409 // Further check for aligned-adjacent pair, so we can use a double store | |
| 1410 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
| 1411 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stdf_op3,"STDF",size, st); | |
| 1412 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); | |
| 1413 } | |
| 1414 | |
| 1415 // Check for float load | |
| 1416 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) { | |
| 1417 int offset = ra_->reg2offset(src_first); | |
| 1418 // Further check for aligned-adjacent pair, so we can use a double load | |
| 1419 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
| 1420 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lddf_op3,"LDDF",size, st); | |
| 1421 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldf_op3 ,"LDF ",size, st); | |
| 1422 } | |
| 1423 | |
| 1424 // -------------------------------------------------------------------- | |
| 1425 // Check for hi bits still needing moving. Only happens for misaligned | |
| 1426 // arguments to native calls. | |
| 1427 if( src_second == dst_second ) | |
| 1428 return size; // Self copy; no move | |
| 1429 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" ); | |
| 1430 | |
| 1431 #ifndef _LP64 | |
| 1432 // In the LP64 build, all registers can be moved as aligned/adjacent | |
| 1433 // pairs, so there's never any need to move the high bits seperately. | |
| 1434 // The 32-bit builds have to deal with the 32-bit ABI which can force | |
| 1435 // all sorts of silly alignment problems. | |
| 1436 | |
| 1437 // Check for integer reg-reg copy. Hi bits are stuck up in the top | |
| 1438 // 32-bits of a 64-bit register, but are needed in low bits of another | |
| 1439 // register (else it's a hi-bits-to-hi-bits copy which should have | |
| 1440 // happened already as part of a 64-bit move) | |
| 1441 if( src_second_rc == rc_int && dst_second_rc == rc_int ) { | |
| 1442 assert( (src_second&1)==1, "its the evil O0/O1 native return case" ); | |
| 1443 assert( (dst_second&1)==0, "should have moved with 1 64-bit move" ); | |
| 1444 // Shift src_second down to dst_second's low bits. | |
| 1445 if( cbuf ) { | |
| 1446 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 ); | |
| 1447 #ifndef PRODUCT | |
| 1448 } else if( !do_size ) { | |
| 1449 if( size != 0 ) st->print("\n\t"); | |
| 1450 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(dst_second)); | |
| 1451 #endif | |
| 1452 } | |
| 1453 return size+4; | |
| 1454 } | |
| 1455 | |
| 1456 // Check for high word integer store. Must down-shift the hi bits | |
| 1457 // into a temp register, then fall into the case of storing int bits. | |
| 1458 if( src_second_rc == rc_int && dst_second_rc == rc_stack && (src_second&1)==1 ) { | |
| 1459 // Shift src_second down to dst_second's low bits. | |
| 1460 if( cbuf ) { | |
| 1461 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[R_O7_num], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 ); | |
| 1462 #ifndef PRODUCT | |
| 1463 } else if( !do_size ) { | |
| 1464 if( size != 0 ) st->print("\n\t"); | |
| 1465 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(R_O7_num)); | |
| 1466 #endif | |
| 1467 } | |
| 1468 size+=4; | |
| 1469 src_second = OptoReg::Name(R_O7_num); // Not R_O7H_num! | |
| 1470 } | |
| 1471 | |
| 1472 // Check for high word integer load | |
| 1473 if( dst_second_rc == rc_int && src_second_rc == rc_stack ) | |
| 1474 return impl_helper(this,cbuf,ra_,do_size,true ,ra_->reg2offset(src_second),dst_second,Assembler::lduw_op3,"LDUW",size, st); | |
| 1475 | |
| 1476 // Check for high word integer store | |
| 1477 if( src_second_rc == rc_int && dst_second_rc == rc_stack ) | |
| 1478 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stw_op3 ,"STW ",size, st); | |
| 1479 | |
| 1480 // Check for high word float store | |
| 1481 if( src_second_rc == rc_float && dst_second_rc == rc_stack ) | |
| 1482 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stf_op3 ,"STF ",size, st); | |
| 1483 | |
| 1484 #endif // !_LP64 | |
| 1485 | |
| 1486 Unimplemented(); | |
| 1487 } | |
| 1488 | |
| 1489 #ifndef PRODUCT | |
| 1490 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
| 1491 implementation( NULL, ra_, false, st ); | |
| 1492 } | |
| 1493 #endif | |
| 1494 | |
| 1495 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1496 implementation( &cbuf, ra_, false, NULL ); | |
| 1497 } | |
| 1498 | |
| 1499 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const { | |
| 1500 return implementation( NULL, ra_, true, NULL ); | |
| 1501 } | |
| 1502 | |
| 1503 //============================================================================= | |
| 1504 #ifndef PRODUCT | |
| 1505 void MachNopNode::format( PhaseRegAlloc *, outputStream *st ) const { | |
| 1506 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count); | |
| 1507 } | |
| 1508 #endif | |
| 1509 | |
| 1510 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const { | |
| 1511 MacroAssembler _masm(&cbuf); | |
| 1512 for(int i = 0; i < _count; i += 1) { | |
| 1513 __ nop(); | |
| 1514 } | |
| 1515 } | |
| 1516 | |
| 1517 uint MachNopNode::size(PhaseRegAlloc *ra_) const { | |
| 1518 return 4 * _count; | |
| 1519 } | |
| 1520 | |
| 1521 | |
| 1522 //============================================================================= | |
| 1523 #ifndef PRODUCT | |
| 1524 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
| 1525 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
| 1526 int reg = ra_->get_reg_first(this); | |
| 1527 st->print("LEA [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]); | |
| 1528 } | |
| 1529 #endif | |
| 1530 | |
| 1531 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1532 MacroAssembler _masm(&cbuf); | |
| 1533 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS; | |
| 1534 int reg = ra_->get_encode(this); | |
| 1535 | |
| 1536 if (Assembler::is_simm13(offset)) { | |
| 1537 __ add(SP, offset, reg_to_register_object(reg)); | |
| 1538 } else { | |
| 1539 __ set(offset, O7); | |
| 1540 __ add(SP, O7, reg_to_register_object(reg)); | |
| 1541 } | |
| 1542 } | |
| 1543 | |
| 1544 uint BoxLockNode::size(PhaseRegAlloc *ra_) const { | |
| 1545 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_) | |
| 1546 assert(ra_ == ra_->C->regalloc(), "sanity"); | |
| 1547 return ra_->C->scratch_emit_size(this); | |
| 1548 } | |
| 1549 | |
| 1550 //============================================================================= | |
| 1551 | |
| 1552 // emit call stub, compiled java to interpretor | |
| 1553 void emit_java_to_interp(CodeBuffer &cbuf ) { | |
| 1554 | |
| 1555 // Stub is fixed up when the corresponding call is converted from calling | |
| 1556 // compiled code to calling interpreted code. | |
| 1557 // set (empty), G5 | |
| 1558 // jmp -1 | |
| 1559 | |
| 1560 address mark = cbuf.inst_mark(); // get mark within main instrs section | |
| 1561 | |
| 1562 MacroAssembler _masm(&cbuf); | |
| 1563 | |
| 1564 address base = | |
| 1565 __ start_a_stub(Compile::MAX_stubs_size); | |
| 1566 if (base == NULL) return; // CodeBuffer::expand failed | |
| 1567 | |
| 1568 // static stub relocation stores the instruction address of the call | |
| 1569 __ relocate(static_stub_Relocation::spec(mark)); | |
| 1570 | |
| 1571 __ set_oop(NULL, reg_to_register_object(Matcher::inline_cache_reg_encode())); | |
| 1572 | |
| 1573 __ set_inst_mark(); | |
| 1574 Address a(G3, (address)-1); | |
| 1575 __ JUMP(a, 0); | |
| 1576 | |
| 1577 __ delayed()->nop(); | |
| 1578 | |
| 1579 // Update current stubs pointer and restore code_end. | |
| 1580 __ end_a_stub(); | |
| 1581 } | |
| 1582 | |
| 1583 // size of call stub, compiled java to interpretor | |
| 1584 uint size_java_to_interp() { | |
| 1585 // This doesn't need to be accurate but it must be larger or equal to | |
| 1586 // the real size of the stub. | |
| 1587 return (NativeMovConstReg::instruction_size + // sethi/setlo; | |
| 1588 NativeJump::instruction_size + // sethi; jmp; nop | |
| 1589 (TraceJumps ? 20 * BytesPerInstWord : 0) ); | |
| 1590 } | |
| 1591 // relocation entries for call stub, compiled java to interpretor | |
| 1592 uint reloc_java_to_interp() { | |
| 1593 return 10; // 4 in emit_java_to_interp + 1 in Java_Static_Call | |
| 1594 } | |
| 1595 | |
| 1596 | |
| 1597 //============================================================================= | |
| 1598 #ifndef PRODUCT | |
| 1599 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
| 1600 st->print_cr("\nUEP:"); | |
| 1601 #ifdef _LP64 | |
|
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1602 if (UseCompressedOops) { |
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1603 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass"); |
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1604 st->print_cr("\tSLL R_G5,3,R_G5"); |
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1605 st->print_cr("\tADD R_G5,R_G6_heap_base,R_G5"); |
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1606 } else { |
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1607 st->print_cr("\tLDX [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check"); |
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1608 } |
| 0 | 1609 st->print_cr("\tCMP R_G5,R_G3" ); |
| 1610 st->print ("\tTne xcc,R_G0+ST_RESERVED_FOR_USER_0+2"); | |
| 1611 #else // _LP64 | |
| 1612 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check"); | |
| 1613 st->print_cr("\tCMP R_G5,R_G3" ); | |
| 1614 st->print ("\tTne icc,R_G0+ST_RESERVED_FOR_USER_0+2"); | |
| 1615 #endif // _LP64 | |
| 1616 } | |
| 1617 #endif | |
| 1618 | |
| 1619 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1620 MacroAssembler _masm(&cbuf); | |
| 1621 Label L; | |
| 1622 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); | |
| 1623 Register temp_reg = G3; | |
| 1624 assert( G5_ic_reg != temp_reg, "conflicting registers" ); | |
| 1625 | |
| 1626 // Load klass from reciever | |
|
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1627 __ load_klass(O0, temp_reg); |
| 0 | 1628 // Compare against expected klass |
| 1629 __ cmp(temp_reg, G5_ic_reg); | |
| 1630 // Branch to miss code, checks xcc or icc depending | |
| 1631 __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2); | |
| 1632 } | |
| 1633 | |
| 1634 uint MachUEPNode::size(PhaseRegAlloc *ra_) const { | |
| 1635 return MachNode::size(ra_); | |
| 1636 } | |
| 1637 | |
| 1638 | |
| 1639 //============================================================================= | |
| 1640 | |
| 1641 uint size_exception_handler() { | |
| 1642 if (TraceJumps) { | |
| 1643 return (400); // just a guess | |
| 1644 } | |
| 1645 return ( NativeJump::instruction_size ); // sethi;jmp;nop | |
| 1646 } | |
| 1647 | |
| 1648 uint size_deopt_handler() { | |
| 1649 if (TraceJumps) { | |
| 1650 return (400); // just a guess | |
| 1651 } | |
| 1652 return ( 4+ NativeJump::instruction_size ); // save;sethi;jmp;restore | |
| 1653 } | |
| 1654 | |
| 1655 // Emit exception handler code. | |
| 1656 int emit_exception_handler(CodeBuffer& cbuf) { | |
| 1657 Register temp_reg = G3; | |
| 1658 Address exception_blob(temp_reg, OptoRuntime::exception_blob()->instructions_begin()); | |
| 1659 MacroAssembler _masm(&cbuf); | |
| 1660 | |
| 1661 address base = | |
| 1662 __ start_a_stub(size_exception_handler()); | |
| 1663 if (base == NULL) return 0; // CodeBuffer::expand failed | |
| 1664 | |
| 1665 int offset = __ offset(); | |
| 1666 | |
| 1667 __ JUMP(exception_blob, 0); // sethi;jmp | |
| 1668 __ delayed()->nop(); | |
| 1669 | |
| 1670 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow"); | |
| 1671 | |
| 1672 __ end_a_stub(); | |
| 1673 | |
| 1674 return offset; | |
| 1675 } | |
| 1676 | |
| 1677 int emit_deopt_handler(CodeBuffer& cbuf) { | |
| 1678 // Can't use any of the current frame's registers as we may have deopted | |
| 1679 // at a poll and everything (including G3) can be live. | |
| 1680 Register temp_reg = L0; | |
| 1681 Address deopt_blob(temp_reg, SharedRuntime::deopt_blob()->unpack()); | |
| 1682 MacroAssembler _masm(&cbuf); | |
| 1683 | |
| 1684 address base = | |
| 1685 __ start_a_stub(size_deopt_handler()); | |
| 1686 if (base == NULL) return 0; // CodeBuffer::expand failed | |
| 1687 | |
| 1688 int offset = __ offset(); | |
| 1689 __ save_frame(0); | |
| 1690 __ JUMP(deopt_blob, 0); // sethi;jmp | |
| 1691 __ delayed()->restore(); | |
| 1692 | |
| 1693 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow"); | |
| 1694 | |
| 1695 __ end_a_stub(); | |
| 1696 return offset; | |
| 1697 | |
| 1698 } | |
| 1699 | |
| 1700 // Given a register encoding, produce a Integer Register object | |
| 1701 static Register reg_to_register_object(int register_encoding) { | |
| 1702 assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding"); | |
| 1703 return as_Register(register_encoding); | |
| 1704 } | |
| 1705 | |
| 1706 // Given a register encoding, produce a single-precision Float Register object | |
| 1707 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) { | |
| 1708 assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding"); | |
| 1709 return as_SingleFloatRegister(register_encoding); | |
| 1710 } | |
| 1711 | |
| 1712 // Given a register encoding, produce a double-precision Float Register object | |
| 1713 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) { | |
| 1714 assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding"); | |
| 1715 assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding"); | |
| 1716 return as_DoubleFloatRegister(register_encoding); | |
| 1717 } | |
| 1718 | |
| 1719 int Matcher::regnum_to_fpu_offset(int regnum) { | |
| 1720 return regnum - 32; // The FP registers are in the second chunk | |
| 1721 } | |
| 1722 | |
| 1723 #ifdef ASSERT | |
| 1724 address last_rethrow = NULL; // debugging aid for Rethrow encoding | |
| 1725 #endif | |
| 1726 | |
| 1727 // Vector width in bytes | |
| 1728 const uint Matcher::vector_width_in_bytes(void) { | |
| 1729 return 8; | |
| 1730 } | |
| 1731 | |
| 1732 // Vector ideal reg | |
| 1733 const uint Matcher::vector_ideal_reg(void) { | |
| 1734 return Op_RegD; | |
| 1735 } | |
| 1736 | |
| 1737 // USII supports fxtof through the whole range of number, USIII doesn't | |
| 1738 const bool Matcher::convL2FSupported(void) { | |
| 1739 return VM_Version::has_fast_fxtof(); | |
| 1740 } | |
| 1741 | |
| 1742 // Is this branch offset short enough that a short branch can be used? | |
| 1743 // | |
| 1744 // NOTE: If the platform does not provide any short branch variants, then | |
| 1745 // this method should return false for offset 0. | |
| 1746 bool Matcher::is_short_branch_offset(int offset) { | |
| 1747 return false; | |
| 1748 } | |
| 1749 | |
| 1750 const bool Matcher::isSimpleConstant64(jlong value) { | |
| 1751 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?. | |
| 1752 // Depends on optimizations in MacroAssembler::setx. | |
| 1753 int hi = (int)(value >> 32); | |
| 1754 int lo = (int)(value & ~0); | |
| 1755 return (hi == 0) || (hi == -1) || (lo == 0); | |
| 1756 } | |
| 1757 | |
| 1758 // No scaling for the parameter the ClearArray node. | |
| 1759 const bool Matcher::init_array_count_is_in_bytes = true; | |
| 1760 | |
| 1761 // Threshold size for cleararray. | |
| 1762 const int Matcher::init_array_short_size = 8 * BytesPerLong; | |
| 1763 | |
| 1764 // Should the Matcher clone shifts on addressing modes, expecting them to | |
| 1765 // be subsumed into complex addressing expressions or compute them into | |
| 1766 // registers? True for Intel but false for most RISCs | |
| 1767 const bool Matcher::clone_shift_expressions = false; | |
| 1768 | |
| 1769 // Is it better to copy float constants, or load them directly from memory? | |
| 1770 // Intel can load a float constant from a direct address, requiring no | |
| 1771 // extra registers. Most RISCs will have to materialize an address into a | |
| 1772 // register first, so they would do better to copy the constant from stack. | |
| 1773 const bool Matcher::rematerialize_float_constants = false; | |
| 1774 | |
| 1775 // If CPU can load and store mis-aligned doubles directly then no fixup is | |
| 1776 // needed. Else we split the double into 2 integer pieces and move it | |
| 1777 // piece-by-piece. Only happens when passing doubles into C code as the | |
| 1778 // Java calling convention forces doubles to be aligned. | |
| 1779 #ifdef _LP64 | |
| 1780 const bool Matcher::misaligned_doubles_ok = true; | |
| 1781 #else | |
| 1782 const bool Matcher::misaligned_doubles_ok = false; | |
| 1783 #endif | |
| 1784 | |
| 1785 // No-op on SPARC. | |
| 1786 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) { | |
| 1787 } | |
| 1788 | |
| 1789 // Advertise here if the CPU requires explicit rounding operations | |
| 1790 // to implement the UseStrictFP mode. | |
| 1791 const bool Matcher::strict_fp_requires_explicit_rounding = false; | |
| 1792 | |
| 1793 // Do floats take an entire double register or just half? | |
| 1794 const bool Matcher::float_in_double = false; | |
| 1795 | |
| 1796 // Do ints take an entire long register or just half? | |
| 1797 // Note that we if-def off of _LP64. | |
| 1798 // The relevant question is how the int is callee-saved. In _LP64 | |
| 1799 // the whole long is written but de-opt'ing will have to extract | |
| 1800 // the relevant 32 bits, in not-_LP64 only the low 32 bits is written. | |
| 1801 #ifdef _LP64 | |
| 1802 const bool Matcher::int_in_long = true; | |
| 1803 #else | |
| 1804 const bool Matcher::int_in_long = false; | |
| 1805 #endif | |
| 1806 | |
| 1807 // Return whether or not this register is ever used as an argument. This | |
| 1808 // function is used on startup to build the trampoline stubs in generateOptoStub. | |
| 1809 // Registers not mentioned will be killed by the VM call in the trampoline, and | |
| 1810 // arguments in those registers not be available to the callee. | |
| 1811 bool Matcher::can_be_java_arg( int reg ) { | |
| 1812 // Standard sparc 6 args in registers | |
| 1813 if( reg == R_I0_num || | |
| 1814 reg == R_I1_num || | |
| 1815 reg == R_I2_num || | |
| 1816 reg == R_I3_num || | |
| 1817 reg == R_I4_num || | |
| 1818 reg == R_I5_num ) return true; | |
| 1819 #ifdef _LP64 | |
| 1820 // 64-bit builds can pass 64-bit pointers and longs in | |
| 1821 // the high I registers | |
| 1822 if( reg == R_I0H_num || | |
| 1823 reg == R_I1H_num || | |
| 1824 reg == R_I2H_num || | |
| 1825 reg == R_I3H_num || | |
| 1826 reg == R_I4H_num || | |
| 1827 reg == R_I5H_num ) return true; | |
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1828 |
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1829 if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) { |
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1830 return true; |
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1831 } |
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1832 |
| 0 | 1833 #else |
| 1834 // 32-bit builds with longs-in-one-entry pass longs in G1 & G4. | |
| 1835 // Longs cannot be passed in O regs, because O regs become I regs | |
| 1836 // after a 'save' and I regs get their high bits chopped off on | |
| 1837 // interrupt. | |
| 1838 if( reg == R_G1H_num || reg == R_G1_num ) return true; | |
| 1839 if( reg == R_G4H_num || reg == R_G4_num ) return true; | |
| 1840 #endif | |
| 1841 // A few float args in registers | |
| 1842 if( reg >= R_F0_num && reg <= R_F7_num ) return true; | |
| 1843 | |
| 1844 return false; | |
| 1845 } | |
| 1846 | |
| 1847 bool Matcher::is_spillable_arg( int reg ) { | |
| 1848 return can_be_java_arg(reg); | |
| 1849 } | |
| 1850 | |
| 1851 // Register for DIVI projection of divmodI | |
| 1852 RegMask Matcher::divI_proj_mask() { | |
| 1853 ShouldNotReachHere(); | |
| 1854 return RegMask(); | |
| 1855 } | |
| 1856 | |
| 1857 // Register for MODI projection of divmodI | |
| 1858 RegMask Matcher::modI_proj_mask() { | |
| 1859 ShouldNotReachHere(); | |
| 1860 return RegMask(); | |
| 1861 } | |
| 1862 | |
| 1863 // Register for DIVL projection of divmodL | |
| 1864 RegMask Matcher::divL_proj_mask() { | |
| 1865 ShouldNotReachHere(); | |
| 1866 return RegMask(); | |
| 1867 } | |
| 1868 | |
| 1869 // Register for MODL projection of divmodL | |
| 1870 RegMask Matcher::modL_proj_mask() { | |
| 1871 ShouldNotReachHere(); | |
| 1872 return RegMask(); | |
| 1873 } | |
| 1874 | |
| 1875 %} | |
| 1876 | |
| 1877 | |
| 1878 // The intptr_t operand types, defined by textual substitution. | |
| 1879 // (Cf. opto/type.hpp. This lets us avoid many, many other ifdefs.) | |
| 1880 #ifdef _LP64 | |
| 1881 #define immX immL | |
| 1882 #define immX13 immL13 | |
| 1883 #define iRegX iRegL | |
| 1884 #define g1RegX g1RegL | |
| 1885 #else | |
| 1886 #define immX immI | |
| 1887 #define immX13 immI13 | |
| 1888 #define iRegX iRegI | |
| 1889 #define g1RegX g1RegI | |
| 1890 #endif | |
| 1891 | |
| 1892 //----------ENCODING BLOCK----------------------------------------------------- | |
| 1893 // This block specifies the encoding classes used by the compiler to output | |
| 1894 // byte streams. Encoding classes are parameterized macros used by | |
| 1895 // Machine Instruction Nodes in order to generate the bit encoding of the | |
| 1896 // instruction. Operands specify their base encoding interface with the | |
| 1897 // interface keyword. There are currently supported four interfaces, | |
| 1898 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an | |
| 1899 // operand to generate a function which returns its register number when | |
| 1900 // queried. CONST_INTER causes an operand to generate a function which | |
| 1901 // returns the value of the constant when queried. MEMORY_INTER causes an | |
| 1902 // operand to generate four functions which return the Base Register, the | |
| 1903 // Index Register, the Scale Value, and the Offset Value of the operand when | |
| 1904 // queried. COND_INTER causes an operand to generate six functions which | |
| 1905 // return the encoding code (ie - encoding bits for the instruction) | |
| 1906 // associated with each basic boolean condition for a conditional instruction. | |
| 1907 // | |
| 1908 // Instructions specify two basic values for encoding. Again, a function | |
| 1909 // is available to check if the constant displacement is an oop. They use the | |
| 1910 // ins_encode keyword to specify their encoding classes (which must be | |
| 1911 // a sequence of enc_class names, and their parameters, specified in | |
| 1912 // the encoding block), and they use the | |
| 1913 // opcode keyword to specify, in order, their primary, secondary, and | |
| 1914 // tertiary opcode. Only the opcode sections which a particular instruction | |
| 1915 // needs for encoding need to be specified. | |
| 1916 encode %{ | |
| 1917 enc_class enc_untested %{ | |
| 1918 #ifdef ASSERT | |
| 1919 MacroAssembler _masm(&cbuf); | |
| 1920 __ untested("encoding"); | |
| 1921 #endif | |
| 1922 %} | |
| 1923 | |
| 1924 enc_class form3_mem_reg( memory mem, iRegI dst ) %{ | |
| 1925 emit_form3_mem_reg(cbuf, this, $primary, $tertiary, | |
| 1926 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg); | |
| 1927 %} | |
| 1928 | |
| 1929 enc_class form3_mem_reg_little( memory mem, iRegI dst) %{ | |
| 1930 emit_form3_mem_reg_asi(cbuf, this, $primary, $tertiary, | |
| 1931 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg, Assembler::ASI_PRIMARY_LITTLE); | |
| 1932 %} | |
| 1933 | |
| 1934 enc_class form3_mem_prefetch_read( memory mem ) %{ | |
| 1935 emit_form3_mem_reg(cbuf, this, $primary, $tertiary, | |
| 1936 $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/); | |
| 1937 %} | |
| 1938 | |
| 1939 enc_class form3_mem_prefetch_write( memory mem ) %{ | |
| 1940 emit_form3_mem_reg(cbuf, this, $primary, $tertiary, | |
| 1941 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/); | |
| 1942 %} | |
| 1943 | |
| 1944 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{ | |
| 1945 assert( Assembler::is_simm13($mem$$disp ), "need disp and disp+4" ); | |
| 1946 assert( Assembler::is_simm13($mem$$disp+4), "need disp and disp+4" ); | |
| 1947 guarantee($mem$$index == R_G0_enc, "double index?"); | |
| 1948 emit_form3_mem_reg(cbuf, this, $primary, $tertiary, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc ); | |
| 1949 emit_form3_mem_reg(cbuf, this, $primary, $tertiary, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg ); | |
| 1950 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 ); | |
| 1951 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc ); | |
| 1952 %} | |
| 1953 | |
| 1954 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{ | |
| 1955 assert( Assembler::is_simm13($mem$$disp ), "need disp and disp+4" ); | |
| 1956 assert( Assembler::is_simm13($mem$$disp+4), "need disp and disp+4" ); | |
| 1957 guarantee($mem$$index == R_G0_enc, "double index?"); | |
| 1958 // Load long with 2 instructions | |
| 1959 emit_form3_mem_reg(cbuf, this, $primary, $tertiary, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 ); | |
| 1960 emit_form3_mem_reg(cbuf, this, $primary, $tertiary, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 ); | |
| 1961 %} | |
| 1962 | |
| 1963 //%%% form3_mem_plus_4_reg is a hack--get rid of it | |
| 1964 enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{ | |
| 1965 guarantee($mem$$disp, "cannot offset a reg-reg operand by 4"); | |
| 1966 emit_form3_mem_reg(cbuf, this, $primary, $tertiary, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg); | |
| 1967 %} | |
| 1968 | |
| 1969 enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{ | |
| 1970 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
| 1971 if( $rs2$$reg != $rd$$reg ) | |
| 1972 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg ); | |
| 1973 %} | |
| 1974 | |
| 1975 // Target lo half of long | |
| 1976 enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{ | |
| 1977 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
| 1978 if( $rs2$$reg != LONG_LO_REG($rd$$reg) ) | |
| 1979 emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg ); | |
| 1980 %} | |
| 1981 | |
| 1982 // Source lo half of long | |
| 1983 enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{ | |
| 1984 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
| 1985 if( LONG_LO_REG($rs2$$reg) != $rd$$reg ) | |
| 1986 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) ); | |
| 1987 %} | |
| 1988 | |
| 1989 // Target hi half of long | |
| 1990 enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{ | |
| 1991 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 ); | |
| 1992 %} | |
| 1993 | |
| 1994 // Source lo half of long, and leave it sign extended. | |
| 1995 enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{ | |
| 1996 // Sign extend low half | |
| 1997 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 ); | |
| 1998 %} | |
| 1999 | |
| 2000 // Source hi half of long, and leave it sign extended. | |
| 2001 enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{ | |
| 2002 // Shift high half to low half | |
| 2003 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 ); | |
| 2004 %} | |
| 2005 | |
| 2006 // Source hi half of long | |
| 2007 enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{ | |
| 2008 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
| 2009 if( LONG_HI_REG($rs2$$reg) != $rd$$reg ) | |
| 2010 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) ); | |
| 2011 %} | |
| 2012 | |
| 2013 enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{ | |
| 2014 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg ); | |
| 2015 %} | |
| 2016 | |
| 2017 enc_class enc_to_bool( iRegI src, iRegI dst ) %{ | |
| 2018 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, 0, 0, $src$$reg ); | |
| 2019 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 ); | |
| 2020 %} | |
| 2021 | |
| 2022 enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{ | |
| 2023 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg ); | |
| 2024 // clear if nothing else is happening | |
| 2025 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 0 ); | |
| 2026 // blt,a,pn done | |
| 2027 emit2_19 ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 ); | |
| 2028 // mov dst,-1 in delay slot | |
| 2029 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 ); | |
| 2030 %} | |
| 2031 | |
| 2032 enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{ | |
| 2033 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F ); | |
| 2034 %} | |
| 2035 | |
| 2036 enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{ | |
| 2037 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 ); | |
| 2038 %} | |
| 2039 | |
| 2040 enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{ | |
| 2041 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg ); | |
| 2042 %} | |
| 2043 | |
| 2044 enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{ | |
| 2045 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant ); | |
| 2046 %} | |
| 2047 | |
| 2048 enc_class move_return_pc_to_o1() %{ | |
| 2049 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset ); | |
| 2050 %} | |
| 2051 | |
| 2052 #ifdef _LP64 | |
| 2053 /* %%% merge with enc_to_bool */ | |
| 2054 enc_class enc_convP2B( iRegI dst, iRegP src ) %{ | |
| 2055 MacroAssembler _masm(&cbuf); | |
| 2056 | |
| 2057 Register src_reg = reg_to_register_object($src$$reg); | |
| 2058 Register dst_reg = reg_to_register_object($dst$$reg); | |
| 2059 __ movr(Assembler::rc_nz, src_reg, 1, dst_reg); | |
| 2060 %} | |
| 2061 #endif | |
| 2062 | |
| 2063 enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{ | |
| 2064 // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))) | |
| 2065 MacroAssembler _masm(&cbuf); | |
| 2066 | |
| 2067 Register p_reg = reg_to_register_object($p$$reg); | |
| 2068 Register q_reg = reg_to_register_object($q$$reg); | |
| 2069 Register y_reg = reg_to_register_object($y$$reg); | |
| 2070 Register tmp_reg = reg_to_register_object($tmp$$reg); | |
| 2071 | |
| 2072 __ subcc( p_reg, q_reg, p_reg ); | |
| 2073 __ add ( p_reg, y_reg, tmp_reg ); | |
| 2074 __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg ); | |
| 2075 %} | |
| 2076 | |
| 2077 enc_class form_d2i_helper(regD src, regF dst) %{ | |
| 2078 // fcmp %fcc0,$src,$src | |
| 2079 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg ); | |
| 2080 // branch %fcc0 not-nan, predict taken | |
| 2081 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); | |
| 2082 // fdtoi $src,$dst | |
| 2083 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtoi_opf, $src$$reg ); | |
| 2084 // fitos $dst,$dst (if nan) | |
| 2085 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg ); | |
| 2086 // clear $dst (if nan) | |
| 2087 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg ); | |
| 2088 // carry on here... | |
| 2089 %} | |
| 2090 | |
| 2091 enc_class form_d2l_helper(regD src, regD dst) %{ | |
| 2092 // fcmp %fcc0,$src,$src check for NAN | |
| 2093 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg ); | |
| 2094 // branch %fcc0 not-nan, predict taken | |
| 2095 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); | |
| 2096 // fdtox $src,$dst convert in delay slot | |
| 2097 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtox_opf, $src$$reg ); | |
| 2098 // fxtod $dst,$dst (if nan) | |
| 2099 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg ); | |
| 2100 // clear $dst (if nan) | |
| 2101 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg ); | |
| 2102 // carry on here... | |
| 2103 %} | |
| 2104 | |
| 2105 enc_class form_f2i_helper(regF src, regF dst) %{ | |
| 2106 // fcmps %fcc0,$src,$src | |
| 2107 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg ); | |
| 2108 // branch %fcc0 not-nan, predict taken | |
| 2109 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); | |
| 2110 // fstoi $src,$dst | |
| 2111 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstoi_opf, $src$$reg ); | |
| 2112 // fitos $dst,$dst (if nan) | |
| 2113 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg ); | |
| 2114 // clear $dst (if nan) | |
| 2115 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg ); | |
| 2116 // carry on here... | |
| 2117 %} | |
| 2118 | |
| 2119 enc_class form_f2l_helper(regF src, regD dst) %{ | |
| 2120 // fcmps %fcc0,$src,$src | |
| 2121 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg ); | |
| 2122 // branch %fcc0 not-nan, predict taken | |
| 2123 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); | |
| 2124 // fstox $src,$dst | |
| 2125 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstox_opf, $src$$reg ); | |
| 2126 // fxtod $dst,$dst (if nan) | |
| 2127 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg ); | |
| 2128 // clear $dst (if nan) | |
| 2129 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg ); | |
| 2130 // carry on here... | |
| 2131 %} | |
| 2132 | |
| 2133 enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
| 2134 enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
| 2135 enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
| 2136 enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
| 2137 | |
| 2138 enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %} | |
| 2139 | |
| 2140 enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
| 2141 enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %} | |
| 2142 | |
| 2143 enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{ | |
| 2144 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); | |
| 2145 %} | |
| 2146 | |
| 2147 enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{ | |
| 2148 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); | |
| 2149 %} | |
| 2150 | |
| 2151 enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{ | |
| 2152 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); | |
| 2153 %} | |
| 2154 | |
| 2155 enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{ | |
| 2156 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); | |
| 2157 %} | |
| 2158 | |
| 2159 enc_class form3_convI2F(regF rs2, regF rd) %{ | |
| 2160 emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg); | |
| 2161 %} | |
| 2162 | |
| 2163 // Encloding class for traceable jumps | |
| 2164 enc_class form_jmpl(g3RegP dest) %{ | |
| 2165 emit_jmpl(cbuf, $dest$$reg); | |
| 2166 %} | |
| 2167 | |
| 2168 enc_class form_jmpl_set_exception_pc(g1RegP dest) %{ | |
| 2169 emit_jmpl_set_exception_pc(cbuf, $dest$$reg); | |
| 2170 %} | |
| 2171 | |
| 2172 enc_class form2_nop() %{ | |
| 2173 emit_nop(cbuf); | |
| 2174 %} | |
| 2175 | |
| 2176 enc_class form2_illtrap() %{ | |
| 2177 emit_illtrap(cbuf); | |
| 2178 %} | |
| 2179 | |
| 2180 | |
| 2181 // Compare longs and convert into -1, 0, 1. | |
| 2182 enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{ | |
| 2183 // CMP $src1,$src2 | |
| 2184 emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg ); | |
| 2185 // blt,a,pn done | |
| 2186 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 ); | |
| 2187 // mov dst,-1 in delay slot | |
| 2188 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 ); | |
| 2189 // bgt,a,pn done | |
| 2190 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 ); | |
| 2191 // mov dst,1 in delay slot | |
| 2192 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 1 ); | |
| 2193 // CLR $dst | |
| 2194 emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 ); | |
| 2195 %} | |
| 2196 | |
| 2197 enc_class enc_PartialSubtypeCheck() %{ | |
| 2198 MacroAssembler _masm(&cbuf); | |
| 2199 __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type); | |
| 2200 __ delayed()->nop(); | |
| 2201 %} | |
| 2202 | |
| 2203 enc_class enc_bp( Label labl, cmpOp cmp, flagsReg cc ) %{ | |
| 2204 MacroAssembler _masm(&cbuf); | |
| 2205 Label &L = *($labl$$label); | |
| 2206 Assembler::Predict predict_taken = | |
| 2207 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; | |
| 2208 | |
| 2209 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, L); | |
| 2210 __ delayed()->nop(); | |
| 2211 %} | |
| 2212 | |
| 2213 enc_class enc_bpl( Label labl, cmpOp cmp, flagsRegL cc ) %{ | |
| 2214 MacroAssembler _masm(&cbuf); | |
| 2215 Label &L = *($labl$$label); | |
| 2216 Assembler::Predict predict_taken = | |
| 2217 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; | |
| 2218 | |
| 2219 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, L); | |
| 2220 __ delayed()->nop(); | |
| 2221 %} | |
| 2222 | |
| 2223 enc_class enc_bpx( Label labl, cmpOp cmp, flagsRegP cc ) %{ | |
| 2224 MacroAssembler _masm(&cbuf); | |
| 2225 Label &L = *($labl$$label); | |
| 2226 Assembler::Predict predict_taken = | |
| 2227 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; | |
| 2228 | |
| 2229 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, L); | |
| 2230 __ delayed()->nop(); | |
| 2231 %} | |
| 2232 | |
| 2233 enc_class enc_fbp( Label labl, cmpOpF cmp, flagsRegF cc ) %{ | |
| 2234 MacroAssembler _masm(&cbuf); | |
| 2235 Label &L = *($labl$$label); | |
| 2236 Assembler::Predict predict_taken = | |
| 2237 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; | |
| 2238 | |
| 2239 __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($cc$$reg), predict_taken, L); | |
| 2240 __ delayed()->nop(); | |
| 2241 %} | |
| 2242 | |
| 2243 enc_class jump_enc( iRegX switch_val, o7RegI table) %{ | |
| 2244 MacroAssembler _masm(&cbuf); | |
| 2245 | |
| 2246 Register switch_reg = as_Register($switch_val$$reg); | |
| 2247 Register table_reg = O7; | |
| 2248 | |
| 2249 address table_base = __ address_table_constant(_index2label); | |
| 2250 RelocationHolder rspec = internal_word_Relocation::spec(table_base); | |
| 2251 | |
| 2252 // Load table address | |
| 2253 Address the_pc(table_reg, table_base, rspec); | |
| 2254 __ load_address(the_pc); | |
| 2255 | |
| 2256 // Jump to base address + switch value | |
| 2257 __ ld_ptr(table_reg, switch_reg, table_reg); | |
| 2258 __ jmp(table_reg, G0); | |
| 2259 __ delayed()->nop(); | |
| 2260 | |
| 2261 %} | |
| 2262 | |
| 2263 enc_class enc_ba( Label labl ) %{ | |
| 2264 MacroAssembler _masm(&cbuf); | |
| 2265 Label &L = *($labl$$label); | |
| 2266 __ ba(false, L); | |
| 2267 __ delayed()->nop(); | |
| 2268 %} | |
| 2269 | |
| 2270 enc_class enc_bpr( Label labl, cmpOp_reg cmp, iRegI op1 ) %{ | |
| 2271 MacroAssembler _masm(&cbuf); | |
| 2272 Label &L = *$labl$$label; | |
| 2273 Assembler::Predict predict_taken = | |
| 2274 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; | |
| 2275 | |
| 2276 __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), L); | |
| 2277 __ delayed()->nop(); | |
| 2278 %} | |
| 2279 | |
| 2280 enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{ | |
| 2281 int op = (Assembler::arith_op << 30) | | |
| 2282 ($dst$$reg << 25) | | |
| 2283 (Assembler::movcc_op3 << 19) | | |
| 2284 (1 << 18) | // cc2 bit for 'icc' | |
| 2285 ($cmp$$cmpcode << 14) | | |
| 2286 (0 << 13) | // select register move | |
| 2287 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' or 'xcc' | |
| 2288 ($src$$reg << 0); | |
| 2289 *((int*)(cbuf.code_end())) = op; | |
| 2290 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
| 2291 %} | |
| 2292 | |
| 2293 enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{ | |
| 2294 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits | |
| 2295 int op = (Assembler::arith_op << 30) | | |
| 2296 ($dst$$reg << 25) | | |
| 2297 (Assembler::movcc_op3 << 19) | | |
| 2298 (1 << 18) | // cc2 bit for 'icc' | |
| 2299 ($cmp$$cmpcode << 14) | | |
| 2300 (1 << 13) | // select immediate move | |
| 2301 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' | |
| 2302 (simm11 << 0); | |
| 2303 *((int*)(cbuf.code_end())) = op; | |
| 2304 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
| 2305 %} | |
| 2306 | |
| 2307 enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{ | |
| 2308 int op = (Assembler::arith_op << 30) | | |
| 2309 ($dst$$reg << 25) | | |
| 2310 (Assembler::movcc_op3 << 19) | | |
| 2311 (0 << 18) | // cc2 bit for 'fccX' | |
| 2312 ($cmp$$cmpcode << 14) | | |
| 2313 (0 << 13) | // select register move | |
| 2314 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3 | |
| 2315 ($src$$reg << 0); | |
| 2316 *((int*)(cbuf.code_end())) = op; | |
| 2317 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
| 2318 %} | |
| 2319 | |
| 2320 enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{ | |
| 2321 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits | |
| 2322 int op = (Assembler::arith_op << 30) | | |
| 2323 ($dst$$reg << 25) | | |
| 2324 (Assembler::movcc_op3 << 19) | | |
| 2325 (0 << 18) | // cc2 bit for 'fccX' | |
| 2326 ($cmp$$cmpcode << 14) | | |
| 2327 (1 << 13) | // select immediate move | |
| 2328 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3 | |
| 2329 (simm11 << 0); | |
| 2330 *((int*)(cbuf.code_end())) = op; | |
| 2331 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
| 2332 %} | |
| 2333 | |
| 2334 enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{ | |
| 2335 int op = (Assembler::arith_op << 30) | | |
| 2336 ($dst$$reg << 25) | | |
| 2337 (Assembler::fpop2_op3 << 19) | | |
| 2338 (0 << 18) | | |
| 2339 ($cmp$$cmpcode << 14) | | |
| 2340 (1 << 13) | // select register move | |
| 2341 ($pcc$$constant << 11) | // cc1-cc0 bits for 'icc' or 'xcc' | |
| 2342 ($primary << 5) | // select single, double or quad | |
| 2343 ($src$$reg << 0); | |
| 2344 *((int*)(cbuf.code_end())) = op; | |
| 2345 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
| 2346 %} | |
| 2347 | |
| 2348 enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{ | |
| 2349 int op = (Assembler::arith_op << 30) | | |
| 2350 ($dst$$reg << 25) | | |
| 2351 (Assembler::fpop2_op3 << 19) | | |
| 2352 (0 << 18) | | |
| 2353 ($cmp$$cmpcode << 14) | | |
| 2354 ($fcc$$reg << 11) | // cc2-cc0 bits for 'fccX' | |
| 2355 ($primary << 5) | // select single, double or quad | |
| 2356 ($src$$reg << 0); | |
| 2357 *((int*)(cbuf.code_end())) = op; | |
| 2358 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
| 2359 %} | |
| 2360 | |
| 2361 // Used by the MIN/MAX encodings. Same as a CMOV, but | |
| 2362 // the condition comes from opcode-field instead of an argument. | |
| 2363 enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{ | |
| 2364 int op = (Assembler::arith_op << 30) | | |
| 2365 ($dst$$reg << 25) | | |
| 2366 (Assembler::movcc_op3 << 19) | | |
| 2367 (1 << 18) | // cc2 bit for 'icc' | |
| 2368 ($primary << 14) | | |
| 2369 (0 << 13) | // select register move | |
| 2370 (0 << 11) | // cc1, cc0 bits for 'icc' | |
| 2371 ($src$$reg << 0); | |
| 2372 *((int*)(cbuf.code_end())) = op; | |
| 2373 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
| 2374 %} | |
| 2375 | |
| 2376 enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{ | |
| 2377 int op = (Assembler::arith_op << 30) | | |
| 2378 ($dst$$reg << 25) | | |
| 2379 (Assembler::movcc_op3 << 19) | | |
| 2380 (6 << 16) | // cc2 bit for 'xcc' | |
| 2381 ($primary << 14) | | |
| 2382 (0 << 13) | // select register move | |
| 2383 (0 << 11) | // cc1, cc0 bits for 'icc' | |
| 2384 ($src$$reg << 0); | |
| 2385 *((int*)(cbuf.code_end())) = op; | |
| 2386 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
| 2387 %} | |
| 2388 | |
| 2389 // Utility encoding for loading a 64 bit Pointer into a register | |
| 2390 // The 64 bit pointer is stored in the generated code stream | |
| 2391 enc_class SetPtr( immP src, iRegP rd ) %{ | |
| 2392 Register dest = reg_to_register_object($rd$$reg); | |
| 2393 // [RGV] This next line should be generated from ADLC | |
| 2394 if ( _opnds[1]->constant_is_oop() ) { | |
| 2395 intptr_t val = $src$$constant; | |
| 2396 MacroAssembler _masm(&cbuf); | |
| 2397 __ set_oop_constant((jobject)val, dest); | |
| 2398 } else { // non-oop pointers, e.g. card mark base, heap top | |
| 2399 emit_ptr(cbuf, $src$$constant, dest, /*ForceRelocatable=*/ false); | |
| 2400 } | |
| 2401 %} | |
| 2402 | |
| 2403 enc_class Set13( immI13 src, iRegI rd ) %{ | |
| 2404 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant ); | |
| 2405 %} | |
| 2406 | |
| 2407 enc_class SetHi22( immI src, iRegI rd ) %{ | |
| 2408 emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant ); | |
| 2409 %} | |
| 2410 | |
| 2411 enc_class Set32( immI src, iRegI rd ) %{ | |
| 2412 MacroAssembler _masm(&cbuf); | |
| 2413 __ set($src$$constant, reg_to_register_object($rd$$reg)); | |
| 2414 %} | |
| 2415 | |
| 2416 enc_class SetNull( iRegI rd ) %{ | |
| 2417 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0 ); | |
| 2418 %} | |
| 2419 | |
| 2420 enc_class call_epilog %{ | |
| 2421 if( VerifyStackAtCalls ) { | |
| 2422 MacroAssembler _masm(&cbuf); | |
| 2423 int framesize = ra_->C->frame_slots() << LogBytesPerInt; | |
| 2424 Register temp_reg = G3; | |
| 2425 __ add(SP, framesize, temp_reg); | |
| 2426 __ cmp(temp_reg, FP); | |
| 2427 __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc); | |
| 2428 } | |
| 2429 %} | |
| 2430 | |
| 2431 // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value | |
| 2432 // to G1 so the register allocator will not have to deal with the misaligned register | |
| 2433 // pair. | |
| 2434 enc_class adjust_long_from_native_call %{ | |
| 2435 #ifndef _LP64 | |
| 2436 if (returns_long()) { | |
| 2437 // sllx O0,32,O0 | |
| 2438 emit3_simm13( cbuf, Assembler::arith_op, R_O0_enc, Assembler::sllx_op3, R_O0_enc, 0x1020 ); | |
| 2439 // srl O1,0,O1 | |
| 2440 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::srl_op3, R_O1_enc, 0x0000 ); | |
| 2441 // or O0,O1,G1 | |
| 2442 emit3 ( cbuf, Assembler::arith_op, R_G1_enc, Assembler:: or_op3, R_O0_enc, 0, R_O1_enc ); | |
| 2443 } | |
| 2444 #endif | |
| 2445 %} | |
| 2446 | |
| 2447 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime | |
| 2448 // CALL directly to the runtime | |
| 2449 // The user of this is responsible for ensuring that R_L7 is empty (killed). | |
| 2450 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type, | |
| 2451 /*preserve_g2=*/true, /*force far call*/true); | |
| 2452 %} | |
| 2453 | |
| 2454 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL | |
| 2455 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine | |
| 2456 // who we intended to call. | |
| 2457 if ( !_method ) { | |
| 2458 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type); | |
| 2459 } else if (_optimized_virtual) { | |
| 2460 emit_call_reloc(cbuf, $meth$$method, relocInfo::opt_virtual_call_type); | |
| 2461 } else { | |
| 2462 emit_call_reloc(cbuf, $meth$$method, relocInfo::static_call_type); | |
| 2463 } | |
| 2464 if( _method ) { // Emit stub for static call | |
| 2465 emit_java_to_interp(cbuf); | |
| 2466 } | |
| 2467 %} | |
| 2468 | |
| 2469 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL | |
| 2470 MacroAssembler _masm(&cbuf); | |
| 2471 __ set_inst_mark(); | |
| 2472 int vtable_index = this->_vtable_index; | |
| 2473 // MachCallDynamicJavaNode::ret_addr_offset uses this same test | |
| 2474 if (vtable_index < 0) { | |
| 2475 // must be invalid_vtable_index, not nonvirtual_vtable_index | |
| 2476 assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value"); | |
| 2477 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); | |
| 2478 assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()"); | |
| 2479 assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub"); | |
| 2480 // !!!!! | |
| 2481 // Generate "set 0x01, R_G5", placeholder instruction to load oop-info | |
| 2482 // emit_call_dynamic_prologue( cbuf ); | |
| 2483 __ set_oop((jobject)Universe::non_oop_word(), G5_ic_reg); | |
| 2484 | |
| 2485 address virtual_call_oop_addr = __ inst_mark(); | |
| 2486 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine | |
| 2487 // who we intended to call. | |
| 2488 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr)); | |
| 2489 emit_call_reloc(cbuf, $meth$$method, relocInfo::none); | |
| 2490 } else { | |
| 2491 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); | |
| 2492 // Just go thru the vtable | |
| 2493 // get receiver klass (receiver already checked for non-null) | |
| 2494 // If we end up going thru a c2i adapter interpreter expects method in G5 | |
| 2495 int off = __ offset(); | |
|
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2496 __ load_klass(O0, G3_scratch); |
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2497 int klass_load_size; |
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2498 if (UseCompressedOops) { |
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2499 klass_load_size = 3*BytesPerInstWord; |
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2500 } else { |
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2501 klass_load_size = 1*BytesPerInstWord; |
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2502 } |
| 0 | 2503 int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size(); |
| 2504 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes(); | |
| 2505 if( __ is_simm13(v_off) ) { | |
| 2506 __ ld_ptr(G3, v_off, G5_method); | |
| 2507 } else { | |
| 2508 // Generate 2 instructions | |
| 2509 __ Assembler::sethi(v_off & ~0x3ff, G5_method); | |
| 2510 __ or3(G5_method, v_off & 0x3ff, G5_method); | |
| 2511 // ld_ptr, set_hi, set | |
|
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2512 assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord, |
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2513 "Unexpected instruction size(s)"); |
| 0 | 2514 __ ld_ptr(G3, G5_method, G5_method); |
| 2515 } | |
| 2516 // NOTE: for vtable dispatches, the vtable entry will never be null. | |
| 2517 // However it may very well end up in handle_wrong_method if the | |
| 2518 // method is abstract for the particular class. | |
| 2519 __ ld_ptr(G5_method, in_bytes(methodOopDesc::from_compiled_offset()), G3_scratch); | |
| 2520 // jump to target (either compiled code or c2iadapter) | |
| 2521 __ jmpl(G3_scratch, G0, O7); | |
| 2522 __ delayed()->nop(); | |
| 2523 } | |
| 2524 %} | |
| 2525 | |
| 2526 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL | |
| 2527 MacroAssembler _masm(&cbuf); | |
| 2528 | |
| 2529 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); | |
| 2530 Register temp_reg = G3; // caller must kill G3! We cannot reuse G5_ic_reg here because | |
| 2531 // we might be calling a C2I adapter which needs it. | |
| 2532 | |
| 2533 assert(temp_reg != G5_ic_reg, "conflicting registers"); | |
| 2534 // Load nmethod | |
| 2535 __ ld_ptr(G5_ic_reg, in_bytes(methodOopDesc::from_compiled_offset()), temp_reg); | |
| 2536 | |
| 2537 // CALL to compiled java, indirect the contents of G3 | |
| 2538 __ set_inst_mark(); | |
| 2539 __ callr(temp_reg, G0); | |
| 2540 __ delayed()->nop(); | |
| 2541 %} | |
| 2542 | |
| 2543 enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{ | |
| 2544 MacroAssembler _masm(&cbuf); | |
| 2545 Register Rdividend = reg_to_register_object($src1$$reg); | |
| 2546 Register Rdivisor = reg_to_register_object($src2$$reg); | |
| 2547 Register Rresult = reg_to_register_object($dst$$reg); | |
| 2548 | |
| 2549 __ sra(Rdivisor, 0, Rdivisor); | |
| 2550 __ sra(Rdividend, 0, Rdividend); | |
| 2551 __ sdivx(Rdividend, Rdivisor, Rresult); | |
| 2552 %} | |
| 2553 | |
| 2554 enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{ | |
| 2555 MacroAssembler _masm(&cbuf); | |
| 2556 | |
| 2557 Register Rdividend = reg_to_register_object($src1$$reg); | |
| 2558 int divisor = $imm$$constant; | |
| 2559 Register Rresult = reg_to_register_object($dst$$reg); | |
| 2560 | |
| 2561 __ sra(Rdividend, 0, Rdividend); | |
| 2562 __ sdivx(Rdividend, divisor, Rresult); | |
| 2563 %} | |
| 2564 | |
| 2565 enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{ | |
| 2566 MacroAssembler _masm(&cbuf); | |
| 2567 Register Rsrc1 = reg_to_register_object($src1$$reg); | |
| 2568 Register Rsrc2 = reg_to_register_object($src2$$reg); | |
| 2569 Register Rdst = reg_to_register_object($dst$$reg); | |
| 2570 | |
| 2571 __ sra( Rsrc1, 0, Rsrc1 ); | |
| 2572 __ sra( Rsrc2, 0, Rsrc2 ); | |
| 2573 __ mulx( Rsrc1, Rsrc2, Rdst ); | |
| 2574 __ srlx( Rdst, 32, Rdst ); | |
| 2575 %} | |
| 2576 | |
| 2577 enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{ | |
| 2578 MacroAssembler _masm(&cbuf); | |
| 2579 Register Rdividend = reg_to_register_object($src1$$reg); | |
| 2580 Register Rdivisor = reg_to_register_object($src2$$reg); | |
| 2581 Register Rresult = reg_to_register_object($dst$$reg); | |
| 2582 Register Rscratch = reg_to_register_object($scratch$$reg); | |
| 2583 | |
| 2584 assert(Rdividend != Rscratch, ""); | |
| 2585 assert(Rdivisor != Rscratch, ""); | |
| 2586 | |
| 2587 __ sra(Rdividend, 0, Rdividend); | |
| 2588 __ sra(Rdivisor, 0, Rdivisor); | |
| 2589 __ sdivx(Rdividend, Rdivisor, Rscratch); | |
| 2590 __ mulx(Rscratch, Rdivisor, Rscratch); | |
| 2591 __ sub(Rdividend, Rscratch, Rresult); | |
| 2592 %} | |
| 2593 | |
| 2594 enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{ | |
| 2595 MacroAssembler _masm(&cbuf); | |
| 2596 | |
| 2597 Register Rdividend = reg_to_register_object($src1$$reg); | |
| 2598 int divisor = $imm$$constant; | |
| 2599 Register Rresult = reg_to_register_object($dst$$reg); | |
| 2600 Register Rscratch = reg_to_register_object($scratch$$reg); | |
| 2601 | |
| 2602 assert(Rdividend != Rscratch, ""); | |
| 2603 | |
| 2604 __ sra(Rdividend, 0, Rdividend); | |
| 2605 __ sdivx(Rdividend, divisor, Rscratch); | |
| 2606 __ mulx(Rscratch, divisor, Rscratch); | |
| 2607 __ sub(Rdividend, Rscratch, Rresult); | |
| 2608 %} | |
| 2609 | |
| 2610 enc_class fabss (sflt_reg dst, sflt_reg src) %{ | |
| 2611 MacroAssembler _masm(&cbuf); | |
| 2612 | |
| 2613 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); | |
| 2614 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); | |
| 2615 | |
| 2616 __ fabs(FloatRegisterImpl::S, Fsrc, Fdst); | |
| 2617 %} | |
| 2618 | |
| 2619 enc_class fabsd (dflt_reg dst, dflt_reg src) %{ | |
| 2620 MacroAssembler _masm(&cbuf); | |
| 2621 | |
| 2622 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); | |
| 2623 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); | |
| 2624 | |
| 2625 __ fabs(FloatRegisterImpl::D, Fsrc, Fdst); | |
| 2626 %} | |
| 2627 | |
| 2628 enc_class fnegd (dflt_reg dst, dflt_reg src) %{ | |
| 2629 MacroAssembler _masm(&cbuf); | |
| 2630 | |
| 2631 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); | |
| 2632 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); | |
| 2633 | |
| 2634 __ fneg(FloatRegisterImpl::D, Fsrc, Fdst); | |
| 2635 %} | |
| 2636 | |
| 2637 enc_class fsqrts (sflt_reg dst, sflt_reg src) %{ | |
| 2638 MacroAssembler _masm(&cbuf); | |
| 2639 | |
| 2640 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); | |
| 2641 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); | |
| 2642 | |
| 2643 __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst); | |
| 2644 %} | |
| 2645 | |
| 2646 enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{ | |
| 2647 MacroAssembler _masm(&cbuf); | |
| 2648 | |
| 2649 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); | |
| 2650 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); | |
| 2651 | |
| 2652 __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst); | |
| 2653 %} | |
| 2654 | |
| 2655 enc_class fmovs (dflt_reg dst, dflt_reg src) %{ | |
| 2656 MacroAssembler _masm(&cbuf); | |
| 2657 | |
| 2658 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); | |
| 2659 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); | |
| 2660 | |
| 2661 __ fmov(FloatRegisterImpl::S, Fsrc, Fdst); | |
| 2662 %} | |
| 2663 | |
| 2664 enc_class fmovd (dflt_reg dst, dflt_reg src) %{ | |
| 2665 MacroAssembler _masm(&cbuf); | |
| 2666 | |
| 2667 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); | |
| 2668 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); | |
| 2669 | |
| 2670 __ fmov(FloatRegisterImpl::D, Fsrc, Fdst); | |
| 2671 %} | |
| 2672 | |
| 2673 enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{ | |
| 2674 MacroAssembler _masm(&cbuf); | |
| 2675 | |
| 2676 Register Roop = reg_to_register_object($oop$$reg); | |
| 2677 Register Rbox = reg_to_register_object($box$$reg); | |
| 2678 Register Rscratch = reg_to_register_object($scratch$$reg); | |
| 2679 Register Rmark = reg_to_register_object($scratch2$$reg); | |
| 2680 | |
| 2681 assert(Roop != Rscratch, ""); | |
| 2682 assert(Roop != Rmark, ""); | |
| 2683 assert(Rbox != Rscratch, ""); | |
| 2684 assert(Rbox != Rmark, ""); | |
| 2685 | |
| 2686 __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters); | |
| 2687 %} | |
| 2688 | |
| 2689 enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{ | |
| 2690 MacroAssembler _masm(&cbuf); | |
| 2691 | |
| 2692 Register Roop = reg_to_register_object($oop$$reg); | |
| 2693 Register Rbox = reg_to_register_object($box$$reg); | |
| 2694 Register Rscratch = reg_to_register_object($scratch$$reg); | |
| 2695 Register Rmark = reg_to_register_object($scratch2$$reg); | |
| 2696 | |
| 2697 assert(Roop != Rscratch, ""); | |
| 2698 assert(Roop != Rmark, ""); | |
| 2699 assert(Rbox != Rscratch, ""); | |
| 2700 assert(Rbox != Rmark, ""); | |
| 2701 | |
| 2702 __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch); | |
| 2703 %} | |
| 2704 | |
| 2705 enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{ | |
| 2706 MacroAssembler _masm(&cbuf); | |
| 2707 Register Rmem = reg_to_register_object($mem$$reg); | |
| 2708 Register Rold = reg_to_register_object($old$$reg); | |
| 2709 Register Rnew = reg_to_register_object($new$$reg); | |
| 2710 | |
| 2711 // casx_under_lock picks 1 of 3 encodings: | |
| 2712 // For 32-bit pointers you get a 32-bit CAS | |
| 2713 // For 64-bit pointers you get a 64-bit CASX | |
| 2714 __ casx_under_lock(Rmem, Rold, Rnew, // Swap(*Rmem,Rnew) if *Rmem == Rold | |
| 2715 (address) StubRoutines::Sparc::atomic_memory_operation_lock_addr()); | |
| 2716 __ cmp( Rold, Rnew ); | |
| 2717 %} | |
| 2718 | |
| 2719 enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{ | |
| 2720 Register Rmem = reg_to_register_object($mem$$reg); | |
| 2721 Register Rold = reg_to_register_object($old$$reg); | |
| 2722 Register Rnew = reg_to_register_object($new$$reg); | |
| 2723 | |
| 2724 MacroAssembler _masm(&cbuf); | |
| 2725 __ mov(Rnew, O7); | |
| 2726 __ casx(Rmem, Rold, O7); | |
| 2727 __ cmp( Rold, O7 ); | |
| 2728 %} | |
| 2729 | |
| 2730 // raw int cas, used for compareAndSwap | |
| 2731 enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{ | |
| 2732 Register Rmem = reg_to_register_object($mem$$reg); | |
| 2733 Register Rold = reg_to_register_object($old$$reg); | |
| 2734 Register Rnew = reg_to_register_object($new$$reg); | |
| 2735 | |
| 2736 MacroAssembler _masm(&cbuf); | |
| 2737 __ mov(Rnew, O7); | |
| 2738 __ cas(Rmem, Rold, O7); | |
| 2739 __ cmp( Rold, O7 ); | |
| 2740 %} | |
| 2741 | |
| 2742 enc_class enc_lflags_ne_to_boolean( iRegI res ) %{ | |
| 2743 Register Rres = reg_to_register_object($res$$reg); | |
| 2744 | |
| 2745 MacroAssembler _masm(&cbuf); | |
| 2746 __ mov(1, Rres); | |
| 2747 __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres ); | |
| 2748 %} | |
| 2749 | |
| 2750 enc_class enc_iflags_ne_to_boolean( iRegI res ) %{ | |
| 2751 Register Rres = reg_to_register_object($res$$reg); | |
| 2752 | |
| 2753 MacroAssembler _masm(&cbuf); | |
| 2754 __ mov(1, Rres); | |
| 2755 __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres ); | |
| 2756 %} | |
| 2757 | |
| 2758 enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{ | |
| 2759 MacroAssembler _masm(&cbuf); | |
| 2760 Register Rdst = reg_to_register_object($dst$$reg); | |
| 2761 FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg) | |
| 2762 : reg_to_DoubleFloatRegister_object($src1$$reg); | |
| 2763 FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg) | |
| 2764 : reg_to_DoubleFloatRegister_object($src2$$reg); | |
| 2765 | |
| 2766 // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1) | |
| 2767 __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst); | |
| 2768 %} | |
| 2769 | |
| 2770 enc_class LdImmL (immL src, iRegL dst, o7RegL tmp) %{ // Load Immediate | |
| 2771 MacroAssembler _masm(&cbuf); | |
| 2772 Register dest = reg_to_register_object($dst$$reg); | |
| 2773 Register temp = reg_to_register_object($tmp$$reg); | |
| 2774 __ set64( $src$$constant, dest, temp ); | |
| 2775 %} | |
| 2776 | |
| 2777 enc_class LdImmF(immF src, regF dst, o7RegP tmp) %{ // Load Immediate | |
| 2778 address float_address = MacroAssembler(&cbuf).float_constant($src$$constant); | |
| 2779 RelocationHolder rspec = internal_word_Relocation::spec(float_address); | |
| 2780 #ifdef _LP64 | |
| 2781 Register tmp_reg = reg_to_register_object($tmp$$reg); | |
| 2782 cbuf.relocate(cbuf.code_end(), rspec, 0); | |
| 2783 emit_ptr(cbuf, (intptr_t)float_address, tmp_reg, /*ForceRelocatable=*/ true); | |
| 2784 emit3_simm10( cbuf, Assembler::ldst_op, $dst$$reg, Assembler::ldf_op3, $tmp$$reg, 0 ); | |
| 2785 #else // _LP64 | |
| 2786 uint *code; | |
| 2787 int tmp_reg = $tmp$$reg; | |
| 2788 | |
| 2789 cbuf.relocate(cbuf.code_end(), rspec, 0); | |
| 2790 emit2_22( cbuf, Assembler::branch_op, tmp_reg, Assembler::sethi_op2, (intptr_t) float_address ); | |
| 2791 | |
| 2792 cbuf.relocate(cbuf.code_end(), rspec, 0); | |
| 2793 emit3_simm10( cbuf, Assembler::ldst_op, $dst$$reg, Assembler::ldf_op3, tmp_reg, (intptr_t) float_address ); | |
| 2794 #endif // _LP64 | |
| 2795 %} | |
| 2796 | |
| 2797 enc_class LdImmD(immD src, regD dst, o7RegP tmp) %{ // Load Immediate | |
| 2798 address double_address = MacroAssembler(&cbuf).double_constant($src$$constant); | |
| 2799 RelocationHolder rspec = internal_word_Relocation::spec(double_address); | |
| 2800 #ifdef _LP64 | |
| 2801 Register tmp_reg = reg_to_register_object($tmp$$reg); | |
| 2802 cbuf.relocate(cbuf.code_end(), rspec, 0); | |
| 2803 emit_ptr(cbuf, (intptr_t)double_address, tmp_reg, /*ForceRelocatable=*/ true); | |
| 2804 emit3_simm10( cbuf, Assembler::ldst_op, $dst$$reg, Assembler::lddf_op3, $tmp$$reg, 0 ); | |
| 2805 #else // _LP64 | |
| 2806 uint *code; | |
| 2807 int tmp_reg = $tmp$$reg; | |
| 2808 | |
| 2809 cbuf.relocate(cbuf.code_end(), rspec, 0); | |
| 2810 emit2_22( cbuf, Assembler::branch_op, tmp_reg, Assembler::sethi_op2, (intptr_t) double_address ); | |
| 2811 | |
| 2812 cbuf.relocate(cbuf.code_end(), rspec, 0); | |
| 2813 emit3_simm10( cbuf, Assembler::ldst_op, $dst$$reg, Assembler::lddf_op3, tmp_reg, (intptr_t) double_address ); | |
| 2814 #endif // _LP64 | |
| 2815 %} | |
| 2816 | |
| 2817 enc_class LdReplImmI(immI src, regD dst, o7RegP tmp, int count, int width) %{ | |
| 2818 // Load a constant replicated "count" times with width "width" | |
| 2819 int bit_width = $width$$constant * 8; | |
| 2820 jlong elt_val = $src$$constant; | |
| 2821 elt_val &= (((jlong)1) << bit_width) - 1; // mask off sign bits | |
| 2822 jlong val = elt_val; | |
| 2823 for (int i = 0; i < $count$$constant - 1; i++) { | |
| 2824 val <<= bit_width; | |
| 2825 val |= elt_val; | |
| 2826 } | |
| 2827 jdouble dval = *(jdouble*)&val; // coerce to double type | |
| 2828 address double_address = MacroAssembler(&cbuf).double_constant(dval); | |
| 2829 RelocationHolder rspec = internal_word_Relocation::spec(double_address); | |
| 2830 #ifdef _LP64 | |
| 2831 Register tmp_reg = reg_to_register_object($tmp$$reg); | |
| 2832 cbuf.relocate(cbuf.code_end(), rspec, 0); | |
| 2833 emit_ptr(cbuf, (intptr_t)double_address, tmp_reg, /*ForceRelocatable=*/ true); | |
| 2834 emit3_simm10( cbuf, Assembler::ldst_op, $dst$$reg, Assembler::lddf_op3, $tmp$$reg, 0 ); | |
| 2835 #else // _LP64 | |
| 2836 uint *code; | |
| 2837 int tmp_reg = $tmp$$reg; | |
| 2838 | |
| 2839 cbuf.relocate(cbuf.code_end(), rspec, 0); | |
| 2840 emit2_22( cbuf, Assembler::branch_op, tmp_reg, Assembler::sethi_op2, (intptr_t) double_address ); | |
| 2841 | |
| 2842 cbuf.relocate(cbuf.code_end(), rspec, 0); | |
| 2843 emit3_simm10( cbuf, Assembler::ldst_op, $dst$$reg, Assembler::lddf_op3, tmp_reg, (intptr_t) double_address ); | |
| 2844 #endif // _LP64 | |
| 2845 %} | |
| 2846 | |
| 2847 | |
| 2848 enc_class ShouldNotEncodeThis ( ) %{ | |
| 2849 ShouldNotCallThis(); | |
| 2850 %} | |
| 2851 | |
| 2852 // Compiler ensures base is doubleword aligned and cnt is count of doublewords | |
| 2853 enc_class enc_Clear_Array(iRegX cnt, iRegP base, iRegX temp) %{ | |
| 2854 MacroAssembler _masm(&cbuf); | |
| 2855 Register nof_bytes_arg = reg_to_register_object($cnt$$reg); | |
| 2856 Register nof_bytes_tmp = reg_to_register_object($temp$$reg); | |
| 2857 Register base_pointer_arg = reg_to_register_object($base$$reg); | |
| 2858 | |
| 2859 Label loop; | |
| 2860 __ mov(nof_bytes_arg, nof_bytes_tmp); | |
| 2861 | |
| 2862 // Loop and clear, walking backwards through the array. | |
| 2863 // nof_bytes_tmp (if >0) is always the number of bytes to zero | |
| 2864 __ bind(loop); | |
| 2865 __ deccc(nof_bytes_tmp, 8); | |
| 2866 __ br(Assembler::greaterEqual, true, Assembler::pt, loop); | |
| 2867 __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp); | |
| 2868 // %%%% this mini-loop must not cross a cache boundary! | |
| 2869 %} | |
| 2870 | |
| 2871 | |
| 2872 enc_class enc_String_Compare(o0RegP str1, o1RegP str2, g3RegP tmp1, g4RegP tmp2, notemp_iRegI result) %{ | |
| 2873 Label Ldone, Lloop; | |
| 2874 MacroAssembler _masm(&cbuf); | |
| 2875 | |
| 2876 Register str1_reg = reg_to_register_object($str1$$reg); | |
| 2877 Register str2_reg = reg_to_register_object($str2$$reg); | |
| 2878 Register tmp1_reg = reg_to_register_object($tmp1$$reg); | |
| 2879 Register tmp2_reg = reg_to_register_object($tmp2$$reg); | |
| 2880 Register result_reg = reg_to_register_object($result$$reg); | |
| 2881 | |
| 2882 // Get the first character position in both strings | |
| 2883 // [8] char array, [12] offset, [16] count | |
| 2884 int value_offset = java_lang_String:: value_offset_in_bytes(); | |
| 2885 int offset_offset = java_lang_String::offset_offset_in_bytes(); | |
| 2886 int count_offset = java_lang_String:: count_offset_in_bytes(); | |
| 2887 | |
| 2888 // load str1 (jchar*) base address into tmp1_reg | |
|
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|
2889 __ load_heap_oop(Address(str1_reg, 0, value_offset), tmp1_reg); |
| 0 | 2890 __ ld(Address(str1_reg, 0, offset_offset), result_reg); |
| 2891 __ add(tmp1_reg, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp1_reg); | |
| 2892 __ ld(Address(str1_reg, 0, count_offset), str1_reg); // hoisted | |
| 2893 __ sll(result_reg, exact_log2(sizeof(jchar)), result_reg); | |
|
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|
2894 __ load_heap_oop(Address(str2_reg, 0, value_offset), tmp2_reg); // hoisted |
| 0 | 2895 __ add(result_reg, tmp1_reg, tmp1_reg); |
| 2896 | |
| 2897 // load str2 (jchar*) base address into tmp2_reg | |
| 2898 // __ ld_ptr(Address(str2_reg, 0, value_offset), tmp2_reg); // hoisted | |
| 2899 __ ld(Address(str2_reg, 0, offset_offset), result_reg); | |
| 2900 __ add(tmp2_reg, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp2_reg); | |
| 2901 __ ld(Address(str2_reg, 0, count_offset), str2_reg); // hoisted | |
| 2902 __ sll(result_reg, exact_log2(sizeof(jchar)), result_reg); | |
| 2903 __ subcc(str1_reg, str2_reg, O7); // hoisted | |
| 2904 __ add(result_reg, tmp2_reg, tmp2_reg); | |
| 2905 | |
| 2906 // Compute the minimum of the string lengths(str1_reg) and the | |
| 2907 // difference of the string lengths (stack) | |
| 2908 | |
| 2909 // discard string base pointers, after loading up the lengths | |
| 2910 // __ ld(Address(str1_reg, 0, count_offset), str1_reg); // hoisted | |
| 2911 // __ ld(Address(str2_reg, 0, count_offset), str2_reg); // hoisted | |
| 2912 | |
| 2913 // See if the lengths are different, and calculate min in str1_reg. | |
| 2914 // Stash diff in O7 in case we need it for a tie-breaker. | |
| 2915 Label Lskip; | |
| 2916 // __ subcc(str1_reg, str2_reg, O7); // hoisted | |
| 2917 __ sll(str1_reg, exact_log2(sizeof(jchar)), str1_reg); // scale the limit | |
| 2918 __ br(Assembler::greater, true, Assembler::pt, Lskip); | |
| 2919 // str2 is shorter, so use its count: | |
| 2920 __ delayed()->sll(str2_reg, exact_log2(sizeof(jchar)), str1_reg); // scale the limit | |
| 2921 __ bind(Lskip); | |
| 2922 | |
| 2923 // reallocate str1_reg, str2_reg, result_reg | |
| 2924 // Note: limit_reg holds the string length pre-scaled by 2 | |
| 2925 Register limit_reg = str1_reg; | |
| 2926 Register chr2_reg = str2_reg; | |
| 2927 Register chr1_reg = result_reg; | |
| 2928 // tmp{12} are the base pointers | |
| 2929 | |
| 2930 // Is the minimum length zero? | |
| 2931 __ cmp(limit_reg, (int)(0 * sizeof(jchar))); // use cast to resolve overloading ambiguity | |
| 2932 __ br(Assembler::equal, true, Assembler::pn, Ldone); | |
| 2933 __ delayed()->mov(O7, result_reg); // result is difference in lengths | |
| 2934 | |
| 2935 // Load first characters | |
| 2936 __ lduh(tmp1_reg, 0, chr1_reg); | |
| 2937 __ lduh(tmp2_reg, 0, chr2_reg); | |
| 2938 | |
| 2939 // Compare first characters | |
| 2940 __ subcc(chr1_reg, chr2_reg, chr1_reg); | |
| 2941 __ br(Assembler::notZero, false, Assembler::pt, Ldone); | |
| 2942 assert(chr1_reg == result_reg, "result must be pre-placed"); | |
| 2943 __ delayed()->nop(); | |
| 2944 | |
| 2945 { | |
| 2946 // Check after comparing first character to see if strings are equivalent | |
| 2947 Label LSkip2; | |
| 2948 // Check if the strings start at same location | |
| 2949 __ cmp(tmp1_reg, tmp2_reg); | |
| 2950 __ brx(Assembler::notEqual, true, Assembler::pt, LSkip2); | |
| 2951 __ delayed()->nop(); | |
| 2952 | |
| 2953 // Check if the length difference is zero (in O7) | |
| 2954 __ cmp(G0, O7); | |
| 2955 __ br(Assembler::equal, true, Assembler::pn, Ldone); | |
| 2956 __ delayed()->mov(G0, result_reg); // result is zero | |
| 2957 | |
| 2958 // Strings might not be equal | |
| 2959 __ bind(LSkip2); | |
| 2960 } | |
| 2961 | |
| 2962 __ subcc(limit_reg, 1 * sizeof(jchar), chr1_reg); | |
| 2963 __ br(Assembler::equal, true, Assembler::pn, Ldone); | |
| 2964 __ delayed()->mov(O7, result_reg); // result is difference in lengths | |
| 2965 | |
| 2966 // Shift tmp1_reg and tmp2_reg to the end of the arrays, negate limit | |
| 2967 __ add(tmp1_reg, limit_reg, tmp1_reg); | |
| 2968 __ add(tmp2_reg, limit_reg, tmp2_reg); | |
| 2969 __ neg(chr1_reg, limit_reg); // limit = -(limit-2) | |
| 2970 | |
| 2971 // Compare the rest of the characters | |
| 2972 __ lduh(tmp1_reg, limit_reg, chr1_reg); | |
| 2973 __ bind(Lloop); | |
| 2974 // __ lduh(tmp1_reg, limit_reg, chr1_reg); // hoisted | |
| 2975 __ lduh(tmp2_reg, limit_reg, chr2_reg); | |
| 2976 __ subcc(chr1_reg, chr2_reg, chr1_reg); | |
| 2977 __ br(Assembler::notZero, false, Assembler::pt, Ldone); | |
| 2978 assert(chr1_reg == result_reg, "result must be pre-placed"); | |
| 2979 __ delayed()->inccc(limit_reg, sizeof(jchar)); | |
| 2980 // annul LDUH if branch is not taken to prevent access past end of string | |
| 2981 __ br(Assembler::notZero, true, Assembler::pt, Lloop); | |
| 2982 __ delayed()->lduh(tmp1_reg, limit_reg, chr1_reg); // hoisted | |
| 2983 | |
| 2984 // If strings are equal up to min length, return the length difference. | |
| 2985 __ mov(O7, result_reg); | |
| 2986 | |
| 2987 // Otherwise, return the difference between the first mismatched chars. | |
| 2988 __ bind(Ldone); | |
| 2989 %} | |
| 2990 | |
| 2991 enc_class enc_rethrow() %{ | |
| 2992 cbuf.set_inst_mark(); | |
| 2993 Register temp_reg = G3; | |
| 2994 Address rethrow_stub(temp_reg, OptoRuntime::rethrow_stub()); | |
| 2995 assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg"); | |
| 2996 MacroAssembler _masm(&cbuf); | |
| 2997 #ifdef ASSERT | |
| 2998 __ save_frame(0); | |
| 2999 Address last_rethrow_addr(L1, (address)&last_rethrow); | |
| 3000 __ sethi(last_rethrow_addr); | |
| 3001 __ get_pc(L2); | |
| 3002 __ inc(L2, 3 * BytesPerInstWord); // skip this & 2 more insns to point at jump_to | |
| 3003 __ st_ptr(L2, last_rethrow_addr); | |
| 3004 __ restore(); | |
| 3005 #endif | |
| 3006 __ JUMP(rethrow_stub, 0); // sethi;jmp | |
| 3007 __ delayed()->nop(); | |
| 3008 %} | |
| 3009 | |
| 3010 enc_class emit_mem_nop() %{ | |
| 3011 // Generates the instruction LDUXA [o6,g0],#0x82,g0 | |
| 3012 unsigned int *code = (unsigned int*)cbuf.code_end(); | |
| 3013 *code = (unsigned int)0xc0839040; | |
| 3014 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
| 3015 %} | |
| 3016 | |
| 3017 enc_class emit_fadd_nop() %{ | |
| 3018 // Generates the instruction FMOVS f31,f31 | |
| 3019 unsigned int *code = (unsigned int*)cbuf.code_end(); | |
| 3020 *code = (unsigned int)0xbfa0003f; | |
| 3021 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
| 3022 %} | |
| 3023 | |
| 3024 enc_class emit_br_nop() %{ | |
| 3025 // Generates the instruction BPN,PN . | |
| 3026 unsigned int *code = (unsigned int*)cbuf.code_end(); | |
| 3027 *code = (unsigned int)0x00400000; | |
| 3028 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
| 3029 %} | |
| 3030 | |
| 3031 enc_class enc_membar_acquire %{ | |
| 3032 MacroAssembler _masm(&cbuf); | |
| 3033 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) ); | |
| 3034 %} | |
| 3035 | |
| 3036 enc_class enc_membar_release %{ | |
| 3037 MacroAssembler _masm(&cbuf); | |
| 3038 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) ); | |
| 3039 %} | |
| 3040 | |
| 3041 enc_class enc_membar_volatile %{ | |
| 3042 MacroAssembler _masm(&cbuf); | |
| 3043 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) ); | |
| 3044 %} | |
|
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3045 |
| 0 | 3046 enc_class enc_repl8b( iRegI src, iRegL dst ) %{ |
| 3047 MacroAssembler _masm(&cbuf); | |
| 3048 Register src_reg = reg_to_register_object($src$$reg); | |
| 3049 Register dst_reg = reg_to_register_object($dst$$reg); | |
| 3050 __ sllx(src_reg, 56, dst_reg); | |
| 3051 __ srlx(dst_reg, 8, O7); | |
| 3052 __ or3 (dst_reg, O7, dst_reg); | |
| 3053 __ srlx(dst_reg, 16, O7); | |
| 3054 __ or3 (dst_reg, O7, dst_reg); | |
| 3055 __ srlx(dst_reg, 32, O7); | |
| 3056 __ or3 (dst_reg, O7, dst_reg); | |
| 3057 %} | |
| 3058 | |
| 3059 enc_class enc_repl4b( iRegI src, iRegL dst ) %{ | |
| 3060 MacroAssembler _masm(&cbuf); | |
| 3061 Register src_reg = reg_to_register_object($src$$reg); | |
| 3062 Register dst_reg = reg_to_register_object($dst$$reg); | |
| 3063 __ sll(src_reg, 24, dst_reg); | |
| 3064 __ srl(dst_reg, 8, O7); | |
| 3065 __ or3(dst_reg, O7, dst_reg); | |
| 3066 __ srl(dst_reg, 16, O7); | |
| 3067 __ or3(dst_reg, O7, dst_reg); | |
| 3068 %} | |
| 3069 | |
| 3070 enc_class enc_repl4s( iRegI src, iRegL dst ) %{ | |
| 3071 MacroAssembler _masm(&cbuf); | |
| 3072 Register src_reg = reg_to_register_object($src$$reg); | |
| 3073 Register dst_reg = reg_to_register_object($dst$$reg); | |
| 3074 __ sllx(src_reg, 48, dst_reg); | |
| 3075 __ srlx(dst_reg, 16, O7); | |
| 3076 __ or3 (dst_reg, O7, dst_reg); | |
| 3077 __ srlx(dst_reg, 32, O7); | |
| 3078 __ or3 (dst_reg, O7, dst_reg); | |
| 3079 %} | |
| 3080 | |
| 3081 enc_class enc_repl2i( iRegI src, iRegL dst ) %{ | |
| 3082 MacroAssembler _masm(&cbuf); | |
| 3083 Register src_reg = reg_to_register_object($src$$reg); | |
| 3084 Register dst_reg = reg_to_register_object($dst$$reg); | |
| 3085 __ sllx(src_reg, 32, dst_reg); | |
| 3086 __ srlx(dst_reg, 32, O7); | |
| 3087 __ or3 (dst_reg, O7, dst_reg); | |
| 3088 %} | |
| 3089 | |
| 3090 %} | |
| 3091 | |
| 3092 //----------FRAME-------------------------------------------------------------- | |
| 3093 // Definition of frame structure and management information. | |
| 3094 // | |
| 3095 // S T A C K L A Y O U T Allocators stack-slot number | |
| 3096 // | (to get allocators register number | |
| 3097 // G Owned by | | v add VMRegImpl::stack0) | |
| 3098 // r CALLER | | | |
| 3099 // o | +--------+ pad to even-align allocators stack-slot | |
| 3100 // w V | pad0 | numbers; owned by CALLER | |
| 3101 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned | |
| 3102 // h ^ | in | 5 | |
| 3103 // | | args | 4 Holes in incoming args owned by SELF | |
| 3104 // | | | | 3 | |
| 3105 // | | +--------+ | |
| 3106 // V | | old out| Empty on Intel, window on Sparc | |
| 3107 // | old |preserve| Must be even aligned. | |
| 3108 // | SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned | |
| 3109 // | | in | 3 area for Intel ret address | |
| 3110 // Owned by |preserve| Empty on Sparc. | |
| 3111 // SELF +--------+ | |
| 3112 // | | pad2 | 2 pad to align old SP | |
| 3113 // | +--------+ 1 | |
| 3114 // | | locks | 0 | |
| 3115 // | +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned | |
| 3116 // | | pad1 | 11 pad to align new SP | |
| 3117 // | +--------+ | |
| 3118 // | | | 10 | |
| 3119 // | | spills | 9 spills | |
| 3120 // V | | 8 (pad0 slot for callee) | |
| 3121 // -----------+--------+----> Matcher::_out_arg_limit, unaligned | |
| 3122 // ^ | out | 7 | |
| 3123 // | | args | 6 Holes in outgoing args owned by CALLEE | |
| 3124 // Owned by +--------+ | |
| 3125 // CALLEE | new out| 6 Empty on Intel, window on Sparc | |
| 3126 // | new |preserve| Must be even-aligned. | |
| 3127 // | SP-+--------+----> Matcher::_new_SP, even aligned | |
| 3128 // | | | | |
| 3129 // | |
| 3130 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is | |
| 3131 // known from SELF's arguments and the Java calling convention. | |
| 3132 // Region 6-7 is determined per call site. | |
| 3133 // Note 2: If the calling convention leaves holes in the incoming argument | |
| 3134 // area, those holes are owned by SELF. Holes in the outgoing area | |
| 3135 // are owned by the CALLEE. Holes should not be nessecary in the | |
| 3136 // incoming area, as the Java calling convention is completely under | |
| 3137 // the control of the AD file. Doubles can be sorted and packed to | |
| 3138 // avoid holes. Holes in the outgoing arguments may be nessecary for | |
| 3139 // varargs C calling conventions. | |
| 3140 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is | |
| 3141 // even aligned with pad0 as needed. | |
| 3142 // Region 6 is even aligned. Region 6-7 is NOT even aligned; | |
| 3143 // region 6-11 is even aligned; it may be padded out more so that | |
| 3144 // the region from SP to FP meets the minimum stack alignment. | |
| 3145 | |
| 3146 frame %{ | |
| 3147 // What direction does stack grow in (assumed to be same for native & Java) | |
| 3148 stack_direction(TOWARDS_LOW); | |
| 3149 | |
| 3150 // These two registers define part of the calling convention | |
| 3151 // between compiled code and the interpreter. | |
| 3152 inline_cache_reg(R_G5); // Inline Cache Register or methodOop for I2C | |
| 3153 interpreter_method_oop_reg(R_G5); // Method Oop Register when calling interpreter | |
| 3154 | |
| 3155 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset] | |
| 3156 cisc_spilling_operand_name(indOffset); | |
| 3157 | |
| 3158 // Number of stack slots consumed by a Monitor enter | |
| 3159 #ifdef _LP64 | |
| 3160 sync_stack_slots(2); | |
| 3161 #else | |
| 3162 sync_stack_slots(1); | |
| 3163 #endif | |
| 3164 | |
| 3165 // Compiled code's Frame Pointer | |
| 3166 frame_pointer(R_SP); | |
| 3167 | |
| 3168 // Stack alignment requirement | |
| 3169 stack_alignment(StackAlignmentInBytes); | |
| 3170 // LP64: Alignment size in bytes (128-bit -> 16 bytes) | |
| 3171 // !LP64: Alignment size in bytes (64-bit -> 8 bytes) | |
| 3172 | |
| 3173 // Number of stack slots between incoming argument block and the start of | |
| 3174 // a new frame. The PROLOG must add this many slots to the stack. The | |
| 3175 // EPILOG must remove this many slots. | |
| 3176 in_preserve_stack_slots(0); | |
| 3177 | |
| 3178 // Number of outgoing stack slots killed above the out_preserve_stack_slots | |
| 3179 // for calls to C. Supports the var-args backing area for register parms. | |
| 3180 // ADLC doesn't support parsing expressions, so I folded the math by hand. | |
| 3181 #ifdef _LP64 | |
| 3182 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word | |
| 3183 varargs_C_out_slots_killed(12); | |
| 3184 #else | |
| 3185 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (1)) * 1-stack-slots-per-word | |
| 3186 varargs_C_out_slots_killed( 7); | |
| 3187 #endif | |
| 3188 | |
| 3189 // The after-PROLOG location of the return address. Location of | |
| 3190 // return address specifies a type (REG or STACK) and a number | |
| 3191 // representing the register number (i.e. - use a register name) or | |
| 3192 // stack slot. | |
| 3193 return_addr(REG R_I7); // Ret Addr is in register I7 | |
| 3194 | |
| 3195 // Body of function which returns an OptoRegs array locating | |
| 3196 // arguments either in registers or in stack slots for calling | |
| 3197 // java | |
| 3198 calling_convention %{ | |
| 3199 (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing); | |
| 3200 | |
| 3201 %} | |
| 3202 | |
| 3203 // Body of function which returns an OptoRegs array locating | |
| 3204 // arguments either in registers or in stack slots for callin | |
| 3205 // C. | |
| 3206 c_calling_convention %{ | |
| 3207 // This is obviously always outgoing | |
| 3208 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length); | |
| 3209 %} | |
| 3210 | |
| 3211 // Location of native (C/C++) and interpreter return values. This is specified to | |
| 3212 // be the same as Java. In the 32-bit VM, long values are actually returned from | |
| 3213 // native calls in O0:O1 and returned to the interpreter in I0:I1. The copying | |
| 3214 // to and from the register pairs is done by the appropriate call and epilog | |
| 3215 // opcodes. This simplifies the register allocator. | |
| 3216 c_return_value %{ | |
| 3217 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); | |
| 3218 #ifdef _LP64 | |
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3219 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num }; |
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3220 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num}; |
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3221 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num }; |
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3222 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num}; |
| 0 | 3223 #else // !_LP64 |
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3224 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num }; |
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3225 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num }; |
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3226 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num }; |
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3227 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num }; |
| 0 | 3228 #endif |
| 3229 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg], | |
| 3230 (is_outgoing?lo_out:lo_in)[ideal_reg] ); | |
| 3231 %} | |
| 3232 | |
| 3233 // Location of compiled Java return values. Same as C | |
| 3234 return_value %{ | |
| 3235 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); | |
| 3236 #ifdef _LP64 | |
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3237 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num }; |
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3238 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num}; |
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3239 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num }; |
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3240 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num}; |
| 0 | 3241 #else // !_LP64 |
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3242 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num }; |
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3243 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num}; |
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3244 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num }; |
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3245 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num}; |
| 0 | 3246 #endif |
| 3247 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg], | |
| 3248 (is_outgoing?lo_out:lo_in)[ideal_reg] ); | |
| 3249 %} | |
| 3250 | |
| 3251 %} | |
| 3252 | |
| 3253 | |
| 3254 //----------ATTRIBUTES--------------------------------------------------------- | |
| 3255 //----------Operand Attributes------------------------------------------------- | |
| 3256 op_attrib op_cost(1); // Required cost attribute | |
| 3257 | |
| 3258 //----------Instruction Attributes--------------------------------------------- | |
| 3259 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute | |
| 3260 ins_attrib ins_size(32); // Required size attribute (in bits) | |
| 3261 ins_attrib ins_pc_relative(0); // Required PC Relative flag | |
| 3262 ins_attrib ins_short_branch(0); // Required flag: is this instruction a | |
| 3263 // non-matching short branch variant of some | |
| 3264 // long branch? | |
| 3265 | |
| 3266 //----------OPERANDS----------------------------------------------------------- | |
| 3267 // Operand definitions must precede instruction definitions for correct parsing | |
| 3268 // in the ADLC because operands constitute user defined types which are used in | |
| 3269 // instruction definitions. | |
| 3270 | |
| 3271 //----------Simple Operands---------------------------------------------------- | |
| 3272 // Immediate Operands | |
| 3273 // Integer Immediate: 32-bit | |
| 3274 operand immI() %{ | |
| 3275 match(ConI); | |
| 3276 | |
| 3277 op_cost(0); | |
| 3278 // formats are generated automatically for constants and base registers | |
| 3279 format %{ %} | |
| 3280 interface(CONST_INTER); | |
| 3281 %} | |
| 3282 | |
| 3283 // Integer Immediate: 13-bit | |
| 3284 operand immI13() %{ | |
| 3285 predicate(Assembler::is_simm13(n->get_int())); | |
| 3286 match(ConI); | |
| 3287 op_cost(0); | |
| 3288 | |
| 3289 format %{ %} | |
| 3290 interface(CONST_INTER); | |
| 3291 %} | |
| 3292 | |
| 3293 // Unsigned (positive) Integer Immediate: 13-bit | |
| 3294 operand immU13() %{ | |
| 3295 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int())); | |
| 3296 match(ConI); | |
| 3297 op_cost(0); | |
| 3298 | |
| 3299 format %{ %} | |
| 3300 interface(CONST_INTER); | |
| 3301 %} | |
| 3302 | |
| 3303 // Integer Immediate: 6-bit | |
| 3304 operand immU6() %{ | |
| 3305 predicate(n->get_int() >= 0 && n->get_int() <= 63); | |
| 3306 match(ConI); | |
| 3307 op_cost(0); | |
| 3308 format %{ %} | |
| 3309 interface(CONST_INTER); | |
| 3310 %} | |
| 3311 | |
| 3312 // Integer Immediate: 11-bit | |
| 3313 operand immI11() %{ | |
| 3314 predicate(Assembler::is_simm(n->get_int(),11)); | |
| 3315 match(ConI); | |
| 3316 op_cost(0); | |
| 3317 format %{ %} | |
| 3318 interface(CONST_INTER); | |
| 3319 %} | |
| 3320 | |
| 3321 // Integer Immediate: 0-bit | |
| 3322 operand immI0() %{ | |
| 3323 predicate(n->get_int() == 0); | |
| 3324 match(ConI); | |
| 3325 op_cost(0); | |
| 3326 | |
| 3327 format %{ %} | |
| 3328 interface(CONST_INTER); | |
| 3329 %} | |
| 3330 | |
| 3331 // Integer Immediate: the value 10 | |
| 3332 operand immI10() %{ | |
| 3333 predicate(n->get_int() == 10); | |
| 3334 match(ConI); | |
| 3335 op_cost(0); | |
| 3336 | |
| 3337 format %{ %} | |
| 3338 interface(CONST_INTER); | |
| 3339 %} | |
| 3340 | |
| 3341 // Integer Immediate: the values 0-31 | |
| 3342 operand immU5() %{ | |
| 3343 predicate(n->get_int() >= 0 && n->get_int() <= 31); | |
| 3344 match(ConI); | |
| 3345 op_cost(0); | |
| 3346 | |
| 3347 format %{ %} | |
| 3348 interface(CONST_INTER); | |
| 3349 %} | |
| 3350 | |
| 3351 // Integer Immediate: the values 1-31 | |
| 3352 operand immI_1_31() %{ | |
| 3353 predicate(n->get_int() >= 1 && n->get_int() <= 31); | |
| 3354 match(ConI); | |
| 3355 op_cost(0); | |
| 3356 | |
| 3357 format %{ %} | |
| 3358 interface(CONST_INTER); | |
| 3359 %} | |
| 3360 | |
| 3361 // Integer Immediate: the values 32-63 | |
| 3362 operand immI_32_63() %{ | |
| 3363 predicate(n->get_int() >= 32 && n->get_int() <= 63); | |
| 3364 match(ConI); | |
| 3365 op_cost(0); | |
| 3366 | |
| 3367 format %{ %} | |
| 3368 interface(CONST_INTER); | |
| 3369 %} | |
| 3370 | |
| 3371 // Integer Immediate: the value 255 | |
| 3372 operand immI_255() %{ | |
| 3373 predicate( n->get_int() == 255 ); | |
| 3374 match(ConI); | |
| 3375 op_cost(0); | |
| 3376 | |
| 3377 format %{ %} | |
| 3378 interface(CONST_INTER); | |
| 3379 %} | |
| 3380 | |
| 3381 // Long Immediate: the value FF | |
| 3382 operand immL_FF() %{ | |
| 3383 predicate( n->get_long() == 0xFFL ); | |
| 3384 match(ConL); | |
| 3385 op_cost(0); | |
| 3386 | |
| 3387 format %{ %} | |
| 3388 interface(CONST_INTER); | |
| 3389 %} | |
| 3390 | |
| 3391 // Long Immediate: the value FFFF | |
| 3392 operand immL_FFFF() %{ | |
| 3393 predicate( n->get_long() == 0xFFFFL ); | |
| 3394 match(ConL); | |
| 3395 op_cost(0); | |
| 3396 | |
| 3397 format %{ %} | |
| 3398 interface(CONST_INTER); | |
| 3399 %} | |
| 3400 | |
| 3401 // Pointer Immediate: 32 or 64-bit | |
| 3402 operand immP() %{ | |
| 3403 match(ConP); | |
| 3404 | |
| 3405 op_cost(5); | |
| 3406 // formats are generated automatically for constants and base registers | |
| 3407 format %{ %} | |
| 3408 interface(CONST_INTER); | |
| 3409 %} | |
| 3410 | |
| 3411 operand immP13() %{ | |
| 3412 predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095)); | |
| 3413 match(ConP); | |
| 3414 op_cost(0); | |
| 3415 | |
| 3416 format %{ %} | |
| 3417 interface(CONST_INTER); | |
| 3418 %} | |
| 3419 | |
| 3420 operand immP0() %{ | |
| 3421 predicate(n->get_ptr() == 0); | |
| 3422 match(ConP); | |
| 3423 op_cost(0); | |
| 3424 | |
| 3425 format %{ %} | |
| 3426 interface(CONST_INTER); | |
| 3427 %} | |
| 3428 | |
| 3429 operand immP_poll() %{ | |
| 3430 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page()); | |
| 3431 match(ConP); | |
| 3432 | |
| 3433 // formats are generated automatically for constants and base registers | |
| 3434 format %{ %} | |
| 3435 interface(CONST_INTER); | |
| 3436 %} | |
| 3437 | |
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3438 // Pointer Immediate |
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3439 operand immN() |
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3440 %{ |
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3441 match(ConN); |
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3442 |
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3443 op_cost(10); |
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3444 format %{ %} |
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3445 interface(CONST_INTER); |
|
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3446 %} |
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3447 |
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3448 // NULL Pointer Immediate |
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3449 operand immN0() |
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3450 %{ |
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3451 predicate(n->get_narrowcon() == 0); |
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3452 match(ConN); |
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3453 |
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3454 op_cost(0); |
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3455 format %{ %} |
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3456 interface(CONST_INTER); |
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3457 %} |
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3458 |
| 0 | 3459 operand immL() %{ |
| 3460 match(ConL); | |
| 3461 op_cost(40); | |
| 3462 // formats are generated automatically for constants and base registers | |
| 3463 format %{ %} | |
| 3464 interface(CONST_INTER); | |
| 3465 %} | |
| 3466 | |
| 3467 operand immL0() %{ | |
| 3468 predicate(n->get_long() == 0L); | |
| 3469 match(ConL); | |
| 3470 op_cost(0); | |
| 3471 // formats are generated automatically for constants and base registers | |
| 3472 format %{ %} | |
| 3473 interface(CONST_INTER); | |
| 3474 %} | |
| 3475 | |
| 3476 // Long Immediate: 13-bit | |
| 3477 operand immL13() %{ | |
| 3478 predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L)); | |
| 3479 match(ConL); | |
| 3480 op_cost(0); | |
| 3481 | |
| 3482 format %{ %} | |
| 3483 interface(CONST_INTER); | |
| 3484 %} | |
| 3485 | |
| 3486 // Long Immediate: low 32-bit mask | |
| 3487 operand immL_32bits() %{ | |
| 3488 predicate(n->get_long() == 0xFFFFFFFFL); | |
| 3489 match(ConL); | |
| 3490 op_cost(0); | |
| 3491 | |
| 3492 format %{ %} | |
| 3493 interface(CONST_INTER); | |
| 3494 %} | |
| 3495 | |
| 3496 // Double Immediate | |
| 3497 operand immD() %{ | |
| 3498 match(ConD); | |
| 3499 | |
| 3500 op_cost(40); | |
| 3501 format %{ %} | |
| 3502 interface(CONST_INTER); | |
| 3503 %} | |
| 3504 | |
| 3505 operand immD0() %{ | |
| 3506 #ifdef _LP64 | |
| 3507 // on 64-bit architectures this comparision is faster | |
| 3508 predicate(jlong_cast(n->getd()) == 0); | |
| 3509 #else | |
| 3510 predicate((n->getd() == 0) && (fpclass(n->getd()) == FP_PZERO)); | |
| 3511 #endif | |
| 3512 match(ConD); | |
| 3513 | |
| 3514 op_cost(0); | |
| 3515 format %{ %} | |
| 3516 interface(CONST_INTER); | |
| 3517 %} | |
| 3518 | |
| 3519 // Float Immediate | |
| 3520 operand immF() %{ | |
| 3521 match(ConF); | |
| 3522 | |
| 3523 op_cost(20); | |
| 3524 format %{ %} | |
| 3525 interface(CONST_INTER); | |
| 3526 %} | |
| 3527 | |
| 3528 // Float Immediate: 0 | |
| 3529 operand immF0() %{ | |
| 3530 predicate((n->getf() == 0) && (fpclass(n->getf()) == FP_PZERO)); | |
| 3531 match(ConF); | |
| 3532 | |
| 3533 op_cost(0); | |
| 3534 format %{ %} | |
| 3535 interface(CONST_INTER); | |
| 3536 %} | |
| 3537 | |
| 3538 // Integer Register Operands | |
| 3539 // Integer Register | |
| 3540 operand iRegI() %{ | |
| 3541 constraint(ALLOC_IN_RC(int_reg)); | |
| 3542 match(RegI); | |
| 3543 | |
| 3544 match(notemp_iRegI); | |
| 3545 match(g1RegI); | |
| 3546 match(o0RegI); | |
| 3547 match(iRegIsafe); | |
| 3548 | |
| 3549 format %{ %} | |
| 3550 interface(REG_INTER); | |
| 3551 %} | |
| 3552 | |
| 3553 operand notemp_iRegI() %{ | |
| 3554 constraint(ALLOC_IN_RC(notemp_int_reg)); | |
| 3555 match(RegI); | |
| 3556 | |
| 3557 match(o0RegI); | |
| 3558 | |
| 3559 format %{ %} | |
| 3560 interface(REG_INTER); | |
| 3561 %} | |
| 3562 | |
| 3563 operand o0RegI() %{ | |
| 3564 constraint(ALLOC_IN_RC(o0_regI)); | |
| 3565 match(iRegI); | |
| 3566 | |
| 3567 format %{ %} | |
| 3568 interface(REG_INTER); | |
| 3569 %} | |
| 3570 | |
| 3571 // Pointer Register | |
| 3572 operand iRegP() %{ | |
| 3573 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 3574 match(RegP); | |
| 3575 | |
| 3576 match(lock_ptr_RegP); | |
| 3577 match(g1RegP); | |
| 3578 match(g2RegP); | |
| 3579 match(g3RegP); | |
| 3580 match(g4RegP); | |
| 3581 match(i0RegP); | |
| 3582 match(o0RegP); | |
| 3583 match(o1RegP); | |
| 3584 match(l7RegP); | |
| 3585 | |
| 3586 format %{ %} | |
| 3587 interface(REG_INTER); | |
| 3588 %} | |
| 3589 | |
| 3590 operand sp_ptr_RegP() %{ | |
| 3591 constraint(ALLOC_IN_RC(sp_ptr_reg)); | |
| 3592 match(RegP); | |
| 3593 match(iRegP); | |
| 3594 | |
| 3595 format %{ %} | |
| 3596 interface(REG_INTER); | |
| 3597 %} | |
| 3598 | |
| 3599 operand lock_ptr_RegP() %{ | |
| 3600 constraint(ALLOC_IN_RC(lock_ptr_reg)); | |
| 3601 match(RegP); | |
| 3602 match(i0RegP); | |
| 3603 match(o0RegP); | |
| 3604 match(o1RegP); | |
| 3605 match(l7RegP); | |
| 3606 | |
| 3607 format %{ %} | |
| 3608 interface(REG_INTER); | |
| 3609 %} | |
| 3610 | |
| 3611 operand g1RegP() %{ | |
| 3612 constraint(ALLOC_IN_RC(g1_regP)); | |
| 3613 match(iRegP); | |
| 3614 | |
| 3615 format %{ %} | |
| 3616 interface(REG_INTER); | |
| 3617 %} | |
| 3618 | |
| 3619 operand g2RegP() %{ | |
| 3620 constraint(ALLOC_IN_RC(g2_regP)); | |
| 3621 match(iRegP); | |
| 3622 | |
| 3623 format %{ %} | |
| 3624 interface(REG_INTER); | |
| 3625 %} | |
| 3626 | |
| 3627 operand g3RegP() %{ | |
| 3628 constraint(ALLOC_IN_RC(g3_regP)); | |
| 3629 match(iRegP); | |
| 3630 | |
| 3631 format %{ %} | |
| 3632 interface(REG_INTER); | |
| 3633 %} | |
| 3634 | |
| 3635 operand g1RegI() %{ | |
| 3636 constraint(ALLOC_IN_RC(g1_regI)); | |
| 3637 match(iRegI); | |
| 3638 | |
| 3639 format %{ %} | |
| 3640 interface(REG_INTER); | |
| 3641 %} | |
| 3642 | |
| 3643 operand g3RegI() %{ | |
| 3644 constraint(ALLOC_IN_RC(g3_regI)); | |
| 3645 match(iRegI); | |
| 3646 | |
| 3647 format %{ %} | |
| 3648 interface(REG_INTER); | |
| 3649 %} | |
| 3650 | |
| 3651 operand g4RegI() %{ | |
| 3652 constraint(ALLOC_IN_RC(g4_regI)); | |
| 3653 match(iRegI); | |
| 3654 | |
| 3655 format %{ %} | |
| 3656 interface(REG_INTER); | |
| 3657 %} | |
| 3658 | |
| 3659 operand g4RegP() %{ | |
| 3660 constraint(ALLOC_IN_RC(g4_regP)); | |
| 3661 match(iRegP); | |
| 3662 | |
| 3663 format %{ %} | |
| 3664 interface(REG_INTER); | |
| 3665 %} | |
| 3666 | |
| 3667 operand i0RegP() %{ | |
| 3668 constraint(ALLOC_IN_RC(i0_regP)); | |
| 3669 match(iRegP); | |
| 3670 | |
| 3671 format %{ %} | |
| 3672 interface(REG_INTER); | |
| 3673 %} | |
| 3674 | |
| 3675 operand o0RegP() %{ | |
| 3676 constraint(ALLOC_IN_RC(o0_regP)); | |
| 3677 match(iRegP); | |
| 3678 | |
| 3679 format %{ %} | |
| 3680 interface(REG_INTER); | |
| 3681 %} | |
| 3682 | |
| 3683 operand o1RegP() %{ | |
| 3684 constraint(ALLOC_IN_RC(o1_regP)); | |
| 3685 match(iRegP); | |
| 3686 | |
| 3687 format %{ %} | |
| 3688 interface(REG_INTER); | |
| 3689 %} | |
| 3690 | |
| 3691 operand o2RegP() %{ | |
| 3692 constraint(ALLOC_IN_RC(o2_regP)); | |
| 3693 match(iRegP); | |
| 3694 | |
| 3695 format %{ %} | |
| 3696 interface(REG_INTER); | |
| 3697 %} | |
| 3698 | |
| 3699 operand o7RegP() %{ | |
| 3700 constraint(ALLOC_IN_RC(o7_regP)); | |
| 3701 match(iRegP); | |
| 3702 | |
| 3703 format %{ %} | |
| 3704 interface(REG_INTER); | |
| 3705 %} | |
| 3706 | |
| 3707 operand l7RegP() %{ | |
| 3708 constraint(ALLOC_IN_RC(l7_regP)); | |
| 3709 match(iRegP); | |
| 3710 | |
| 3711 format %{ %} | |
| 3712 interface(REG_INTER); | |
| 3713 %} | |
| 3714 | |
| 3715 operand o7RegI() %{ | |
| 3716 constraint(ALLOC_IN_RC(o7_regI)); | |
| 3717 match(iRegI); | |
| 3718 | |
| 3719 format %{ %} | |
| 3720 interface(REG_INTER); | |
| 3721 %} | |
| 3722 | |
|
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3723 operand iRegN() %{ |
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3724 constraint(ALLOC_IN_RC(int_reg)); |
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3725 match(RegN); |
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3726 |
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3727 format %{ %} |
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3728 interface(REG_INTER); |
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3729 %} |
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3730 |
| 0 | 3731 // Long Register |
| 3732 operand iRegL() %{ | |
| 3733 constraint(ALLOC_IN_RC(long_reg)); | |
| 3734 match(RegL); | |
| 3735 | |
| 3736 format %{ %} | |
| 3737 interface(REG_INTER); | |
| 3738 %} | |
| 3739 | |
| 3740 operand o2RegL() %{ | |
| 3741 constraint(ALLOC_IN_RC(o2_regL)); | |
| 3742 match(iRegL); | |
| 3743 | |
| 3744 format %{ %} | |
| 3745 interface(REG_INTER); | |
| 3746 %} | |
| 3747 | |
| 3748 operand o7RegL() %{ | |
| 3749 constraint(ALLOC_IN_RC(o7_regL)); | |
| 3750 match(iRegL); | |
| 3751 | |
| 3752 format %{ %} | |
| 3753 interface(REG_INTER); | |
| 3754 %} | |
| 3755 | |
| 3756 operand g1RegL() %{ | |
| 3757 constraint(ALLOC_IN_RC(g1_regL)); | |
| 3758 match(iRegL); | |
| 3759 | |
| 3760 format %{ %} | |
| 3761 interface(REG_INTER); | |
| 3762 %} | |
| 3763 | |
| 3764 // Int Register safe | |
| 3765 // This is 64bit safe | |
| 3766 operand iRegIsafe() %{ | |
| 3767 constraint(ALLOC_IN_RC(long_reg)); | |
| 3768 | |
| 3769 match(iRegI); | |
| 3770 | |
| 3771 format %{ %} | |
| 3772 interface(REG_INTER); | |
| 3773 %} | |
| 3774 | |
| 3775 // Condition Code Flag Register | |
| 3776 operand flagsReg() %{ | |
| 3777 constraint(ALLOC_IN_RC(int_flags)); | |
| 3778 match(RegFlags); | |
| 3779 | |
| 3780 format %{ "ccr" %} // both ICC and XCC | |
| 3781 interface(REG_INTER); | |
| 3782 %} | |
| 3783 | |
| 3784 // Condition Code Register, unsigned comparisons. | |
| 3785 operand flagsRegU() %{ | |
| 3786 constraint(ALLOC_IN_RC(int_flags)); | |
| 3787 match(RegFlags); | |
| 3788 | |
| 3789 format %{ "icc_U" %} | |
| 3790 interface(REG_INTER); | |
| 3791 %} | |
| 3792 | |
| 3793 // Condition Code Register, pointer comparisons. | |
| 3794 operand flagsRegP() %{ | |
| 3795 constraint(ALLOC_IN_RC(int_flags)); | |
| 3796 match(RegFlags); | |
| 3797 | |
| 3798 #ifdef _LP64 | |
| 3799 format %{ "xcc_P" %} | |
| 3800 #else | |
| 3801 format %{ "icc_P" %} | |
| 3802 #endif | |
| 3803 interface(REG_INTER); | |
| 3804 %} | |
| 3805 | |
| 3806 // Condition Code Register, long comparisons. | |
| 3807 operand flagsRegL() %{ | |
| 3808 constraint(ALLOC_IN_RC(int_flags)); | |
| 3809 match(RegFlags); | |
| 3810 | |
| 3811 format %{ "xcc_L" %} | |
| 3812 interface(REG_INTER); | |
| 3813 %} | |
| 3814 | |
| 3815 // Condition Code Register, floating comparisons, unordered same as "less". | |
| 3816 operand flagsRegF() %{ | |
| 3817 constraint(ALLOC_IN_RC(float_flags)); | |
| 3818 match(RegFlags); | |
| 3819 match(flagsRegF0); | |
| 3820 | |
| 3821 format %{ %} | |
| 3822 interface(REG_INTER); | |
| 3823 %} | |
| 3824 | |
| 3825 operand flagsRegF0() %{ | |
| 3826 constraint(ALLOC_IN_RC(float_flag0)); | |
| 3827 match(RegFlags); | |
| 3828 | |
| 3829 format %{ %} | |
| 3830 interface(REG_INTER); | |
| 3831 %} | |
| 3832 | |
| 3833 | |
| 3834 // Condition Code Flag Register used by long compare | |
| 3835 operand flagsReg_long_LTGE() %{ | |
| 3836 constraint(ALLOC_IN_RC(int_flags)); | |
| 3837 match(RegFlags); | |
| 3838 format %{ "icc_LTGE" %} | |
| 3839 interface(REG_INTER); | |
| 3840 %} | |
| 3841 operand flagsReg_long_EQNE() %{ | |
| 3842 constraint(ALLOC_IN_RC(int_flags)); | |
| 3843 match(RegFlags); | |
| 3844 format %{ "icc_EQNE" %} | |
| 3845 interface(REG_INTER); | |
| 3846 %} | |
| 3847 operand flagsReg_long_LEGT() %{ | |
| 3848 constraint(ALLOC_IN_RC(int_flags)); | |
| 3849 match(RegFlags); | |
| 3850 format %{ "icc_LEGT" %} | |
| 3851 interface(REG_INTER); | |
| 3852 %} | |
| 3853 | |
| 3854 | |
| 3855 operand regD() %{ | |
| 3856 constraint(ALLOC_IN_RC(dflt_reg)); | |
| 3857 match(RegD); | |
| 3858 | |
| 3859 format %{ %} | |
| 3860 interface(REG_INTER); | |
| 3861 %} | |
| 3862 | |
| 3863 operand regF() %{ | |
| 3864 constraint(ALLOC_IN_RC(sflt_reg)); | |
| 3865 match(RegF); | |
| 3866 | |
| 3867 format %{ %} | |
| 3868 interface(REG_INTER); | |
| 3869 %} | |
| 3870 | |
| 3871 operand regD_low() %{ | |
| 3872 constraint(ALLOC_IN_RC(dflt_low_reg)); | |
| 3873 match(RegD); | |
| 3874 | |
| 3875 format %{ %} | |
| 3876 interface(REG_INTER); | |
| 3877 %} | |
| 3878 | |
| 3879 // Special Registers | |
| 3880 | |
| 3881 // Method Register | |
| 3882 operand inline_cache_regP(iRegP reg) %{ | |
| 3883 constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1 | |
| 3884 match(reg); | |
| 3885 format %{ %} | |
| 3886 interface(REG_INTER); | |
| 3887 %} | |
| 3888 | |
| 3889 operand interpreter_method_oop_regP(iRegP reg) %{ | |
| 3890 constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1 | |
| 3891 match(reg); | |
| 3892 format %{ %} | |
| 3893 interface(REG_INTER); | |
| 3894 %} | |
| 3895 | |
| 3896 | |
| 3897 //----------Complex Operands--------------------------------------------------- | |
| 3898 // Indirect Memory Reference | |
| 3899 operand indirect(sp_ptr_RegP reg) %{ | |
| 3900 constraint(ALLOC_IN_RC(sp_ptr_reg)); | |
| 3901 match(reg); | |
| 3902 | |
| 3903 op_cost(100); | |
| 3904 format %{ "[$reg]" %} | |
| 3905 interface(MEMORY_INTER) %{ | |
| 3906 base($reg); | |
| 3907 index(0x0); | |
| 3908 scale(0x0); | |
| 3909 disp(0x0); | |
| 3910 %} | |
| 3911 %} | |
| 3912 | |
| 3913 // Indirect with Offset | |
| 3914 operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{ | |
| 3915 constraint(ALLOC_IN_RC(sp_ptr_reg)); | |
| 3916 match(AddP reg offset); | |
| 3917 | |
| 3918 op_cost(100); | |
| 3919 format %{ "[$reg + $offset]" %} | |
| 3920 interface(MEMORY_INTER) %{ | |
| 3921 base($reg); | |
| 3922 index(0x0); | |
| 3923 scale(0x0); | |
| 3924 disp($offset); | |
| 3925 %} | |
| 3926 %} | |
| 3927 | |
| 3928 // Note: Intel has a swapped version also, like this: | |
| 3929 //operand indOffsetX(iRegI reg, immP offset) %{ | |
| 3930 // constraint(ALLOC_IN_RC(int_reg)); | |
| 3931 // match(AddP offset reg); | |
| 3932 // | |
| 3933 // op_cost(100); | |
| 3934 // format %{ "[$reg + $offset]" %} | |
| 3935 // interface(MEMORY_INTER) %{ | |
| 3936 // base($reg); | |
| 3937 // index(0x0); | |
| 3938 // scale(0x0); | |
| 3939 // disp($offset); | |
| 3940 // %} | |
| 3941 //%} | |
| 3942 //// However, it doesn't make sense for SPARC, since | |
| 3943 // we have no particularly good way to embed oops in | |
| 3944 // single instructions. | |
| 3945 | |
| 3946 // Indirect with Register Index | |
| 3947 operand indIndex(iRegP addr, iRegX index) %{ | |
| 3948 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 3949 match(AddP addr index); | |
| 3950 | |
| 3951 op_cost(100); | |
| 3952 format %{ "[$addr + $index]" %} | |
| 3953 interface(MEMORY_INTER) %{ | |
| 3954 base($addr); | |
| 3955 index($index); | |
| 3956 scale(0x0); | |
| 3957 disp(0x0); | |
| 3958 %} | |
| 3959 %} | |
| 3960 | |
| 3961 //----------Special Memory Operands-------------------------------------------- | |
| 3962 // Stack Slot Operand - This operand is used for loading and storing temporary | |
| 3963 // values on the stack where a match requires a value to | |
| 3964 // flow through memory. | |
| 3965 operand stackSlotI(sRegI reg) %{ | |
| 3966 constraint(ALLOC_IN_RC(stack_slots)); | |
| 3967 op_cost(100); | |
| 3968 //match(RegI); | |
| 3969 format %{ "[$reg]" %} | |
| 3970 interface(MEMORY_INTER) %{ | |
| 3971 base(0xE); // R_SP | |
| 3972 index(0x0); | |
| 3973 scale(0x0); | |
| 3974 disp($reg); // Stack Offset | |
| 3975 %} | |
| 3976 %} | |
| 3977 | |
| 3978 operand stackSlotP(sRegP reg) %{ | |
| 3979 constraint(ALLOC_IN_RC(stack_slots)); | |
| 3980 op_cost(100); | |
| 3981 //match(RegP); | |
| 3982 format %{ "[$reg]" %} | |
| 3983 interface(MEMORY_INTER) %{ | |
| 3984 base(0xE); // R_SP | |
| 3985 index(0x0); | |
| 3986 scale(0x0); | |
| 3987 disp($reg); // Stack Offset | |
| 3988 %} | |
| 3989 %} | |
| 3990 | |
| 3991 operand stackSlotF(sRegF reg) %{ | |
| 3992 constraint(ALLOC_IN_RC(stack_slots)); | |
| 3993 op_cost(100); | |
| 3994 //match(RegF); | |
| 3995 format %{ "[$reg]" %} | |
| 3996 interface(MEMORY_INTER) %{ | |
| 3997 base(0xE); // R_SP | |
| 3998 index(0x0); | |
| 3999 scale(0x0); | |
| 4000 disp($reg); // Stack Offset | |
| 4001 %} | |
| 4002 %} | |
| 4003 operand stackSlotD(sRegD reg) %{ | |
| 4004 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4005 op_cost(100); | |
| 4006 //match(RegD); | |
| 4007 format %{ "[$reg]" %} | |
| 4008 interface(MEMORY_INTER) %{ | |
| 4009 base(0xE); // R_SP | |
| 4010 index(0x0); | |
| 4011 scale(0x0); | |
| 4012 disp($reg); // Stack Offset | |
| 4013 %} | |
| 4014 %} | |
| 4015 operand stackSlotL(sRegL reg) %{ | |
| 4016 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4017 op_cost(100); | |
| 4018 //match(RegL); | |
| 4019 format %{ "[$reg]" %} | |
| 4020 interface(MEMORY_INTER) %{ | |
| 4021 base(0xE); // R_SP | |
| 4022 index(0x0); | |
| 4023 scale(0x0); | |
| 4024 disp($reg); // Stack Offset | |
| 4025 %} | |
| 4026 %} | |
| 4027 | |
| 4028 // Operands for expressing Control Flow | |
| 4029 // NOTE: Label is a predefined operand which should not be redefined in | |
| 4030 // the AD file. It is generically handled within the ADLC. | |
| 4031 | |
| 4032 //----------Conditional Branch Operands---------------------------------------- | |
| 4033 // Comparison Op - This is the operation of the comparison, and is limited to | |
| 4034 // the following set of codes: | |
| 4035 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=) | |
| 4036 // | |
| 4037 // Other attributes of the comparison, such as unsignedness, are specified | |
| 4038 // by the comparison instruction that sets a condition code flags register. | |
| 4039 // That result is represented by a flags operand whose subtype is appropriate | |
| 4040 // to the unsignedness (etc.) of the comparison. | |
| 4041 // | |
| 4042 // Later, the instruction which matches both the Comparison Op (a Bool) and | |
| 4043 // the flags (produced by the Cmp) specifies the coding of the comparison op | |
| 4044 // by matching a specific subtype of Bool operand below, such as cmpOpU. | |
| 4045 | |
| 4046 operand cmpOp() %{ | |
| 4047 match(Bool); | |
| 4048 | |
| 4049 format %{ "" %} | |
| 4050 interface(COND_INTER) %{ | |
| 4051 equal(0x1); | |
| 4052 not_equal(0x9); | |
| 4053 less(0x3); | |
| 4054 greater_equal(0xB); | |
| 4055 less_equal(0x2); | |
| 4056 greater(0xA); | |
| 4057 %} | |
| 4058 %} | |
| 4059 | |
| 4060 // Comparison Op, unsigned | |
| 4061 operand cmpOpU() %{ | |
| 4062 match(Bool); | |
| 4063 | |
| 4064 format %{ "u" %} | |
| 4065 interface(COND_INTER) %{ | |
| 4066 equal(0x1); | |
| 4067 not_equal(0x9); | |
| 4068 less(0x5); | |
| 4069 greater_equal(0xD); | |
| 4070 less_equal(0x4); | |
| 4071 greater(0xC); | |
| 4072 %} | |
| 4073 %} | |
| 4074 | |
| 4075 // Comparison Op, pointer (same as unsigned) | |
| 4076 operand cmpOpP() %{ | |
| 4077 match(Bool); | |
| 4078 | |
| 4079 format %{ "p" %} | |
| 4080 interface(COND_INTER) %{ | |
| 4081 equal(0x1); | |
| 4082 not_equal(0x9); | |
| 4083 less(0x5); | |
| 4084 greater_equal(0xD); | |
| 4085 less_equal(0x4); | |
| 4086 greater(0xC); | |
| 4087 %} | |
| 4088 %} | |
| 4089 | |
| 4090 // Comparison Op, branch-register encoding | |
| 4091 operand cmpOp_reg() %{ | |
| 4092 match(Bool); | |
| 4093 | |
| 4094 format %{ "" %} | |
| 4095 interface(COND_INTER) %{ | |
| 4096 equal (0x1); | |
| 4097 not_equal (0x5); | |
| 4098 less (0x3); | |
| 4099 greater_equal(0x7); | |
| 4100 less_equal (0x2); | |
| 4101 greater (0x6); | |
| 4102 %} | |
| 4103 %} | |
| 4104 | |
| 4105 // Comparison Code, floating, unordered same as less | |
| 4106 operand cmpOpF() %{ | |
| 4107 match(Bool); | |
| 4108 | |
| 4109 format %{ "fl" %} | |
| 4110 interface(COND_INTER) %{ | |
| 4111 equal(0x9); | |
| 4112 not_equal(0x1); | |
| 4113 less(0x3); | |
| 4114 greater_equal(0xB); | |
| 4115 less_equal(0xE); | |
| 4116 greater(0x6); | |
| 4117 %} | |
| 4118 %} | |
| 4119 | |
| 4120 // Used by long compare | |
| 4121 operand cmpOp_commute() %{ | |
| 4122 match(Bool); | |
| 4123 | |
| 4124 format %{ "" %} | |
| 4125 interface(COND_INTER) %{ | |
| 4126 equal(0x1); | |
| 4127 not_equal(0x9); | |
| 4128 less(0xA); | |
| 4129 greater_equal(0x2); | |
| 4130 less_equal(0xB); | |
| 4131 greater(0x3); | |
| 4132 %} | |
| 4133 %} | |
| 4134 | |
| 4135 //----------OPERAND CLASSES---------------------------------------------------- | |
| 4136 // Operand Classes are groups of operands that are used to simplify | |
| 4137 // instruction definitions by not requiring the AD writer to specify seperate | |
| 4138 // instructions for every form of operand when the instruction accepts | |
| 4139 // multiple operand types with the same basic encoding and format. The classic | |
| 4140 // case of this is memory operands. | |
| 4141 // Indirect is not included since its use is limited to Compare & Swap | |
| 4142 opclass memory( indirect, indOffset13, indIndex ); | |
| 4143 | |
| 4144 //----------PIPELINE----------------------------------------------------------- | |
| 4145 pipeline %{ | |
| 4146 | |
| 4147 //----------ATTRIBUTES--------------------------------------------------------- | |
| 4148 attributes %{ | |
| 4149 fixed_size_instructions; // Fixed size instructions | |
| 4150 branch_has_delay_slot; // Branch has delay slot following | |
| 4151 max_instructions_per_bundle = 4; // Up to 4 instructions per bundle | |
| 4152 instruction_unit_size = 4; // An instruction is 4 bytes long | |
| 4153 instruction_fetch_unit_size = 16; // The processor fetches one line | |
| 4154 instruction_fetch_units = 1; // of 16 bytes | |
| 4155 | |
| 4156 // List of nop instructions | |
| 4157 nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR ); | |
| 4158 %} | |
| 4159 | |
| 4160 //----------RESOURCES---------------------------------------------------------- | |
| 4161 // Resources are the functional units available to the machine | |
| 4162 resources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1); | |
| 4163 | |
| 4164 //----------PIPELINE DESCRIPTION----------------------------------------------- | |
| 4165 // Pipeline Description specifies the stages in the machine's pipeline | |
| 4166 | |
| 4167 pipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D); | |
| 4168 | |
| 4169 //----------PIPELINE CLASSES--------------------------------------------------- | |
| 4170 // Pipeline Classes describe the stages in which input and output are | |
| 4171 // referenced by the hardware pipeline. | |
| 4172 | |
| 4173 // Integer ALU reg-reg operation | |
| 4174 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 4175 single_instruction; | |
| 4176 dst : E(write); | |
| 4177 src1 : R(read); | |
| 4178 src2 : R(read); | |
| 4179 IALU : R; | |
| 4180 %} | |
| 4181 | |
| 4182 // Integer ALU reg-reg long operation | |
| 4183 pipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 4184 instruction_count(2); | |
| 4185 dst : E(write); | |
| 4186 src1 : R(read); | |
| 4187 src2 : R(read); | |
| 4188 IALU : R; | |
| 4189 IALU : R; | |
| 4190 %} | |
| 4191 | |
| 4192 // Integer ALU reg-reg long dependent operation | |
| 4193 pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{ | |
| 4194 instruction_count(1); multiple_bundles; | |
| 4195 dst : E(write); | |
| 4196 src1 : R(read); | |
| 4197 src2 : R(read); | |
| 4198 cr : E(write); | |
| 4199 IALU : R(2); | |
| 4200 %} | |
| 4201 | |
| 4202 // Integer ALU reg-imm operaion | |
| 4203 pipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{ | |
| 4204 single_instruction; | |
| 4205 dst : E(write); | |
| 4206 src1 : R(read); | |
| 4207 IALU : R; | |
| 4208 %} | |
| 4209 | |
| 4210 // Integer ALU reg-reg operation with condition code | |
| 4211 pipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{ | |
| 4212 single_instruction; | |
| 4213 dst : E(write); | |
| 4214 cr : E(write); | |
| 4215 src1 : R(read); | |
| 4216 src2 : R(read); | |
| 4217 IALU : R; | |
| 4218 %} | |
| 4219 | |
| 4220 // Integer ALU reg-imm operation with condition code | |
| 4221 pipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{ | |
| 4222 single_instruction; | |
| 4223 dst : E(write); | |
| 4224 cr : E(write); | |
| 4225 src1 : R(read); | |
| 4226 IALU : R; | |
| 4227 %} | |
| 4228 | |
| 4229 // Integer ALU zero-reg operation | |
| 4230 pipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{ | |
| 4231 single_instruction; | |
| 4232 dst : E(write); | |
| 4233 src2 : R(read); | |
| 4234 IALU : R; | |
| 4235 %} | |
| 4236 | |
| 4237 // Integer ALU zero-reg operation with condition code only | |
| 4238 pipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{ | |
| 4239 single_instruction; | |
| 4240 cr : E(write); | |
| 4241 src : R(read); | |
| 4242 IALU : R; | |
| 4243 %} | |
| 4244 | |
| 4245 // Integer ALU reg-reg operation with condition code only | |
| 4246 pipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{ | |
| 4247 single_instruction; | |
| 4248 cr : E(write); | |
| 4249 src1 : R(read); | |
| 4250 src2 : R(read); | |
| 4251 IALU : R; | |
| 4252 %} | |
| 4253 | |
| 4254 // Integer ALU reg-imm operation with condition code only | |
| 4255 pipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{ | |
| 4256 single_instruction; | |
| 4257 cr : E(write); | |
| 4258 src1 : R(read); | |
| 4259 IALU : R; | |
| 4260 %} | |
| 4261 | |
| 4262 // Integer ALU reg-reg-zero operation with condition code only | |
| 4263 pipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{ | |
| 4264 single_instruction; | |
| 4265 cr : E(write); | |
| 4266 src1 : R(read); | |
| 4267 src2 : R(read); | |
| 4268 IALU : R; | |
| 4269 %} | |
| 4270 | |
| 4271 // Integer ALU reg-imm-zero operation with condition code only | |
| 4272 pipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{ | |
| 4273 single_instruction; | |
| 4274 cr : E(write); | |
| 4275 src1 : R(read); | |
| 4276 IALU : R; | |
| 4277 %} | |
| 4278 | |
| 4279 // Integer ALU reg-reg operation with condition code, src1 modified | |
| 4280 pipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{ | |
| 4281 single_instruction; | |
| 4282 cr : E(write); | |
| 4283 src1 : E(write); | |
| 4284 src1 : R(read); | |
| 4285 src2 : R(read); | |
| 4286 IALU : R; | |
| 4287 %} | |
| 4288 | |
| 4289 // Integer ALU reg-imm operation with condition code, src1 modified | |
| 4290 pipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{ | |
| 4291 single_instruction; | |
| 4292 cr : E(write); | |
| 4293 src1 : E(write); | |
| 4294 src1 : R(read); | |
| 4295 IALU : R; | |
| 4296 %} | |
| 4297 | |
| 4298 pipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{ | |
| 4299 multiple_bundles; | |
| 4300 dst : E(write)+4; | |
| 4301 cr : E(write); | |
| 4302 src1 : R(read); | |
| 4303 src2 : R(read); | |
| 4304 IALU : R(3); | |
| 4305 BR : R(2); | |
| 4306 %} | |
| 4307 | |
| 4308 // Integer ALU operation | |
| 4309 pipe_class ialu_none(iRegI dst) %{ | |
| 4310 single_instruction; | |
| 4311 dst : E(write); | |
| 4312 IALU : R; | |
| 4313 %} | |
| 4314 | |
| 4315 // Integer ALU reg operation | |
| 4316 pipe_class ialu_reg(iRegI dst, iRegI src) %{ | |
| 4317 single_instruction; may_have_no_code; | |
| 4318 dst : E(write); | |
| 4319 src : R(read); | |
| 4320 IALU : R; | |
| 4321 %} | |
| 4322 | |
| 4323 // Integer ALU reg conditional operation | |
| 4324 // This instruction has a 1 cycle stall, and cannot execute | |
| 4325 // in the same cycle as the instruction setting the condition | |
| 4326 // code. We kludge this by pretending to read the condition code | |
| 4327 // 1 cycle earlier, and by marking the functional units as busy | |
| 4328 // for 2 cycles with the result available 1 cycle later than | |
| 4329 // is really the case. | |
| 4330 pipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{ | |
| 4331 single_instruction; | |
| 4332 op2_out : C(write); | |
| 4333 op1 : R(read); | |
| 4334 cr : R(read); // This is really E, with a 1 cycle stall | |
| 4335 BR : R(2); | |
| 4336 MS : R(2); | |
| 4337 %} | |
| 4338 | |
| 4339 #ifdef _LP64 | |
| 4340 pipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{ | |
| 4341 instruction_count(1); multiple_bundles; | |
| 4342 dst : C(write)+1; | |
| 4343 src : R(read)+1; | |
| 4344 IALU : R(1); | |
| 4345 BR : E(2); | |
| 4346 MS : E(2); | |
| 4347 %} | |
| 4348 #endif | |
| 4349 | |
| 4350 // Integer ALU reg operation | |
| 4351 pipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{ | |
| 4352 single_instruction; may_have_no_code; | |
| 4353 dst : E(write); | |
| 4354 src : R(read); | |
| 4355 IALU : R; | |
| 4356 %} | |
| 4357 pipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{ | |
| 4358 single_instruction; may_have_no_code; | |
| 4359 dst : E(write); | |
| 4360 src : R(read); | |
| 4361 IALU : R; | |
| 4362 %} | |
| 4363 | |
| 4364 // Two integer ALU reg operations | |
| 4365 pipe_class ialu_reg_2(iRegL dst, iRegL src) %{ | |
| 4366 instruction_count(2); | |
| 4367 dst : E(write); | |
| 4368 src : R(read); | |
| 4369 A0 : R; | |
| 4370 A1 : R; | |
| 4371 %} | |
| 4372 | |
| 4373 // Two integer ALU reg operations | |
| 4374 pipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{ | |
| 4375 instruction_count(2); may_have_no_code; | |
| 4376 dst : E(write); | |
| 4377 src : R(read); | |
| 4378 A0 : R; | |
| 4379 A1 : R; | |
| 4380 %} | |
| 4381 | |
| 4382 // Integer ALU imm operation | |
| 4383 pipe_class ialu_imm(iRegI dst, immI13 src) %{ | |
| 4384 single_instruction; | |
| 4385 dst : E(write); | |
| 4386 IALU : R; | |
| 4387 %} | |
| 4388 | |
| 4389 // Integer ALU reg-reg with carry operation | |
| 4390 pipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{ | |
| 4391 single_instruction; | |
| 4392 dst : E(write); | |
| 4393 src1 : R(read); | |
| 4394 src2 : R(read); | |
| 4395 IALU : R; | |
| 4396 %} | |
| 4397 | |
| 4398 // Integer ALU cc operation | |
| 4399 pipe_class ialu_cc(iRegI dst, flagsReg cc) %{ | |
| 4400 single_instruction; | |
| 4401 dst : E(write); | |
| 4402 cc : R(read); | |
| 4403 IALU : R; | |
| 4404 %} | |
| 4405 | |
| 4406 // Integer ALU cc / second IALU operation | |
| 4407 pipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{ | |
| 4408 instruction_count(1); multiple_bundles; | |
| 4409 dst : E(write)+1; | |
| 4410 src : R(read); | |
| 4411 IALU : R; | |
| 4412 %} | |
| 4413 | |
| 4414 // Integer ALU cc / second IALU operation | |
| 4415 pipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{ | |
| 4416 instruction_count(1); multiple_bundles; | |
| 4417 dst : E(write)+1; | |
| 4418 p : R(read); | |
| 4419 q : R(read); | |
| 4420 IALU : R; | |
| 4421 %} | |
| 4422 | |
| 4423 // Integer ALU hi-lo-reg operation | |
| 4424 pipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{ | |
| 4425 instruction_count(1); multiple_bundles; | |
| 4426 dst : E(write)+1; | |
| 4427 IALU : R(2); | |
| 4428 %} | |
| 4429 | |
| 4430 // Float ALU hi-lo-reg operation (with temp) | |
| 4431 pipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{ | |
| 4432 instruction_count(1); multiple_bundles; | |
| 4433 dst : E(write)+1; | |
| 4434 IALU : R(2); | |
| 4435 %} | |
| 4436 | |
| 4437 // Long Constant | |
| 4438 pipe_class loadConL( iRegL dst, immL src ) %{ | |
| 4439 instruction_count(2); multiple_bundles; | |
| 4440 dst : E(write)+1; | |
| 4441 IALU : R(2); | |
| 4442 IALU : R(2); | |
| 4443 %} | |
| 4444 | |
| 4445 // Pointer Constant | |
| 4446 pipe_class loadConP( iRegP dst, immP src ) %{ | |
| 4447 instruction_count(0); multiple_bundles; | |
| 4448 fixed_latency(6); | |
| 4449 %} | |
| 4450 | |
| 4451 // Polling Address | |
| 4452 pipe_class loadConP_poll( iRegP dst, immP_poll src ) %{ | |
| 4453 #ifdef _LP64 | |
| 4454 instruction_count(0); multiple_bundles; | |
| 4455 fixed_latency(6); | |
| 4456 #else | |
| 4457 dst : E(write); | |
| 4458 IALU : R; | |
| 4459 #endif | |
| 4460 %} | |
| 4461 | |
| 4462 // Long Constant small | |
| 4463 pipe_class loadConLlo( iRegL dst, immL src ) %{ | |
| 4464 instruction_count(2); | |
| 4465 dst : E(write); | |
| 4466 IALU : R; | |
| 4467 IALU : R; | |
| 4468 %} | |
| 4469 | |
| 4470 // [PHH] This is wrong for 64-bit. See LdImmF/D. | |
| 4471 pipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{ | |
| 4472 instruction_count(1); multiple_bundles; | |
| 4473 src : R(read); | |
| 4474 dst : M(write)+1; | |
| 4475 IALU : R; | |
| 4476 MS : E; | |
| 4477 %} | |
| 4478 | |
| 4479 // Integer ALU nop operation | |
| 4480 pipe_class ialu_nop() %{ | |
| 4481 single_instruction; | |
| 4482 IALU : R; | |
| 4483 %} | |
| 4484 | |
| 4485 // Integer ALU nop operation | |
| 4486 pipe_class ialu_nop_A0() %{ | |
| 4487 single_instruction; | |
| 4488 A0 : R; | |
| 4489 %} | |
| 4490 | |
| 4491 // Integer ALU nop operation | |
| 4492 pipe_class ialu_nop_A1() %{ | |
| 4493 single_instruction; | |
| 4494 A1 : R; | |
| 4495 %} | |
| 4496 | |
| 4497 // Integer Multiply reg-reg operation | |
| 4498 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 4499 single_instruction; | |
| 4500 dst : E(write); | |
| 4501 src1 : R(read); | |
| 4502 src2 : R(read); | |
| 4503 MS : R(5); | |
| 4504 %} | |
| 4505 | |
| 4506 // Integer Multiply reg-imm operation | |
| 4507 pipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{ | |
| 4508 single_instruction; | |
| 4509 dst : E(write); | |
| 4510 src1 : R(read); | |
| 4511 MS : R(5); | |
| 4512 %} | |
| 4513 | |
| 4514 pipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 4515 single_instruction; | |
| 4516 dst : E(write)+4; | |
| 4517 src1 : R(read); | |
| 4518 src2 : R(read); | |
| 4519 MS : R(6); | |
| 4520 %} | |
| 4521 | |
| 4522 pipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{ | |
| 4523 single_instruction; | |
| 4524 dst : E(write)+4; | |
| 4525 src1 : R(read); | |
| 4526 MS : R(6); | |
| 4527 %} | |
| 4528 | |
| 4529 // Integer Divide reg-reg | |
| 4530 pipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{ | |
| 4531 instruction_count(1); multiple_bundles; | |
| 4532 dst : E(write); | |
| 4533 temp : E(write); | |
| 4534 src1 : R(read); | |
| 4535 src2 : R(read); | |
| 4536 temp : R(read); | |
| 4537 MS : R(38); | |
| 4538 %} | |
| 4539 | |
| 4540 // Integer Divide reg-imm | |
| 4541 pipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{ | |
| 4542 instruction_count(1); multiple_bundles; | |
| 4543 dst : E(write); | |
| 4544 temp : E(write); | |
| 4545 src1 : R(read); | |
| 4546 temp : R(read); | |
| 4547 MS : R(38); | |
| 4548 %} | |
| 4549 | |
| 4550 // Long Divide | |
| 4551 pipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 4552 dst : E(write)+71; | |
| 4553 src1 : R(read); | |
| 4554 src2 : R(read)+1; | |
| 4555 MS : R(70); | |
| 4556 %} | |
| 4557 | |
| 4558 pipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{ | |
| 4559 dst : E(write)+71; | |
| 4560 src1 : R(read); | |
| 4561 MS : R(70); | |
| 4562 %} | |
| 4563 | |
| 4564 // Floating Point Add Float | |
| 4565 pipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{ | |
| 4566 single_instruction; | |
| 4567 dst : X(write); | |
| 4568 src1 : E(read); | |
| 4569 src2 : E(read); | |
| 4570 FA : R; | |
| 4571 %} | |
| 4572 | |
| 4573 // Floating Point Add Double | |
| 4574 pipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{ | |
| 4575 single_instruction; | |
| 4576 dst : X(write); | |
| 4577 src1 : E(read); | |
| 4578 src2 : E(read); | |
| 4579 FA : R; | |
| 4580 %} | |
| 4581 | |
| 4582 // Floating Point Conditional Move based on integer flags | |
| 4583 pipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{ | |
| 4584 single_instruction; | |
| 4585 dst : X(write); | |
| 4586 src : E(read); | |
| 4587 cr : R(read); | |
| 4588 FA : R(2); | |
| 4589 BR : R(2); | |
| 4590 %} | |
| 4591 | |
| 4592 // Floating Point Conditional Move based on integer flags | |
| 4593 pipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{ | |
| 4594 single_instruction; | |
| 4595 dst : X(write); | |
| 4596 src : E(read); | |
| 4597 cr : R(read); | |
| 4598 FA : R(2); | |
| 4599 BR : R(2); | |
| 4600 %} | |
| 4601 | |
| 4602 // Floating Point Multiply Float | |
| 4603 pipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{ | |
| 4604 single_instruction; | |
| 4605 dst : X(write); | |
| 4606 src1 : E(read); | |
| 4607 src2 : E(read); | |
| 4608 FM : R; | |
| 4609 %} | |
| 4610 | |
| 4611 // Floating Point Multiply Double | |
| 4612 pipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{ | |
| 4613 single_instruction; | |
| 4614 dst : X(write); | |
| 4615 src1 : E(read); | |
| 4616 src2 : E(read); | |
| 4617 FM : R; | |
| 4618 %} | |
| 4619 | |
| 4620 // Floating Point Divide Float | |
| 4621 pipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{ | |
| 4622 single_instruction; | |
| 4623 dst : X(write); | |
| 4624 src1 : E(read); | |
| 4625 src2 : E(read); | |
| 4626 FM : R; | |
| 4627 FDIV : C(14); | |
| 4628 %} | |
| 4629 | |
| 4630 // Floating Point Divide Double | |
| 4631 pipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{ | |
| 4632 single_instruction; | |
| 4633 dst : X(write); | |
| 4634 src1 : E(read); | |
| 4635 src2 : E(read); | |
| 4636 FM : R; | |
| 4637 FDIV : C(17); | |
| 4638 %} | |
| 4639 | |
| 4640 // Floating Point Move/Negate/Abs Float | |
| 4641 pipe_class faddF_reg(regF dst, regF src) %{ | |
| 4642 single_instruction; | |
| 4643 dst : W(write); | |
| 4644 src : E(read); | |
| 4645 FA : R(1); | |
| 4646 %} | |
| 4647 | |
| 4648 // Floating Point Move/Negate/Abs Double | |
| 4649 pipe_class faddD_reg(regD dst, regD src) %{ | |
| 4650 single_instruction; | |
| 4651 dst : W(write); | |
| 4652 src : E(read); | |
| 4653 FA : R; | |
| 4654 %} | |
| 4655 | |
| 4656 // Floating Point Convert F->D | |
| 4657 pipe_class fcvtF2D(regD dst, regF src) %{ | |
| 4658 single_instruction; | |
| 4659 dst : X(write); | |
| 4660 src : E(read); | |
| 4661 FA : R; | |
| 4662 %} | |
| 4663 | |
| 4664 // Floating Point Convert I->D | |
| 4665 pipe_class fcvtI2D(regD dst, regF src) %{ | |
| 4666 single_instruction; | |
| 4667 dst : X(write); | |
| 4668 src : E(read); | |
| 4669 FA : R; | |
| 4670 %} | |
| 4671 | |
| 4672 // Floating Point Convert LHi->D | |
| 4673 pipe_class fcvtLHi2D(regD dst, regD src) %{ | |
| 4674 single_instruction; | |
| 4675 dst : X(write); | |
| 4676 src : E(read); | |
| 4677 FA : R; | |
| 4678 %} | |
| 4679 | |
| 4680 // Floating Point Convert L->D | |
| 4681 pipe_class fcvtL2D(regD dst, regF src) %{ | |
| 4682 single_instruction; | |
| 4683 dst : X(write); | |
| 4684 src : E(read); | |
| 4685 FA : R; | |
| 4686 %} | |
| 4687 | |
| 4688 // Floating Point Convert L->F | |
| 4689 pipe_class fcvtL2F(regD dst, regF src) %{ | |
| 4690 single_instruction; | |
| 4691 dst : X(write); | |
| 4692 src : E(read); | |
| 4693 FA : R; | |
| 4694 %} | |
| 4695 | |
| 4696 // Floating Point Convert D->F | |
| 4697 pipe_class fcvtD2F(regD dst, regF src) %{ | |
| 4698 single_instruction; | |
| 4699 dst : X(write); | |
| 4700 src : E(read); | |
| 4701 FA : R; | |
| 4702 %} | |
| 4703 | |
| 4704 // Floating Point Convert I->L | |
| 4705 pipe_class fcvtI2L(regD dst, regF src) %{ | |
| 4706 single_instruction; | |
| 4707 dst : X(write); | |
| 4708 src : E(read); | |
| 4709 FA : R; | |
| 4710 %} | |
| 4711 | |
| 4712 // Floating Point Convert D->F | |
| 4713 pipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{ | |
| 4714 instruction_count(1); multiple_bundles; | |
| 4715 dst : X(write)+6; | |
| 4716 src : E(read); | |
| 4717 FA : R; | |
| 4718 %} | |
| 4719 | |
| 4720 // Floating Point Convert D->L | |
| 4721 pipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{ | |
| 4722 instruction_count(1); multiple_bundles; | |
| 4723 dst : X(write)+6; | |
| 4724 src : E(read); | |
| 4725 FA : R; | |
| 4726 %} | |
| 4727 | |
| 4728 // Floating Point Convert F->I | |
| 4729 pipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{ | |
| 4730 instruction_count(1); multiple_bundles; | |
| 4731 dst : X(write)+6; | |
| 4732 src : E(read); | |
| 4733 FA : R; | |
| 4734 %} | |
| 4735 | |
| 4736 // Floating Point Convert F->L | |
| 4737 pipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{ | |
| 4738 instruction_count(1); multiple_bundles; | |
| 4739 dst : X(write)+6; | |
| 4740 src : E(read); | |
| 4741 FA : R; | |
| 4742 %} | |
| 4743 | |
| 4744 // Floating Point Convert I->F | |
| 4745 pipe_class fcvtI2F(regF dst, regF src) %{ | |
| 4746 single_instruction; | |
| 4747 dst : X(write); | |
| 4748 src : E(read); | |
| 4749 FA : R; | |
| 4750 %} | |
| 4751 | |
| 4752 // Floating Point Compare | |
| 4753 pipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{ | |
| 4754 single_instruction; | |
| 4755 cr : X(write); | |
| 4756 src1 : E(read); | |
| 4757 src2 : E(read); | |
| 4758 FA : R; | |
| 4759 %} | |
| 4760 | |
| 4761 // Floating Point Compare | |
| 4762 pipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{ | |
| 4763 single_instruction; | |
| 4764 cr : X(write); | |
| 4765 src1 : E(read); | |
| 4766 src2 : E(read); | |
| 4767 FA : R; | |
| 4768 %} | |
| 4769 | |
| 4770 // Floating Add Nop | |
| 4771 pipe_class fadd_nop() %{ | |
| 4772 single_instruction; | |
| 4773 FA : R; | |
| 4774 %} | |
| 4775 | |
| 4776 // Integer Store to Memory | |
| 4777 pipe_class istore_mem_reg(memory mem, iRegI src) %{ | |
| 4778 single_instruction; | |
| 4779 mem : R(read); | |
| 4780 src : C(read); | |
| 4781 MS : R; | |
| 4782 %} | |
| 4783 | |
| 4784 // Integer Store to Memory | |
| 4785 pipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{ | |
| 4786 single_instruction; | |
| 4787 mem : R(read); | |
| 4788 src : C(read); | |
| 4789 MS : R; | |
| 4790 %} | |
| 4791 | |
| 4792 // Integer Store Zero to Memory | |
| 4793 pipe_class istore_mem_zero(memory mem, immI0 src) %{ | |
| 4794 single_instruction; | |
| 4795 mem : R(read); | |
| 4796 MS : R; | |
| 4797 %} | |
| 4798 | |
| 4799 // Special Stack Slot Store | |
| 4800 pipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{ | |
| 4801 single_instruction; | |
| 4802 stkSlot : R(read); | |
| 4803 src : C(read); | |
| 4804 MS : R; | |
| 4805 %} | |
| 4806 | |
| 4807 // Special Stack Slot Store | |
| 4808 pipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{ | |
| 4809 instruction_count(2); multiple_bundles; | |
| 4810 stkSlot : R(read); | |
| 4811 src : C(read); | |
| 4812 MS : R(2); | |
| 4813 %} | |
| 4814 | |
| 4815 // Float Store | |
| 4816 pipe_class fstoreF_mem_reg(memory mem, RegF src) %{ | |
| 4817 single_instruction; | |
| 4818 mem : R(read); | |
| 4819 src : C(read); | |
| 4820 MS : R; | |
| 4821 %} | |
| 4822 | |
| 4823 // Float Store | |
| 4824 pipe_class fstoreF_mem_zero(memory mem, immF0 src) %{ | |
| 4825 single_instruction; | |
| 4826 mem : R(read); | |
| 4827 MS : R; | |
| 4828 %} | |
| 4829 | |
| 4830 // Double Store | |
| 4831 pipe_class fstoreD_mem_reg(memory mem, RegD src) %{ | |
| 4832 instruction_count(1); | |
| 4833 mem : R(read); | |
| 4834 src : C(read); | |
| 4835 MS : R; | |
| 4836 %} | |
| 4837 | |
| 4838 // Double Store | |
| 4839 pipe_class fstoreD_mem_zero(memory mem, immD0 src) %{ | |
| 4840 single_instruction; | |
| 4841 mem : R(read); | |
| 4842 MS : R; | |
| 4843 %} | |
| 4844 | |
| 4845 // Special Stack Slot Float Store | |
| 4846 pipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{ | |
| 4847 single_instruction; | |
| 4848 stkSlot : R(read); | |
| 4849 src : C(read); | |
| 4850 MS : R; | |
| 4851 %} | |
| 4852 | |
| 4853 // Special Stack Slot Double Store | |
| 4854 pipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{ | |
| 4855 single_instruction; | |
| 4856 stkSlot : R(read); | |
| 4857 src : C(read); | |
| 4858 MS : R; | |
| 4859 %} | |
| 4860 | |
| 4861 // Integer Load (when sign bit propagation not needed) | |
| 4862 pipe_class iload_mem(iRegI dst, memory mem) %{ | |
| 4863 single_instruction; | |
| 4864 mem : R(read); | |
| 4865 dst : C(write); | |
| 4866 MS : R; | |
| 4867 %} | |
| 4868 | |
| 4869 // Integer Load from stack operand | |
| 4870 pipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{ | |
| 4871 single_instruction; | |
| 4872 mem : R(read); | |
| 4873 dst : C(write); | |
| 4874 MS : R; | |
| 4875 %} | |
| 4876 | |
| 4877 // Integer Load (when sign bit propagation or masking is needed) | |
| 4878 pipe_class iload_mask_mem(iRegI dst, memory mem) %{ | |
| 4879 single_instruction; | |
| 4880 mem : R(read); | |
| 4881 dst : M(write); | |
| 4882 MS : R; | |
| 4883 %} | |
| 4884 | |
| 4885 // Float Load | |
| 4886 pipe_class floadF_mem(regF dst, memory mem) %{ | |
| 4887 single_instruction; | |
| 4888 mem : R(read); | |
| 4889 dst : M(write); | |
| 4890 MS : R; | |
| 4891 %} | |
| 4892 | |
| 4893 // Float Load | |
| 4894 pipe_class floadD_mem(regD dst, memory mem) %{ | |
| 4895 instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case | |
| 4896 mem : R(read); | |
| 4897 dst : M(write); | |
| 4898 MS : R; | |
| 4899 %} | |
| 4900 | |
| 4901 // Float Load | |
| 4902 pipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{ | |
| 4903 single_instruction; | |
| 4904 stkSlot : R(read); | |
| 4905 dst : M(write); | |
| 4906 MS : R; | |
| 4907 %} | |
| 4908 | |
| 4909 // Float Load | |
| 4910 pipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{ | |
| 4911 single_instruction; | |
| 4912 stkSlot : R(read); | |
| 4913 dst : M(write); | |
| 4914 MS : R; | |
| 4915 %} | |
| 4916 | |
| 4917 // Memory Nop | |
| 4918 pipe_class mem_nop() %{ | |
| 4919 single_instruction; | |
| 4920 MS : R; | |
| 4921 %} | |
| 4922 | |
| 4923 pipe_class sethi(iRegP dst, immI src) %{ | |
| 4924 single_instruction; | |
| 4925 dst : E(write); | |
| 4926 IALU : R; | |
| 4927 %} | |
| 4928 | |
| 4929 pipe_class loadPollP(iRegP poll) %{ | |
| 4930 single_instruction; | |
| 4931 poll : R(read); | |
| 4932 MS : R; | |
| 4933 %} | |
| 4934 | |
| 4935 pipe_class br(Universe br, label labl) %{ | |
| 4936 single_instruction_with_delay_slot; | |
| 4937 BR : R; | |
| 4938 %} | |
| 4939 | |
| 4940 pipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{ | |
| 4941 single_instruction_with_delay_slot; | |
| 4942 cr : E(read); | |
| 4943 BR : R; | |
| 4944 %} | |
| 4945 | |
| 4946 pipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{ | |
| 4947 single_instruction_with_delay_slot; | |
| 4948 op1 : E(read); | |
| 4949 BR : R; | |
| 4950 MS : R; | |
| 4951 %} | |
| 4952 | |
| 4953 pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{ | |
| 4954 single_instruction_with_delay_slot; | |
| 4955 cr : E(read); | |
| 4956 BR : R; | |
| 4957 %} | |
| 4958 | |
| 4959 pipe_class br_nop() %{ | |
| 4960 single_instruction; | |
| 4961 BR : R; | |
| 4962 %} | |
| 4963 | |
| 4964 pipe_class simple_call(method meth) %{ | |
| 4965 instruction_count(2); multiple_bundles; force_serialization; | |
| 4966 fixed_latency(100); | |
| 4967 BR : R(1); | |
| 4968 MS : R(1); | |
| 4969 A0 : R(1); | |
| 4970 %} | |
| 4971 | |
| 4972 pipe_class compiled_call(method meth) %{ | |
| 4973 instruction_count(1); multiple_bundles; force_serialization; | |
| 4974 fixed_latency(100); | |
| 4975 MS : R(1); | |
| 4976 %} | |
| 4977 | |
| 4978 pipe_class call(method meth) %{ | |
| 4979 instruction_count(0); multiple_bundles; force_serialization; | |
| 4980 fixed_latency(100); | |
| 4981 %} | |
| 4982 | |
| 4983 pipe_class tail_call(Universe ignore, label labl) %{ | |
| 4984 single_instruction; has_delay_slot; | |
| 4985 fixed_latency(100); | |
| 4986 BR : R(1); | |
| 4987 MS : R(1); | |
| 4988 %} | |
| 4989 | |
| 4990 pipe_class ret(Universe ignore) %{ | |
| 4991 single_instruction; has_delay_slot; | |
| 4992 BR : R(1); | |
| 4993 MS : R(1); | |
| 4994 %} | |
| 4995 | |
| 4996 pipe_class ret_poll(g3RegP poll) %{ | |
| 4997 instruction_count(3); has_delay_slot; | |
| 4998 poll : E(read); | |
| 4999 MS : R; | |
| 5000 %} | |
| 5001 | |
| 5002 // The real do-nothing guy | |
| 5003 pipe_class empty( ) %{ | |
| 5004 instruction_count(0); | |
| 5005 %} | |
| 5006 | |
| 5007 pipe_class long_memory_op() %{ | |
| 5008 instruction_count(0); multiple_bundles; force_serialization; | |
| 5009 fixed_latency(25); | |
| 5010 MS : R(1); | |
| 5011 %} | |
| 5012 | |
| 5013 // Check-cast | |
| 5014 pipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{ | |
| 5015 array : R(read); | |
| 5016 match : R(read); | |
| 5017 IALU : R(2); | |
| 5018 BR : R(2); | |
| 5019 MS : R; | |
| 5020 %} | |
| 5021 | |
| 5022 // Convert FPU flags into +1,0,-1 | |
| 5023 pipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{ | |
| 5024 src1 : E(read); | |
| 5025 src2 : E(read); | |
| 5026 dst : E(write); | |
| 5027 FA : R; | |
| 5028 MS : R(2); | |
| 5029 BR : R(2); | |
| 5030 %} | |
| 5031 | |
| 5032 // Compare for p < q, and conditionally add y | |
| 5033 pipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{ | |
| 5034 p : E(read); | |
| 5035 q : E(read); | |
| 5036 y : E(read); | |
| 5037 IALU : R(3) | |
| 5038 %} | |
| 5039 | |
| 5040 // Perform a compare, then move conditionally in a branch delay slot. | |
| 5041 pipe_class min_max( iRegI src2, iRegI srcdst ) %{ | |
| 5042 src2 : E(read); | |
| 5043 srcdst : E(read); | |
| 5044 IALU : R; | |
| 5045 BR : R; | |
| 5046 %} | |
| 5047 | |
| 5048 // Define the class for the Nop node | |
| 5049 define %{ | |
| 5050 MachNop = ialu_nop; | |
| 5051 %} | |
| 5052 | |
| 5053 %} | |
| 5054 | |
| 5055 //----------INSTRUCTIONS------------------------------------------------------- | |
| 5056 | |
| 5057 //------------Special Stack Slot instructions - no match rules----------------- | |
| 5058 instruct stkI_to_regF(regF dst, stackSlotI src) %{ | |
| 5059 // No match rule to avoid chain rule match. | |
| 5060 effect(DEF dst, USE src); | |
| 5061 ins_cost(MEMORY_REF_COST); | |
| 5062 size(4); | |
| 5063 format %{ "LDF $src,$dst\t! stkI to regF" %} | |
| 5064 opcode(Assembler::ldf_op3); | |
| 5065 ins_encode(form3_mem_reg(src, dst)); | |
| 5066 ins_pipe(floadF_stk); | |
| 5067 %} | |
| 5068 | |
| 5069 instruct stkL_to_regD(regD dst, stackSlotL src) %{ | |
| 5070 // No match rule to avoid chain rule match. | |
| 5071 effect(DEF dst, USE src); | |
| 5072 ins_cost(MEMORY_REF_COST); | |
| 5073 size(4); | |
| 5074 format %{ "LDDF $src,$dst\t! stkL to regD" %} | |
| 5075 opcode(Assembler::lddf_op3); | |
| 5076 ins_encode(form3_mem_reg(src, dst)); | |
| 5077 ins_pipe(floadD_stk); | |
| 5078 %} | |
| 5079 | |
| 5080 instruct regF_to_stkI(stackSlotI dst, regF src) %{ | |
| 5081 // No match rule to avoid chain rule match. | |
| 5082 effect(DEF dst, USE src); | |
| 5083 ins_cost(MEMORY_REF_COST); | |
| 5084 size(4); | |
| 5085 format %{ "STF $src,$dst\t! regF to stkI" %} | |
| 5086 opcode(Assembler::stf_op3); | |
| 5087 ins_encode(form3_mem_reg(dst, src)); | |
| 5088 ins_pipe(fstoreF_stk_reg); | |
| 5089 %} | |
| 5090 | |
| 5091 instruct regD_to_stkL(stackSlotL dst, regD src) %{ | |
| 5092 // No match rule to avoid chain rule match. | |
| 5093 effect(DEF dst, USE src); | |
| 5094 ins_cost(MEMORY_REF_COST); | |
| 5095 size(4); | |
| 5096 format %{ "STDF $src,$dst\t! regD to stkL" %} | |
| 5097 opcode(Assembler::stdf_op3); | |
| 5098 ins_encode(form3_mem_reg(dst, src)); | |
| 5099 ins_pipe(fstoreD_stk_reg); | |
| 5100 %} | |
| 5101 | |
| 5102 instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{ | |
| 5103 effect(DEF dst, USE src); | |
| 5104 ins_cost(MEMORY_REF_COST*2); | |
| 5105 size(8); | |
| 5106 format %{ "STW $src,$dst.hi\t! long\n\t" | |
| 5107 "STW R_G0,$dst.lo" %} | |
| 5108 opcode(Assembler::stw_op3); | |
| 5109 ins_encode(form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0)); | |
| 5110 ins_pipe(lstoreI_stk_reg); | |
| 5111 %} | |
| 5112 | |
| 5113 instruct regL_to_stkD(stackSlotD dst, iRegL src) %{ | |
| 5114 // No match rule to avoid chain rule match. | |
| 5115 effect(DEF dst, USE src); | |
| 5116 ins_cost(MEMORY_REF_COST); | |
| 5117 size(4); | |
| 5118 format %{ "STX $src,$dst\t! regL to stkD" %} | |
| 5119 opcode(Assembler::stx_op3); | |
| 5120 ins_encode( form3_mem_reg( dst, src ) ); | |
| 5121 ins_pipe(istore_stk_reg); | |
| 5122 %} | |
| 5123 | |
| 5124 //---------- Chain stack slots between similar types -------- | |
| 5125 | |
| 5126 // Load integer from stack slot | |
| 5127 instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{ | |
| 5128 match(Set dst src); | |
| 5129 ins_cost(MEMORY_REF_COST); | |
| 5130 | |
| 5131 size(4); | |
| 5132 format %{ "LDUW $src,$dst\t!stk" %} | |
| 5133 opcode(Assembler::lduw_op3); | |
| 5134 ins_encode( form3_mem_reg( src, dst ) ); | |
| 5135 ins_pipe(iload_mem); | |
| 5136 %} | |
| 5137 | |
| 5138 // Store integer to stack slot | |
| 5139 instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{ | |
| 5140 match(Set dst src); | |
| 5141 ins_cost(MEMORY_REF_COST); | |
| 5142 | |
| 5143 size(4); | |
| 5144 format %{ "STW $src,$dst\t!stk" %} | |
| 5145 opcode(Assembler::stw_op3); | |
| 5146 ins_encode( form3_mem_reg( dst, src ) ); | |
| 5147 ins_pipe(istore_mem_reg); | |
| 5148 %} | |
| 5149 | |
| 5150 // Load long from stack slot | |
| 5151 instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{ | |
| 5152 match(Set dst src); | |
| 5153 | |
| 5154 ins_cost(MEMORY_REF_COST); | |
| 5155 size(4); | |
| 5156 format %{ "LDX $src,$dst\t! long" %} | |
| 5157 opcode(Assembler::ldx_op3); | |
| 5158 ins_encode( form3_mem_reg( src, dst ) ); | |
| 5159 ins_pipe(iload_mem); | |
| 5160 %} | |
| 5161 | |
| 5162 // Store long to stack slot | |
| 5163 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{ | |
| 5164 match(Set dst src); | |
| 5165 | |
| 5166 ins_cost(MEMORY_REF_COST); | |
| 5167 size(4); | |
| 5168 format %{ "STX $src,$dst\t! long" %} | |
| 5169 opcode(Assembler::stx_op3); | |
| 5170 ins_encode( form3_mem_reg( dst, src ) ); | |
| 5171 ins_pipe(istore_mem_reg); | |
| 5172 %} | |
| 5173 | |
| 5174 #ifdef _LP64 | |
| 5175 // Load pointer from stack slot, 64-bit encoding | |
| 5176 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{ | |
| 5177 match(Set dst src); | |
| 5178 ins_cost(MEMORY_REF_COST); | |
| 5179 size(4); | |
| 5180 format %{ "LDX $src,$dst\t!ptr" %} | |
| 5181 opcode(Assembler::ldx_op3); | |
| 5182 ins_encode( form3_mem_reg( src, dst ) ); | |
| 5183 ins_pipe(iload_mem); | |
| 5184 %} | |
| 5185 | |
| 5186 // Store pointer to stack slot | |
| 5187 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{ | |
| 5188 match(Set dst src); | |
| 5189 ins_cost(MEMORY_REF_COST); | |
| 5190 size(4); | |
| 5191 format %{ "STX $src,$dst\t!ptr" %} | |
| 5192 opcode(Assembler::stx_op3); | |
| 5193 ins_encode( form3_mem_reg( dst, src ) ); | |
| 5194 ins_pipe(istore_mem_reg); | |
| 5195 %} | |
| 5196 #else // _LP64 | |
| 5197 // Load pointer from stack slot, 32-bit encoding | |
| 5198 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{ | |
| 5199 match(Set dst src); | |
| 5200 ins_cost(MEMORY_REF_COST); | |
| 5201 format %{ "LDUW $src,$dst\t!ptr" %} | |
| 5202 opcode(Assembler::lduw_op3, Assembler::ldst_op); | |
| 5203 ins_encode( form3_mem_reg( src, dst ) ); | |
| 5204 ins_pipe(iload_mem); | |
| 5205 %} | |
| 5206 | |
| 5207 // Store pointer to stack slot | |
| 5208 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{ | |
| 5209 match(Set dst src); | |
| 5210 ins_cost(MEMORY_REF_COST); | |
| 5211 format %{ "STW $src,$dst\t!ptr" %} | |
| 5212 opcode(Assembler::stw_op3, Assembler::ldst_op); | |
| 5213 ins_encode( form3_mem_reg( dst, src ) ); | |
| 5214 ins_pipe(istore_mem_reg); | |
| 5215 %} | |
| 5216 #endif // _LP64 | |
| 5217 | |
| 5218 //------------Special Nop instructions for bundling - no match rules----------- | |
| 5219 // Nop using the A0 functional unit | |
| 5220 instruct Nop_A0() %{ | |
| 5221 ins_cost(0); | |
| 5222 | |
| 5223 format %{ "NOP ! Alu Pipeline" %} | |
| 5224 opcode(Assembler::or_op3, Assembler::arith_op); | |
| 5225 ins_encode( form2_nop() ); | |
| 5226 ins_pipe(ialu_nop_A0); | |
| 5227 %} | |
| 5228 | |
| 5229 // Nop using the A1 functional unit | |
| 5230 instruct Nop_A1( ) %{ | |
| 5231 ins_cost(0); | |
| 5232 | |
| 5233 format %{ "NOP ! Alu Pipeline" %} | |
| 5234 opcode(Assembler::or_op3, Assembler::arith_op); | |
| 5235 ins_encode( form2_nop() ); | |
| 5236 ins_pipe(ialu_nop_A1); | |
| 5237 %} | |
| 5238 | |
| 5239 // Nop using the memory functional unit | |
| 5240 instruct Nop_MS( ) %{ | |
| 5241 ins_cost(0); | |
| 5242 | |
| 5243 format %{ "NOP ! Memory Pipeline" %} | |
| 5244 ins_encode( emit_mem_nop ); | |
| 5245 ins_pipe(mem_nop); | |
| 5246 %} | |
| 5247 | |
| 5248 // Nop using the floating add functional unit | |
| 5249 instruct Nop_FA( ) %{ | |
| 5250 ins_cost(0); | |
| 5251 | |
| 5252 format %{ "NOP ! Floating Add Pipeline" %} | |
| 5253 ins_encode( emit_fadd_nop ); | |
| 5254 ins_pipe(fadd_nop); | |
| 5255 %} | |
| 5256 | |
| 5257 // Nop using the branch functional unit | |
| 5258 instruct Nop_BR( ) %{ | |
| 5259 ins_cost(0); | |
| 5260 | |
| 5261 format %{ "NOP ! Branch Pipeline" %} | |
| 5262 ins_encode( emit_br_nop ); | |
| 5263 ins_pipe(br_nop); | |
| 5264 %} | |
| 5265 | |
| 5266 //----------Load/Store/Move Instructions--------------------------------------- | |
| 5267 //----------Load Instructions-------------------------------------------------- | |
| 5268 // Load Byte (8bit signed) | |
| 5269 instruct loadB(iRegI dst, memory mem) %{ | |
| 5270 match(Set dst (LoadB mem)); | |
| 5271 ins_cost(MEMORY_REF_COST); | |
| 5272 | |
| 5273 size(4); | |
| 5274 format %{ "LDSB $mem,$dst" %} | |
| 5275 opcode(Assembler::ldsb_op3); | |
| 5276 ins_encode( form3_mem_reg( mem, dst ) ); | |
| 5277 ins_pipe(iload_mask_mem); | |
| 5278 %} | |
| 5279 | |
| 5280 // Load Byte (8bit UNsigned) into an int reg | |
| 5281 instruct loadUB(iRegI dst, memory mem, immI_255 bytemask) %{ | |
| 5282 match(Set dst (AndI (LoadB mem) bytemask)); | |
| 5283 ins_cost(MEMORY_REF_COST); | |
| 5284 | |
| 5285 size(4); | |
| 5286 format %{ "LDUB $mem,$dst" %} | |
| 5287 opcode(Assembler::ldub_op3); | |
| 5288 ins_encode( form3_mem_reg( mem, dst ) ); | |
| 5289 ins_pipe(iload_mask_mem); | |
| 5290 %} | |
| 5291 | |
| 5292 // Load Byte (8bit UNsigned) into a Long Register | |
| 5293 instruct loadUBL(iRegL dst, memory mem, immL_FF bytemask) %{ | |
| 5294 match(Set dst (AndL (ConvI2L (LoadB mem)) bytemask)); | |
| 5295 ins_cost(MEMORY_REF_COST); | |
| 5296 | |
| 5297 size(4); | |
| 5298 format %{ "LDUB $mem,$dst" %} | |
| 5299 opcode(Assembler::ldub_op3); | |
| 5300 ins_encode( form3_mem_reg( mem, dst ) ); | |
| 5301 ins_pipe(iload_mask_mem); | |
| 5302 %} | |
| 5303 | |
| 5304 // Load Char (16bit UNsigned) into a Long Register | |
| 5305 instruct loadUCL(iRegL dst, memory mem, immL_FFFF bytemask) %{ | |
| 5306 match(Set dst (AndL (ConvI2L (LoadC mem)) bytemask)); | |
| 5307 ins_cost(MEMORY_REF_COST); | |
| 5308 | |
| 5309 size(4); | |
| 5310 format %{ "LDUH $mem,$dst" %} | |
| 5311 opcode(Assembler::lduh_op3); | |
| 5312 ins_encode( form3_mem_reg( mem, dst ) ); | |
| 5313 ins_pipe(iload_mask_mem); | |
| 5314 %} | |
| 5315 | |
| 5316 // Load Char (16bit unsigned) | |
| 5317 instruct loadC(iRegI dst, memory mem) %{ | |
| 5318 match(Set dst (LoadC mem)); | |
| 5319 ins_cost(MEMORY_REF_COST); | |
| 5320 | |
| 5321 size(4); | |
| 5322 format %{ "LDUH $mem,$dst" %} | |
| 5323 opcode(Assembler::lduh_op3); | |
| 5324 ins_encode( form3_mem_reg( mem, dst ) ); | |
| 5325 ins_pipe(iload_mask_mem); | |
| 5326 %} | |
| 5327 | |
| 5328 // Load Integer | |
| 5329 instruct loadI(iRegI dst, memory mem) %{ | |
| 5330 match(Set dst (LoadI mem)); | |
| 5331 ins_cost(MEMORY_REF_COST); | |
| 5332 size(4); | |
| 5333 | |
| 5334 format %{ "LDUW $mem,$dst" %} | |
| 5335 opcode(Assembler::lduw_op3); | |
| 5336 ins_encode( form3_mem_reg( mem, dst ) ); | |
| 5337 ins_pipe(iload_mem); | |
| 5338 %} | |
| 5339 | |
| 5340 // Load Long - aligned | |
| 5341 instruct loadL(iRegL dst, memory mem ) %{ | |
| 5342 match(Set dst (LoadL mem)); | |
| 5343 ins_cost(MEMORY_REF_COST); | |
| 5344 size(4); | |
| 5345 format %{ "LDX $mem,$dst\t! long" %} | |
| 5346 opcode(Assembler::ldx_op3); | |
| 5347 ins_encode( form3_mem_reg( mem, dst ) ); | |
| 5348 ins_pipe(iload_mem); | |
| 5349 %} | |
| 5350 | |
| 5351 // Load Long - UNaligned | |
| 5352 instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{ | |
| 5353 match(Set dst (LoadL_unaligned mem)); | |
| 5354 effect(KILL tmp); | |
| 5355 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST); | |
| 5356 size(16); | |
| 5357 format %{ "LDUW $mem+4,R_O7\t! misaligned long\n" | |
| 5358 "\tLDUW $mem ,$dst\n" | |
| 5359 "\tSLLX #32, $dst, $dst\n" | |
| 5360 "\tOR $dst, R_O7, $dst" %} | |
| 5361 opcode(Assembler::lduw_op3); | |
| 5362 ins_encode( form3_mem_reg_long_unaligned_marshal( mem, dst )); | |
| 5363 ins_pipe(iload_mem); | |
| 5364 %} | |
| 5365 | |
| 5366 // Load Aligned Packed Byte into a Double Register | |
| 5367 instruct loadA8B(regD dst, memory mem) %{ | |
| 5368 match(Set dst (Load8B mem)); | |
| 5369 ins_cost(MEMORY_REF_COST); | |
| 5370 size(4); | |
| 5371 format %{ "LDDF $mem,$dst\t! packed8B" %} | |
| 5372 opcode(Assembler::lddf_op3); | |
| 5373 ins_encode( form3_mem_reg( mem, dst ) ); | |
| 5374 ins_pipe(floadD_mem); | |
| 5375 %} | |
| 5376 | |
| 5377 // Load Aligned Packed Char into a Double Register | |
| 5378 instruct loadA4C(regD dst, memory mem) %{ | |
| 5379 match(Set dst (Load4C mem)); | |
| 5380 ins_cost(MEMORY_REF_COST); | |
| 5381 size(4); | |
| 5382 format %{ "LDDF $mem,$dst\t! packed4C" %} | |
| 5383 opcode(Assembler::lddf_op3); | |
| 5384 ins_encode( form3_mem_reg( mem, dst ) ); | |
| 5385 ins_pipe(floadD_mem); | |
| 5386 %} | |
| 5387 | |
| 5388 // Load Aligned Packed Short into a Double Register | |
| 5389 instruct loadA4S(regD dst, memory mem) %{ | |
| 5390 match(Set dst (Load4S mem)); | |
| 5391 ins_cost(MEMORY_REF_COST); | |
| 5392 size(4); | |
| 5393 format %{ "LDDF $mem,$dst\t! packed4S" %} | |
| 5394 opcode(Assembler::lddf_op3); | |
| 5395 ins_encode( form3_mem_reg( mem, dst ) ); | |
| 5396 ins_pipe(floadD_mem); | |
| 5397 %} | |
| 5398 | |
| 5399 // Load Aligned Packed Int into a Double Register | |
| 5400 instruct loadA2I(regD dst, memory mem) %{ | |
| 5401 match(Set dst (Load2I mem)); | |
| 5402 ins_cost(MEMORY_REF_COST); | |
| 5403 size(4); | |
| 5404 format %{ "LDDF $mem,$dst\t! packed2I" %} | |
| 5405 opcode(Assembler::lddf_op3); | |
| 5406 ins_encode( form3_mem_reg( mem, dst ) ); | |
| 5407 ins_pipe(floadD_mem); | |
| 5408 %} | |
| 5409 | |
| 5410 // Load Range | |
| 5411 instruct loadRange(iRegI dst, memory mem) %{ | |
| 5412 match(Set dst (LoadRange mem)); | |
| 5413 ins_cost(MEMORY_REF_COST); | |
| 5414 | |
| 5415 size(4); | |
| 5416 format %{ "LDUW $mem,$dst\t! range" %} | |
| 5417 opcode(Assembler::lduw_op3); | |
| 5418 ins_encode( form3_mem_reg( mem, dst ) ); | |
| 5419 ins_pipe(iload_mem); | |
| 5420 %} | |
| 5421 | |
| 5422 // Load Integer into %f register (for fitos/fitod) | |
| 5423 instruct loadI_freg(regF dst, memory mem) %{ | |
| 5424 match(Set dst (LoadI mem)); | |
| 5425 ins_cost(MEMORY_REF_COST); | |
| 5426 size(4); | |
| 5427 | |
| 5428 format %{ "LDF $mem,$dst\t! for fitos/fitod" %} | |
| 5429 opcode(Assembler::ldf_op3); | |
| 5430 ins_encode( form3_mem_reg( mem, dst ) ); | |
| 5431 ins_pipe(floadF_mem); | |
| 5432 %} | |
| 5433 | |
| 5434 // Load Pointer | |
| 5435 instruct loadP(iRegP dst, memory mem) %{ | |
| 5436 match(Set dst (LoadP mem)); | |
| 5437 ins_cost(MEMORY_REF_COST); | |
| 5438 size(4); | |
| 5439 | |
| 5440 #ifndef _LP64 | |
| 5441 format %{ "LDUW $mem,$dst\t! ptr" %} | |
| 5442 opcode(Assembler::lduw_op3, 0, REGP_OP); | |
| 5443 #else | |
| 5444 format %{ "LDX $mem,$dst\t! ptr" %} | |
| 5445 opcode(Assembler::ldx_op3, 0, REGP_OP); | |
| 5446 #endif | |
| 5447 ins_encode( form3_mem_reg( mem, dst ) ); | |
| 5448 ins_pipe(iload_mem); | |
| 5449 %} | |
| 5450 | |
|
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5451 // Load Compressed Pointer |
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5452 instruct loadN(iRegN dst, memory mem) %{ |
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5453 match(Set dst (LoadN mem)); |
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5454 ins_cost(MEMORY_REF_COST); |
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5455 size(4); |
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5456 |
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5457 format %{ "LDUW $mem,$dst\t! compressed ptr" %} |
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5458 ins_encode %{ |
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5459 Register base = as_Register($mem$$base); |
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5460 Register index = as_Register($mem$$index); |
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5461 Register dst = $dst$$Register; |
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5462 if (index != G0) { |
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5463 __ lduw(base, index, dst); |
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5464 } else { |
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5465 __ lduw(base, $mem$$disp, dst); |
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5466 } |
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5467 %} |
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5468 ins_pipe(iload_mem); |
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5469 %} |
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5470 |
| 0 | 5471 // Load Klass Pointer |
| 5472 instruct loadKlass(iRegP dst, memory mem) %{ | |
| 5473 match(Set dst (LoadKlass mem)); | |
| 5474 ins_cost(MEMORY_REF_COST); | |
| 5475 size(4); | |
| 5476 | |
| 5477 #ifndef _LP64 | |
| 5478 format %{ "LDUW $mem,$dst\t! klass ptr" %} | |
| 5479 opcode(Assembler::lduw_op3, 0, REGP_OP); | |
| 5480 #else | |
| 5481 format %{ "LDX $mem,$dst\t! klass ptr" %} | |
| 5482 opcode(Assembler::ldx_op3, 0, REGP_OP); | |
| 5483 #endif | |
| 5484 ins_encode( form3_mem_reg( mem, dst ) ); | |
| 5485 ins_pipe(iload_mem); | |
| 5486 %} | |
| 5487 | |
|
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5488 // Load narrow Klass Pointer |
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5489 instruct loadNKlass(iRegN dst, memory mem) %{ |
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5490 match(Set dst (LoadNKlass mem)); |
|
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5491 ins_cost(MEMORY_REF_COST); |
|
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5492 size(4); |
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5493 |
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5494 format %{ "LDUW $mem,$dst\t! compressed klass ptr" %} |
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5495 |
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5496 ins_encode %{ |
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5497 Register base = as_Register($mem$$base); |
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5498 Register index = as_Register($mem$$index); |
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5499 Register dst = $dst$$Register; |
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5500 if (index != G0) { |
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5501 __ lduw(base, index, dst); |
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5502 } else { |
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5503 __ lduw(base, $mem$$disp, dst); |
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5504 } |
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5505 %} |
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5506 ins_pipe(iload_mem); |
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5507 %} |
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5508 |
| 0 | 5509 // Load Short (16bit signed) |
| 5510 instruct loadS(iRegI dst, memory mem) %{ | |
| 5511 match(Set dst (LoadS mem)); | |
| 5512 ins_cost(MEMORY_REF_COST); | |
| 5513 | |
| 5514 size(4); | |
| 5515 format %{ "LDSH $mem,$dst" %} | |
| 5516 opcode(Assembler::ldsh_op3); | |
| 5517 ins_encode( form3_mem_reg( mem, dst ) ); | |
| 5518 ins_pipe(iload_mask_mem); | |
| 5519 %} | |
| 5520 | |
| 5521 // Load Double | |
| 5522 instruct loadD(regD dst, memory mem) %{ | |
| 5523 match(Set dst (LoadD mem)); | |
| 5524 ins_cost(MEMORY_REF_COST); | |
| 5525 | |
| 5526 size(4); | |
| 5527 format %{ "LDDF $mem,$dst" %} | |
| 5528 opcode(Assembler::lddf_op3); | |
| 5529 ins_encode( form3_mem_reg( mem, dst ) ); | |
| 5530 ins_pipe(floadD_mem); | |
| 5531 %} | |
| 5532 | |
| 5533 // Load Double - UNaligned | |
| 5534 instruct loadD_unaligned(regD_low dst, memory mem ) %{ | |
| 5535 match(Set dst (LoadD_unaligned mem)); | |
| 5536 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST); | |
| 5537 size(8); | |
| 5538 format %{ "LDF $mem ,$dst.hi\t! misaligned double\n" | |
| 5539 "\tLDF $mem+4,$dst.lo\t!" %} | |
| 5540 opcode(Assembler::ldf_op3); | |
| 5541 ins_encode( form3_mem_reg_double_unaligned( mem, dst )); | |
| 5542 ins_pipe(iload_mem); | |
| 5543 %} | |
| 5544 | |
| 5545 // Load Float | |
| 5546 instruct loadF(regF dst, memory mem) %{ | |
| 5547 match(Set dst (LoadF mem)); | |
| 5548 ins_cost(MEMORY_REF_COST); | |
| 5549 | |
| 5550 size(4); | |
| 5551 format %{ "LDF $mem,$dst" %} | |
| 5552 opcode(Assembler::ldf_op3); | |
| 5553 ins_encode( form3_mem_reg( mem, dst ) ); | |
| 5554 ins_pipe(floadF_mem); | |
| 5555 %} | |
| 5556 | |
| 5557 // Load Constant | |
| 5558 instruct loadConI( iRegI dst, immI src ) %{ | |
| 5559 match(Set dst src); | |
| 5560 ins_cost(DEFAULT_COST * 3/2); | |
| 5561 format %{ "SET $src,$dst" %} | |
| 5562 ins_encode( Set32(src, dst) ); | |
| 5563 ins_pipe(ialu_hi_lo_reg); | |
| 5564 %} | |
| 5565 | |
| 5566 instruct loadConI13( iRegI dst, immI13 src ) %{ | |
| 5567 match(Set dst src); | |
| 5568 | |
| 5569 size(4); | |
| 5570 format %{ "MOV $src,$dst" %} | |
| 5571 ins_encode( Set13( src, dst ) ); | |
| 5572 ins_pipe(ialu_imm); | |
| 5573 %} | |
| 5574 | |
| 5575 instruct loadConP(iRegP dst, immP src) %{ | |
| 5576 match(Set dst src); | |
| 5577 ins_cost(DEFAULT_COST * 3/2); | |
| 5578 format %{ "SET $src,$dst\t!ptr" %} | |
| 5579 // This rule does not use "expand" unlike loadConI because then | |
| 5580 // the result type is not known to be an Oop. An ADLC | |
| 5581 // enhancement will be needed to make that work - not worth it! | |
| 5582 | |
| 5583 ins_encode( SetPtr( src, dst ) ); | |
| 5584 ins_pipe(loadConP); | |
| 5585 | |
| 5586 %} | |
| 5587 | |
| 5588 instruct loadConP0(iRegP dst, immP0 src) %{ | |
| 5589 match(Set dst src); | |
| 5590 | |
| 5591 size(4); | |
| 5592 format %{ "CLR $dst\t!ptr" %} | |
| 5593 ins_encode( SetNull( dst ) ); | |
| 5594 ins_pipe(ialu_imm); | |
| 5595 %} | |
| 5596 | |
| 5597 instruct loadConP_poll(iRegP dst, immP_poll src) %{ | |
| 5598 match(Set dst src); | |
| 5599 ins_cost(DEFAULT_COST); | |
| 5600 format %{ "SET $src,$dst\t!ptr" %} | |
| 5601 ins_encode %{ | |
| 5602 Address polling_page(reg_to_register_object($dst$$reg), (address)os::get_polling_page()); | |
| 5603 __ sethi(polling_page, false ); | |
| 5604 %} | |
| 5605 ins_pipe(loadConP_poll); | |
| 5606 %} | |
| 5607 | |
|
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5608 instruct loadConN0(iRegN dst, immN0 src) %{ |
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5609 match(Set dst src); |
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5610 |
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5611 size(4); |
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5612 format %{ "CLR $dst\t! compressed NULL ptr" %} |
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5613 ins_encode( SetNull( dst ) ); |
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5614 ins_pipe(ialu_imm); |
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5615 %} |
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5616 |
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5617 instruct loadConN(iRegN dst, immN src) %{ |
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5618 match(Set dst src); |
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5619 ins_cost(DEFAULT_COST * 3/2); |
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5620 format %{ "SET $src,$dst\t! compressed ptr" %} |
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5621 ins_encode %{ |
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5622 Register dst = $dst$$Register; |
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5623 __ set_narrow_oop((jobject)$src$$constant, dst); |
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5624 %} |
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5625 ins_pipe(ialu_hi_lo_reg); |
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5626 %} |
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5627 |
| 0 | 5628 instruct loadConL(iRegL dst, immL src, o7RegL tmp) %{ |
| 5629 // %%% maybe this should work like loadConD | |
| 5630 match(Set dst src); | |
| 5631 effect(KILL tmp); | |
| 5632 ins_cost(DEFAULT_COST * 4); | |
| 5633 format %{ "SET64 $src,$dst KILL $tmp\t! long" %} | |
| 5634 ins_encode( LdImmL(src, dst, tmp) ); | |
| 5635 ins_pipe(loadConL); | |
| 5636 %} | |
| 5637 | |
| 5638 instruct loadConL0( iRegL dst, immL0 src ) %{ | |
| 5639 match(Set dst src); | |
| 5640 ins_cost(DEFAULT_COST); | |
| 5641 size(4); | |
| 5642 format %{ "CLR $dst\t! long" %} | |
| 5643 ins_encode( Set13( src, dst ) ); | |
| 5644 ins_pipe(ialu_imm); | |
| 5645 %} | |
| 5646 | |
| 5647 instruct loadConL13( iRegL dst, immL13 src ) %{ | |
| 5648 match(Set dst src); | |
| 5649 ins_cost(DEFAULT_COST * 2); | |
| 5650 | |
| 5651 size(4); | |
| 5652 format %{ "MOV $src,$dst\t! long" %} | |
| 5653 ins_encode( Set13( src, dst ) ); | |
| 5654 ins_pipe(ialu_imm); | |
| 5655 %} | |
| 5656 | |
| 5657 instruct loadConF(regF dst, immF src, o7RegP tmp) %{ | |
| 5658 match(Set dst src); | |
| 5659 effect(KILL tmp); | |
| 5660 | |
| 5661 #ifdef _LP64 | |
| 5662 size(36); | |
| 5663 #else | |
| 5664 size(8); | |
| 5665 #endif | |
| 5666 | |
| 5667 format %{ "SETHI hi(&$src),$tmp\t!get float $src from table\n\t" | |
| 5668 "LDF [$tmp+lo(&$src)],$dst" %} | |
| 5669 ins_encode( LdImmF(src, dst, tmp) ); | |
| 5670 ins_pipe(loadConFD); | |
| 5671 %} | |
| 5672 | |
| 5673 instruct loadConD(regD dst, immD src, o7RegP tmp) %{ | |
| 5674 match(Set dst src); | |
| 5675 effect(KILL tmp); | |
| 5676 | |
| 5677 #ifdef _LP64 | |
| 5678 size(36); | |
| 5679 #else | |
| 5680 size(8); | |
| 5681 #endif | |
| 5682 | |
| 5683 format %{ "SETHI hi(&$src),$tmp\t!get double $src from table\n\t" | |
| 5684 "LDDF [$tmp+lo(&$src)],$dst" %} | |
| 5685 ins_encode( LdImmD(src, dst, tmp) ); | |
| 5686 ins_pipe(loadConFD); | |
| 5687 %} | |
| 5688 | |
| 5689 // Prefetch instructions. | |
| 5690 // Must be safe to execute with invalid address (cannot fault). | |
| 5691 | |
| 5692 instruct prefetchr( memory mem ) %{ | |
| 5693 match( PrefetchRead mem ); | |
| 5694 ins_cost(MEMORY_REF_COST); | |
| 5695 | |
| 5696 format %{ "PREFETCH $mem,0\t! Prefetch read-many" %} | |
| 5697 opcode(Assembler::prefetch_op3); | |
| 5698 ins_encode( form3_mem_prefetch_read( mem ) ); | |
| 5699 ins_pipe(iload_mem); | |
| 5700 %} | |
| 5701 | |
| 5702 instruct prefetchw( memory mem ) %{ | |
| 5703 match( PrefetchWrite mem ); | |
| 5704 ins_cost(MEMORY_REF_COST); | |
| 5705 | |
| 5706 format %{ "PREFETCH $mem,2\t! Prefetch write-many (and read)" %} | |
| 5707 opcode(Assembler::prefetch_op3); | |
| 5708 ins_encode( form3_mem_prefetch_write( mem ) ); | |
| 5709 ins_pipe(iload_mem); | |
| 5710 %} | |
| 5711 | |
| 5712 | |
| 5713 //----------Store Instructions------------------------------------------------- | |
| 5714 // Store Byte | |
| 5715 instruct storeB(memory mem, iRegI src) %{ | |
| 5716 match(Set mem (StoreB mem src)); | |
| 5717 ins_cost(MEMORY_REF_COST); | |
| 5718 | |
| 5719 size(4); | |
| 5720 format %{ "STB $src,$mem\t! byte" %} | |
| 5721 opcode(Assembler::stb_op3); | |
| 5722 ins_encode( form3_mem_reg( mem, src ) ); | |
| 5723 ins_pipe(istore_mem_reg); | |
| 5724 %} | |
| 5725 | |
| 5726 instruct storeB0(memory mem, immI0 src) %{ | |
| 5727 match(Set mem (StoreB mem src)); | |
| 5728 ins_cost(MEMORY_REF_COST); | |
| 5729 | |
| 5730 size(4); | |
| 5731 format %{ "STB $src,$mem\t! byte" %} | |
| 5732 opcode(Assembler::stb_op3); | |
| 5733 ins_encode( form3_mem_reg( mem, R_G0 ) ); | |
| 5734 ins_pipe(istore_mem_zero); | |
| 5735 %} | |
| 5736 | |
| 5737 instruct storeCM0(memory mem, immI0 src) %{ | |
| 5738 match(Set mem (StoreCM mem src)); | |
| 5739 ins_cost(MEMORY_REF_COST); | |
| 5740 | |
| 5741 size(4); | |
| 5742 format %{ "STB $src,$mem\t! CMS card-mark byte 0" %} | |
| 5743 opcode(Assembler::stb_op3); | |
| 5744 ins_encode( form3_mem_reg( mem, R_G0 ) ); | |
| 5745 ins_pipe(istore_mem_zero); | |
| 5746 %} | |
| 5747 | |
| 5748 // Store Char/Short | |
| 5749 instruct storeC(memory mem, iRegI src) %{ | |
| 5750 match(Set mem (StoreC mem src)); | |
| 5751 ins_cost(MEMORY_REF_COST); | |
| 5752 | |
| 5753 size(4); | |
| 5754 format %{ "STH $src,$mem\t! short" %} | |
| 5755 opcode(Assembler::sth_op3); | |
| 5756 ins_encode( form3_mem_reg( mem, src ) ); | |
| 5757 ins_pipe(istore_mem_reg); | |
| 5758 %} | |
| 5759 | |
| 5760 instruct storeC0(memory mem, immI0 src) %{ | |
| 5761 match(Set mem (StoreC mem src)); | |
| 5762 ins_cost(MEMORY_REF_COST); | |
| 5763 | |
| 5764 size(4); | |
| 5765 format %{ "STH $src,$mem\t! short" %} | |
| 5766 opcode(Assembler::sth_op3); | |
| 5767 ins_encode( form3_mem_reg( mem, R_G0 ) ); | |
| 5768 ins_pipe(istore_mem_zero); | |
| 5769 %} | |
| 5770 | |
| 5771 // Store Integer | |
| 5772 instruct storeI(memory mem, iRegI src) %{ | |
| 5773 match(Set mem (StoreI mem src)); | |
| 5774 ins_cost(MEMORY_REF_COST); | |
| 5775 | |
| 5776 size(4); | |
| 5777 format %{ "STW $src,$mem" %} | |
| 5778 opcode(Assembler::stw_op3); | |
| 5779 ins_encode( form3_mem_reg( mem, src ) ); | |
| 5780 ins_pipe(istore_mem_reg); | |
| 5781 %} | |
| 5782 | |
| 5783 // Store Long | |
| 5784 instruct storeL(memory mem, iRegL src) %{ | |
| 5785 match(Set mem (StoreL mem src)); | |
| 5786 ins_cost(MEMORY_REF_COST); | |
| 5787 size(4); | |
| 5788 format %{ "STX $src,$mem\t! long" %} | |
| 5789 opcode(Assembler::stx_op3); | |
| 5790 ins_encode( form3_mem_reg( mem, src ) ); | |
| 5791 ins_pipe(istore_mem_reg); | |
| 5792 %} | |
| 5793 | |
| 5794 instruct storeI0(memory mem, immI0 src) %{ | |
| 5795 match(Set mem (StoreI mem src)); | |
| 5796 ins_cost(MEMORY_REF_COST); | |
| 5797 | |
| 5798 size(4); | |
| 5799 format %{ "STW $src,$mem" %} | |
| 5800 opcode(Assembler::stw_op3); | |
| 5801 ins_encode( form3_mem_reg( mem, R_G0 ) ); | |
| 5802 ins_pipe(istore_mem_zero); | |
| 5803 %} | |
| 5804 | |
| 5805 instruct storeL0(memory mem, immL0 src) %{ | |
| 5806 match(Set mem (StoreL mem src)); | |
| 5807 ins_cost(MEMORY_REF_COST); | |
| 5808 | |
| 5809 size(4); | |
| 5810 format %{ "STX $src,$mem" %} | |
| 5811 opcode(Assembler::stx_op3); | |
| 5812 ins_encode( form3_mem_reg( mem, R_G0 ) ); | |
| 5813 ins_pipe(istore_mem_zero); | |
| 5814 %} | |
| 5815 | |
| 5816 // Store Integer from float register (used after fstoi) | |
| 5817 instruct storeI_Freg(memory mem, regF src) %{ | |
| 5818 match(Set mem (StoreI mem src)); | |
| 5819 ins_cost(MEMORY_REF_COST); | |
| 5820 | |
| 5821 size(4); | |
| 5822 format %{ "STF $src,$mem\t! after fstoi/fdtoi" %} | |
| 5823 opcode(Assembler::stf_op3); | |
| 5824 ins_encode( form3_mem_reg( mem, src ) ); | |
| 5825 ins_pipe(fstoreF_mem_reg); | |
| 5826 %} | |
| 5827 | |
| 5828 // Store Pointer | |
| 5829 instruct storeP(memory dst, sp_ptr_RegP src) %{ | |
| 5830 match(Set dst (StoreP dst src)); | |
| 5831 ins_cost(MEMORY_REF_COST); | |
| 5832 size(4); | |
| 5833 | |
| 5834 #ifndef _LP64 | |
| 5835 format %{ "STW $src,$dst\t! ptr" %} | |
| 5836 opcode(Assembler::stw_op3, 0, REGP_OP); | |
| 5837 #else | |
| 5838 format %{ "STX $src,$dst\t! ptr" %} | |
| 5839 opcode(Assembler::stx_op3, 0, REGP_OP); | |
| 5840 #endif | |
| 5841 ins_encode( form3_mem_reg( dst, src ) ); | |
| 5842 ins_pipe(istore_mem_spORreg); | |
| 5843 %} | |
| 5844 | |
| 5845 instruct storeP0(memory dst, immP0 src) %{ | |
| 5846 match(Set dst (StoreP dst src)); | |
| 5847 ins_cost(MEMORY_REF_COST); | |
| 5848 size(4); | |
| 5849 | |
| 5850 #ifndef _LP64 | |
| 5851 format %{ "STW $src,$dst\t! ptr" %} | |
| 5852 opcode(Assembler::stw_op3, 0, REGP_OP); | |
| 5853 #else | |
| 5854 format %{ "STX $src,$dst\t! ptr" %} | |
| 5855 opcode(Assembler::stx_op3, 0, REGP_OP); | |
| 5856 #endif | |
| 5857 ins_encode( form3_mem_reg( dst, R_G0 ) ); | |
| 5858 ins_pipe(istore_mem_zero); | |
| 5859 %} | |
| 5860 | |
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5861 // Store Compressed Pointer |
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5862 instruct storeN(memory dst, iRegN src) %{ |
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5863 match(Set dst (StoreN dst src)); |
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5864 ins_cost(MEMORY_REF_COST); |
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5865 size(4); |
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5866 |
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5867 format %{ "STW $src,$dst\t! compressed ptr" %} |
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5868 ins_encode %{ |
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5869 Register base = as_Register($dst$$base); |
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5870 Register index = as_Register($dst$$index); |
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5871 Register src = $src$$Register; |
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5872 if (index != G0) { |
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5873 __ stw(src, base, index); |
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5874 } else { |
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5875 __ stw(src, base, $dst$$disp); |
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5876 } |
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5877 %} |
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5878 ins_pipe(istore_mem_spORreg); |
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5879 %} |
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5880 |
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5881 instruct storeN0(memory dst, immN0 src) %{ |
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5882 match(Set dst (StoreN dst src)); |
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5883 ins_cost(MEMORY_REF_COST); |
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5884 size(4); |
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5885 |
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5886 format %{ "STW $src,$dst\t! compressed ptr" %} |
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5887 ins_encode %{ |
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5888 Register base = as_Register($dst$$base); |
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5889 Register index = as_Register($dst$$index); |
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5890 if (index != G0) { |
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5891 __ stw(0, base, index); |
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5892 } else { |
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5893 __ stw(0, base, $dst$$disp); |
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5894 } |
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5895 %} |
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5896 ins_pipe(istore_mem_zero); |
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5897 %} |
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5898 |
| 0 | 5899 // Store Double |
| 5900 instruct storeD( memory mem, regD src) %{ | |
| 5901 match(Set mem (StoreD mem src)); | |
| 5902 ins_cost(MEMORY_REF_COST); | |
| 5903 | |
| 5904 size(4); | |
| 5905 format %{ "STDF $src,$mem" %} | |
| 5906 opcode(Assembler::stdf_op3); | |
| 5907 ins_encode( form3_mem_reg( mem, src ) ); | |
| 5908 ins_pipe(fstoreD_mem_reg); | |
| 5909 %} | |
| 5910 | |
| 5911 instruct storeD0( memory mem, immD0 src) %{ | |
| 5912 match(Set mem (StoreD mem src)); | |
| 5913 ins_cost(MEMORY_REF_COST); | |
| 5914 | |
| 5915 size(4); | |
| 5916 format %{ "STX $src,$mem" %} | |
| 5917 opcode(Assembler::stx_op3); | |
| 5918 ins_encode( form3_mem_reg( mem, R_G0 ) ); | |
| 5919 ins_pipe(fstoreD_mem_zero); | |
| 5920 %} | |
| 5921 | |
| 5922 // Store Float | |
| 5923 instruct storeF( memory mem, regF src) %{ | |
| 5924 match(Set mem (StoreF mem src)); | |
| 5925 ins_cost(MEMORY_REF_COST); | |
| 5926 | |
| 5927 size(4); | |
| 5928 format %{ "STF $src,$mem" %} | |
| 5929 opcode(Assembler::stf_op3); | |
| 5930 ins_encode( form3_mem_reg( mem, src ) ); | |
| 5931 ins_pipe(fstoreF_mem_reg); | |
| 5932 %} | |
| 5933 | |
| 5934 instruct storeF0( memory mem, immF0 src) %{ | |
| 5935 match(Set mem (StoreF mem src)); | |
| 5936 ins_cost(MEMORY_REF_COST); | |
| 5937 | |
| 5938 size(4); | |
| 5939 format %{ "STW $src,$mem\t! storeF0" %} | |
| 5940 opcode(Assembler::stw_op3); | |
| 5941 ins_encode( form3_mem_reg( mem, R_G0 ) ); | |
| 5942 ins_pipe(fstoreF_mem_zero); | |
| 5943 %} | |
| 5944 | |
| 5945 // Store Aligned Packed Bytes in Double register to memory | |
| 5946 instruct storeA8B(memory mem, regD src) %{ | |
| 5947 match(Set mem (Store8B mem src)); | |
| 5948 ins_cost(MEMORY_REF_COST); | |
| 5949 size(4); | |
| 5950 format %{ "STDF $src,$mem\t! packed8B" %} | |
| 5951 opcode(Assembler::stdf_op3); | |
| 5952 ins_encode( form3_mem_reg( mem, src ) ); | |
| 5953 ins_pipe(fstoreD_mem_reg); | |
| 5954 %} | |
| 5955 | |
|
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5956 // Convert oop pointer into compressed form |
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5957 instruct encodeHeapOop(iRegN dst, iRegP src) %{ |
|
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5958 predicate(n->bottom_type()->is_narrowoop()->make_oopptr()->ptr() != TypePtr::NotNull); |
|
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5959 match(Set dst (EncodeP src)); |
|
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5960 format %{ "encode_heap_oop $src, $dst" %} |
|
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5961 ins_encode %{ |
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5962 __ encode_heap_oop($src$$Register, $dst$$Register); |
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5963 %} |
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|
5964 ins_pipe(ialu_reg); |
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5965 %} |
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5966 |
|
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5967 instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{ |
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5968 predicate(n->bottom_type()->is_narrowoop()->make_oopptr()->ptr() == TypePtr::NotNull); |
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5969 match(Set dst (EncodeP src)); |
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5970 format %{ "encode_heap_oop_not_null $src, $dst" %} |
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5971 ins_encode %{ |
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5972 __ encode_heap_oop_not_null($src$$Register, $dst$$Register); |
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5973 %} |
|
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5974 ins_pipe(ialu_reg); |
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|
5975 %} |
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|
5976 |
|
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5977 instruct decodeHeapOop(iRegP dst, iRegN src) %{ |
|
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5978 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull); |
|
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5979 match(Set dst (DecodeN src)); |
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5980 format %{ "decode_heap_oop $src, $dst" %} |
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5981 ins_encode %{ |
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5982 __ decode_heap_oop($src$$Register, $dst$$Register); |
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5983 %} |
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5984 ins_pipe(ialu_reg); |
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5985 %} |
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|
5986 |
|
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5987 instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{ |
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5988 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull); |
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5989 match(Set dst (DecodeN src)); |
|
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|
5990 format %{ "decode_heap_oop_not_null $src, $dst" %} |
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5991 ins_encode %{ |
|
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|
5992 __ decode_heap_oop_not_null($src$$Register, $dst$$Register); |
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5993 %} |
|
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|
5994 ins_pipe(ialu_reg); |
|
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|
5995 %} |
|
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|
5996 |
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5997 |
| 0 | 5998 // Store Zero into Aligned Packed Bytes |
| 5999 instruct storeA8B0(memory mem, immI0 zero) %{ | |
| 6000 match(Set mem (Store8B mem zero)); | |
| 6001 ins_cost(MEMORY_REF_COST); | |
| 6002 size(4); | |
| 6003 format %{ "STX $zero,$mem\t! packed8B" %} | |
| 6004 opcode(Assembler::stx_op3); | |
| 6005 ins_encode( form3_mem_reg( mem, R_G0 ) ); | |
| 6006 ins_pipe(fstoreD_mem_zero); | |
| 6007 %} | |
| 6008 | |
| 6009 // Store Aligned Packed Chars/Shorts in Double register to memory | |
| 6010 instruct storeA4C(memory mem, regD src) %{ | |
| 6011 match(Set mem (Store4C mem src)); | |
| 6012 ins_cost(MEMORY_REF_COST); | |
| 6013 size(4); | |
| 6014 format %{ "STDF $src,$mem\t! packed4C" %} | |
| 6015 opcode(Assembler::stdf_op3); | |
| 6016 ins_encode( form3_mem_reg( mem, src ) ); | |
| 6017 ins_pipe(fstoreD_mem_reg); | |
| 6018 %} | |
| 6019 | |
| 6020 // Store Zero into Aligned Packed Chars/Shorts | |
| 6021 instruct storeA4C0(memory mem, immI0 zero) %{ | |
| 6022 match(Set mem (Store4C mem (Replicate4C zero))); | |
| 6023 ins_cost(MEMORY_REF_COST); | |
| 6024 size(4); | |
| 6025 format %{ "STX $zero,$mem\t! packed4C" %} | |
| 6026 opcode(Assembler::stx_op3); | |
| 6027 ins_encode( form3_mem_reg( mem, R_G0 ) ); | |
| 6028 ins_pipe(fstoreD_mem_zero); | |
| 6029 %} | |
| 6030 | |
| 6031 // Store Aligned Packed Ints in Double register to memory | |
| 6032 instruct storeA2I(memory mem, regD src) %{ | |
| 6033 match(Set mem (Store2I mem src)); | |
| 6034 ins_cost(MEMORY_REF_COST); | |
| 6035 size(4); | |
| 6036 format %{ "STDF $src,$mem\t! packed2I" %} | |
| 6037 opcode(Assembler::stdf_op3); | |
| 6038 ins_encode( form3_mem_reg( mem, src ) ); | |
| 6039 ins_pipe(fstoreD_mem_reg); | |
| 6040 %} | |
| 6041 | |
| 6042 // Store Zero into Aligned Packed Ints | |
| 6043 instruct storeA2I0(memory mem, immI0 zero) %{ | |
| 6044 match(Set mem (Store2I mem zero)); | |
| 6045 ins_cost(MEMORY_REF_COST); | |
| 6046 size(4); | |
| 6047 format %{ "STX $zero,$mem\t! packed2I" %} | |
| 6048 opcode(Assembler::stx_op3); | |
| 6049 ins_encode( form3_mem_reg( mem, R_G0 ) ); | |
| 6050 ins_pipe(fstoreD_mem_zero); | |
| 6051 %} | |
| 6052 | |
| 6053 | |
| 6054 //----------MemBar Instructions----------------------------------------------- | |
| 6055 // Memory barrier flavors | |
| 6056 | |
| 6057 instruct membar_acquire() %{ | |
| 6058 match(MemBarAcquire); | |
| 6059 ins_cost(4*MEMORY_REF_COST); | |
| 6060 | |
| 6061 size(0); | |
| 6062 format %{ "MEMBAR-acquire" %} | |
| 6063 ins_encode( enc_membar_acquire ); | |
| 6064 ins_pipe(long_memory_op); | |
| 6065 %} | |
| 6066 | |
| 6067 instruct membar_acquire_lock() %{ | |
| 6068 match(MemBarAcquire); | |
| 6069 predicate(Matcher::prior_fast_lock(n)); | |
| 6070 ins_cost(0); | |
| 6071 | |
| 6072 size(0); | |
| 6073 format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %} | |
| 6074 ins_encode( ); | |
| 6075 ins_pipe(empty); | |
| 6076 %} | |
| 6077 | |
| 6078 instruct membar_release() %{ | |
| 6079 match(MemBarRelease); | |
| 6080 ins_cost(4*MEMORY_REF_COST); | |
| 6081 | |
| 6082 size(0); | |
| 6083 format %{ "MEMBAR-release" %} | |
| 6084 ins_encode( enc_membar_release ); | |
| 6085 ins_pipe(long_memory_op); | |
| 6086 %} | |
| 6087 | |
| 6088 instruct membar_release_lock() %{ | |
| 6089 match(MemBarRelease); | |
| 6090 predicate(Matcher::post_fast_unlock(n)); | |
| 6091 ins_cost(0); | |
| 6092 | |
| 6093 size(0); | |
| 6094 format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %} | |
| 6095 ins_encode( ); | |
| 6096 ins_pipe(empty); | |
| 6097 %} | |
| 6098 | |
| 6099 instruct membar_volatile() %{ | |
| 6100 match(MemBarVolatile); | |
| 6101 ins_cost(4*MEMORY_REF_COST); | |
| 6102 | |
| 6103 size(4); | |
| 6104 format %{ "MEMBAR-volatile" %} | |
| 6105 ins_encode( enc_membar_volatile ); | |
| 6106 ins_pipe(long_memory_op); | |
| 6107 %} | |
| 6108 | |
| 6109 instruct unnecessary_membar_volatile() %{ | |
| 6110 match(MemBarVolatile); | |
| 6111 predicate(Matcher::post_store_load_barrier(n)); | |
| 6112 ins_cost(0); | |
| 6113 | |
| 6114 size(0); | |
| 6115 format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %} | |
| 6116 ins_encode( ); | |
| 6117 ins_pipe(empty); | |
| 6118 %} | |
| 6119 | |
| 6120 //----------Register Move Instructions----------------------------------------- | |
| 6121 instruct roundDouble_nop(regD dst) %{ | |
| 6122 match(Set dst (RoundDouble dst)); | |
| 6123 ins_cost(0); | |
| 6124 // SPARC results are already "rounded" (i.e., normal-format IEEE) | |
| 6125 ins_encode( ); | |
| 6126 ins_pipe(empty); | |
| 6127 %} | |
| 6128 | |
| 6129 | |
| 6130 instruct roundFloat_nop(regF dst) %{ | |
| 6131 match(Set dst (RoundFloat dst)); | |
| 6132 ins_cost(0); | |
| 6133 // SPARC results are already "rounded" (i.e., normal-format IEEE) | |
| 6134 ins_encode( ); | |
| 6135 ins_pipe(empty); | |
| 6136 %} | |
| 6137 | |
| 6138 | |
| 6139 // Cast Index to Pointer for unsafe natives | |
| 6140 instruct castX2P(iRegX src, iRegP dst) %{ | |
| 6141 match(Set dst (CastX2P src)); | |
| 6142 | |
| 6143 format %{ "MOV $src,$dst\t! IntX->Ptr" %} | |
| 6144 ins_encode( form3_g0_rs2_rd_move( src, dst ) ); | |
| 6145 ins_pipe(ialu_reg); | |
| 6146 %} | |
| 6147 | |
| 6148 // Cast Pointer to Index for unsafe natives | |
| 6149 instruct castP2X(iRegP src, iRegX dst) %{ | |
| 6150 match(Set dst (CastP2X src)); | |
| 6151 | |
| 6152 format %{ "MOV $src,$dst\t! Ptr->IntX" %} | |
| 6153 ins_encode( form3_g0_rs2_rd_move( src, dst ) ); | |
| 6154 ins_pipe(ialu_reg); | |
| 6155 %} | |
| 6156 | |
| 6157 instruct stfSSD(stackSlotD stkSlot, regD src) %{ | |
| 6158 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! | |
| 6159 match(Set stkSlot src); // chain rule | |
| 6160 ins_cost(MEMORY_REF_COST); | |
| 6161 format %{ "STDF $src,$stkSlot\t!stk" %} | |
| 6162 opcode(Assembler::stdf_op3); | |
| 6163 ins_encode(form3_mem_reg(stkSlot, src)); | |
| 6164 ins_pipe(fstoreD_stk_reg); | |
| 6165 %} | |
| 6166 | |
| 6167 instruct ldfSSD(regD dst, stackSlotD stkSlot) %{ | |
| 6168 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! | |
| 6169 match(Set dst stkSlot); // chain rule | |
| 6170 ins_cost(MEMORY_REF_COST); | |
| 6171 format %{ "LDDF $stkSlot,$dst\t!stk" %} | |
| 6172 opcode(Assembler::lddf_op3); | |
| 6173 ins_encode(form3_mem_reg(stkSlot, dst)); | |
| 6174 ins_pipe(floadD_stk); | |
| 6175 %} | |
| 6176 | |
| 6177 instruct stfSSF(stackSlotF stkSlot, regF src) %{ | |
| 6178 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! | |
| 6179 match(Set stkSlot src); // chain rule | |
| 6180 ins_cost(MEMORY_REF_COST); | |
| 6181 format %{ "STF $src,$stkSlot\t!stk" %} | |
| 6182 opcode(Assembler::stf_op3); | |
| 6183 ins_encode(form3_mem_reg(stkSlot, src)); | |
| 6184 ins_pipe(fstoreF_stk_reg); | |
| 6185 %} | |
| 6186 | |
| 6187 //----------Conditional Move--------------------------------------------------- | |
| 6188 // Conditional move | |
| 6189 instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{ | |
| 6190 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src))); | |
| 6191 ins_cost(150); | |
| 6192 format %{ "MOV$cmp $pcc,$src,$dst" %} | |
| 6193 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
| 6194 ins_pipe(ialu_reg); | |
| 6195 %} | |
| 6196 | |
| 6197 instruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{ | |
| 6198 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src))); | |
| 6199 ins_cost(140); | |
| 6200 format %{ "MOV$cmp $pcc,$src,$dst" %} | |
| 6201 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); | |
| 6202 ins_pipe(ialu_imm); | |
| 6203 %} | |
| 6204 | |
| 6205 instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{ | |
| 6206 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); | |
| 6207 ins_cost(150); | |
| 6208 size(4); | |
| 6209 format %{ "MOV$cmp $icc,$src,$dst" %} | |
| 6210 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); | |
| 6211 ins_pipe(ialu_reg); | |
| 6212 %} | |
| 6213 | |
| 6214 instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{ | |
| 6215 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); | |
| 6216 ins_cost(140); | |
| 6217 size(4); | |
| 6218 format %{ "MOV$cmp $icc,$src,$dst" %} | |
| 6219 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); | |
| 6220 ins_pipe(ialu_imm); | |
| 6221 %} | |
| 6222 | |
|
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6223 instruct cmovII_U_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{ |
| 0 | 6224 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); |
| 6225 ins_cost(150); | |
| 6226 size(4); | |
| 6227 format %{ "MOV$cmp $icc,$src,$dst" %} | |
| 6228 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); | |
| 6229 ins_pipe(ialu_reg); | |
| 6230 %} | |
| 6231 | |
|
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6232 instruct cmovII_U_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{ |
| 0 | 6233 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); |
| 6234 ins_cost(140); | |
| 6235 size(4); | |
| 6236 format %{ "MOV$cmp $icc,$src,$dst" %} | |
| 6237 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); | |
| 6238 ins_pipe(ialu_imm); | |
| 6239 %} | |
| 6240 | |
| 6241 instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{ | |
| 6242 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src))); | |
| 6243 ins_cost(150); | |
| 6244 size(4); | |
| 6245 format %{ "MOV$cmp $fcc,$src,$dst" %} | |
| 6246 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); | |
| 6247 ins_pipe(ialu_reg); | |
| 6248 %} | |
| 6249 | |
| 6250 instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{ | |
| 6251 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src))); | |
| 6252 ins_cost(140); | |
| 6253 size(4); | |
| 6254 format %{ "MOV$cmp $fcc,$src,$dst" %} | |
| 6255 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) ); | |
| 6256 ins_pipe(ialu_imm); | |
| 6257 %} | |
| 6258 | |
|
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6259 // Conditional move for RegN. Only cmov(reg,reg). |
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6260 instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{ |
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6261 match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src))); |
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6262 ins_cost(150); |
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6263 format %{ "MOV$cmp $pcc,$src,$dst" %} |
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6264 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); |
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6265 ins_pipe(ialu_reg); |
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6266 %} |
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|
6267 |
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6268 // This instruction also works with CmpN so we don't need cmovNN_reg. |
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6269 instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{ |
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6270 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src))); |
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6271 ins_cost(150); |
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6272 size(4); |
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6273 format %{ "MOV$cmp $icc,$src,$dst" %} |
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6274 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); |
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6275 ins_pipe(ialu_reg); |
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6276 %} |
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|
6277 |
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6278 instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{ |
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6279 match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src))); |
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6280 ins_cost(150); |
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|
6281 size(4); |
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6282 format %{ "MOV$cmp $fcc,$src,$dst" %} |
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6283 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); |
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6284 ins_pipe(ialu_reg); |
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6285 %} |
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6286 |
| 0 | 6287 // Conditional move |
| 6288 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{ | |
| 6289 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src))); | |
| 6290 ins_cost(150); | |
| 6291 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %} | |
| 6292 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
| 6293 ins_pipe(ialu_reg); | |
| 6294 %} | |
| 6295 | |
| 6296 instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{ | |
| 6297 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src))); | |
| 6298 ins_cost(140); | |
| 6299 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %} | |
| 6300 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); | |
| 6301 ins_pipe(ialu_imm); | |
| 6302 %} | |
| 6303 | |
|
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6304 // This instruction also works with CmpN so we don't need cmovPN_reg. |
| 0 | 6305 instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{ |
| 6306 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); | |
| 6307 ins_cost(150); | |
| 6308 | |
| 6309 size(4); | |
| 6310 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} | |
| 6311 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); | |
| 6312 ins_pipe(ialu_reg); | |
| 6313 %} | |
| 6314 | |
| 6315 instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{ | |
| 6316 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); | |
| 6317 ins_cost(140); | |
| 6318 | |
| 6319 size(4); | |
| 6320 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} | |
| 6321 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); | |
| 6322 ins_pipe(ialu_imm); | |
| 6323 %} | |
| 6324 | |
| 6325 instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{ | |
| 6326 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src))); | |
| 6327 ins_cost(150); | |
| 6328 size(4); | |
| 6329 format %{ "MOV$cmp $fcc,$src,$dst" %} | |
| 6330 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); | |
| 6331 ins_pipe(ialu_imm); | |
| 6332 %} | |
| 6333 | |
| 6334 instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{ | |
| 6335 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src))); | |
| 6336 ins_cost(140); | |
| 6337 size(4); | |
| 6338 format %{ "MOV$cmp $fcc,$src,$dst" %} | |
| 6339 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) ); | |
| 6340 ins_pipe(ialu_imm); | |
| 6341 %} | |
| 6342 | |
| 6343 // Conditional move | |
| 6344 instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{ | |
| 6345 match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src))); | |
| 6346 ins_cost(150); | |
| 6347 opcode(0x101); | |
| 6348 format %{ "FMOVD$cmp $pcc,$src,$dst" %} | |
| 6349 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
| 6350 ins_pipe(int_conditional_float_move); | |
| 6351 %} | |
| 6352 | |
| 6353 instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{ | |
| 6354 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src))); | |
| 6355 ins_cost(150); | |
| 6356 | |
| 6357 size(4); | |
| 6358 format %{ "FMOVS$cmp $icc,$src,$dst" %} | |
| 6359 opcode(0x101); | |
| 6360 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); | |
| 6361 ins_pipe(int_conditional_float_move); | |
| 6362 %} | |
| 6363 | |
| 6364 // Conditional move, | |
| 6365 instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{ | |
| 6366 match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src))); | |
| 6367 ins_cost(150); | |
| 6368 size(4); | |
| 6369 format %{ "FMOVF$cmp $fcc,$src,$dst" %} | |
| 6370 opcode(0x1); | |
| 6371 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) ); | |
| 6372 ins_pipe(int_conditional_double_move); | |
| 6373 %} | |
| 6374 | |
| 6375 // Conditional move | |
| 6376 instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{ | |
| 6377 match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src))); | |
| 6378 ins_cost(150); | |
| 6379 size(4); | |
| 6380 opcode(0x102); | |
| 6381 format %{ "FMOVD$cmp $pcc,$src,$dst" %} | |
| 6382 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
| 6383 ins_pipe(int_conditional_double_move); | |
| 6384 %} | |
| 6385 | |
| 6386 instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{ | |
| 6387 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src))); | |
| 6388 ins_cost(150); | |
| 6389 | |
| 6390 size(4); | |
| 6391 format %{ "FMOVD$cmp $icc,$src,$dst" %} | |
| 6392 opcode(0x102); | |
| 6393 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); | |
| 6394 ins_pipe(int_conditional_double_move); | |
| 6395 %} | |
| 6396 | |
| 6397 // Conditional move, | |
| 6398 instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{ | |
| 6399 match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src))); | |
| 6400 ins_cost(150); | |
| 6401 size(4); | |
| 6402 format %{ "FMOVD$cmp $fcc,$src,$dst" %} | |
| 6403 opcode(0x2); | |
| 6404 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) ); | |
| 6405 ins_pipe(int_conditional_double_move); | |
| 6406 %} | |
| 6407 | |
| 6408 // Conditional move | |
| 6409 instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{ | |
| 6410 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src))); | |
| 6411 ins_cost(150); | |
| 6412 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %} | |
| 6413 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
| 6414 ins_pipe(ialu_reg); | |
| 6415 %} | |
| 6416 | |
| 6417 instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{ | |
| 6418 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src))); | |
| 6419 ins_cost(140); | |
| 6420 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %} | |
| 6421 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); | |
| 6422 ins_pipe(ialu_imm); | |
| 6423 %} | |
| 6424 | |
| 6425 instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{ | |
| 6426 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src))); | |
| 6427 ins_cost(150); | |
| 6428 | |
| 6429 size(4); | |
| 6430 format %{ "MOV$cmp $icc,$src,$dst\t! long" %} | |
| 6431 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); | |
| 6432 ins_pipe(ialu_reg); | |
| 6433 %} | |
| 6434 | |
| 6435 | |
| 6436 instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{ | |
| 6437 match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src))); | |
| 6438 ins_cost(150); | |
| 6439 | |
| 6440 size(4); | |
| 6441 format %{ "MOV$cmp $fcc,$src,$dst\t! long" %} | |
| 6442 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); | |
| 6443 ins_pipe(ialu_reg); | |
| 6444 %} | |
| 6445 | |
| 6446 | |
| 6447 | |
| 6448 //----------OS and Locking Instructions---------------------------------------- | |
| 6449 | |
| 6450 // This name is KNOWN by the ADLC and cannot be changed. | |
| 6451 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type | |
| 6452 // for this guy. | |
| 6453 instruct tlsLoadP(g2RegP dst) %{ | |
| 6454 match(Set dst (ThreadLocal)); | |
| 6455 | |
| 6456 size(0); | |
| 6457 ins_cost(0); | |
| 6458 format %{ "# TLS is in G2" %} | |
| 6459 ins_encode( /*empty encoding*/ ); | |
| 6460 ins_pipe(ialu_none); | |
| 6461 %} | |
| 6462 | |
| 6463 instruct checkCastPP( iRegP dst ) %{ | |
| 6464 match(Set dst (CheckCastPP dst)); | |
| 6465 | |
| 6466 size(0); | |
| 6467 format %{ "# checkcastPP of $dst" %} | |
| 6468 ins_encode( /*empty encoding*/ ); | |
| 6469 ins_pipe(empty); | |
| 6470 %} | |
| 6471 | |
| 6472 | |
| 6473 instruct castPP( iRegP dst ) %{ | |
| 6474 match(Set dst (CastPP dst)); | |
| 6475 format %{ "# castPP of $dst" %} | |
| 6476 ins_encode( /*empty encoding*/ ); | |
| 6477 ins_pipe(empty); | |
| 6478 %} | |
| 6479 | |
| 6480 instruct castII( iRegI dst ) %{ | |
| 6481 match(Set dst (CastII dst)); | |
| 6482 format %{ "# castII of $dst" %} | |
| 6483 ins_encode( /*empty encoding*/ ); | |
| 6484 ins_cost(0); | |
| 6485 ins_pipe(empty); | |
| 6486 %} | |
| 6487 | |
| 6488 //----------Arithmetic Instructions-------------------------------------------- | |
| 6489 // Addition Instructions | |
| 6490 // Register Addition | |
| 6491 instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 6492 match(Set dst (AddI src1 src2)); | |
| 6493 | |
| 6494 size(4); | |
| 6495 format %{ "ADD $src1,$src2,$dst" %} | |
| 6496 ins_encode %{ | |
| 6497 __ add($src1$$Register, $src2$$Register, $dst$$Register); | |
| 6498 %} | |
| 6499 ins_pipe(ialu_reg_reg); | |
| 6500 %} | |
| 6501 | |
| 6502 // Immediate Addition | |
| 6503 instruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
| 6504 match(Set dst (AddI src1 src2)); | |
| 6505 | |
| 6506 size(4); | |
| 6507 format %{ "ADD $src1,$src2,$dst" %} | |
| 6508 opcode(Assembler::add_op3, Assembler::arith_op); | |
| 6509 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 6510 ins_pipe(ialu_reg_imm); | |
| 6511 %} | |
| 6512 | |
| 6513 // Pointer Register Addition | |
| 6514 instruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{ | |
| 6515 match(Set dst (AddP src1 src2)); | |
| 6516 | |
| 6517 size(4); | |
| 6518 format %{ "ADD $src1,$src2,$dst" %} | |
| 6519 opcode(Assembler::add_op3, Assembler::arith_op); | |
| 6520 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 6521 ins_pipe(ialu_reg_reg); | |
| 6522 %} | |
| 6523 | |
| 6524 // Pointer Immediate Addition | |
| 6525 instruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{ | |
| 6526 match(Set dst (AddP src1 src2)); | |
| 6527 | |
| 6528 size(4); | |
| 6529 format %{ "ADD $src1,$src2,$dst" %} | |
| 6530 opcode(Assembler::add_op3, Assembler::arith_op); | |
| 6531 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 6532 ins_pipe(ialu_reg_imm); | |
| 6533 %} | |
| 6534 | |
| 6535 // Long Addition | |
| 6536 instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 6537 match(Set dst (AddL src1 src2)); | |
| 6538 | |
| 6539 size(4); | |
| 6540 format %{ "ADD $src1,$src2,$dst\t! long" %} | |
| 6541 opcode(Assembler::add_op3, Assembler::arith_op); | |
| 6542 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 6543 ins_pipe(ialu_reg_reg); | |
| 6544 %} | |
| 6545 | |
| 6546 instruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
| 6547 match(Set dst (AddL src1 con)); | |
| 6548 | |
| 6549 size(4); | |
| 6550 format %{ "ADD $src1,$con,$dst" %} | |
| 6551 opcode(Assembler::add_op3, Assembler::arith_op); | |
| 6552 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
| 6553 ins_pipe(ialu_reg_imm); | |
| 6554 %} | |
| 6555 | |
| 6556 //----------Conditional_store-------------------------------------------------- | |
| 6557 // Conditional-store of the updated heap-top. | |
| 6558 // Used during allocation of the shared heap. | |
| 6559 // Sets flags (EQ) on success. Implemented with a CASA on Sparc. | |
| 6560 | |
| 6561 // LoadP-locked. Same as a regular pointer load when used with a compare-swap | |
| 6562 instruct loadPLocked(iRegP dst, memory mem) %{ | |
| 6563 match(Set dst (LoadPLocked mem)); | |
| 6564 ins_cost(MEMORY_REF_COST); | |
| 6565 | |
| 6566 #ifndef _LP64 | |
| 6567 size(4); | |
| 6568 format %{ "LDUW $mem,$dst\t! ptr" %} | |
| 6569 opcode(Assembler::lduw_op3, 0, REGP_OP); | |
| 6570 #else | |
| 6571 format %{ "LDX $mem,$dst\t! ptr" %} | |
| 6572 opcode(Assembler::ldx_op3, 0, REGP_OP); | |
| 6573 #endif | |
| 6574 ins_encode( form3_mem_reg( mem, dst ) ); | |
| 6575 ins_pipe(iload_mem); | |
| 6576 %} | |
| 6577 | |
| 6578 // LoadL-locked. Same as a regular long load when used with a compare-swap | |
| 6579 instruct loadLLocked(iRegL dst, memory mem) %{ | |
| 6580 match(Set dst (LoadLLocked mem)); | |
| 6581 ins_cost(MEMORY_REF_COST); | |
| 6582 size(4); | |
| 6583 format %{ "LDX $mem,$dst\t! long" %} | |
| 6584 opcode(Assembler::ldx_op3); | |
| 6585 ins_encode( form3_mem_reg( mem, dst ) ); | |
| 6586 ins_pipe(iload_mem); | |
| 6587 %} | |
| 6588 | |
| 6589 instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{ | |
| 6590 match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval))); | |
| 6591 effect( KILL newval ); | |
| 6592 format %{ "CASA [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t" | |
| 6593 "CMP R_G3,$oldval\t\t! See if we made progress" %} | |
| 6594 ins_encode( enc_cas(heap_top_ptr,oldval,newval) ); | |
| 6595 ins_pipe( long_memory_op ); | |
| 6596 %} | |
| 6597 | |
| 6598 instruct storeLConditional_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ | |
| 6599 match(Set res (StoreLConditional mem_ptr (Binary oldval newval))); | |
| 6600 effect( USE mem_ptr, KILL ccr, KILL tmp1); | |
| 6601 // Marshal the register pairs into V9 64-bit registers, then do the compare-and-swap | |
| 6602 format %{ | |
| 6603 "MOV $newval,R_O7\n\t" | |
| 6604 "CASXA [$mem_ptr],$oldval,R_O7\t! If $oldval==[$mem_ptr] Then store R_O7 into [$mem_ptr], set R_O7=[$mem_ptr] in any case\n\t" | |
| 6605 "CMP $oldval,R_O7\t\t! See if we made progress\n\t" | |
| 6606 "MOV 1,$res\n\t" | |
| 6607 "MOVne xcc,R_G0,$res" | |
| 6608 %} | |
| 6609 ins_encode( enc_casx(mem_ptr, oldval, newval), | |
| 6610 enc_lflags_ne_to_boolean(res) ); | |
| 6611 ins_pipe( long_memory_op ); | |
| 6612 %} | |
| 6613 | |
| 6614 instruct storeLConditional_flags(iRegP mem_ptr, iRegL oldval, iRegL newval, flagsRegL xcc, o7RegI tmp1, immI0 zero) %{ | |
| 6615 match(Set xcc (CmpI (StoreLConditional mem_ptr (Binary oldval newval)) zero)); | |
| 6616 effect( USE mem_ptr, KILL tmp1); | |
| 6617 // Marshal the register pairs into V9 64-bit registers, then do the compare-and-swap | |
| 6618 format %{ | |
| 6619 "MOV $newval,R_O7\n\t" | |
| 6620 "CASXA [$mem_ptr],$oldval,R_O7\t! If $oldval==[$mem_ptr] Then store R_O7 into [$mem_ptr], set R_O7=[$mem_ptr] in any case\n\t" | |
| 6621 "CMP $oldval,R_O7\t\t! See if we made progress" | |
| 6622 %} | |
| 6623 ins_encode( enc_casx(mem_ptr, oldval, newval)); | |
| 6624 ins_pipe( long_memory_op ); | |
| 6625 %} | |
| 6626 | |
| 6627 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them | |
| 6628 | |
| 6629 instruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ | |
| 6630 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval))); | |
| 6631 effect( USE mem_ptr, KILL ccr, KILL tmp1); | |
| 6632 format %{ | |
| 6633 "MOV $newval,O7\n\t" | |
| 6634 "CASXA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" | |
| 6635 "CMP $oldval,O7\t\t! See if we made progress\n\t" | |
| 6636 "MOV 1,$res\n\t" | |
| 6637 "MOVne xcc,R_G0,$res" | |
| 6638 %} | |
| 6639 ins_encode( enc_casx(mem_ptr, oldval, newval), | |
| 6640 enc_lflags_ne_to_boolean(res) ); | |
| 6641 ins_pipe( long_memory_op ); | |
| 6642 %} | |
| 6643 | |
| 6644 | |
| 6645 instruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ | |
| 6646 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval))); | |
| 6647 effect( USE mem_ptr, KILL ccr, KILL tmp1); | |
| 6648 format %{ | |
| 6649 "MOV $newval,O7\n\t" | |
| 6650 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" | |
| 6651 "CMP $oldval,O7\t\t! See if we made progress\n\t" | |
| 6652 "MOV 1,$res\n\t" | |
| 6653 "MOVne icc,R_G0,$res" | |
| 6654 %} | |
| 6655 ins_encode( enc_casi(mem_ptr, oldval, newval), | |
| 6656 enc_iflags_ne_to_boolean(res) ); | |
| 6657 ins_pipe( long_memory_op ); | |
| 6658 %} | |
| 6659 | |
| 6660 instruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ | |
| 6661 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval))); | |
| 6662 effect( USE mem_ptr, KILL ccr, KILL tmp1); | |
| 6663 format %{ | |
| 6664 "MOV $newval,O7\n\t" | |
|
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6665 "CASA_PTR [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" |
| 0 | 6666 "CMP $oldval,O7\t\t! See if we made progress\n\t" |
| 6667 "MOV 1,$res\n\t" | |
| 6668 "MOVne xcc,R_G0,$res" | |
| 6669 %} | |
|
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6670 #ifdef _LP64 |
| 0 | 6671 ins_encode( enc_casx(mem_ptr, oldval, newval), |
| 6672 enc_lflags_ne_to_boolean(res) ); | |
| 6673 #else | |
|
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6674 ins_encode( enc_casi(mem_ptr, oldval, newval), |
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6675 enc_iflags_ne_to_boolean(res) ); |
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6676 #endif |
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6677 ins_pipe( long_memory_op ); |
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6678 %} |
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6679 |
|
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6680 instruct compareAndSwapN_bool(iRegP mem_ptr, iRegN oldval, iRegN newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ |
|
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6681 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval))); |
|
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6682 effect( USE mem_ptr, KILL ccr, KILL tmp1); |
| 0 | 6683 format %{ |
| 6684 "MOV $newval,O7\n\t" | |
| 6685 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" | |
| 6686 "CMP $oldval,O7\t\t! See if we made progress\n\t" | |
| 6687 "MOV 1,$res\n\t" | |
| 6688 "MOVne icc,R_G0,$res" | |
| 6689 %} | |
|
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6690 ins_encode( enc_casi(mem_ptr, oldval, newval), |
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|
6691 enc_iflags_ne_to_boolean(res) ); |
| 0 | 6692 ins_pipe( long_memory_op ); |
| 6693 %} | |
| 6694 | |
| 6695 //--------------------- | |
| 6696 // Subtraction Instructions | |
| 6697 // Register Subtraction | |
| 6698 instruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 6699 match(Set dst (SubI src1 src2)); | |
| 6700 | |
| 6701 size(4); | |
| 6702 format %{ "SUB $src1,$src2,$dst" %} | |
| 6703 opcode(Assembler::sub_op3, Assembler::arith_op); | |
| 6704 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 6705 ins_pipe(ialu_reg_reg); | |
| 6706 %} | |
| 6707 | |
| 6708 // Immediate Subtraction | |
| 6709 instruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
| 6710 match(Set dst (SubI src1 src2)); | |
| 6711 | |
| 6712 size(4); | |
| 6713 format %{ "SUB $src1,$src2,$dst" %} | |
| 6714 opcode(Assembler::sub_op3, Assembler::arith_op); | |
| 6715 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 6716 ins_pipe(ialu_reg_imm); | |
| 6717 %} | |
| 6718 | |
| 6719 instruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{ | |
| 6720 match(Set dst (SubI zero src2)); | |
| 6721 | |
| 6722 size(4); | |
| 6723 format %{ "NEG $src2,$dst" %} | |
| 6724 opcode(Assembler::sub_op3, Assembler::arith_op); | |
| 6725 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) ); | |
| 6726 ins_pipe(ialu_zero_reg); | |
| 6727 %} | |
| 6728 | |
| 6729 // Long subtraction | |
| 6730 instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 6731 match(Set dst (SubL src1 src2)); | |
| 6732 | |
| 6733 size(4); | |
| 6734 format %{ "SUB $src1,$src2,$dst\t! long" %} | |
| 6735 opcode(Assembler::sub_op3, Assembler::arith_op); | |
| 6736 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 6737 ins_pipe(ialu_reg_reg); | |
| 6738 %} | |
| 6739 | |
| 6740 // Immediate Subtraction | |
| 6741 instruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
| 6742 match(Set dst (SubL src1 con)); | |
| 6743 | |
| 6744 size(4); | |
| 6745 format %{ "SUB $src1,$con,$dst\t! long" %} | |
| 6746 opcode(Assembler::sub_op3, Assembler::arith_op); | |
| 6747 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
| 6748 ins_pipe(ialu_reg_imm); | |
| 6749 %} | |
| 6750 | |
| 6751 // Long negation | |
| 6752 instruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{ | |
| 6753 match(Set dst (SubL zero src2)); | |
| 6754 | |
| 6755 size(4); | |
| 6756 format %{ "NEG $src2,$dst\t! long" %} | |
| 6757 opcode(Assembler::sub_op3, Assembler::arith_op); | |
| 6758 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) ); | |
| 6759 ins_pipe(ialu_zero_reg); | |
| 6760 %} | |
| 6761 | |
| 6762 // Multiplication Instructions | |
| 6763 // Integer Multiplication | |
| 6764 // Register Multiplication | |
| 6765 instruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 6766 match(Set dst (MulI src1 src2)); | |
| 6767 | |
| 6768 size(4); | |
| 6769 format %{ "MULX $src1,$src2,$dst" %} | |
| 6770 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
| 6771 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 6772 ins_pipe(imul_reg_reg); | |
| 6773 %} | |
| 6774 | |
| 6775 // Immediate Multiplication | |
| 6776 instruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
| 6777 match(Set dst (MulI src1 src2)); | |
| 6778 | |
| 6779 size(4); | |
| 6780 format %{ "MULX $src1,$src2,$dst" %} | |
| 6781 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
| 6782 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 6783 ins_pipe(imul_reg_imm); | |
| 6784 %} | |
| 6785 | |
| 6786 instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 6787 match(Set dst (MulL src1 src2)); | |
| 6788 ins_cost(DEFAULT_COST * 5); | |
| 6789 size(4); | |
| 6790 format %{ "MULX $src1,$src2,$dst\t! long" %} | |
| 6791 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
| 6792 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 6793 ins_pipe(mulL_reg_reg); | |
| 6794 %} | |
| 6795 | |
| 6796 // Immediate Multiplication | |
| 6797 instruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ | |
| 6798 match(Set dst (MulL src1 src2)); | |
| 6799 ins_cost(DEFAULT_COST * 5); | |
| 6800 size(4); | |
| 6801 format %{ "MULX $src1,$src2,$dst" %} | |
| 6802 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
| 6803 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 6804 ins_pipe(mulL_reg_imm); | |
| 6805 %} | |
| 6806 | |
| 6807 // Integer Division | |
| 6808 // Register Division | |
| 6809 instruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{ | |
| 6810 match(Set dst (DivI src1 src2)); | |
| 6811 ins_cost((2+71)*DEFAULT_COST); | |
| 6812 | |
| 6813 format %{ "SRA $src2,0,$src2\n\t" | |
| 6814 "SRA $src1,0,$src1\n\t" | |
| 6815 "SDIVX $src1,$src2,$dst" %} | |
| 6816 ins_encode( idiv_reg( src1, src2, dst ) ); | |
| 6817 ins_pipe(sdiv_reg_reg); | |
| 6818 %} | |
| 6819 | |
| 6820 // Immediate Division | |
| 6821 instruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{ | |
| 6822 match(Set dst (DivI src1 src2)); | |
| 6823 ins_cost((2+71)*DEFAULT_COST); | |
| 6824 | |
| 6825 format %{ "SRA $src1,0,$src1\n\t" | |
| 6826 "SDIVX $src1,$src2,$dst" %} | |
| 6827 ins_encode( idiv_imm( src1, src2, dst ) ); | |
| 6828 ins_pipe(sdiv_reg_imm); | |
| 6829 %} | |
| 6830 | |
| 6831 //----------Div-By-10-Expansion------------------------------------------------ | |
| 6832 // Extract hi bits of a 32x32->64 bit multiply. | |
| 6833 // Expand rule only, not matched | |
| 6834 instruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{ | |
| 6835 effect( DEF dst, USE src1, USE src2 ); | |
| 6836 format %{ "MULX $src1,$src2,$dst\t! Used in div-by-10\n\t" | |
| 6837 "SRLX $dst,#32,$dst\t\t! Extract only hi word of result" %} | |
| 6838 ins_encode( enc_mul_hi(dst,src1,src2)); | |
| 6839 ins_pipe(sdiv_reg_reg); | |
| 6840 %} | |
| 6841 | |
| 6842 // Magic constant, reciprical of 10 | |
| 6843 instruct loadConI_x66666667(iRegIsafe dst) %{ | |
| 6844 effect( DEF dst ); | |
| 6845 | |
| 6846 size(8); | |
| 6847 format %{ "SET 0x66666667,$dst\t! Used in div-by-10" %} | |
| 6848 ins_encode( Set32(0x66666667, dst) ); | |
| 6849 ins_pipe(ialu_hi_lo_reg); | |
| 6850 %} | |
| 6851 | |
| 6852 // Register Shift Right Arithmatic Long by 32-63 | |
| 6853 instruct sra_31( iRegI dst, iRegI src ) %{ | |
| 6854 effect( DEF dst, USE src ); | |
| 6855 format %{ "SRA $src,31,$dst\t! Used in div-by-10" %} | |
| 6856 ins_encode( form3_rs1_rd_copysign_hi(src,dst) ); | |
| 6857 ins_pipe(ialu_reg_reg); | |
| 6858 %} | |
| 6859 | |
| 6860 // Arithmetic Shift Right by 8-bit immediate | |
| 6861 instruct sra_reg_2( iRegI dst, iRegI src ) %{ | |
| 6862 effect( DEF dst, USE src ); | |
| 6863 format %{ "SRA $src,2,$dst\t! Used in div-by-10" %} | |
| 6864 opcode(Assembler::sra_op3, Assembler::arith_op); | |
| 6865 ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) ); | |
| 6866 ins_pipe(ialu_reg_imm); | |
| 6867 %} | |
| 6868 | |
| 6869 // Integer DIV with 10 | |
| 6870 instruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{ | |
| 6871 match(Set dst (DivI src div)); | |
| 6872 ins_cost((6+6)*DEFAULT_COST); | |
| 6873 expand %{ | |
| 6874 iRegIsafe tmp1; // Killed temps; | |
| 6875 iRegIsafe tmp2; // Killed temps; | |
| 6876 iRegI tmp3; // Killed temps; | |
| 6877 iRegI tmp4; // Killed temps; | |
| 6878 loadConI_x66666667( tmp1 ); // SET 0x66666667 -> tmp1 | |
| 6879 mul_hi( tmp2, src, tmp1 ); // MUL hibits(src * tmp1) -> tmp2 | |
| 6880 sra_31( tmp3, src ); // SRA src,31 -> tmp3 | |
| 6881 sra_reg_2( tmp4, tmp2 ); // SRA tmp2,2 -> tmp4 | |
| 6882 subI_reg_reg( dst,tmp4,tmp3); // SUB tmp4 - tmp3 -> dst | |
| 6883 %} | |
| 6884 %} | |
| 6885 | |
| 6886 // Register Long Division | |
| 6887 instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 6888 match(Set dst (DivL src1 src2)); | |
| 6889 ins_cost(DEFAULT_COST*71); | |
| 6890 size(4); | |
| 6891 format %{ "SDIVX $src1,$src2,$dst\t! long" %} | |
| 6892 opcode(Assembler::sdivx_op3, Assembler::arith_op); | |
| 6893 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 6894 ins_pipe(divL_reg_reg); | |
| 6895 %} | |
| 6896 | |
| 6897 // Register Long Division | |
| 6898 instruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ | |
| 6899 match(Set dst (DivL src1 src2)); | |
| 6900 ins_cost(DEFAULT_COST*71); | |
| 6901 size(4); | |
| 6902 format %{ "SDIVX $src1,$src2,$dst\t! long" %} | |
| 6903 opcode(Assembler::sdivx_op3, Assembler::arith_op); | |
| 6904 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 6905 ins_pipe(divL_reg_imm); | |
| 6906 %} | |
| 6907 | |
| 6908 // Integer Remainder | |
| 6909 // Register Remainder | |
| 6910 instruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{ | |
| 6911 match(Set dst (ModI src1 src2)); | |
| 6912 effect( KILL ccr, KILL temp); | |
| 6913 | |
| 6914 format %{ "SREM $src1,$src2,$dst" %} | |
| 6915 ins_encode( irem_reg(src1, src2, dst, temp) ); | |
| 6916 ins_pipe(sdiv_reg_reg); | |
| 6917 %} | |
| 6918 | |
| 6919 // Immediate Remainder | |
| 6920 instruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{ | |
| 6921 match(Set dst (ModI src1 src2)); | |
| 6922 effect( KILL ccr, KILL temp); | |
| 6923 | |
| 6924 format %{ "SREM $src1,$src2,$dst" %} | |
| 6925 ins_encode( irem_imm(src1, src2, dst, temp) ); | |
| 6926 ins_pipe(sdiv_reg_imm); | |
| 6927 %} | |
| 6928 | |
| 6929 // Register Long Remainder | |
| 6930 instruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 6931 effect(DEF dst, USE src1, USE src2); | |
| 6932 size(4); | |
| 6933 format %{ "SDIVX $src1,$src2,$dst\t! long" %} | |
| 6934 opcode(Assembler::sdivx_op3, Assembler::arith_op); | |
| 6935 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 6936 ins_pipe(divL_reg_reg); | |
| 6937 %} | |
| 6938 | |
| 6939 // Register Long Division | |
| 6940 instruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{ | |
| 6941 effect(DEF dst, USE src1, USE src2); | |
| 6942 size(4); | |
| 6943 format %{ "SDIVX $src1,$src2,$dst\t! long" %} | |
| 6944 opcode(Assembler::sdivx_op3, Assembler::arith_op); | |
| 6945 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 6946 ins_pipe(divL_reg_imm); | |
| 6947 %} | |
| 6948 | |
| 6949 instruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 6950 effect(DEF dst, USE src1, USE src2); | |
| 6951 size(4); | |
| 6952 format %{ "MULX $src1,$src2,$dst\t! long" %} | |
| 6953 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
| 6954 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 6955 ins_pipe(mulL_reg_reg); | |
| 6956 %} | |
| 6957 | |
| 6958 // Immediate Multiplication | |
| 6959 instruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{ | |
| 6960 effect(DEF dst, USE src1, USE src2); | |
| 6961 size(4); | |
| 6962 format %{ "MULX $src1,$src2,$dst" %} | |
| 6963 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
| 6964 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 6965 ins_pipe(mulL_reg_imm); | |
| 6966 %} | |
| 6967 | |
| 6968 instruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 6969 effect(DEF dst, USE src1, USE src2); | |
| 6970 size(4); | |
| 6971 format %{ "SUB $src1,$src2,$dst\t! long" %} | |
| 6972 opcode(Assembler::sub_op3, Assembler::arith_op); | |
| 6973 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 6974 ins_pipe(ialu_reg_reg); | |
| 6975 %} | |
| 6976 | |
| 6977 instruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 6978 effect(DEF dst, USE src1, USE src2); | |
| 6979 size(4); | |
| 6980 format %{ "SUB $src1,$src2,$dst\t! long" %} | |
| 6981 opcode(Assembler::sub_op3, Assembler::arith_op); | |
| 6982 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 6983 ins_pipe(ialu_reg_reg); | |
| 6984 %} | |
| 6985 | |
| 6986 // Register Long Remainder | |
| 6987 instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 6988 match(Set dst (ModL src1 src2)); | |
| 6989 ins_cost(DEFAULT_COST*(71 + 6 + 1)); | |
| 6990 expand %{ | |
| 6991 iRegL tmp1; | |
| 6992 iRegL tmp2; | |
| 6993 divL_reg_reg_1(tmp1, src1, src2); | |
| 6994 mulL_reg_reg_1(tmp2, tmp1, src2); | |
| 6995 subL_reg_reg_1(dst, src1, tmp2); | |
| 6996 %} | |
| 6997 %} | |
| 6998 | |
| 6999 // Register Long Remainder | |
| 7000 instruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ | |
| 7001 match(Set dst (ModL src1 src2)); | |
| 7002 ins_cost(DEFAULT_COST*(71 + 6 + 1)); | |
| 7003 expand %{ | |
| 7004 iRegL tmp1; | |
| 7005 iRegL tmp2; | |
| 7006 divL_reg_imm13_1(tmp1, src1, src2); | |
| 7007 mulL_reg_imm13_1(tmp2, tmp1, src2); | |
| 7008 subL_reg_reg_2 (dst, src1, tmp2); | |
| 7009 %} | |
| 7010 %} | |
| 7011 | |
| 7012 // Integer Shift Instructions | |
| 7013 // Register Shift Left | |
| 7014 instruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 7015 match(Set dst (LShiftI src1 src2)); | |
| 7016 | |
| 7017 size(4); | |
| 7018 format %{ "SLL $src1,$src2,$dst" %} | |
| 7019 opcode(Assembler::sll_op3, Assembler::arith_op); | |
| 7020 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7021 ins_pipe(ialu_reg_reg); | |
| 7022 %} | |
| 7023 | |
| 7024 // Register Shift Left Immediate | |
| 7025 instruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ | |
| 7026 match(Set dst (LShiftI src1 src2)); | |
| 7027 | |
| 7028 size(4); | |
| 7029 format %{ "SLL $src1,$src2,$dst" %} | |
| 7030 opcode(Assembler::sll_op3, Assembler::arith_op); | |
| 7031 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); | |
| 7032 ins_pipe(ialu_reg_imm); | |
| 7033 %} | |
| 7034 | |
| 7035 // Register Shift Left | |
| 7036 instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ | |
| 7037 match(Set dst (LShiftL src1 src2)); | |
| 7038 | |
| 7039 size(4); | |
| 7040 format %{ "SLLX $src1,$src2,$dst" %} | |
| 7041 opcode(Assembler::sllx_op3, Assembler::arith_op); | |
| 7042 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7043 ins_pipe(ialu_reg_reg); | |
| 7044 %} | |
| 7045 | |
| 7046 // Register Shift Left Immediate | |
| 7047 instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ | |
| 7048 match(Set dst (LShiftL src1 src2)); | |
| 7049 | |
| 7050 size(4); | |
| 7051 format %{ "SLLX $src1,$src2,$dst" %} | |
| 7052 opcode(Assembler::sllx_op3, Assembler::arith_op); | |
| 7053 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); | |
| 7054 ins_pipe(ialu_reg_imm); | |
| 7055 %} | |
| 7056 | |
| 7057 // Register Arithmetic Shift Right | |
| 7058 instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 7059 match(Set dst (RShiftI src1 src2)); | |
| 7060 size(4); | |
| 7061 format %{ "SRA $src1,$src2,$dst" %} | |
| 7062 opcode(Assembler::sra_op3, Assembler::arith_op); | |
| 7063 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7064 ins_pipe(ialu_reg_reg); | |
| 7065 %} | |
| 7066 | |
| 7067 // Register Arithmetic Shift Right Immediate | |
| 7068 instruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ | |
| 7069 match(Set dst (RShiftI src1 src2)); | |
| 7070 | |
| 7071 size(4); | |
| 7072 format %{ "SRA $src1,$src2,$dst" %} | |
| 7073 opcode(Assembler::sra_op3, Assembler::arith_op); | |
| 7074 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); | |
| 7075 ins_pipe(ialu_reg_imm); | |
| 7076 %} | |
| 7077 | |
| 7078 // Register Shift Right Arithmatic Long | |
| 7079 instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ | |
| 7080 match(Set dst (RShiftL src1 src2)); | |
| 7081 | |
| 7082 size(4); | |
| 7083 format %{ "SRAX $src1,$src2,$dst" %} | |
| 7084 opcode(Assembler::srax_op3, Assembler::arith_op); | |
| 7085 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7086 ins_pipe(ialu_reg_reg); | |
| 7087 %} | |
| 7088 | |
| 7089 // Register Shift Left Immediate | |
| 7090 instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ | |
| 7091 match(Set dst (RShiftL src1 src2)); | |
| 7092 | |
| 7093 size(4); | |
| 7094 format %{ "SRAX $src1,$src2,$dst" %} | |
| 7095 opcode(Assembler::srax_op3, Assembler::arith_op); | |
| 7096 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); | |
| 7097 ins_pipe(ialu_reg_imm); | |
| 7098 %} | |
| 7099 | |
| 7100 // Register Shift Right | |
| 7101 instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 7102 match(Set dst (URShiftI src1 src2)); | |
| 7103 | |
| 7104 size(4); | |
| 7105 format %{ "SRL $src1,$src2,$dst" %} | |
| 7106 opcode(Assembler::srl_op3, Assembler::arith_op); | |
| 7107 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7108 ins_pipe(ialu_reg_reg); | |
| 7109 %} | |
| 7110 | |
| 7111 // Register Shift Right Immediate | |
| 7112 instruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ | |
| 7113 match(Set dst (URShiftI src1 src2)); | |
| 7114 | |
| 7115 size(4); | |
| 7116 format %{ "SRL $src1,$src2,$dst" %} | |
| 7117 opcode(Assembler::srl_op3, Assembler::arith_op); | |
| 7118 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); | |
| 7119 ins_pipe(ialu_reg_imm); | |
| 7120 %} | |
| 7121 | |
| 7122 // Register Shift Right | |
| 7123 instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ | |
| 7124 match(Set dst (URShiftL src1 src2)); | |
| 7125 | |
| 7126 size(4); | |
| 7127 format %{ "SRLX $src1,$src2,$dst" %} | |
| 7128 opcode(Assembler::srlx_op3, Assembler::arith_op); | |
| 7129 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7130 ins_pipe(ialu_reg_reg); | |
| 7131 %} | |
| 7132 | |
| 7133 // Register Shift Right Immediate | |
| 7134 instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ | |
| 7135 match(Set dst (URShiftL src1 src2)); | |
| 7136 | |
| 7137 size(4); | |
| 7138 format %{ "SRLX $src1,$src2,$dst" %} | |
| 7139 opcode(Assembler::srlx_op3, Assembler::arith_op); | |
| 7140 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); | |
| 7141 ins_pipe(ialu_reg_imm); | |
| 7142 %} | |
| 7143 | |
| 7144 // Register Shift Right Immediate with a CastP2X | |
| 7145 #ifdef _LP64 | |
| 7146 instruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{ | |
| 7147 match(Set dst (URShiftL (CastP2X src1) src2)); | |
| 7148 size(4); | |
| 7149 format %{ "SRLX $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %} | |
| 7150 opcode(Assembler::srlx_op3, Assembler::arith_op); | |
| 7151 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); | |
| 7152 ins_pipe(ialu_reg_imm); | |
| 7153 %} | |
| 7154 #else | |
| 7155 instruct shrP_reg_imm5(iRegI dst, iRegP src1, immU5 src2) %{ | |
| 7156 match(Set dst (URShiftI (CastP2X src1) src2)); | |
| 7157 size(4); | |
| 7158 format %{ "SRL $src1,$src2,$dst\t! Cast ptr $src1 to int and shift" %} | |
| 7159 opcode(Assembler::srl_op3, Assembler::arith_op); | |
| 7160 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); | |
| 7161 ins_pipe(ialu_reg_imm); | |
| 7162 %} | |
| 7163 #endif | |
| 7164 | |
| 7165 | |
| 7166 //----------Floating Point Arithmetic Instructions----------------------------- | |
| 7167 | |
| 7168 // Add float single precision | |
| 7169 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{ | |
| 7170 match(Set dst (AddF src1 src2)); | |
| 7171 | |
| 7172 size(4); | |
| 7173 format %{ "FADDS $src1,$src2,$dst" %} | |
| 7174 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf); | |
| 7175 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); | |
| 7176 ins_pipe(faddF_reg_reg); | |
| 7177 %} | |
| 7178 | |
| 7179 // Add float double precision | |
| 7180 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{ | |
| 7181 match(Set dst (AddD src1 src2)); | |
| 7182 | |
| 7183 size(4); | |
| 7184 format %{ "FADDD $src1,$src2,$dst" %} | |
| 7185 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf); | |
| 7186 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
| 7187 ins_pipe(faddD_reg_reg); | |
| 7188 %} | |
| 7189 | |
| 7190 // Sub float single precision | |
| 7191 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{ | |
| 7192 match(Set dst (SubF src1 src2)); | |
| 7193 | |
| 7194 size(4); | |
| 7195 format %{ "FSUBS $src1,$src2,$dst" %} | |
| 7196 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf); | |
| 7197 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); | |
| 7198 ins_pipe(faddF_reg_reg); | |
| 7199 %} | |
| 7200 | |
| 7201 // Sub float double precision | |
| 7202 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{ | |
| 7203 match(Set dst (SubD src1 src2)); | |
| 7204 | |
| 7205 size(4); | |
| 7206 format %{ "FSUBD $src1,$src2,$dst" %} | |
| 7207 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf); | |
| 7208 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
| 7209 ins_pipe(faddD_reg_reg); | |
| 7210 %} | |
| 7211 | |
| 7212 // Mul float single precision | |
| 7213 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{ | |
| 7214 match(Set dst (MulF src1 src2)); | |
| 7215 | |
| 7216 size(4); | |
| 7217 format %{ "FMULS $src1,$src2,$dst" %} | |
| 7218 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf); | |
| 7219 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); | |
| 7220 ins_pipe(fmulF_reg_reg); | |
| 7221 %} | |
| 7222 | |
| 7223 // Mul float double precision | |
| 7224 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{ | |
| 7225 match(Set dst (MulD src1 src2)); | |
| 7226 | |
| 7227 size(4); | |
| 7228 format %{ "FMULD $src1,$src2,$dst" %} | |
| 7229 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf); | |
| 7230 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
| 7231 ins_pipe(fmulD_reg_reg); | |
| 7232 %} | |
| 7233 | |
| 7234 // Div float single precision | |
| 7235 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{ | |
| 7236 match(Set dst (DivF src1 src2)); | |
| 7237 | |
| 7238 size(4); | |
| 7239 format %{ "FDIVS $src1,$src2,$dst" %} | |
| 7240 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf); | |
| 7241 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); | |
| 7242 ins_pipe(fdivF_reg_reg); | |
| 7243 %} | |
| 7244 | |
| 7245 // Div float double precision | |
| 7246 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{ | |
| 7247 match(Set dst (DivD src1 src2)); | |
| 7248 | |
| 7249 size(4); | |
| 7250 format %{ "FDIVD $src1,$src2,$dst" %} | |
| 7251 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf); | |
| 7252 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
| 7253 ins_pipe(fdivD_reg_reg); | |
| 7254 %} | |
| 7255 | |
| 7256 // Absolute float double precision | |
| 7257 instruct absD_reg(regD dst, regD src) %{ | |
| 7258 match(Set dst (AbsD src)); | |
| 7259 | |
| 7260 format %{ "FABSd $src,$dst" %} | |
| 7261 ins_encode(fabsd(dst, src)); | |
| 7262 ins_pipe(faddD_reg); | |
| 7263 %} | |
| 7264 | |
| 7265 // Absolute float single precision | |
| 7266 instruct absF_reg(regF dst, regF src) %{ | |
| 7267 match(Set dst (AbsF src)); | |
| 7268 | |
| 7269 format %{ "FABSs $src,$dst" %} | |
| 7270 ins_encode(fabss(dst, src)); | |
| 7271 ins_pipe(faddF_reg); | |
| 7272 %} | |
| 7273 | |
| 7274 instruct negF_reg(regF dst, regF src) %{ | |
| 7275 match(Set dst (NegF src)); | |
| 7276 | |
| 7277 size(4); | |
| 7278 format %{ "FNEGs $src,$dst" %} | |
| 7279 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf); | |
| 7280 ins_encode(form3_opf_rs2F_rdF(src, dst)); | |
| 7281 ins_pipe(faddF_reg); | |
| 7282 %} | |
| 7283 | |
| 7284 instruct negD_reg(regD dst, regD src) %{ | |
| 7285 match(Set dst (NegD src)); | |
| 7286 | |
| 7287 format %{ "FNEGd $src,$dst" %} | |
| 7288 ins_encode(fnegd(dst, src)); | |
| 7289 ins_pipe(faddD_reg); | |
| 7290 %} | |
| 7291 | |
| 7292 // Sqrt float double precision | |
| 7293 instruct sqrtF_reg_reg(regF dst, regF src) %{ | |
| 7294 match(Set dst (ConvD2F (SqrtD (ConvF2D src)))); | |
| 7295 | |
| 7296 size(4); | |
| 7297 format %{ "FSQRTS $src,$dst" %} | |
| 7298 ins_encode(fsqrts(dst, src)); | |
| 7299 ins_pipe(fdivF_reg_reg); | |
| 7300 %} | |
| 7301 | |
| 7302 // Sqrt float double precision | |
| 7303 instruct sqrtD_reg_reg(regD dst, regD src) %{ | |
| 7304 match(Set dst (SqrtD src)); | |
| 7305 | |
| 7306 size(4); | |
| 7307 format %{ "FSQRTD $src,$dst" %} | |
| 7308 ins_encode(fsqrtd(dst, src)); | |
| 7309 ins_pipe(fdivD_reg_reg); | |
| 7310 %} | |
| 7311 | |
| 7312 //----------Logical Instructions----------------------------------------------- | |
| 7313 // And Instructions | |
| 7314 // Register And | |
| 7315 instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 7316 match(Set dst (AndI src1 src2)); | |
| 7317 | |
| 7318 size(4); | |
| 7319 format %{ "AND $src1,$src2,$dst" %} | |
| 7320 opcode(Assembler::and_op3, Assembler::arith_op); | |
| 7321 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7322 ins_pipe(ialu_reg_reg); | |
| 7323 %} | |
| 7324 | |
| 7325 // Immediate And | |
| 7326 instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
| 7327 match(Set dst (AndI src1 src2)); | |
| 7328 | |
| 7329 size(4); | |
| 7330 format %{ "AND $src1,$src2,$dst" %} | |
| 7331 opcode(Assembler::and_op3, Assembler::arith_op); | |
| 7332 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7333 ins_pipe(ialu_reg_imm); | |
| 7334 %} | |
| 7335 | |
| 7336 // Register And Long | |
| 7337 instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7338 match(Set dst (AndL src1 src2)); | |
| 7339 | |
| 7340 ins_cost(DEFAULT_COST); | |
| 7341 size(4); | |
| 7342 format %{ "AND $src1,$src2,$dst\t! long" %} | |
| 7343 opcode(Assembler::and_op3, Assembler::arith_op); | |
| 7344 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7345 ins_pipe(ialu_reg_reg); | |
| 7346 %} | |
| 7347 | |
| 7348 instruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
| 7349 match(Set dst (AndL src1 con)); | |
| 7350 | |
| 7351 ins_cost(DEFAULT_COST); | |
| 7352 size(4); | |
| 7353 format %{ "AND $src1,$con,$dst\t! long" %} | |
| 7354 opcode(Assembler::and_op3, Assembler::arith_op); | |
| 7355 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
| 7356 ins_pipe(ialu_reg_imm); | |
| 7357 %} | |
| 7358 | |
| 7359 // Or Instructions | |
| 7360 // Register Or | |
| 7361 instruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 7362 match(Set dst (OrI src1 src2)); | |
| 7363 | |
| 7364 size(4); | |
| 7365 format %{ "OR $src1,$src2,$dst" %} | |
| 7366 opcode(Assembler::or_op3, Assembler::arith_op); | |
| 7367 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7368 ins_pipe(ialu_reg_reg); | |
| 7369 %} | |
| 7370 | |
| 7371 // Immediate Or | |
| 7372 instruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
| 7373 match(Set dst (OrI src1 src2)); | |
| 7374 | |
| 7375 size(4); | |
| 7376 format %{ "OR $src1,$src2,$dst" %} | |
| 7377 opcode(Assembler::or_op3, Assembler::arith_op); | |
| 7378 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7379 ins_pipe(ialu_reg_imm); | |
| 7380 %} | |
| 7381 | |
| 7382 // Register Or Long | |
| 7383 instruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7384 match(Set dst (OrL src1 src2)); | |
| 7385 | |
| 7386 ins_cost(DEFAULT_COST); | |
| 7387 size(4); | |
| 7388 format %{ "OR $src1,$src2,$dst\t! long" %} | |
| 7389 opcode(Assembler::or_op3, Assembler::arith_op); | |
| 7390 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7391 ins_pipe(ialu_reg_reg); | |
| 7392 %} | |
| 7393 | |
| 7394 instruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
| 7395 match(Set dst (OrL src1 con)); | |
| 7396 ins_cost(DEFAULT_COST*2); | |
| 7397 | |
| 7398 ins_cost(DEFAULT_COST); | |
| 7399 size(4); | |
| 7400 format %{ "OR $src1,$con,$dst\t! long" %} | |
| 7401 opcode(Assembler::or_op3, Assembler::arith_op); | |
| 7402 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
| 7403 ins_pipe(ialu_reg_imm); | |
| 7404 %} | |
| 7405 | |
| 7406 // Xor Instructions | |
| 7407 // Register Xor | |
| 7408 instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 7409 match(Set dst (XorI src1 src2)); | |
| 7410 | |
| 7411 size(4); | |
| 7412 format %{ "XOR $src1,$src2,$dst" %} | |
| 7413 opcode(Assembler::xor_op3, Assembler::arith_op); | |
| 7414 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7415 ins_pipe(ialu_reg_reg); | |
| 7416 %} | |
| 7417 | |
| 7418 // Immediate Xor | |
| 7419 instruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
| 7420 match(Set dst (XorI src1 src2)); | |
| 7421 | |
| 7422 size(4); | |
| 7423 format %{ "XOR $src1,$src2,$dst" %} | |
| 7424 opcode(Assembler::xor_op3, Assembler::arith_op); | |
| 7425 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7426 ins_pipe(ialu_reg_imm); | |
| 7427 %} | |
| 7428 | |
| 7429 // Register Xor Long | |
| 7430 instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7431 match(Set dst (XorL src1 src2)); | |
| 7432 | |
| 7433 ins_cost(DEFAULT_COST); | |
| 7434 size(4); | |
| 7435 format %{ "XOR $src1,$src2,$dst\t! long" %} | |
| 7436 opcode(Assembler::xor_op3, Assembler::arith_op); | |
| 7437 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7438 ins_pipe(ialu_reg_reg); | |
| 7439 %} | |
| 7440 | |
| 7441 instruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
| 7442 match(Set dst (XorL src1 con)); | |
| 7443 | |
| 7444 ins_cost(DEFAULT_COST); | |
| 7445 size(4); | |
| 7446 format %{ "XOR $src1,$con,$dst\t! long" %} | |
| 7447 opcode(Assembler::xor_op3, Assembler::arith_op); | |
| 7448 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
| 7449 ins_pipe(ialu_reg_imm); | |
| 7450 %} | |
| 7451 | |
| 7452 //----------Convert to Boolean------------------------------------------------- | |
| 7453 // Nice hack for 32-bit tests but doesn't work for | |
| 7454 // 64-bit pointers. | |
| 7455 instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{ | |
| 7456 match(Set dst (Conv2B src)); | |
| 7457 effect( KILL ccr ); | |
| 7458 ins_cost(DEFAULT_COST*2); | |
| 7459 format %{ "CMP R_G0,$src\n\t" | |
| 7460 "ADDX R_G0,0,$dst" %} | |
| 7461 ins_encode( enc_to_bool( src, dst ) ); | |
| 7462 ins_pipe(ialu_reg_ialu); | |
| 7463 %} | |
| 7464 | |
| 7465 #ifndef _LP64 | |
| 7466 instruct convP2B( iRegI dst, iRegP src, flagsReg ccr ) %{ | |
| 7467 match(Set dst (Conv2B src)); | |
| 7468 effect( KILL ccr ); | |
| 7469 ins_cost(DEFAULT_COST*2); | |
| 7470 format %{ "CMP R_G0,$src\n\t" | |
| 7471 "ADDX R_G0,0,$dst" %} | |
| 7472 ins_encode( enc_to_bool( src, dst ) ); | |
| 7473 ins_pipe(ialu_reg_ialu); | |
| 7474 %} | |
| 7475 #else | |
| 7476 instruct convP2B( iRegI dst, iRegP src ) %{ | |
| 7477 match(Set dst (Conv2B src)); | |
| 7478 ins_cost(DEFAULT_COST*2); | |
| 7479 format %{ "MOV $src,$dst\n\t" | |
| 7480 "MOVRNZ $src,1,$dst" %} | |
| 7481 ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) ); | |
| 7482 ins_pipe(ialu_clr_and_mover); | |
| 7483 %} | |
| 7484 #endif | |
| 7485 | |
| 7486 instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{ | |
| 7487 match(Set dst (CmpLTMask p q)); | |
| 7488 effect( KILL ccr ); | |
| 7489 ins_cost(DEFAULT_COST*4); | |
| 7490 format %{ "CMP $p,$q\n\t" | |
| 7491 "MOV #0,$dst\n\t" | |
| 7492 "BLT,a .+8\n\t" | |
| 7493 "MOV #-1,$dst" %} | |
| 7494 ins_encode( enc_ltmask(p,q,dst) ); | |
| 7495 ins_pipe(ialu_reg_reg_ialu); | |
| 7496 %} | |
| 7497 | |
| 7498 instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{ | |
| 7499 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))); | |
| 7500 effect(KILL ccr, TEMP tmp); | |
| 7501 ins_cost(DEFAULT_COST*3); | |
| 7502 | |
| 7503 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t" | |
| 7504 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t" | |
| 7505 "MOVl $tmp,$p\t! p' < 0 ? p'+y : p'" %} | |
| 7506 ins_encode( enc_cadd_cmpLTMask(p, q, y, tmp) ); | |
| 7507 ins_pipe( cadd_cmpltmask ); | |
| 7508 %} | |
| 7509 | |
| 7510 instruct cadd_cmpLTMask2( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{ | |
| 7511 match(Set p (AddI (SubI p q) (AndI (CmpLTMask p q) y))); | |
| 7512 effect( KILL ccr, TEMP tmp); | |
| 7513 ins_cost(DEFAULT_COST*3); | |
| 7514 | |
| 7515 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t" | |
| 7516 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t" | |
| 7517 "MOVl $tmp,$p\t! p' < 0 ? p'+y : p'" %} | |
| 7518 ins_encode( enc_cadd_cmpLTMask(p, q, y, tmp) ); | |
| 7519 ins_pipe( cadd_cmpltmask ); | |
| 7520 %} | |
| 7521 | |
| 7522 //----------Arithmetic Conversion Instructions--------------------------------- | |
| 7523 // The conversions operations are all Alpha sorted. Please keep it that way! | |
| 7524 | |
| 7525 instruct convD2F_reg(regF dst, regD src) %{ | |
| 7526 match(Set dst (ConvD2F src)); | |
| 7527 size(4); | |
| 7528 format %{ "FDTOS $src,$dst" %} | |
| 7529 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf); | |
| 7530 ins_encode(form3_opf_rs2D_rdF(src, dst)); | |
| 7531 ins_pipe(fcvtD2F); | |
| 7532 %} | |
| 7533 | |
| 7534 | |
| 7535 // Convert a double to an int in a float register. | |
| 7536 // If the double is a NAN, stuff a zero in instead. | |
| 7537 instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{ | |
| 7538 effect(DEF dst, USE src, KILL fcc0); | |
| 7539 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t" | |
| 7540 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" | |
| 7541 "FDTOI $src,$dst\t! convert in delay slot\n\t" | |
| 7542 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t" | |
| 7543 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n" | |
| 7544 "skip:" %} | |
| 7545 ins_encode(form_d2i_helper(src,dst)); | |
| 7546 ins_pipe(fcvtD2I); | |
| 7547 %} | |
| 7548 | |
| 7549 instruct convD2I_reg(stackSlotI dst, regD src) %{ | |
| 7550 match(Set dst (ConvD2I src)); | |
| 7551 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); | |
| 7552 expand %{ | |
| 7553 regF tmp; | |
| 7554 convD2I_helper(tmp, src); | |
| 7555 regF_to_stkI(dst, tmp); | |
| 7556 %} | |
| 7557 %} | |
| 7558 | |
| 7559 // Convert a double to a long in a double register. | |
| 7560 // If the double is a NAN, stuff a zero in instead. | |
| 7561 instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{ | |
| 7562 effect(DEF dst, USE src, KILL fcc0); | |
| 7563 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t" | |
| 7564 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" | |
| 7565 "FDTOX $src,$dst\t! convert in delay slot\n\t" | |
| 7566 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t" | |
| 7567 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n" | |
| 7568 "skip:" %} | |
| 7569 ins_encode(form_d2l_helper(src,dst)); | |
| 7570 ins_pipe(fcvtD2L); | |
| 7571 %} | |
| 7572 | |
| 7573 | |
| 7574 // Double to Long conversion | |
| 7575 instruct convD2L_reg(stackSlotL dst, regD src) %{ | |
| 7576 match(Set dst (ConvD2L src)); | |
| 7577 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); | |
| 7578 expand %{ | |
| 7579 regD tmp; | |
| 7580 convD2L_helper(tmp, src); | |
| 7581 regD_to_stkL(dst, tmp); | |
| 7582 %} | |
| 7583 %} | |
| 7584 | |
| 7585 | |
| 7586 instruct convF2D_reg(regD dst, regF src) %{ | |
| 7587 match(Set dst (ConvF2D src)); | |
| 7588 format %{ "FSTOD $src,$dst" %} | |
| 7589 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf); | |
| 7590 ins_encode(form3_opf_rs2F_rdD(src, dst)); | |
| 7591 ins_pipe(fcvtF2D); | |
| 7592 %} | |
| 7593 | |
| 7594 | |
| 7595 instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{ | |
| 7596 effect(DEF dst, USE src, KILL fcc0); | |
| 7597 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t" | |
| 7598 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" | |
| 7599 "FSTOI $src,$dst\t! convert in delay slot\n\t" | |
| 7600 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t" | |
| 7601 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n" | |
| 7602 "skip:" %} | |
| 7603 ins_encode(form_f2i_helper(src,dst)); | |
| 7604 ins_pipe(fcvtF2I); | |
| 7605 %} | |
| 7606 | |
| 7607 instruct convF2I_reg(stackSlotI dst, regF src) %{ | |
| 7608 match(Set dst (ConvF2I src)); | |
| 7609 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); | |
| 7610 expand %{ | |
| 7611 regF tmp; | |
| 7612 convF2I_helper(tmp, src); | |
| 7613 regF_to_stkI(dst, tmp); | |
| 7614 %} | |
| 7615 %} | |
| 7616 | |
| 7617 | |
| 7618 instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{ | |
| 7619 effect(DEF dst, USE src, KILL fcc0); | |
| 7620 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t" | |
| 7621 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" | |
| 7622 "FSTOX $src,$dst\t! convert in delay slot\n\t" | |
| 7623 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t" | |
| 7624 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n" | |
| 7625 "skip:" %} | |
| 7626 ins_encode(form_f2l_helper(src,dst)); | |
| 7627 ins_pipe(fcvtF2L); | |
| 7628 %} | |
| 7629 | |
| 7630 // Float to Long conversion | |
| 7631 instruct convF2L_reg(stackSlotL dst, regF src) %{ | |
| 7632 match(Set dst (ConvF2L src)); | |
| 7633 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); | |
| 7634 expand %{ | |
| 7635 regD tmp; | |
| 7636 convF2L_helper(tmp, src); | |
| 7637 regD_to_stkL(dst, tmp); | |
| 7638 %} | |
| 7639 %} | |
| 7640 | |
| 7641 | |
| 7642 instruct convI2D_helper(regD dst, regF tmp) %{ | |
| 7643 effect(USE tmp, DEF dst); | |
| 7644 format %{ "FITOD $tmp,$dst" %} | |
| 7645 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf); | |
| 7646 ins_encode(form3_opf_rs2F_rdD(tmp, dst)); | |
| 7647 ins_pipe(fcvtI2D); | |
| 7648 %} | |
| 7649 | |
| 7650 instruct convI2D_reg(stackSlotI src, regD dst) %{ | |
| 7651 match(Set dst (ConvI2D src)); | |
| 7652 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
| 7653 expand %{ | |
| 7654 regF tmp; | |
| 7655 stkI_to_regF( tmp, src); | |
| 7656 convI2D_helper( dst, tmp); | |
| 7657 %} | |
| 7658 %} | |
| 7659 | |
| 7660 instruct convI2D_mem( regD_low dst, memory mem ) %{ | |
| 7661 match(Set dst (ConvI2D (LoadI mem))); | |
| 7662 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
| 7663 size(8); | |
| 7664 format %{ "LDF $mem,$dst\n\t" | |
| 7665 "FITOD $dst,$dst" %} | |
| 7666 opcode(Assembler::ldf_op3, Assembler::fitod_opf); | |
| 7667 ins_encode( form3_mem_reg( mem, dst ), form3_convI2F(dst, dst)); | |
| 7668 ins_pipe(floadF_mem); | |
| 7669 %} | |
| 7670 | |
| 7671 | |
| 7672 instruct convI2F_helper(regF dst, regF tmp) %{ | |
| 7673 effect(DEF dst, USE tmp); | |
| 7674 format %{ "FITOS $tmp,$dst" %} | |
| 7675 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf); | |
| 7676 ins_encode(form3_opf_rs2F_rdF(tmp, dst)); | |
| 7677 ins_pipe(fcvtI2F); | |
| 7678 %} | |
| 7679 | |
| 7680 instruct convI2F_reg( regF dst, stackSlotI src ) %{ | |
| 7681 match(Set dst (ConvI2F src)); | |
| 7682 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
| 7683 expand %{ | |
| 7684 regF tmp; | |
| 7685 stkI_to_regF(tmp,src); | |
| 7686 convI2F_helper(dst, tmp); | |
| 7687 %} | |
| 7688 %} | |
| 7689 | |
| 7690 instruct convI2F_mem( regF dst, memory mem ) %{ | |
| 7691 match(Set dst (ConvI2F (LoadI mem))); | |
| 7692 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
| 7693 size(8); | |
| 7694 format %{ "LDF $mem,$dst\n\t" | |
| 7695 "FITOS $dst,$dst" %} | |
| 7696 opcode(Assembler::ldf_op3, Assembler::fitos_opf); | |
| 7697 ins_encode( form3_mem_reg( mem, dst ), form3_convI2F(dst, dst)); | |
| 7698 ins_pipe(floadF_mem); | |
| 7699 %} | |
| 7700 | |
| 7701 | |
| 7702 instruct convI2L_reg(iRegL dst, iRegI src) %{ | |
| 7703 match(Set dst (ConvI2L src)); | |
| 7704 size(4); | |
| 7705 format %{ "SRA $src,0,$dst\t! int->long" %} | |
| 7706 opcode(Assembler::sra_op3, Assembler::arith_op); | |
| 7707 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); | |
| 7708 ins_pipe(ialu_reg_reg); | |
| 7709 %} | |
| 7710 | |
| 7711 // Zero-extend convert int to long | |
| 7712 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{ | |
| 7713 match(Set dst (AndL (ConvI2L src) mask) ); | |
| 7714 size(4); | |
| 7715 format %{ "SRL $src,0,$dst\t! zero-extend int to long" %} | |
| 7716 opcode(Assembler::srl_op3, Assembler::arith_op); | |
| 7717 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); | |
| 7718 ins_pipe(ialu_reg_reg); | |
| 7719 %} | |
| 7720 | |
| 7721 // Zero-extend long | |
| 7722 instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{ | |
| 7723 match(Set dst (AndL src mask) ); | |
| 7724 size(4); | |
| 7725 format %{ "SRL $src,0,$dst\t! zero-extend long" %} | |
| 7726 opcode(Assembler::srl_op3, Assembler::arith_op); | |
| 7727 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); | |
| 7728 ins_pipe(ialu_reg_reg); | |
| 7729 %} | |
| 7730 | |
| 7731 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{ | |
| 7732 match(Set dst (MoveF2I src)); | |
| 7733 effect(DEF dst, USE src); | |
| 7734 ins_cost(MEMORY_REF_COST); | |
| 7735 | |
| 7736 size(4); | |
| 7737 format %{ "LDUW $src,$dst\t! MoveF2I" %} | |
| 7738 opcode(Assembler::lduw_op3); | |
| 7739 ins_encode( form3_mem_reg( src, dst ) ); | |
| 7740 ins_pipe(iload_mem); | |
| 7741 %} | |
| 7742 | |
| 7743 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{ | |
| 7744 match(Set dst (MoveI2F src)); | |
| 7745 effect(DEF dst, USE src); | |
| 7746 ins_cost(MEMORY_REF_COST); | |
| 7747 | |
| 7748 size(4); | |
| 7749 format %{ "LDF $src,$dst\t! MoveI2F" %} | |
| 7750 opcode(Assembler::ldf_op3); | |
| 7751 ins_encode(form3_mem_reg(src, dst)); | |
| 7752 ins_pipe(floadF_stk); | |
| 7753 %} | |
| 7754 | |
| 7755 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{ | |
| 7756 match(Set dst (MoveD2L src)); | |
| 7757 effect(DEF dst, USE src); | |
| 7758 ins_cost(MEMORY_REF_COST); | |
| 7759 | |
| 7760 size(4); | |
| 7761 format %{ "LDX $src,$dst\t! MoveD2L" %} | |
| 7762 opcode(Assembler::ldx_op3); | |
| 7763 ins_encode( form3_mem_reg( src, dst ) ); | |
| 7764 ins_pipe(iload_mem); | |
| 7765 %} | |
| 7766 | |
| 7767 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{ | |
| 7768 match(Set dst (MoveL2D src)); | |
| 7769 effect(DEF dst, USE src); | |
| 7770 ins_cost(MEMORY_REF_COST); | |
| 7771 | |
| 7772 size(4); | |
| 7773 format %{ "LDDF $src,$dst\t! MoveL2D" %} | |
| 7774 opcode(Assembler::lddf_op3); | |
| 7775 ins_encode(form3_mem_reg(src, dst)); | |
| 7776 ins_pipe(floadD_stk); | |
| 7777 %} | |
| 7778 | |
| 7779 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{ | |
| 7780 match(Set dst (MoveF2I src)); | |
| 7781 effect(DEF dst, USE src); | |
| 7782 ins_cost(MEMORY_REF_COST); | |
| 7783 | |
| 7784 size(4); | |
| 7785 format %{ "STF $src,$dst\t!MoveF2I" %} | |
| 7786 opcode(Assembler::stf_op3); | |
| 7787 ins_encode(form3_mem_reg(dst, src)); | |
| 7788 ins_pipe(fstoreF_stk_reg); | |
| 7789 %} | |
| 7790 | |
| 7791 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{ | |
| 7792 match(Set dst (MoveI2F src)); | |
| 7793 effect(DEF dst, USE src); | |
| 7794 ins_cost(MEMORY_REF_COST); | |
| 7795 | |
| 7796 size(4); | |
| 7797 format %{ "STW $src,$dst\t!MoveI2F" %} | |
| 7798 opcode(Assembler::stw_op3); | |
| 7799 ins_encode( form3_mem_reg( dst, src ) ); | |
| 7800 ins_pipe(istore_mem_reg); | |
| 7801 %} | |
| 7802 | |
| 7803 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{ | |
| 7804 match(Set dst (MoveD2L src)); | |
| 7805 effect(DEF dst, USE src); | |
| 7806 ins_cost(MEMORY_REF_COST); | |
| 7807 | |
| 7808 size(4); | |
| 7809 format %{ "STDF $src,$dst\t!MoveD2L" %} | |
| 7810 opcode(Assembler::stdf_op3); | |
| 7811 ins_encode(form3_mem_reg(dst, src)); | |
| 7812 ins_pipe(fstoreD_stk_reg); | |
| 7813 %} | |
| 7814 | |
| 7815 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{ | |
| 7816 match(Set dst (MoveL2D src)); | |
| 7817 effect(DEF dst, USE src); | |
| 7818 ins_cost(MEMORY_REF_COST); | |
| 7819 | |
| 7820 size(4); | |
| 7821 format %{ "STX $src,$dst\t!MoveL2D" %} | |
| 7822 opcode(Assembler::stx_op3); | |
| 7823 ins_encode( form3_mem_reg( dst, src ) ); | |
| 7824 ins_pipe(istore_mem_reg); | |
| 7825 %} | |
| 7826 | |
| 7827 | |
| 7828 //----------- | |
| 7829 // Long to Double conversion using V8 opcodes. | |
| 7830 // Still useful because cheetah traps and becomes | |
| 7831 // amazingly slow for some common numbers. | |
| 7832 | |
| 7833 // Magic constant, 0x43300000 | |
| 7834 instruct loadConI_x43300000(iRegI dst) %{ | |
| 7835 effect(DEF dst); | |
| 7836 size(4); | |
| 7837 format %{ "SETHI HI(0x43300000),$dst\t! 2^52" %} | |
| 7838 ins_encode(SetHi22(0x43300000, dst)); | |
| 7839 ins_pipe(ialu_none); | |
| 7840 %} | |
| 7841 | |
| 7842 // Magic constant, 0x41f00000 | |
| 7843 instruct loadConI_x41f00000(iRegI dst) %{ | |
| 7844 effect(DEF dst); | |
| 7845 size(4); | |
| 7846 format %{ "SETHI HI(0x41f00000),$dst\t! 2^32" %} | |
| 7847 ins_encode(SetHi22(0x41f00000, dst)); | |
| 7848 ins_pipe(ialu_none); | |
| 7849 %} | |
| 7850 | |
| 7851 // Construct a double from two float halves | |
| 7852 instruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{ | |
| 7853 effect(DEF dst, USE src1, USE src2); | |
| 7854 size(8); | |
| 7855 format %{ "FMOVS $src1.hi,$dst.hi\n\t" | |
| 7856 "FMOVS $src2.lo,$dst.lo" %} | |
| 7857 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf); | |
| 7858 ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst)); | |
| 7859 ins_pipe(faddD_reg_reg); | |
| 7860 %} | |
| 7861 | |
| 7862 // Convert integer in high half of a double register (in the lower half of | |
| 7863 // the double register file) to double | |
| 7864 instruct convI2D_regDHi_regD(regD dst, regD_low src) %{ | |
| 7865 effect(DEF dst, USE src); | |
| 7866 size(4); | |
| 7867 format %{ "FITOD $src,$dst" %} | |
| 7868 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf); | |
| 7869 ins_encode(form3_opf_rs2D_rdD(src, dst)); | |
| 7870 ins_pipe(fcvtLHi2D); | |
| 7871 %} | |
| 7872 | |
| 7873 // Add float double precision | |
| 7874 instruct addD_regD_regD(regD dst, regD src1, regD src2) %{ | |
| 7875 effect(DEF dst, USE src1, USE src2); | |
| 7876 size(4); | |
| 7877 format %{ "FADDD $src1,$src2,$dst" %} | |
| 7878 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf); | |
| 7879 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
| 7880 ins_pipe(faddD_reg_reg); | |
| 7881 %} | |
| 7882 | |
| 7883 // Sub float double precision | |
| 7884 instruct subD_regD_regD(regD dst, regD src1, regD src2) %{ | |
| 7885 effect(DEF dst, USE src1, USE src2); | |
| 7886 size(4); | |
| 7887 format %{ "FSUBD $src1,$src2,$dst" %} | |
| 7888 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf); | |
| 7889 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
| 7890 ins_pipe(faddD_reg_reg); | |
| 7891 %} | |
| 7892 | |
| 7893 // Mul float double precision | |
| 7894 instruct mulD_regD_regD(regD dst, regD src1, regD src2) %{ | |
| 7895 effect(DEF dst, USE src1, USE src2); | |
| 7896 size(4); | |
| 7897 format %{ "FMULD $src1,$src2,$dst" %} | |
| 7898 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf); | |
| 7899 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
| 7900 ins_pipe(fmulD_reg_reg); | |
| 7901 %} | |
| 7902 | |
| 7903 instruct convL2D_reg_slow_fxtof(regD dst, stackSlotL src) %{ | |
| 7904 match(Set dst (ConvL2D src)); | |
| 7905 ins_cost(DEFAULT_COST*8 + MEMORY_REF_COST*6); | |
| 7906 | |
| 7907 expand %{ | |
| 7908 regD_low tmpsrc; | |
| 7909 iRegI ix43300000; | |
| 7910 iRegI ix41f00000; | |
| 7911 stackSlotL lx43300000; | |
| 7912 stackSlotL lx41f00000; | |
| 7913 regD_low dx43300000; | |
| 7914 regD dx41f00000; | |
| 7915 regD tmp1; | |
| 7916 regD_low tmp2; | |
| 7917 regD tmp3; | |
| 7918 regD tmp4; | |
| 7919 | |
| 7920 stkL_to_regD(tmpsrc, src); | |
| 7921 | |
| 7922 loadConI_x43300000(ix43300000); | |
| 7923 loadConI_x41f00000(ix41f00000); | |
| 7924 regI_to_stkLHi(lx43300000, ix43300000); | |
| 7925 regI_to_stkLHi(lx41f00000, ix41f00000); | |
| 7926 stkL_to_regD(dx43300000, lx43300000); | |
| 7927 stkL_to_regD(dx41f00000, lx41f00000); | |
| 7928 | |
| 7929 convI2D_regDHi_regD(tmp1, tmpsrc); | |
| 7930 regDHi_regDLo_to_regD(tmp2, dx43300000, tmpsrc); | |
| 7931 subD_regD_regD(tmp3, tmp2, dx43300000); | |
| 7932 mulD_regD_regD(tmp4, tmp1, dx41f00000); | |
| 7933 addD_regD_regD(dst, tmp3, tmp4); | |
| 7934 %} | |
| 7935 %} | |
| 7936 | |
| 7937 // Long to Double conversion using fast fxtof | |
| 7938 instruct convL2D_helper(regD dst, regD tmp) %{ | |
| 7939 effect(DEF dst, USE tmp); | |
| 7940 size(4); | |
| 7941 format %{ "FXTOD $tmp,$dst" %} | |
| 7942 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf); | |
| 7943 ins_encode(form3_opf_rs2D_rdD(tmp, dst)); | |
| 7944 ins_pipe(fcvtL2D); | |
| 7945 %} | |
| 7946 | |
| 7947 instruct convL2D_reg_fast_fxtof(regD dst, stackSlotL src) %{ | |
| 7948 predicate(VM_Version::has_fast_fxtof()); | |
| 7949 match(Set dst (ConvL2D src)); | |
| 7950 ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST); | |
| 7951 expand %{ | |
| 7952 regD tmp; | |
| 7953 stkL_to_regD(tmp, src); | |
| 7954 convL2D_helper(dst, tmp); | |
| 7955 %} | |
| 7956 %} | |
| 7957 | |
| 7958 //----------- | |
| 7959 // Long to Float conversion using V8 opcodes. | |
| 7960 // Still useful because cheetah traps and becomes | |
| 7961 // amazingly slow for some common numbers. | |
| 7962 | |
| 7963 // Long to Float conversion using fast fxtof | |
| 7964 instruct convL2F_helper(regF dst, regD tmp) %{ | |
| 7965 effect(DEF dst, USE tmp); | |
| 7966 size(4); | |
| 7967 format %{ "FXTOS $tmp,$dst" %} | |
| 7968 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf); | |
| 7969 ins_encode(form3_opf_rs2D_rdF(tmp, dst)); | |
| 7970 ins_pipe(fcvtL2F); | |
| 7971 %} | |
| 7972 | |
| 7973 instruct convL2F_reg_fast_fxtof(regF dst, stackSlotL src) %{ | |
| 7974 match(Set dst (ConvL2F src)); | |
| 7975 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
| 7976 expand %{ | |
| 7977 regD tmp; | |
| 7978 stkL_to_regD(tmp, src); | |
| 7979 convL2F_helper(dst, tmp); | |
| 7980 %} | |
| 7981 %} | |
| 7982 //----------- | |
| 7983 | |
| 7984 instruct convL2I_reg(iRegI dst, iRegL src) %{ | |
| 7985 match(Set dst (ConvL2I src)); | |
| 7986 #ifndef _LP64 | |
| 7987 format %{ "MOV $src.lo,$dst\t! long->int" %} | |
| 7988 ins_encode( form3_g0_rs2_rd_move_lo2( src, dst ) ); | |
| 7989 ins_pipe(ialu_move_reg_I_to_L); | |
| 7990 #else | |
| 7991 size(4); | |
| 7992 format %{ "SRA $src,R_G0,$dst\t! long->int" %} | |
| 7993 ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) ); | |
| 7994 ins_pipe(ialu_reg); | |
| 7995 #endif | |
| 7996 %} | |
| 7997 | |
| 7998 // Register Shift Right Immediate | |
| 7999 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{ | |
| 8000 match(Set dst (ConvL2I (RShiftL src cnt))); | |
| 8001 | |
| 8002 size(4); | |
| 8003 format %{ "SRAX $src,$cnt,$dst" %} | |
| 8004 opcode(Assembler::srax_op3, Assembler::arith_op); | |
| 8005 ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) ); | |
| 8006 ins_pipe(ialu_reg_imm); | |
| 8007 %} | |
| 8008 | |
| 8009 // Replicate scalar to packed byte values in Double register | |
| 8010 instruct Repl8B_reg_helper(iRegL dst, iRegI src) %{ | |
| 8011 effect(DEF dst, USE src); | |
| 8012 format %{ "SLLX $src,56,$dst\n\t" | |
| 8013 "SRLX $dst, 8,O7\n\t" | |
| 8014 "OR $dst,O7,$dst\n\t" | |
| 8015 "SRLX $dst,16,O7\n\t" | |
| 8016 "OR $dst,O7,$dst\n\t" | |
| 8017 "SRLX $dst,32,O7\n\t" | |
| 8018 "OR $dst,O7,$dst\t! replicate8B" %} | |
| 8019 ins_encode( enc_repl8b(src, dst)); | |
| 8020 ins_pipe(ialu_reg); | |
| 8021 %} | |
| 8022 | |
| 8023 // Replicate scalar to packed byte values in Double register | |
| 8024 instruct Repl8B_reg(stackSlotD dst, iRegI src) %{ | |
| 8025 match(Set dst (Replicate8B src)); | |
| 8026 expand %{ | |
| 8027 iRegL tmp; | |
| 8028 Repl8B_reg_helper(tmp, src); | |
| 8029 regL_to_stkD(dst, tmp); | |
| 8030 %} | |
| 8031 %} | |
| 8032 | |
| 8033 // Replicate scalar constant to packed byte values in Double register | |
| 8034 instruct Repl8B_immI(regD dst, immI13 src, o7RegP tmp) %{ | |
| 8035 match(Set dst (Replicate8B src)); | |
| 8036 #ifdef _LP64 | |
| 8037 size(36); | |
| 8038 #else | |
| 8039 size(8); | |
| 8040 #endif | |
| 8041 format %{ "SETHI hi(&Repl8($src)),$tmp\t!get Repl8B($src) from table\n\t" | |
| 8042 "LDDF [$tmp+lo(&Repl8($src))],$dst" %} | |
| 8043 ins_encode( LdReplImmI(src, dst, tmp, (8), (1)) ); | |
| 8044 ins_pipe(loadConFD); | |
| 8045 %} | |
| 8046 | |
| 8047 // Replicate scalar to packed char values into stack slot | |
| 8048 instruct Repl4C_reg_helper(iRegL dst, iRegI src) %{ | |
| 8049 effect(DEF dst, USE src); | |
| 8050 format %{ "SLLX $src,48,$dst\n\t" | |
| 8051 "SRLX $dst,16,O7\n\t" | |
| 8052 "OR $dst,O7,$dst\n\t" | |
| 8053 "SRLX $dst,32,O7\n\t" | |
| 8054 "OR $dst,O7,$dst\t! replicate4C" %} | |
| 8055 ins_encode( enc_repl4s(src, dst) ); | |
| 8056 ins_pipe(ialu_reg); | |
| 8057 %} | |
| 8058 | |
| 8059 // Replicate scalar to packed char values into stack slot | |
| 8060 instruct Repl4C_reg(stackSlotD dst, iRegI src) %{ | |
| 8061 match(Set dst (Replicate4C src)); | |
| 8062 expand %{ | |
| 8063 iRegL tmp; | |
| 8064 Repl4C_reg_helper(tmp, src); | |
| 8065 regL_to_stkD(dst, tmp); | |
| 8066 %} | |
| 8067 %} | |
| 8068 | |
| 8069 // Replicate scalar constant to packed char values in Double register | |
| 8070 instruct Repl4C_immI(regD dst, immI src, o7RegP tmp) %{ | |
| 8071 match(Set dst (Replicate4C src)); | |
| 8072 #ifdef _LP64 | |
| 8073 size(36); | |
| 8074 #else | |
| 8075 size(8); | |
| 8076 #endif | |
| 8077 format %{ "SETHI hi(&Repl4($src)),$tmp\t!get Repl4C($src) from table\n\t" | |
| 8078 "LDDF [$tmp+lo(&Repl4($src))],$dst" %} | |
| 8079 ins_encode( LdReplImmI(src, dst, tmp, (4), (2)) ); | |
| 8080 ins_pipe(loadConFD); | |
| 8081 %} | |
| 8082 | |
| 8083 // Replicate scalar to packed short values into stack slot | |
| 8084 instruct Repl4S_reg_helper(iRegL dst, iRegI src) %{ | |
| 8085 effect(DEF dst, USE src); | |
| 8086 format %{ "SLLX $src,48,$dst\n\t" | |
| 8087 "SRLX $dst,16,O7\n\t" | |
| 8088 "OR $dst,O7,$dst\n\t" | |
| 8089 "SRLX $dst,32,O7\n\t" | |
| 8090 "OR $dst,O7,$dst\t! replicate4S" %} | |
| 8091 ins_encode( enc_repl4s(src, dst) ); | |
| 8092 ins_pipe(ialu_reg); | |
| 8093 %} | |
| 8094 | |
| 8095 // Replicate scalar to packed short values into stack slot | |
| 8096 instruct Repl4S_reg(stackSlotD dst, iRegI src) %{ | |
| 8097 match(Set dst (Replicate4S src)); | |
| 8098 expand %{ | |
| 8099 iRegL tmp; | |
| 8100 Repl4S_reg_helper(tmp, src); | |
| 8101 regL_to_stkD(dst, tmp); | |
| 8102 %} | |
| 8103 %} | |
| 8104 | |
| 8105 // Replicate scalar constant to packed short values in Double register | |
| 8106 instruct Repl4S_immI(regD dst, immI src, o7RegP tmp) %{ | |
| 8107 match(Set dst (Replicate4S src)); | |
| 8108 #ifdef _LP64 | |
| 8109 size(36); | |
| 8110 #else | |
| 8111 size(8); | |
| 8112 #endif | |
| 8113 format %{ "SETHI hi(&Repl4($src)),$tmp\t!get Repl4S($src) from table\n\t" | |
| 8114 "LDDF [$tmp+lo(&Repl4($src))],$dst" %} | |
| 8115 ins_encode( LdReplImmI(src, dst, tmp, (4), (2)) ); | |
| 8116 ins_pipe(loadConFD); | |
| 8117 %} | |
| 8118 | |
| 8119 // Replicate scalar to packed int values in Double register | |
| 8120 instruct Repl2I_reg_helper(iRegL dst, iRegI src) %{ | |
| 8121 effect(DEF dst, USE src); | |
| 8122 format %{ "SLLX $src,32,$dst\n\t" | |
| 8123 "SRLX $dst,32,O7\n\t" | |
| 8124 "OR $dst,O7,$dst\t! replicate2I" %} | |
| 8125 ins_encode( enc_repl2i(src, dst)); | |
| 8126 ins_pipe(ialu_reg); | |
| 8127 %} | |
| 8128 | |
| 8129 // Replicate scalar to packed int values in Double register | |
| 8130 instruct Repl2I_reg(stackSlotD dst, iRegI src) %{ | |
| 8131 match(Set dst (Replicate2I src)); | |
| 8132 expand %{ | |
| 8133 iRegL tmp; | |
| 8134 Repl2I_reg_helper(tmp, src); | |
| 8135 regL_to_stkD(dst, tmp); | |
| 8136 %} | |
| 8137 %} | |
| 8138 | |
| 8139 // Replicate scalar zero constant to packed int values in Double register | |
| 8140 instruct Repl2I_immI(regD dst, immI src, o7RegP tmp) %{ | |
| 8141 match(Set dst (Replicate2I src)); | |
| 8142 #ifdef _LP64 | |
| 8143 size(36); | |
| 8144 #else | |
| 8145 size(8); | |
| 8146 #endif | |
| 8147 format %{ "SETHI hi(&Repl2($src)),$tmp\t!get Repl2I($src) from table\n\t" | |
| 8148 "LDDF [$tmp+lo(&Repl2($src))],$dst" %} | |
| 8149 ins_encode( LdReplImmI(src, dst, tmp, (2), (4)) ); | |
| 8150 ins_pipe(loadConFD); | |
| 8151 %} | |
| 8152 | |
| 8153 //----------Control Flow Instructions------------------------------------------ | |
| 8154 // Compare Instructions | |
| 8155 // Compare Integers | |
| 8156 instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{ | |
| 8157 match(Set icc (CmpI op1 op2)); | |
| 8158 effect( DEF icc, USE op1, USE op2 ); | |
| 8159 | |
| 8160 size(4); | |
| 8161 format %{ "CMP $op1,$op2" %} | |
| 8162 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
| 8163 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
| 8164 ins_pipe(ialu_cconly_reg_reg); | |
| 8165 %} | |
| 8166 | |
| 8167 instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{ | |
| 8168 match(Set icc (CmpU op1 op2)); | |
| 8169 | |
| 8170 size(4); | |
| 8171 format %{ "CMP $op1,$op2\t! unsigned" %} | |
| 8172 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
| 8173 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
| 8174 ins_pipe(ialu_cconly_reg_reg); | |
| 8175 %} | |
| 8176 | |
| 8177 instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{ | |
| 8178 match(Set icc (CmpI op1 op2)); | |
| 8179 effect( DEF icc, USE op1 ); | |
| 8180 | |
| 8181 size(4); | |
| 8182 format %{ "CMP $op1,$op2" %} | |
| 8183 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
| 8184 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); | |
| 8185 ins_pipe(ialu_cconly_reg_imm); | |
| 8186 %} | |
| 8187 | |
| 8188 instruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{ | |
| 8189 match(Set icc (CmpI (AndI op1 op2) zero)); | |
| 8190 | |
| 8191 size(4); | |
| 8192 format %{ "BTST $op2,$op1" %} | |
| 8193 opcode(Assembler::andcc_op3, Assembler::arith_op); | |
| 8194 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
| 8195 ins_pipe(ialu_cconly_reg_reg_zero); | |
| 8196 %} | |
| 8197 | |
| 8198 instruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{ | |
| 8199 match(Set icc (CmpI (AndI op1 op2) zero)); | |
| 8200 | |
| 8201 size(4); | |
| 8202 format %{ "BTST $op2,$op1" %} | |
| 8203 opcode(Assembler::andcc_op3, Assembler::arith_op); | |
| 8204 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); | |
| 8205 ins_pipe(ialu_cconly_reg_imm_zero); | |
| 8206 %} | |
| 8207 | |
| 8208 instruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{ | |
| 8209 match(Set xcc (CmpL op1 op2)); | |
| 8210 effect( DEF xcc, USE op1, USE op2 ); | |
| 8211 | |
| 8212 size(4); | |
| 8213 format %{ "CMP $op1,$op2\t\t! long" %} | |
| 8214 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
| 8215 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
| 8216 ins_pipe(ialu_cconly_reg_reg); | |
| 8217 %} | |
| 8218 | |
| 8219 instruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{ | |
| 8220 match(Set xcc (CmpL op1 con)); | |
| 8221 effect( DEF xcc, USE op1, USE con ); | |
| 8222 | |
| 8223 size(4); | |
| 8224 format %{ "CMP $op1,$con\t\t! long" %} | |
| 8225 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
| 8226 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) ); | |
| 8227 ins_pipe(ialu_cconly_reg_reg); | |
| 8228 %} | |
| 8229 | |
| 8230 instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{ | |
| 8231 match(Set xcc (CmpL (AndL op1 op2) zero)); | |
| 8232 effect( DEF xcc, USE op1, USE op2 ); | |
| 8233 | |
| 8234 size(4); | |
| 8235 format %{ "BTST $op1,$op2\t\t! long" %} | |
| 8236 opcode(Assembler::andcc_op3, Assembler::arith_op); | |
| 8237 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
| 8238 ins_pipe(ialu_cconly_reg_reg); | |
| 8239 %} | |
| 8240 | |
| 8241 // useful for checking the alignment of a pointer: | |
| 8242 instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{ | |
| 8243 match(Set xcc (CmpL (AndL op1 con) zero)); | |
| 8244 effect( DEF xcc, USE op1, USE con ); | |
| 8245 | |
| 8246 size(4); | |
| 8247 format %{ "BTST $op1,$con\t\t! long" %} | |
| 8248 opcode(Assembler::andcc_op3, Assembler::arith_op); | |
| 8249 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) ); | |
| 8250 ins_pipe(ialu_cconly_reg_reg); | |
| 8251 %} | |
| 8252 | |
| 8253 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU13 op2 ) %{ | |
| 8254 match(Set icc (CmpU op1 op2)); | |
| 8255 | |
| 8256 size(4); | |
| 8257 format %{ "CMP $op1,$op2\t! unsigned" %} | |
| 8258 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
| 8259 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); | |
| 8260 ins_pipe(ialu_cconly_reg_imm); | |
| 8261 %} | |
| 8262 | |
| 8263 // Compare Pointers | |
| 8264 instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{ | |
| 8265 match(Set pcc (CmpP op1 op2)); | |
| 8266 | |
| 8267 size(4); | |
| 8268 format %{ "CMP $op1,$op2\t! ptr" %} | |
| 8269 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
| 8270 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
| 8271 ins_pipe(ialu_cconly_reg_reg); | |
| 8272 %} | |
| 8273 | |
| 8274 instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{ | |
| 8275 match(Set pcc (CmpP op1 op2)); | |
| 8276 | |
| 8277 size(4); | |
| 8278 format %{ "CMP $op1,$op2\t! ptr" %} | |
| 8279 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
| 8280 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); | |
| 8281 ins_pipe(ialu_cconly_reg_imm); | |
| 8282 %} | |
| 8283 | |
|
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8284 // Compare Narrow oops |
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8285 instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{ |
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8286 match(Set icc (CmpN op1 op2)); |
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8287 |
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8288 size(4); |
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8289 format %{ "CMP $op1,$op2\t! compressed ptr" %} |
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8290 opcode(Assembler::subcc_op3, Assembler::arith_op); |
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8291 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); |
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8292 ins_pipe(ialu_cconly_reg_reg); |
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8293 %} |
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8294 |
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8295 instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{ |
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8296 match(Set icc (CmpN op1 op2)); |
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8297 |
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8298 size(4); |
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8299 format %{ "CMP $op1,$op2\t! compressed ptr" %} |
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8300 opcode(Assembler::subcc_op3, Assembler::arith_op); |
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8301 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); |
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8302 ins_pipe(ialu_cconly_reg_imm); |
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8303 %} |
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8304 |
| 0 | 8305 //----------Max and Min-------------------------------------------------------- |
| 8306 // Min Instructions | |
| 8307 // Conditional move for min | |
| 8308 instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{ | |
| 8309 effect( USE_DEF op2, USE op1, USE icc ); | |
| 8310 | |
| 8311 size(4); | |
| 8312 format %{ "MOVlt icc,$op1,$op2\t! min" %} | |
| 8313 opcode(Assembler::less); | |
| 8314 ins_encode( enc_cmov_reg_minmax(op2,op1) ); | |
| 8315 ins_pipe(ialu_reg_flags); | |
| 8316 %} | |
| 8317 | |
| 8318 // Min Register with Register. | |
| 8319 instruct minI_eReg(iRegI op1, iRegI op2) %{ | |
| 8320 match(Set op2 (MinI op1 op2)); | |
| 8321 ins_cost(DEFAULT_COST*2); | |
| 8322 expand %{ | |
| 8323 flagsReg icc; | |
| 8324 compI_iReg(icc,op1,op2); | |
| 8325 cmovI_reg_lt(op2,op1,icc); | |
| 8326 %} | |
| 8327 %} | |
| 8328 | |
| 8329 // Max Instructions | |
| 8330 // Conditional move for max | |
| 8331 instruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{ | |
| 8332 effect( USE_DEF op2, USE op1, USE icc ); | |
| 8333 format %{ "MOVgt icc,$op1,$op2\t! max" %} | |
| 8334 opcode(Assembler::greater); | |
| 8335 ins_encode( enc_cmov_reg_minmax(op2,op1) ); | |
| 8336 ins_pipe(ialu_reg_flags); | |
| 8337 %} | |
| 8338 | |
| 8339 // Max Register with Register | |
| 8340 instruct maxI_eReg(iRegI op1, iRegI op2) %{ | |
| 8341 match(Set op2 (MaxI op1 op2)); | |
| 8342 ins_cost(DEFAULT_COST*2); | |
| 8343 expand %{ | |
| 8344 flagsReg icc; | |
| 8345 compI_iReg(icc,op1,op2); | |
| 8346 cmovI_reg_gt(op2,op1,icc); | |
| 8347 %} | |
| 8348 %} | |
| 8349 | |
| 8350 | |
| 8351 //----------Float Compares---------------------------------------------------- | |
| 8352 // Compare floating, generate condition code | |
| 8353 instruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{ | |
| 8354 match(Set fcc (CmpF src1 src2)); | |
| 8355 | |
| 8356 size(4); | |
| 8357 format %{ "FCMPs $fcc,$src1,$src2" %} | |
| 8358 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf); | |
| 8359 ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) ); | |
| 8360 ins_pipe(faddF_fcc_reg_reg_zero); | |
| 8361 %} | |
| 8362 | |
| 8363 instruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{ | |
| 8364 match(Set fcc (CmpD src1 src2)); | |
| 8365 | |
| 8366 size(4); | |
| 8367 format %{ "FCMPd $fcc,$src1,$src2" %} | |
| 8368 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf); | |
| 8369 ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) ); | |
| 8370 ins_pipe(faddD_fcc_reg_reg_zero); | |
| 8371 %} | |
| 8372 | |
| 8373 | |
| 8374 // Compare floating, generate -1,0,1 | |
| 8375 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{ | |
| 8376 match(Set dst (CmpF3 src1 src2)); | |
| 8377 effect(KILL fcc0); | |
| 8378 ins_cost(DEFAULT_COST*3+BRANCH_COST*3); | |
| 8379 format %{ "fcmpl $dst,$src1,$src2" %} | |
| 8380 // Primary = float | |
| 8381 opcode( true ); | |
| 8382 ins_encode( floating_cmp( dst, src1, src2 ) ); | |
| 8383 ins_pipe( floating_cmp ); | |
| 8384 %} | |
| 8385 | |
| 8386 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{ | |
| 8387 match(Set dst (CmpD3 src1 src2)); | |
| 8388 effect(KILL fcc0); | |
| 8389 ins_cost(DEFAULT_COST*3+BRANCH_COST*3); | |
| 8390 format %{ "dcmpl $dst,$src1,$src2" %} | |
| 8391 // Primary = double (not float) | |
| 8392 opcode( false ); | |
| 8393 ins_encode( floating_cmp( dst, src1, src2 ) ); | |
| 8394 ins_pipe( floating_cmp ); | |
| 8395 %} | |
| 8396 | |
| 8397 //----------Branches--------------------------------------------------------- | |
| 8398 // Jump | |
| 8399 // (compare 'operand indIndex' and 'instruct addP_reg_reg' above) | |
| 8400 instruct jumpXtnd(iRegX switch_val, o7RegI table) %{ | |
| 8401 match(Jump switch_val); | |
| 8402 | |
| 8403 ins_cost(350); | |
| 8404 | |
| 8405 format %{ "SETHI [hi(table_base)],O7\n\t" | |
| 8406 "ADD O7, lo(table_base), O7\n\t" | |
| 8407 "LD [O7+$switch_val], O7\n\t" | |
| 8408 "JUMP O7" | |
| 8409 %} | |
| 8410 ins_encode( jump_enc( switch_val, table) ); | |
| 8411 ins_pc_relative(1); | |
| 8412 ins_pipe(ialu_reg_reg); | |
| 8413 %} | |
| 8414 | |
| 8415 // Direct Branch. Use V8 version with longer range. | |
| 8416 instruct branch(label labl) %{ | |
| 8417 match(Goto); | |
| 8418 effect(USE labl); | |
| 8419 | |
| 8420 size(8); | |
| 8421 ins_cost(BRANCH_COST); | |
| 8422 format %{ "BA $labl" %} | |
| 8423 // Prim = bits 24-22, Secnd = bits 31-30, Tert = cond | |
| 8424 opcode(Assembler::br_op2, Assembler::branch_op, Assembler::always); | |
| 8425 ins_encode( enc_ba( labl ) ); | |
| 8426 ins_pc_relative(1); | |
| 8427 ins_pipe(br); | |
| 8428 %} | |
| 8429 | |
| 8430 // Conditional Direct Branch | |
| 8431 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{ | |
| 8432 match(If cmp icc); | |
| 8433 effect(USE labl); | |
| 8434 | |
| 8435 size(8); | |
| 8436 ins_cost(BRANCH_COST); | |
| 8437 format %{ "BP$cmp $icc,$labl" %} | |
| 8438 // Prim = bits 24-22, Secnd = bits 31-30 | |
| 8439 ins_encode( enc_bp( labl, cmp, icc ) ); | |
| 8440 ins_pc_relative(1); | |
| 8441 ins_pipe(br_cc); | |
| 8442 %} | |
| 8443 | |
| 8444 // Branch-on-register tests all 64 bits. We assume that values | |
| 8445 // in 64-bit registers always remains zero or sign extended | |
| 8446 // unless our code munges the high bits. Interrupts can chop | |
| 8447 // the high order bits to zero or sign at any time. | |
| 8448 instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{ | |
| 8449 match(If cmp (CmpI op1 zero)); | |
| 8450 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); | |
| 8451 effect(USE labl); | |
| 8452 | |
| 8453 size(8); | |
| 8454 ins_cost(BRANCH_COST); | |
| 8455 format %{ "BR$cmp $op1,$labl" %} | |
| 8456 ins_encode( enc_bpr( labl, cmp, op1 ) ); | |
| 8457 ins_pc_relative(1); | |
| 8458 ins_pipe(br_reg); | |
| 8459 %} | |
| 8460 | |
| 8461 instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{ | |
| 8462 match(If cmp (CmpP op1 null)); | |
| 8463 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); | |
| 8464 effect(USE labl); | |
| 8465 | |
| 8466 size(8); | |
| 8467 ins_cost(BRANCH_COST); | |
| 8468 format %{ "BR$cmp $op1,$labl" %} | |
| 8469 ins_encode( enc_bpr( labl, cmp, op1 ) ); | |
| 8470 ins_pc_relative(1); | |
| 8471 ins_pipe(br_reg); | |
| 8472 %} | |
| 8473 | |
| 8474 instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{ | |
| 8475 match(If cmp (CmpL op1 zero)); | |
| 8476 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); | |
| 8477 effect(USE labl); | |
| 8478 | |
| 8479 size(8); | |
| 8480 ins_cost(BRANCH_COST); | |
| 8481 format %{ "BR$cmp $op1,$labl" %} | |
| 8482 ins_encode( enc_bpr( labl, cmp, op1 ) ); | |
| 8483 ins_pc_relative(1); | |
| 8484 ins_pipe(br_reg); | |
| 8485 %} | |
| 8486 | |
| 8487 instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{ | |
| 8488 match(If cmp icc); | |
| 8489 effect(USE labl); | |
| 8490 | |
| 8491 format %{ "BP$cmp $icc,$labl" %} | |
| 8492 // Prim = bits 24-22, Secnd = bits 31-30 | |
| 8493 ins_encode( enc_bp( labl, cmp, icc ) ); | |
| 8494 ins_pc_relative(1); | |
| 8495 ins_pipe(br_cc); | |
| 8496 %} | |
| 8497 | |
| 8498 instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{ | |
| 8499 match(If cmp pcc); | |
| 8500 effect(USE labl); | |
| 8501 | |
| 8502 size(8); | |
| 8503 ins_cost(BRANCH_COST); | |
| 8504 format %{ "BP$cmp $pcc,$labl" %} | |
| 8505 // Prim = bits 24-22, Secnd = bits 31-30 | |
| 8506 ins_encode( enc_bpx( labl, cmp, pcc ) ); | |
| 8507 ins_pc_relative(1); | |
| 8508 ins_pipe(br_cc); | |
| 8509 %} | |
| 8510 | |
| 8511 instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{ | |
| 8512 match(If cmp fcc); | |
| 8513 effect(USE labl); | |
| 8514 | |
| 8515 size(8); | |
| 8516 ins_cost(BRANCH_COST); | |
| 8517 format %{ "FBP$cmp $fcc,$labl" %} | |
| 8518 // Prim = bits 24-22, Secnd = bits 31-30 | |
| 8519 ins_encode( enc_fbp( labl, cmp, fcc ) ); | |
| 8520 ins_pc_relative(1); | |
| 8521 ins_pipe(br_fcc); | |
| 8522 %} | |
| 8523 | |
| 8524 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{ | |
| 8525 match(CountedLoopEnd cmp icc); | |
| 8526 effect(USE labl); | |
| 8527 | |
| 8528 size(8); | |
| 8529 ins_cost(BRANCH_COST); | |
| 8530 format %{ "BP$cmp $icc,$labl\t! Loop end" %} | |
| 8531 // Prim = bits 24-22, Secnd = bits 31-30 | |
| 8532 ins_encode( enc_bp( labl, cmp, icc ) ); | |
| 8533 ins_pc_relative(1); | |
| 8534 ins_pipe(br_cc); | |
| 8535 %} | |
| 8536 | |
| 8537 instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{ | |
| 8538 match(CountedLoopEnd cmp icc); | |
| 8539 effect(USE labl); | |
| 8540 | |
| 8541 size(8); | |
| 8542 ins_cost(BRANCH_COST); | |
| 8543 format %{ "BP$cmp $icc,$labl\t! Loop end" %} | |
| 8544 // Prim = bits 24-22, Secnd = bits 31-30 | |
| 8545 ins_encode( enc_bp( labl, cmp, icc ) ); | |
| 8546 ins_pc_relative(1); | |
| 8547 ins_pipe(br_cc); | |
| 8548 %} | |
| 8549 | |
| 8550 // ============================================================================ | |
| 8551 // Long Compare | |
| 8552 // | |
| 8553 // Currently we hold longs in 2 registers. Comparing such values efficiently | |
| 8554 // is tricky. The flavor of compare used depends on whether we are testing | |
| 8555 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit. | |
| 8556 // The GE test is the negated LT test. The LE test can be had by commuting | |
| 8557 // the operands (yielding a GE test) and then negating; negate again for the | |
| 8558 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the | |
| 8559 // NE test is negated from that. | |
| 8560 | |
| 8561 // Due to a shortcoming in the ADLC, it mixes up expressions like: | |
| 8562 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the | |
| 8563 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections | |
| 8564 // are collapsed internally in the ADLC's dfa-gen code. The match for | |
| 8565 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the | |
| 8566 // foo match ends up with the wrong leaf. One fix is to not match both | |
| 8567 // reg-reg and reg-zero forms of long-compare. This is unfortunate because | |
| 8568 // both forms beat the trinary form of long-compare and both are very useful | |
| 8569 // on Intel which has so few registers. | |
| 8570 | |
| 8571 instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{ | |
| 8572 match(If cmp xcc); | |
| 8573 effect(USE labl); | |
| 8574 | |
| 8575 size(8); | |
| 8576 ins_cost(BRANCH_COST); | |
| 8577 format %{ "BP$cmp $xcc,$labl" %} | |
| 8578 // Prim = bits 24-22, Secnd = bits 31-30 | |
| 8579 ins_encode( enc_bpl( labl, cmp, xcc ) ); | |
| 8580 ins_pc_relative(1); | |
| 8581 ins_pipe(br_cc); | |
| 8582 %} | |
| 8583 | |
| 8584 // Manifest a CmpL3 result in an integer register. Very painful. | |
| 8585 // This is the test to avoid. | |
| 8586 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{ | |
| 8587 match(Set dst (CmpL3 src1 src2) ); | |
| 8588 effect( KILL ccr ); | |
| 8589 ins_cost(6*DEFAULT_COST); | |
| 8590 size(24); | |
| 8591 format %{ "CMP $src1,$src2\t\t! long\n" | |
| 8592 "\tBLT,a,pn done\n" | |
| 8593 "\tMOV -1,$dst\t! delay slot\n" | |
| 8594 "\tBGT,a,pn done\n" | |
| 8595 "\tMOV 1,$dst\t! delay slot\n" | |
| 8596 "\tCLR $dst\n" | |
| 8597 "done:" %} | |
| 8598 ins_encode( cmpl_flag(src1,src2,dst) ); | |
| 8599 ins_pipe(cmpL_reg); | |
| 8600 %} | |
| 8601 | |
| 8602 // Conditional move | |
| 8603 instruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{ | |
| 8604 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src))); | |
| 8605 ins_cost(150); | |
| 8606 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %} | |
| 8607 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); | |
| 8608 ins_pipe(ialu_reg); | |
| 8609 %} | |
| 8610 | |
| 8611 instruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{ | |
| 8612 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src))); | |
| 8613 ins_cost(140); | |
| 8614 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %} | |
| 8615 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); | |
| 8616 ins_pipe(ialu_imm); | |
| 8617 %} | |
| 8618 | |
| 8619 instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{ | |
| 8620 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src))); | |
| 8621 ins_cost(150); | |
| 8622 format %{ "MOV$cmp $xcc,$src,$dst" %} | |
| 8623 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); | |
| 8624 ins_pipe(ialu_reg); | |
| 8625 %} | |
| 8626 | |
| 8627 instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{ | |
| 8628 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src))); | |
| 8629 ins_cost(140); | |
| 8630 format %{ "MOV$cmp $xcc,$src,$dst" %} | |
| 8631 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); | |
| 8632 ins_pipe(ialu_imm); | |
| 8633 %} | |
| 8634 | |
|
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8635 instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{ |
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8636 match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src))); |
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8637 ins_cost(150); |
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8638 format %{ "MOV$cmp $xcc,$src,$dst" %} |
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8639 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); |
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8640 ins_pipe(ialu_reg); |
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8641 %} |
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8642 |
| 0 | 8643 instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{ |
| 8644 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src))); | |
| 8645 ins_cost(150); | |
| 8646 format %{ "MOV$cmp $xcc,$src,$dst" %} | |
| 8647 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); | |
| 8648 ins_pipe(ialu_reg); | |
| 8649 %} | |
| 8650 | |
| 8651 instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{ | |
| 8652 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src))); | |
| 8653 ins_cost(140); | |
| 8654 format %{ "MOV$cmp $xcc,$src,$dst" %} | |
| 8655 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); | |
| 8656 ins_pipe(ialu_imm); | |
| 8657 %} | |
| 8658 | |
| 8659 instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{ | |
| 8660 match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src))); | |
| 8661 ins_cost(150); | |
| 8662 opcode(0x101); | |
| 8663 format %{ "FMOVS$cmp $xcc,$src,$dst" %} | |
| 8664 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) ); | |
| 8665 ins_pipe(int_conditional_float_move); | |
| 8666 %} | |
| 8667 | |
| 8668 instruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{ | |
| 8669 match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src))); | |
| 8670 ins_cost(150); | |
| 8671 opcode(0x102); | |
| 8672 format %{ "FMOVD$cmp $xcc,$src,$dst" %} | |
| 8673 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) ); | |
| 8674 ins_pipe(int_conditional_float_move); | |
| 8675 %} | |
| 8676 | |
| 8677 // ============================================================================ | |
| 8678 // Safepoint Instruction | |
| 8679 instruct safePoint_poll(iRegP poll) %{ | |
| 8680 match(SafePoint poll); | |
| 8681 effect(USE poll); | |
| 8682 | |
| 8683 size(4); | |
| 8684 #ifdef _LP64 | |
| 8685 format %{ "LDX [$poll],R_G0\t! Safepoint: poll for GC" %} | |
| 8686 #else | |
| 8687 format %{ "LDUW [$poll],R_G0\t! Safepoint: poll for GC" %} | |
| 8688 #endif | |
| 8689 ins_encode %{ | |
| 8690 __ relocate(relocInfo::poll_type); | |
| 8691 __ ld_ptr($poll$$Register, 0, G0); | |
| 8692 %} | |
| 8693 ins_pipe(loadPollP); | |
| 8694 %} | |
| 8695 | |
| 8696 // ============================================================================ | |
| 8697 // Call Instructions | |
| 8698 // Call Java Static Instruction | |
| 8699 instruct CallStaticJavaDirect( method meth ) %{ | |
| 8700 match(CallStaticJava); | |
| 8701 effect(USE meth); | |
| 8702 | |
| 8703 size(8); | |
| 8704 ins_cost(CALL_COST); | |
| 8705 format %{ "CALL,static ; NOP ==> " %} | |
| 8706 ins_encode( Java_Static_Call( meth ), call_epilog ); | |
| 8707 ins_pc_relative(1); | |
| 8708 ins_pipe(simple_call); | |
| 8709 %} | |
| 8710 | |
| 8711 // Call Java Dynamic Instruction | |
| 8712 instruct CallDynamicJavaDirect( method meth ) %{ | |
| 8713 match(CallDynamicJava); | |
| 8714 effect(USE meth); | |
| 8715 | |
| 8716 ins_cost(CALL_COST); | |
| 8717 format %{ "SET (empty),R_G5\n\t" | |
| 8718 "CALL,dynamic ; NOP ==> " %} | |
| 8719 ins_encode( Java_Dynamic_Call( meth ), call_epilog ); | |
| 8720 ins_pc_relative(1); | |
| 8721 ins_pipe(call); | |
| 8722 %} | |
| 8723 | |
| 8724 // Call Runtime Instruction | |
| 8725 instruct CallRuntimeDirect(method meth, l7RegP l7) %{ | |
| 8726 match(CallRuntime); | |
| 8727 effect(USE meth, KILL l7); | |
| 8728 ins_cost(CALL_COST); | |
| 8729 format %{ "CALL,runtime" %} | |
| 8730 ins_encode( Java_To_Runtime( meth ), | |
| 8731 call_epilog, adjust_long_from_native_call ); | |
| 8732 ins_pc_relative(1); | |
| 8733 ins_pipe(simple_call); | |
| 8734 %} | |
| 8735 | |
| 8736 // Call runtime without safepoint - same as CallRuntime | |
| 8737 instruct CallLeafDirect(method meth, l7RegP l7) %{ | |
| 8738 match(CallLeaf); | |
| 8739 effect(USE meth, KILL l7); | |
| 8740 ins_cost(CALL_COST); | |
| 8741 format %{ "CALL,runtime leaf" %} | |
| 8742 ins_encode( Java_To_Runtime( meth ), | |
| 8743 call_epilog, | |
| 8744 adjust_long_from_native_call ); | |
| 8745 ins_pc_relative(1); | |
| 8746 ins_pipe(simple_call); | |
| 8747 %} | |
| 8748 | |
| 8749 // Call runtime without safepoint - same as CallLeaf | |
| 8750 instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{ | |
| 8751 match(CallLeafNoFP); | |
| 8752 effect(USE meth, KILL l7); | |
| 8753 ins_cost(CALL_COST); | |
| 8754 format %{ "CALL,runtime leaf nofp" %} | |
| 8755 ins_encode( Java_To_Runtime( meth ), | |
| 8756 call_epilog, | |
| 8757 adjust_long_from_native_call ); | |
| 8758 ins_pc_relative(1); | |
| 8759 ins_pipe(simple_call); | |
| 8760 %} | |
| 8761 | |
| 8762 // Tail Call; Jump from runtime stub to Java code. | |
| 8763 // Also known as an 'interprocedural jump'. | |
| 8764 // Target of jump will eventually return to caller. | |
| 8765 // TailJump below removes the return address. | |
| 8766 instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{ | |
| 8767 match(TailCall jump_target method_oop ); | |
| 8768 | |
| 8769 ins_cost(CALL_COST); | |
| 8770 format %{ "Jmp $jump_target ; NOP \t! $method_oop holds method oop" %} | |
| 8771 ins_encode(form_jmpl(jump_target)); | |
| 8772 ins_pipe(tail_call); | |
| 8773 %} | |
| 8774 | |
| 8775 | |
| 8776 // Return Instruction | |
| 8777 instruct Ret() %{ | |
| 8778 match(Return); | |
| 8779 | |
| 8780 // The epilogue node did the ret already. | |
| 8781 size(0); | |
| 8782 format %{ "! return" %} | |
| 8783 ins_encode(); | |
| 8784 ins_pipe(empty); | |
| 8785 %} | |
| 8786 | |
| 8787 | |
| 8788 // Tail Jump; remove the return address; jump to target. | |
| 8789 // TailCall above leaves the return address around. | |
| 8790 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2). | |
| 8791 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a | |
| 8792 // "restore" before this instruction (in Epilogue), we need to materialize it | |
| 8793 // in %i0. | |
| 8794 instruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{ | |
| 8795 match( TailJump jump_target ex_oop ); | |
| 8796 ins_cost(CALL_COST); | |
| 8797 format %{ "! discard R_O7\n\t" | |
| 8798 "Jmp $jump_target ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %} | |
| 8799 ins_encode(form_jmpl_set_exception_pc(jump_target)); | |
| 8800 // opcode(Assembler::jmpl_op3, Assembler::arith_op); | |
| 8801 // The hack duplicates the exception oop into G3, so that CreateEx can use it there. | |
| 8802 // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() ); | |
| 8803 ins_pipe(tail_call); | |
| 8804 %} | |
| 8805 | |
| 8806 // Create exception oop: created by stack-crawling runtime code. | |
| 8807 // Created exception is now available to this handler, and is setup | |
| 8808 // just prior to jumping to this handler. No code emitted. | |
| 8809 instruct CreateException( o0RegP ex_oop ) | |
| 8810 %{ | |
| 8811 match(Set ex_oop (CreateEx)); | |
| 8812 ins_cost(0); | |
| 8813 | |
| 8814 size(0); | |
| 8815 // use the following format syntax | |
| 8816 format %{ "! exception oop is in R_O0; no code emitted" %} | |
| 8817 ins_encode(); | |
| 8818 ins_pipe(empty); | |
| 8819 %} | |
| 8820 | |
| 8821 | |
| 8822 // Rethrow exception: | |
| 8823 // The exception oop will come in the first argument position. | |
| 8824 // Then JUMP (not call) to the rethrow stub code. | |
| 8825 instruct RethrowException() | |
| 8826 %{ | |
| 8827 match(Rethrow); | |
| 8828 ins_cost(CALL_COST); | |
| 8829 | |
| 8830 // use the following format syntax | |
| 8831 format %{ "Jmp rethrow_stub" %} | |
| 8832 ins_encode(enc_rethrow); | |
| 8833 ins_pipe(tail_call); | |
| 8834 %} | |
| 8835 | |
| 8836 | |
| 8837 // Die now | |
| 8838 instruct ShouldNotReachHere( ) | |
| 8839 %{ | |
| 8840 match(Halt); | |
| 8841 ins_cost(CALL_COST); | |
| 8842 | |
| 8843 size(4); | |
| 8844 // Use the following format syntax | |
| 8845 format %{ "ILLTRAP ; ShouldNotReachHere" %} | |
| 8846 ins_encode( form2_illtrap() ); | |
| 8847 ins_pipe(tail_call); | |
| 8848 %} | |
| 8849 | |
| 8850 // ============================================================================ | |
| 8851 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass | |
| 8852 // array for an instance of the superklass. Set a hidden internal cache on a | |
| 8853 // hit (cache is checked with exposed code in gen_subtype_check()). Return | |
| 8854 // not zero for a miss or zero for a hit. The encoding ALSO sets flags. | |
| 8855 instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{ | |
| 8856 match(Set index (PartialSubtypeCheck sub super)); | |
| 8857 effect( KILL pcc, KILL o7 ); | |
| 8858 ins_cost(DEFAULT_COST*10); | |
| 8859 format %{ "CALL PartialSubtypeCheck\n\tNOP" %} | |
| 8860 ins_encode( enc_PartialSubtypeCheck() ); | |
| 8861 ins_pipe(partial_subtype_check_pipe); | |
| 8862 %} | |
| 8863 | |
| 8864 instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{ | |
| 8865 match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero)); | |
| 8866 effect( KILL idx, KILL o7 ); | |
| 8867 ins_cost(DEFAULT_COST*10); | |
| 8868 format %{ "CALL PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %} | |
| 8869 ins_encode( enc_PartialSubtypeCheck() ); | |
| 8870 ins_pipe(partial_subtype_check_pipe); | |
| 8871 %} | |
| 8872 | |
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8873 |
| 0 | 8874 // ============================================================================ |
| 8875 // inlined locking and unlocking | |
| 8876 | |
| 8877 instruct cmpFastLock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{ | |
| 8878 match(Set pcc (FastLock object box)); | |
| 8879 | |
| 8880 effect(KILL scratch, TEMP scratch2); | |
| 8881 ins_cost(100); | |
| 8882 | |
| 8883 size(4*112); // conservative overestimation ... | |
| 8884 format %{ "FASTLOCK $object, $box; KILL $scratch, $scratch2, $box" %} | |
| 8885 ins_encode( Fast_Lock(object, box, scratch, scratch2) ); | |
| 8886 ins_pipe(long_memory_op); | |
| 8887 %} | |
| 8888 | |
| 8889 | |
| 8890 instruct cmpFastUnlock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{ | |
| 8891 match(Set pcc (FastUnlock object box)); | |
| 8892 effect(KILL scratch, TEMP scratch2); | |
| 8893 ins_cost(100); | |
| 8894 | |
| 8895 size(4*120); // conservative overestimation ... | |
| 8896 format %{ "FASTUNLOCK $object, $box; KILL $scratch, $scratch2, $box" %} | |
| 8897 ins_encode( Fast_Unlock(object, box, scratch, scratch2) ); | |
| 8898 ins_pipe(long_memory_op); | |
| 8899 %} | |
| 8900 | |
| 8901 // Count and Base registers are fixed because the allocator cannot | |
| 8902 // kill unknown registers. The encodings are generic. | |
| 8903 instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{ | |
| 8904 match(Set dummy (ClearArray cnt base)); | |
| 8905 effect(TEMP temp, KILL ccr); | |
| 8906 ins_cost(300); | |
| 8907 format %{ "MOV $cnt,$temp\n" | |
| 8908 "loop: SUBcc $temp,8,$temp\t! Count down a dword of bytes\n" | |
| 8909 " BRge loop\t\t! Clearing loop\n" | |
| 8910 " STX G0,[$base+$temp]\t! delay slot" %} | |
| 8911 ins_encode( enc_Clear_Array(cnt, base, temp) ); | |
| 8912 ins_pipe(long_memory_op); | |
| 8913 %} | |
| 8914 | |
|
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8915 instruct string_compare(o0RegP str1, o1RegP str2, g3RegP tmp1, g4RegP tmp2, notemp_iRegI result, |
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|
8916 o7RegI tmp3, flagsReg ccr) %{ |
| 0 | 8917 match(Set result (StrComp str1 str2)); |
|
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8918 effect(USE_KILL str1, USE_KILL str2, KILL tmp1, KILL tmp2, KILL ccr, KILL tmp3); |
| 0 | 8919 ins_cost(300); |
| 8920 format %{ "String Compare $str1,$str2 -> $result" %} | |
| 8921 ins_encode( enc_String_Compare(str1, str2, tmp1, tmp2, result) ); | |
| 8922 ins_pipe(long_memory_op); | |
| 8923 %} | |
| 8924 | |
| 8925 // ============================================================================ | |
| 8926 //------------Bytes reverse-------------------------------------------------- | |
| 8927 | |
| 8928 instruct bytes_reverse_int(iRegI dst, stackSlotI src) %{ | |
| 8929 match(Set dst (ReverseBytesI src)); | |
| 8930 effect(DEF dst, USE src); | |
| 8931 | |
| 8932 // Op cost is artificially doubled to make sure that load or store | |
| 8933 // instructions are preferred over this one which requires a spill | |
| 8934 // onto a stack slot. | |
| 8935 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); | |
| 8936 size(8); | |
| 8937 format %{ "LDUWA $src, $dst\t!asi=primary_little" %} | |
| 8938 opcode(Assembler::lduwa_op3); | |
| 8939 ins_encode( form3_mem_reg_little(src, dst) ); | |
| 8940 ins_pipe( iload_mem ); | |
| 8941 %} | |
| 8942 | |
| 8943 instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{ | |
| 8944 match(Set dst (ReverseBytesL src)); | |
| 8945 effect(DEF dst, USE src); | |
| 8946 | |
| 8947 // Op cost is artificially doubled to make sure that load or store | |
| 8948 // instructions are preferred over this one which requires a spill | |
| 8949 // onto a stack slot. | |
| 8950 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); | |
| 8951 size(8); | |
| 8952 format %{ "LDXA $src, $dst\t!asi=primary_little" %} | |
| 8953 | |
| 8954 opcode(Assembler::ldxa_op3); | |
| 8955 ins_encode( form3_mem_reg_little(src, dst) ); | |
| 8956 ins_pipe( iload_mem ); | |
| 8957 %} | |
| 8958 | |
| 8959 // Load Integer reversed byte order | |
| 8960 instruct loadI_reversed(iRegI dst, memory src) %{ | |
| 8961 match(Set dst (ReverseBytesI (LoadI src))); | |
| 8962 | |
| 8963 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
| 8964 size(8); | |
| 8965 format %{ "LDUWA $src, $dst\t!asi=primary_little" %} | |
| 8966 | |
| 8967 opcode(Assembler::lduwa_op3); | |
| 8968 ins_encode( form3_mem_reg_little( src, dst) ); | |
| 8969 ins_pipe(iload_mem); | |
| 8970 %} | |
| 8971 | |
| 8972 // Load Long - aligned and reversed | |
| 8973 instruct loadL_reversed(iRegL dst, memory src) %{ | |
| 8974 match(Set dst (ReverseBytesL (LoadL src))); | |
| 8975 | |
| 8976 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
| 8977 size(8); | |
| 8978 format %{ "LDXA $src, $dst\t!asi=primary_little" %} | |
| 8979 | |
| 8980 opcode(Assembler::ldxa_op3); | |
| 8981 ins_encode( form3_mem_reg_little( src, dst ) ); | |
| 8982 ins_pipe(iload_mem); | |
| 8983 %} | |
| 8984 | |
| 8985 // Store Integer reversed byte order | |
| 8986 instruct storeI_reversed(memory dst, iRegI src) %{ | |
| 8987 match(Set dst (StoreI dst (ReverseBytesI src))); | |
| 8988 | |
| 8989 ins_cost(MEMORY_REF_COST); | |
| 8990 size(8); | |
| 8991 format %{ "STWA $src, $dst\t!asi=primary_little" %} | |
| 8992 | |
| 8993 opcode(Assembler::stwa_op3); | |
| 8994 ins_encode( form3_mem_reg_little( dst, src) ); | |
| 8995 ins_pipe(istore_mem_reg); | |
| 8996 %} | |
| 8997 | |
| 8998 // Store Long reversed byte order | |
| 8999 instruct storeL_reversed(memory dst, iRegL src) %{ | |
| 9000 match(Set dst (StoreL dst (ReverseBytesL src))); | |
| 9001 | |
| 9002 ins_cost(MEMORY_REF_COST); | |
| 9003 size(8); | |
| 9004 format %{ "STXA $src, $dst\t!asi=primary_little" %} | |
| 9005 | |
| 9006 opcode(Assembler::stxa_op3); | |
| 9007 ins_encode( form3_mem_reg_little( dst, src) ); | |
| 9008 ins_pipe(istore_mem_reg); | |
| 9009 %} | |
| 9010 | |
| 9011 //----------PEEPHOLE RULES----------------------------------------------------- | |
| 9012 // These must follow all instruction definitions as they use the names | |
| 9013 // defined in the instructions definitions. | |
| 9014 // | |
| 9015 // peepmatch ( root_instr_name [preceeding_instruction]* ); | |
| 9016 // | |
| 9017 // peepconstraint %{ | |
| 9018 // (instruction_number.operand_name relational_op instruction_number.operand_name | |
| 9019 // [, ...] ); | |
| 9020 // // instruction numbers are zero-based using left to right order in peepmatch | |
| 9021 // | |
| 9022 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) ); | |
| 9023 // // provide an instruction_number.operand_name for each operand that appears | |
| 9024 // // in the replacement instruction's match rule | |
| 9025 // | |
| 9026 // ---------VM FLAGS--------------------------------------------------------- | |
| 9027 // | |
| 9028 // All peephole optimizations can be turned off using -XX:-OptoPeephole | |
| 9029 // | |
| 9030 // Each peephole rule is given an identifying number starting with zero and | |
| 9031 // increasing by one in the order seen by the parser. An individual peephole | |
| 9032 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=# | |
| 9033 // on the command-line. | |
| 9034 // | |
| 9035 // ---------CURRENT LIMITATIONS---------------------------------------------- | |
| 9036 // | |
| 9037 // Only match adjacent instructions in same basic block | |
| 9038 // Only equality constraints | |
| 9039 // Only constraints between operands, not (0.dest_reg == EAX_enc) | |
| 9040 // Only one replacement instruction | |
| 9041 // | |
| 9042 // ---------EXAMPLE---------------------------------------------------------- | |
| 9043 // | |
| 9044 // // pertinent parts of existing instructions in architecture description | |
| 9045 // instruct movI(eRegI dst, eRegI src) %{ | |
| 9046 // match(Set dst (CopyI src)); | |
| 9047 // %} | |
| 9048 // | |
| 9049 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{ | |
| 9050 // match(Set dst (AddI dst src)); | |
| 9051 // effect(KILL cr); | |
| 9052 // %} | |
| 9053 // | |
| 9054 // // Change (inc mov) to lea | |
| 9055 // peephole %{ | |
| 9056 // // increment preceeded by register-register move | |
| 9057 // peepmatch ( incI_eReg movI ); | |
| 9058 // // require that the destination register of the increment | |
| 9059 // // match the destination register of the move | |
| 9060 // peepconstraint ( 0.dst == 1.dst ); | |
| 9061 // // construct a replacement instruction that sets | |
| 9062 // // the destination to ( move's source register + one ) | |
| 9063 // peepreplace ( incI_eReg_immI1( 0.dst 1.src 0.src ) ); | |
| 9064 // %} | |
| 9065 // | |
| 9066 | |
| 9067 // // Change load of spilled value to only a spill | |
| 9068 // instruct storeI(memory mem, eRegI src) %{ | |
| 9069 // match(Set mem (StoreI mem src)); | |
| 9070 // %} | |
| 9071 // | |
| 9072 // instruct loadI(eRegI dst, memory mem) %{ | |
| 9073 // match(Set dst (LoadI mem)); | |
| 9074 // %} | |
| 9075 // | |
| 9076 // peephole %{ | |
| 9077 // peepmatch ( loadI storeI ); | |
| 9078 // peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem ); | |
| 9079 // peepreplace ( storeI( 1.mem 1.mem 1.src ) ); | |
| 9080 // %} | |
| 9081 | |
| 9082 //----------SMARTSPILL RULES--------------------------------------------------- | |
| 9083 // These must follow all instruction definitions as they use the names | |
| 9084 // defined in the instructions definitions. | |
| 9085 // | |
| 9086 // SPARC will probably not have any of these rules due to RISC instruction set. | |
| 9087 | |
| 9088 //----------PIPELINE----------------------------------------------------------- | |
| 9089 // Rules which define the behavior of the target architectures pipeline. |