annotate src/share/vm/opto/postaloc.cpp @ 17524:89152779163c

Merge with jdk8-b132
author Gilles Duboscq <duboscq@ssw.jku.at>
date Wed, 15 Oct 2014 11:59:32 +0200
parents 4ca6dc0799b6
children
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1 /*
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Gilles Duboscq <duboscq@ssw.jku.at>
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2 * Copyright (c) 1998, 2013, Oracle and/or its affiliates. All rights reserved.
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3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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4 *
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5 * This code is free software; you can redistribute it and/or modify it
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6 * under the terms of the GNU General Public License version 2 only, as
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7 * published by the Free Software Foundation.
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8 *
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9 * This code is distributed in the hope that it will be useful, but WITHOUT
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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12 * version 2 for more details (a copy is included in the LICENSE file that
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13 * accompanied this code).
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14 *
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15 * You should have received a copy of the GNU General Public License version
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16 * 2 along with this work; if not, write to the Free Software Foundation,
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17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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18 *
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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20 * or visit www.oracle.com if you need additional information or have any
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21 * questions.
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22 *
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23 */
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24
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25 #include "precompiled.hpp"
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26 #include "memory/allocation.inline.hpp"
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27 #include "opto/chaitin.hpp"
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28 #include "opto/machnode.hpp"
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29
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30 // See if this register (or pairs, or vector) already contains the value.
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31 static bool register_contains_value(Node* val, OptoReg::Name reg, int n_regs,
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32 Node_List& value) {
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33 for (int i = 0; i < n_regs; i++) {
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34 OptoReg::Name nreg = OptoReg::add(reg,-i);
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35 if (value[nreg] != val)
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36 return false;
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37 }
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38 return true;
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39 }
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40
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41 //---------------------------may_be_copy_of_callee-----------------------------
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42 // Check to see if we can possibly be a copy of a callee-save value.
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43 bool PhaseChaitin::may_be_copy_of_callee( Node *def ) const {
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44 // Short circuit if there are no callee save registers
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45 if (_matcher.number_of_saved_registers() == 0) return false;
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46
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47 // Expect only a spill-down and reload on exit for callee-save spills.
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48 // Chains of copies cannot be deep.
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49 // 5008997 - This is wishful thinking. Register allocator seems to
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50 // be splitting live ranges for callee save registers to such
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51 // an extent that in large methods the chains can be very long
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52 // (50+). The conservative answer is to return true if we don't
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53 // know as this prevents optimizations from occurring.
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54
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55 const int limit = 60;
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56 int i;
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57 for( i=0; i < limit; i++ ) {
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58 if( def->is_Proj() && def->in(0)->is_Start() &&
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59 _matcher.is_save_on_entry(lrgs(_lrg_map.live_range_id(def)).reg()))
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60 return true; // Direct use of callee-save proj
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61 if( def->is_Copy() ) // Copies carry value through
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62 def = def->in(def->is_Copy());
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63 else if( def->is_Phi() ) // Phis can merge it from any direction
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64 def = def->in(1);
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65 else
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66 break;
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67 guarantee(def != NULL, "must not resurrect dead copy");
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68 }
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69 // If we reached the end and didn't find a callee save proj
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70 // then this may be a callee save proj so we return true
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71 // as the conservative answer. If we didn't reach then end
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72 // we must have discovered that it was not a callee save
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73 // else we would have returned.
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74 return i == limit;
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75 }
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76
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77 //------------------------------yank-----------------------------------
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78 // Helper function for yank_if_dead
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79 int PhaseChaitin::yank( Node *old, Block *current_block, Node_List *value, Node_List *regnd ) {
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80 int blk_adjust=0;
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81 Block *oldb = _cfg.get_block_for_node(old);
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82 oldb->find_remove(old);
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83 // Count 1 if deleting an instruction from the current block
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84 if (oldb == current_block) {
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85 blk_adjust++;
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86 }
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87 _cfg.unmap_node_from_block(old);
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88 OptoReg::Name old_reg = lrgs(_lrg_map.live_range_id(old)).reg();
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89 if( regnd && (*regnd)[old_reg]==old ) { // Instruction is currently available?
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90 value->map(old_reg,NULL); // Yank from value/regnd maps
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91 regnd->map(old_reg,NULL); // This register's value is now unknown
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92 }
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93 return blk_adjust;
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94 }
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95
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96 #ifdef ASSERT
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97 static bool expected_yanked_node(Node *old, Node *orig_old) {
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98 // This code is expected only next original nodes:
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99 // - load from constant table node which may have next data input nodes:
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100 // MachConstantBase, MachTemp, MachSpillCopy
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101 // - Phi nodes that are considered Junk
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102 // - load constant node which may have next data input nodes:
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103 // MachTemp, MachSpillCopy
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104 // - MachSpillCopy
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105 // - MachProj and Copy dead nodes
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106 if (old->is_MachSpillCopy()) {
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107 return true;
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108 } else if (old->is_Con()) {
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109 return true;
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110 } else if (old->is_MachProj()) { // Dead kills projection of Con node
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111 return (old == orig_old);
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112 } else if (old->is_Copy()) { // Dead copy of a callee-save value
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113 return (old == orig_old);
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114 } else if (old->is_MachTemp()) {
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115 return orig_old->is_Con();
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116 } else if (old->is_Phi()) { // Junk phi's
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117 return true;
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118 } else if (old->is_MachConstantBase()) {
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119 return (orig_old->is_Con() && orig_old->is_MachConstant());
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120 }
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121 return false;
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122 }
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123 #endif
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124
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125 //------------------------------yank_if_dead-----------------------------------
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126 // Removed edges from 'old'. Yank if dead. Return adjustment counts to
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127 // iterators in the current block.
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128 int PhaseChaitin::yank_if_dead_recurse(Node *old, Node *orig_old, Block *current_block,
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129 Node_List *value, Node_List *regnd) {
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130 int blk_adjust=0;
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131 if (old->outcnt() == 0 && old != C->top()) {
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132 #ifdef ASSERT
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133 if (!expected_yanked_node(old, orig_old)) {
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134 tty->print_cr("==============================================");
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135 tty->print_cr("orig_old:");
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136 orig_old->dump();
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137 tty->print_cr("old:");
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138 old->dump();
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139 assert(false, "unexpected yanked node");
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140 }
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141 if (old->is_Con())
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142 orig_old = old; // Reset to satisfy expected nodes checks.
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143 #endif
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144 blk_adjust += yank(old, current_block, value, regnd);
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145
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146 for (uint i = 1; i < old->req(); i++) {
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147 Node* n = old->in(i);
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148 if (n != NULL) {
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149 old->set_req(i, NULL);
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150 blk_adjust += yank_if_dead_recurse(n, orig_old, current_block, value, regnd);
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151 }
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152 }
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153 // Disconnect control and remove precedence edges if any exist
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154 old->disconnect_inputs(NULL, C);
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155 }
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156 return blk_adjust;
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157 }
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158
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159 //------------------------------use_prior_register-----------------------------
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160 // Use the prior value instead of the current value, in an effort to make
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161 // the current value go dead. Return block iterator adjustment, in case
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162 // we yank some instructions from this block.
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163 int PhaseChaitin::use_prior_register( Node *n, uint idx, Node *def, Block *current_block, Node_List &value, Node_List &regnd ) {
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164 // No effect?
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165 if( def == n->in(idx) ) return 0;
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166 // Def is currently dead and can be removed? Do not resurrect
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167 if( def->outcnt() == 0 ) return 0;
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168
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169 // Not every pair of physical registers are assignment compatible,
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170 // e.g. on sparc floating point registers are not assignable to integer
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171 // registers.
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172 const LRG &def_lrg = lrgs(_lrg_map.live_range_id(def));
0
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173 OptoReg::Name def_reg = def_lrg.reg();
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174 const RegMask &use_mask = n->in_RegMask(idx);
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175 bool can_use = ( RegMask::can_represent(def_reg) ? (use_mask.Member(def_reg) != 0)
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176 : (use_mask.is_AllStack() != 0));
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177 if (!RegMask::is_vector(def->ideal_reg())) {
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178 // Check for a copy to or from a misaligned pair.
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179 // It is workaround for a sparc with misaligned pairs.
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180 can_use = can_use && !use_mask.is_misaligned_pair() && !def_lrg.mask().is_misaligned_pair();
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181 }
0
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182 if (!can_use)
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183 return 0;
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184
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185 // Capture the old def in case it goes dead...
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186 Node *old = n->in(idx);
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187
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188 // Save-on-call copies can only be elided if the entire copy chain can go
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189 // away, lest we get the same callee-save value alive in 2 locations at
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190 // once. We check for the obvious trivial case here. Although it can
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191 // sometimes be elided with cooperation outside our scope, here we will just
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192 // miss the opportunity. :-(
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193 if( may_be_copy_of_callee(def) ) {
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194 if( old->outcnt() > 1 ) return 0; // We're the not last user
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195 int idx = old->is_Copy();
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196 assert( idx, "chain of copies being removed" );
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197 Node *old2 = old->in(idx); // Chain of copies
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198 if( old2->outcnt() > 1 ) return 0; // old is not the last user
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199 int idx2 = old2->is_Copy();
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200 if( !idx2 ) return 0; // Not a chain of 2 copies
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201 if( def != old2->in(idx2) ) return 0; // Chain of exactly 2 copies
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202 }
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203
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204 // Use the new def
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205 n->set_req(idx,def);
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206 _post_alloc++;
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207
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208 // Is old def now dead? We successfully yanked a copy?
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209 return yank_if_dead(old,current_block,&value,&regnd);
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210 }
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211
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212
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213 //------------------------------skip_copies------------------------------------
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214 // Skip through any number of copies (that don't mod oop-i-ness)
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215 Node *PhaseChaitin::skip_copies( Node *c ) {
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216 int idx = c->is_Copy();
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217 uint is_oop = lrgs(_lrg_map.live_range_id(c))._is_oop;
0
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218 while (idx != 0) {
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219 guarantee(c->in(idx) != NULL, "must not resurrect dead copy");
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220 if (lrgs(_lrg_map.live_range_id(c->in(idx)))._is_oop != is_oop) {
0
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221 break; // casting copy, not the same value
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diff changeset
222 }
0
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223 c = c->in(idx);
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224 idx = c->is_Copy();
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225 }
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226 return c;
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227 }
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228
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229 //------------------------------elide_copy-------------------------------------
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230 // Remove (bypass) copies along Node n, edge k.
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231 int PhaseChaitin::elide_copy( Node *n, int k, Block *current_block, Node_List &value, Node_List &regnd, bool can_change_regs ) {
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232 int blk_adjust = 0;
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233
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diff changeset
234 uint nk_idx = _lrg_map.live_range_id(n->in(k));
8373c19be854 8011621: live_ranges_in_separate_class.patch
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235 OptoReg::Name nk_reg = lrgs(nk_idx).reg();
0
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236
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237 // Remove obvious same-register copies
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238 Node *x = n->in(k);
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239 int idx;
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240 while( (idx=x->is_Copy()) != 0 ) {
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241 Node *copy = x->in(idx);
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242 guarantee(copy != NULL, "must not resurrect dead copy");
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243 if(lrgs(_lrg_map.live_range_id(copy)).reg() != nk_reg) {
8373c19be854 8011621: live_ranges_in_separate_class.patch
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244 break;
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diff changeset
245 }
0
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246 blk_adjust += use_prior_register(n,k,copy,current_block,value,regnd);
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247 if (n->in(k) != copy) {
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248 break; // Failed for some cutout?
8373c19be854 8011621: live_ranges_in_separate_class.patch
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diff changeset
249 }
0
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250 x = copy; // Progress, try again
a61af66fc99e Initial load
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251 }
a61af66fc99e Initial load
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252
a61af66fc99e Initial load
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253 // Phis and 2-address instructions cannot change registers so easily - their
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254 // outputs must match their input.
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255 if( !can_change_regs )
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256 return blk_adjust; // Only check stupid copies!
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257
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258 // Loop backedges won't have a value-mapping yet
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259 if( &value == NULL ) return blk_adjust;
a61af66fc99e Initial load
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260
a61af66fc99e Initial load
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diff changeset
261 // Skip through all copies to the _value_ being used. Do not change from
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parents:
diff changeset
262 // int to pointer. This attempts to jump through a chain of copies, where
a61af66fc99e Initial load
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parents:
diff changeset
263 // intermediate copies might be illegal, i.e., value is stored down to stack
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parents:
diff changeset
264 // then reloaded BUT survives in a register the whole way.
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diff changeset
265 Node *val = skip_copies(n->in(k));
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266
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1972
diff changeset
267 if (val == x && nk_idx != 0 &&
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
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diff changeset
268 regnd[nk_reg] != NULL && regnd[nk_reg] != x &&
10111
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parents: 7196
diff changeset
269 _lrg_map.live_range_id(x) == _lrg_map.live_range_id(regnd[nk_reg])) {
2008
2f644f85485d 6961690: load oops from constant table on SPARC
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diff changeset
270 // When rematerialzing nodes and stretching lifetimes, the
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
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diff changeset
271 // allocator will reuse the original def for multidef LRG instead
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1972
diff changeset
272 // of the current reaching def because it can't know it's safe to
2f644f85485d 6961690: load oops from constant table on SPARC
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diff changeset
273 // do so. After allocation completes if they are in the same LRG
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1972
diff changeset
274 // then it should use the current reaching def instead.
2f644f85485d 6961690: load oops from constant table on SPARC
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diff changeset
275 n->set_req(k, regnd[nk_reg]);
2f644f85485d 6961690: load oops from constant table on SPARC
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diff changeset
276 blk_adjust += yank_if_dead(val, current_block, &value, &regnd);
2f644f85485d 6961690: load oops from constant table on SPARC
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parents: 1972
diff changeset
277 val = skip_copies(n->in(k));
2f644f85485d 6961690: load oops from constant table on SPARC
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diff changeset
278 }
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
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diff changeset
279
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
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280 if (val == x) return blk_adjust; // No progress?
0
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parents:
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281
6179
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282 int n_regs = RegMask::num_registers(val->ideal_reg());
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diff changeset
283 uint val_idx = _lrg_map.live_range_id(val);
0
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parents:
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284 OptoReg::Name val_reg = lrgs(val_idx).reg();
a61af66fc99e Initial load
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285
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286 // See if it happens to already be in the correct register!
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287 // (either Phi's direct register, or the common case of the name
a61af66fc99e Initial load
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288 // never-clobbered original-def register)
6179
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diff changeset
289 if (register_contains_value(val, val_reg, n_regs, value)) {
0
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290 blk_adjust += use_prior_register(n,k,regnd[val_reg],current_block,value,regnd);
a61af66fc99e Initial load
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291 if( n->in(k) == regnd[val_reg] ) // Success! Quit trying
a61af66fc99e Initial load
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292 return blk_adjust;
a61af66fc99e Initial load
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parents:
diff changeset
293 }
a61af66fc99e Initial load
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parents:
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294
a61af66fc99e Initial load
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295 // See if we can skip the copy by changing registers. Don't change from
a61af66fc99e Initial load
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parents:
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296 // using a register to using the stack unless we know we can remove a
a61af66fc99e Initial load
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297 // copy-load. Otherwise we might end up making a pile of Intel cisc-spill
a61af66fc99e Initial load
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parents:
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298 // ops reading from memory instead of just loading once and using the
a61af66fc99e Initial load
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parents:
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299 // register.
a61af66fc99e Initial load
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300
a61af66fc99e Initial load
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parents:
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301 // Also handle duplicate copies here.
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parents:
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302 const Type *t = val->is_Con() ? val->bottom_type() : NULL;
a61af66fc99e Initial load
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parents:
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303
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parents:
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304 // Scan all registers to see if this value is around already
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diff changeset
305 for( uint reg = 0; reg < (uint)_max_reg; reg++ ) {
400
cc80376deb0c 6667595: Set probability FAIR for pre-, post- loops and ALWAYS for main loop
kvn
parents: 196
diff changeset
306 if (reg == (uint)nk_reg) {
cc80376deb0c 6667595: Set probability FAIR for pre-, post- loops and ALWAYS for main loop
kvn
parents: 196
diff changeset
307 // Found ourselves so check if there is only one user of this
cc80376deb0c 6667595: Set probability FAIR for pre-, post- loops and ALWAYS for main loop
kvn
parents: 196
diff changeset
308 // copy and keep on searching for a better copy if so.
cc80376deb0c 6667595: Set probability FAIR for pre-, post- loops and ALWAYS for main loop
kvn
parents: 196
diff changeset
309 bool ignore_self = true;
cc80376deb0c 6667595: Set probability FAIR for pre-, post- loops and ALWAYS for main loop
kvn
parents: 196
diff changeset
310 x = n->in(k);
cc80376deb0c 6667595: Set probability FAIR for pre-, post- loops and ALWAYS for main loop
kvn
parents: 196
diff changeset
311 DUIterator_Fast imax, i = x->fast_outs(imax);
cc80376deb0c 6667595: Set probability FAIR for pre-, post- loops and ALWAYS for main loop
kvn
parents: 196
diff changeset
312 Node* first = x->fast_out(i); i++;
cc80376deb0c 6667595: Set probability FAIR for pre-, post- loops and ALWAYS for main loop
kvn
parents: 196
diff changeset
313 while (i < imax && ignore_self) {
cc80376deb0c 6667595: Set probability FAIR for pre-, post- loops and ALWAYS for main loop
kvn
parents: 196
diff changeset
314 Node* use = x->fast_out(i); i++;
cc80376deb0c 6667595: Set probability FAIR for pre-, post- loops and ALWAYS for main loop
kvn
parents: 196
diff changeset
315 if (use != first) ignore_self = false;
cc80376deb0c 6667595: Set probability FAIR for pre-, post- loops and ALWAYS for main loop
kvn
parents: 196
diff changeset
316 }
cc80376deb0c 6667595: Set probability FAIR for pre-, post- loops and ALWAYS for main loop
kvn
parents: 196
diff changeset
317 if (ignore_self) continue;
cc80376deb0c 6667595: Set probability FAIR for pre-, post- loops and ALWAYS for main loop
kvn
parents: 196
diff changeset
318 }
cc80376deb0c 6667595: Set probability FAIR for pre-, post- loops and ALWAYS for main loop
kvn
parents: 196
diff changeset
319
0
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parents:
diff changeset
320 Node *vv = value[reg];
6185
424142833d10 7178280: Failed new vector regression tests
kvn
parents: 6179
diff changeset
321 if (n_regs > 1) { // Doubles and vectors check for aligned-adjacent set
424142833d10 7178280: Failed new vector regression tests
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diff changeset
322 uint last = (n_regs-1); // Looking for the last part of a set
424142833d10 7178280: Failed new vector regression tests
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diff changeset
323 if ((reg&last) != last) continue; // Wrong part of a set
424142833d10 7178280: Failed new vector regression tests
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diff changeset
324 if (!register_contains_value(vv, reg, n_regs, value)) continue; // Different value
0
a61af66fc99e Initial load
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parents:
diff changeset
325 }
a61af66fc99e Initial load
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parents:
diff changeset
326 if( vv == val || // Got a direct hit?
a61af66fc99e Initial load
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parents:
diff changeset
327 (t && vv && vv->bottom_type() == t && vv->is_Mach() &&
a61af66fc99e Initial load
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parents:
diff changeset
328 vv->as_Mach()->rule() == val->as_Mach()->rule()) ) { // Or same constant?
a61af66fc99e Initial load
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parents:
diff changeset
329 assert( !n->is_Phi(), "cannot change registers at a Phi so easily" );
a61af66fc99e Initial load
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parents:
diff changeset
330 if( OptoReg::is_stack(nk_reg) || // CISC-loading from stack OR
a61af66fc99e Initial load
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parents:
diff changeset
331 OptoReg::is_reg(reg) || // turning into a register use OR
a61af66fc99e Initial load
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parents:
diff changeset
332 regnd[reg]->outcnt()==1 ) { // last use of a spill-load turns into a CISC use
a61af66fc99e Initial load
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parents:
diff changeset
333 blk_adjust += use_prior_register(n,k,regnd[reg],current_block,value,regnd);
a61af66fc99e Initial load
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parents:
diff changeset
334 if( n->in(k) == regnd[reg] ) // Success! Quit trying
a61af66fc99e Initial load
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parents:
diff changeset
335 return blk_adjust;
a61af66fc99e Initial load
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parents:
diff changeset
336 } // End of if not degrading to a stack
a61af66fc99e Initial load
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parents:
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337 } // End of if found value in another register
a61af66fc99e Initial load
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parents:
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338 } // End of scan all machine registers
a61af66fc99e Initial load
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parents:
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339 return blk_adjust;
a61af66fc99e Initial load
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parents:
diff changeset
340 }
a61af66fc99e Initial load
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parents:
diff changeset
341
a61af66fc99e Initial load
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diff changeset
342
a61af66fc99e Initial load
duke
parents:
diff changeset
343 //
a61af66fc99e Initial load
duke
parents:
diff changeset
344 // Check if nreg already contains the constant value val. Normal copy
a61af66fc99e Initial load
duke
parents:
diff changeset
345 // elimination doesn't doesn't work on constants because multiple
a61af66fc99e Initial load
duke
parents:
diff changeset
346 // nodes can represent the same constant so the type and rule of the
a61af66fc99e Initial load
duke
parents:
diff changeset
347 // MachNode must be checked to ensure equivalence.
a61af66fc99e Initial load
duke
parents:
diff changeset
348 //
70
b683f557224b 6661247: Internal bug in 32-bit HotSpot optimizer while bit manipulations
never
parents: 0
diff changeset
349 bool PhaseChaitin::eliminate_copy_of_constant(Node* val, Node* n,
b683f557224b 6661247: Internal bug in 32-bit HotSpot optimizer while bit manipulations
never
parents: 0
diff changeset
350 Block *current_block,
0
a61af66fc99e Initial load
duke
parents:
diff changeset
351 Node_List& value, Node_List& regnd,
a61af66fc99e Initial load
duke
parents:
diff changeset
352 OptoReg::Name nreg, OptoReg::Name nreg2) {
a61af66fc99e Initial load
duke
parents:
diff changeset
353 if (value[nreg] != val && val->is_Con() &&
a61af66fc99e Initial load
duke
parents:
diff changeset
354 value[nreg] != NULL && value[nreg]->is_Con() &&
a61af66fc99e Initial load
duke
parents:
diff changeset
355 (nreg2 == OptoReg::Bad || value[nreg] == value[nreg2]) &&
a61af66fc99e Initial load
duke
parents:
diff changeset
356 value[nreg]->bottom_type() == val->bottom_type() &&
a61af66fc99e Initial load
duke
parents:
diff changeset
357 value[nreg]->as_Mach()->rule() == val->as_Mach()->rule()) {
a61af66fc99e Initial load
duke
parents:
diff changeset
358 // This code assumes that two MachNodes representing constants
a61af66fc99e Initial load
duke
parents:
diff changeset
359 // which have the same rule and the same bottom type will produce
a61af66fc99e Initial load
duke
parents:
diff changeset
360 // identical effects into a register. This seems like it must be
a61af66fc99e Initial load
duke
parents:
diff changeset
361 // objectively true unless there are hidden inputs to the nodes
a61af66fc99e Initial load
duke
parents:
diff changeset
362 // but if that were to change this code would need to updated.
a61af66fc99e Initial load
duke
parents:
diff changeset
363 // Since they are equivalent the second one if redundant and can
a61af66fc99e Initial load
duke
parents:
diff changeset
364 // be removed.
a61af66fc99e Initial load
duke
parents:
diff changeset
365 //
70
b683f557224b 6661247: Internal bug in 32-bit HotSpot optimizer while bit manipulations
never
parents: 0
diff changeset
366 // n will be replaced with the old value but n might have
0
a61af66fc99e Initial load
duke
parents:
diff changeset
367 // kills projections associated with it so remove them now so that
605
98cb887364d3 6810672: Comment typos
twisti
parents: 400
diff changeset
368 // yank_if_dead will be able to eliminate the copy once the uses
0
a61af66fc99e Initial load
duke
parents:
diff changeset
369 // have been transferred to the old[value].
70
b683f557224b 6661247: Internal bug in 32-bit HotSpot optimizer while bit manipulations
never
parents: 0
diff changeset
370 for (DUIterator_Fast imax, i = n->fast_outs(imax); i < imax; i++) {
b683f557224b 6661247: Internal bug in 32-bit HotSpot optimizer while bit manipulations
never
parents: 0
diff changeset
371 Node* use = n->fast_out(i);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
372 if (use->is_Proj() && use->outcnt() == 0) {
a61af66fc99e Initial load
duke
parents:
diff changeset
373 // Kill projections have no users and one input
a61af66fc99e Initial load
duke
parents:
diff changeset
374 use->set_req(0, C->top());
a61af66fc99e Initial load
duke
parents:
diff changeset
375 yank_if_dead(use, current_block, &value, &regnd);
a61af66fc99e Initial load
duke
parents:
diff changeset
376 --i; --imax;
a61af66fc99e Initial load
duke
parents:
diff changeset
377 }
a61af66fc99e Initial load
duke
parents:
diff changeset
378 }
a61af66fc99e Initial load
duke
parents:
diff changeset
379 _post_alloc++;
a61af66fc99e Initial load
duke
parents:
diff changeset
380 return true;
a61af66fc99e Initial load
duke
parents:
diff changeset
381 }
a61af66fc99e Initial load
duke
parents:
diff changeset
382 return false;
a61af66fc99e Initial load
duke
parents:
diff changeset
383 }
a61af66fc99e Initial load
duke
parents:
diff changeset
384
a61af66fc99e Initial load
duke
parents:
diff changeset
385
a61af66fc99e Initial load
duke
parents:
diff changeset
386 //------------------------------post_allocate_copy_removal---------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
387 // Post-Allocation peephole copy removal. We do this in 1 pass over the
a61af66fc99e Initial load
duke
parents:
diff changeset
388 // basic blocks. We maintain a mapping of registers to Nodes (an array of
a61af66fc99e Initial load
duke
parents:
diff changeset
389 // Nodes indexed by machine register or stack slot number). NULL means that a
a61af66fc99e Initial load
duke
parents:
diff changeset
390 // register is not mapped to any Node. We can (want to have!) have several
a61af66fc99e Initial load
duke
parents:
diff changeset
391 // registers map to the same Node. We walk forward over the instructions
a61af66fc99e Initial load
duke
parents:
diff changeset
392 // updating the mapping as we go. At merge points we force a NULL if we have
a61af66fc99e Initial load
duke
parents:
diff changeset
393 // to merge 2 different Nodes into the same register. Phi functions will give
a61af66fc99e Initial load
duke
parents:
diff changeset
394 // us a new Node if there is a proper value merging. Since the blocks are
a61af66fc99e Initial load
duke
parents:
diff changeset
395 // arranged in some RPO, we will visit all parent blocks before visiting any
a61af66fc99e Initial load
duke
parents:
diff changeset
396 // successor blocks (except at loops).
a61af66fc99e Initial load
duke
parents:
diff changeset
397 //
a61af66fc99e Initial load
duke
parents:
diff changeset
398 // If we find a Copy we look to see if the Copy's source register is a stack
a61af66fc99e Initial load
duke
parents:
diff changeset
399 // slot and that value has already been loaded into some machine register; if
a61af66fc99e Initial load
duke
parents:
diff changeset
400 // so we use machine register directly. This turns a Load into a reg-reg
a61af66fc99e Initial load
duke
parents:
diff changeset
401 // Move. We also look for reloads of identical constants.
a61af66fc99e Initial load
duke
parents:
diff changeset
402 //
a61af66fc99e Initial load
duke
parents:
diff changeset
403 // When we see a use from a reg-reg Copy, we will attempt to use the copy's
a61af66fc99e Initial load
duke
parents:
diff changeset
404 // source directly and make the copy go dead.
a61af66fc99e Initial load
duke
parents:
diff changeset
405 void PhaseChaitin::post_allocate_copy_removal() {
a61af66fc99e Initial load
duke
parents:
diff changeset
406 NOT_PRODUCT( Compile::TracePhase t3("postAllocCopyRemoval", &_t_postAllocCopyRemoval, TimeCompiler); )
a61af66fc99e Initial load
duke
parents:
diff changeset
407 ResourceMark rm;
a61af66fc99e Initial load
duke
parents:
diff changeset
408
a61af66fc99e Initial load
duke
parents:
diff changeset
409 // Need a mapping from basic block Node_Lists. We need a Node_List to
a61af66fc99e Initial load
duke
parents:
diff changeset
410 // map from register number to value-producing Node.
12071
adb9a7d94cb5 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 12023
diff changeset
411 Node_List **blk2value = NEW_RESOURCE_ARRAY( Node_List *, _cfg.number_of_blocks() + 1);
adb9a7d94cb5 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 12023
diff changeset
412 memset(blk2value, 0, sizeof(Node_List*) * (_cfg.number_of_blocks() + 1));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
413 // Need a mapping from basic block Node_Lists. We need a Node_List to
a61af66fc99e Initial load
duke
parents:
diff changeset
414 // map from register number to register-defining Node.
12071
adb9a7d94cb5 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 12023
diff changeset
415 Node_List **blk2regnd = NEW_RESOURCE_ARRAY( Node_List *, _cfg.number_of_blocks() + 1);
adb9a7d94cb5 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 12023
diff changeset
416 memset(blk2regnd, 0, sizeof(Node_List*) * (_cfg.number_of_blocks() + 1));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
417
a61af66fc99e Initial load
duke
parents:
diff changeset
418 // We keep unused Node_Lists on a free_list to avoid wasting
a61af66fc99e Initial load
duke
parents:
diff changeset
419 // memory.
a61af66fc99e Initial load
duke
parents:
diff changeset
420 GrowableArray<Node_List*> free_list = GrowableArray<Node_List*>(16);
a61af66fc99e Initial load
duke
parents:
diff changeset
421
a61af66fc99e Initial load
duke
parents:
diff changeset
422 // For all blocks
12071
adb9a7d94cb5 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 12023
diff changeset
423 for (uint i = 0; i < _cfg.number_of_blocks(); i++) {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
424 uint j;
12071
adb9a7d94cb5 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 12023
diff changeset
425 Block* block = _cfg.get_block(i);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
426
a61af66fc99e Initial load
duke
parents:
diff changeset
427 // Count of Phis in block
a61af66fc99e Initial load
duke
parents:
diff changeset
428 uint phi_dex;
12167
650868c062a9 8023691: Create interface for nodes in class Block
adlertz
parents: 12071
diff changeset
429 for (phi_dex = 1; phi_dex < block->number_of_nodes(); phi_dex++) {
650868c062a9 8023691: Create interface for nodes in class Block
adlertz
parents: 12071
diff changeset
430 Node* phi = block->get_node(phi_dex);
12071
adb9a7d94cb5 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 12023
diff changeset
431 if (!phi->is_Phi()) {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
432 break;
12071
adb9a7d94cb5 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 12023
diff changeset
433 }
0
a61af66fc99e Initial load
duke
parents:
diff changeset
434 }
a61af66fc99e Initial load
duke
parents:
diff changeset
435
a61af66fc99e Initial load
duke
parents:
diff changeset
436 // If any predecessor has not been visited, we do not know the state
a61af66fc99e Initial load
duke
parents:
diff changeset
437 // of registers at the start. Check for this, while updating copies
a61af66fc99e Initial load
duke
parents:
diff changeset
438 // along Phi input edges
a61af66fc99e Initial load
duke
parents:
diff changeset
439 bool missing_some_inputs = false;
a61af66fc99e Initial load
duke
parents:
diff changeset
440 Block *freed = NULL;
12071
adb9a7d94cb5 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 12023
diff changeset
441 for (j = 1; j < block->num_preds(); j++) {
adb9a7d94cb5 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 12023
diff changeset
442 Block* pb = _cfg.get_block_for_node(block->pred(j));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
443 // Remove copies along phi edges
12071
adb9a7d94cb5 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 12023
diff changeset
444 for (uint k = 1; k < phi_dex; k++) {
12167
650868c062a9 8023691: Create interface for nodes in class Block
adlertz
parents: 12071
diff changeset
445 elide_copy(block->get_node(k), j, block, *blk2value[pb->_pre_order], *blk2regnd[pb->_pre_order], false);
12071
adb9a7d94cb5 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 12023
diff changeset
446 }
adb9a7d94cb5 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 12023
diff changeset
447 if (blk2value[pb->_pre_order]) { // Have a mapping on this edge?
0
a61af66fc99e Initial load
duke
parents:
diff changeset
448 // See if this predecessor's mappings have been used by everybody
a61af66fc99e Initial load
duke
parents:
diff changeset
449 // who wants them. If so, free 'em.
a61af66fc99e Initial load
duke
parents:
diff changeset
450 uint k;
12071
adb9a7d94cb5 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 12023
diff changeset
451 for (k = 0; k < pb->_num_succs; k++) {
adb9a7d94cb5 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 12023
diff changeset
452 Block* pbsucc = pb->_succs[k];
adb9a7d94cb5 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 12023
diff changeset
453 if (!blk2value[pbsucc->_pre_order] && pbsucc != block) {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
454 break; // Found a future user
12071
adb9a7d94cb5 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 12023
diff changeset
455 }
0
a61af66fc99e Initial load
duke
parents:
diff changeset
456 }
12071
adb9a7d94cb5 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 12023
diff changeset
457 if (k >= pb->_num_succs) { // No more uses, free!
0
a61af66fc99e Initial load
duke
parents:
diff changeset
458 freed = pb; // Record last block freed
a61af66fc99e Initial load
duke
parents:
diff changeset
459 free_list.push(blk2value[pb->_pre_order]);
a61af66fc99e Initial load
duke
parents:
diff changeset
460 free_list.push(blk2regnd[pb->_pre_order]);
a61af66fc99e Initial load
duke
parents:
diff changeset
461 }
a61af66fc99e Initial load
duke
parents:
diff changeset
462 } else { // This block has unvisited (loopback) inputs
a61af66fc99e Initial load
duke
parents:
diff changeset
463 missing_some_inputs = true;
a61af66fc99e Initial load
duke
parents:
diff changeset
464 }
a61af66fc99e Initial load
duke
parents:
diff changeset
465 }
a61af66fc99e Initial load
duke
parents:
diff changeset
466
a61af66fc99e Initial load
duke
parents:
diff changeset
467
a61af66fc99e Initial load
duke
parents:
diff changeset
468 // Extract Node_List mappings. If 'freed' is non-zero, we just popped
a61af66fc99e Initial load
duke
parents:
diff changeset
469 // 'freed's blocks off the list
a61af66fc99e Initial load
duke
parents:
diff changeset
470 Node_List &regnd = *(free_list.is_empty() ? new Node_List() : free_list.pop());
a61af66fc99e Initial load
duke
parents:
diff changeset
471 Node_List &value = *(free_list.is_empty() ? new Node_List() : free_list.pop());
a61af66fc99e Initial load
duke
parents:
diff changeset
472 assert( !freed || blk2value[freed->_pre_order] == &value, "" );
a61af66fc99e Initial load
duke
parents:
diff changeset
473 value.map(_max_reg,NULL);
a61af66fc99e Initial load
duke
parents:
diff changeset
474 regnd.map(_max_reg,NULL);
a61af66fc99e Initial load
duke
parents:
diff changeset
475 // Set mappings as OUR mappings
12071
adb9a7d94cb5 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 12023
diff changeset
476 blk2value[block->_pre_order] = &value;
adb9a7d94cb5 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 12023
diff changeset
477 blk2regnd[block->_pre_order] = &regnd;
0
a61af66fc99e Initial load
duke
parents:
diff changeset
478
a61af66fc99e Initial load
duke
parents:
diff changeset
479 // Initialize value & regnd for this block
12071
adb9a7d94cb5 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 12023
diff changeset
480 if (missing_some_inputs) {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
481 // Some predecessor has not yet been visited; zap map to empty
12071
adb9a7d94cb5 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 12023
diff changeset
482 for (uint k = 0; k < (uint)_max_reg; k++) {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
483 value.map(k,NULL);
a61af66fc99e Initial load
duke
parents:
diff changeset
484 regnd.map(k,NULL);
a61af66fc99e Initial load
duke
parents:
diff changeset
485 }
a61af66fc99e Initial load
duke
parents:
diff changeset
486 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
487 if( !freed ) { // Didn't get a freebie prior block
a61af66fc99e Initial load
duke
parents:
diff changeset
488 // Must clone some data
12071
adb9a7d94cb5 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 12023
diff changeset
489 freed = _cfg.get_block_for_node(block->pred(1));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
490 Node_List &f_value = *blk2value[freed->_pre_order];
a61af66fc99e Initial load
duke
parents:
diff changeset
491 Node_List &f_regnd = *blk2regnd[freed->_pre_order];
a61af66fc99e Initial load
duke
parents:
diff changeset
492 for( uint k = 0; k < (uint)_max_reg; k++ ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
493 value.map(k,f_value[k]);
a61af66fc99e Initial load
duke
parents:
diff changeset
494 regnd.map(k,f_regnd[k]);
a61af66fc99e Initial load
duke
parents:
diff changeset
495 }
a61af66fc99e Initial load
duke
parents:
diff changeset
496 }
a61af66fc99e Initial load
duke
parents:
diff changeset
497 // Merge all inputs together, setting to NULL any conflicts.
12071
adb9a7d94cb5 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 12023
diff changeset
498 for (j = 1; j < block->num_preds(); j++) {
adb9a7d94cb5 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 12023
diff changeset
499 Block* pb = _cfg.get_block_for_node(block->pred(j));
adb9a7d94cb5 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 12023
diff changeset
500 if (pb == freed) {
adb9a7d94cb5 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 12023
diff changeset
501 continue; // Did self already via freelist
adb9a7d94cb5 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 12023
diff changeset
502 }
0
a61af66fc99e Initial load
duke
parents:
diff changeset
503 Node_List &p_regnd = *blk2regnd[pb->_pre_order];
a61af66fc99e Initial load
duke
parents:
diff changeset
504 for( uint k = 0; k < (uint)_max_reg; k++ ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
505 if( regnd[k] != p_regnd[k] ) { // Conflict on reaching defs?
a61af66fc99e Initial load
duke
parents:
diff changeset
506 value.map(k,NULL); // Then no value handy
a61af66fc99e Initial load
duke
parents:
diff changeset
507 regnd.map(k,NULL);
a61af66fc99e Initial load
duke
parents:
diff changeset
508 }
a61af66fc99e Initial load
duke
parents:
diff changeset
509 }
a61af66fc99e Initial load
duke
parents:
diff changeset
510 }
a61af66fc99e Initial load
duke
parents:
diff changeset
511 }
a61af66fc99e Initial load
duke
parents:
diff changeset
512
a61af66fc99e Initial load
duke
parents:
diff changeset
513 // For all Phi's
12071
adb9a7d94cb5 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 12023
diff changeset
514 for (j = 1; j < phi_dex; j++) {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
515 uint k;
12167
650868c062a9 8023691: Create interface for nodes in class Block
adlertz
parents: 12071
diff changeset
516 Node *phi = block->get_node(j);
10111
8373c19be854 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 7196
diff changeset
517 uint pidx = _lrg_map.live_range_id(phi);
8373c19be854 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 7196
diff changeset
518 OptoReg::Name preg = lrgs(_lrg_map.live_range_id(phi)).reg();
0
a61af66fc99e Initial load
duke
parents:
diff changeset
519
a61af66fc99e Initial load
duke
parents:
diff changeset
520 // Remove copies remaining on edges. Check for junk phi.
a61af66fc99e Initial load
duke
parents:
diff changeset
521 Node *u = NULL;
10111
8373c19be854 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 7196
diff changeset
522 for (k = 1; k < phi->req(); k++) {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
523 Node *x = phi->in(k);
a61af66fc99e Initial load
duke
parents:
diff changeset
524 if( phi != x && u != x ) // Found a different input
a61af66fc99e Initial load
duke
parents:
diff changeset
525 u = u ? NodeSentinel : x; // Capture unique input, or NodeSentinel for 2nd input
a61af66fc99e Initial load
duke
parents:
diff changeset
526 }
12071
adb9a7d94cb5 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 12023
diff changeset
527 if (u != NodeSentinel) { // Junk Phi. Remove
13012
f01788f13696 8026940: assert(n->outcnt() != 0 || C->top() == n || n->is_Proj()) failed: No dead instructions after post-alloc
adlertz
parents: 12167
diff changeset
528 phi->replace_by(u);
f01788f13696 8026940: assert(n->outcnt() != 0 || C->top() == n || n->is_Proj()) failed: No dead instructions after post-alloc
adlertz
parents: 12167
diff changeset
529 j -= yank_if_dead(phi, block, &value, &regnd);
12023
d1034bd8cefc 8022284: Hide internal data structure in PhaseCFG
adlertz
parents: 10111
diff changeset
530 phi_dex--;
0
a61af66fc99e Initial load
duke
parents:
diff changeset
531 continue;
a61af66fc99e Initial load
duke
parents:
diff changeset
532 }
a61af66fc99e Initial load
duke
parents:
diff changeset
533 // Note that if value[pidx] exists, then we merged no new values here
a61af66fc99e Initial load
duke
parents:
diff changeset
534 // and the phi is useless. This can happen even with the above phi
a61af66fc99e Initial load
duke
parents:
diff changeset
535 // removal for complex flows. I cannot keep the better known value here
a61af66fc99e Initial load
duke
parents:
diff changeset
536 // because locally the phi appears to define a new merged value. If I
a61af66fc99e Initial load
duke
parents:
diff changeset
537 // keep the better value then a copy of the phi, being unable to use the
a61af66fc99e Initial load
duke
parents:
diff changeset
538 // global flow analysis, can't "peek through" the phi to the original
a61af66fc99e Initial load
duke
parents:
diff changeset
539 // reaching value and so will act like it's defining a new value. This
a61af66fc99e Initial load
duke
parents:
diff changeset
540 // can lead to situations where some uses are from the old and some from
a61af66fc99e Initial load
duke
parents:
diff changeset
541 // the new values. Not illegal by itself but throws the over-strong
a61af66fc99e Initial load
duke
parents:
diff changeset
542 // assert in scheduling.
a61af66fc99e Initial load
duke
parents:
diff changeset
543 if( pidx ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
544 value.map(preg,phi);
a61af66fc99e Initial load
duke
parents:
diff changeset
545 regnd.map(preg,phi);
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 4776
diff changeset
546 int n_regs = RegMask::num_registers(phi->ideal_reg());
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 4776
diff changeset
547 for (int l = 1; l < n_regs; l++) {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 4776
diff changeset
548 OptoReg::Name preg_lo = OptoReg::add(preg,-l);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
549 value.map(preg_lo,phi);
a61af66fc99e Initial load
duke
parents:
diff changeset
550 regnd.map(preg_lo,phi);
a61af66fc99e Initial load
duke
parents:
diff changeset
551 }
a61af66fc99e Initial load
duke
parents:
diff changeset
552 }
a61af66fc99e Initial load
duke
parents:
diff changeset
553 }
a61af66fc99e Initial load
duke
parents:
diff changeset
554
a61af66fc99e Initial load
duke
parents:
diff changeset
555 // For all remaining instructions
12167
650868c062a9 8023691: Create interface for nodes in class Block
adlertz
parents: 12071
diff changeset
556 for (j = phi_dex; j < block->number_of_nodes(); j++) {
650868c062a9 8023691: Create interface for nodes in class Block
adlertz
parents: 12071
diff changeset
557 Node* n = block->get_node(j);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
558
12071
adb9a7d94cb5 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 12023
diff changeset
559 if(n->outcnt() == 0 && // Dead?
adb9a7d94cb5 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 12023
diff changeset
560 n != C->top() && // (ignore TOP, it has no du info)
adb9a7d94cb5 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 12023
diff changeset
561 !n->is_Proj() ) { // fat-proj kills
adb9a7d94cb5 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 12023
diff changeset
562 j -= yank_if_dead(n, block, &value, &regnd);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
563 continue;
a61af66fc99e Initial load
duke
parents:
diff changeset
564 }
a61af66fc99e Initial load
duke
parents:
diff changeset
565
a61af66fc99e Initial load
duke
parents:
diff changeset
566 // Improve reaching-def info. Occasionally post-alloc's liveness gives
a61af66fc99e Initial load
duke
parents:
diff changeset
567 // up (at loop backedges, because we aren't doing a full flow pass).
a61af66fc99e Initial load
duke
parents:
diff changeset
568 // The presence of a live use essentially asserts that the use's def is
a61af66fc99e Initial load
duke
parents:
diff changeset
569 // alive and well at the use (or else the allocator fubar'd). Take
a61af66fc99e Initial load
duke
parents:
diff changeset
570 // advantage of this info to set a reaching def for the use-reg.
a61af66fc99e Initial load
duke
parents:
diff changeset
571 uint k;
10111
8373c19be854 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 7196
diff changeset
572 for (k = 1; k < n->req(); k++) {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
573 Node *def = n->in(k); // n->in(k) is a USE; def is the DEF for this USE
a61af66fc99e Initial load
duke
parents:
diff changeset
574 guarantee(def != NULL, "no disconnected nodes at this point");
10111
8373c19be854 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 7196
diff changeset
575 uint useidx = _lrg_map.live_range_id(def); // useidx is the live range index for this USE
0
a61af66fc99e Initial load
duke
parents:
diff changeset
576
a61af66fc99e Initial load
duke
parents:
diff changeset
577 if( useidx ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
578 OptoReg::Name ureg = lrgs(useidx).reg();
a61af66fc99e Initial load
duke
parents:
diff changeset
579 if( !value[ureg] ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
580 int idx; // Skip occasional useless copy
a61af66fc99e Initial load
duke
parents:
diff changeset
581 while( (idx=def->is_Copy()) != 0 &&
a61af66fc99e Initial load
duke
parents:
diff changeset
582 def->in(idx) != NULL && // NULL should not happen
10111
8373c19be854 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 7196
diff changeset
583 ureg == lrgs(_lrg_map.live_range_id(def->in(idx))).reg())
0
a61af66fc99e Initial load
duke
parents:
diff changeset
584 def = def->in(idx);
a61af66fc99e Initial load
duke
parents:
diff changeset
585 Node *valdef = skip_copies(def); // tighten up val through non-useless copies
a61af66fc99e Initial load
duke
parents:
diff changeset
586 value.map(ureg,valdef); // record improved reaching-def info
a61af66fc99e Initial load
duke
parents:
diff changeset
587 regnd.map(ureg, def);
a61af66fc99e Initial load
duke
parents:
diff changeset
588 // Record other half of doubles
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 4776
diff changeset
589 uint def_ideal_reg = def->ideal_reg();
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 4776
diff changeset
590 int n_regs = RegMask::num_registers(def_ideal_reg);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 4776
diff changeset
591 for (int l = 1; l < n_regs; l++) {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 4776
diff changeset
592 OptoReg::Name ureg_lo = OptoReg::add(ureg,-l);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 4776
diff changeset
593 if (!value[ureg_lo] &&
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 4776
diff changeset
594 (!RegMask::can_represent(ureg_lo) ||
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 4776
diff changeset
595 lrgs(useidx).mask().Member(ureg_lo))) { // Nearly always adjacent
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 4776
diff changeset
596 value.map(ureg_lo,valdef); // record improved reaching-def info
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 4776
diff changeset
597 regnd.map(ureg_lo, def);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 4776
diff changeset
598 }
0
a61af66fc99e Initial load
duke
parents:
diff changeset
599 }
a61af66fc99e Initial load
duke
parents:
diff changeset
600 }
a61af66fc99e Initial load
duke
parents:
diff changeset
601 }
a61af66fc99e Initial load
duke
parents:
diff changeset
602 }
a61af66fc99e Initial load
duke
parents:
diff changeset
603
a61af66fc99e Initial load
duke
parents:
diff changeset
604 const uint two_adr = n->is_Mach() ? n->as_Mach()->two_adr() : 0;
a61af66fc99e Initial load
duke
parents:
diff changeset
605
a61af66fc99e Initial load
duke
parents:
diff changeset
606 // Remove copies along input edges
12071
adb9a7d94cb5 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 12023
diff changeset
607 for (k = 1; k < n->req(); k++) {
adb9a7d94cb5 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 12023
diff changeset
608 j -= elide_copy(n, k, block, value, regnd, two_adr != k);
adb9a7d94cb5 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 12023
diff changeset
609 }
0
a61af66fc99e Initial load
duke
parents:
diff changeset
610
a61af66fc99e Initial load
duke
parents:
diff changeset
611 // Unallocated Nodes define no registers
10111
8373c19be854 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 7196
diff changeset
612 uint lidx = _lrg_map.live_range_id(n);
8373c19be854 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 7196
diff changeset
613 if (!lidx) {
8373c19be854 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 7196
diff changeset
614 continue;
8373c19be854 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 7196
diff changeset
615 }
0
a61af66fc99e Initial load
duke
parents:
diff changeset
616
a61af66fc99e Initial load
duke
parents:
diff changeset
617 // Update the register defined by this instruction
a61af66fc99e Initial load
duke
parents:
diff changeset
618 OptoReg::Name nreg = lrgs(lidx).reg();
a61af66fc99e Initial load
duke
parents:
diff changeset
619 // Skip through all copies to the _value_ being defined.
a61af66fc99e Initial load
duke
parents:
diff changeset
620 // Do not change from int to pointer
a61af66fc99e Initial load
duke
parents:
diff changeset
621 Node *val = skip_copies(n);
a61af66fc99e Initial load
duke
parents:
diff changeset
622
923
a70508bb21c3 6862863: C2 compiler fails in elide_copy()
never
parents: 605
diff changeset
623 // Clear out a dead definition before starting so that the
a70508bb21c3 6862863: C2 compiler fails in elide_copy()
never
parents: 605
diff changeset
624 // elimination code doesn't have to guard against it. The
a70508bb21c3 6862863: C2 compiler fails in elide_copy()
never
parents: 605
diff changeset
625 // definition could in fact be a kill projection with a count of
a70508bb21c3 6862863: C2 compiler fails in elide_copy()
never
parents: 605
diff changeset
626 // 0 which is safe but since those are uninteresting for copy
a70508bb21c3 6862863: C2 compiler fails in elide_copy()
never
parents: 605
diff changeset
627 // elimination just delete them as well.
a70508bb21c3 6862863: C2 compiler fails in elide_copy()
never
parents: 605
diff changeset
628 if (regnd[nreg] != NULL && regnd[nreg]->outcnt() == 0) {
a70508bb21c3 6862863: C2 compiler fails in elide_copy()
never
parents: 605
diff changeset
629 regnd.map(nreg, NULL);
a70508bb21c3 6862863: C2 compiler fails in elide_copy()
never
parents: 605
diff changeset
630 value.map(nreg, NULL);
a70508bb21c3 6862863: C2 compiler fails in elide_copy()
never
parents: 605
diff changeset
631 }
a70508bb21c3 6862863: C2 compiler fails in elide_copy()
never
parents: 605
diff changeset
632
0
a61af66fc99e Initial load
duke
parents:
diff changeset
633 uint n_ideal_reg = n->ideal_reg();
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 4776
diff changeset
634 int n_regs = RegMask::num_registers(n_ideal_reg);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 4776
diff changeset
635 if (n_regs == 1) {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
636 // If Node 'n' does not change the value mapped by the register,
a61af66fc99e Initial load
duke
parents:
diff changeset
637 // then 'n' is a useless copy. Do not update the register->node
a61af66fc99e Initial load
duke
parents:
diff changeset
638 // mapping so 'n' will go dead.
a61af66fc99e Initial load
duke
parents:
diff changeset
639 if( value[nreg] != val ) {
12071
adb9a7d94cb5 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 12023
diff changeset
640 if (eliminate_copy_of_constant(val, n, block, value, regnd, nreg, OptoReg::Bad)) {
adb9a7d94cb5 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 12023
diff changeset
641 j -= replace_and_yank_if_dead(n, nreg, block, value, regnd);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
642 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
643 // Update the mapping: record new Node defined by the register
a61af66fc99e Initial load
duke
parents:
diff changeset
644 regnd.map(nreg,n);
a61af66fc99e Initial load
duke
parents:
diff changeset
645 // Update mapping for defined *value*, which is the defined
a61af66fc99e Initial load
duke
parents:
diff changeset
646 // Node after skipping all copies.
a61af66fc99e Initial load
duke
parents:
diff changeset
647 value.map(nreg,val);
a61af66fc99e Initial load
duke
parents:
diff changeset
648 }
923
a70508bb21c3 6862863: C2 compiler fails in elide_copy()
never
parents: 605
diff changeset
649 } else if( !may_be_copy_of_callee(n) ) {
12071
adb9a7d94cb5 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 12023
diff changeset
650 assert(n->is_Copy(), "");
adb9a7d94cb5 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 12023
diff changeset
651 j -= replace_and_yank_if_dead(n, nreg, block, value, regnd);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
652 }
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 4776
diff changeset
653 } else if (RegMask::is_vector(n_ideal_reg)) {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 4776
diff changeset
654 // If Node 'n' does not change the value mapped by the register,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 4776
diff changeset
655 // then 'n' is a useless copy. Do not update the register->node
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 4776
diff changeset
656 // mapping so 'n' will go dead.
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 4776
diff changeset
657 if (!register_contains_value(val, nreg, n_regs, value)) {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 4776
diff changeset
658 // Update the mapping: record new Node defined by the register
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 4776
diff changeset
659 regnd.map(nreg,n);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 4776
diff changeset
660 // Update mapping for defined *value*, which is the defined
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 4776
diff changeset
661 // Node after skipping all copies.
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 4776
diff changeset
662 value.map(nreg,val);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 4776
diff changeset
663 for (int l = 1; l < n_regs; l++) {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 4776
diff changeset
664 OptoReg::Name nreg_lo = OptoReg::add(nreg,-l);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 4776
diff changeset
665 regnd.map(nreg_lo, n );
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 4776
diff changeset
666 value.map(nreg_lo,val);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 4776
diff changeset
667 }
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 4776
diff changeset
668 } else if (n->is_Copy()) {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 4776
diff changeset
669 // Note: vector can't be constant and can't be copy of calee.
12071
adb9a7d94cb5 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 12023
diff changeset
670 j -= replace_and_yank_if_dead(n, nreg, block, value, regnd);
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 4776
diff changeset
671 }
0
a61af66fc99e Initial load
duke
parents:
diff changeset
672 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
673 // If the value occupies a register pair, record same info
a61af66fc99e Initial load
duke
parents:
diff changeset
674 // in both registers.
a61af66fc99e Initial load
duke
parents:
diff changeset
675 OptoReg::Name nreg_lo = OptoReg::add(nreg,-1);
a61af66fc99e Initial load
duke
parents:
diff changeset
676 if( RegMask::can_represent(nreg_lo) && // Either a spill slot, or
a61af66fc99e Initial load
duke
parents:
diff changeset
677 !lrgs(lidx).mask().Member(nreg_lo) ) { // Nearly always adjacent
a61af66fc99e Initial load
duke
parents:
diff changeset
678 // Sparc occasionally has non-adjacent pairs.
a61af66fc99e Initial load
duke
parents:
diff changeset
679 // Find the actual other value
a61af66fc99e Initial load
duke
parents:
diff changeset
680 RegMask tmp = lrgs(lidx).mask();
a61af66fc99e Initial load
duke
parents:
diff changeset
681 tmp.Remove(nreg);
a61af66fc99e Initial load
duke
parents:
diff changeset
682 nreg_lo = tmp.find_first_elem();
a61af66fc99e Initial load
duke
parents:
diff changeset
683 }
12071
adb9a7d94cb5 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 12023
diff changeset
684 if (value[nreg] != val || value[nreg_lo] != val) {
adb9a7d94cb5 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 12023
diff changeset
685 if (eliminate_copy_of_constant(val, n, block, value, regnd, nreg, nreg_lo)) {
adb9a7d94cb5 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 12023
diff changeset
686 j -= replace_and_yank_if_dead(n, nreg, block, value, regnd);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
687 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
688 regnd.map(nreg , n );
a61af66fc99e Initial load
duke
parents:
diff changeset
689 regnd.map(nreg_lo, n );
a61af66fc99e Initial load
duke
parents:
diff changeset
690 value.map(nreg ,val);
a61af66fc99e Initial load
duke
parents:
diff changeset
691 value.map(nreg_lo,val);
a61af66fc99e Initial load
duke
parents:
diff changeset
692 }
12071
adb9a7d94cb5 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 12023
diff changeset
693 } else if (!may_be_copy_of_callee(n)) {
adb9a7d94cb5 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 12023
diff changeset
694 assert(n->is_Copy(), "");
adb9a7d94cb5 8023003: Cleanup the public interface to PhaseCFG
adlertz
parents: 12023
diff changeset
695 j -= replace_and_yank_if_dead(n, nreg, block, value, regnd);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
696 }
a61af66fc99e Initial load
duke
parents:
diff changeset
697 }
a61af66fc99e Initial load
duke
parents:
diff changeset
698
a61af66fc99e Initial load
duke
parents:
diff changeset
699 // Fat projections kill many registers
a61af66fc99e Initial load
duke
parents:
diff changeset
700 if( n_ideal_reg == MachProjNode::fat_proj ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
701 RegMask rm = n->out_RegMask();
a61af66fc99e Initial load
duke
parents:
diff changeset
702 // wow, what an expensive iterator...
a61af66fc99e Initial load
duke
parents:
diff changeset
703 nreg = rm.find_first_elem();
a61af66fc99e Initial load
duke
parents:
diff changeset
704 while( OptoReg::is_valid(nreg)) {
a61af66fc99e Initial load
duke
parents:
diff changeset
705 rm.Remove(nreg);
a61af66fc99e Initial load
duke
parents:
diff changeset
706 value.map(nreg,n);
a61af66fc99e Initial load
duke
parents:
diff changeset
707 regnd.map(nreg,n);
a61af66fc99e Initial load
duke
parents:
diff changeset
708 nreg = rm.find_first_elem();
a61af66fc99e Initial load
duke
parents:
diff changeset
709 }
a61af66fc99e Initial load
duke
parents:
diff changeset
710 }
a61af66fc99e Initial load
duke
parents:
diff changeset
711
a61af66fc99e Initial load
duke
parents:
diff changeset
712 } // End of for all instructions in the block
a61af66fc99e Initial load
duke
parents:
diff changeset
713
a61af66fc99e Initial load
duke
parents:
diff changeset
714 } // End for all blocks
a61af66fc99e Initial load
duke
parents:
diff changeset
715 }