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annotate graal/com.oracle.graal.asm.amd64.test/src/com/oracle/graal/asm/amd64/test/BitOpsTest.java @ 19867:89c729e9e0a4

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Refactoring of AMD64 code generation.
author Roland Schatz <roland.schatz@oracle.com>
date Mon, 16 Mar 2015 15:12:22 +0100
parents 6dc4f0be9a70
children 5e868236654f
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1 /*
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2 * Copyright (c) 2013, 2015, Oracle and/or its affiliates. All rights reserved.
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3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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4 *
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5 * This code is free software; you can redistribute it and/or modify it
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6 * under the terms of the GNU General Public License version 2 only, as
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7 * published by the Free Software Foundation.
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8 *
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9 * This code is distributed in the hope that it will be useful, but WITHOUT
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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12 * version 2 for more details (a copy is included in the LICENSE file that
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13 * accompanied this code).
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14 *
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15 * You should have received a copy of the GNU General Public License version
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16 * 2 along with this work; if not, write to the Free Software Foundation,
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17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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18 *
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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20 * or visit www.oracle.com if you need additional information or have any
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21 * questions.
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22 */
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23
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24 package com.oracle.graal.asm.amd64.test;
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25
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26 import static com.oracle.graal.api.code.ValueUtil.*;
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27 import static com.oracle.graal.asm.amd64.AMD64Assembler.AMD64RMOp.*;
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28 import static com.oracle.graal.asm.amd64.AMD64Assembler.OperandSize.*;
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29 import static com.oracle.graal.compiler.common.UnsafeAccess.*;
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30 import static org.junit.Assume.*;
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31
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32 import java.lang.reflect.*;
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33 import java.util.*;
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34
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35 import org.junit.*;
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36
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37 import com.oracle.graal.amd64.*;
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38 import com.oracle.graal.amd64.AMD64.CPUFeature;
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39 import com.oracle.graal.api.code.*;
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40 import com.oracle.graal.api.meta.*;
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41 import com.oracle.graal.asm.amd64.*;
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42 import com.oracle.graal.asm.test.*;
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43
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44 public class BitOpsTest extends AssemblerTest {
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45 private static boolean lzcntSupported;
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46 private static boolean tzcntSupported;
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47
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48 @Before
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49 public void checkAMD64() {
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50 assumeTrue("skipping AMD64 specific test", codeCache.getTarget().arch instanceof AMD64);
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51 EnumSet<CPUFeature> features = ((AMD64) codeCache.getTarget().arch).getFeatures();
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52 lzcntSupported = features.contains(CPUFeature.LZCNT);
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53 tzcntSupported = features.contains(CPUFeature.BMI1);
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54 }
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55
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56 @Test
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57 public void lzcntlTest() {
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58 if (lzcntSupported) {
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59 CodeGenTest test = new CodeGenTest() {
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60
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61 @Override
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62 public byte[] generateCode(CompilationResult compResult, TargetDescription target, RegisterConfig registerConfig, CallingConvention cc) {
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63 AMD64Assembler asm = new AMD64Assembler(target, registerConfig);
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64 Register ret = registerConfig.getReturnRegister(Kind.Int);
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65 Register arg = asRegister(cc.getArgument(0));
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66 LZCNT.emit(asm, DWORD, ret, arg);
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67 asm.ret(0);
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68 return asm.close(true);
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69 }
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70 };
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71 assertReturn("intStub", test, 31, 1);
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72 }
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73 }
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74
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75 @Test
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76 public void lzcntlMemTest() {
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77 if (lzcntSupported) {
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78 CodeGenTest test = new CodeGenTest() {
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79
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80 @Override
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81 public byte[] generateCode(CompilationResult compResult, TargetDescription target, RegisterConfig registerConfig, CallingConvention cc) {
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82 AMD64Assembler asm = new AMD64Assembler(target, registerConfig);
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83 Register ret = registerConfig.getReturnRegister(Kind.Int);
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84 try {
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85 Field f = IntField.class.getDeclaredField("x");
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86 AMD64Address arg = new AMD64Address(asRegister(cc.getArgument(0)), (int) unsafe.objectFieldOffset(f));
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87 LZCNT.emit(asm, DWORD, ret, arg);
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88 asm.ret(0);
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89 return asm.close(true);
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90 } catch (Exception e) {
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91 throw new RuntimeException("exception while trying to generate field access:", e);
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92 }
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93 }
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94 };
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95 assertReturn("intFieldStub", test, 31, new IntField(1));
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96 }
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97 }
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98
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99 @Test
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100 public void lzcntqTest() {
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101 if (lzcntSupported) {
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102 CodeGenTest test = new CodeGenTest() {
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103
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104 @Override
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105 public byte[] generateCode(CompilationResult compResult, TargetDescription target, RegisterConfig registerConfig, CallingConvention cc) {
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106 AMD64Assembler asm = new AMD64Assembler(target, registerConfig);
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107 Register ret = registerConfig.getReturnRegister(Kind.Int);
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108 Register arg = asRegister(cc.getArgument(0));
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109 LZCNT.emit(asm, QWORD, ret, arg);
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110 asm.ret(0);
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111 return asm.close(true);
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112 }
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113 };
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114 assertReturn("longStub", test, 63, 1L);
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115 }
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116 }
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117
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118 @Test
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119 public void lzcntqMemTest() {
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120 if (lzcntSupported) {
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121 CodeGenTest test = new CodeGenTest() {
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122
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123 @Override
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124 public byte[] generateCode(CompilationResult compResult, TargetDescription target, RegisterConfig registerConfig, CallingConvention cc) {
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125 AMD64Assembler asm = new AMD64Assembler(target, registerConfig);
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126 Register ret = registerConfig.getReturnRegister(Kind.Int);
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127 try {
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128 Field f = LongField.class.getDeclaredField("x");
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129 AMD64Address arg = new AMD64Address(asRegister(cc.getArgument(0)), (int) unsafe.objectFieldOffset(f));
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diff changeset
130 LZCNT.emit(asm, QWORD, ret, arg);
18415
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diff changeset
131 asm.ret(0);
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diff changeset
132 return asm.close(true);
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diff changeset
133 } catch (Exception e) {
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diff changeset
134 throw new RuntimeException("exception while trying to generate field access:", e);
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135 }
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diff changeset
136 }
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diff changeset
137 };
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parents:
diff changeset
138 assertReturn("longFieldStub", test, 63, new LongField(1));
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139 }
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parents:
diff changeset
140 }
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parents:
diff changeset
141
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diff changeset
142 @Test
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diff changeset
143 public void tzcntlTest() {
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diff changeset
144 if (tzcntSupported) {
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diff changeset
145 CodeGenTest test = new CodeGenTest() {
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parents:
diff changeset
146
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diff changeset
147 @Override
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diff changeset
148 public byte[] generateCode(CompilationResult compResult, TargetDescription target, RegisterConfig registerConfig, CallingConvention cc) {
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diff changeset
149 AMD64Assembler asm = new AMD64Assembler(target, registerConfig);
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diff changeset
150 Register ret = registerConfig.getReturnRegister(Kind.Int);
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diff changeset
151 Register arg = asRegister(cc.getArgument(0));
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diff changeset
152 TZCNT.emit(asm, DWORD, ret, arg);
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153 asm.ret(0);
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diff changeset
154 return asm.close(true);
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diff changeset
155 }
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diff changeset
156 };
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parents:
diff changeset
157 assertReturn("intStub", test, 31, 0x8000_0000);
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158 }
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159 }
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diff changeset
160
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diff changeset
161 @Test
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diff changeset
162 public void tzcntlMemTest() {
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diff changeset
163 if (tzcntSupported) {
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diff changeset
164 CodeGenTest test = new CodeGenTest() {
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diff changeset
165
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diff changeset
166 @Override
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diff changeset
167 public byte[] generateCode(CompilationResult compResult, TargetDescription target, RegisterConfig registerConfig, CallingConvention cc) {
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diff changeset
168 AMD64Assembler asm = new AMD64Assembler(target, registerConfig);
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diff changeset
169 Register ret = registerConfig.getReturnRegister(Kind.Int);
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diff changeset
170 try {
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diff changeset
171 Field f = IntField.class.getDeclaredField("x");
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diff changeset
172 AMD64Address arg = new AMD64Address(asRegister(cc.getArgument(0)), (int) unsafe.objectFieldOffset(f));
19867
89c729e9e0a4 Refactoring of AMD64 code generation.
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diff changeset
173 TZCNT.emit(asm, DWORD, ret, arg);
18415
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diff changeset
174 asm.ret(0);
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diff changeset
175 return asm.close(true);
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parents:
diff changeset
176 } catch (Exception e) {
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diff changeset
177 throw new RuntimeException("exception while trying to generate field access:", e);
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diff changeset
178 }
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parents:
diff changeset
179 }
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diff changeset
180 };
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parents:
diff changeset
181 assertReturn("intFieldStub", test, 31, new IntField(0x8000_0000));
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diff changeset
182 }
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parents:
diff changeset
183 }
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parents:
diff changeset
184
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diff changeset
185 @Test
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diff changeset
186 public void tzcntqTest() {
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diff changeset
187 if (tzcntSupported) {
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diff changeset
188 CodeGenTest test = new CodeGenTest() {
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parents:
diff changeset
189
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diff changeset
190 @Override
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parents:
diff changeset
191 public byte[] generateCode(CompilationResult compResult, TargetDescription target, RegisterConfig registerConfig, CallingConvention cc) {
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parents:
diff changeset
192 AMD64Assembler asm = new AMD64Assembler(target, registerConfig);
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parents:
diff changeset
193 Register ret = registerConfig.getReturnRegister(Kind.Int);
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parents:
diff changeset
194 Register arg = asRegister(cc.getArgument(0));
19867
89c729e9e0a4 Refactoring of AMD64 code generation.
Roland Schatz <roland.schatz@oracle.com>
parents: 18415
diff changeset
195 TZCNT.emit(asm, QWORD, ret, arg);
18415
6dc4f0be9a70 Add support of lzcnt and tzcnt
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diff changeset
196 asm.ret(0);
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diff changeset
197 return asm.close(true);
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diff changeset
198 }
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diff changeset
199 };
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parents:
diff changeset
200 assertReturn("longStub", test, 63, 0x8000_0000_0000_0000L);
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parents:
diff changeset
201 }
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parents:
diff changeset
202 }
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parents:
diff changeset
203
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parents:
diff changeset
204 @Test
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Gilles Duboscq <duboscq@ssw.jku.at>
parents:
diff changeset
205 public void tzcntqMemTest() {
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Gilles Duboscq <duboscq@ssw.jku.at>
parents:
diff changeset
206 if (tzcntSupported) {
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parents:
diff changeset
207 CodeGenTest test = new CodeGenTest() {
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parents:
diff changeset
208
6dc4f0be9a70 Add support of lzcnt and tzcnt
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parents:
diff changeset
209 @Override
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Gilles Duboscq <duboscq@ssw.jku.at>
parents:
diff changeset
210 public byte[] generateCode(CompilationResult compResult, TargetDescription target, RegisterConfig registerConfig, CallingConvention cc) {
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parents:
diff changeset
211 AMD64Assembler asm = new AMD64Assembler(target, registerConfig);
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Gilles Duboscq <duboscq@ssw.jku.at>
parents:
diff changeset
212 Register ret = registerConfig.getReturnRegister(Kind.Int);
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Gilles Duboscq <duboscq@ssw.jku.at>
parents:
diff changeset
213 try {
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parents:
diff changeset
214 Field f = LongField.class.getDeclaredField("x");
6dc4f0be9a70 Add support of lzcnt and tzcnt
Gilles Duboscq <duboscq@ssw.jku.at>
parents:
diff changeset
215 AMD64Address arg = new AMD64Address(asRegister(cc.getArgument(0)), (int) unsafe.objectFieldOffset(f));
19867
89c729e9e0a4 Refactoring of AMD64 code generation.
Roland Schatz <roland.schatz@oracle.com>
parents: 18415
diff changeset
216 TZCNT.emit(asm, QWORD, ret, arg);
18415
6dc4f0be9a70 Add support of lzcnt and tzcnt
Gilles Duboscq <duboscq@ssw.jku.at>
parents:
diff changeset
217 asm.ret(0);
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parents:
diff changeset
218 return asm.close(true);
6dc4f0be9a70 Add support of lzcnt and tzcnt
Gilles Duboscq <duboscq@ssw.jku.at>
parents:
diff changeset
219 } catch (Exception e) {
6dc4f0be9a70 Add support of lzcnt and tzcnt
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parents:
diff changeset
220 throw new RuntimeException("exception while trying to generate field access:", e);
6dc4f0be9a70 Add support of lzcnt and tzcnt
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parents:
diff changeset
221 }
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parents:
diff changeset
222 }
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parents:
diff changeset
223 };
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Gilles Duboscq <duboscq@ssw.jku.at>
parents:
diff changeset
224 assertReturn("longFieldStub", test, 63, new LongField(0x8000_0000_0000_0000L));
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parents:
diff changeset
225 }
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parents:
diff changeset
226 }
6dc4f0be9a70 Add support of lzcnt and tzcnt
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parents:
diff changeset
227
6dc4f0be9a70 Add support of lzcnt and tzcnt
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parents:
diff changeset
228 @SuppressWarnings("unused")
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parents:
diff changeset
229 public static int intStub(int arg) {
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parents:
diff changeset
230 return 0;
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parents:
diff changeset
231 }
6dc4f0be9a70 Add support of lzcnt and tzcnt
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parents:
diff changeset
232
6dc4f0be9a70 Add support of lzcnt and tzcnt
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parents:
diff changeset
233 @SuppressWarnings("unused")
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parents:
diff changeset
234 public static int longStub(long arg) {
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parents:
diff changeset
235 return 0;
6dc4f0be9a70 Add support of lzcnt and tzcnt
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parents:
diff changeset
236 }
6dc4f0be9a70 Add support of lzcnt and tzcnt
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parents:
diff changeset
237
6dc4f0be9a70 Add support of lzcnt and tzcnt
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parents:
diff changeset
238 public static class IntField {
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parents:
diff changeset
239 public int x;
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parents:
diff changeset
240
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parents:
diff changeset
241 IntField(int x) {
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Gilles Duboscq <duboscq@ssw.jku.at>
parents:
diff changeset
242 this.x = x;
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parents:
diff changeset
243 }
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parents:
diff changeset
244 }
6dc4f0be9a70 Add support of lzcnt and tzcnt
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parents:
diff changeset
245
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parents:
diff changeset
246 public static class LongField {
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parents:
diff changeset
247 public long x;
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parents:
diff changeset
248
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parents:
diff changeset
249 LongField(long x) {
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parents:
diff changeset
250 this.x = x;
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parents:
diff changeset
251 }
6dc4f0be9a70 Add support of lzcnt and tzcnt
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parents:
diff changeset
252 }
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parents:
diff changeset
253
6dc4f0be9a70 Add support of lzcnt and tzcnt
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parents:
diff changeset
254 @SuppressWarnings("unused")
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parents:
diff changeset
255 public static int intFieldStub(IntField arg) {
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parents:
diff changeset
256 return 0;
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parents:
diff changeset
257 }
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parents:
diff changeset
258
6dc4f0be9a70 Add support of lzcnt and tzcnt
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parents:
diff changeset
259 @SuppressWarnings("unused")
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parents:
diff changeset
260 public static int longFieldStub(LongField arg) {
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parents:
diff changeset
261 return 0;
6dc4f0be9a70 Add support of lzcnt and tzcnt
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parents:
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262 }
6dc4f0be9a70 Add support of lzcnt and tzcnt
Gilles Duboscq <duboscq@ssw.jku.at>
parents:
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263 }