Mercurial > hg > truffle
annotate src/cpu/sparc/vm/c1_LIRAssembler_sparc.cpp @ 6848:8e47bac5643a
7054512: Compress class pointers after perm gen removal
Summary: support of compress class pointers in the compilers.
Reviewed-by: kvn, twisti
author | roland |
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date | Tue, 09 Oct 2012 10:11:38 +0200 |
parents | 7eca5de9e0b6 |
children | 94e9408dbf50 |
rev | line source |
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0 | 1 /* |
6057 | 2 * Copyright (c) 2000, 2012, Oracle and/or its affiliates. All rights reserved. |
0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
4 * | |
5 * This code is free software; you can redistribute it and/or modify it | |
6 * under the terms of the GNU General Public License version 2 only, as | |
7 * published by the Free Software Foundation. | |
8 * | |
9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 * version 2 for more details (a copy is included in the LICENSE file that | |
13 * accompanied this code). | |
14 * | |
15 * You should have received a copy of the GNU General Public License version | |
16 * 2 along with this work; if not, write to the Free Software Foundation, | |
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
18 * | |
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
0 | 22 * |
23 */ | |
24 | |
1972 | 25 #include "precompiled.hpp" |
26 #include "c1/c1_Compilation.hpp" | |
27 #include "c1/c1_LIRAssembler.hpp" | |
28 #include "c1/c1_MacroAssembler.hpp" | |
29 #include "c1/c1_Runtime1.hpp" | |
30 #include "c1/c1_ValueStack.hpp" | |
31 #include "ci/ciArrayKlass.hpp" | |
32 #include "ci/ciInstance.hpp" | |
33 #include "gc_interface/collectedHeap.hpp" | |
34 #include "memory/barrierSet.hpp" | |
35 #include "memory/cardTableModRefBS.hpp" | |
36 #include "nativeInst_sparc.hpp" | |
37 #include "oops/objArrayKlass.hpp" | |
38 #include "runtime/sharedRuntime.hpp" | |
0 | 39 |
40 #define __ _masm-> | |
41 | |
42 | |
43 //------------------------------------------------------------ | |
44 | |
45 | |
46 bool LIR_Assembler::is_small_constant(LIR_Opr opr) { | |
47 if (opr->is_constant()) { | |
48 LIR_Const* constant = opr->as_constant_ptr(); | |
49 switch (constant->type()) { | |
50 case T_INT: { | |
51 jint value = constant->as_jint(); | |
52 return Assembler::is_simm13(value); | |
53 } | |
54 | |
55 default: | |
56 return false; | |
57 } | |
58 } | |
59 return false; | |
60 } | |
61 | |
62 | |
63 bool LIR_Assembler::is_single_instruction(LIR_Op* op) { | |
64 switch (op->code()) { | |
65 case lir_null_check: | |
66 return true; | |
67 | |
68 | |
69 case lir_add: | |
70 case lir_ushr: | |
71 case lir_shr: | |
72 case lir_shl: | |
73 // integer shifts and adds are always one instruction | |
74 return op->result_opr()->is_single_cpu(); | |
75 | |
76 | |
77 case lir_move: { | |
78 LIR_Op1* op1 = op->as_Op1(); | |
79 LIR_Opr src = op1->in_opr(); | |
80 LIR_Opr dst = op1->result_opr(); | |
81 | |
82 if (src == dst) { | |
83 NEEDS_CLEANUP; | |
84 // this works around a problem where moves with the same src and dst | |
85 // end up in the delay slot and then the assembler swallows the mov | |
86 // since it has no effect and then it complains because the delay slot | |
87 // is empty. returning false stops the optimizer from putting this in | |
88 // the delay slot | |
89 return false; | |
90 } | |
91 | |
92 // don't put moves involving oops into the delay slot since the VerifyOops code | |
93 // will make it much larger than a single instruction. | |
94 if (VerifyOops) { | |
95 return false; | |
96 } | |
97 | |
98 if (src->is_double_cpu() || dst->is_double_cpu() || op1->patch_code() != lir_patch_none || | |
99 ((src->is_double_fpu() || dst->is_double_fpu()) && op1->move_kind() != lir_move_normal)) { | |
100 return false; | |
101 } | |
102 | |
2002 | 103 if (UseCompressedOops) { |
104 if (dst->is_address() && !dst->is_stack() && (dst->type() == T_OBJECT || dst->type() == T_ARRAY)) return false; | |
105 if (src->is_address() && !src->is_stack() && (src->type() == T_OBJECT || src->type() == T_ARRAY)) return false; | |
106 } | |
107 | |
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108 if (UseCompressedKlassPointers) { |
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109 if (src->is_address() && !src->is_stack() && src->type() == T_ADDRESS && |
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110 src->as_address_ptr()->disp() == oopDesc::klass_offset_in_bytes()) return false; |
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111 } |
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112 |
0 | 113 if (dst->is_register()) { |
114 if (src->is_address() && Assembler::is_simm13(src->as_address_ptr()->disp())) { | |
115 return !PatchALot; | |
116 } else if (src->is_single_stack()) { | |
117 return true; | |
118 } | |
119 } | |
120 | |
121 if (src->is_register()) { | |
122 if (dst->is_address() && Assembler::is_simm13(dst->as_address_ptr()->disp())) { | |
123 return !PatchALot; | |
124 } else if (dst->is_single_stack()) { | |
125 return true; | |
126 } | |
127 } | |
128 | |
129 if (dst->is_register() && | |
130 ((src->is_register() && src->is_single_word() && src->is_same_type(dst)) || | |
131 (src->is_constant() && LIR_Assembler::is_small_constant(op->as_Op1()->in_opr())))) { | |
132 return true; | |
133 } | |
134 | |
135 return false; | |
136 } | |
137 | |
138 default: | |
139 return false; | |
140 } | |
141 ShouldNotReachHere(); | |
142 } | |
143 | |
144 | |
145 LIR_Opr LIR_Assembler::receiverOpr() { | |
146 return FrameMap::O0_oop_opr; | |
147 } | |
148 | |
149 | |
150 LIR_Opr LIR_Assembler::osrBufferPointer() { | |
151 return FrameMap::I0_opr; | |
152 } | |
153 | |
154 | |
155 int LIR_Assembler::initial_frame_size_in_bytes() { | |
156 return in_bytes(frame_map()->framesize_in_bytes()); | |
157 } | |
158 | |
159 | |
160 // inline cache check: the inline cached class is in G5_inline_cache_reg(G5); | |
161 // we fetch the class of the receiver (O0) and compare it with the cached class. | |
162 // If they do not match we jump to slow case. | |
163 int LIR_Assembler::check_icache() { | |
164 int offset = __ offset(); | |
165 __ inline_cache_check(O0, G5_inline_cache_reg); | |
166 return offset; | |
167 } | |
168 | |
169 | |
170 void LIR_Assembler::osr_entry() { | |
171 // On-stack-replacement entry sequence (interpreter frame layout described in interpreter_sparc.cpp): | |
172 // | |
173 // 1. Create a new compiled activation. | |
174 // 2. Initialize local variables in the compiled activation. The expression stack must be empty | |
175 // at the osr_bci; it is not initialized. | |
176 // 3. Jump to the continuation address in compiled code to resume execution. | |
177 | |
178 // OSR entry point | |
179 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset()); | |
180 BlockBegin* osr_entry = compilation()->hir()->osr_entry(); | |
181 ValueStack* entry_state = osr_entry->end()->state(); | |
182 int number_of_locks = entry_state->locks_size(); | |
183 | |
184 // Create a frame for the compiled activation. | |
185 __ build_frame(initial_frame_size_in_bytes()); | |
186 | |
187 // OSR buffer is | |
188 // | |
189 // locals[nlocals-1..0] | |
190 // monitors[number_of_locks-1..0] | |
191 // | |
192 // locals is a direct copy of the interpreter frame so in the osr buffer | |
193 // so first slot in the local array is the last local from the interpreter | |
194 // and last slot is local[0] (receiver) from the interpreter | |
195 // | |
196 // Similarly with locks. The first lock slot in the osr buffer is the nth lock | |
197 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock | |
198 // in the interpreter frame (the method lock if a sync method) | |
199 | |
200 // Initialize monitors in the compiled activation. | |
201 // I0: pointer to osr buffer | |
202 // | |
203 // All other registers are dead at this point and the locals will be | |
204 // copied into place by code emitted in the IR. | |
205 | |
206 Register OSR_buf = osrBufferPointer()->as_register(); | |
207 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below"); | |
208 int monitor_offset = BytesPerWord * method()->max_locals() + | |
1060 | 209 (2 * BytesPerWord) * (number_of_locks - 1); |
210 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in | |
211 // the OSR buffer using 2 word entries: first the lock and then | |
212 // the oop. | |
0 | 213 for (int i = 0; i < number_of_locks; i++) { |
1060 | 214 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord); |
0 | 215 #ifdef ASSERT |
216 // verify the interpreter's monitor has a non-null object | |
217 { | |
218 Label L; | |
1060 | 219 __ ld_ptr(OSR_buf, slot_offset + 1*BytesPerWord, O7); |
3839 | 220 __ cmp_and_br_short(O7, G0, Assembler::notEqual, Assembler::pt, L); |
0 | 221 __ stop("locked object is NULL"); |
222 __ bind(L); | |
223 } | |
224 #endif // ASSERT | |
225 // Copy the lock field into the compiled activation. | |
1060 | 226 __ ld_ptr(OSR_buf, slot_offset + 0, O7); |
0 | 227 __ st_ptr(O7, frame_map()->address_for_monitor_lock(i)); |
1060 | 228 __ ld_ptr(OSR_buf, slot_offset + 1*BytesPerWord, O7); |
0 | 229 __ st_ptr(O7, frame_map()->address_for_monitor_object(i)); |
230 } | |
231 } | |
232 } | |
233 | |
234 | |
235 // Optimized Library calls | |
236 // This is the fast version of java.lang.String.compare; it has not | |
237 // OSR-entry and therefore, we generate a slow version for OSR's | |
238 void LIR_Assembler::emit_string_compare(LIR_Opr left, LIR_Opr right, LIR_Opr dst, CodeEmitInfo* info) { | |
239 Register str0 = left->as_register(); | |
240 Register str1 = right->as_register(); | |
241 | |
242 Label Ldone; | |
243 | |
244 Register result = dst->as_register(); | |
245 { | |
6057 | 246 // Get a pointer to the first character of string0 in tmp0 |
247 // and get string0.length() in str0 | |
248 // Get a pointer to the first character of string1 in tmp1 | |
249 // and get string1.length() in str1 | |
250 // Also, get string0.length()-string1.length() in | |
251 // o7 and get the condition code set | |
0 | 252 // Note: some instructions have been hoisted for better instruction scheduling |
253 | |
254 Register tmp0 = L0; | |
255 Register tmp1 = L1; | |
256 Register tmp2 = L2; | |
257 | |
258 int value_offset = java_lang_String:: value_offset_in_bytes(); // char array | |
6057 | 259 if (java_lang_String::has_offset_field()) { |
260 int offset_offset = java_lang_String::offset_offset_in_bytes(); // first character position | |
261 int count_offset = java_lang_String:: count_offset_in_bytes(); | |
262 __ load_heap_oop(str0, value_offset, tmp0); | |
263 __ ld(str0, offset_offset, tmp2); | |
264 __ add(tmp0, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp0); | |
265 __ ld(str0, count_offset, str0); | |
266 __ sll(tmp2, exact_log2(sizeof(jchar)), tmp2); | |
267 } else { | |
268 __ load_heap_oop(str0, value_offset, tmp1); | |
269 __ add(tmp1, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp0); | |
270 __ ld(tmp1, arrayOopDesc::length_offset_in_bytes(), str0); | |
271 } | |
0 | 272 |
273 // str1 may be null | |
274 add_debug_info_for_null_check_here(info); | |
275 | |
6057 | 276 if (java_lang_String::has_offset_field()) { |
277 int offset_offset = java_lang_String::offset_offset_in_bytes(); // first character position | |
278 int count_offset = java_lang_String:: count_offset_in_bytes(); | |
279 __ load_heap_oop(str1, value_offset, tmp1); | |
280 __ add(tmp0, tmp2, tmp0); | |
281 | |
282 __ ld(str1, offset_offset, tmp2); | |
283 __ add(tmp1, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp1); | |
284 __ ld(str1, count_offset, str1); | |
285 __ sll(tmp2, exact_log2(sizeof(jchar)), tmp2); | |
286 __ add(tmp1, tmp2, tmp1); | |
287 } else { | |
288 __ load_heap_oop(str1, value_offset, tmp2); | |
289 __ add(tmp2, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp1); | |
290 __ ld(tmp2, arrayOopDesc::length_offset_in_bytes(), str1); | |
291 } | |
0 | 292 __ subcc(str0, str1, O7); |
293 } | |
294 | |
295 { | |
296 // Compute the minimum of the string lengths, scale it and store it in limit | |
297 Register count0 = I0; | |
298 Register count1 = I1; | |
299 Register limit = L3; | |
300 | |
301 Label Lskip; | |
302 __ sll(count0, exact_log2(sizeof(jchar)), limit); // string0 is shorter | |
303 __ br(Assembler::greater, true, Assembler::pt, Lskip); | |
304 __ delayed()->sll(count1, exact_log2(sizeof(jchar)), limit); // string1 is shorter | |
305 __ bind(Lskip); | |
306 | |
307 // If either string is empty (or both of them) the result is the difference in lengths | |
308 __ cmp(limit, 0); | |
309 __ br(Assembler::equal, true, Assembler::pn, Ldone); | |
310 __ delayed()->mov(O7, result); // result is difference in lengths | |
311 } | |
312 | |
313 { | |
314 // Neither string is empty | |
315 Label Lloop; | |
316 | |
317 Register base0 = L0; | |
318 Register base1 = L1; | |
319 Register chr0 = I0; | |
320 Register chr1 = I1; | |
321 Register limit = L3; | |
322 | |
323 // Shift base0 and base1 to the end of the arrays, negate limit | |
324 __ add(base0, limit, base0); | |
325 __ add(base1, limit, base1); | |
6057 | 326 __ neg(limit); // limit = -min{string0.length(), string1.length()} |
0 | 327 |
328 __ lduh(base0, limit, chr0); | |
329 __ bind(Lloop); | |
330 __ lduh(base1, limit, chr1); | |
331 __ subcc(chr0, chr1, chr0); | |
332 __ br(Assembler::notZero, false, Assembler::pn, Ldone); | |
333 assert(chr0 == result, "result must be pre-placed"); | |
334 __ delayed()->inccc(limit, sizeof(jchar)); | |
335 __ br(Assembler::notZero, true, Assembler::pt, Lloop); | |
336 __ delayed()->lduh(base0, limit, chr0); | |
337 } | |
338 | |
339 // If strings are equal up to min length, return the length difference. | |
340 __ mov(O7, result); | |
341 | |
342 // Otherwise, return the difference between the first mismatched chars. | |
343 __ bind(Ldone); | |
344 } | |
345 | |
346 | |
347 // -------------------------------------------------------------------------------------------- | |
348 | |
349 void LIR_Assembler::monitorexit(LIR_Opr obj_opr, LIR_Opr lock_opr, Register hdr, int monitor_no) { | |
350 if (!GenerateSynchronizationCode) return; | |
351 | |
352 Register obj_reg = obj_opr->as_register(); | |
353 Register lock_reg = lock_opr->as_register(); | |
354 | |
355 Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no); | |
356 Register reg = mon_addr.base(); | |
357 int offset = mon_addr.disp(); | |
358 // compute pointer to BasicLock | |
359 if (mon_addr.is_simm13()) { | |
360 __ add(reg, offset, lock_reg); | |
361 } | |
362 else { | |
363 __ set(offset, lock_reg); | |
364 __ add(reg, lock_reg, lock_reg); | |
365 } | |
366 // unlock object | |
367 MonitorAccessStub* slow_case = new MonitorExitStub(lock_opr, UseFastLocking, monitor_no); | |
368 // _slow_case_stubs->append(slow_case); | |
369 // temporary fix: must be created after exceptionhandler, therefore as call stub | |
370 _slow_case_stubs->append(slow_case); | |
371 if (UseFastLocking) { | |
372 // try inlined fast unlocking first, revert to slow locking if it fails | |
373 // note: lock_reg points to the displaced header since the displaced header offset is 0! | |
374 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); | |
375 __ unlock_object(hdr, obj_reg, lock_reg, *slow_case->entry()); | |
376 } else { | |
377 // always do slow unlocking | |
378 // note: the slow unlocking code could be inlined here, however if we use | |
379 // slow unlocking, speed doesn't matter anyway and this solution is | |
380 // simpler and requires less duplicated code - additionally, the | |
381 // slow unlocking code is the same in either case which simplifies | |
382 // debugging | |
383 __ br(Assembler::always, false, Assembler::pt, *slow_case->entry()); | |
384 __ delayed()->nop(); | |
385 } | |
386 // done | |
387 __ bind(*slow_case->continuation()); | |
388 } | |
389 | |
390 | |
1204 | 391 int LIR_Assembler::emit_exception_handler() { |
0 | 392 // if the last instruction is a call (typically to do a throw which |
393 // is coming at the end after block reordering) the return address | |
394 // must still point into the code area in order to avoid assertion | |
395 // failures when searching for the corresponding bci => add a nop | |
396 // (was bug 5/14/1999 - gri) | |
397 __ nop(); | |
398 | |
399 // generate code for exception handler | |
400 ciMethod* method = compilation()->method(); | |
401 | |
402 address handler_base = __ start_a_stub(exception_handler_size); | |
403 | |
404 if (handler_base == NULL) { | |
405 // not enough space left for the handler | |
406 bailout("exception handler overflow"); | |
1204 | 407 return -1; |
0 | 408 } |
1204 | 409 |
0 | 410 int offset = code_offset(); |
411 | |
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412 __ call(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id), relocInfo::runtime_call_type); |
0 | 413 __ delayed()->nop(); |
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414 __ should_not_reach_here(); |
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415 guarantee(code_offset() - offset <= exception_handler_size, "overflow"); |
0 | 416 __ end_a_stub(); |
1204 | 417 |
418 return offset; | |
0 | 419 } |
420 | |
1204 | 421 |
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422 // Emit the code to remove the frame from the stack in the exception |
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423 // unwind path. |
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424 int LIR_Assembler::emit_unwind_handler() { |
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425 #ifndef PRODUCT |
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426 if (CommentedAssembly) { |
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427 _masm->block_comment("Unwind handler"); |
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428 } |
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429 #endif |
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430 |
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431 int offset = code_offset(); |
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432 |
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433 // Fetch the exception from TLS and clear out exception related thread state |
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434 __ ld_ptr(G2_thread, in_bytes(JavaThread::exception_oop_offset()), O0); |
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435 __ st_ptr(G0, G2_thread, in_bytes(JavaThread::exception_oop_offset())); |
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436 __ st_ptr(G0, G2_thread, in_bytes(JavaThread::exception_pc_offset())); |
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437 |
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438 __ bind(_unwind_handler_entry); |
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439 __ verify_not_null_oop(O0); |
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440 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) { |
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441 __ mov(O0, I0); // Preserve the exception |
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442 } |
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443 |
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444 // Preform needed unlocking |
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445 MonitorExitStub* stub = NULL; |
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446 if (method()->is_synchronized()) { |
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447 monitor_address(0, FrameMap::I1_opr); |
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448 stub = new MonitorExitStub(FrameMap::I1_opr, true, 0); |
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449 __ unlock_object(I3, I2, I1, *stub->entry()); |
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450 __ bind(*stub->continuation()); |
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451 } |
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452 |
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453 if (compilation()->env()->dtrace_method_probes()) { |
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454 __ mov(G2_thread, O0); |
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455 __ save_thread(I1); // need to preserve thread in G2 across |
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456 // runtime call |
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457 metadata2reg(method()->constant_encoding(), O1); |
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458 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit), relocInfo::runtime_call_type); |
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459 __ delayed()->nop(); |
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460 __ restore_thread(I1); |
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461 } |
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462 |
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463 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) { |
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464 __ mov(I0, O0); // Restore the exception |
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465 } |
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466 |
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467 // dispatch to the unwind logic |
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468 __ call(Runtime1::entry_for(Runtime1::unwind_exception_id), relocInfo::runtime_call_type); |
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469 __ delayed()->nop(); |
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470 |
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471 // Emit the slow path assembly |
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472 if (stub != NULL) { |
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473 stub->emit_code(this); |
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474 } |
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475 |
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476 return offset; |
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477 } |
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478 |
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479 |
1204 | 480 int LIR_Assembler::emit_deopt_handler() { |
0 | 481 // if the last instruction is a call (typically to do a throw which |
482 // is coming at the end after block reordering) the return address | |
483 // must still point into the code area in order to avoid assertion | |
484 // failures when searching for the corresponding bci => add a nop | |
485 // (was bug 5/14/1999 - gri) | |
486 __ nop(); | |
487 | |
488 // generate code for deopt handler | |
489 ciMethod* method = compilation()->method(); | |
490 address handler_base = __ start_a_stub(deopt_handler_size); | |
491 if (handler_base == NULL) { | |
492 // not enough space left for the handler | |
493 bailout("deopt handler overflow"); | |
1204 | 494 return -1; |
0 | 495 } |
1204 | 496 |
0 | 497 int offset = code_offset(); |
727 | 498 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack()); |
499 __ JUMP(deopt_blob, G3_scratch, 0); // sethi;jmp | |
0 | 500 __ delayed()->nop(); |
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501 guarantee(code_offset() - offset <= deopt_handler_size, "overflow"); |
0 | 502 __ end_a_stub(); |
1204 | 503 |
504 return offset; | |
0 | 505 } |
506 | |
507 | |
508 void LIR_Assembler::jobject2reg(jobject o, Register reg) { | |
509 if (o == NULL) { | |
510 __ set(NULL_WORD, reg); | |
511 } else { | |
512 int oop_index = __ oop_recorder()->find_index(o); | |
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513 assert(Universe::heap()->is_in_reserved(JNIHandles::resolve(o)), "should be real oop"); |
0 | 514 RelocationHolder rspec = oop_Relocation::spec(oop_index); |
515 __ set(NULL_WORD, reg, rspec); // Will be set when the nmethod is created | |
516 } | |
517 } | |
518 | |
519 | |
520 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) { | |
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521 // Allocate a new index in table to hold the object once it's been patched |
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522 int oop_index = __ oop_recorder()->allocate_oop_index(NULL); |
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523 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_mirror_id, oop_index); |
0 | 524 |
727 | 525 AddressLiteral addrlit(NULL, oop_Relocation::spec(oop_index)); |
526 assert(addrlit.rspec().type() == relocInfo::oop_type, "must be an oop reloc"); | |
0 | 527 // It may not seem necessary to use a sethi/add pair to load a NULL into dest, but the |
528 // NULL will be dynamically patched later and the patched value may be large. We must | |
529 // therefore generate the sethi/add as a placeholders | |
727 | 530 __ patchable_set(addrlit, reg); |
0 | 531 |
532 patching_epilog(patch, lir_patch_normal, reg, info); | |
533 } | |
534 | |
535 | |
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536 void LIR_Assembler::metadata2reg(Metadata* o, Register reg) { |
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537 __ set_metadata_constant(o, reg); |
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538 } |
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539 |
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540 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo *info) { |
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541 // Allocate a new index in table to hold the klass once it's been patched |
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542 int index = __ oop_recorder()->allocate_metadata_index(NULL); |
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543 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id, index); |
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544 AddressLiteral addrlit(NULL, metadata_Relocation::spec(index)); |
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545 assert(addrlit.rspec().type() == relocInfo::metadata_type, "must be an metadata reloc"); |
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546 // It may not seem necessary to use a sethi/add pair to load a NULL into dest, but the |
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547 // NULL will be dynamically patched later and the patched value may be large. We must |
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548 // therefore generate the sethi/add as a placeholders |
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549 __ patchable_set(addrlit, reg); |
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550 |
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551 patching_epilog(patch, lir_patch_normal, reg, info); |
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552 } |
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553 |
0 | 554 void LIR_Assembler::emit_op3(LIR_Op3* op) { |
555 Register Rdividend = op->in_opr1()->as_register(); | |
556 Register Rdivisor = noreg; | |
557 Register Rscratch = op->in_opr3()->as_register(); | |
558 Register Rresult = op->result_opr()->as_register(); | |
559 int divisor = -1; | |
560 | |
561 if (op->in_opr2()->is_register()) { | |
562 Rdivisor = op->in_opr2()->as_register(); | |
563 } else { | |
564 divisor = op->in_opr2()->as_constant_ptr()->as_jint(); | |
565 assert(Assembler::is_simm13(divisor), "can only handle simm13"); | |
566 } | |
567 | |
568 assert(Rdividend != Rscratch, ""); | |
569 assert(Rdivisor != Rscratch, ""); | |
570 assert(op->code() == lir_idiv || op->code() == lir_irem, "Must be irem or idiv"); | |
571 | |
572 if (Rdivisor == noreg && is_power_of_2(divisor)) { | |
573 // convert division by a power of two into some shifts and logical operations | |
574 if (op->code() == lir_idiv) { | |
575 if (divisor == 2) { | |
576 __ srl(Rdividend, 31, Rscratch); | |
577 } else { | |
578 __ sra(Rdividend, 31, Rscratch); | |
579 __ and3(Rscratch, divisor - 1, Rscratch); | |
580 } | |
581 __ add(Rdividend, Rscratch, Rscratch); | |
582 __ sra(Rscratch, log2_intptr(divisor), Rresult); | |
583 return; | |
584 } else { | |
585 if (divisor == 2) { | |
586 __ srl(Rdividend, 31, Rscratch); | |
587 } else { | |
588 __ sra(Rdividend, 31, Rscratch); | |
589 __ and3(Rscratch, divisor - 1,Rscratch); | |
590 } | |
591 __ add(Rdividend, Rscratch, Rscratch); | |
592 __ andn(Rscratch, divisor - 1,Rscratch); | |
593 __ sub(Rdividend, Rscratch, Rresult); | |
594 return; | |
595 } | |
596 } | |
597 | |
598 __ sra(Rdividend, 31, Rscratch); | |
599 __ wry(Rscratch); | |
600 if (!VM_Version::v9_instructions_work()) { | |
601 // v9 doesn't require these nops | |
602 __ nop(); | |
603 __ nop(); | |
604 __ nop(); | |
605 __ nop(); | |
606 } | |
607 | |
608 add_debug_info_for_div0_here(op->info()); | |
609 | |
610 if (Rdivisor != noreg) { | |
611 __ sdivcc(Rdividend, Rdivisor, (op->code() == lir_idiv ? Rresult : Rscratch)); | |
612 } else { | |
613 assert(Assembler::is_simm13(divisor), "can only handle simm13"); | |
614 __ sdivcc(Rdividend, divisor, (op->code() == lir_idiv ? Rresult : Rscratch)); | |
615 } | |
616 | |
617 Label skip; | |
618 __ br(Assembler::overflowSet, true, Assembler::pn, skip); | |
619 __ delayed()->Assembler::sethi(0x80000000, (op->code() == lir_idiv ? Rresult : Rscratch)); | |
620 __ bind(skip); | |
621 | |
622 if (op->code() == lir_irem) { | |
623 if (Rdivisor != noreg) { | |
624 __ smul(Rscratch, Rdivisor, Rscratch); | |
625 } else { | |
626 __ smul(Rscratch, divisor, Rscratch); | |
627 } | |
628 __ sub(Rdividend, Rscratch, Rresult); | |
629 } | |
630 } | |
631 | |
632 | |
633 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) { | |
634 #ifdef ASSERT | |
635 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label"); | |
636 if (op->block() != NULL) _branch_target_blocks.append(op->block()); | |
637 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock()); | |
638 #endif | |
639 assert(op->info() == NULL, "shouldn't have CodeEmitInfo"); | |
640 | |
641 if (op->cond() == lir_cond_always) { | |
642 __ br(Assembler::always, false, Assembler::pt, *(op->label())); | |
643 } else if (op->code() == lir_cond_float_branch) { | |
644 assert(op->ublock() != NULL, "must have unordered successor"); | |
645 bool is_unordered = (op->ublock() == op->block()); | |
646 Assembler::Condition acond; | |
647 switch (op->cond()) { | |
648 case lir_cond_equal: acond = Assembler::f_equal; break; | |
649 case lir_cond_notEqual: acond = Assembler::f_notEqual; break; | |
650 case lir_cond_less: acond = (is_unordered ? Assembler::f_unorderedOrLess : Assembler::f_less); break; | |
651 case lir_cond_greater: acond = (is_unordered ? Assembler::f_unorderedOrGreater : Assembler::f_greater); break; | |
652 case lir_cond_lessEqual: acond = (is_unordered ? Assembler::f_unorderedOrLessOrEqual : Assembler::f_lessOrEqual); break; | |
653 case lir_cond_greaterEqual: acond = (is_unordered ? Assembler::f_unorderedOrGreaterOrEqual: Assembler::f_greaterOrEqual); break; | |
654 default : ShouldNotReachHere(); | |
655 }; | |
656 | |
657 if (!VM_Version::v9_instructions_work()) { | |
658 __ nop(); | |
659 } | |
660 __ fb( acond, false, Assembler::pn, *(op->label())); | |
661 } else { | |
662 assert (op->code() == lir_branch, "just checking"); | |
663 | |
664 Assembler::Condition acond; | |
665 switch (op->cond()) { | |
666 case lir_cond_equal: acond = Assembler::equal; break; | |
667 case lir_cond_notEqual: acond = Assembler::notEqual; break; | |
668 case lir_cond_less: acond = Assembler::less; break; | |
669 case lir_cond_lessEqual: acond = Assembler::lessEqual; break; | |
670 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; break; | |
671 case lir_cond_greater: acond = Assembler::greater; break; | |
672 case lir_cond_aboveEqual: acond = Assembler::greaterEqualUnsigned; break; | |
673 case lir_cond_belowEqual: acond = Assembler::lessEqualUnsigned; break; | |
674 default: ShouldNotReachHere(); | |
675 }; | |
676 | |
677 // sparc has different condition codes for testing 32-bit | |
678 // vs. 64-bit values. We could always test xcc is we could | |
679 // guarantee that 32-bit loads always sign extended but that isn't | |
680 // true and since sign extension isn't free, it would impose a | |
681 // slight cost. | |
682 #ifdef _LP64 | |
683 if (op->type() == T_INT) { | |
684 __ br(acond, false, Assembler::pn, *(op->label())); | |
685 } else | |
686 #endif | |
687 __ brx(acond, false, Assembler::pn, *(op->label())); | |
688 } | |
689 // The peephole pass fills the delay slot | |
690 } | |
691 | |
692 | |
693 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) { | |
694 Bytecodes::Code code = op->bytecode(); | |
695 LIR_Opr dst = op->result_opr(); | |
696 | |
697 switch(code) { | |
698 case Bytecodes::_i2l: { | |
699 Register rlo = dst->as_register_lo(); | |
700 Register rhi = dst->as_register_hi(); | |
701 Register rval = op->in_opr()->as_register(); | |
702 #ifdef _LP64 | |
703 __ sra(rval, 0, rlo); | |
704 #else | |
705 __ mov(rval, rlo); | |
706 __ sra(rval, BitsPerInt-1, rhi); | |
707 #endif | |
708 break; | |
709 } | |
710 case Bytecodes::_i2d: | |
711 case Bytecodes::_i2f: { | |
712 bool is_double = (code == Bytecodes::_i2d); | |
713 FloatRegister rdst = is_double ? dst->as_double_reg() : dst->as_float_reg(); | |
714 FloatRegisterImpl::Width w = is_double ? FloatRegisterImpl::D : FloatRegisterImpl::S; | |
715 FloatRegister rsrc = op->in_opr()->as_float_reg(); | |
716 if (rsrc != rdst) { | |
717 __ fmov(FloatRegisterImpl::S, rsrc, rdst); | |
718 } | |
719 __ fitof(w, rdst, rdst); | |
720 break; | |
721 } | |
722 case Bytecodes::_f2i:{ | |
723 FloatRegister rsrc = op->in_opr()->as_float_reg(); | |
724 Address addr = frame_map()->address_for_slot(dst->single_stack_ix()); | |
725 Label L; | |
726 // result must be 0 if value is NaN; test by comparing value to itself | |
727 __ fcmp(FloatRegisterImpl::S, Assembler::fcc0, rsrc, rsrc); | |
728 if (!VM_Version::v9_instructions_work()) { | |
729 __ nop(); | |
730 } | |
731 __ fb(Assembler::f_unordered, true, Assembler::pn, L); | |
732 __ delayed()->st(G0, addr); // annuled if contents of rsrc is not NaN | |
733 __ ftoi(FloatRegisterImpl::S, rsrc, rsrc); | |
734 // move integer result from float register to int register | |
735 __ stf(FloatRegisterImpl::S, rsrc, addr.base(), addr.disp()); | |
736 __ bind (L); | |
737 break; | |
738 } | |
739 case Bytecodes::_l2i: { | |
740 Register rlo = op->in_opr()->as_register_lo(); | |
741 Register rhi = op->in_opr()->as_register_hi(); | |
742 Register rdst = dst->as_register(); | |
743 #ifdef _LP64 | |
744 __ sra(rlo, 0, rdst); | |
745 #else | |
746 __ mov(rlo, rdst); | |
747 #endif | |
748 break; | |
749 } | |
750 case Bytecodes::_d2f: | |
751 case Bytecodes::_f2d: { | |
752 bool is_double = (code == Bytecodes::_f2d); | |
753 assert((!is_double && dst->is_single_fpu()) || (is_double && dst->is_double_fpu()), "check"); | |
754 LIR_Opr val = op->in_opr(); | |
755 FloatRegister rval = (code == Bytecodes::_d2f) ? val->as_double_reg() : val->as_float_reg(); | |
756 FloatRegister rdst = is_double ? dst->as_double_reg() : dst->as_float_reg(); | |
757 FloatRegisterImpl::Width vw = is_double ? FloatRegisterImpl::S : FloatRegisterImpl::D; | |
758 FloatRegisterImpl::Width dw = is_double ? FloatRegisterImpl::D : FloatRegisterImpl::S; | |
759 __ ftof(vw, dw, rval, rdst); | |
760 break; | |
761 } | |
762 case Bytecodes::_i2s: | |
763 case Bytecodes::_i2b: { | |
764 Register rval = op->in_opr()->as_register(); | |
765 Register rdst = dst->as_register(); | |
766 int shift = (code == Bytecodes::_i2b) ? (BitsPerInt - T_BYTE_aelem_bytes * BitsPerByte) : (BitsPerInt - BitsPerShort); | |
767 __ sll (rval, shift, rdst); | |
768 __ sra (rdst, shift, rdst); | |
769 break; | |
770 } | |
771 case Bytecodes::_i2c: { | |
772 Register rval = op->in_opr()->as_register(); | |
773 Register rdst = dst->as_register(); | |
774 int shift = BitsPerInt - T_CHAR_aelem_bytes * BitsPerByte; | |
775 __ sll (rval, shift, rdst); | |
776 __ srl (rdst, shift, rdst); | |
777 break; | |
778 } | |
779 | |
780 default: ShouldNotReachHere(); | |
781 } | |
782 } | |
783 | |
784 | |
785 void LIR_Assembler::align_call(LIR_Code) { | |
786 // do nothing since all instructions are word aligned on sparc | |
787 } | |
788 | |
789 | |
1295 | 790 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) { |
791 __ call(op->addr(), rtype); | |
1564 | 792 // The peephole pass fills the delay slot, add_call_info is done in |
793 // LIR_Assembler::emit_delay. | |
0 | 794 } |
795 | |
796 | |
1295 | 797 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) { |
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798 __ ic_call(op->addr(), false); |
1564 | 799 // The peephole pass fills the delay slot, add_call_info is done in |
800 // LIR_Assembler::emit_delay. | |
0 | 801 } |
802 | |
803 | |
1295 | 804 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) { |
805 add_debug_info_for_null_check_here(op->info()); | |
2002 | 806 __ load_klass(O0, G3_scratch); |
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807 if (Assembler::is_simm13(op->vtable_offset())) { |
1295 | 808 __ ld_ptr(G3_scratch, op->vtable_offset(), G5_method); |
0 | 809 } else { |
810 // This will generate 2 instructions | |
1295 | 811 __ set(op->vtable_offset(), G5_method); |
0 | 812 // ld_ptr, set_hi, set |
813 __ ld_ptr(G3_scratch, G5_method, G5_method); | |
814 } | |
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815 __ ld_ptr(G5_method, Method::from_compiled_offset(), G3_scratch); |
0 | 816 __ callr(G3_scratch, G0); |
817 // the peephole pass fills the delay slot | |
818 } | |
819 | |
2002 | 820 int LIR_Assembler::store(LIR_Opr from_reg, Register base, int offset, BasicType type, bool wide, bool unaligned) { |
0 | 821 int store_offset; |
822 if (!Assembler::is_simm13(offset + (type == T_LONG) ? wordSize : 0)) { | |
823 assert(!unaligned, "can't handle this"); | |
824 // for offsets larger than a simm13 we setup the offset in O7 | |
727 | 825 __ set(offset, O7); |
2002 | 826 store_offset = store(from_reg, base, O7, type, wide); |
0 | 827 } else { |
2002 | 828 if (type == T_ARRAY || type == T_OBJECT) { |
829 __ verify_oop(from_reg->as_register()); | |
830 } | |
0 | 831 store_offset = code_offset(); |
832 switch (type) { | |
833 case T_BOOLEAN: // fall through | |
834 case T_BYTE : __ stb(from_reg->as_register(), base, offset); break; | |
835 case T_CHAR : __ sth(from_reg->as_register(), base, offset); break; | |
836 case T_SHORT : __ sth(from_reg->as_register(), base, offset); break; | |
837 case T_INT : __ stw(from_reg->as_register(), base, offset); break; | |
838 case T_LONG : | |
839 #ifdef _LP64 | |
840 if (unaligned || PatchALot) { | |
841 __ srax(from_reg->as_register_lo(), 32, O7); | |
842 __ stw(from_reg->as_register_lo(), base, offset + lo_word_offset_in_bytes); | |
843 __ stw(O7, base, offset + hi_word_offset_in_bytes); | |
844 } else { | |
845 __ stx(from_reg->as_register_lo(), base, offset); | |
846 } | |
847 #else | |
848 assert(Assembler::is_simm13(offset + 4), "must be"); | |
849 __ stw(from_reg->as_register_lo(), base, offset + lo_word_offset_in_bytes); | |
850 __ stw(from_reg->as_register_hi(), base, offset + hi_word_offset_in_bytes); | |
851 #endif | |
852 break; | |
2002 | 853 case T_ADDRESS: |
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854 case T_METADATA: |
2002 | 855 __ st_ptr(from_reg->as_register(), base, offset); |
856 break; | |
0 | 857 case T_ARRAY : // fall through |
2002 | 858 case T_OBJECT: |
859 { | |
860 if (UseCompressedOops && !wide) { | |
861 __ encode_heap_oop(from_reg->as_register(), G3_scratch); | |
862 store_offset = code_offset(); | |
863 __ stw(G3_scratch, base, offset); | |
864 } else { | |
865 __ st_ptr(from_reg->as_register(), base, offset); | |
866 } | |
867 break; | |
868 } | |
869 | |
0 | 870 case T_FLOAT : __ stf(FloatRegisterImpl::S, from_reg->as_float_reg(), base, offset); break; |
871 case T_DOUBLE: | |
872 { | |
873 FloatRegister reg = from_reg->as_double_reg(); | |
874 // split unaligned stores | |
875 if (unaligned || PatchALot) { | |
876 assert(Assembler::is_simm13(offset + 4), "must be"); | |
877 __ stf(FloatRegisterImpl::S, reg->successor(), base, offset + 4); | |
878 __ stf(FloatRegisterImpl::S, reg, base, offset); | |
879 } else { | |
880 __ stf(FloatRegisterImpl::D, reg, base, offset); | |
881 } | |
882 break; | |
883 } | |
884 default : ShouldNotReachHere(); | |
885 } | |
886 } | |
887 return store_offset; | |
888 } | |
889 | |
890 | |
2002 | 891 int LIR_Assembler::store(LIR_Opr from_reg, Register base, Register disp, BasicType type, bool wide) { |
892 if (type == T_ARRAY || type == T_OBJECT) { | |
893 __ verify_oop(from_reg->as_register()); | |
894 } | |
0 | 895 int store_offset = code_offset(); |
896 switch (type) { | |
897 case T_BOOLEAN: // fall through | |
898 case T_BYTE : __ stb(from_reg->as_register(), base, disp); break; | |
899 case T_CHAR : __ sth(from_reg->as_register(), base, disp); break; | |
900 case T_SHORT : __ sth(from_reg->as_register(), base, disp); break; | |
901 case T_INT : __ stw(from_reg->as_register(), base, disp); break; | |
902 case T_LONG : | |
903 #ifdef _LP64 | |
904 __ stx(from_reg->as_register_lo(), base, disp); | |
905 #else | |
906 assert(from_reg->as_register_hi()->successor() == from_reg->as_register_lo(), "must match"); | |
907 __ std(from_reg->as_register_hi(), base, disp); | |
908 #endif | |
909 break; | |
2002 | 910 case T_ADDRESS: |
911 __ st_ptr(from_reg->as_register(), base, disp); | |
912 break; | |
0 | 913 case T_ARRAY : // fall through |
2002 | 914 case T_OBJECT: |
915 { | |
916 if (UseCompressedOops && !wide) { | |
917 __ encode_heap_oop(from_reg->as_register(), G3_scratch); | |
918 store_offset = code_offset(); | |
919 __ stw(G3_scratch, base, disp); | |
920 } else { | |
921 __ st_ptr(from_reg->as_register(), base, disp); | |
922 } | |
923 break; | |
924 } | |
0 | 925 case T_FLOAT : __ stf(FloatRegisterImpl::S, from_reg->as_float_reg(), base, disp); break; |
926 case T_DOUBLE: __ stf(FloatRegisterImpl::D, from_reg->as_double_reg(), base, disp); break; | |
927 default : ShouldNotReachHere(); | |
928 } | |
929 return store_offset; | |
930 } | |
931 | |
932 | |
2002 | 933 int LIR_Assembler::load(Register base, int offset, LIR_Opr to_reg, BasicType type, bool wide, bool unaligned) { |
0 | 934 int load_offset; |
935 if (!Assembler::is_simm13(offset + (type == T_LONG) ? wordSize : 0)) { | |
936 assert(base != O7, "destroying register"); | |
937 assert(!unaligned, "can't handle this"); | |
938 // for offsets larger than a simm13 we setup the offset in O7 | |
727 | 939 __ set(offset, O7); |
2002 | 940 load_offset = load(base, O7, to_reg, type, wide); |
0 | 941 } else { |
942 load_offset = code_offset(); | |
943 switch(type) { | |
944 case T_BOOLEAN: // fall through | |
945 case T_BYTE : __ ldsb(base, offset, to_reg->as_register()); break; | |
946 case T_CHAR : __ lduh(base, offset, to_reg->as_register()); break; | |
947 case T_SHORT : __ ldsh(base, offset, to_reg->as_register()); break; | |
948 case T_INT : __ ld(base, offset, to_reg->as_register()); break; | |
949 case T_LONG : | |
950 if (!unaligned) { | |
951 #ifdef _LP64 | |
952 __ ldx(base, offset, to_reg->as_register_lo()); | |
953 #else | |
954 assert(to_reg->as_register_hi()->successor() == to_reg->as_register_lo(), | |
955 "must be sequential"); | |
956 __ ldd(base, offset, to_reg->as_register_hi()); | |
957 #endif | |
958 } else { | |
959 #ifdef _LP64 | |
960 assert(base != to_reg->as_register_lo(), "can't handle this"); | |
1060 | 961 assert(O7 != to_reg->as_register_lo(), "can't handle this"); |
0 | 962 __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_lo()); |
1060 | 963 __ lduw(base, offset + lo_word_offset_in_bytes, O7); // in case O7 is base or offset, use it last |
0 | 964 __ sllx(to_reg->as_register_lo(), 32, to_reg->as_register_lo()); |
1060 | 965 __ or3(to_reg->as_register_lo(), O7, to_reg->as_register_lo()); |
0 | 966 #else |
967 if (base == to_reg->as_register_lo()) { | |
968 __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_hi()); | |
969 __ ld(base, offset + lo_word_offset_in_bytes, to_reg->as_register_lo()); | |
970 } else { | |
971 __ ld(base, offset + lo_word_offset_in_bytes, to_reg->as_register_lo()); | |
972 __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_hi()); | |
973 } | |
974 #endif | |
975 } | |
976 break; | |
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977 case T_METADATA: __ ld_ptr(base, offset, to_reg->as_register()); break; |
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978 case T_ADDRESS: |
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979 if (offset == oopDesc::klass_offset_in_bytes()) { |
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980 __ lduw(base, offset, to_reg->as_register()); |
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981 #ifdef _LP64 |
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982 if (UseCompressedKlassPointers) { |
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983 __ decode_klass_not_null(to_reg->as_register()); |
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984 } |
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985 #endif |
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986 } else { |
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987 __ ld_ptr(base, offset, to_reg->as_register()); |
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988 } |
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989 break; |
0 | 990 case T_ARRAY : // fall through |
2002 | 991 case T_OBJECT: |
992 { | |
993 if (UseCompressedOops && !wide) { | |
994 __ lduw(base, offset, to_reg->as_register()); | |
995 __ decode_heap_oop(to_reg->as_register()); | |
996 } else { | |
997 __ ld_ptr(base, offset, to_reg->as_register()); | |
998 } | |
999 break; | |
1000 } | |
0 | 1001 case T_FLOAT: __ ldf(FloatRegisterImpl::S, base, offset, to_reg->as_float_reg()); break; |
1002 case T_DOUBLE: | |
1003 { | |
1004 FloatRegister reg = to_reg->as_double_reg(); | |
1005 // split unaligned loads | |
1006 if (unaligned || PatchALot) { | |
1060 | 1007 __ ldf(FloatRegisterImpl::S, base, offset + 4, reg->successor()); |
1008 __ ldf(FloatRegisterImpl::S, base, offset, reg); | |
0 | 1009 } else { |
1010 __ ldf(FloatRegisterImpl::D, base, offset, to_reg->as_double_reg()); | |
1011 } | |
1012 break; | |
1013 } | |
1014 default : ShouldNotReachHere(); | |
1015 } | |
2002 | 1016 if (type == T_ARRAY || type == T_OBJECT) { |
1017 __ verify_oop(to_reg->as_register()); | |
1018 } | |
0 | 1019 } |
1020 return load_offset; | |
1021 } | |
1022 | |
1023 | |
2002 | 1024 int LIR_Assembler::load(Register base, Register disp, LIR_Opr to_reg, BasicType type, bool wide) { |
0 | 1025 int load_offset = code_offset(); |
1026 switch(type) { | |
1027 case T_BOOLEAN: // fall through | |
2002 | 1028 case T_BYTE : __ ldsb(base, disp, to_reg->as_register()); break; |
1029 case T_CHAR : __ lduh(base, disp, to_reg->as_register()); break; | |
1030 case T_SHORT : __ ldsh(base, disp, to_reg->as_register()); break; | |
1031 case T_INT : __ ld(base, disp, to_reg->as_register()); break; | |
1032 case T_ADDRESS: __ ld_ptr(base, disp, to_reg->as_register()); break; | |
0 | 1033 case T_ARRAY : // fall through |
2002 | 1034 case T_OBJECT: |
1035 { | |
1036 if (UseCompressedOops && !wide) { | |
1037 __ lduw(base, disp, to_reg->as_register()); | |
1038 __ decode_heap_oop(to_reg->as_register()); | |
1039 } else { | |
1040 __ ld_ptr(base, disp, to_reg->as_register()); | |
1041 } | |
1042 break; | |
1043 } | |
0 | 1044 case T_FLOAT: __ ldf(FloatRegisterImpl::S, base, disp, to_reg->as_float_reg()); break; |
1045 case T_DOUBLE: __ ldf(FloatRegisterImpl::D, base, disp, to_reg->as_double_reg()); break; | |
1046 case T_LONG : | |
1047 #ifdef _LP64 | |
1048 __ ldx(base, disp, to_reg->as_register_lo()); | |
1049 #else | |
1050 assert(to_reg->as_register_hi()->successor() == to_reg->as_register_lo(), | |
1051 "must be sequential"); | |
1052 __ ldd(base, disp, to_reg->as_register_hi()); | |
1053 #endif | |
1054 break; | |
1055 default : ShouldNotReachHere(); | |
1056 } | |
2002 | 1057 if (type == T_ARRAY || type == T_OBJECT) { |
1058 __ verify_oop(to_reg->as_register()); | |
1059 } | |
0 | 1060 return load_offset; |
1061 } | |
1062 | |
1063 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) { | |
1064 LIR_Const* c = src->as_constant_ptr(); | |
1065 switch (c->type()) { | |
1066 case T_INT: | |
2002 | 1067 case T_FLOAT: { |
1068 Register src_reg = O7; | |
1069 int value = c->as_jint_bits(); | |
1070 if (value == 0) { | |
1071 src_reg = G0; | |
1072 } else { | |
1073 __ set(value, O7); | |
1074 } | |
1075 Address addr = frame_map()->address_for_slot(dest->single_stack_ix()); | |
1076 __ stw(src_reg, addr.base(), addr.disp()); | |
1077 break; | |
1078 } | |
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1079 case T_ADDRESS: { |
0 | 1080 Register src_reg = O7; |
1081 int value = c->as_jint_bits(); | |
1082 if (value == 0) { | |
1083 src_reg = G0; | |
1084 } else { | |
1085 __ set(value, O7); | |
1086 } | |
1087 Address addr = frame_map()->address_for_slot(dest->single_stack_ix()); | |
2002 | 1088 __ st_ptr(src_reg, addr.base(), addr.disp()); |
0 | 1089 break; |
1090 } | |
1091 case T_OBJECT: { | |
1092 Register src_reg = O7; | |
1093 jobject2reg(c->as_jobject(), src_reg); | |
1094 Address addr = frame_map()->address_for_slot(dest->single_stack_ix()); | |
1095 __ st_ptr(src_reg, addr.base(), addr.disp()); | |
1096 break; | |
1097 } | |
1098 case T_LONG: | |
1099 case T_DOUBLE: { | |
1100 Address addr = frame_map()->address_for_double_slot(dest->double_stack_ix()); | |
1101 | |
1102 Register tmp = O7; | |
1103 int value_lo = c->as_jint_lo_bits(); | |
1104 if (value_lo == 0) { | |
1105 tmp = G0; | |
1106 } else { | |
1107 __ set(value_lo, O7); | |
1108 } | |
1109 __ stw(tmp, addr.base(), addr.disp() + lo_word_offset_in_bytes); | |
1110 int value_hi = c->as_jint_hi_bits(); | |
1111 if (value_hi == 0) { | |
1112 tmp = G0; | |
1113 } else { | |
1114 __ set(value_hi, O7); | |
1115 } | |
1116 __ stw(tmp, addr.base(), addr.disp() + hi_word_offset_in_bytes); | |
1117 break; | |
1118 } | |
1119 default: | |
1120 Unimplemented(); | |
1121 } | |
1122 } | |
1123 | |
1124 | |
2002 | 1125 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) { |
0 | 1126 LIR_Const* c = src->as_constant_ptr(); |
1127 LIR_Address* addr = dest->as_address_ptr(); | |
1128 Register base = addr->base()->as_pointer_register(); | |
2002 | 1129 int offset = -1; |
1130 | |
0 | 1131 switch (c->type()) { |
1132 case T_INT: | |
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1133 case T_FLOAT: |
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1134 case T_ADDRESS: { |
0 | 1135 LIR_Opr tmp = FrameMap::O7_opr; |
1136 int value = c->as_jint_bits(); | |
1137 if (value == 0) { | |
1138 tmp = FrameMap::G0_opr; | |
1139 } else if (Assembler::is_simm13(value)) { | |
1140 __ set(value, O7); | |
1141 } | |
1142 if (addr->index()->is_valid()) { | |
1143 assert(addr->disp() == 0, "must be zero"); | |
2002 | 1144 offset = store(tmp, base, addr->index()->as_pointer_register(), type, wide); |
0 | 1145 } else { |
1146 assert(Assembler::is_simm13(addr->disp()), "can't handle larger addresses"); | |
2002 | 1147 offset = store(tmp, base, addr->disp(), type, wide, false); |
0 | 1148 } |
1149 break; | |
1150 } | |
1151 case T_LONG: | |
1152 case T_DOUBLE: { | |
1153 assert(!addr->index()->is_valid(), "can't handle reg reg address here"); | |
1154 assert(Assembler::is_simm13(addr->disp()) && | |
1155 Assembler::is_simm13(addr->disp() + 4), "can't handle larger addresses"); | |
1156 | |
2002 | 1157 LIR_Opr tmp = FrameMap::O7_opr; |
0 | 1158 int value_lo = c->as_jint_lo_bits(); |
1159 if (value_lo == 0) { | |
2002 | 1160 tmp = FrameMap::G0_opr; |
0 | 1161 } else { |
1162 __ set(value_lo, O7); | |
1163 } | |
2002 | 1164 offset = store(tmp, base, addr->disp() + lo_word_offset_in_bytes, T_INT, wide, false); |
0 | 1165 int value_hi = c->as_jint_hi_bits(); |
1166 if (value_hi == 0) { | |
2002 | 1167 tmp = FrameMap::G0_opr; |
0 | 1168 } else { |
1169 __ set(value_hi, O7); | |
1170 } | |
4052 | 1171 store(tmp, base, addr->disp() + hi_word_offset_in_bytes, T_INT, wide, false); |
0 | 1172 break; |
1173 } | |
1174 case T_OBJECT: { | |
1175 jobject obj = c->as_jobject(); | |
1176 LIR_Opr tmp; | |
1177 if (obj == NULL) { | |
1178 tmp = FrameMap::G0_opr; | |
1179 } else { | |
1180 tmp = FrameMap::O7_opr; | |
1181 jobject2reg(c->as_jobject(), O7); | |
1182 } | |
1183 // handle either reg+reg or reg+disp address | |
1184 if (addr->index()->is_valid()) { | |
1185 assert(addr->disp() == 0, "must be zero"); | |
2002 | 1186 offset = store(tmp, base, addr->index()->as_pointer_register(), type, wide); |
0 | 1187 } else { |
1188 assert(Assembler::is_simm13(addr->disp()), "can't handle larger addresses"); | |
2002 | 1189 offset = store(tmp, base, addr->disp(), type, wide, false); |
0 | 1190 } |
1191 | |
1192 break; | |
1193 } | |
1194 default: | |
1195 Unimplemented(); | |
1196 } | |
2002 | 1197 if (info != NULL) { |
1198 assert(offset != -1, "offset should've been set"); | |
1199 add_debug_info_for_null_check(offset, info); | |
1200 } | |
0 | 1201 } |
1202 | |
1203 | |
1204 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) { | |
1205 LIR_Const* c = src->as_constant_ptr(); | |
1206 LIR_Opr to_reg = dest; | |
1207 | |
1208 switch (c->type()) { | |
1209 case T_INT: | |
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1210 case T_ADDRESS: |
0 | 1211 { |
1212 jint con = c->as_jint(); | |
1213 if (to_reg->is_single_cpu()) { | |
1214 assert(patch_code == lir_patch_none, "no patching handled here"); | |
1215 __ set(con, to_reg->as_register()); | |
1216 } else { | |
1217 ShouldNotReachHere(); | |
1218 assert(to_reg->is_single_fpu(), "wrong register kind"); | |
1219 | |
1220 __ set(con, O7); | |
727 | 1221 Address temp_slot(SP, (frame::register_save_words * wordSize) + STACK_BIAS); |
0 | 1222 __ st(O7, temp_slot); |
1223 __ ldf(FloatRegisterImpl::S, temp_slot, to_reg->as_float_reg()); | |
1224 } | |
1225 } | |
1226 break; | |
1227 | |
1228 case T_LONG: | |
1229 { | |
1230 jlong con = c->as_jlong(); | |
1231 | |
1232 if (to_reg->is_double_cpu()) { | |
1233 #ifdef _LP64 | |
1234 __ set(con, to_reg->as_register_lo()); | |
1235 #else | |
1236 __ set(low(con), to_reg->as_register_lo()); | |
1237 __ set(high(con), to_reg->as_register_hi()); | |
1238 #endif | |
1239 #ifdef _LP64 | |
1240 } else if (to_reg->is_single_cpu()) { | |
1241 __ set(con, to_reg->as_register()); | |
1242 #endif | |
1243 } else { | |
1244 ShouldNotReachHere(); | |
1245 assert(to_reg->is_double_fpu(), "wrong register kind"); | |
727 | 1246 Address temp_slot_lo(SP, ((frame::register_save_words ) * wordSize) + STACK_BIAS); |
1247 Address temp_slot_hi(SP, ((frame::register_save_words) * wordSize) + (longSize/2) + STACK_BIAS); | |
0 | 1248 __ set(low(con), O7); |
1249 __ st(O7, temp_slot_lo); | |
1250 __ set(high(con), O7); | |
1251 __ st(O7, temp_slot_hi); | |
1252 __ ldf(FloatRegisterImpl::D, temp_slot_lo, to_reg->as_double_reg()); | |
1253 } | |
1254 } | |
1255 break; | |
1256 | |
1257 case T_OBJECT: | |
1258 { | |
1259 if (patch_code == lir_patch_none) { | |
1260 jobject2reg(c->as_jobject(), to_reg->as_register()); | |
1261 } else { | |
1262 jobject2reg_with_patching(to_reg->as_register(), info); | |
1263 } | |
1264 } | |
1265 break; | |
1266 | |
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1267 case T_METADATA: |
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1268 { |
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1269 if (patch_code == lir_patch_none) { |
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1270 metadata2reg(c->as_metadata(), to_reg->as_register()); |
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1271 } else { |
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1272 klass2reg_with_patching(to_reg->as_register(), info); |
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1273 } |
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1274 } |
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1275 break; |
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1276 |
0 | 1277 case T_FLOAT: |
1278 { | |
1279 address const_addr = __ float_constant(c->as_jfloat()); | |
1280 if (const_addr == NULL) { | |
1281 bailout("const section overflow"); | |
1282 break; | |
1283 } | |
1284 RelocationHolder rspec = internal_word_Relocation::spec(const_addr); | |
727 | 1285 AddressLiteral const_addrlit(const_addr, rspec); |
0 | 1286 if (to_reg->is_single_fpu()) { |
727 | 1287 __ patchable_sethi(const_addrlit, O7); |
0 | 1288 __ relocate(rspec); |
727 | 1289 __ ldf(FloatRegisterImpl::S, O7, const_addrlit.low10(), to_reg->as_float_reg()); |
0 | 1290 |
1291 } else { | |
1292 assert(to_reg->is_single_cpu(), "Must be a cpu register."); | |
1293 | |
727 | 1294 __ set(const_addrlit, O7); |
2002 | 1295 __ ld(O7, 0, to_reg->as_register()); |
0 | 1296 } |
1297 } | |
1298 break; | |
1299 | |
1300 case T_DOUBLE: | |
1301 { | |
1302 address const_addr = __ double_constant(c->as_jdouble()); | |
1303 if (const_addr == NULL) { | |
1304 bailout("const section overflow"); | |
1305 break; | |
1306 } | |
1307 RelocationHolder rspec = internal_word_Relocation::spec(const_addr); | |
1308 | |
1309 if (to_reg->is_double_fpu()) { | |
727 | 1310 AddressLiteral const_addrlit(const_addr, rspec); |
1311 __ patchable_sethi(const_addrlit, O7); | |
0 | 1312 __ relocate(rspec); |
727 | 1313 __ ldf (FloatRegisterImpl::D, O7, const_addrlit.low10(), to_reg->as_double_reg()); |
0 | 1314 } else { |
1315 assert(to_reg->is_double_cpu(), "Must be a long register."); | |
1316 #ifdef _LP64 | |
1317 __ set(jlong_cast(c->as_jdouble()), to_reg->as_register_lo()); | |
1318 #else | |
1319 __ set(low(jlong_cast(c->as_jdouble())), to_reg->as_register_lo()); | |
1320 __ set(high(jlong_cast(c->as_jdouble())), to_reg->as_register_hi()); | |
1321 #endif | |
1322 } | |
1323 | |
1324 } | |
1325 break; | |
1326 | |
1327 default: | |
1328 ShouldNotReachHere(); | |
1329 } | |
1330 } | |
1331 | |
1332 Address LIR_Assembler::as_Address(LIR_Address* addr) { | |
1333 Register reg = addr->base()->as_register(); | |
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1334 LIR_Opr index = addr->index(); |
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1335 if (index->is_illegal()) { |
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1336 return Address(reg, addr->disp()); |
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1337 } else { |
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1338 assert (addr->disp() == 0, "unsupported address mode"); |
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1339 return Address(reg, index->as_pointer_register()); |
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1340 } |
0 | 1341 } |
1342 | |
1343 | |
1344 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) { | |
1345 switch (type) { | |
1346 case T_INT: | |
1347 case T_FLOAT: { | |
1348 Register tmp = O7; | |
1349 Address from = frame_map()->address_for_slot(src->single_stack_ix()); | |
1350 Address to = frame_map()->address_for_slot(dest->single_stack_ix()); | |
1351 __ lduw(from.base(), from.disp(), tmp); | |
1352 __ stw(tmp, to.base(), to.disp()); | |
1353 break; | |
1354 } | |
1355 case T_OBJECT: { | |
1356 Register tmp = O7; | |
1357 Address from = frame_map()->address_for_slot(src->single_stack_ix()); | |
1358 Address to = frame_map()->address_for_slot(dest->single_stack_ix()); | |
1359 __ ld_ptr(from.base(), from.disp(), tmp); | |
1360 __ st_ptr(tmp, to.base(), to.disp()); | |
1361 break; | |
1362 } | |
1363 case T_LONG: | |
1364 case T_DOUBLE: { | |
1365 Register tmp = O7; | |
1366 Address from = frame_map()->address_for_double_slot(src->double_stack_ix()); | |
1367 Address to = frame_map()->address_for_double_slot(dest->double_stack_ix()); | |
1368 __ lduw(from.base(), from.disp(), tmp); | |
1369 __ stw(tmp, to.base(), to.disp()); | |
1370 __ lduw(from.base(), from.disp() + 4, tmp); | |
1371 __ stw(tmp, to.base(), to.disp() + 4); | |
1372 break; | |
1373 } | |
1374 | |
1375 default: | |
1376 ShouldNotReachHere(); | |
1377 } | |
1378 } | |
1379 | |
1380 | |
1381 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) { | |
1382 Address base = as_Address(addr); | |
727 | 1383 return Address(base.base(), base.disp() + hi_word_offset_in_bytes); |
0 | 1384 } |
1385 | |
1386 | |
1387 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) { | |
1388 Address base = as_Address(addr); | |
727 | 1389 return Address(base.base(), base.disp() + lo_word_offset_in_bytes); |
0 | 1390 } |
1391 | |
1392 | |
1393 void LIR_Assembler::mem2reg(LIR_Opr src_opr, LIR_Opr dest, BasicType type, | |
2002 | 1394 LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool unaligned) { |
0 | 1395 |
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1396 assert(type != T_METADATA, "load of metadata ptr not supported"); |
0 | 1397 LIR_Address* addr = src_opr->as_address_ptr(); |
1398 LIR_Opr to_reg = dest; | |
1399 | |
1400 Register src = addr->base()->as_pointer_register(); | |
1401 Register disp_reg = noreg; | |
1402 int disp_value = addr->disp(); | |
1403 bool needs_patching = (patch_code != lir_patch_none); | |
1404 | |
1405 if (addr->base()->type() == T_OBJECT) { | |
1406 __ verify_oop(src); | |
1407 } | |
1408 | |
1409 PatchingStub* patch = NULL; | |
1410 if (needs_patching) { | |
1411 patch = new PatchingStub(_masm, PatchingStub::access_field_id); | |
1412 assert(!to_reg->is_double_cpu() || | |
1413 patch_code == lir_patch_none || | |
1414 patch_code == lir_patch_normal, "patching doesn't match register"); | |
1415 } | |
1416 | |
1417 if (addr->index()->is_illegal()) { | |
1418 if (!Assembler::is_simm13(disp_value) && (!unaligned || Assembler::is_simm13(disp_value + 4))) { | |
1419 if (needs_patching) { | |
727 | 1420 __ patchable_set(0, O7); |
0 | 1421 } else { |
1422 __ set(disp_value, O7); | |
1423 } | |
1424 disp_reg = O7; | |
1425 } | |
1426 } else if (unaligned || PatchALot) { | |
1427 __ add(src, addr->index()->as_register(), O7); | |
1428 src = O7; | |
1429 } else { | |
1430 disp_reg = addr->index()->as_pointer_register(); | |
1431 assert(disp_value == 0, "can't handle 3 operand addresses"); | |
1432 } | |
1433 | |
1434 // remember the offset of the load. The patching_epilog must be done | |
1435 // before the call to add_debug_info, otherwise the PcDescs don't get | |
1436 // entered in increasing order. | |
1437 int offset = code_offset(); | |
1438 | |
1439 assert(disp_reg != noreg || Assembler::is_simm13(disp_value), "should have set this up"); | |
1440 if (disp_reg == noreg) { | |
2002 | 1441 offset = load(src, disp_value, to_reg, type, wide, unaligned); |
0 | 1442 } else { |
1443 assert(!unaligned, "can't handle this"); | |
2002 | 1444 offset = load(src, disp_reg, to_reg, type, wide); |
0 | 1445 } |
1446 | |
1447 if (patch != NULL) { | |
1448 patching_epilog(patch, patch_code, src, info); | |
1449 } | |
1450 if (info != NULL) add_debug_info_for_null_check(offset, info); | |
1451 } | |
1452 | |
1453 | |
1454 void LIR_Assembler::prefetchr(LIR_Opr src) { | |
1455 LIR_Address* addr = src->as_address_ptr(); | |
1456 Address from_addr = as_Address(addr); | |
1457 | |
1458 if (VM_Version::has_v9()) { | |
1459 __ prefetch(from_addr, Assembler::severalReads); | |
1460 } | |
1461 } | |
1462 | |
1463 | |
1464 void LIR_Assembler::prefetchw(LIR_Opr src) { | |
1465 LIR_Address* addr = src->as_address_ptr(); | |
1466 Address from_addr = as_Address(addr); | |
1467 | |
1468 if (VM_Version::has_v9()) { | |
1469 __ prefetch(from_addr, Assembler::severalWritesAndPossiblyReads); | |
1470 } | |
1471 } | |
1472 | |
1473 | |
1474 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) { | |
1475 Address addr; | |
1476 if (src->is_single_word()) { | |
1477 addr = frame_map()->address_for_slot(src->single_stack_ix()); | |
1478 } else if (src->is_double_word()) { | |
1479 addr = frame_map()->address_for_double_slot(src->double_stack_ix()); | |
1480 } | |
1481 | |
1482 bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0; | |
2002 | 1483 load(addr.base(), addr.disp(), dest, dest->type(), true /*wide*/, unaligned); |
0 | 1484 } |
1485 | |
1486 | |
1487 void LIR_Assembler::reg2stack(LIR_Opr from_reg, LIR_Opr dest, BasicType type, bool pop_fpu_stack) { | |
1488 Address addr; | |
1489 if (dest->is_single_word()) { | |
1490 addr = frame_map()->address_for_slot(dest->single_stack_ix()); | |
1491 } else if (dest->is_double_word()) { | |
1492 addr = frame_map()->address_for_slot(dest->double_stack_ix()); | |
1493 } | |
1494 bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0; | |
2002 | 1495 store(from_reg, addr.base(), addr.disp(), from_reg->type(), true /*wide*/, unaligned); |
0 | 1496 } |
1497 | |
1498 | |
1499 void LIR_Assembler::reg2reg(LIR_Opr from_reg, LIR_Opr to_reg) { | |
1500 if (from_reg->is_float_kind() && to_reg->is_float_kind()) { | |
1501 if (from_reg->is_double_fpu()) { | |
1502 // double to double moves | |
1503 assert(to_reg->is_double_fpu(), "should match"); | |
1504 __ fmov(FloatRegisterImpl::D, from_reg->as_double_reg(), to_reg->as_double_reg()); | |
1505 } else { | |
1506 // float to float moves | |
1507 assert(to_reg->is_single_fpu(), "should match"); | |
1508 __ fmov(FloatRegisterImpl::S, from_reg->as_float_reg(), to_reg->as_float_reg()); | |
1509 } | |
1510 } else if (!from_reg->is_float_kind() && !to_reg->is_float_kind()) { | |
1511 if (from_reg->is_double_cpu()) { | |
1512 #ifdef _LP64 | |
1513 __ mov(from_reg->as_pointer_register(), to_reg->as_pointer_register()); | |
1514 #else | |
1515 assert(to_reg->is_double_cpu() && | |
1516 from_reg->as_register_hi() != to_reg->as_register_lo() && | |
1517 from_reg->as_register_lo() != to_reg->as_register_hi(), | |
1518 "should both be long and not overlap"); | |
1519 // long to long moves | |
1520 __ mov(from_reg->as_register_hi(), to_reg->as_register_hi()); | |
1521 __ mov(from_reg->as_register_lo(), to_reg->as_register_lo()); | |
1522 #endif | |
1523 #ifdef _LP64 | |
1524 } else if (to_reg->is_double_cpu()) { | |
1525 // int to int moves | |
1526 __ mov(from_reg->as_register(), to_reg->as_register_lo()); | |
1527 #endif | |
1528 } else { | |
1529 // int to int moves | |
1530 __ mov(from_reg->as_register(), to_reg->as_register()); | |
1531 } | |
1532 } else { | |
1533 ShouldNotReachHere(); | |
1534 } | |
1535 if (to_reg->type() == T_OBJECT || to_reg->type() == T_ARRAY) { | |
1536 __ verify_oop(to_reg->as_register()); | |
1537 } | |
1538 } | |
1539 | |
1540 | |
1541 void LIR_Assembler::reg2mem(LIR_Opr from_reg, LIR_Opr dest, BasicType type, | |
1542 LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, | |
2002 | 1543 bool wide, bool unaligned) { |
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1544 assert(type != T_METADATA, "store of metadata ptr not supported"); |
0 | 1545 LIR_Address* addr = dest->as_address_ptr(); |
1546 | |
1547 Register src = addr->base()->as_pointer_register(); | |
1548 Register disp_reg = noreg; | |
1549 int disp_value = addr->disp(); | |
1550 bool needs_patching = (patch_code != lir_patch_none); | |
1551 | |
1552 if (addr->base()->is_oop_register()) { | |
1553 __ verify_oop(src); | |
1554 } | |
1555 | |
1556 PatchingStub* patch = NULL; | |
1557 if (needs_patching) { | |
1558 patch = new PatchingStub(_masm, PatchingStub::access_field_id); | |
1559 assert(!from_reg->is_double_cpu() || | |
1560 patch_code == lir_patch_none || | |
1561 patch_code == lir_patch_normal, "patching doesn't match register"); | |
1562 } | |
1563 | |
1564 if (addr->index()->is_illegal()) { | |
1565 if (!Assembler::is_simm13(disp_value) && (!unaligned || Assembler::is_simm13(disp_value + 4))) { | |
1566 if (needs_patching) { | |
727 | 1567 __ patchable_set(0, O7); |
0 | 1568 } else { |
1569 __ set(disp_value, O7); | |
1570 } | |
1571 disp_reg = O7; | |
1572 } | |
1573 } else if (unaligned || PatchALot) { | |
1574 __ add(src, addr->index()->as_register(), O7); | |
1575 src = O7; | |
1576 } else { | |
1577 disp_reg = addr->index()->as_pointer_register(); | |
1578 assert(disp_value == 0, "can't handle 3 operand addresses"); | |
1579 } | |
1580 | |
1581 // remember the offset of the store. The patching_epilog must be done | |
1582 // before the call to add_debug_info_for_null_check, otherwise the PcDescs don't get | |
1583 // entered in increasing order. | |
1584 int offset; | |
1585 | |
1586 assert(disp_reg != noreg || Assembler::is_simm13(disp_value), "should have set this up"); | |
1587 if (disp_reg == noreg) { | |
2002 | 1588 offset = store(from_reg, src, disp_value, type, wide, unaligned); |
0 | 1589 } else { |
1590 assert(!unaligned, "can't handle this"); | |
2002 | 1591 offset = store(from_reg, src, disp_reg, type, wide); |
0 | 1592 } |
1593 | |
1594 if (patch != NULL) { | |
1595 patching_epilog(patch, patch_code, src, info); | |
1596 } | |
1597 | |
1598 if (info != NULL) add_debug_info_for_null_check(offset, info); | |
1599 } | |
1600 | |
1601 | |
1602 void LIR_Assembler::return_op(LIR_Opr result) { | |
1603 // the poll may need a register so just pick one that isn't the return register | |
1783 | 1604 #if defined(TIERED) && !defined(_LP64) |
0 | 1605 if (result->type_field() == LIR_OprDesc::long_type) { |
1606 // Must move the result to G1 | |
1607 // Must leave proper result in O0,O1 and G1 (TIERED only) | |
1608 __ sllx(I0, 32, G1); // Shift bits into high G1 | |
1609 __ srl (I1, 0, I1); // Zero extend O1 (harmless?) | |
1610 __ or3 (I1, G1, G1); // OR 64 bits into G1 | |
1783 | 1611 #ifdef ASSERT |
1612 // mangle it so any problems will show up | |
1613 __ set(0xdeadbeef, I0); | |
1614 __ set(0xdeadbeef, I1); | |
1615 #endif | |
0 | 1616 } |
1617 #endif // TIERED | |
1618 __ set((intptr_t)os::get_polling_page(), L0); | |
1619 __ relocate(relocInfo::poll_return_type); | |
1620 __ ld_ptr(L0, 0, G0); | |
1621 __ ret(); | |
1622 __ delayed()->restore(); | |
1623 } | |
1624 | |
1625 | |
1626 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) { | |
1627 __ set((intptr_t)os::get_polling_page(), tmp->as_register()); | |
1628 if (info != NULL) { | |
1629 add_debug_info_for_branch(info); | |
1630 } else { | |
1631 __ relocate(relocInfo::poll_type); | |
1632 } | |
1633 | |
1634 int offset = __ offset(); | |
1635 __ ld_ptr(tmp->as_register(), 0, G0); | |
1636 | |
1637 return offset; | |
1638 } | |
1639 | |
1640 | |
1641 void LIR_Assembler::emit_static_call_stub() { | |
1642 address call_pc = __ pc(); | |
1643 address stub = __ start_a_stub(call_stub_size); | |
1644 if (stub == NULL) { | |
1645 bailout("static call stub overflow"); | |
1646 return; | |
1647 } | |
1648 | |
1649 int start = __ offset(); | |
1650 __ relocate(static_stub_Relocation::spec(call_pc)); | |
1651 | |
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1652 __ set_metadata(NULL, G5); |
0 | 1653 // must be set to -1 at code generation time |
727 | 1654 AddressLiteral addrlit(-1); |
1655 __ jump_to(addrlit, G3); | |
0 | 1656 __ delayed()->nop(); |
1657 | |
1658 assert(__ offset() - start <= call_stub_size, "stub too big"); | |
1659 __ end_a_stub(); | |
1660 } | |
1661 | |
1662 | |
1663 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) { | |
1664 if (opr1->is_single_fpu()) { | |
1665 __ fcmp(FloatRegisterImpl::S, Assembler::fcc0, opr1->as_float_reg(), opr2->as_float_reg()); | |
1666 } else if (opr1->is_double_fpu()) { | |
1667 __ fcmp(FloatRegisterImpl::D, Assembler::fcc0, opr1->as_double_reg(), opr2->as_double_reg()); | |
1668 } else if (opr1->is_single_cpu()) { | |
1669 if (opr2->is_constant()) { | |
1670 switch (opr2->as_constant_ptr()->type()) { | |
1671 case T_INT: | |
1672 { jint con = opr2->as_constant_ptr()->as_jint(); | |
1673 if (Assembler::is_simm13(con)) { | |
1674 __ cmp(opr1->as_register(), con); | |
1675 } else { | |
1676 __ set(con, O7); | |
1677 __ cmp(opr1->as_register(), O7); | |
1678 } | |
1679 } | |
1680 break; | |
1681 | |
1682 case T_OBJECT: | |
1683 // there are only equal/notequal comparisions on objects | |
1684 { jobject con = opr2->as_constant_ptr()->as_jobject(); | |
1685 if (con == NULL) { | |
1686 __ cmp(opr1->as_register(), 0); | |
1687 } else { | |
1688 jobject2reg(con, O7); | |
1689 __ cmp(opr1->as_register(), O7); | |
1690 } | |
1691 } | |
1692 break; | |
1693 | |
1694 default: | |
1695 ShouldNotReachHere(); | |
1696 break; | |
1697 } | |
1698 } else { | |
1699 if (opr2->is_address()) { | |
1700 LIR_Address * addr = opr2->as_address_ptr(); | |
1701 BasicType type = addr->type(); | |
1702 if ( type == T_OBJECT ) __ ld_ptr(as_Address(addr), O7); | |
1703 else __ ld(as_Address(addr), O7); | |
1704 __ cmp(opr1->as_register(), O7); | |
1705 } else { | |
1706 __ cmp(opr1->as_register(), opr2->as_register()); | |
1707 } | |
1708 } | |
1709 } else if (opr1->is_double_cpu()) { | |
1710 Register xlo = opr1->as_register_lo(); | |
1711 Register xhi = opr1->as_register_hi(); | |
1712 if (opr2->is_constant() && opr2->as_jlong() == 0) { | |
1713 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles these cases"); | |
1714 #ifdef _LP64 | |
1715 __ orcc(xhi, G0, G0); | |
1716 #else | |
1717 __ orcc(xhi, xlo, G0); | |
1718 #endif | |
1719 } else if (opr2->is_register()) { | |
1720 Register ylo = opr2->as_register_lo(); | |
1721 Register yhi = opr2->as_register_hi(); | |
1722 #ifdef _LP64 | |
1723 __ cmp(xlo, ylo); | |
1724 #else | |
1725 __ subcc(xlo, ylo, xlo); | |
1726 __ subccc(xhi, yhi, xhi); | |
1727 if (condition == lir_cond_equal || condition == lir_cond_notEqual) { | |
1728 __ orcc(xhi, xlo, G0); | |
1729 } | |
1730 #endif | |
1731 } else { | |
1732 ShouldNotReachHere(); | |
1733 } | |
1734 } else if (opr1->is_address()) { | |
1735 LIR_Address * addr = opr1->as_address_ptr(); | |
1736 BasicType type = addr->type(); | |
1737 assert (opr2->is_constant(), "Checking"); | |
1738 if ( type == T_OBJECT ) __ ld_ptr(as_Address(addr), O7); | |
1739 else __ ld(as_Address(addr), O7); | |
1740 __ cmp(O7, opr2->as_constant_ptr()->as_jint()); | |
1741 } else { | |
1742 ShouldNotReachHere(); | |
1743 } | |
1744 } | |
1745 | |
1746 | |
1747 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){ | |
1748 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) { | |
1749 bool is_unordered_less = (code == lir_ucmp_fd2i); | |
1750 if (left->is_single_fpu()) { | |
1751 __ float_cmp(true, is_unordered_less ? -1 : 1, left->as_float_reg(), right->as_float_reg(), dst->as_register()); | |
1752 } else if (left->is_double_fpu()) { | |
1753 __ float_cmp(false, is_unordered_less ? -1 : 1, left->as_double_reg(), right->as_double_reg(), dst->as_register()); | |
1754 } else { | |
1755 ShouldNotReachHere(); | |
1756 } | |
1757 } else if (code == lir_cmp_l2i) { | |
1369 | 1758 #ifdef _LP64 |
1759 __ lcmp(left->as_register_lo(), right->as_register_lo(), dst->as_register()); | |
1760 #else | |
0 | 1761 __ lcmp(left->as_register_hi(), left->as_register_lo(), |
1762 right->as_register_hi(), right->as_register_lo(), | |
1763 dst->as_register()); | |
1369 | 1764 #endif |
0 | 1765 } else { |
1766 ShouldNotReachHere(); | |
1767 } | |
1768 } | |
1769 | |
1770 | |
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1771 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) { |
0 | 1772 Assembler::Condition acond; |
1773 switch (condition) { | |
1774 case lir_cond_equal: acond = Assembler::equal; break; | |
1775 case lir_cond_notEqual: acond = Assembler::notEqual; break; | |
1776 case lir_cond_less: acond = Assembler::less; break; | |
1777 case lir_cond_lessEqual: acond = Assembler::lessEqual; break; | |
1778 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; break; | |
1779 case lir_cond_greater: acond = Assembler::greater; break; | |
1780 case lir_cond_aboveEqual: acond = Assembler::greaterEqualUnsigned; break; | |
1781 case lir_cond_belowEqual: acond = Assembler::lessEqualUnsigned; break; | |
1782 default: ShouldNotReachHere(); | |
1783 }; | |
1784 | |
1785 if (opr1->is_constant() && opr1->type() == T_INT) { | |
1786 Register dest = result->as_register(); | |
1787 // load up first part of constant before branch | |
1788 // and do the rest in the delay slot. | |
1789 if (!Assembler::is_simm13(opr1->as_jint())) { | |
1790 __ sethi(opr1->as_jint(), dest); | |
1791 } | |
1792 } else if (opr1->is_constant()) { | |
1793 const2reg(opr1, result, lir_patch_none, NULL); | |
1794 } else if (opr1->is_register()) { | |
1795 reg2reg(opr1, result); | |
1796 } else if (opr1->is_stack()) { | |
1797 stack2reg(opr1, result, result->type()); | |
1798 } else { | |
1799 ShouldNotReachHere(); | |
1800 } | |
1801 Label skip; | |
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1802 #ifdef _LP64 |
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1803 if (type == T_INT) { |
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1804 __ br(acond, false, Assembler::pt, skip); |
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1805 } else |
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1806 #endif |
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1807 __ brx(acond, false, Assembler::pt, skip); // checks icc on 32bit and xcc on 64bit |
0 | 1808 if (opr1->is_constant() && opr1->type() == T_INT) { |
1809 Register dest = result->as_register(); | |
1810 if (Assembler::is_simm13(opr1->as_jint())) { | |
1811 __ delayed()->or3(G0, opr1->as_jint(), dest); | |
1812 } else { | |
1813 // the sethi has been done above, so just put in the low 10 bits | |
1814 __ delayed()->or3(dest, opr1->as_jint() & 0x3ff, dest); | |
1815 } | |
1816 } else { | |
1817 // can't do anything useful in the delay slot | |
1818 __ delayed()->nop(); | |
1819 } | |
1820 if (opr2->is_constant()) { | |
1821 const2reg(opr2, result, lir_patch_none, NULL); | |
1822 } else if (opr2->is_register()) { | |
1823 reg2reg(opr2, result); | |
1824 } else if (opr2->is_stack()) { | |
1825 stack2reg(opr2, result, result->type()); | |
1826 } else { | |
1827 ShouldNotReachHere(); | |
1828 } | |
1829 __ bind(skip); | |
1830 } | |
1831 | |
1832 | |
1833 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) { | |
1834 assert(info == NULL, "unused on this code path"); | |
1835 assert(left->is_register(), "wrong items state"); | |
1836 assert(dest->is_register(), "wrong items state"); | |
1837 | |
1838 if (right->is_register()) { | |
1839 if (dest->is_float_kind()) { | |
1840 | |
1841 FloatRegister lreg, rreg, res; | |
1842 FloatRegisterImpl::Width w; | |
1843 if (right->is_single_fpu()) { | |
1844 w = FloatRegisterImpl::S; | |
1845 lreg = left->as_float_reg(); | |
1846 rreg = right->as_float_reg(); | |
1847 res = dest->as_float_reg(); | |
1848 } else { | |
1849 w = FloatRegisterImpl::D; | |
1850 lreg = left->as_double_reg(); | |
1851 rreg = right->as_double_reg(); | |
1852 res = dest->as_double_reg(); | |
1853 } | |
1854 | |
1855 switch (code) { | |
1856 case lir_add: __ fadd(w, lreg, rreg, res); break; | |
1857 case lir_sub: __ fsub(w, lreg, rreg, res); break; | |
1858 case lir_mul: // fall through | |
1859 case lir_mul_strictfp: __ fmul(w, lreg, rreg, res); break; | |
1860 case lir_div: // fall through | |
1861 case lir_div_strictfp: __ fdiv(w, lreg, rreg, res); break; | |
1862 default: ShouldNotReachHere(); | |
1863 } | |
1864 | |
1865 } else if (dest->is_double_cpu()) { | |
1866 #ifdef _LP64 | |
1867 Register dst_lo = dest->as_register_lo(); | |
1868 Register op1_lo = left->as_pointer_register(); | |
1869 Register op2_lo = right->as_pointer_register(); | |
1870 | |
1871 switch (code) { | |
1872 case lir_add: | |
1873 __ add(op1_lo, op2_lo, dst_lo); | |
1874 break; | |
1875 | |
1876 case lir_sub: | |
1877 __ sub(op1_lo, op2_lo, dst_lo); | |
1878 break; | |
1879 | |
1880 default: ShouldNotReachHere(); | |
1881 } | |
1882 #else | |
1883 Register op1_lo = left->as_register_lo(); | |
1884 Register op1_hi = left->as_register_hi(); | |
1885 Register op2_lo = right->as_register_lo(); | |
1886 Register op2_hi = right->as_register_hi(); | |
1887 Register dst_lo = dest->as_register_lo(); | |
1888 Register dst_hi = dest->as_register_hi(); | |
1889 | |
1890 switch (code) { | |
1891 case lir_add: | |
1892 __ addcc(op1_lo, op2_lo, dst_lo); | |
1893 __ addc (op1_hi, op2_hi, dst_hi); | |
1894 break; | |
1895 | |
1896 case lir_sub: | |
1897 __ subcc(op1_lo, op2_lo, dst_lo); | |
1898 __ subc (op1_hi, op2_hi, dst_hi); | |
1899 break; | |
1900 | |
1901 default: ShouldNotReachHere(); | |
1902 } | |
1903 #endif | |
1904 } else { | |
1905 assert (right->is_single_cpu(), "Just Checking"); | |
1906 | |
1907 Register lreg = left->as_register(); | |
1908 Register res = dest->as_register(); | |
1909 Register rreg = right->as_register(); | |
1910 switch (code) { | |
1911 case lir_add: __ add (lreg, rreg, res); break; | |
1912 case lir_sub: __ sub (lreg, rreg, res); break; | |
1913 case lir_mul: __ mult (lreg, rreg, res); break; | |
1914 default: ShouldNotReachHere(); | |
1915 } | |
1916 } | |
1917 } else { | |
1918 assert (right->is_constant(), "must be constant"); | |
1919 | |
1920 if (dest->is_single_cpu()) { | |
1921 Register lreg = left->as_register(); | |
1922 Register res = dest->as_register(); | |
1923 int simm13 = right->as_constant_ptr()->as_jint(); | |
1924 | |
1925 switch (code) { | |
1926 case lir_add: __ add (lreg, simm13, res); break; | |
1927 case lir_sub: __ sub (lreg, simm13, res); break; | |
1928 case lir_mul: __ mult (lreg, simm13, res); break; | |
1929 default: ShouldNotReachHere(); | |
1930 } | |
1931 } else { | |
1932 Register lreg = left->as_pointer_register(); | |
1933 Register res = dest->as_register_lo(); | |
1934 long con = right->as_constant_ptr()->as_jlong(); | |
1935 assert(Assembler::is_simm13(con), "must be simm13"); | |
1936 | |
1937 switch (code) { | |
1938 case lir_add: __ add (lreg, (int)con, res); break; | |
1939 case lir_sub: __ sub (lreg, (int)con, res); break; | |
1940 case lir_mul: __ mult (lreg, (int)con, res); break; | |
1941 default: ShouldNotReachHere(); | |
1942 } | |
1943 } | |
1944 } | |
1945 } | |
1946 | |
1947 | |
1948 void LIR_Assembler::fpop() { | |
1949 // do nothing | |
1950 } | |
1951 | |
1952 | |
1953 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr thread, LIR_Opr dest, LIR_Op* op) { | |
1954 switch (code) { | |
1955 case lir_sin: | |
1956 case lir_tan: | |
1957 case lir_cos: { | |
1958 assert(thread->is_valid(), "preserve the thread object for performance reasons"); | |
1959 assert(dest->as_double_reg() == F0, "the result will be in f0/f1"); | |
1960 break; | |
1961 } | |
1962 case lir_sqrt: { | |
1963 assert(!thread->is_valid(), "there is no need for a thread_reg for dsqrt"); | |
1964 FloatRegister src_reg = value->as_double_reg(); | |
1965 FloatRegister dst_reg = dest->as_double_reg(); | |
1966 __ fsqrt(FloatRegisterImpl::D, src_reg, dst_reg); | |
1967 break; | |
1968 } | |
1969 case lir_abs: { | |
1970 assert(!thread->is_valid(), "there is no need for a thread_reg for fabs"); | |
1971 FloatRegister src_reg = value->as_double_reg(); | |
1972 FloatRegister dst_reg = dest->as_double_reg(); | |
1973 __ fabs(FloatRegisterImpl::D, src_reg, dst_reg); | |
1974 break; | |
1975 } | |
1976 default: { | |
1977 ShouldNotReachHere(); | |
1978 break; | |
1979 } | |
1980 } | |
1981 } | |
1982 | |
1983 | |
1984 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest) { | |
1985 if (right->is_constant()) { | |
1986 if (dest->is_single_cpu()) { | |
1987 int simm13 = right->as_constant_ptr()->as_jint(); | |
1988 switch (code) { | |
1989 case lir_logic_and: __ and3 (left->as_register(), simm13, dest->as_register()); break; | |
1990 case lir_logic_or: __ or3 (left->as_register(), simm13, dest->as_register()); break; | |
1991 case lir_logic_xor: __ xor3 (left->as_register(), simm13, dest->as_register()); break; | |
1992 default: ShouldNotReachHere(); | |
1993 } | |
1994 } else { | |
1995 long c = right->as_constant_ptr()->as_jlong(); | |
1996 assert(c == (int)c && Assembler::is_simm13(c), "out of range"); | |
1997 int simm13 = (int)c; | |
1998 switch (code) { | |
1999 case lir_logic_and: | |
2000 #ifndef _LP64 | |
2001 __ and3 (left->as_register_hi(), 0, dest->as_register_hi()); | |
2002 #endif | |
2003 __ and3 (left->as_register_lo(), simm13, dest->as_register_lo()); | |
2004 break; | |
2005 | |
2006 case lir_logic_or: | |
2007 #ifndef _LP64 | |
2008 __ or3 (left->as_register_hi(), 0, dest->as_register_hi()); | |
2009 #endif | |
2010 __ or3 (left->as_register_lo(), simm13, dest->as_register_lo()); | |
2011 break; | |
2012 | |
2013 case lir_logic_xor: | |
2014 #ifndef _LP64 | |
2015 __ xor3 (left->as_register_hi(), 0, dest->as_register_hi()); | |
2016 #endif | |
2017 __ xor3 (left->as_register_lo(), simm13, dest->as_register_lo()); | |
2018 break; | |
2019 | |
2020 default: ShouldNotReachHere(); | |
2021 } | |
2022 } | |
2023 } else { | |
2024 assert(right->is_register(), "right should be in register"); | |
2025 | |
2026 if (dest->is_single_cpu()) { | |
2027 switch (code) { | |
2028 case lir_logic_and: __ and3 (left->as_register(), right->as_register(), dest->as_register()); break; | |
2029 case lir_logic_or: __ or3 (left->as_register(), right->as_register(), dest->as_register()); break; | |
2030 case lir_logic_xor: __ xor3 (left->as_register(), right->as_register(), dest->as_register()); break; | |
2031 default: ShouldNotReachHere(); | |
2032 } | |
2033 } else { | |
2034 #ifdef _LP64 | |
2035 Register l = (left->is_single_cpu() && left->is_oop_register()) ? left->as_register() : | |
2036 left->as_register_lo(); | |
2037 Register r = (right->is_single_cpu() && right->is_oop_register()) ? right->as_register() : | |
2038 right->as_register_lo(); | |
2039 | |
2040 switch (code) { | |
2041 case lir_logic_and: __ and3 (l, r, dest->as_register_lo()); break; | |
2042 case lir_logic_or: __ or3 (l, r, dest->as_register_lo()); break; | |
2043 case lir_logic_xor: __ xor3 (l, r, dest->as_register_lo()); break; | |
2044 default: ShouldNotReachHere(); | |
2045 } | |
2046 #else | |
2047 switch (code) { | |
2048 case lir_logic_and: | |
2049 __ and3 (left->as_register_hi(), right->as_register_hi(), dest->as_register_hi()); | |
2050 __ and3 (left->as_register_lo(), right->as_register_lo(), dest->as_register_lo()); | |
2051 break; | |
2052 | |
2053 case lir_logic_or: | |
2054 __ or3 (left->as_register_hi(), right->as_register_hi(), dest->as_register_hi()); | |
2055 __ or3 (left->as_register_lo(), right->as_register_lo(), dest->as_register_lo()); | |
2056 break; | |
2057 | |
2058 case lir_logic_xor: | |
2059 __ xor3 (left->as_register_hi(), right->as_register_hi(), dest->as_register_hi()); | |
2060 __ xor3 (left->as_register_lo(), right->as_register_lo(), dest->as_register_lo()); | |
2061 break; | |
2062 | |
2063 default: ShouldNotReachHere(); | |
2064 } | |
2065 #endif | |
2066 } | |
2067 } | |
2068 } | |
2069 | |
2070 | |
2071 int LIR_Assembler::shift_amount(BasicType t) { | |
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2072 int elem_size = type2aelembytes(t); |
0 | 2073 switch (elem_size) { |
2074 case 1 : return 0; | |
2075 case 2 : return 1; | |
2076 case 4 : return 2; | |
2077 case 8 : return 3; | |
2078 } | |
2079 ShouldNotReachHere(); | |
2080 return -1; | |
2081 } | |
2082 | |
2083 | |
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2084 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) { |
0 | 2085 assert(exceptionOop->as_register() == Oexception, "should match"); |
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2086 assert(exceptionPC->as_register() == Oissuing_pc, "should match"); |
0 | 2087 |
2088 info->add_register_oop(exceptionOop); | |
2089 | |
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2090 // reuse the debug info from the safepoint poll for the throw op itself |
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2091 address pc_for_athrow = __ pc(); |
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2092 int pc_for_athrow_offset = __ offset(); |
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2093 RelocationHolder rspec = internal_word_Relocation::spec(pc_for_athrow); |
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2094 __ set(pc_for_athrow, Oissuing_pc, rspec); |
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2095 add_call_info(pc_for_athrow_offset, info); // for exception handler |
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2096 |
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2097 __ call(Runtime1::entry_for(Runtime1::handle_exception_id), relocInfo::runtime_call_type); |
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2098 __ delayed()->nop(); |
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2099 } |
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2100 |
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2101 |
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2102 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) { |
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2103 assert(exceptionOop->as_register() == Oexception, "should match"); |
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2104 |
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2105 __ br(Assembler::always, false, Assembler::pt, _unwind_handler_entry); |
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2106 __ delayed()->nop(); |
0 | 2107 } |
2108 | |
2109 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) { | |
2110 Register src = op->src()->as_register(); | |
2111 Register dst = op->dst()->as_register(); | |
2112 Register src_pos = op->src_pos()->as_register(); | |
2113 Register dst_pos = op->dst_pos()->as_register(); | |
2114 Register length = op->length()->as_register(); | |
2115 Register tmp = op->tmp()->as_register(); | |
2116 Register tmp2 = O7; | |
2117 | |
2118 int flags = op->flags(); | |
2119 ciArrayKlass* default_type = op->expected_type(); | |
2120 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL; | |
2121 if (basic_type == T_ARRAY) basic_type = T_OBJECT; | |
2122 | |
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2123 #ifdef _LP64 |
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2124 // higher 32bits must be null |
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2125 __ sra(dst_pos, 0, dst_pos); |
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2126 __ sra(src_pos, 0, src_pos); |
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2127 __ sra(length, 0, length); |
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2128 #endif |
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2129 |
0 | 2130 // set up the arraycopy stub information |
2131 ArrayCopyStub* stub = op->stub(); | |
2132 | |
2133 // always do stub if no type information is available. it's ok if | |
2134 // the known type isn't loaded since the code sanity checks | |
2135 // in debug mode and the type isn't required when we know the exact type | |
2136 // also check that the type is an array type. | |
2446 | 2137 if (op->expected_type() == NULL) { |
0 | 2138 __ mov(src, O0); |
2139 __ mov(src_pos, O1); | |
2140 __ mov(dst, O2); | |
2141 __ mov(dst_pos, O3); | |
2142 __ mov(length, O4); | |
2446 | 2143 address copyfunc_addr = StubRoutines::generic_arraycopy(); |
2144 | |
2145 if (copyfunc_addr == NULL) { // Use C version if stub was not generated | |
2146 __ call_VM_leaf(tmp, CAST_FROM_FN_PTR(address, Runtime1::arraycopy)); | |
2147 } else { | |
2148 #ifndef PRODUCT | |
2149 if (PrintC1Statistics) { | |
2150 address counter = (address)&Runtime1::_generic_arraycopystub_cnt; | |
2151 __ inc_counter(counter, G1, G3); | |
2152 } | |
2153 #endif | |
2154 __ call_VM_leaf(tmp, copyfunc_addr); | |
2155 } | |
2156 | |
2157 if (copyfunc_addr != NULL) { | |
2158 __ xor3(O0, -1, tmp); | |
2159 __ sub(length, tmp, length); | |
2160 __ add(src_pos, tmp, src_pos); | |
3839 | 2161 __ cmp_zero_and_br(Assembler::less, O0, *stub->entry()); |
2446 | 2162 __ delayed()->add(dst_pos, tmp, dst_pos); |
2163 } else { | |
3839 | 2164 __ cmp_zero_and_br(Assembler::less, O0, *stub->entry()); |
2446 | 2165 __ delayed()->nop(); |
2166 } | |
0 | 2167 __ bind(*stub->continuation()); |
2168 return; | |
2169 } | |
2170 | |
2171 assert(default_type != NULL && default_type->is_array_klass(), "must be true at this point"); | |
2172 | |
2173 // make sure src and dst are non-null and load array length | |
2174 if (flags & LIR_OpArrayCopy::src_null_check) { | |
2175 __ tst(src); | |
2002 | 2176 __ brx(Assembler::equal, false, Assembler::pn, *stub->entry()); |
0 | 2177 __ delayed()->nop(); |
2178 } | |
2179 | |
2180 if (flags & LIR_OpArrayCopy::dst_null_check) { | |
2181 __ tst(dst); | |
2002 | 2182 __ brx(Assembler::equal, false, Assembler::pn, *stub->entry()); |
0 | 2183 __ delayed()->nop(); |
2184 } | |
2185 | |
2186 if (flags & LIR_OpArrayCopy::src_pos_positive_check) { | |
2187 // test src_pos register | |
3839 | 2188 __ cmp_zero_and_br(Assembler::less, src_pos, *stub->entry()); |
0 | 2189 __ delayed()->nop(); |
2190 } | |
2191 | |
2192 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) { | |
2193 // test dst_pos register | |
3839 | 2194 __ cmp_zero_and_br(Assembler::less, dst_pos, *stub->entry()); |
0 | 2195 __ delayed()->nop(); |
2196 } | |
2197 | |
2198 if (flags & LIR_OpArrayCopy::length_positive_check) { | |
2199 // make sure length isn't negative | |
3839 | 2200 __ cmp_zero_and_br(Assembler::less, length, *stub->entry()); |
0 | 2201 __ delayed()->nop(); |
2202 } | |
2203 | |
2204 if (flags & LIR_OpArrayCopy::src_range_check) { | |
2205 __ ld(src, arrayOopDesc::length_offset_in_bytes(), tmp2); | |
2206 __ add(length, src_pos, tmp); | |
2207 __ cmp(tmp2, tmp); | |
2208 __ br(Assembler::carrySet, false, Assembler::pn, *stub->entry()); | |
2209 __ delayed()->nop(); | |
2210 } | |
2211 | |
2212 if (flags & LIR_OpArrayCopy::dst_range_check) { | |
2213 __ ld(dst, arrayOopDesc::length_offset_in_bytes(), tmp2); | |
2214 __ add(length, dst_pos, tmp); | |
2215 __ cmp(tmp2, tmp); | |
2216 __ br(Assembler::carrySet, false, Assembler::pn, *stub->entry()); | |
2217 __ delayed()->nop(); | |
2218 } | |
2219 | |
2446 | 2220 int shift = shift_amount(basic_type); |
2221 | |
0 | 2222 if (flags & LIR_OpArrayCopy::type_check) { |
2446 | 2223 // We don't know the array types are compatible |
2224 if (basic_type != T_OBJECT) { | |
2225 // Simple test for basic type arrays | |
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2226 if (UseCompressedKlassPointers) { |
2446 | 2227 // We don't need decode because we just need to compare |
2228 __ lduw(src, oopDesc::klass_offset_in_bytes(), tmp); | |
2229 __ lduw(dst, oopDesc::klass_offset_in_bytes(), tmp2); | |
2230 __ cmp(tmp, tmp2); | |
2231 __ br(Assembler::notEqual, false, Assembler::pt, *stub->entry()); | |
2232 } else { | |
2233 __ ld_ptr(src, oopDesc::klass_offset_in_bytes(), tmp); | |
2234 __ ld_ptr(dst, oopDesc::klass_offset_in_bytes(), tmp2); | |
2235 __ cmp(tmp, tmp2); | |
2236 __ brx(Assembler::notEqual, false, Assembler::pt, *stub->entry()); | |
2237 } | |
2238 __ delayed()->nop(); | |
2002 | 2239 } else { |
2446 | 2240 // For object arrays, if src is a sub class of dst then we can |
2241 // safely do the copy. | |
2242 address copyfunc_addr = StubRoutines::checkcast_arraycopy(); | |
2243 | |
2244 Label cont, slow; | |
2245 assert_different_registers(tmp, tmp2, G3, G1); | |
2246 | |
2247 __ load_klass(src, G3); | |
2248 __ load_klass(dst, G1); | |
2249 | |
2250 __ check_klass_subtype_fast_path(G3, G1, tmp, tmp2, &cont, copyfunc_addr == NULL ? stub->entry() : &slow, NULL); | |
2251 | |
2252 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type); | |
2253 __ delayed()->nop(); | |
2254 | |
2255 __ cmp(G3, 0); | |
2256 if (copyfunc_addr != NULL) { // use stub if available | |
2257 // src is not a sub class of dst so we have to do a | |
2258 // per-element check. | |
2259 __ br(Assembler::notEqual, false, Assembler::pt, cont); | |
2260 __ delayed()->nop(); | |
2261 | |
2262 __ bind(slow); | |
2263 | |
2264 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray; | |
2265 if ((flags & mask) != mask) { | |
2266 // Check that at least both of them object arrays. | |
2267 assert(flags & mask, "one of the two should be known to be an object array"); | |
2268 | |
2269 if (!(flags & LIR_OpArrayCopy::src_objarray)) { | |
2270 __ load_klass(src, tmp); | |
2271 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) { | |
2272 __ load_klass(dst, tmp); | |
2273 } | |
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2274 int lh_offset = in_bytes(Klass::layout_helper_offset()); |
2446 | 2275 |
2276 __ lduw(tmp, lh_offset, tmp2); | |
2277 | |
2278 jint objArray_lh = Klass::array_layout_helper(T_OBJECT); | |
2279 __ set(objArray_lh, tmp); | |
2280 __ cmp(tmp, tmp2); | |
2281 __ br(Assembler::notEqual, false, Assembler::pt, *stub->entry()); | |
2282 __ delayed()->nop(); | |
2283 } | |
2284 | |
2285 Register src_ptr = O0; | |
2286 Register dst_ptr = O1; | |
2287 Register len = O2; | |
2288 Register chk_off = O3; | |
2289 Register super_k = O4; | |
2290 | |
2291 __ add(src, arrayOopDesc::base_offset_in_bytes(basic_type), src_ptr); | |
2292 if (shift == 0) { | |
2293 __ add(src_ptr, src_pos, src_ptr); | |
2294 } else { | |
2295 __ sll(src_pos, shift, tmp); | |
2296 __ add(src_ptr, tmp, src_ptr); | |
2297 } | |
2298 | |
2299 __ add(dst, arrayOopDesc::base_offset_in_bytes(basic_type), dst_ptr); | |
2300 if (shift == 0) { | |
2301 __ add(dst_ptr, dst_pos, dst_ptr); | |
2302 } else { | |
2303 __ sll(dst_pos, shift, tmp); | |
2304 __ add(dst_ptr, tmp, dst_ptr); | |
2305 } | |
2306 __ mov(length, len); | |
2307 __ load_klass(dst, tmp); | |
2308 | |
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2309 int ek_offset = in_bytes(objArrayKlass::element_klass_offset()); |
2446 | 2310 __ ld_ptr(tmp, ek_offset, super_k); |
2311 | |
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2312 int sco_offset = in_bytes(Klass::super_check_offset_offset()); |
2446 | 2313 __ lduw(super_k, sco_offset, chk_off); |
2314 | |
2315 __ call_VM_leaf(tmp, copyfunc_addr); | |
2316 | |
2317 #ifndef PRODUCT | |
2318 if (PrintC1Statistics) { | |
2319 Label failed; | |
3839 | 2320 __ br_notnull_short(O0, Assembler::pn, failed); |
2446 | 2321 __ inc_counter((address)&Runtime1::_arraycopy_checkcast_cnt, G1, G3); |
2322 __ bind(failed); | |
2323 } | |
2324 #endif | |
2325 | |
2326 __ br_null(O0, false, Assembler::pt, *stub->continuation()); | |
2327 __ delayed()->xor3(O0, -1, tmp); | |
2328 | |
2329 #ifndef PRODUCT | |
2330 if (PrintC1Statistics) { | |
2331 __ inc_counter((address)&Runtime1::_arraycopy_checkcast_attempt_cnt, G1, G3); | |
2332 } | |
2333 #endif | |
2334 | |
2335 __ sub(length, tmp, length); | |
2336 __ add(src_pos, tmp, src_pos); | |
2337 __ br(Assembler::always, false, Assembler::pt, *stub->entry()); | |
2338 __ delayed()->add(dst_pos, tmp, dst_pos); | |
2339 | |
2340 __ bind(cont); | |
2341 } else { | |
2342 __ br(Assembler::equal, false, Assembler::pn, *stub->entry()); | |
2343 __ delayed()->nop(); | |
2344 __ bind(cont); | |
2345 } | |
2002 | 2346 } |
0 | 2347 } |
2348 | |
2349 #ifdef ASSERT | |
2350 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) { | |
2351 // Sanity check the known type with the incoming class. For the | |
2352 // primitive case the types must match exactly with src.klass and | |
2353 // dst.klass each exactly matching the default type. For the | |
2354 // object array case, if no type check is needed then either the | |
2355 // dst type is exactly the expected type and the src type is a | |
2356 // subtype which we can't check or src is the same array as dst | |
2357 // but not necessarily exactly of type default_type. | |
2358 Label known_ok, halt; | |
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2359 metadata2reg(op->expected_type()->constant_encoding(), tmp); |
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2360 if (UseCompressedKlassPointers) { |
2002 | 2361 // tmp holds the default type. It currently comes uncompressed after the |
2362 // load of a constant, so encode it. | |
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2363 __ encode_klass_not_null(tmp); |
2002 | 2364 // load the raw value of the dst klass, since we will be comparing |
2365 // uncompressed values directly. | |
2366 __ lduw(dst, oopDesc::klass_offset_in_bytes(), tmp2); | |
2367 if (basic_type != T_OBJECT) { | |
2368 __ cmp(tmp, tmp2); | |
2369 __ br(Assembler::notEqual, false, Assembler::pn, halt); | |
2370 // load the raw value of the src klass. | |
2371 __ delayed()->lduw(src, oopDesc::klass_offset_in_bytes(), tmp2); | |
3839 | 2372 __ cmp_and_br_short(tmp, tmp2, Assembler::equal, Assembler::pn, known_ok); |
2002 | 2373 } else { |
2374 __ cmp(tmp, tmp2); | |
2375 __ br(Assembler::equal, false, Assembler::pn, known_ok); | |
2376 __ delayed()->cmp(src, dst); | |
2377 __ brx(Assembler::equal, false, Assembler::pn, known_ok); | |
2378 __ delayed()->nop(); | |
2379 } | |
0 | 2380 } else { |
2002 | 2381 __ ld_ptr(dst, oopDesc::klass_offset_in_bytes(), tmp2); |
2382 if (basic_type != T_OBJECT) { | |
2383 __ cmp(tmp, tmp2); | |
2384 __ brx(Assembler::notEqual, false, Assembler::pn, halt); | |
2385 __ delayed()->ld_ptr(src, oopDesc::klass_offset_in_bytes(), tmp2); | |
3839 | 2386 __ cmp_and_brx_short(tmp, tmp2, Assembler::equal, Assembler::pn, known_ok); |
2002 | 2387 } else { |
2388 __ cmp(tmp, tmp2); | |
2389 __ brx(Assembler::equal, false, Assembler::pn, known_ok); | |
2390 __ delayed()->cmp(src, dst); | |
2391 __ brx(Assembler::equal, false, Assembler::pn, known_ok); | |
2392 __ delayed()->nop(); | |
2393 } | |
0 | 2394 } |
2395 __ bind(halt); | |
2396 __ stop("incorrect type information in arraycopy"); | |
2397 __ bind(known_ok); | |
2398 } | |
2399 #endif | |
2400 | |
2446 | 2401 #ifndef PRODUCT |
2402 if (PrintC1Statistics) { | |
2403 address counter = Runtime1::arraycopy_count_address(basic_type); | |
2404 __ inc_counter(counter, G1, G3); | |
2405 } | |
2406 #endif | |
0 | 2407 |
2408 Register src_ptr = O0; | |
2409 Register dst_ptr = O1; | |
2410 Register len = O2; | |
2411 | |
2412 __ add(src, arrayOopDesc::base_offset_in_bytes(basic_type), src_ptr); | |
2413 if (shift == 0) { | |
2414 __ add(src_ptr, src_pos, src_ptr); | |
2415 } else { | |
2416 __ sll(src_pos, shift, tmp); | |
2417 __ add(src_ptr, tmp, src_ptr); | |
2418 } | |
2419 | |
2420 __ add(dst, arrayOopDesc::base_offset_in_bytes(basic_type), dst_ptr); | |
2421 if (shift == 0) { | |
2422 __ add(dst_ptr, dst_pos, dst_ptr); | |
2423 } else { | |
2424 __ sll(dst_pos, shift, tmp); | |
2425 __ add(dst_ptr, tmp, dst_ptr); | |
2426 } | |
2427 | |
2446 | 2428 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0; |
2429 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0; | |
2430 const char *name; | |
2431 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false); | |
2432 | |
2433 // arraycopy stubs takes a length in number of elements, so don't scale it. | |
2434 __ mov(length, len); | |
2435 __ call_VM_leaf(tmp, entry); | |
0 | 2436 |
2437 __ bind(*stub->continuation()); | |
2438 } | |
2439 | |
2440 | |
2441 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) { | |
2442 if (dest->is_single_cpu()) { | |
2443 #ifdef _LP64 | |
2444 if (left->type() == T_OBJECT) { | |
2445 switch (code) { | |
2446 case lir_shl: __ sllx (left->as_register(), count->as_register(), dest->as_register()); break; | |
2447 case lir_shr: __ srax (left->as_register(), count->as_register(), dest->as_register()); break; | |
2448 case lir_ushr: __ srl (left->as_register(), count->as_register(), dest->as_register()); break; | |
2449 default: ShouldNotReachHere(); | |
2450 } | |
2451 } else | |
2452 #endif | |
2453 switch (code) { | |
2454 case lir_shl: __ sll (left->as_register(), count->as_register(), dest->as_register()); break; | |
2455 case lir_shr: __ sra (left->as_register(), count->as_register(), dest->as_register()); break; | |
2456 case lir_ushr: __ srl (left->as_register(), count->as_register(), dest->as_register()); break; | |
2457 default: ShouldNotReachHere(); | |
2458 } | |
2459 } else { | |
2460 #ifdef _LP64 | |
2461 switch (code) { | |
2462 case lir_shl: __ sllx (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break; | |
2463 case lir_shr: __ srax (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break; | |
2464 case lir_ushr: __ srlx (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break; | |
2465 default: ShouldNotReachHere(); | |
2466 } | |
2467 #else | |
2468 switch (code) { | |
2469 case lir_shl: __ lshl (left->as_register_hi(), left->as_register_lo(), count->as_register(), dest->as_register_hi(), dest->as_register_lo(), G3_scratch); break; | |
2470 case lir_shr: __ lshr (left->as_register_hi(), left->as_register_lo(), count->as_register(), dest->as_register_hi(), dest->as_register_lo(), G3_scratch); break; | |
2471 case lir_ushr: __ lushr (left->as_register_hi(), left->as_register_lo(), count->as_register(), dest->as_register_hi(), dest->as_register_lo(), G3_scratch); break; | |
2472 default: ShouldNotReachHere(); | |
2473 } | |
2474 #endif | |
2475 } | |
2476 } | |
2477 | |
2478 | |
2479 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) { | |
2480 #ifdef _LP64 | |
2481 if (left->type() == T_OBJECT) { | |
2482 count = count & 63; // shouldn't shift by more than sizeof(intptr_t) | |
2483 Register l = left->as_register(); | |
2484 Register d = dest->as_register_lo(); | |
2485 switch (code) { | |
2486 case lir_shl: __ sllx (l, count, d); break; | |
2487 case lir_shr: __ srax (l, count, d); break; | |
2488 case lir_ushr: __ srlx (l, count, d); break; | |
2489 default: ShouldNotReachHere(); | |
2490 } | |
2491 return; | |
2492 } | |
2493 #endif | |
2494 | |
2495 if (dest->is_single_cpu()) { | |
2496 count = count & 0x1F; // Java spec | |
2497 switch (code) { | |
2498 case lir_shl: __ sll (left->as_register(), count, dest->as_register()); break; | |
2499 case lir_shr: __ sra (left->as_register(), count, dest->as_register()); break; | |
2500 case lir_ushr: __ srl (left->as_register(), count, dest->as_register()); break; | |
2501 default: ShouldNotReachHere(); | |
2502 } | |
2503 } else if (dest->is_double_cpu()) { | |
2504 count = count & 63; // Java spec | |
2505 switch (code) { | |
2506 case lir_shl: __ sllx (left->as_pointer_register(), count, dest->as_pointer_register()); break; | |
2507 case lir_shr: __ srax (left->as_pointer_register(), count, dest->as_pointer_register()); break; | |
2508 case lir_ushr: __ srlx (left->as_pointer_register(), count, dest->as_pointer_register()); break; | |
2509 default: ShouldNotReachHere(); | |
2510 } | |
2511 } else { | |
2512 ShouldNotReachHere(); | |
2513 } | |
2514 } | |
2515 | |
2516 | |
2517 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) { | |
2518 assert(op->tmp1()->as_register() == G1 && | |
2519 op->tmp2()->as_register() == G3 && | |
2520 op->tmp3()->as_register() == G4 && | |
2521 op->obj()->as_register() == O0 && | |
2522 op->klass()->as_register() == G5, "must be"); | |
2523 if (op->init_check()) { | |
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2524 __ ldub(op->klass()->as_register(), |
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2525 in_bytes(InstanceKlass::init_state_offset()), |
0 | 2526 op->tmp1()->as_register()); |
2527 add_debug_info_for_null_check_here(op->stub()->info()); | |
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2528 __ cmp(op->tmp1()->as_register(), InstanceKlass::fully_initialized); |
0 | 2529 __ br(Assembler::notEqual, false, Assembler::pn, *op->stub()->entry()); |
2530 __ delayed()->nop(); | |
2531 } | |
2532 __ allocate_object(op->obj()->as_register(), | |
2533 op->tmp1()->as_register(), | |
2534 op->tmp2()->as_register(), | |
2535 op->tmp3()->as_register(), | |
2536 op->header_size(), | |
2537 op->object_size(), | |
2538 op->klass()->as_register(), | |
2539 *op->stub()->entry()); | |
2540 __ bind(*op->stub()->continuation()); | |
2541 __ verify_oop(op->obj()->as_register()); | |
2542 } | |
2543 | |
2544 | |
2545 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) { | |
2546 assert(op->tmp1()->as_register() == G1 && | |
2547 op->tmp2()->as_register() == G3 && | |
2548 op->tmp3()->as_register() == G4 && | |
2549 op->tmp4()->as_register() == O1 && | |
2550 op->klass()->as_register() == G5, "must be"); | |
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2551 |
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2552 LP64_ONLY( __ signx(op->len()->as_register()); ) |
0 | 2553 if (UseSlowPath || |
2554 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) || | |
2555 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) { | |
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2556 __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry()); |
0 | 2557 __ delayed()->nop(); |
2558 } else { | |
2559 __ allocate_array(op->obj()->as_register(), | |
2560 op->len()->as_register(), | |
2561 op->tmp1()->as_register(), | |
2562 op->tmp2()->as_register(), | |
2563 op->tmp3()->as_register(), | |
2564 arrayOopDesc::header_size(op->type()), | |
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2565 type2aelembytes(op->type()), |
0 | 2566 op->klass()->as_register(), |
2567 *op->stub()->entry()); | |
2568 } | |
2569 __ bind(*op->stub()->continuation()); | |
2570 } | |
2571 | |
2572 | |
1783 | 2573 void LIR_Assembler::type_profile_helper(Register mdo, int mdo_offset_bias, |
2574 ciMethodData *md, ciProfileData *data, | |
2575 Register recv, Register tmp1, Label* update_done) { | |
2576 uint i; | |
2577 for (i = 0; i < VirtualCallData::row_limit(); i++) { | |
2578 Label next_test; | |
2579 // See if the receiver is receiver[n]. | |
2580 Address receiver_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) - | |
2581 mdo_offset_bias); | |
2582 __ ld_ptr(receiver_addr, tmp1); | |
2583 __ verify_oop(tmp1); | |
3839 | 2584 __ cmp_and_brx_short(recv, tmp1, Assembler::notEqual, Assembler::pt, next_test); |
1783 | 2585 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) - |
2586 mdo_offset_bias); | |
2587 __ ld_ptr(data_addr, tmp1); | |
2588 __ add(tmp1, DataLayout::counter_increment, tmp1); | |
2589 __ st_ptr(tmp1, data_addr); | |
3839 | 2590 __ ba(*update_done); |
1783 | 2591 __ delayed()->nop(); |
2592 __ bind(next_test); | |
2593 } | |
2594 | |
2595 // Didn't find receiver; find next empty slot and fill it in | |
2596 for (i = 0; i < VirtualCallData::row_limit(); i++) { | |
2597 Label next_test; | |
2598 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) - | |
2599 mdo_offset_bias); | |
2002 | 2600 __ ld_ptr(recv_addr, tmp1); |
3839 | 2601 __ br_notnull_short(tmp1, Assembler::pt, next_test); |
1783 | 2602 __ st_ptr(recv, recv_addr); |
2603 __ set(DataLayout::counter_increment, tmp1); | |
2604 __ st_ptr(tmp1, mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) - | |
2605 mdo_offset_bias); | |
3839 | 2606 __ ba(*update_done); |
1783 | 2607 __ delayed()->nop(); |
2608 __ bind(next_test); | |
2609 } | |
2610 } | |
2611 | |
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2612 |
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2613 void LIR_Assembler::setup_md_access(ciMethod* method, int bci, |
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2614 ciMethodData*& md, ciProfileData*& data, int& mdo_offset_bias) { |
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2615 md = method->method_data_or_null(); |
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2616 assert(md != NULL, "Sanity"); |
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2617 data = md->bci_to_data(bci); |
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2618 assert(data != NULL, "need data for checkcast"); |
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2619 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check"); |
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2620 if (!Assembler::is_simm13(md->byte_offset_of_slot(data, DataLayout::header_offset()) + data->size_in_bytes())) { |
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2621 // The offset is large so bias the mdo by the base of the slot so |
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2622 // that the ld can use simm13s to reference the slots of the data |
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2623 mdo_offset_bias = md->byte_offset_of_slot(data, DataLayout::header_offset()); |
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2624 } |
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2625 } |
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2626 |
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2627 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) { |
1783 | 2628 // we always need a stub for the failure case. |
2629 CodeStub* stub = op->stub(); | |
2630 Register obj = op->object()->as_register(); | |
2631 Register k_RInfo = op->tmp1()->as_register(); | |
2632 Register klass_RInfo = op->tmp2()->as_register(); | |
2633 Register dst = op->result_opr()->as_register(); | |
2634 Register Rtmp1 = op->tmp3()->as_register(); | |
2635 ciKlass* k = op->klass(); | |
2636 | |
2637 | |
2638 if (obj == k_RInfo) { | |
2639 k_RInfo = klass_RInfo; | |
2640 klass_RInfo = obj; | |
2641 } | |
2642 | |
2643 ciMethodData* md; | |
2644 ciProfileData* data; | |
2645 int mdo_offset_bias = 0; | |
2646 if (op->should_profile()) { | |
2647 ciMethod* method = op->profiled_method(); | |
2648 assert(method != NULL, "Should have method"); | |
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2649 setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias); |
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2650 |
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2651 Label not_null; |
3839 | 2652 __ br_notnull_short(obj, Assembler::pn, not_null); |
1783 | 2653 Register mdo = k_RInfo; |
2654 Register data_val = Rtmp1; | |
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2655 metadata2reg(md->constant_encoding(), mdo); |
1783 | 2656 if (mdo_offset_bias > 0) { |
2657 __ set(mdo_offset_bias, data_val); | |
2658 __ add(mdo, data_val, mdo); | |
2659 } | |
2660 Address flags_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias); | |
2661 __ ldub(flags_addr, data_val); | |
2662 __ or3(data_val, BitData::null_seen_byte_constant(), data_val); | |
2663 __ stb(data_val, flags_addr); | |
3839 | 2664 __ ba(*obj_is_null); |
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2665 __ delayed()->nop(); |
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2666 __ bind(not_null); |
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2667 } else { |
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2668 __ br_null(obj, false, Assembler::pn, *obj_is_null); |
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2669 __ delayed()->nop(); |
1783 | 2670 } |
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2671 |
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2672 Label profile_cast_failure, profile_cast_success; |
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2673 Label *failure_target = op->should_profile() ? &profile_cast_failure : failure; |
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2674 Label *success_target = op->should_profile() ? &profile_cast_success : success; |
1783 | 2675 |
2676 // patching may screw with our temporaries on sparc, | |
2677 // so let's do it before loading the class | |
2678 if (k->is_loaded()) { | |
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2679 metadata2reg(k->constant_encoding(), k_RInfo); |
1783 | 2680 } else { |
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2681 klass2reg_with_patching(k_RInfo, op->info_for_patch()); |
1783 | 2682 } |
2683 assert(obj != k_RInfo, "must be different"); | |
2684 | |
2685 // get object class | |
2686 // not a safepoint as obj null check happens earlier | |
2002 | 2687 __ load_klass(obj, klass_RInfo); |
1783 | 2688 if (op->fast_check()) { |
2689 assert_different_registers(klass_RInfo, k_RInfo); | |
2690 __ cmp(k_RInfo, klass_RInfo); | |
2691 __ brx(Assembler::notEqual, false, Assembler::pt, *failure_target); | |
2692 __ delayed()->nop(); | |
2693 } else { | |
2694 bool need_slow_path = true; | |
2695 if (k->is_loaded()) { | |
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2696 if ((int) k->super_check_offset() != in_bytes(Klass::secondary_super_cache_offset())) |
1783 | 2697 need_slow_path = false; |
2698 // perform the fast part of the checking logic | |
2699 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, noreg, | |
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2700 (need_slow_path ? success_target : NULL), |
1783 | 2701 failure_target, NULL, |
2702 RegisterOrConstant(k->super_check_offset())); | |
2703 } else { | |
2704 // perform the fast part of the checking logic | |
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2705 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, O7, success_target, |
1783 | 2706 failure_target, NULL); |
2707 } | |
2708 if (need_slow_path) { | |
2709 // call out-of-line instance of __ check_klass_subtype_slow_path(...): | |
2710 assert(klass_RInfo == G3 && k_RInfo == G1, "incorrect call setup"); | |
2711 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type); | |
2712 __ delayed()->nop(); | |
2713 __ cmp(G3, 0); | |
2714 __ br(Assembler::equal, false, Assembler::pn, *failure_target); | |
2715 __ delayed()->nop(); | |
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2716 // Fall through to success case |
1783 | 2717 } |
2718 } | |
2719 | |
2720 if (op->should_profile()) { | |
2721 Register mdo = klass_RInfo, recv = k_RInfo, tmp1 = Rtmp1; | |
2722 assert_different_registers(obj, mdo, recv, tmp1); | |
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2723 __ bind(profile_cast_success); |
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2724 metadata2reg(md->constant_encoding(), mdo); |
1783 | 2725 if (mdo_offset_bias > 0) { |
2726 __ set(mdo_offset_bias, tmp1); | |
2727 __ add(mdo, tmp1, mdo); | |
2728 } | |
2002 | 2729 __ load_klass(obj, recv); |
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2730 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, success); |
1783 | 2731 // Jump over the failure case |
3839 | 2732 __ ba(*success); |
1783 | 2733 __ delayed()->nop(); |
2734 // Cast failure case | |
2735 __ bind(profile_cast_failure); | |
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2736 metadata2reg(md->constant_encoding(), mdo); |
1783 | 2737 if (mdo_offset_bias > 0) { |
2738 __ set(mdo_offset_bias, tmp1); | |
2739 __ add(mdo, tmp1, mdo); | |
2740 } | |
2741 Address data_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias); | |
2742 __ ld_ptr(data_addr, tmp1); | |
2743 __ sub(tmp1, DataLayout::counter_increment, tmp1); | |
2744 __ st_ptr(tmp1, data_addr); | |
3839 | 2745 __ ba(*failure); |
1783 | 2746 __ delayed()->nop(); |
2747 } | |
3839 | 2748 __ ba(*success); |
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2749 __ delayed()->nop(); |
1783 | 2750 } |
2751 | |
0 | 2752 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) { |
2753 LIR_Code code = op->code(); | |
2754 if (code == lir_store_check) { | |
2755 Register value = op->object()->as_register(); | |
2756 Register array = op->array()->as_register(); | |
2757 Register k_RInfo = op->tmp1()->as_register(); | |
2758 Register klass_RInfo = op->tmp2()->as_register(); | |
2759 Register Rtmp1 = op->tmp3()->as_register(); | |
2760 | |
2761 __ verify_oop(value); | |
2762 CodeStub* stub = op->stub(); | |
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2763 // check if it needs to be profiled |
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2764 ciMethodData* md; |
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2765 ciProfileData* data; |
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2766 int mdo_offset_bias = 0; |
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2767 if (op->should_profile()) { |
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2768 ciMethod* method = op->profiled_method(); |
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2769 assert(method != NULL, "Should have method"); |
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2770 setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias); |
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2771 } |
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2772 Label profile_cast_success, profile_cast_failure, done; |
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2773 Label *success_target = op->should_profile() ? &profile_cast_success : &done; |
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2774 Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry(); |
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2775 |
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2776 if (op->should_profile()) { |
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2777 Label not_null; |
3839 | 2778 __ br_notnull_short(value, Assembler::pn, not_null); |
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2779 Register mdo = k_RInfo; |
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2780 Register data_val = Rtmp1; |
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2781 metadata2reg(md->constant_encoding(), mdo); |
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2782 if (mdo_offset_bias > 0) { |
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2783 __ set(mdo_offset_bias, data_val); |
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2784 __ add(mdo, data_val, mdo); |
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2785 } |
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2786 Address flags_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias); |
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2787 __ ldub(flags_addr, data_val); |
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2788 __ or3(data_val, BitData::null_seen_byte_constant(), data_val); |
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2789 __ stb(data_val, flags_addr); |
3839 | 2790 __ ba_short(done); |
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2791 __ bind(not_null); |
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2792 } else { |
3839 | 2793 __ br_null_short(value, Assembler::pn, done); |
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2794 } |
2002 | 2795 add_debug_info_for_null_check_here(op->info_for_exception()); |
2796 __ load_klass(array, k_RInfo); | |
2797 __ load_klass(value, klass_RInfo); | |
0 | 2798 |
2799 // get instance klass | |
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2800 __ ld_ptr(Address(k_RInfo, objArrayKlass::element_klass_offset()), k_RInfo); |
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2801 // perform the fast part of the checking logic |
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2802 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, O7, success_target, failure_target, NULL); |
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2803 |
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2804 // call out-of-line instance of __ check_klass_subtype_slow_path(...): |
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2805 assert(klass_RInfo == G3 && k_RInfo == G1, "incorrect call setup"); |
0 | 2806 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type); |
2807 __ delayed()->nop(); | |
2808 __ cmp(G3, 0); | |
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2809 __ br(Assembler::equal, false, Assembler::pn, *failure_target); |
0 | 2810 __ delayed()->nop(); |
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2811 // fall through to the success case |
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2812 |
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2813 if (op->should_profile()) { |
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2814 Register mdo = klass_RInfo, recv = k_RInfo, tmp1 = Rtmp1; |
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2815 assert_different_registers(value, mdo, recv, tmp1); |
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2816 __ bind(profile_cast_success); |
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2817 metadata2reg(md->constant_encoding(), mdo); |
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2818 if (mdo_offset_bias > 0) { |
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2819 __ set(mdo_offset_bias, tmp1); |
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2820 __ add(mdo, tmp1, mdo); |
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2821 } |
2002 | 2822 __ load_klass(value, recv); |
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2823 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &done); |
3839 | 2824 __ ba_short(done); |
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2825 // Cast failure case |
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2826 __ bind(profile_cast_failure); |
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2827 metadata2reg(md->constant_encoding(), mdo); |
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2828 if (mdo_offset_bias > 0) { |
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2829 __ set(mdo_offset_bias, tmp1); |
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2830 __ add(mdo, tmp1, mdo); |
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2831 } |
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2832 Address data_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias); |
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2833 __ ld_ptr(data_addr, tmp1); |
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2834 __ sub(tmp1, DataLayout::counter_increment, tmp1); |
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2835 __ st_ptr(tmp1, data_addr); |
3839 | 2836 __ ba(*stub->entry()); |
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2837 __ delayed()->nop(); |
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2838 } |
0 | 2839 __ bind(done); |
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2840 } else if (code == lir_checkcast) { |
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2841 Register obj = op->object()->as_register(); |
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2842 Register dst = op->result_opr()->as_register(); |
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2843 Label success; |
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2844 emit_typecheck_helper(op, &success, op->stub()->entry(), &success); |
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2845 __ bind(success); |
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2846 __ mov(obj, dst); |
0 | 2847 } else if (code == lir_instanceof) { |
2848 Register obj = op->object()->as_register(); | |
2849 Register dst = op->result_opr()->as_register(); | |
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2850 Label success, failure, done; |
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2851 emit_typecheck_helper(op, &success, &failure, &failure); |
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2852 __ bind(failure); |
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2853 __ set(0, dst); |
3839 | 2854 __ ba_short(done); |
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2855 __ bind(success); |
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2856 __ set(1, dst); |
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2857 __ bind(done); |
0 | 2858 } else { |
2859 ShouldNotReachHere(); | |
2860 } | |
2861 | |
2862 } | |
2863 | |
2864 | |
2865 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) { | |
2866 if (op->code() == lir_cas_long) { | |
2867 assert(VM_Version::supports_cx8(), "wrong machine"); | |
2868 Register addr = op->addr()->as_pointer_register(); | |
2869 Register cmp_value_lo = op->cmp_value()->as_register_lo(); | |
2870 Register cmp_value_hi = op->cmp_value()->as_register_hi(); | |
2871 Register new_value_lo = op->new_value()->as_register_lo(); | |
2872 Register new_value_hi = op->new_value()->as_register_hi(); | |
2873 Register t1 = op->tmp1()->as_register(); | |
2874 Register t2 = op->tmp2()->as_register(); | |
2875 #ifdef _LP64 | |
2876 __ mov(cmp_value_lo, t1); | |
2877 __ mov(new_value_lo, t2); | |
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2878 // perform the compare and swap operation |
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2879 __ casx(addr, t1, t2); |
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2880 // generate condition code - if the swap succeeded, t2 ("new value" reg) was |
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2881 // overwritten with the original value in "addr" and will be equal to t1. |
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2882 __ cmp(t1, t2); |
0 | 2883 #else |
2884 // move high and low halves of long values into single registers | |
2885 __ sllx(cmp_value_hi, 32, t1); // shift high half into temp reg | |
2886 __ srl(cmp_value_lo, 0, cmp_value_lo); // clear upper 32 bits of low half | |
2887 __ or3(t1, cmp_value_lo, t1); // t1 holds 64-bit compare value | |
2888 __ sllx(new_value_hi, 32, t2); | |
2889 __ srl(new_value_lo, 0, new_value_lo); | |
2890 __ or3(t2, new_value_lo, t2); // t2 holds 64-bit value to swap | |
2891 // perform the compare and swap operation | |
2892 __ casx(addr, t1, t2); | |
2893 // generate condition code - if the swap succeeded, t2 ("new value" reg) was | |
2894 // overwritten with the original value in "addr" and will be equal to t1. | |
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2895 // Produce icc flag for 32bit. |
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|
2896 __ sub(t1, t2, t2); |
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|
2897 __ srlx(t2, 32, t1); |
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2898 __ orcc(t2, t1, G0); |
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2899 #endif |
0 | 2900 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj) { |
2901 Register addr = op->addr()->as_pointer_register(); | |
2902 Register cmp_value = op->cmp_value()->as_register(); | |
2903 Register new_value = op->new_value()->as_register(); | |
2904 Register t1 = op->tmp1()->as_register(); | |
2905 Register t2 = op->tmp2()->as_register(); | |
2906 __ mov(cmp_value, t1); | |
2907 __ mov(new_value, t2); | |
2908 if (op->code() == lir_cas_obj) { | |
2002 | 2909 if (UseCompressedOops) { |
2910 __ encode_heap_oop(t1); | |
2911 __ encode_heap_oop(t2); | |
0 | 2912 __ cas(addr, t1, t2); |
2002 | 2913 } else { |
2010 | 2914 __ cas_ptr(addr, t1, t2); |
0 | 2915 } |
2002 | 2916 } else { |
2917 __ cas(addr, t1, t2); | |
2918 } | |
0 | 2919 __ cmp(t1, t2); |
2920 } else { | |
2921 Unimplemented(); | |
2922 } | |
2923 } | |
2924 | |
2925 void LIR_Assembler::set_24bit_FPU() { | |
2926 Unimplemented(); | |
2927 } | |
2928 | |
2929 | |
2930 void LIR_Assembler::reset_FPU() { | |
2931 Unimplemented(); | |
2932 } | |
2933 | |
2934 | |
2935 void LIR_Assembler::breakpoint() { | |
2936 __ breakpoint_trap(); | |
2937 } | |
2938 | |
2939 | |
2940 void LIR_Assembler::push(LIR_Opr opr) { | |
2941 Unimplemented(); | |
2942 } | |
2943 | |
2944 | |
2945 void LIR_Assembler::pop(LIR_Opr opr) { | |
2946 Unimplemented(); | |
2947 } | |
2948 | |
2949 | |
2950 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst_opr) { | |
2951 Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no); | |
2952 Register dst = dst_opr->as_register(); | |
2953 Register reg = mon_addr.base(); | |
2954 int offset = mon_addr.disp(); | |
2955 // compute pointer to BasicLock | |
2956 if (mon_addr.is_simm13()) { | |
2957 __ add(reg, offset, dst); | |
2958 } else { | |
2959 __ set(offset, dst); | |
2960 __ add(dst, reg, dst); | |
2961 } | |
2962 } | |
2963 | |
2964 | |
2965 void LIR_Assembler::emit_lock(LIR_OpLock* op) { | |
2966 Register obj = op->obj_opr()->as_register(); | |
2967 Register hdr = op->hdr_opr()->as_register(); | |
2968 Register lock = op->lock_opr()->as_register(); | |
2969 | |
2970 // obj may not be an oop | |
2971 if (op->code() == lir_lock) { | |
2972 MonitorEnterStub* stub = (MonitorEnterStub*)op->stub(); | |
2973 if (UseFastLocking) { | |
2974 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); | |
2975 // add debug info for NullPointerException only if one is possible | |
2976 if (op->info() != NULL) { | |
2977 add_debug_info_for_null_check_here(op->info()); | |
2978 } | |
2979 __ lock_object(hdr, obj, lock, op->scratch_opr()->as_register(), *op->stub()->entry()); | |
2980 } else { | |
2981 // always do slow locking | |
2982 // note: the slow locking code could be inlined here, however if we use | |
2983 // slow locking, speed doesn't matter anyway and this solution is | |
2984 // simpler and requires less duplicated code - additionally, the | |
2985 // slow locking code is the same in either case which simplifies | |
2986 // debugging | |
2987 __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry()); | |
2988 __ delayed()->nop(); | |
2989 } | |
2990 } else { | |
2991 assert (op->code() == lir_unlock, "Invalid code, expected lir_unlock"); | |
2992 if (UseFastLocking) { | |
2993 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); | |
2994 __ unlock_object(hdr, obj, lock, *op->stub()->entry()); | |
2995 } else { | |
2996 // always do slow unlocking | |
2997 // note: the slow unlocking code could be inlined here, however if we use | |
2998 // slow unlocking, speed doesn't matter anyway and this solution is | |
2999 // simpler and requires less duplicated code - additionally, the | |
3000 // slow unlocking code is the same in either case which simplifies | |
3001 // debugging | |
3002 __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry()); | |
3003 __ delayed()->nop(); | |
3004 } | |
3005 } | |
3006 __ bind(*op->stub()->continuation()); | |
3007 } | |
3008 | |
3009 | |
3010 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) { | |
3011 ciMethod* method = op->profiled_method(); | |
3012 int bci = op->profiled_bci(); | |
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3013 ciMethod* callee = op->profiled_callee(); |
0 | 3014 |
3015 // Update counter for all call types | |
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3016 ciMethodData* md = method->method_data_or_null(); |
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3017 assert(md != NULL, "Sanity"); |
0 | 3018 ciProfileData* data = md->bci_to_data(bci); |
3019 assert(data->is_CounterData(), "need CounterData for calls"); | |
3020 assert(op->mdo()->is_single_cpu(), "mdo must be allocated"); | |
1783 | 3021 Register mdo = op->mdo()->as_register(); |
3022 #ifdef _LP64 | |
3023 assert(op->tmp1()->is_double_cpu(), "tmp1 must be allocated"); | |
3024 Register tmp1 = op->tmp1()->as_register_lo(); | |
3025 #else | |
0 | 3026 assert(op->tmp1()->is_single_cpu(), "tmp1 must be allocated"); |
3027 Register tmp1 = op->tmp1()->as_register(); | |
1783 | 3028 #endif |
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3029 metadata2reg(md->constant_encoding(), mdo); |
0 | 3030 int mdo_offset_bias = 0; |
3031 if (!Assembler::is_simm13(md->byte_offset_of_slot(data, CounterData::count_offset()) + | |
3032 data->size_in_bytes())) { | |
3033 // The offset is large so bias the mdo by the base of the slot so | |
3034 // that the ld can use simm13s to reference the slots of the data | |
3035 mdo_offset_bias = md->byte_offset_of_slot(data, CounterData::count_offset()); | |
3036 __ set(mdo_offset_bias, O7); | |
3037 __ add(mdo, O7, mdo); | |
3038 } | |
3039 | |
727 | 3040 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias); |
0 | 3041 Bytecodes::Code bc = method->java_code_at_bci(bci); |
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3042 const bool callee_is_static = callee->is_loaded() && callee->is_static(); |
0 | 3043 // Perform additional virtual call profiling for invokevirtual and |
3044 // invokeinterface bytecodes | |
3045 if ((bc == Bytecodes::_invokevirtual || bc == Bytecodes::_invokeinterface) && | |
6266
1d7922586cf6
7023639: JSR 292 method handle invocation needs a fast path for compiled code
twisti
parents:
6057
diff
changeset
|
3046 !callee_is_static && // required for optimized MH invokes |
1783 | 3047 C1ProfileVirtualCalls) { |
0 | 3048 assert(op->recv()->is_single_cpu(), "recv must be allocated"); |
3049 Register recv = op->recv()->as_register(); | |
3050 assert_different_registers(mdo, tmp1, recv); | |
3051 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls"); | |
3052 ciKlass* known_klass = op->known_holder(); | |
1783 | 3053 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) { |
0 | 3054 // We know the type that will be seen at this call site; we can |
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da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
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diff
changeset
|
3055 // statically update the MethodData* rather than needing to do |
0 | 3056 // dynamic tests on the receiver type |
3057 | |
3058 // NOTE: we should probably put a lock around this search to | |
3059 // avoid collisions by concurrent compilations | |
3060 ciVirtualCallData* vc_data = (ciVirtualCallData*) data; | |
3061 uint i; | |
3062 for (i = 0; i < VirtualCallData::row_limit(); i++) { | |
3063 ciKlass* receiver = vc_data->receiver(i); | |
3064 if (known_klass->equals(receiver)) { | |
727 | 3065 Address data_addr(mdo, md->byte_offset_of_slot(data, |
3066 VirtualCallData::receiver_count_offset(i)) - | |
0 | 3067 mdo_offset_bias); |
1783 | 3068 __ ld_ptr(data_addr, tmp1); |
0 | 3069 __ add(tmp1, DataLayout::counter_increment, tmp1); |
1783 | 3070 __ st_ptr(tmp1, data_addr); |
0 | 3071 return; |
3072 } | |
3073 } | |
3074 | |
3075 // Receiver type not found in profile data; select an empty slot | |
3076 | |
3077 // Note that this is less efficient than it should be because it | |
3078 // always does a write to the receiver part of the | |
3079 // VirtualCallData rather than just the first time | |
3080 for (i = 0; i < VirtualCallData::row_limit(); i++) { | |
3081 ciKlass* receiver = vc_data->receiver(i); | |
3082 if (receiver == NULL) { | |
727 | 3083 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) - |
0 | 3084 mdo_offset_bias); |
6725
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|
3085 metadata2reg(known_klass->constant_encoding(), tmp1); |
0 | 3086 __ st_ptr(tmp1, recv_addr); |
727 | 3087 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - |
0 | 3088 mdo_offset_bias); |
1783 | 3089 __ ld_ptr(data_addr, tmp1); |
0 | 3090 __ add(tmp1, DataLayout::counter_increment, tmp1); |
1783 | 3091 __ st_ptr(tmp1, data_addr); |
0 | 3092 return; |
3093 } | |
3094 } | |
3095 } else { | |
2002 | 3096 __ load_klass(recv, recv); |
0 | 3097 Label update_done; |
1783 | 3098 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &update_done); |
1251
576e77447e3c
6923002: assert(false,"this call site should not be polymorphic")
kvn
parents:
1204
diff
changeset
|
3099 // Receiver did not match any saved receiver and there is no empty row for it. |
576e77447e3c
6923002: assert(false,"this call site should not be polymorphic")
kvn
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1204
diff
changeset
|
3100 // Increment total counter to indicate polymorphic case. |
1783 | 3101 __ ld_ptr(counter_addr, tmp1); |
1251
576e77447e3c
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1204
diff
changeset
|
3102 __ add(tmp1, DataLayout::counter_increment, tmp1); |
1783 | 3103 __ st_ptr(tmp1, counter_addr); |
0 | 3104 |
3105 __ bind(update_done); | |
3106 } | |
1251
576e77447e3c
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1204
diff
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|
3107 } else { |
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diff
changeset
|
3108 // Static call |
1783 | 3109 __ ld_ptr(counter_addr, tmp1); |
1251
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diff
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|
3110 __ add(tmp1, DataLayout::counter_increment, tmp1); |
1783 | 3111 __ st_ptr(tmp1, counter_addr); |
0 | 3112 } |
3113 } | |
3114 | |
3115 void LIR_Assembler::align_backward_branch_target() { | |
1365 | 3116 __ align(OptoLoopAlignment); |
0 | 3117 } |
3118 | |
3119 | |
3120 void LIR_Assembler::emit_delay(LIR_OpDelay* op) { | |
3121 // make sure we are expecting a delay | |
3122 // this has the side effect of clearing the delay state | |
3123 // so we can use _masm instead of _masm->delayed() to do the | |
3124 // code generation. | |
3125 __ delayed(); | |
3126 | |
3127 // make sure we only emit one instruction | |
3128 int offset = code_offset(); | |
3129 op->delay_op()->emit_code(this); | |
3130 #ifdef ASSERT | |
3131 if (code_offset() - offset != NativeInstruction::nop_instruction_size) { | |
3132 op->delay_op()->print(); | |
3133 } | |
3134 assert(code_offset() - offset == NativeInstruction::nop_instruction_size, | |
3135 "only one instruction can go in a delay slot"); | |
3136 #endif | |
3137 | |
3138 // we may also be emitting the call info for the instruction | |
3139 // which we are the delay slot of. | |
1564 | 3140 CodeEmitInfo* call_info = op->call_info(); |
0 | 3141 if (call_info) { |
3142 add_call_info(code_offset(), call_info); | |
3143 } | |
3144 | |
3145 if (VerifyStackAtCalls) { | |
3146 _masm->sub(FP, SP, O7); | |
3147 _masm->cmp(O7, initial_frame_size_in_bytes()); | |
3148 _masm->trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2 ); | |
3149 } | |
3150 } | |
3151 | |
3152 | |
3153 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) { | |
3154 assert(left->is_register(), "can only handle registers"); | |
3155 | |
3156 if (left->is_single_cpu()) { | |
3157 __ neg(left->as_register(), dest->as_register()); | |
3158 } else if (left->is_single_fpu()) { | |
3159 __ fneg(FloatRegisterImpl::S, left->as_float_reg(), dest->as_float_reg()); | |
3160 } else if (left->is_double_fpu()) { | |
3161 __ fneg(FloatRegisterImpl::D, left->as_double_reg(), dest->as_double_reg()); | |
3162 } else { | |
3163 assert (left->is_double_cpu(), "Must be a long"); | |
3164 Register Rlow = left->as_register_lo(); | |
3165 Register Rhi = left->as_register_hi(); | |
3166 #ifdef _LP64 | |
3167 __ sub(G0, Rlow, dest->as_register_lo()); | |
3168 #else | |
3169 __ subcc(G0, Rlow, dest->as_register_lo()); | |
3170 __ subc (G0, Rhi, dest->as_register_hi()); | |
3171 #endif | |
3172 } | |
3173 } | |
3174 | |
3175 | |
3176 void LIR_Assembler::fxch(int i) { | |
3177 Unimplemented(); | |
3178 } | |
3179 | |
3180 void LIR_Assembler::fld(int i) { | |
3181 Unimplemented(); | |
3182 } | |
3183 | |
3184 void LIR_Assembler::ffree(int i) { | |
3185 Unimplemented(); | |
3186 } | |
3187 | |
3188 void LIR_Assembler::rt_call(LIR_Opr result, address dest, | |
3189 const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) { | |
3190 | |
3191 // if tmp is invalid, then the function being called doesn't destroy the thread | |
3192 if (tmp->is_valid()) { | |
3193 __ save_thread(tmp->as_register()); | |
3194 } | |
3195 __ call(dest, relocInfo::runtime_call_type); | |
3196 __ delayed()->nop(); | |
3197 if (info != NULL) { | |
3198 add_call_info_here(info); | |
3199 } | |
3200 if (tmp->is_valid()) { | |
3201 __ restore_thread(tmp->as_register()); | |
3202 } | |
3203 | |
3204 #ifdef ASSERT | |
3205 __ verify_thread(); | |
3206 #endif // ASSERT | |
3207 } | |
3208 | |
3209 | |
3210 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) { | |
3211 #ifdef _LP64 | |
3212 ShouldNotReachHere(); | |
3213 #endif | |
3214 | |
3215 NEEDS_CLEANUP; | |
3216 if (type == T_LONG) { | |
3217 LIR_Address* mem_addr = dest->is_address() ? dest->as_address_ptr() : src->as_address_ptr(); | |
3218 | |
3219 // (extended to allow indexed as well as constant displaced for JSR-166) | |
3220 Register idx = noreg; // contains either constant offset or index | |
3221 | |
3222 int disp = mem_addr->disp(); | |
3223 if (mem_addr->index() == LIR_OprFact::illegalOpr) { | |
3224 if (!Assembler::is_simm13(disp)) { | |
3225 idx = O7; | |
3226 __ set(disp, idx); | |
3227 } | |
3228 } else { | |
3229 assert(disp == 0, "not both indexed and disp"); | |
3230 idx = mem_addr->index()->as_register(); | |
3231 } | |
3232 | |
3233 int null_check_offset = -1; | |
3234 | |
3235 Register base = mem_addr->base()->as_register(); | |
3236 if (src->is_register() && dest->is_address()) { | |
3237 // G4 is high half, G5 is low half | |
3238 if (VM_Version::v9_instructions_work()) { | |
3239 // clear the top bits of G5, and scale up G4 | |
3240 __ srl (src->as_register_lo(), 0, G5); | |
3241 __ sllx(src->as_register_hi(), 32, G4); | |
3242 // combine the two halves into the 64 bits of G4 | |
3243 __ or3(G4, G5, G4); | |
3244 null_check_offset = __ offset(); | |
3245 if (idx == noreg) { | |
3246 __ stx(G4, base, disp); | |
3247 } else { | |
3248 __ stx(G4, base, idx); | |
3249 } | |
3250 } else { | |
3251 __ mov (src->as_register_hi(), G4); | |
3252 __ mov (src->as_register_lo(), G5); | |
3253 null_check_offset = __ offset(); | |
3254 if (idx == noreg) { | |
3255 __ std(G4, base, disp); | |
3256 } else { | |
3257 __ std(G4, base, idx); | |
3258 } | |
3259 } | |
3260 } else if (src->is_address() && dest->is_register()) { | |
3261 null_check_offset = __ offset(); | |
3262 if (VM_Version::v9_instructions_work()) { | |
3263 if (idx == noreg) { | |
3264 __ ldx(base, disp, G5); | |
3265 } else { | |
3266 __ ldx(base, idx, G5); | |
3267 } | |
3268 __ srax(G5, 32, dest->as_register_hi()); // fetch the high half into hi | |
3269 __ mov (G5, dest->as_register_lo()); // copy low half into lo | |
3270 } else { | |
3271 if (idx == noreg) { | |
3272 __ ldd(base, disp, G4); | |
3273 } else { | |
3274 __ ldd(base, idx, G4); | |
3275 } | |
3276 // G4 is high half, G5 is low half | |
3277 __ mov (G4, dest->as_register_hi()); | |
3278 __ mov (G5, dest->as_register_lo()); | |
3279 } | |
3280 } else { | |
3281 Unimplemented(); | |
3282 } | |
3283 if (info != NULL) { | |
3284 add_debug_info_for_null_check(null_check_offset, info); | |
3285 } | |
3286 | |
3287 } else { | |
3288 // use normal move for all other volatiles since they don't need | |
3289 // special handling to remain atomic. | |
2002 | 3290 move_op(src, dest, type, lir_patch_none, info, false, false, false); |
0 | 3291 } |
3292 } | |
3293 | |
3294 void LIR_Assembler::membar() { | |
3295 // only StoreLoad membars are ever explicitly needed on sparcs in TSO mode | |
3296 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) ); | |
3297 } | |
3298 | |
3299 void LIR_Assembler::membar_acquire() { | |
3300 // no-op on TSO | |
3301 } | |
3302 | |
3303 void LIR_Assembler::membar_release() { | |
3304 // no-op on TSO | |
3305 } | |
3306 | |
4966
701a83c86f28
7120481: storeStore barrier in constructor with final field
jiangli
parents:
4808
diff
changeset
|
3307 void LIR_Assembler::membar_loadload() { |
701a83c86f28
7120481: storeStore barrier in constructor with final field
jiangli
parents:
4808
diff
changeset
|
3308 // no-op |
701a83c86f28
7120481: storeStore barrier in constructor with final field
jiangli
parents:
4808
diff
changeset
|
3309 //__ membar(Assembler::Membar_mask_bits(Assembler::loadload)); |
701a83c86f28
7120481: storeStore barrier in constructor with final field
jiangli
parents:
4808
diff
changeset
|
3310 } |
701a83c86f28
7120481: storeStore barrier in constructor with final field
jiangli
parents:
4808
diff
changeset
|
3311 |
701a83c86f28
7120481: storeStore barrier in constructor with final field
jiangli
parents:
4808
diff
changeset
|
3312 void LIR_Assembler::membar_storestore() { |
701a83c86f28
7120481: storeStore barrier in constructor with final field
jiangli
parents:
4808
diff
changeset
|
3313 // no-op |
701a83c86f28
7120481: storeStore barrier in constructor with final field
jiangli
parents:
4808
diff
changeset
|
3314 //__ membar(Assembler::Membar_mask_bits(Assembler::storestore)); |
701a83c86f28
7120481: storeStore barrier in constructor with final field
jiangli
parents:
4808
diff
changeset
|
3315 } |
701a83c86f28
7120481: storeStore barrier in constructor with final field
jiangli
parents:
4808
diff
changeset
|
3316 |
701a83c86f28
7120481: storeStore barrier in constructor with final field
jiangli
parents:
4808
diff
changeset
|
3317 void LIR_Assembler::membar_loadstore() { |
701a83c86f28
7120481: storeStore barrier in constructor with final field
jiangli
parents:
4808
diff
changeset
|
3318 // no-op |
701a83c86f28
7120481: storeStore barrier in constructor with final field
jiangli
parents:
4808
diff
changeset
|
3319 //__ membar(Assembler::Membar_mask_bits(Assembler::loadstore)); |
701a83c86f28
7120481: storeStore barrier in constructor with final field
jiangli
parents:
4808
diff
changeset
|
3320 } |
701a83c86f28
7120481: storeStore barrier in constructor with final field
jiangli
parents:
4808
diff
changeset
|
3321 |
701a83c86f28
7120481: storeStore barrier in constructor with final field
jiangli
parents:
4808
diff
changeset
|
3322 void LIR_Assembler::membar_storeload() { |
701a83c86f28
7120481: storeStore barrier in constructor with final field
jiangli
parents:
4808
diff
changeset
|
3323 __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad)); |
701a83c86f28
7120481: storeStore barrier in constructor with final field
jiangli
parents:
4808
diff
changeset
|
3324 } |
701a83c86f28
7120481: storeStore barrier in constructor with final field
jiangli
parents:
4808
diff
changeset
|
3325 |
701a83c86f28
7120481: storeStore barrier in constructor with final field
jiangli
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changeset
|
3326 |
1783 | 3327 // Pack two sequential registers containing 32 bit values |
0 | 3328 // into a single 64 bit register. |
1783 | 3329 // src and src->successor() are packed into dst |
3330 // src and dst may be the same register. | |
3331 // Note: src is destroyed | |
3332 void LIR_Assembler::pack64(LIR_Opr src, LIR_Opr dst) { | |
3333 Register rs = src->as_register(); | |
3334 Register rd = dst->as_register_lo(); | |
0 | 3335 __ sllx(rs, 32, rs); |
3336 __ srl(rs->successor(), 0, rs->successor()); | |
3337 __ or3(rs, rs->successor(), rd); | |
3338 } | |
3339 | |
1783 | 3340 // Unpack a 64 bit value in a register into |
0 | 3341 // two sequential registers. |
1783 | 3342 // src is unpacked into dst and dst->successor() |
3343 void LIR_Assembler::unpack64(LIR_Opr src, LIR_Opr dst) { | |
3344 Register rs = src->as_register_lo(); | |
3345 Register rd = dst->as_register_hi(); | |
3346 assert_different_registers(rs, rd, rd->successor()); | |
3347 __ srlx(rs, 32, rd); | |
3348 __ srl (rs, 0, rd->successor()); | |
0 | 3349 } |
3350 | |
3351 | |
3352 void LIR_Assembler::leal(LIR_Opr addr_opr, LIR_Opr dest) { | |
3353 LIR_Address* addr = addr_opr->as_address_ptr(); | |
3354 assert(addr->index()->is_illegal() && addr->scale() == LIR_Address::times_1 && Assembler::is_simm13(addr->disp()), "can't handle complex addresses yet"); | |
1783 | 3355 |
3356 __ add(addr->base()->as_pointer_register(), addr->disp(), dest->as_pointer_register()); | |
0 | 3357 } |
3358 | |
3359 | |
3360 void LIR_Assembler::get_thread(LIR_Opr result_reg) { | |
3361 assert(result_reg->is_register(), "check"); | |
3362 __ mov(G2_thread, result_reg->as_register()); | |
3363 } | |
3364 | |
3365 | |
3366 void LIR_Assembler::peephole(LIR_List* lir) { | |
3367 LIR_OpList* inst = lir->instructions_list(); | |
3368 for (int i = 0; i < inst->length(); i++) { | |
3369 LIR_Op* op = inst->at(i); | |
3370 switch (op->code()) { | |
3371 case lir_cond_float_branch: | |
3372 case lir_branch: { | |
3373 LIR_OpBranch* branch = op->as_OpBranch(); | |
3374 assert(branch->info() == NULL, "shouldn't be state on branches anymore"); | |
3375 LIR_Op* delay_op = NULL; | |
3376 // we'd like to be able to pull following instructions into | |
3377 // this slot but we don't know enough to do it safely yet so | |
3378 // only optimize block to block control flow. | |
3379 if (LIRFillDelaySlots && branch->block()) { | |
3380 LIR_Op* prev = inst->at(i - 1); | |
3381 if (prev && LIR_Assembler::is_single_instruction(prev) && prev->info() == NULL) { | |
3382 // swap previous instruction into delay slot | |
3383 inst->at_put(i - 1, op); | |
3384 inst->at_put(i, new LIR_OpDelay(prev, op->info())); | |
3385 #ifndef PRODUCT | |
3386 if (LIRTracePeephole) { | |
3387 tty->print_cr("delayed"); | |
3388 inst->at(i - 1)->print(); | |
3389 inst->at(i)->print(); | |
1564 | 3390 tty->cr(); |
0 | 3391 } |
3392 #endif | |
3393 continue; | |
3394 } | |
3395 } | |
3396 | |
3397 if (!delay_op) { | |
3398 delay_op = new LIR_OpDelay(new LIR_Op0(lir_nop), NULL); | |
3399 } | |
3400 inst->insert_before(i + 1, delay_op); | |
3401 break; | |
3402 } | |
3403 case lir_static_call: | |
3404 case lir_virtual_call: | |
3405 case lir_icvirtual_call: | |
1564 | 3406 case lir_optvirtual_call: |
3407 case lir_dynamic_call: { | |
0 | 3408 LIR_Op* prev = inst->at(i - 1); |
3409 if (LIRFillDelaySlots && prev && prev->code() == lir_move && prev->info() == NULL && | |
3410 (op->code() != lir_virtual_call || | |
3411 !prev->result_opr()->is_single_cpu() || | |
3412 prev->result_opr()->as_register() != O0) && | |
3413 LIR_Assembler::is_single_instruction(prev)) { | |
3414 // Only moves without info can be put into the delay slot. | |
3415 // Also don't allow the setup of the receiver in the delay | |
3416 // slot for vtable calls. | |
3417 inst->at_put(i - 1, op); | |
3418 inst->at_put(i, new LIR_OpDelay(prev, op->info())); | |
3419 #ifndef PRODUCT | |
3420 if (LIRTracePeephole) { | |
3421 tty->print_cr("delayed"); | |
3422 inst->at(i - 1)->print(); | |
3423 inst->at(i)->print(); | |
1564 | 3424 tty->cr(); |
0 | 3425 } |
3426 #endif | |
1783 | 3427 } else { |
3428 LIR_Op* delay_op = new LIR_OpDelay(new LIR_Op0(lir_nop), op->as_OpJavaCall()->info()); | |
3429 inst->insert_before(i + 1, delay_op); | |
3430 i++; | |
0 | 3431 } |
3432 | |
1783 | 3433 #if defined(TIERED) && !defined(_LP64) |
3434 // fixup the return value from G1 to O0/O1 for long returns. | |
3435 // It's done here instead of in LIRGenerator because there's | |
3436 // such a mismatch between the single reg and double reg | |
3437 // calling convention. | |
3438 LIR_OpJavaCall* callop = op->as_OpJavaCall(); | |
3439 if (callop->result_opr() == FrameMap::out_long_opr) { | |
3440 LIR_OpJavaCall* call; | |
3441 LIR_OprList* arguments = new LIR_OprList(callop->arguments()->length()); | |
3442 for (int a = 0; a < arguments->length(); a++) { | |
3443 arguments[a] = callop->arguments()[a]; | |
3444 } | |
3445 if (op->code() == lir_virtual_call) { | |
3446 call = new LIR_OpJavaCall(op->code(), callop->method(), callop->receiver(), FrameMap::g1_long_single_opr, | |
3447 callop->vtable_offset(), arguments, callop->info()); | |
3448 } else { | |
3449 call = new LIR_OpJavaCall(op->code(), callop->method(), callop->receiver(), FrameMap::g1_long_single_opr, | |
3450 callop->addr(), arguments, callop->info()); | |
3451 } | |
3452 inst->at_put(i - 1, call); | |
3453 inst->insert_before(i + 1, new LIR_Op1(lir_unpack64, FrameMap::g1_long_single_opr, callop->result_opr(), | |
3454 T_LONG, lir_patch_none, NULL)); | |
3455 } | |
3456 #endif | |
0 | 3457 break; |
3458 } | |
3459 } | |
3460 } | |
3461 } | |
3462 | |
6795
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6739
diff
changeset
|
3463 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) { |
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3464 LIR_Address* addr = src->as_address_ptr(); |
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3465 |
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3466 assert(data == dest, "swap uses only 2 operands"); |
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3467 assert (code == lir_xchg, "no xadd on sparc"); |
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3468 |
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3469 if (data->type() == T_INT) { |
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3470 __ swap(as_Address(addr), data->as_register()); |
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3471 } else if (data->is_oop()) { |
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3472 Register obj = data->as_register(); |
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3473 Register narrow = tmp->as_register(); |
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3474 #ifdef _LP64 |
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3475 assert(UseCompressedOops, "swap is 32bit only"); |
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3476 __ encode_heap_oop(obj, narrow); |
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3477 __ swap(as_Address(addr), narrow); |
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3478 __ decode_heap_oop(narrow, obj); |
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3479 #else |
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3480 __ swap(as_Address(addr), obj); |
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3481 #endif |
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3482 } else { |
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3483 ShouldNotReachHere(); |
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3484 } |
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3485 } |
0 | 3486 |
3487 #undef __ |