Mercurial > hg > truffle
annotate src/cpu/sparc/vm/vm_version_sparc.cpp @ 13434:a150ff9e8efc
Merge
author | hseigel |
---|---|
date | Fri, 06 Dec 2013 11:49:50 -0500 |
parents | 46c544b8fbfc |
children | eae426d683f6 |
rev | line source |
---|---|
0 | 1 /* |
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4053
diff
changeset
|
2 * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved. |
0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
4 * | |
5 * This code is free software; you can redistribute it and/or modify it | |
6 * under the terms of the GNU General Public License version 2 only, as | |
7 * published by the Free Software Foundation. | |
8 * | |
9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 * version 2 for more details (a copy is included in the LICENSE file that | |
13 * accompanied this code). | |
14 * | |
15 * You should have received a copy of the GNU General Public License version | |
16 * 2 along with this work; if not, write to the Free Software Foundation, | |
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
18 * | |
1552
c18cbe5936b8
6941466: Oracle rebranding changes for Hotspot repositories
trims
parents:
1518
diff
changeset
|
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
c18cbe5936b8
6941466: Oracle rebranding changes for Hotspot repositories
trims
parents:
1518
diff
changeset
|
20 * or visit www.oracle.com if you need additional information or have any |
c18cbe5936b8
6941466: Oracle rebranding changes for Hotspot repositories
trims
parents:
1518
diff
changeset
|
21 * questions. |
0 | 22 * |
23 */ | |
24 | |
1972 | 25 #include "precompiled.hpp" |
7204
f0c2369fda5a
8003250: SPARC: move MacroAssembler into separate file
twisti
parents:
6848
diff
changeset
|
26 #include "asm/macroAssembler.inline.hpp" |
1972 | 27 #include "memory/resourceArea.hpp" |
28 #include "runtime/java.hpp" | |
29 #include "runtime/stubCodeGenerator.hpp" | |
30 #include "vm_version_sparc.hpp" | |
31 #ifdef TARGET_OS_FAMILY_linux | |
32 # include "os_linux.inline.hpp" | |
33 #endif | |
34 #ifdef TARGET_OS_FAMILY_solaris | |
35 # include "os_solaris.inline.hpp" | |
36 #endif | |
0 | 37 |
38 int VM_Version::_features = VM_Version::unknown_m; | |
39 const char* VM_Version::_features_str = ""; | |
40 | |
41 void VM_Version::initialize() { | |
42 _features = determine_features(); | |
43 PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes(); | |
44 PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes(); | |
45 PrefetchFieldsAhead = prefetch_fields_ahead(); | |
46 | |
3854 | 47 assert(0 <= AllocatePrefetchInstr && AllocatePrefetchInstr <= 1, "invalid value"); |
48 if( AllocatePrefetchInstr < 0 ) AllocatePrefetchInstr = 0; | |
49 if( AllocatePrefetchInstr > 1 ) AllocatePrefetchInstr = 0; | |
50 | |
0 | 51 // Allocation prefetch settings |
3854 | 52 intx cache_line_size = prefetch_data_size(); |
0 | 53 if( cache_line_size > AllocatePrefetchStepSize ) |
54 AllocatePrefetchStepSize = cache_line_size; | |
3854 | 55 |
56 assert(AllocatePrefetchLines > 0, "invalid value"); | |
57 if( AllocatePrefetchLines < 1 ) // set valid value in product VM | |
58 AllocatePrefetchLines = 3; | |
59 assert(AllocateInstancePrefetchLines > 0, "invalid value"); | |
60 if( AllocateInstancePrefetchLines < 1 ) // set valid value in product VM | |
61 AllocateInstancePrefetchLines = 1; | |
0 | 62 |
63 AllocatePrefetchDistance = allocate_prefetch_distance(); | |
64 AllocatePrefetchStyle = allocate_prefetch_style(); | |
65 | |
3854 | 66 assert((AllocatePrefetchDistance % AllocatePrefetchStepSize) == 0 && |
67 (AllocatePrefetchDistance > 0), "invalid value"); | |
68 if ((AllocatePrefetchDistance % AllocatePrefetchStepSize) != 0 || | |
69 (AllocatePrefetchDistance <= 0)) { | |
70 AllocatePrefetchDistance = AllocatePrefetchStepSize; | |
71 } | |
0 | 72 |
3839 | 73 if (AllocatePrefetchStyle == 3 && !has_blk_init()) { |
74 warning("BIS instructions are not available on this CPU"); | |
75 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 1); | |
76 } | |
77 | |
10997 | 78 guarantee(VM_Version::has_v9(), "only SPARC v9 is supported"); |
79 | |
80 assert(ArraycopySrcPrefetchDistance < 4096, "invalid value"); | |
81 if (ArraycopySrcPrefetchDistance >= 4096) | |
82 ArraycopySrcPrefetchDistance = 4064; | |
83 assert(ArraycopyDstPrefetchDistance < 4096, "invalid value"); | |
84 if (ArraycopyDstPrefetchDistance >= 4096) | |
85 ArraycopyDstPrefetchDistance = 4064; | |
3903 | 86 |
0 | 87 UseSSE = 0; // Only on x86 and x64 |
88 | |
3854 | 89 _supports_cx8 = has_v9(); |
6795
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6610
diff
changeset
|
90 _supports_atomic_getset4 = true; // swap instruction |
0 | 91 |
2080 | 92 if (is_niagara()) { |
0 | 93 // Indirect branch is the same cost as direct |
94 if (FLAG_IS_DEFAULT(UseInlineCaches)) { | |
675 | 95 FLAG_SET_DEFAULT(UseInlineCaches, false); |
0 | 96 } |
2080 | 97 // Align loops on a single instruction boundary. |
98 if (FLAG_IS_DEFAULT(OptoLoopAlignment)) { | |
99 FLAG_SET_DEFAULT(OptoLoopAlignment, 4); | |
100 } | |
6610 | 101 // When using CMS or G1, we cannot use memset() in BOT updates |
102 // because the sun4v/CMT version in libc_psr uses BIS which | |
103 // exposes "phantom zeros" to concurrent readers. See 6948537. | |
104 if (FLAG_IS_DEFAULT(UseMemSetInBOT) && (UseConcMarkSweepGC || UseG1GC)) { | |
2080 | 105 FLAG_SET_DEFAULT(UseMemSetInBOT, false); |
106 } | |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
10
diff
changeset
|
107 #ifdef _LP64 |
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
641
diff
changeset
|
108 // 32-bit oops don't make sense for the 64-bit VM on sparc |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
641
diff
changeset
|
109 // since the 32-bit VM has the same registers and smaller objects. |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
641
diff
changeset
|
110 Universe::set_narrow_oop_shift(LogMinObjAlignmentInBytes); |
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6797
diff
changeset
|
111 Universe::set_narrow_klass_shift(LogKlassAlignmentInBytes); |
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
10
diff
changeset
|
112 #endif // _LP64 |
0 | 113 #ifdef COMPILER2 |
114 // Indirect branch is the same cost as direct | |
115 if (FLAG_IS_DEFAULT(UseJumpTables)) { | |
675 | 116 FLAG_SET_DEFAULT(UseJumpTables, true); |
0 | 117 } |
118 // Single-issue, so entry and loop tops are | |
119 // aligned on a single instruction boundary | |
120 if (FLAG_IS_DEFAULT(InteriorEntryAlignment)) { | |
675 | 121 FLAG_SET_DEFAULT(InteriorEntryAlignment, 4); |
0 | 122 } |
2080 | 123 if (is_niagara_plus()) { |
3854 | 124 if (has_blk_init() && UseTLAB && |
125 FLAG_IS_DEFAULT(AllocatePrefetchInstr)) { | |
126 // Use BIS instruction for TLAB allocation prefetch. | |
127 FLAG_SET_ERGO(intx, AllocatePrefetchInstr, 1); | |
128 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) { | |
129 FLAG_SET_ERGO(intx, AllocatePrefetchStyle, 3); | |
130 } | |
1367
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1365
diff
changeset
|
131 if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) { |
3854 | 132 // Use smaller prefetch distance with BIS |
1367
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1365
diff
changeset
|
133 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 64); |
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1365
diff
changeset
|
134 } |
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1365
diff
changeset
|
135 } |
3854 | 136 if (is_T4()) { |
137 // Double number of prefetched cache lines on T4 | |
138 // since L2 cache line size is smaller (32 bytes). | |
139 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) { | |
140 FLAG_SET_ERGO(intx, AllocatePrefetchLines, AllocatePrefetchLines*2); | |
141 } | |
142 if (FLAG_IS_DEFAULT(AllocateInstancePrefetchLines)) { | |
143 FLAG_SET_ERGO(intx, AllocateInstancePrefetchLines, AllocateInstancePrefetchLines*2); | |
144 } | |
145 } | |
1367
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1365
diff
changeset
|
146 if (AllocatePrefetchStyle != 3 && FLAG_IS_DEFAULT(AllocatePrefetchDistance)) { |
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1365
diff
changeset
|
147 // Use different prefetch distance without BIS |
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1365
diff
changeset
|
148 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 256); |
9e321dcfa5b7
6940726: Use BIS instruction for allocation prefetch on Sparc
kvn
parents:
1365
diff
changeset
|
149 } |
3854 | 150 if (AllocatePrefetchInstr == 1) { |
151 // Need a space at the end of TLAB for BIS since it | |
152 // will fault when accessing memory outside of heap. | |
153 | |
154 // +1 for rounding up to next cache line, +1 to be safe | |
155 int lines = AllocatePrefetchLines + 2; | |
156 int step_size = AllocatePrefetchStepSize; | |
157 int distance = AllocatePrefetchDistance; | |
158 _reserve_for_allocation_prefetch = (distance + step_size*lines)/(int)HeapWordSize; | |
159 } | |
0 | 160 } |
161 #endif | |
162 } | |
163 | |
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
164 // Use hardware population count instruction if available. |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
165 if (has_hardware_popc()) { |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
166 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) { |
675 | 167 FLAG_SET_DEFAULT(UsePopCountInstruction, true); |
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
168 } |
3839 | 169 } else if (UsePopCountInstruction) { |
170 warning("POPC instruction is not available on this CPU"); | |
171 FLAG_SET_DEFAULT(UsePopCountInstruction, false); | |
172 } | |
173 | |
174 // T4 and newer Sparc cpus have new compare and branch instruction. | |
175 if (has_cbcond()) { | |
176 if (FLAG_IS_DEFAULT(UseCBCond)) { | |
177 FLAG_SET_DEFAULT(UseCBCond, true); | |
178 } | |
179 } else if (UseCBCond) { | |
180 warning("CBCOND instruction is not available on this CPU"); | |
181 FLAG_SET_DEFAULT(UseCBCond, false); | |
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
182 } |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
183 |
3892 | 184 assert(BlockZeroingLowLimit > 0, "invalid value"); |
185 if (has_block_zeroing()) { | |
186 if (FLAG_IS_DEFAULT(UseBlockZeroing)) { | |
187 FLAG_SET_DEFAULT(UseBlockZeroing, true); | |
188 } | |
189 } else if (UseBlockZeroing) { | |
190 warning("BIS zeroing instructions are not available on this CPU"); | |
191 FLAG_SET_DEFAULT(UseBlockZeroing, false); | |
192 } | |
193 | |
3903 | 194 assert(BlockCopyLowLimit > 0, "invalid value"); |
195 if (has_block_zeroing()) { // has_blk_init() && is_T4(): core's local L2 cache | |
196 if (FLAG_IS_DEFAULT(UseBlockCopy)) { | |
197 FLAG_SET_DEFAULT(UseBlockCopy, true); | |
198 } | |
199 } else if (UseBlockCopy) { | |
200 warning("BIS instructions are not available or expensive on this CPU"); | |
201 FLAG_SET_DEFAULT(UseBlockCopy, false); | |
202 } | |
203 | |
1730
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
204 #ifdef COMPILER2 |
3839 | 205 // T4 and newer Sparc cpus have fast RDPC. |
206 if (has_fast_rdpc() && FLAG_IS_DEFAULT(UseRDPCForConstantTableBase)) { | |
4053
e3b0dcc327b9
7104561: UseRDPCForConstantTableBase doesn't work after shorten branches changes
twisti
parents:
3903
diff
changeset
|
207 FLAG_SET_DEFAULT(UseRDPCForConstantTableBase, true); |
3839 | 208 } |
209 | |
1730
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
210 // Currently not supported anywhere. |
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
211 FLAG_SET_DEFAULT(UseFPUForSpilling, false); |
3851 | 212 |
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4053
diff
changeset
|
213 MaxVectorSize = 8; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4053
diff
changeset
|
214 |
3851 | 215 assert((InteriorEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size"); |
1730
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
216 #endif |
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
217 |
3851 | 218 assert((CodeEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size"); |
219 assert((OptoLoopAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size"); | |
220 | |
0 | 221 char buf[512]; |
3839 | 222 jio_snprintf(buf, sizeof(buf), "%s%s%s%s%s%s%s%s%s%s%s%s%s%s", |
223 (has_v9() ? ", v9" : (has_v8() ? ", v8" : "")), | |
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
224 (has_hardware_popc() ? ", popc" : ""), |
3839 | 225 (has_vis1() ? ", vis1" : ""), |
226 (has_vis2() ? ", vis2" : ""), | |
227 (has_vis3() ? ", vis3" : ""), | |
228 (has_blk_init() ? ", blk_init" : ""), | |
229 (has_cbcond() ? ", cbcond" : ""), | |
230 (is_ultra3() ? ", ultra3" : ""), | |
231 (is_sun4v() ? ", sun4v" : ""), | |
232 (is_niagara_plus() ? ", niagara_plus" : (is_niagara() ? ", niagara" : "")), | |
233 (is_sparc64() ? ", sparc64" : ""), | |
641
6af0a709d52b
6812587: Use auxv to determine SPARC hardware features on Solaris
twisti
parents:
196
diff
changeset
|
234 (!has_hardware_mul32() ? ", no-mul32" : ""), |
6af0a709d52b
6812587: Use auxv to determine SPARC hardware features on Solaris
twisti
parents:
196
diff
changeset
|
235 (!has_hardware_div32() ? ", no-div32" : ""), |
0 | 236 (!has_hardware_fsmuld() ? ", no-fsmuld" : "")); |
237 | |
238 // buf is started with ", " or is empty | |
239 _features_str = strdup(strlen(buf) > 2 ? buf + 2 : buf); | |
240 | |
3804 | 241 // UseVIS is set to the smallest of what hardware supports and what |
242 // the command line requires. I.e., you cannot set UseVIS to 3 on | |
243 // older UltraSparc which do not support it. | |
244 if (UseVIS > 3) UseVIS=3; | |
245 if (UseVIS < 0) UseVIS=0; | |
246 if (!has_vis3()) // Drop to 2 if no VIS3 support | |
247 UseVIS = MIN2((intx)2,UseVIS); | |
248 if (!has_vis2()) // Drop to 1 if no VIS2 support | |
249 UseVIS = MIN2((intx)1,UseVIS); | |
250 if (!has_vis1()) // Drop to 0 if no VIS1 support | |
251 UseVIS = 0; | |
252 | |
7587 | 253 if (FLAG_IS_DEFAULT(ContendedPaddingWidth) && |
254 (cache_line_size > ContendedPaddingWidth)) | |
255 ContendedPaddingWidth = cache_line_size; | |
256 | |
0 | 257 #ifndef PRODUCT |
258 if (PrintMiscellaneous && Verbose) { | |
3854 | 259 tty->print("Allocation"); |
0 | 260 if (AllocatePrefetchStyle <= 0) { |
3854 | 261 tty->print_cr(": no prefetching"); |
0 | 262 } else { |
3854 | 263 tty->print(" prefetching: "); |
264 if (AllocatePrefetchInstr == 0) { | |
265 tty->print("PREFETCH"); | |
266 } else if (AllocatePrefetchInstr == 1) { | |
267 tty->print("BIS"); | |
268 } | |
0 | 269 if (AllocatePrefetchLines > 1) { |
3854 | 270 tty->print_cr(" at distance %d, %d lines of %d bytes", AllocatePrefetchDistance, AllocatePrefetchLines, AllocatePrefetchStepSize); |
0 | 271 } else { |
3854 | 272 tty->print_cr(" at distance %d, one line of %d bytes", AllocatePrefetchDistance, AllocatePrefetchStepSize); |
0 | 273 } |
274 } | |
275 if (PrefetchCopyIntervalInBytes > 0) { | |
276 tty->print_cr("PrefetchCopyIntervalInBytes %d", PrefetchCopyIntervalInBytes); | |
277 } | |
278 if (PrefetchScanIntervalInBytes > 0) { | |
279 tty->print_cr("PrefetchScanIntervalInBytes %d", PrefetchScanIntervalInBytes); | |
280 } | |
281 if (PrefetchFieldsAhead > 0) { | |
282 tty->print_cr("PrefetchFieldsAhead %d", PrefetchFieldsAhead); | |
283 } | |
7587 | 284 if (ContendedPaddingWidth > 0) { |
285 tty->print_cr("ContendedPaddingWidth %d", ContendedPaddingWidth); | |
286 } | |
0 | 287 } |
288 #endif // PRODUCT | |
289 } | |
290 | |
291 void VM_Version::print_features() { | |
292 tty->print_cr("Version:%s", cpu_features()); | |
293 } | |
294 | |
295 int VM_Version::determine_features() { | |
296 if (UseV8InstrsOnly) { | |
297 NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-V8");) | |
298 return generic_v8_m; | |
299 } | |
300 | |
301 int features = platform_features(unknown_m); // platform_features() is os_arch specific | |
302 | |
303 if (features == unknown_m) { | |
304 features = generic_v9_m; | |
305 warning("Cannot recognize SPARC version. Default to V9"); | |
306 } | |
307 | |
2080 | 308 assert(is_T_family(features) == is_niagara(features), "Niagara should be T series"); |
309 if (UseNiagaraInstrs) { // Force code generation for Niagara | |
310 if (is_T_family(features)) { | |
0 | 311 // Happy to accomodate... |
312 } else { | |
313 NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-Niagara");) | |
2080 | 314 features |= T_family_m; |
0 | 315 } |
316 } else { | |
2080 | 317 if (is_T_family(features) && !FLAG_IS_DEFAULT(UseNiagaraInstrs)) { |
0 | 318 NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-Not-Niagara");) |
2080 | 319 features &= ~(T_family_m | T1_model_m); |
0 | 320 } else { |
321 // Happy to accomodate... | |
322 } | |
323 } | |
324 | |
325 return features; | |
326 } | |
327 | |
328 static int saved_features = 0; | |
329 | |
330 void VM_Version::allow_all() { | |
331 saved_features = _features; | |
332 _features = all_features_m; | |
333 } | |
334 | |
335 void VM_Version::revert() { | |
336 _features = saved_features; | |
337 } | |
10
28372612af5e
6362677: Change parallel GC collector default number of parallel GC threads.
jmasa
parents:
0
diff
changeset
|
338 |
28372612af5e
6362677: Change parallel GC collector default number of parallel GC threads.
jmasa
parents:
0
diff
changeset
|
339 unsigned int VM_Version::calc_parallel_worker_threads() { |
28372612af5e
6362677: Change parallel GC collector default number of parallel GC threads.
jmasa
parents:
0
diff
changeset
|
340 unsigned int result; |
6797
3a327d0b8586
7188176: The JVM should differentiate between T and M series and adjust GC ergonomics
twisti
parents:
6795
diff
changeset
|
341 if (is_M_series()) { |
3a327d0b8586
7188176: The JVM should differentiate between T and M series and adjust GC ergonomics
twisti
parents:
6795
diff
changeset
|
342 // for now, use same gc thread calculation for M-series as for niagara-plus |
3a327d0b8586
7188176: The JVM should differentiate between T and M series and adjust GC ergonomics
twisti
parents:
6795
diff
changeset
|
343 // in future, we may want to tweak parameters for nof_parallel_worker_thread |
3a327d0b8586
7188176: The JVM should differentiate between T and M series and adjust GC ergonomics
twisti
parents:
6795
diff
changeset
|
344 result = nof_parallel_worker_threads(5, 16, 8); |
3a327d0b8586
7188176: The JVM should differentiate between T and M series and adjust GC ergonomics
twisti
parents:
6795
diff
changeset
|
345 } else if (is_niagara_plus()) { |
10
28372612af5e
6362677: Change parallel GC collector default number of parallel GC threads.
jmasa
parents:
0
diff
changeset
|
346 result = nof_parallel_worker_threads(5, 16, 8); |
28372612af5e
6362677: Change parallel GC collector default number of parallel GC threads.
jmasa
parents:
0
diff
changeset
|
347 } else { |
28372612af5e
6362677: Change parallel GC collector default number of parallel GC threads.
jmasa
parents:
0
diff
changeset
|
348 result = nof_parallel_worker_threads(5, 8, 8); |
28372612af5e
6362677: Change parallel GC collector default number of parallel GC threads.
jmasa
parents:
0
diff
changeset
|
349 } |
28372612af5e
6362677: Change parallel GC collector default number of parallel GC threads.
jmasa
parents:
0
diff
changeset
|
350 return result; |
28372612af5e
6362677: Change parallel GC collector default number of parallel GC threads.
jmasa
parents:
0
diff
changeset
|
351 } |