Mercurial > hg > truffle
annotate src/cpu/sparc/vm/vm_version_sparc.cpp @ 643:c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
Summary: bitCount() should use POPC on SPARC processors where POPC is implemented directly in hardware.
Reviewed-by: kvn, never
| author | twisti |
|---|---|
| date | Fri, 13 Mar 2009 11:35:17 -0700 |
| parents | 660978a2a31a |
| children | f6da6f0174ac |
| rev | line source |
|---|---|
| 0 | 1 /* |
|
641
6af0a709d52b
6812587: Use auxv to determine SPARC hardware features on Solaris
twisti
parents:
196
diff
changeset
|
2 * Copyright 1997-2009 Sun Microsystems, Inc. All Rights Reserved. |
| 0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 4 * | |
| 5 * This code is free software; you can redistribute it and/or modify it | |
| 6 * under the terms of the GNU General Public License version 2 only, as | |
| 7 * published by the Free Software Foundation. | |
| 8 * | |
| 9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 * version 2 for more details (a copy is included in the LICENSE file that | |
| 13 * accompanied this code). | |
| 14 * | |
| 15 * You should have received a copy of the GNU General Public License version | |
| 16 * 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 * | |
| 19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
| 20 * CA 95054 USA or visit www.sun.com if you need additional information or | |
| 21 * have any questions. | |
| 22 * | |
| 23 */ | |
| 24 | |
| 25 # include "incls/_precompiled.incl" | |
| 26 # include "incls/_vm_version_sparc.cpp.incl" | |
| 27 | |
| 28 int VM_Version::_features = VM_Version::unknown_m; | |
| 29 const char* VM_Version::_features_str = ""; | |
| 30 | |
|
10
28372612af5e
6362677: Change parallel GC collector default number of parallel GC threads.
jmasa
parents:
0
diff
changeset
|
31 bool VM_Version::is_niagara1_plus() { |
|
28372612af5e
6362677: Change parallel GC collector default number of parallel GC threads.
jmasa
parents:
0
diff
changeset
|
32 // This is a placeholder until the real test is determined. |
|
28372612af5e
6362677: Change parallel GC collector default number of parallel GC threads.
jmasa
parents:
0
diff
changeset
|
33 return is_niagara1() && |
|
28372612af5e
6362677: Change parallel GC collector default number of parallel GC threads.
jmasa
parents:
0
diff
changeset
|
34 (os::processor_count() > maximum_niagara1_processor_count()); |
|
28372612af5e
6362677: Change parallel GC collector default number of parallel GC threads.
jmasa
parents:
0
diff
changeset
|
35 } |
|
28372612af5e
6362677: Change parallel GC collector default number of parallel GC threads.
jmasa
parents:
0
diff
changeset
|
36 |
| 0 | 37 void VM_Version::initialize() { |
| 38 _features = determine_features(); | |
| 39 PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes(); | |
| 40 PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes(); | |
| 41 PrefetchFieldsAhead = prefetch_fields_ahead(); | |
| 42 | |
| 43 // Allocation prefetch settings | |
| 44 intx cache_line_size = L1_data_cache_line_size(); | |
| 45 if( cache_line_size > AllocatePrefetchStepSize ) | |
| 46 AllocatePrefetchStepSize = cache_line_size; | |
| 47 if( FLAG_IS_DEFAULT(AllocatePrefetchLines) ) | |
| 48 AllocatePrefetchLines = 3; // Optimistic value | |
| 49 assert( AllocatePrefetchLines > 0, "invalid value"); | |
| 50 if( AllocatePrefetchLines < 1 ) // set valid value in product VM | |
| 51 AllocatePrefetchLines = 1; // Conservative value | |
| 52 | |
| 53 AllocatePrefetchDistance = allocate_prefetch_distance(); | |
| 54 AllocatePrefetchStyle = allocate_prefetch_style(); | |
| 55 | |
| 56 assert(AllocatePrefetchDistance % AllocatePrefetchStepSize == 0, "invalid value"); | |
| 57 | |
| 58 UseSSE = 0; // Only on x86 and x64 | |
| 59 | |
| 60 _supports_cx8 = has_v9(); | |
| 61 | |
| 62 if (is_niagara1()) { | |
| 63 // Indirect branch is the same cost as direct | |
| 64 if (FLAG_IS_DEFAULT(UseInlineCaches)) { | |
| 65 UseInlineCaches = false; | |
| 66 } | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
10
diff
changeset
|
67 #ifdef _LP64 |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
10
diff
changeset
|
68 // Single issue niagara1 is slower for CompressedOops |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
10
diff
changeset
|
69 // but niagaras after that it's fine. |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
10
diff
changeset
|
70 if (!is_niagara1_plus()) { |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
10
diff
changeset
|
71 if (FLAG_IS_DEFAULT(UseCompressedOops)) { |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
10
diff
changeset
|
72 FLAG_SET_ERGO(bool, UseCompressedOops, false); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
10
diff
changeset
|
73 } |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
10
diff
changeset
|
74 } |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
641
diff
changeset
|
75 // 32-bit oops don't make sense for the 64-bit VM on sparc |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
641
diff
changeset
|
76 // since the 32-bit VM has the same registers and smaller objects. |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
641
diff
changeset
|
77 Universe::set_narrow_oop_shift(LogMinObjAlignmentInBytes); |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
10
diff
changeset
|
78 #endif // _LP64 |
| 0 | 79 #ifdef COMPILER2 |
| 80 // Indirect branch is the same cost as direct | |
| 81 if (FLAG_IS_DEFAULT(UseJumpTables)) { | |
| 82 UseJumpTables = true; | |
| 83 } | |
| 84 // Single-issue, so entry and loop tops are | |
| 85 // aligned on a single instruction boundary | |
| 86 if (FLAG_IS_DEFAULT(InteriorEntryAlignment)) { | |
| 87 InteriorEntryAlignment = 4; | |
| 88 } | |
| 89 if (FLAG_IS_DEFAULT(OptoLoopAlignment)) { | |
| 90 OptoLoopAlignment = 4; | |
| 91 } | |
| 92 #endif | |
| 93 } | |
| 94 | |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
95 // Use hardware population count instruction if available. |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
96 if (has_hardware_popc()) { |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
97 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) { |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
98 UsePopCountInstruction = true; |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
99 } |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
100 } |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
101 |
| 0 | 102 char buf[512]; |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
103 jio_snprintf(buf, sizeof(buf), "%s%s%s%s%s%s%s%s%s%s%s%s", |
| 0 | 104 (has_v8() ? ", has_v8" : ""), |
| 105 (has_v9() ? ", has_v9" : ""), | |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
106 (has_hardware_popc() ? ", popc" : ""), |
| 0 | 107 (has_vis1() ? ", has_vis1" : ""), |
| 108 (has_vis2() ? ", has_vis2" : ""), | |
| 109 (is_ultra3() ? ", is_ultra3" : ""), | |
| 110 (is_sun4v() ? ", is_sun4v" : ""), | |
| 111 (is_niagara1() ? ", is_niagara1" : ""), | |
|
641
6af0a709d52b
6812587: Use auxv to determine SPARC hardware features on Solaris
twisti
parents:
196
diff
changeset
|
112 (is_niagara1_plus() ? ", is_niagara1_plus" : ""), |
|
6af0a709d52b
6812587: Use auxv to determine SPARC hardware features on Solaris
twisti
parents:
196
diff
changeset
|
113 (!has_hardware_mul32() ? ", no-mul32" : ""), |
|
6af0a709d52b
6812587: Use auxv to determine SPARC hardware features on Solaris
twisti
parents:
196
diff
changeset
|
114 (!has_hardware_div32() ? ", no-div32" : ""), |
| 0 | 115 (!has_hardware_fsmuld() ? ", no-fsmuld" : "")); |
| 116 | |
| 117 // buf is started with ", " or is empty | |
| 118 _features_str = strdup(strlen(buf) > 2 ? buf + 2 : buf); | |
| 119 | |
| 120 #ifndef PRODUCT | |
| 121 if (PrintMiscellaneous && Verbose) { | |
| 122 tty->print("Allocation: "); | |
| 123 if (AllocatePrefetchStyle <= 0) { | |
| 124 tty->print_cr("no prefetching"); | |
| 125 } else { | |
| 126 if (AllocatePrefetchLines > 1) { | |
| 127 tty->print_cr("PREFETCH %d, %d lines of size %d bytes", AllocatePrefetchDistance, AllocatePrefetchLines, AllocatePrefetchStepSize); | |
| 128 } else { | |
| 129 tty->print_cr("PREFETCH %d, one line", AllocatePrefetchDistance); | |
| 130 } | |
| 131 } | |
| 132 if (PrefetchCopyIntervalInBytes > 0) { | |
| 133 tty->print_cr("PrefetchCopyIntervalInBytes %d", PrefetchCopyIntervalInBytes); | |
| 134 } | |
| 135 if (PrefetchScanIntervalInBytes > 0) { | |
| 136 tty->print_cr("PrefetchScanIntervalInBytes %d", PrefetchScanIntervalInBytes); | |
| 137 } | |
| 138 if (PrefetchFieldsAhead > 0) { | |
| 139 tty->print_cr("PrefetchFieldsAhead %d", PrefetchFieldsAhead); | |
| 140 } | |
| 141 } | |
| 142 #endif // PRODUCT | |
| 143 } | |
| 144 | |
| 145 void VM_Version::print_features() { | |
| 146 tty->print_cr("Version:%s", cpu_features()); | |
| 147 } | |
| 148 | |
| 149 int VM_Version::determine_features() { | |
| 150 if (UseV8InstrsOnly) { | |
| 151 NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-V8");) | |
| 152 return generic_v8_m; | |
| 153 } | |
| 154 | |
| 155 int features = platform_features(unknown_m); // platform_features() is os_arch specific | |
| 156 | |
| 157 if (features == unknown_m) { | |
| 158 features = generic_v9_m; | |
| 159 warning("Cannot recognize SPARC version. Default to V9"); | |
| 160 } | |
| 161 | |
| 162 if (UseNiagaraInstrs) { | |
| 163 if (is_niagara1(features)) { | |
| 164 // Happy to accomodate... | |
| 165 } else { | |
| 166 NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-Niagara");) | |
| 167 features = niagara1_m; | |
| 168 } | |
| 169 } else { | |
| 170 if (is_niagara1(features) && !FLAG_IS_DEFAULT(UseNiagaraInstrs)) { | |
| 171 NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-Not-Niagara");) | |
| 172 features &= ~niagara1_unique_m; | |
| 173 } else { | |
| 174 // Happy to accomodate... | |
| 175 } | |
| 176 } | |
| 177 | |
| 178 return features; | |
| 179 } | |
| 180 | |
| 181 static int saved_features = 0; | |
| 182 | |
| 183 void VM_Version::allow_all() { | |
| 184 saved_features = _features; | |
| 185 _features = all_features_m; | |
| 186 } | |
| 187 | |
| 188 void VM_Version::revert() { | |
| 189 _features = saved_features; | |
| 190 } | |
|
10
28372612af5e
6362677: Change parallel GC collector default number of parallel GC threads.
jmasa
parents:
0
diff
changeset
|
191 |
|
28372612af5e
6362677: Change parallel GC collector default number of parallel GC threads.
jmasa
parents:
0
diff
changeset
|
192 unsigned int VM_Version::calc_parallel_worker_threads() { |
|
28372612af5e
6362677: Change parallel GC collector default number of parallel GC threads.
jmasa
parents:
0
diff
changeset
|
193 unsigned int result; |
|
28372612af5e
6362677: Change parallel GC collector default number of parallel GC threads.
jmasa
parents:
0
diff
changeset
|
194 if (is_niagara1_plus()) { |
|
28372612af5e
6362677: Change parallel GC collector default number of parallel GC threads.
jmasa
parents:
0
diff
changeset
|
195 result = nof_parallel_worker_threads(5, 16, 8); |
|
28372612af5e
6362677: Change parallel GC collector default number of parallel GC threads.
jmasa
parents:
0
diff
changeset
|
196 } else { |
|
28372612af5e
6362677: Change parallel GC collector default number of parallel GC threads.
jmasa
parents:
0
diff
changeset
|
197 result = nof_parallel_worker_threads(5, 8, 8); |
|
28372612af5e
6362677: Change parallel GC collector default number of parallel GC threads.
jmasa
parents:
0
diff
changeset
|
198 } |
|
28372612af5e
6362677: Change parallel GC collector default number of parallel GC threads.
jmasa
parents:
0
diff
changeset
|
199 return result; |
|
28372612af5e
6362677: Change parallel GC collector default number of parallel GC threads.
jmasa
parents:
0
diff
changeset
|
200 } |