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1 /*
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2 * Copyright 1997-2007 Sun Microsystems, Inc. All Rights Reserved.
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3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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4 *
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5 * This code is free software; you can redistribute it and/or modify it
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6 * under the terms of the GNU General Public License version 2 only, as
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7 * published by the Free Software Foundation.
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8 *
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9 * This code is distributed in the hope that it will be useful, but WITHOUT
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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12 * version 2 for more details (a copy is included in the LICENSE file that
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13 * accompanied this code).
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14 *
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15 * You should have received a copy of the GNU General Public License version
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16 * 2 along with this work; if not, write to the Free Software Foundation,
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17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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18 *
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19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
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20 * CA 95054 USA or visit www.sun.com if you need additional information or
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21 * have any questions.
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22 *
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23 */
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24
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25 # include "incls/_precompiled.incl"
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26 # include "incls/_nativeInst_sparc.cpp.incl"
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27
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28
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29 void NativeInstruction::set_data64_sethi(address instaddr, intptr_t x) {
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30 ResourceMark rm;
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31 CodeBuffer buf(instaddr, 10 * BytesPerInstWord );
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32 MacroAssembler* _masm = new MacroAssembler(&buf);
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33 Register destreg;
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34
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35 destreg = inv_rd(*(unsigned int *)instaddr);
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36 // Generate a the new sequence
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37 Address dest( destreg, (address)x );
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38 _masm->sethi( dest, true );
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39 ICache::invalidate_range(instaddr, 7 * BytesPerInstWord);
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40 }
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41
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42 void NativeInstruction::verify() {
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43 // make sure code pattern is actually an instruction address
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44 address addr = addr_at(0);
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45 if (addr == 0 || ((intptr_t)addr & 3) != 0) {
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46 fatal("not an instruction address");
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47 }
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48 }
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49
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50 void NativeInstruction::print() {
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51 tty->print_cr(INTPTR_FORMAT ": 0x%x", addr_at(0), long_at(0));
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52 }
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53
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54 void NativeInstruction::set_long_at(int offset, int i) {
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55 address addr = addr_at(offset);
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56 *(int*)addr = i;
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57 ICache::invalidate_word(addr);
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58 }
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59
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60 void NativeInstruction::set_jlong_at(int offset, jlong i) {
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61 address addr = addr_at(offset);
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62 *(jlong*)addr = i;
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63 // Don't need to invalidate 2 words here, because
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64 // the flush instruction operates on doublewords.
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65 ICache::invalidate_word(addr);
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66 }
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67
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68 void NativeInstruction::set_addr_at(int offset, address x) {
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69 address addr = addr_at(offset);
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70 assert( ((intptr_t)addr & (wordSize-1)) == 0, "set_addr_at bad address alignment");
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71 *(uintptr_t*)addr = (uintptr_t)x;
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72 // Don't need to invalidate 2 words here in the 64-bit case,
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73 // because the flush instruction operates on doublewords.
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74 ICache::invalidate_word(addr);
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75 // The Intel code has this assertion for NativeCall::set_destination,
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76 // NativeMovConstReg::set_data, NativeMovRegMem::set_offset,
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77 // NativeJump::set_jump_destination, and NativePushImm32::set_data
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78 //assert (Patching_lock->owned_by_self(), "must hold lock to patch instruction")
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79 }
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80
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81 bool NativeInstruction::is_zero_test(Register ®) {
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82 int x = long_at(0);
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83 Assembler::op3s temp = (Assembler::op3s) (Assembler::sub_op3 | Assembler::cc_bit_op3);
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84 if (is_op3(x, temp, Assembler::arith_op) &&
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85 inv_immed(x) && inv_rd(x) == G0) {
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86 if (inv_rs1(x) == G0) {
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87 reg = inv_rs2(x);
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88 return true;
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89 } else if (inv_rs2(x) == G0) {
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90 reg = inv_rs1(x);
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91 return true;
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92 }
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93 }
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94 return false;
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95 }
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96
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97 bool NativeInstruction::is_load_store_with_small_offset(Register reg) {
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98 int x = long_at(0);
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99 if (is_op(x, Assembler::ldst_op) &&
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100 inv_rs1(x) == reg && inv_immed(x)) {
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101 return true;
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102 }
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103 return false;
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104 }
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105
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106 void NativeCall::verify() {
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107 NativeInstruction::verify();
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108 // make sure code pattern is actually a call instruction
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109 if (!is_op(long_at(0), Assembler::call_op)) {
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110 fatal("not a call");
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111 }
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112 }
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113
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114 void NativeCall::print() {
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115 tty->print_cr(INTPTR_FORMAT ": call " INTPTR_FORMAT, instruction_address(), destination());
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116 }
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117
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118
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119 // MT-safe patching of a call instruction (and following word).
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120 // First patches the second word, and then atomicly replaces
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121 // the first word with the first new instruction word.
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122 // Other processors might briefly see the old first word
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123 // followed by the new second word. This is OK if the old
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124 // second word is harmless, and the new second word may be
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125 // harmlessly executed in the delay slot of the call.
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126 void NativeCall::replace_mt_safe(address instr_addr, address code_buffer) {
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127 assert(Patching_lock->is_locked() ||
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128 SafepointSynchronize::is_at_safepoint(), "concurrent code patching");
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129 assert (instr_addr != NULL, "illegal address for code patching");
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130 NativeCall* n_call = nativeCall_at (instr_addr); // checking that it is a call
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131 assert(NativeCall::instruction_size == 8, "wrong instruction size; must be 8");
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132 int i0 = ((int*)code_buffer)[0];
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133 int i1 = ((int*)code_buffer)[1];
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134 int* contention_addr = (int*) n_call->addr_at(1*BytesPerInstWord);
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135 assert(inv_op(*contention_addr) == Assembler::arith_op ||
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136 *contention_addr == nop_instruction() || !VM_Version::v9_instructions_work(),
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137 "must not interfere with original call");
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138 // The set_long_at calls do the ICacheInvalidate so we just need to do them in reverse order
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139 n_call->set_long_at(1*BytesPerInstWord, i1);
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140 n_call->set_long_at(0*BytesPerInstWord, i0);
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141 // NOTE: It is possible that another thread T will execute
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142 // only the second patched word.
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143 // In other words, since the original instruction is this
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144 // call patching_stub; nop (NativeCall)
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145 // and the new sequence from the buffer is this:
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146 // sethi %hi(K), %r; add %r, %lo(K), %r (NativeMovConstReg)
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147 // what T will execute is this:
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148 // call patching_stub; add %r, %lo(K), %r
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149 // thereby putting garbage into %r before calling the patching stub.
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150 // This is OK, because the patching stub ignores the value of %r.
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151
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152 // Make sure the first-patched instruction, which may co-exist
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153 // briefly with the call, will do something harmless.
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154 assert(inv_op(*contention_addr) == Assembler::arith_op ||
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155 *contention_addr == nop_instruction() || !VM_Version::v9_instructions_work(),
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156 "must not interfere with original call");
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157 }
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158
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159 // Similar to replace_mt_safe, but just changes the destination. The
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160 // important thing is that free-running threads are able to execute this
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161 // call instruction at all times. Thus, the displacement field must be
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162 // instruction-word-aligned. This is always true on SPARC.
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163 //
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164 // Used in the runtime linkage of calls; see class CompiledIC.
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165 void NativeCall::set_destination_mt_safe(address dest) {
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166 assert(Patching_lock->is_locked() ||
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167 SafepointSynchronize::is_at_safepoint(), "concurrent code patching");
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168 // set_destination uses set_long_at which does the ICache::invalidate
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169 set_destination(dest);
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170 }
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171
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172 // Code for unit testing implementation of NativeCall class
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173 void NativeCall::test() {
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174 #ifdef ASSERT
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175 ResourceMark rm;
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176 CodeBuffer cb("test", 100, 100);
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177 MacroAssembler* a = new MacroAssembler(&cb);
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178 NativeCall *nc;
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179 uint idx;
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180 int offsets[] = {
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181 0x0,
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182 0xfffffff0,
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183 0x7ffffff0,
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184 0x80000000,
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185 0x20,
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186 0x4000,
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187 };
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188
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189 VM_Version::allow_all();
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190
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191 a->call( a->pc(), relocInfo::none );
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192 a->delayed()->nop();
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193 nc = nativeCall_at( cb.code_begin() );
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194 nc->print();
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195
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196 nc = nativeCall_overwriting_at( nc->next_instruction_address() );
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197 for (idx = 0; idx < ARRAY_SIZE(offsets); idx++) {
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198 nc->set_destination( cb.code_begin() + offsets[idx] );
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199 assert(nc->destination() == (cb.code_begin() + offsets[idx]), "check unit test");
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200 nc->print();
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201 }
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202
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203 nc = nativeCall_before( cb.code_begin() + 8 );
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204 nc->print();
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205
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206 VM_Version::revert();
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207 #endif
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208 }
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209 // End code for unit testing implementation of NativeCall class
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210
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211 //-------------------------------------------------------------------
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212
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213 #ifdef _LP64
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214
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215 void NativeFarCall::set_destination(address dest) {
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216 // Address materialized in the instruction stream, so nothing to do.
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217 return;
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218 #if 0 // What we'd do if we really did want to change the destination
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219 if (destination() == dest) {
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220 return;
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221 }
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222 ResourceMark rm;
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223 CodeBuffer buf(addr_at(0), instruction_size + 1);
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224 MacroAssembler* _masm = new MacroAssembler(&buf);
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225 // Generate the new sequence
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226 Address(O7, dest);
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227 _masm->jumpl_to(dest, O7);
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228 ICache::invalidate_range(addr_at(0), instruction_size );
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229 #endif
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230 }
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231
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232 void NativeFarCall::verify() {
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233 // make sure code pattern is actually a jumpl_to instruction
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234 assert((int)instruction_size == (int)NativeJump::instruction_size, "same as jump_to");
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235 assert((int)jmpl_offset == (int)NativeMovConstReg::add_offset, "sethi size ok");
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236 nativeJump_at(addr_at(0))->verify();
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237 }
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238
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239 bool NativeFarCall::is_call_at(address instr) {
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240 return nativeInstruction_at(instr)->is_sethi();
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241 }
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242
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243 void NativeFarCall::print() {
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244 tty->print_cr(INTPTR_FORMAT ": call " INTPTR_FORMAT, instruction_address(), destination());
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245 }
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246
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247 bool NativeFarCall::destination_is_compiled_verified_entry_point() {
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248 nmethod* callee = CodeCache::find_nmethod(destination());
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249 if (callee == NULL) {
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250 return false;
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251 } else {
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252 return destination() == callee->verified_entry_point();
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253 }
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254 }
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255
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256 // MT-safe patching of a far call.
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257 void NativeFarCall::replace_mt_safe(address instr_addr, address code_buffer) {
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258 Unimplemented();
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259 }
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260
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261 // Code for unit testing implementation of NativeFarCall class
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262 void NativeFarCall::test() {
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263 Unimplemented();
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264 }
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265 // End code for unit testing implementation of NativeFarCall class
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266
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267 #endif // _LP64
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268
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269 //-------------------------------------------------------------------
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270
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271
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272 void NativeMovConstReg::verify() {
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273 NativeInstruction::verify();
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274 // make sure code pattern is actually a "set_oop" synthetic instruction
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275 // see MacroAssembler::set_oop()
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276 int i0 = long_at(sethi_offset);
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277 int i1 = long_at(add_offset);
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278
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279 // verify the pattern "sethi %hi22(imm), reg ; add reg, %lo10(imm), reg"
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280 Register rd = inv_rd(i0);
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281 #ifndef _LP64
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282 if (!(is_op2(i0, Assembler::sethi_op2) && rd != G0 &&
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283 is_op3(i1, Assembler::add_op3, Assembler::arith_op) &&
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284 inv_immed(i1) && (unsigned)get_simm13(i1) < (1 << 10) &&
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285 rd == inv_rs1(i1) && rd == inv_rd(i1))) {
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286 fatal("not a set_oop");
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287 }
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288 #else
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289 if (!is_op2(i0, Assembler::sethi_op2) && rd != G0 ) {
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290 fatal("not a set_oop");
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291 }
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292 #endif
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293 }
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294
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295
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296 void NativeMovConstReg::print() {
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297 tty->print_cr(INTPTR_FORMAT ": mov reg, " INTPTR_FORMAT, instruction_address(), data());
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298 }
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299
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300
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301 #ifdef _LP64
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302 intptr_t NativeMovConstReg::data() const {
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303 return data64(addr_at(sethi_offset), long_at(add_offset));
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304 }
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305 #else
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306 intptr_t NativeMovConstReg::data() const {
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307 return data32(long_at(sethi_offset), long_at(add_offset));
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308 }
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309 #endif
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310
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311
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312 void NativeMovConstReg::set_data(intptr_t x) {
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313 #ifdef _LP64
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314 set_data64_sethi(addr_at(sethi_offset), x);
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315 #else
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316 set_long_at(sethi_offset, set_data32_sethi( long_at(sethi_offset), x));
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317 #endif
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318 set_long_at(add_offset, set_data32_simm13( long_at(add_offset), x));
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319
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320 // also store the value into an oop_Relocation cell, if any
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321 CodeBlob* nm = CodeCache::find_blob(instruction_address());
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322 if (nm != NULL) {
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323 RelocIterator iter(nm, instruction_address(), next_instruction_address());
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324 oop* oop_addr = NULL;
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325 while (iter.next()) {
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326 if (iter.type() == relocInfo::oop_type) {
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327 oop_Relocation *r = iter.oop_reloc();
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328 if (oop_addr == NULL) {
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329 oop_addr = r->oop_addr();
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330 *oop_addr = (oop)x;
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331 } else {
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332 assert(oop_addr == r->oop_addr(), "must be only one set-oop here");
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333 }
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334 }
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335 }
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336 }
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337 }
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338
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339
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340 // Code for unit testing implementation of NativeMovConstReg class
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341 void NativeMovConstReg::test() {
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342 #ifdef ASSERT
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343 ResourceMark rm;
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344 CodeBuffer cb("test", 100, 100);
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345 MacroAssembler* a = new MacroAssembler(&cb);
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346 NativeMovConstReg* nm;
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347 uint idx;
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348 int offsets[] = {
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349 0x0,
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350 0x7fffffff,
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351 0x80000000,
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352 0xffffffff,
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353 0x20,
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354 4096,
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355 4097,
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356 };
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357
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358 VM_Version::allow_all();
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359
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360 a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none);
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361 a->add(I3, low10(0xaaaabbbb), I3);
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362 a->sethi(0xccccdddd, O2, true, RelocationHolder::none);
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363 a->add(O2, low10(0xccccdddd), O2);
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364
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365 nm = nativeMovConstReg_at( cb.code_begin() );
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366 nm->print();
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367
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368 nm = nativeMovConstReg_at( nm->next_instruction_address() );
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369 for (idx = 0; idx < ARRAY_SIZE(offsets); idx++) {
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370 nm->set_data( offsets[idx] );
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371 assert(nm->data() == offsets[idx], "check unit test");
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372 }
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373 nm->print();
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374
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375 VM_Version::revert();
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376 #endif
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377 }
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378 // End code for unit testing implementation of NativeMovConstReg class
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379
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380 //-------------------------------------------------------------------
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381
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382 void NativeMovConstRegPatching::verify() {
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383 NativeInstruction::verify();
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384 // Make sure code pattern is sethi/nop/add.
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385 int i0 = long_at(sethi_offset);
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386 int i1 = long_at(nop_offset);
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387 int i2 = long_at(add_offset);
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388 assert((int)nop_offset == (int)NativeMovConstReg::add_offset, "sethi size ok");
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389
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390 // Verify the pattern "sethi %hi22(imm), reg; nop; add reg, %lo10(imm), reg"
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391 // The casual reader should note that on Sparc a nop is a special case if sethi
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392 // in which the destination register is %g0.
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393 Register rd0 = inv_rd(i0);
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394 Register rd1 = inv_rd(i1);
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395 if (!(is_op2(i0, Assembler::sethi_op2) && rd0 != G0 &&
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396 is_op2(i1, Assembler::sethi_op2) && rd1 == G0 && // nop is a special case of sethi
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397 is_op3(i2, Assembler::add_op3, Assembler::arith_op) &&
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398 inv_immed(i2) && (unsigned)get_simm13(i2) < (1 << 10) &&
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399 rd0 == inv_rs1(i2) && rd0 == inv_rd(i2))) {
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400 fatal("not a set_oop");
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401 }
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402 }
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403
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404
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405 void NativeMovConstRegPatching::print() {
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406 tty->print_cr(INTPTR_FORMAT ": mov reg, " INTPTR_FORMAT, instruction_address(), data());
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407 }
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408
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409
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410 int NativeMovConstRegPatching::data() const {
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411 #ifdef _LP64
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412 return data64(addr_at(sethi_offset), long_at(add_offset));
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413 #else
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414 return data32(long_at(sethi_offset), long_at(add_offset));
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415 #endif
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416 }
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417
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418
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419 void NativeMovConstRegPatching::set_data(int x) {
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420 #ifdef _LP64
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421 set_data64_sethi(addr_at(sethi_offset), x);
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422 #else
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423 set_long_at(sethi_offset, set_data32_sethi(long_at(sethi_offset), x));
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424 #endif
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425 set_long_at(add_offset, set_data32_simm13(long_at(add_offset), x));
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426
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427 // also store the value into an oop_Relocation cell, if any
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428 CodeBlob* nm = CodeCache::find_blob(instruction_address());
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429 if (nm != NULL) {
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430 RelocIterator iter(nm, instruction_address(), next_instruction_address());
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431 oop* oop_addr = NULL;
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432 while (iter.next()) {
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433 if (iter.type() == relocInfo::oop_type) {
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434 oop_Relocation *r = iter.oop_reloc();
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435 if (oop_addr == NULL) {
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436 oop_addr = r->oop_addr();
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437 *oop_addr = (oop)x;
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438 } else {
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439 assert(oop_addr == r->oop_addr(), "must be only one set-oop here");
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440 }
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441 }
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442 }
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443 }
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444 }
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445
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446
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447 // Code for unit testing implementation of NativeMovConstRegPatching class
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448 void NativeMovConstRegPatching::test() {
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449 #ifdef ASSERT
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450 ResourceMark rm;
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|
451 CodeBuffer cb("test", 100, 100);
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452 MacroAssembler* a = new MacroAssembler(&cb);
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453 NativeMovConstRegPatching* nm;
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454 uint idx;
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|
455 int offsets[] = {
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456 0x0,
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|
457 0x7fffffff,
|
|
|
458 0x80000000,
|
|
|
459 0xffffffff,
|
|
|
460 0x20,
|
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461 4096,
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|
462 4097,
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|
463 };
|
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464
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|
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465 VM_Version::allow_all();
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466
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467 a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none);
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468 a->nop();
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|
469 a->add(I3, low10(0xaaaabbbb), I3);
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470 a->sethi(0xccccdddd, O2, true, RelocationHolder::none);
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|
471 a->nop();
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|
|
472 a->add(O2, low10(0xccccdddd), O2);
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|
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473
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|
474 nm = nativeMovConstRegPatching_at( cb.code_begin() );
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|
|
475 nm->print();
|
|
|
476
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|
|
477 nm = nativeMovConstRegPatching_at( nm->next_instruction_address() );
|
|
|
478 for (idx = 0; idx < ARRAY_SIZE(offsets); idx++) {
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|
|
479 nm->set_data( offsets[idx] );
|
|
|
480 assert(nm->data() == offsets[idx], "check unit test");
|
|
|
481 }
|
|
|
482 nm->print();
|
|
|
483
|
|
|
484 VM_Version::revert();
|
|
|
485 #endif // ASSERT
|
|
|
486 }
|
|
|
487 // End code for unit testing implementation of NativeMovConstRegPatching class
|
|
|
488
|
|
|
489
|
|
|
490 //-------------------------------------------------------------------
|
|
|
491
|
|
|
492
|
|
|
493 void NativeMovRegMem::copy_instruction_to(address new_instruction_address) {
|
|
|
494 Untested("copy_instruction_to");
|
|
|
495 int instruction_size = next_instruction_address() - instruction_address();
|
|
|
496 for (int i = 0; i < instruction_size; i += BytesPerInstWord) {
|
|
|
497 *(int*)(new_instruction_address + i) = *(int*)(address(this) + i);
|
|
|
498 }
|
|
|
499 }
|
|
|
500
|
|
|
501
|
|
|
502 void NativeMovRegMem::verify() {
|
|
|
503 NativeInstruction::verify();
|
|
|
504 // make sure code pattern is actually a "ld" or "st" of some sort.
|
|
|
505 int i0 = long_at(0);
|
|
|
506 int op3 = inv_op3(i0);
|
|
|
507
|
|
|
508 assert((int)add_offset == NativeMovConstReg::add_offset, "sethi size ok");
|
|
|
509
|
|
|
510 if (!(is_op(i0, Assembler::ldst_op) &&
|
|
|
511 inv_immed(i0) &&
|
|
|
512 0 != (op3 < op3_ldst_int_limit
|
|
|
513 ? (1 << op3 ) & (op3_mask_ld | op3_mask_st)
|
|
|
514 : (1 << (op3 - op3_ldst_int_limit)) & (op3_mask_ldf | op3_mask_stf))))
|
|
|
515 {
|
|
|
516 int i1 = long_at(ldst_offset);
|
|
|
517 Register rd = inv_rd(i0);
|
|
|
518
|
|
|
519 op3 = inv_op3(i1);
|
|
|
520 if (!is_op(i1, Assembler::ldst_op) && rd == inv_rs2(i1) &&
|
|
|
521 0 != (op3 < op3_ldst_int_limit
|
|
|
522 ? (1 << op3 ) & (op3_mask_ld | op3_mask_st)
|
|
|
523 : (1 << (op3 - op3_ldst_int_limit)) & (op3_mask_ldf | op3_mask_stf))) {
|
|
|
524 fatal("not a ld* or st* op");
|
|
|
525 }
|
|
|
526 }
|
|
|
527 }
|
|
|
528
|
|
|
529
|
|
|
530 void NativeMovRegMem::print() {
|
|
|
531 if (is_immediate()) {
|
|
|
532 tty->print_cr(INTPTR_FORMAT ": mov reg, [reg + %x]", instruction_address(), offset());
|
|
|
533 } else {
|
|
|
534 tty->print_cr(INTPTR_FORMAT ": mov reg, [reg + reg]", instruction_address());
|
|
|
535 }
|
|
|
536 }
|
|
|
537
|
|
|
538
|
|
|
539 // Code for unit testing implementation of NativeMovRegMem class
|
|
|
540 void NativeMovRegMem::test() {
|
|
|
541 #ifdef ASSERT
|
|
|
542 ResourceMark rm;
|
|
|
543 CodeBuffer cb("test", 1000, 1000);
|
|
|
544 MacroAssembler* a = new MacroAssembler(&cb);
|
|
|
545 NativeMovRegMem* nm;
|
|
|
546 uint idx = 0;
|
|
|
547 uint idx1;
|
|
|
548 int offsets[] = {
|
|
|
549 0x0,
|
|
|
550 0xffffffff,
|
|
|
551 0x7fffffff,
|
|
|
552 0x80000000,
|
|
|
553 4096,
|
|
|
554 4097,
|
|
|
555 0x20,
|
|
|
556 0x4000,
|
|
|
557 };
|
|
|
558
|
|
|
559 VM_Version::allow_all();
|
|
|
560
|
|
|
561 a->ldsw( G5, low10(0xffffffff), G4 ); idx++;
|
|
|
562 a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->add(I3, low10(0xaaaabbbb), I3);
|
|
|
563 a->ldsw( G5, I3, G4 ); idx++;
|
|
|
564 a->ldsb( G5, low10(0xffffffff), G4 ); idx++;
|
|
|
565 a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->add(I3, low10(0xaaaabbbb), I3);
|
|
|
566 a->ldsb( G5, I3, G4 ); idx++;
|
|
|
567 a->ldsh( G5, low10(0xffffffff), G4 ); idx++;
|
|
|
568 a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->add(I3, low10(0xaaaabbbb), I3);
|
|
|
569 a->ldsh( G5, I3, G4 ); idx++;
|
|
|
570 a->lduw( G5, low10(0xffffffff), G4 ); idx++;
|
|
|
571 a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->add(I3, low10(0xaaaabbbb), I3);
|
|
|
572 a->lduw( G5, I3, G4 ); idx++;
|
|
|
573 a->ldub( G5, low10(0xffffffff), G4 ); idx++;
|
|
|
574 a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->add(I3, low10(0xaaaabbbb), I3);
|
|
|
575 a->ldub( G5, I3, G4 ); idx++;
|
|
|
576 a->lduh( G5, low10(0xffffffff), G4 ); idx++;
|
|
|
577 a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->add(I3, low10(0xaaaabbbb), I3);
|
|
|
578 a->lduh( G5, I3, G4 ); idx++;
|
|
|
579 a->ldx( G5, low10(0xffffffff), G4 ); idx++;
|
|
|
580 a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->add(I3, low10(0xaaaabbbb), I3);
|
|
|
581 a->ldx( G5, I3, G4 ); idx++;
|
|
|
582 a->ldd( G5, low10(0xffffffff), G4 ); idx++;
|
|
|
583 a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->add(I3, low10(0xaaaabbbb), I3);
|
|
|
584 a->ldd( G5, I3, G4 ); idx++;
|
|
|
585 a->ldf( FloatRegisterImpl::D, O2, -1, F14 ); idx++;
|
|
|
586 a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->add(I3, low10(0xaaaabbbb), I3);
|
|
|
587 a->ldf( FloatRegisterImpl::S, O0, I3, F15 ); idx++;
|
|
|
588
|
|
|
589 a->stw( G5, G4, low10(0xffffffff) ); idx++;
|
|
|
590 a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->add(I3, low10(0xaaaabbbb), I3);
|
|
|
591 a->stw( G5, G4, I3 ); idx++;
|
|
|
592 a->stb( G5, G4, low10(0xffffffff) ); idx++;
|
|
|
593 a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->add(I3, low10(0xaaaabbbb), I3);
|
|
|
594 a->stb( G5, G4, I3 ); idx++;
|
|
|
595 a->sth( G5, G4, low10(0xffffffff) ); idx++;
|
|
|
596 a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->add(I3, low10(0xaaaabbbb), I3);
|
|
|
597 a->sth( G5, G4, I3 ); idx++;
|
|
|
598 a->stx( G5, G4, low10(0xffffffff) ); idx++;
|
|
|
599 a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->add(I3, low10(0xaaaabbbb), I3);
|
|
|
600 a->stx( G5, G4, I3 ); idx++;
|
|
|
601 a->std( G5, G4, low10(0xffffffff) ); idx++;
|
|
|
602 a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->add(I3, low10(0xaaaabbbb), I3);
|
|
|
603 a->std( G5, G4, I3 ); idx++;
|
|
|
604 a->stf( FloatRegisterImpl::S, F18, O2, -1 ); idx++;
|
|
|
605 a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->add(I3, low10(0xaaaabbbb), I3);
|
|
|
606 a->stf( FloatRegisterImpl::S, F15, O0, I3 ); idx++;
|
|
|
607
|
|
|
608 nm = nativeMovRegMem_at( cb.code_begin() );
|
|
|
609 nm->print();
|
|
|
610 nm->set_offset( low10(0) );
|
|
|
611 nm->print();
|
|
|
612 nm->add_offset_in_bytes( low10(0xbb) * wordSize );
|
|
|
613 nm->print();
|
|
|
614
|
|
|
615 while (--idx) {
|
|
|
616 nm = nativeMovRegMem_at( nm->next_instruction_address() );
|
|
|
617 nm->print();
|
|
|
618 for (idx1 = 0; idx1 < ARRAY_SIZE(offsets); idx1++) {
|
|
|
619 nm->set_offset( nm->is_immediate() ? low10(offsets[idx1]) : offsets[idx1] );
|
|
|
620 assert(nm->offset() == (nm->is_immediate() ? low10(offsets[idx1]) : offsets[idx1]),
|
|
|
621 "check unit test");
|
|
|
622 nm->print();
|
|
|
623 }
|
|
|
624 nm->add_offset_in_bytes( low10(0xbb) * wordSize );
|
|
|
625 nm->print();
|
|
|
626 }
|
|
|
627
|
|
|
628 VM_Version::revert();
|
|
|
629 #endif // ASSERT
|
|
|
630 }
|
|
|
631
|
|
|
632 // End code for unit testing implementation of NativeMovRegMem class
|
|
|
633
|
|
|
634 //--------------------------------------------------------------------------------
|
|
|
635
|
|
|
636
|
|
|
637 void NativeMovRegMemPatching::copy_instruction_to(address new_instruction_address) {
|
|
|
638 Untested("copy_instruction_to");
|
|
|
639 int instruction_size = next_instruction_address() - instruction_address();
|
|
|
640 for (int i = 0; i < instruction_size; i += wordSize) {
|
|
|
641 *(long*)(new_instruction_address + i) = *(long*)(address(this) + i);
|
|
|
642 }
|
|
|
643 }
|
|
|
644
|
|
|
645
|
|
|
646 void NativeMovRegMemPatching::verify() {
|
|
|
647 NativeInstruction::verify();
|
|
|
648 // make sure code pattern is actually a "ld" or "st" of some sort.
|
|
|
649 int i0 = long_at(0);
|
|
|
650 int op3 = inv_op3(i0);
|
|
|
651
|
|
|
652 assert((int)nop_offset == (int)NativeMovConstReg::add_offset, "sethi size ok");
|
|
|
653
|
|
|
654 if (!(is_op(i0, Assembler::ldst_op) &&
|
|
|
655 inv_immed(i0) &&
|
|
|
656 0 != (op3 < op3_ldst_int_limit
|
|
|
657 ? (1 << op3 ) & (op3_mask_ld | op3_mask_st)
|
|
|
658 : (1 << (op3 - op3_ldst_int_limit)) & (op3_mask_ldf | op3_mask_stf)))) {
|
|
|
659 int i1 = long_at(ldst_offset);
|
|
|
660 Register rd = inv_rd(i0);
|
|
|
661
|
|
|
662 op3 = inv_op3(i1);
|
|
|
663 if (!is_op(i1, Assembler::ldst_op) && rd == inv_rs2(i1) &&
|
|
|
664 0 != (op3 < op3_ldst_int_limit
|
|
|
665 ? (1 << op3 ) & (op3_mask_ld | op3_mask_st)
|
|
|
666 : (1 << (op3 - op3_ldst_int_limit)) & (op3_mask_ldf | op3_mask_stf))) {
|
|
|
667 fatal("not a ld* or st* op");
|
|
|
668 }
|
|
|
669 }
|
|
|
670 }
|
|
|
671
|
|
|
672
|
|
|
673 void NativeMovRegMemPatching::print() {
|
|
|
674 if (is_immediate()) {
|
|
|
675 tty->print_cr(INTPTR_FORMAT ": mov reg, [reg + %x]", instruction_address(), offset());
|
|
|
676 } else {
|
|
|
677 tty->print_cr(INTPTR_FORMAT ": mov reg, [reg + reg]", instruction_address());
|
|
|
678 }
|
|
|
679 }
|
|
|
680
|
|
|
681
|
|
|
682 // Code for unit testing implementation of NativeMovRegMemPatching class
|
|
|
683 void NativeMovRegMemPatching::test() {
|
|
|
684 #ifdef ASSERT
|
|
|
685 ResourceMark rm;
|
|
|
686 CodeBuffer cb("test", 1000, 1000);
|
|
|
687 MacroAssembler* a = new MacroAssembler(&cb);
|
|
|
688 NativeMovRegMemPatching* nm;
|
|
|
689 uint idx = 0;
|
|
|
690 uint idx1;
|
|
|
691 int offsets[] = {
|
|
|
692 0x0,
|
|
|
693 0xffffffff,
|
|
|
694 0x7fffffff,
|
|
|
695 0x80000000,
|
|
|
696 4096,
|
|
|
697 4097,
|
|
|
698 0x20,
|
|
|
699 0x4000,
|
|
|
700 };
|
|
|
701
|
|
|
702 VM_Version::allow_all();
|
|
|
703
|
|
|
704 a->ldsw( G5, low10(0xffffffff), G4 ); idx++;
|
|
|
705 a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->nop(); a->add(I3, low10(0xaaaabbbb), I3);
|
|
|
706 a->ldsw( G5, I3, G4 ); idx++;
|
|
|
707 a->ldsb( G5, low10(0xffffffff), G4 ); idx++;
|
|
|
708 a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->nop(); a->add(I3, low10(0xaaaabbbb), I3);
|
|
|
709 a->ldsb( G5, I3, G4 ); idx++;
|
|
|
710 a->ldsh( G5, low10(0xffffffff), G4 ); idx++;
|
|
|
711 a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->nop(); a->add(I3, low10(0xaaaabbbb), I3);
|
|
|
712 a->ldsh( G5, I3, G4 ); idx++;
|
|
|
713 a->lduw( G5, low10(0xffffffff), G4 ); idx++;
|
|
|
714 a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->nop(); a->add(I3, low10(0xaaaabbbb), I3);
|
|
|
715 a->lduw( G5, I3, G4 ); idx++;
|
|
|
716 a->ldub( G5, low10(0xffffffff), G4 ); idx++;
|
|
|
717 a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->nop(); a->add(I3, low10(0xaaaabbbb), I3);
|
|
|
718 a->ldub( G5, I3, G4 ); idx++;
|
|
|
719 a->lduh( G5, low10(0xffffffff), G4 ); idx++;
|
|
|
720 a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->nop(); a->add(I3, low10(0xaaaabbbb), I3);
|
|
|
721 a->lduh( G5, I3, G4 ); idx++;
|
|
|
722 a->ldx( G5, low10(0xffffffff), G4 ); idx++;
|
|
|
723 a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->nop(); a->add(I3, low10(0xaaaabbbb), I3);
|
|
|
724 a->ldx( G5, I3, G4 ); idx++;
|
|
|
725 a->ldd( G5, low10(0xffffffff), G4 ); idx++;
|
|
|
726 a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->nop(); a->add(I3, low10(0xaaaabbbb), I3);
|
|
|
727 a->ldd( G5, I3, G4 ); idx++;
|
|
|
728 a->ldf( FloatRegisterImpl::D, O2, -1, F14 ); idx++;
|
|
|
729 a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->nop(); a->add(I3, low10(0xaaaabbbb), I3);
|
|
|
730 a->ldf( FloatRegisterImpl::S, O0, I3, F15 ); idx++;
|
|
|
731
|
|
|
732 a->stw( G5, G4, low10(0xffffffff) ); idx++;
|
|
|
733 a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->nop(); a->add(I3, low10(0xaaaabbbb), I3);
|
|
|
734 a->stw( G5, G4, I3 ); idx++;
|
|
|
735 a->stb( G5, G4, low10(0xffffffff) ); idx++;
|
|
|
736 a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->nop(); a->add(I3, low10(0xaaaabbbb), I3);
|
|
|
737 a->stb( G5, G4, I3 ); idx++;
|
|
|
738 a->sth( G5, G4, low10(0xffffffff) ); idx++;
|
|
|
739 a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->nop(); a->add(I3, low10(0xaaaabbbb), I3);
|
|
|
740 a->sth( G5, G4, I3 ); idx++;
|
|
|
741 a->stx( G5, G4, low10(0xffffffff) ); idx++;
|
|
|
742 a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->nop(); a->add(I3, low10(0xaaaabbbb), I3);
|
|
|
743 a->stx( G5, G4, I3 ); idx++;
|
|
|
744 a->std( G5, G4, low10(0xffffffff) ); idx++;
|
|
|
745 a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->nop(); a->add(I3, low10(0xaaaabbbb), I3);
|
|
|
746 a->std( G5, G4, I3 ); idx++;
|
|
|
747 a->stf( FloatRegisterImpl::S, F18, O2, -1 ); idx++;
|
|
|
748 a->sethi(0xaaaabbbb, I3, true, RelocationHolder::none); a->nop(); a->add(I3, low10(0xaaaabbbb), I3);
|
|
|
749 a->stf( FloatRegisterImpl::S, F15, O0, I3 ); idx++;
|
|
|
750
|
|
|
751 nm = nativeMovRegMemPatching_at( cb.code_begin() );
|
|
|
752 nm->print();
|
|
|
753 nm->set_offset( low10(0) );
|
|
|
754 nm->print();
|
|
|
755 nm->add_offset_in_bytes( low10(0xbb) * wordSize );
|
|
|
756 nm->print();
|
|
|
757
|
|
|
758 while (--idx) {
|
|
|
759 nm = nativeMovRegMemPatching_at( nm->next_instruction_address() );
|
|
|
760 nm->print();
|
|
|
761 for (idx1 = 0; idx1 < ARRAY_SIZE(offsets); idx1++) {
|
|
|
762 nm->set_offset( nm->is_immediate() ? low10(offsets[idx1]) : offsets[idx1] );
|
|
|
763 assert(nm->offset() == (nm->is_immediate() ? low10(offsets[idx1]) : offsets[idx1]),
|
|
|
764 "check unit test");
|
|
|
765 nm->print();
|
|
|
766 }
|
|
|
767 nm->add_offset_in_bytes( low10(0xbb) * wordSize );
|
|
|
768 nm->print();
|
|
|
769 }
|
|
|
770
|
|
|
771 VM_Version::revert();
|
|
|
772 #endif // ASSERT
|
|
|
773 }
|
|
|
774 // End code for unit testing implementation of NativeMovRegMemPatching class
|
|
|
775
|
|
|
776
|
|
|
777 //--------------------------------------------------------------------------------
|
|
|
778
|
|
|
779
|
|
|
780 void NativeJump::verify() {
|
|
|
781 NativeInstruction::verify();
|
|
|
782 int i0 = long_at(sethi_offset);
|
|
|
783 int i1 = long_at(jmpl_offset);
|
|
|
784 assert((int)jmpl_offset == (int)NativeMovConstReg::add_offset, "sethi size ok");
|
|
|
785 // verify the pattern "sethi %hi22(imm), treg ; jmpl treg, %lo10(imm), lreg"
|
|
|
786 Register rd = inv_rd(i0);
|
|
|
787 #ifndef _LP64
|
|
|
788 if (!(is_op2(i0, Assembler::sethi_op2) && rd != G0 &&
|
|
|
789 (is_op3(i1, Assembler::jmpl_op3, Assembler::arith_op) ||
|
|
|
790 (TraceJumps && is_op3(i1, Assembler::add_op3, Assembler::arith_op))) &&
|
|
|
791 inv_immed(i1) && (unsigned)get_simm13(i1) < (1 << 10) &&
|
|
|
792 rd == inv_rs1(i1))) {
|
|
|
793 fatal("not a jump_to instruction");
|
|
|
794 }
|
|
|
795 #else
|
|
|
796 // In LP64, the jump instruction location varies for non relocatable
|
|
|
797 // jumps, for example is could be sethi, xor, jmp instead of the
|
|
|
798 // 7 instructions for sethi. So let's check sethi only.
|
|
|
799 if (!is_op2(i0, Assembler::sethi_op2) && rd != G0 ) {
|
|
|
800 fatal("not a jump_to instruction");
|
|
|
801 }
|
|
|
802 #endif
|
|
|
803 }
|
|
|
804
|
|
|
805
|
|
|
806 void NativeJump::print() {
|
|
|
807 tty->print_cr(INTPTR_FORMAT ": jmpl reg, " INTPTR_FORMAT, instruction_address(), jump_destination());
|
|
|
808 }
|
|
|
809
|
|
|
810
|
|
|
811 // Code for unit testing implementation of NativeJump class
|
|
|
812 void NativeJump::test() {
|
|
|
813 #ifdef ASSERT
|
|
|
814 ResourceMark rm;
|
|
|
815 CodeBuffer cb("test", 100, 100);
|
|
|
816 MacroAssembler* a = new MacroAssembler(&cb);
|
|
|
817 NativeJump* nj;
|
|
|
818 uint idx;
|
|
|
819 int offsets[] = {
|
|
|
820 0x0,
|
|
|
821 0xffffffff,
|
|
|
822 0x7fffffff,
|
|
|
823 0x80000000,
|
|
|
824 4096,
|
|
|
825 4097,
|
|
|
826 0x20,
|
|
|
827 0x4000,
|
|
|
828 };
|
|
|
829
|
|
|
830 VM_Version::allow_all();
|
|
|
831
|
|
|
832 a->sethi(0x7fffbbbb, I3, true, RelocationHolder::none);
|
|
|
833 a->jmpl(I3, low10(0x7fffbbbb), G0, RelocationHolder::none);
|
|
|
834 a->delayed()->nop();
|
|
|
835 a->sethi(0x7fffbbbb, I3, true, RelocationHolder::none);
|
|
|
836 a->jmpl(I3, low10(0x7fffbbbb), L3, RelocationHolder::none);
|
|
|
837 a->delayed()->nop();
|
|
|
838
|
|
|
839 nj = nativeJump_at( cb.code_begin() );
|
|
|
840 nj->print();
|
|
|
841
|
|
|
842 nj = nativeJump_at( nj->next_instruction_address() );
|
|
|
843 for (idx = 0; idx < ARRAY_SIZE(offsets); idx++) {
|
|
|
844 nj->set_jump_destination( nj->instruction_address() + offsets[idx] );
|
|
|
845 assert(nj->jump_destination() == (nj->instruction_address() + offsets[idx]), "check unit test");
|
|
|
846 nj->print();
|
|
|
847 }
|
|
|
848
|
|
|
849 VM_Version::revert();
|
|
|
850 #endif // ASSERT
|
|
|
851 }
|
|
|
852 // End code for unit testing implementation of NativeJump class
|
|
|
853
|
|
|
854
|
|
|
855 void NativeJump::insert(address code_pos, address entry) {
|
|
|
856 Unimplemented();
|
|
|
857 }
|
|
|
858
|
|
|
859 // MT safe inserting of a jump over an unknown instruction sequence (used by nmethod::makeZombie)
|
|
|
860 // The problem: jump_to <dest> is a 3-word instruction (including its delay slot).
|
|
|
861 // Atomic write can be only with 1 word.
|
|
|
862 void NativeJump::patch_verified_entry(address entry, address verified_entry, address dest) {
|
|
|
863 // Here's one way to do it: Pre-allocate a three-word jump sequence somewhere
|
|
|
864 // in the header of the nmethod, within a short branch's span of the patch point.
|
|
|
865 // Set up the jump sequence using NativeJump::insert, and then use an annulled
|
|
|
866 // unconditional branch at the target site (an atomic 1-word update).
|
|
|
867 // Limitations: You can only patch nmethods, with any given nmethod patched at
|
|
|
868 // most once, and the patch must be in the nmethod's header.
|
|
|
869 // It's messy, but you can ask the CodeCache for the nmethod containing the
|
|
|
870 // target address.
|
|
|
871
|
|
|
872 // %%%%% For now, do something MT-stupid:
|
|
|
873 ResourceMark rm;
|
|
|
874 int code_size = 1 * BytesPerInstWord;
|
|
|
875 CodeBuffer cb(verified_entry, code_size + 1);
|
|
|
876 MacroAssembler* a = new MacroAssembler(&cb);
|
|
|
877 if (VM_Version::v9_instructions_work()) {
|
|
|
878 a->ldsw(G0, 0, O7); // "ld" must agree with code in the signal handler
|
|
|
879 } else {
|
|
|
880 a->lduw(G0, 0, O7); // "ld" must agree with code in the signal handler
|
|
|
881 }
|
|
|
882 ICache::invalidate_range(verified_entry, code_size);
|
|
|
883 }
|
|
|
884
|
|
|
885
|
|
|
886 void NativeIllegalInstruction::insert(address code_pos) {
|
|
|
887 NativeIllegalInstruction* nii = (NativeIllegalInstruction*) nativeInstruction_at(code_pos);
|
|
|
888 nii->set_long_at(0, illegal_instruction());
|
|
|
889 }
|
|
|
890
|
|
|
891 static int illegal_instruction_bits = 0;
|
|
|
892
|
|
|
893 int NativeInstruction::illegal_instruction() {
|
|
|
894 if (illegal_instruction_bits == 0) {
|
|
|
895 ResourceMark rm;
|
|
|
896 char buf[40];
|
|
|
897 CodeBuffer cbuf((address)&buf[0], 20);
|
|
|
898 MacroAssembler* a = new MacroAssembler(&cbuf);
|
|
|
899 address ia = a->pc();
|
|
|
900 a->trap(ST_RESERVED_FOR_USER_0 + 1);
|
|
|
901 int bits = *(int*)ia;
|
|
|
902 assert(is_op3(bits, Assembler::trap_op3, Assembler::arith_op), "bad instruction");
|
|
|
903 illegal_instruction_bits = bits;
|
|
|
904 assert(illegal_instruction_bits != 0, "oops");
|
|
|
905 }
|
|
|
906 return illegal_instruction_bits;
|
|
|
907 }
|
|
|
908
|
|
|
909 static int ic_miss_trap_bits = 0;
|
|
|
910
|
|
|
911 bool NativeInstruction::is_ic_miss_trap() {
|
|
|
912 if (ic_miss_trap_bits == 0) {
|
|
|
913 ResourceMark rm;
|
|
|
914 char buf[40];
|
|
|
915 CodeBuffer cbuf((address)&buf[0], 20);
|
|
|
916 MacroAssembler* a = new MacroAssembler(&cbuf);
|
|
|
917 address ia = a->pc();
|
|
|
918 a->trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0 + 2);
|
|
|
919 int bits = *(int*)ia;
|
|
|
920 assert(is_op3(bits, Assembler::trap_op3, Assembler::arith_op), "bad instruction");
|
|
|
921 ic_miss_trap_bits = bits;
|
|
|
922 assert(ic_miss_trap_bits != 0, "oops");
|
|
|
923 }
|
|
|
924 return long_at(0) == ic_miss_trap_bits;
|
|
|
925 }
|
|
|
926
|
|
|
927
|
|
|
928 bool NativeInstruction::is_illegal() {
|
|
|
929 if (illegal_instruction_bits == 0) {
|
|
|
930 return false;
|
|
|
931 }
|
|
|
932 return long_at(0) == illegal_instruction_bits;
|
|
|
933 }
|
|
|
934
|
|
|
935
|
|
|
936 void NativeGeneralJump::verify() {
|
|
|
937 assert(((NativeInstruction *)this)->is_jump() ||
|
|
|
938 ((NativeInstruction *)this)->is_cond_jump(), "not a general jump instruction");
|
|
|
939 }
|
|
|
940
|
|
|
941
|
|
|
942 void NativeGeneralJump::insert_unconditional(address code_pos, address entry) {
|
|
|
943 Assembler::Condition condition = Assembler::always;
|
|
|
944 int x = Assembler::op2(Assembler::br_op2) | Assembler::annul(false) |
|
|
|
945 Assembler::cond(condition) | Assembler::wdisp((intptr_t)entry, (intptr_t)code_pos, 22);
|
|
|
946 NativeGeneralJump* ni = (NativeGeneralJump*) nativeInstruction_at(code_pos);
|
|
|
947 ni->set_long_at(0, x);
|
|
|
948 }
|
|
|
949
|
|
|
950
|
|
|
951 // MT-safe patching of a jmp instruction (and following word).
|
|
|
952 // First patches the second word, and then atomicly replaces
|
|
|
953 // the first word with the first new instruction word.
|
|
|
954 // Other processors might briefly see the old first word
|
|
|
955 // followed by the new second word. This is OK if the old
|
|
|
956 // second word is harmless, and the new second word may be
|
|
|
957 // harmlessly executed in the delay slot of the call.
|
|
|
958 void NativeGeneralJump::replace_mt_safe(address instr_addr, address code_buffer) {
|
|
|
959 assert(Patching_lock->is_locked() ||
|
|
|
960 SafepointSynchronize::is_at_safepoint(), "concurrent code patching");
|
|
|
961 assert (instr_addr != NULL, "illegal address for code patching");
|
|
|
962 NativeGeneralJump* h_jump = nativeGeneralJump_at (instr_addr); // checking that it is a call
|
|
|
963 assert(NativeGeneralJump::instruction_size == 8, "wrong instruction size; must be 8");
|
|
|
964 int i0 = ((int*)code_buffer)[0];
|
|
|
965 int i1 = ((int*)code_buffer)[1];
|
|
|
966 int* contention_addr = (int*) h_jump->addr_at(1*BytesPerInstWord);
|
|
|
967 assert(inv_op(*contention_addr) == Assembler::arith_op ||
|
|
|
968 *contention_addr == nop_instruction() || !VM_Version::v9_instructions_work(),
|
|
|
969 "must not interfere with original call");
|
|
|
970 // The set_long_at calls do the ICacheInvalidate so we just need to do them in reverse order
|
|
|
971 h_jump->set_long_at(1*BytesPerInstWord, i1);
|
|
|
972 h_jump->set_long_at(0*BytesPerInstWord, i0);
|
|
|
973 // NOTE: It is possible that another thread T will execute
|
|
|
974 // only the second patched word.
|
|
|
975 // In other words, since the original instruction is this
|
|
|
976 // jmp patching_stub; nop (NativeGeneralJump)
|
|
|
977 // and the new sequence from the buffer is this:
|
|
|
978 // sethi %hi(K), %r; add %r, %lo(K), %r (NativeMovConstReg)
|
|
|
979 // what T will execute is this:
|
|
|
980 // jmp patching_stub; add %r, %lo(K), %r
|
|
|
981 // thereby putting garbage into %r before calling the patching stub.
|
|
|
982 // This is OK, because the patching stub ignores the value of %r.
|
|
|
983
|
|
|
984 // Make sure the first-patched instruction, which may co-exist
|
|
|
985 // briefly with the call, will do something harmless.
|
|
|
986 assert(inv_op(*contention_addr) == Assembler::arith_op ||
|
|
|
987 *contention_addr == nop_instruction() || !VM_Version::v9_instructions_work(),
|
|
|
988 "must not interfere with original call");
|
|
|
989 }
|
