annotate src/share/vm/opto/mulnode.cpp @ 0:a61af66fc99e jdk7-b24

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author duke
date Sat, 01 Dec 2007 00:00:00 +0000
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children f3de1255b035
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1 /*
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2 * Copyright 1997-2006 Sun Microsystems, Inc. All Rights Reserved.
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3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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4 *
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5 * This code is free software; you can redistribute it and/or modify it
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6 * under the terms of the GNU General Public License version 2 only, as
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7 * published by the Free Software Foundation.
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8 *
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9 * This code is distributed in the hope that it will be useful, but WITHOUT
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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12 * version 2 for more details (a copy is included in the LICENSE file that
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13 * accompanied this code).
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14 *
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15 * You should have received a copy of the GNU General Public License version
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16 * 2 along with this work; if not, write to the Free Software Foundation,
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17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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18 *
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19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
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20 * CA 95054 USA or visit www.sun.com if you need additional information or
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21 * have any questions.
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22 *
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23 */
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24
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25 // Portions of code courtesy of Clifford Click
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26
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27 #include "incls/_precompiled.incl"
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28 #include "incls/_mulnode.cpp.incl"
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29
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30
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31 //=============================================================================
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32 //------------------------------hash-------------------------------------------
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33 // Hash function over MulNodes. Needs to be commutative; i.e., I swap
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34 // (commute) inputs to MulNodes willy-nilly so the hash function must return
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35 // the same value in the presence of edge swapping.
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36 uint MulNode::hash() const {
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37 return (uintptr_t)in(1) + (uintptr_t)in(2) + Opcode();
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38 }
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39
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40 //------------------------------Identity---------------------------------------
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41 // Multiplying a one preserves the other argument
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42 Node *MulNode::Identity( PhaseTransform *phase ) {
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43 register const Type *one = mul_id(); // The multiplicative identity
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44 if( phase->type( in(1) )->higher_equal( one ) ) return in(2);
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45 if( phase->type( in(2) )->higher_equal( one ) ) return in(1);
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46
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47 return this;
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48 }
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49
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50 //------------------------------Ideal------------------------------------------
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51 // We also canonicalize the Node, moving constants to the right input,
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52 // and flatten expressions (so that 1+x+2 becomes x+3).
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53 Node *MulNode::Ideal(PhaseGVN *phase, bool can_reshape) {
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54 const Type *t1 = phase->type( in(1) );
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55 const Type *t2 = phase->type( in(2) );
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56 Node *progress = NULL; // Progress flag
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57 // We are OK if right is a constant, or right is a load and
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58 // left is a non-constant.
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59 if( !(t2->singleton() ||
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60 (in(2)->is_Load() && !(t1->singleton() || in(1)->is_Load())) ) ) {
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61 if( t1->singleton() || // Left input is a constant?
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62 // Otherwise, sort inputs (commutativity) to help value numbering.
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63 (in(1)->_idx > in(2)->_idx) ) {
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64 swap_edges(1, 2);
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65 const Type *t = t1;
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66 t1 = t2;
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67 t2 = t;
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68 progress = this; // Made progress
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69 }
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70 }
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71
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72 // If the right input is a constant, and the left input is a product of a
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73 // constant, flatten the expression tree.
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74 uint op = Opcode();
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75 if( t2->singleton() && // Right input is a constant?
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76 op != Op_MulF && // Float & double cannot reassociate
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77 op != Op_MulD ) {
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78 if( t2 == Type::TOP ) return NULL;
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79 Node *mul1 = in(1);
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80 #ifdef ASSERT
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81 // Check for dead loop
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82 int op1 = mul1->Opcode();
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83 if( phase->eqv( mul1, this ) || phase->eqv( in(2), this ) ||
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84 ( op1 == mul_opcode() || op1 == add_opcode() ) &&
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85 ( phase->eqv( mul1->in(1), this ) || phase->eqv( mul1->in(2), this ) ||
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86 phase->eqv( mul1->in(1), mul1 ) || phase->eqv( mul1->in(2), mul1 ) ) )
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87 assert(false, "dead loop in MulNode::Ideal");
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88 #endif
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89
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90 if( mul1->Opcode() == mul_opcode() ) { // Left input is a multiply?
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91 // Mul of a constant?
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92 const Type *t12 = phase->type( mul1->in(2) );
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93 if( t12->singleton() && t12 != Type::TOP) { // Left input is an add of a constant?
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94 // Compute new constant; check for overflow
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95 const Type *tcon01 = mul1->as_Mul()->mul_ring(t2,t12);
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96 if( tcon01->singleton() ) {
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97 // The Mul of the flattened expression
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98 set_req(1, mul1->in(1));
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99 set_req(2, phase->makecon( tcon01 ));
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100 t2 = tcon01;
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101 progress = this; // Made progress
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102 }
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103 }
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104 }
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105 // If the right input is a constant, and the left input is an add of a
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106 // constant, flatten the tree: (X+con1)*con0 ==> X*con0 + con1*con0
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107 const Node *add1 = in(1);
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108 if( add1->Opcode() == add_opcode() ) { // Left input is an add?
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109 // Add of a constant?
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110 const Type *t12 = phase->type( add1->in(2) );
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111 if( t12->singleton() && t12 != Type::TOP ) { // Left input is an add of a constant?
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112 assert( add1->in(1) != add1, "dead loop in MulNode::Ideal" );
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113 // Compute new constant; check for overflow
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114 const Type *tcon01 = mul_ring(t2,t12);
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115 if( tcon01->singleton() ) {
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116
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117 // Convert (X+con1)*con0 into X*con0
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118 Node *mul = clone(); // mul = ()*con0
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119 mul->set_req(1,add1->in(1)); // mul = X*con0
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120 mul = phase->transform(mul);
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121
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122 Node *add2 = add1->clone();
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123 add2->set_req(1, mul); // X*con0 + con0*con1
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124 add2->set_req(2, phase->makecon(tcon01) );
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125 progress = add2;
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126 }
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127 }
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128 } // End of is left input an add
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129 } // End of is right input a Mul
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130
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131 return progress;
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132 }
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133
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134 //------------------------------Value-----------------------------------------
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135 const Type *MulNode::Value( PhaseTransform *phase ) const {
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136 const Type *t1 = phase->type( in(1) );
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137 const Type *t2 = phase->type( in(2) );
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138 // Either input is TOP ==> the result is TOP
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139 if( t1 == Type::TOP ) return Type::TOP;
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140 if( t2 == Type::TOP ) return Type::TOP;
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141
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142 // Either input is ZERO ==> the result is ZERO.
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143 // Not valid for floats or doubles since +0.0 * -0.0 --> +0.0
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144 int op = Opcode();
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145 if( op == Op_MulI || op == Op_AndI || op == Op_MulL || op == Op_AndL ) {
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146 const Type *zero = add_id(); // The multiplicative zero
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147 if( t1->higher_equal( zero ) ) return zero;
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148 if( t2->higher_equal( zero ) ) return zero;
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149 }
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150
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151 // Either input is BOTTOM ==> the result is the local BOTTOM
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152 if( t1 == Type::BOTTOM || t2 == Type::BOTTOM )
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153 return bottom_type();
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154
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155 return mul_ring(t1,t2); // Local flavor of type multiplication
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156 }
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157
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158
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159 //=============================================================================
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160 //------------------------------Ideal------------------------------------------
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161 // Check for power-of-2 multiply, then try the regular MulNode::Ideal
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162 Node *MulINode::Ideal(PhaseGVN *phase, bool can_reshape) {
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163 // Swap constant to right
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164 jint con;
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165 if ((con = in(1)->find_int_con(0)) != 0) {
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166 swap_edges(1, 2);
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167 // Finish rest of method to use info in 'con'
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168 } else if ((con = in(2)->find_int_con(0)) == 0) {
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169 return MulNode::Ideal(phase, can_reshape);
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170 }
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171
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172 // Now we have a constant Node on the right and the constant in con
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173 if( con == 0 ) return NULL; // By zero is handled by Value call
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174 if( con == 1 ) return NULL; // By one is handled by Identity call
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175
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176 // Check for negative constant; if so negate the final result
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177 bool sign_flip = false;
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178 if( con < 0 ) {
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179 con = -con;
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180 sign_flip = true;
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181 }
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182
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183 // Get low bit; check for being the only bit
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184 Node *res = NULL;
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185 jint bit1 = con & -con; // Extract low bit
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186 if( bit1 == con ) { // Found a power of 2?
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187 res = new (phase->C, 3) LShiftINode( in(1), phase->intcon(log2_intptr(bit1)) );
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188 } else {
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189
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190 // Check for constant with 2 bits set
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191 jint bit2 = con-bit1;
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192 bit2 = bit2 & -bit2; // Extract 2nd bit
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193 if( bit2 + bit1 == con ) { // Found all bits in con?
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194 Node *n1 = phase->transform( new (phase->C, 3) LShiftINode( in(1), phase->intcon(log2_intptr(bit1)) ) );
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195 Node *n2 = phase->transform( new (phase->C, 3) LShiftINode( in(1), phase->intcon(log2_intptr(bit2)) ) );
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196 res = new (phase->C, 3) AddINode( n2, n1 );
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197
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198 } else if (is_power_of_2(con+1)) {
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199 // Sleezy: power-of-2 -1. Next time be generic.
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200 jint temp = (jint) (con + 1);
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201 Node *n1 = phase->transform( new (phase->C, 3) LShiftINode( in(1), phase->intcon(log2_intptr(temp)) ) );
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202 res = new (phase->C, 3) SubINode( n1, in(1) );
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203 } else {
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204 return MulNode::Ideal(phase, can_reshape);
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205 }
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206 }
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207
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208 if( sign_flip ) { // Need to negate result?
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209 res = phase->transform(res);// Transform, before making the zero con
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210 res = new (phase->C, 3) SubINode(phase->intcon(0),res);
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211 }
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212
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213 return res; // Return final result
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214 }
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215
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216 //------------------------------mul_ring---------------------------------------
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217 // Compute the product type of two integer ranges into this node.
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218 const Type *MulINode::mul_ring(const Type *t0, const Type *t1) const {
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219 const TypeInt *r0 = t0->is_int(); // Handy access
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220 const TypeInt *r1 = t1->is_int();
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221
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222 // Fetch endpoints of all ranges
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223 int32 lo0 = r0->_lo;
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224 double a = (double)lo0;
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225 int32 hi0 = r0->_hi;
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226 double b = (double)hi0;
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227 int32 lo1 = r1->_lo;
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228 double c = (double)lo1;
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229 int32 hi1 = r1->_hi;
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230 double d = (double)hi1;
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231
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232 // Compute all endpoints & check for overflow
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233 int32 A = lo0*lo1;
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234 if( (double)A != a*c ) return TypeInt::INT; // Overflow?
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235 int32 B = lo0*hi1;
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236 if( (double)B != a*d ) return TypeInt::INT; // Overflow?
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237 int32 C = hi0*lo1;
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238 if( (double)C != b*c ) return TypeInt::INT; // Overflow?
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239 int32 D = hi0*hi1;
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240 if( (double)D != b*d ) return TypeInt::INT; // Overflow?
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241
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242 if( A < B ) { lo0 = A; hi0 = B; } // Sort range endpoints
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243 else { lo0 = B; hi0 = A; }
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244 if( C < D ) {
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245 if( C < lo0 ) lo0 = C;
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246 if( D > hi0 ) hi0 = D;
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247 } else {
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248 if( D < lo0 ) lo0 = D;
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249 if( C > hi0 ) hi0 = C;
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250 }
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251 return TypeInt::make(lo0, hi0, MAX2(r0->_widen,r1->_widen));
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252 }
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253
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254
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255 //=============================================================================
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256 //------------------------------Ideal------------------------------------------
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257 // Check for power-of-2 multiply, then try the regular MulNode::Ideal
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258 Node *MulLNode::Ideal(PhaseGVN *phase, bool can_reshape) {
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259 // Swap constant to right
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260 jlong con;
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261 if ((con = in(1)->find_long_con(0)) != 0) {
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262 swap_edges(1, 2);
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263 // Finish rest of method to use info in 'con'
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264 } else if ((con = in(2)->find_long_con(0)) == 0) {
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265 return MulNode::Ideal(phase, can_reshape);
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266 }
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267
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268 // Now we have a constant Node on the right and the constant in con
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269 if( con == CONST64(0) ) return NULL; // By zero is handled by Value call
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270 if( con == CONST64(1) ) return NULL; // By one is handled by Identity call
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271
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272 // Check for negative constant; if so negate the final result
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273 bool sign_flip = false;
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274 if( con < 0 ) {
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275 con = -con;
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276 sign_flip = true;
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277 }
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278
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279 // Get low bit; check for being the only bit
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280 Node *res = NULL;
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281 jlong bit1 = con & -con; // Extract low bit
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282 if( bit1 == con ) { // Found a power of 2?
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283 res = new (phase->C, 3) LShiftLNode( in(1), phase->intcon(log2_long(bit1)) );
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284 } else {
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285
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286 // Check for constant with 2 bits set
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287 jlong bit2 = con-bit1;
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288 bit2 = bit2 & -bit2; // Extract 2nd bit
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289 if( bit2 + bit1 == con ) { // Found all bits in con?
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290 Node *n1 = phase->transform( new (phase->C, 3) LShiftLNode( in(1), phase->intcon(log2_long(bit1)) ) );
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291 Node *n2 = phase->transform( new (phase->C, 3) LShiftLNode( in(1), phase->intcon(log2_long(bit2)) ) );
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292 res = new (phase->C, 3) AddLNode( n2, n1 );
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293
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294 } else if (is_power_of_2_long(con+1)) {
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295 // Sleezy: power-of-2 -1. Next time be generic.
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296 jlong temp = (jlong) (con + 1);
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297 Node *n1 = phase->transform( new (phase->C, 3) LShiftLNode( in(1), phase->intcon(log2_long(temp)) ) );
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298 res = new (phase->C, 3) SubLNode( n1, in(1) );
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299 } else {
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300 return MulNode::Ideal(phase, can_reshape);
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301 }
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302 }
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303
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304 if( sign_flip ) { // Need to negate result?
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305 res = phase->transform(res);// Transform, before making the zero con
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306 res = new (phase->C, 3) SubLNode(phase->longcon(0),res);
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307 }
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308
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309 return res; // Return final result
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310 }
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311
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312 //------------------------------mul_ring---------------------------------------
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313 // Compute the product type of two integer ranges into this node.
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314 const Type *MulLNode::mul_ring(const Type *t0, const Type *t1) const {
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315 const TypeLong *r0 = t0->is_long(); // Handy access
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316 const TypeLong *r1 = t1->is_long();
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317
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318 // Fetch endpoints of all ranges
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319 jlong lo0 = r0->_lo;
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320 double a = (double)lo0;
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diff changeset
321 jlong hi0 = r0->_hi;
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322 double b = (double)hi0;
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323 jlong lo1 = r1->_lo;
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324 double c = (double)lo1;
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325 jlong hi1 = r1->_hi;
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326 double d = (double)hi1;
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327
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328 // Compute all endpoints & check for overflow
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diff changeset
329 jlong A = lo0*lo1;
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330 if( (double)A != a*c ) return TypeLong::LONG; // Overflow?
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331 jlong B = lo0*hi1;
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332 if( (double)B != a*d ) return TypeLong::LONG; // Overflow?
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parents:
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333 jlong C = hi0*lo1;
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diff changeset
334 if( (double)C != b*c ) return TypeLong::LONG; // Overflow?
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335 jlong D = hi0*hi1;
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336 if( (double)D != b*d ) return TypeLong::LONG; // Overflow?
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parents:
diff changeset
337
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338 if( A < B ) { lo0 = A; hi0 = B; } // Sort range endpoints
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339 else { lo0 = B; hi0 = A; }
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parents:
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340 if( C < D ) {
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parents:
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341 if( C < lo0 ) lo0 = C;
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parents:
diff changeset
342 if( D > hi0 ) hi0 = D;
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parents:
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343 } else {
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parents:
diff changeset
344 if( D < lo0 ) lo0 = D;
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parents:
diff changeset
345 if( C > hi0 ) hi0 = C;
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parents:
diff changeset
346 }
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347 return TypeLong::make(lo0, hi0, MAX2(r0->_widen,r1->_widen));
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parents:
diff changeset
348 }
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349
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350 //=============================================================================
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351 //------------------------------mul_ring---------------------------------------
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diff changeset
352 // Compute the product type of two double ranges into this node.
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353 const Type *MulFNode::mul_ring(const Type *t0, const Type *t1) const {
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parents:
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354 if( t0 == Type::FLOAT || t1 == Type::FLOAT ) return Type::FLOAT;
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parents:
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355 return TypeF::make( t0->getf() * t1->getf() );
a61af66fc99e Initial load
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parents:
diff changeset
356 }
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357
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358 //=============================================================================
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parents:
diff changeset
359 //------------------------------mul_ring---------------------------------------
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360 // Compute the product type of two double ranges into this node.
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361 const Type *MulDNode::mul_ring(const Type *t0, const Type *t1) const {
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parents:
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362 if( t0 == Type::DOUBLE || t1 == Type::DOUBLE ) return Type::DOUBLE;
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parents:
diff changeset
363 // We must be adding 2 double constants.
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parents:
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364 return TypeD::make( t0->getd() * t1->getd() );
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parents:
diff changeset
365 }
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366
a61af66fc99e Initial load
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parents:
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367 //=============================================================================
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parents:
diff changeset
368 //------------------------------mul_ring---------------------------------------
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parents:
diff changeset
369 // Supplied function returns the product of the inputs IN THE CURRENT RING.
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parents:
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370 // For the logical operations the ring's MUL is really a logical AND function.
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parents:
diff changeset
371 // This also type-checks the inputs for sanity. Guaranteed never to
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parents:
diff changeset
372 // be passed a TOP or BOTTOM type, these are filtered out by pre-check.
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diff changeset
373 const Type *AndINode::mul_ring( const Type *t0, const Type *t1 ) const {
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parents:
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374 const TypeInt *r0 = t0->is_int(); // Handy access
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parents:
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375 const TypeInt *r1 = t1->is_int();
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parents:
diff changeset
376 int widen = MAX2(r0->_widen,r1->_widen);
a61af66fc99e Initial load
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diff changeset
377
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parents:
diff changeset
378 // If either input is a constant, might be able to trim cases
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parents:
diff changeset
379 if( !r0->is_con() && !r1->is_con() )
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parents:
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380 return TypeInt::INT; // No constants to be had
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parents:
diff changeset
381
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parents:
diff changeset
382 // Both constants? Return bits
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parents:
diff changeset
383 if( r0->is_con() && r1->is_con() )
a61af66fc99e Initial load
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parents:
diff changeset
384 return TypeInt::make( r0->get_con() & r1->get_con() );
a61af66fc99e Initial load
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parents:
diff changeset
385
a61af66fc99e Initial load
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parents:
diff changeset
386 if( r0->is_con() && r0->get_con() > 0 )
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parents:
diff changeset
387 return TypeInt::make(0, r0->get_con(), widen);
a61af66fc99e Initial load
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parents:
diff changeset
388
a61af66fc99e Initial load
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parents:
diff changeset
389 if( r1->is_con() && r1->get_con() > 0 )
a61af66fc99e Initial load
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parents:
diff changeset
390 return TypeInt::make(0, r1->get_con(), widen);
a61af66fc99e Initial load
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parents:
diff changeset
391
a61af66fc99e Initial load
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parents:
diff changeset
392 if( r0 == TypeInt::BOOL || r1 == TypeInt::BOOL ) {
a61af66fc99e Initial load
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parents:
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393 return TypeInt::BOOL;
a61af66fc99e Initial load
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parents:
diff changeset
394 }
a61af66fc99e Initial load
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parents:
diff changeset
395
a61af66fc99e Initial load
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parents:
diff changeset
396 return TypeInt::INT; // No constants to be had
a61af66fc99e Initial load
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parents:
diff changeset
397 }
a61af66fc99e Initial load
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parents:
diff changeset
398
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parents:
diff changeset
399 //------------------------------Identity---------------------------------------
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parents:
diff changeset
400 // Masking off the high bits of an unsigned load is not required
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parents:
diff changeset
401 Node *AndINode::Identity( PhaseTransform *phase ) {
a61af66fc99e Initial load
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parents:
diff changeset
402
a61af66fc99e Initial load
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parents:
diff changeset
403 // x & x => x
a61af66fc99e Initial load
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parents:
diff changeset
404 if (phase->eqv(in(1), in(2))) return in(1);
a61af66fc99e Initial load
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parents:
diff changeset
405
a61af66fc99e Initial load
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parents:
diff changeset
406 Node *load = in(1);
a61af66fc99e Initial load
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parents:
diff changeset
407 const TypeInt *t2 = phase->type( in(2) )->isa_int();
a61af66fc99e Initial load
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parents:
diff changeset
408 if( t2 && t2->is_con() ) {
a61af66fc99e Initial load
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parents:
diff changeset
409 int con = t2->get_con();
a61af66fc99e Initial load
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parents:
diff changeset
410 // Masking off high bits which are always zero is useless.
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parents:
diff changeset
411 const TypeInt* t1 = phase->type( in(1) )->isa_int();
a61af66fc99e Initial load
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parents:
diff changeset
412 if (t1 != NULL && t1->_lo >= 0) {
a61af66fc99e Initial load
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parents:
diff changeset
413 jint t1_support = ((jint)1 << (1 + log2_intptr(t1->_hi))) - 1;
a61af66fc99e Initial load
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parents:
diff changeset
414 if ((t1_support & con) == t1_support)
a61af66fc99e Initial load
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parents:
diff changeset
415 return load;
a61af66fc99e Initial load
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parents:
diff changeset
416 }
a61af66fc99e Initial load
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parents:
diff changeset
417 uint lop = load->Opcode();
a61af66fc99e Initial load
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parents:
diff changeset
418 if( lop == Op_LoadC &&
a61af66fc99e Initial load
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parents:
diff changeset
419 con == 0x0000FFFF ) // Already zero-extended
a61af66fc99e Initial load
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parents:
diff changeset
420 return load;
a61af66fc99e Initial load
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parents:
diff changeset
421 // Masking off the high bits of a unsigned-shift-right is not
a61af66fc99e Initial load
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parents:
diff changeset
422 // needed either.
a61af66fc99e Initial load
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parents:
diff changeset
423 if( lop == Op_URShiftI ) {
a61af66fc99e Initial load
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parents:
diff changeset
424 const TypeInt *t12 = phase->type( load->in(2) )->isa_int();
a61af66fc99e Initial load
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parents:
diff changeset
425 if( t12 && t12->is_con() ) {
a61af66fc99e Initial load
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parents:
diff changeset
426 int shift_con = t12->get_con();
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parents:
diff changeset
427 int mask = max_juint >> shift_con;
a61af66fc99e Initial load
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parents:
diff changeset
428 if( (mask&con) == mask ) // If AND is useless, skip it
a61af66fc99e Initial load
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parents:
diff changeset
429 return load;
a61af66fc99e Initial load
duke
parents:
diff changeset
430 }
a61af66fc99e Initial load
duke
parents:
diff changeset
431 }
a61af66fc99e Initial load
duke
parents:
diff changeset
432 }
a61af66fc99e Initial load
duke
parents:
diff changeset
433 return MulNode::Identity(phase);
a61af66fc99e Initial load
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parents:
diff changeset
434 }
a61af66fc99e Initial load
duke
parents:
diff changeset
435
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parents:
diff changeset
436 //------------------------------Ideal------------------------------------------
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parents:
diff changeset
437 Node *AndINode::Ideal(PhaseGVN *phase, bool can_reshape) {
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duke
parents:
diff changeset
438 // Special case constant AND mask
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parents:
diff changeset
439 const TypeInt *t2 = phase->type( in(2) )->isa_int();
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parents:
diff changeset
440 if( !t2 || !t2->is_con() ) return MulNode::Ideal(phase, can_reshape);
a61af66fc99e Initial load
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parents:
diff changeset
441 const int mask = t2->get_con();
a61af66fc99e Initial load
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parents:
diff changeset
442 Node *load = in(1);
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parents:
diff changeset
443 uint lop = load->Opcode();
a61af66fc99e Initial load
duke
parents:
diff changeset
444
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duke
parents:
diff changeset
445 // Masking bits off of a Character? Hi bits are already zero.
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duke
parents:
diff changeset
446 if( lop == Op_LoadC &&
a61af66fc99e Initial load
duke
parents:
diff changeset
447 (mask & 0xFFFF0000) ) // Can we make a smaller mask?
a61af66fc99e Initial load
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parents:
diff changeset
448 return new (phase->C, 3) AndINode(load,phase->intcon(mask&0xFFFF));
a61af66fc99e Initial load
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parents:
diff changeset
449
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parents:
diff changeset
450 // Masking bits off of a Short? Loading a Character does some masking
a61af66fc99e Initial load
duke
parents:
diff changeset
451 if( lop == Op_LoadS &&
a61af66fc99e Initial load
duke
parents:
diff changeset
452 (mask & 0xFFFF0000) == 0 ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
453 Node *ldc = new (phase->C, 3) LoadCNode(load->in(MemNode::Control),
a61af66fc99e Initial load
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parents:
diff changeset
454 load->in(MemNode::Memory),
a61af66fc99e Initial load
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parents:
diff changeset
455 load->in(MemNode::Address),
a61af66fc99e Initial load
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parents:
diff changeset
456 load->adr_type());
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parents:
diff changeset
457 ldc = phase->transform(ldc);
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parents:
diff changeset
458 return new (phase->C, 3) AndINode(ldc,phase->intcon(mask&0xFFFF));
a61af66fc99e Initial load
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parents:
diff changeset
459 }
a61af66fc99e Initial load
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parents:
diff changeset
460
a61af66fc99e Initial load
duke
parents:
diff changeset
461 // Masking sign bits off of a Byte? Let the matcher use an unsigned load
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parents:
diff changeset
462 if( lop == Op_LoadB &&
a61af66fc99e Initial load
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parents:
diff changeset
463 (!in(0) && load->in(0)) &&
a61af66fc99e Initial load
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parents:
diff changeset
464 (mask == 0x000000FF) ) {
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parents:
diff changeset
465 // Associate this node with the LoadB, so the matcher can see them together.
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parents:
diff changeset
466 // If we don't do this, it is common for the LoadB to have one control
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parents:
diff changeset
467 // edge, and the store or call containing this AndI to have a different
a61af66fc99e Initial load
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parents:
diff changeset
468 // control edge. This will cause Label_Root to group the AndI with
a61af66fc99e Initial load
duke
parents:
diff changeset
469 // the encoding store or call, so the matcher has no chance to match
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parents:
diff changeset
470 // this AndI together with the LoadB. Setting the control edge here
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parents:
diff changeset
471 // prevents Label_Root from grouping the AndI with the store or call,
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parents:
diff changeset
472 // if it has a control edge that is inconsistent with the LoadB.
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parents:
diff changeset
473 set_req(0, load->in(0));
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parents:
diff changeset
474 return this;
a61af66fc99e Initial load
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parents:
diff changeset
475 }
a61af66fc99e Initial load
duke
parents:
diff changeset
476
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duke
parents:
diff changeset
477 // Masking off sign bits? Dont make them!
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parents:
diff changeset
478 if( lop == Op_RShiftI ) {
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parents:
diff changeset
479 const TypeInt *t12 = phase->type(load->in(2))->isa_int();
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duke
parents:
diff changeset
480 if( t12 && t12->is_con() ) { // Shift is by a constant
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duke
parents:
diff changeset
481 int shift = t12->get_con();
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parents:
diff changeset
482 shift &= BitsPerJavaInteger-1; // semantics of Java shifts
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parents:
diff changeset
483 const int sign_bits_mask = ~right_n_bits(BitsPerJavaInteger - shift);
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duke
parents:
diff changeset
484 // If the AND'ing of the 2 masks has no bits, then only original shifted
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parents:
diff changeset
485 // bits survive. NO sign-extension bits survive the maskings.
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parents:
diff changeset
486 if( (sign_bits_mask & mask) == 0 ) {
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duke
parents:
diff changeset
487 // Use zero-fill shift instead
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parents:
diff changeset
488 Node *zshift = phase->transform(new (phase->C, 3) URShiftINode(load->in(1),load->in(2)));
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parents:
diff changeset
489 return new (phase->C, 3) AndINode( zshift, in(2) );
a61af66fc99e Initial load
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parents:
diff changeset
490 }
a61af66fc99e Initial load
duke
parents:
diff changeset
491 }
a61af66fc99e Initial load
duke
parents:
diff changeset
492 }
a61af66fc99e Initial load
duke
parents:
diff changeset
493
a61af66fc99e Initial load
duke
parents:
diff changeset
494 // Check for 'negate/and-1', a pattern emitted when someone asks for
a61af66fc99e Initial load
duke
parents:
diff changeset
495 // 'mod 2'. Negate leaves the low order bit unchanged (think: complement
a61af66fc99e Initial load
duke
parents:
diff changeset
496 // plus 1) and the mask is of the low order bit. Skip the negate.
a61af66fc99e Initial load
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parents:
diff changeset
497 if( lop == Op_SubI && mask == 1 && load->in(1) &&
a61af66fc99e Initial load
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parents:
diff changeset
498 phase->type(load->in(1)) == TypeInt::ZERO )
a61af66fc99e Initial load
duke
parents:
diff changeset
499 return new (phase->C, 3) AndINode( load->in(2), in(2) );
a61af66fc99e Initial load
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parents:
diff changeset
500
a61af66fc99e Initial load
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parents:
diff changeset
501 return MulNode::Ideal(phase, can_reshape);
a61af66fc99e Initial load
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parents:
diff changeset
502 }
a61af66fc99e Initial load
duke
parents:
diff changeset
503
a61af66fc99e Initial load
duke
parents:
diff changeset
504 //=============================================================================
a61af66fc99e Initial load
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parents:
diff changeset
505 //------------------------------mul_ring---------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
506 // Supplied function returns the product of the inputs IN THE CURRENT RING.
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parents:
diff changeset
507 // For the logical operations the ring's MUL is really a logical AND function.
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parents:
diff changeset
508 // This also type-checks the inputs for sanity. Guaranteed never to
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parents:
diff changeset
509 // be passed a TOP or BOTTOM type, these are filtered out by pre-check.
a61af66fc99e Initial load
duke
parents:
diff changeset
510 const Type *AndLNode::mul_ring( const Type *t0, const Type *t1 ) const {
a61af66fc99e Initial load
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parents:
diff changeset
511 const TypeLong *r0 = t0->is_long(); // Handy access
a61af66fc99e Initial load
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parents:
diff changeset
512 const TypeLong *r1 = t1->is_long();
a61af66fc99e Initial load
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parents:
diff changeset
513 int widen = MAX2(r0->_widen,r1->_widen);
a61af66fc99e Initial load
duke
parents:
diff changeset
514
a61af66fc99e Initial load
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parents:
diff changeset
515 // If either input is a constant, might be able to trim cases
a61af66fc99e Initial load
duke
parents:
diff changeset
516 if( !r0->is_con() && !r1->is_con() )
a61af66fc99e Initial load
duke
parents:
diff changeset
517 return TypeLong::LONG; // No constants to be had
a61af66fc99e Initial load
duke
parents:
diff changeset
518
a61af66fc99e Initial load
duke
parents:
diff changeset
519 // Both constants? Return bits
a61af66fc99e Initial load
duke
parents:
diff changeset
520 if( r0->is_con() && r1->is_con() )
a61af66fc99e Initial load
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parents:
diff changeset
521 return TypeLong::make( r0->get_con() & r1->get_con() );
a61af66fc99e Initial load
duke
parents:
diff changeset
522
a61af66fc99e Initial load
duke
parents:
diff changeset
523 if( r0->is_con() && r0->get_con() > 0 )
a61af66fc99e Initial load
duke
parents:
diff changeset
524 return TypeLong::make(CONST64(0), r0->get_con(), widen);
a61af66fc99e Initial load
duke
parents:
diff changeset
525
a61af66fc99e Initial load
duke
parents:
diff changeset
526 if( r1->is_con() && r1->get_con() > 0 )
a61af66fc99e Initial load
duke
parents:
diff changeset
527 return TypeLong::make(CONST64(0), r1->get_con(), widen);
a61af66fc99e Initial load
duke
parents:
diff changeset
528
a61af66fc99e Initial load
duke
parents:
diff changeset
529 return TypeLong::LONG; // No constants to be had
a61af66fc99e Initial load
duke
parents:
diff changeset
530 }
a61af66fc99e Initial load
duke
parents:
diff changeset
531
a61af66fc99e Initial load
duke
parents:
diff changeset
532 //------------------------------Identity---------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
533 // Masking off the high bits of an unsigned load is not required
a61af66fc99e Initial load
duke
parents:
diff changeset
534 Node *AndLNode::Identity( PhaseTransform *phase ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
535
a61af66fc99e Initial load
duke
parents:
diff changeset
536 // x & x => x
a61af66fc99e Initial load
duke
parents:
diff changeset
537 if (phase->eqv(in(1), in(2))) return in(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
538
a61af66fc99e Initial load
duke
parents:
diff changeset
539 Node *usr = in(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
540 const TypeLong *t2 = phase->type( in(2) )->isa_long();
a61af66fc99e Initial load
duke
parents:
diff changeset
541 if( t2 && t2->is_con() ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
542 jlong con = t2->get_con();
a61af66fc99e Initial load
duke
parents:
diff changeset
543 // Masking off high bits which are always zero is useless.
a61af66fc99e Initial load
duke
parents:
diff changeset
544 const TypeLong* t1 = phase->type( in(1) )->isa_long();
a61af66fc99e Initial load
duke
parents:
diff changeset
545 if (t1 != NULL && t1->_lo >= 0) {
a61af66fc99e Initial load
duke
parents:
diff changeset
546 jlong t1_support = ((jlong)1 << (1 + log2_long(t1->_hi))) - 1;
a61af66fc99e Initial load
duke
parents:
diff changeset
547 if ((t1_support & con) == t1_support)
a61af66fc99e Initial load
duke
parents:
diff changeset
548 return usr;
a61af66fc99e Initial load
duke
parents:
diff changeset
549 }
a61af66fc99e Initial load
duke
parents:
diff changeset
550 uint lop = usr->Opcode();
a61af66fc99e Initial load
duke
parents:
diff changeset
551 // Masking off the high bits of a unsigned-shift-right is not
a61af66fc99e Initial load
duke
parents:
diff changeset
552 // needed either.
a61af66fc99e Initial load
duke
parents:
diff changeset
553 if( lop == Op_URShiftL ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
554 const TypeInt *t12 = phase->type( usr->in(2) )->isa_int();
a61af66fc99e Initial load
duke
parents:
diff changeset
555 if( t12 && t12->is_con() ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
556 int shift_con = t12->get_con();
a61af66fc99e Initial load
duke
parents:
diff changeset
557 jlong mask = max_julong >> shift_con;
a61af66fc99e Initial load
duke
parents:
diff changeset
558 if( (mask&con) == mask ) // If AND is useless, skip it
a61af66fc99e Initial load
duke
parents:
diff changeset
559 return usr;
a61af66fc99e Initial load
duke
parents:
diff changeset
560 }
a61af66fc99e Initial load
duke
parents:
diff changeset
561 }
a61af66fc99e Initial load
duke
parents:
diff changeset
562 }
a61af66fc99e Initial load
duke
parents:
diff changeset
563 return MulNode::Identity(phase);
a61af66fc99e Initial load
duke
parents:
diff changeset
564 }
a61af66fc99e Initial load
duke
parents:
diff changeset
565
a61af66fc99e Initial load
duke
parents:
diff changeset
566 //------------------------------Ideal------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
567 Node *AndLNode::Ideal(PhaseGVN *phase, bool can_reshape) {
a61af66fc99e Initial load
duke
parents:
diff changeset
568 // Special case constant AND mask
a61af66fc99e Initial load
duke
parents:
diff changeset
569 const TypeLong *t2 = phase->type( in(2) )->isa_long();
a61af66fc99e Initial load
duke
parents:
diff changeset
570 if( !t2 || !t2->is_con() ) return MulNode::Ideal(phase, can_reshape);
a61af66fc99e Initial load
duke
parents:
diff changeset
571 const jlong mask = t2->get_con();
a61af66fc99e Initial load
duke
parents:
diff changeset
572
a61af66fc99e Initial load
duke
parents:
diff changeset
573 Node *rsh = in(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
574 uint rop = rsh->Opcode();
a61af66fc99e Initial load
duke
parents:
diff changeset
575
a61af66fc99e Initial load
duke
parents:
diff changeset
576 // Masking off sign bits? Dont make them!
a61af66fc99e Initial load
duke
parents:
diff changeset
577 if( rop == Op_RShiftL ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
578 const TypeInt *t12 = phase->type(rsh->in(2))->isa_int();
a61af66fc99e Initial load
duke
parents:
diff changeset
579 if( t12 && t12->is_con() ) { // Shift is by a constant
a61af66fc99e Initial load
duke
parents:
diff changeset
580 int shift = t12->get_con();
a61af66fc99e Initial load
duke
parents:
diff changeset
581 shift &= (BitsPerJavaInteger*2)-1; // semantics of Java shifts
a61af66fc99e Initial load
duke
parents:
diff changeset
582 const jlong sign_bits_mask = ~(((jlong)CONST64(1) << (jlong)(BitsPerJavaInteger*2 - shift)) -1);
a61af66fc99e Initial load
duke
parents:
diff changeset
583 // If the AND'ing of the 2 masks has no bits, then only original shifted
a61af66fc99e Initial load
duke
parents:
diff changeset
584 // bits survive. NO sign-extension bits survive the maskings.
a61af66fc99e Initial load
duke
parents:
diff changeset
585 if( (sign_bits_mask & mask) == 0 ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
586 // Use zero-fill shift instead
a61af66fc99e Initial load
duke
parents:
diff changeset
587 Node *zshift = phase->transform(new (phase->C, 3) URShiftLNode(rsh->in(1),rsh->in(2)));
a61af66fc99e Initial load
duke
parents:
diff changeset
588 return new (phase->C, 3) AndLNode( zshift, in(2) );
a61af66fc99e Initial load
duke
parents:
diff changeset
589 }
a61af66fc99e Initial load
duke
parents:
diff changeset
590 }
a61af66fc99e Initial load
duke
parents:
diff changeset
591 }
a61af66fc99e Initial load
duke
parents:
diff changeset
592
a61af66fc99e Initial load
duke
parents:
diff changeset
593 return MulNode::Ideal(phase, can_reshape);
a61af66fc99e Initial load
duke
parents:
diff changeset
594 }
a61af66fc99e Initial load
duke
parents:
diff changeset
595
a61af66fc99e Initial load
duke
parents:
diff changeset
596 //=============================================================================
a61af66fc99e Initial load
duke
parents:
diff changeset
597 //------------------------------Identity---------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
598 Node *LShiftINode::Identity( PhaseTransform *phase ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
599 const TypeInt *ti = phase->type( in(2) )->isa_int(); // shift count is an int
a61af66fc99e Initial load
duke
parents:
diff changeset
600 return ( ti && ti->is_con() && ( ti->get_con() & ( BitsPerInt - 1 ) ) == 0 ) ? in(1) : this;
a61af66fc99e Initial load
duke
parents:
diff changeset
601 }
a61af66fc99e Initial load
duke
parents:
diff changeset
602
a61af66fc99e Initial load
duke
parents:
diff changeset
603 //------------------------------Ideal------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
604 // If the right input is a constant, and the left input is an add of a
a61af66fc99e Initial load
duke
parents:
diff changeset
605 // constant, flatten the tree: (X+con1)<<con0 ==> X<<con0 + con1<<con0
a61af66fc99e Initial load
duke
parents:
diff changeset
606 Node *LShiftINode::Ideal(PhaseGVN *phase, bool can_reshape) {
a61af66fc99e Initial load
duke
parents:
diff changeset
607 const Type *t = phase->type( in(2) );
a61af66fc99e Initial load
duke
parents:
diff changeset
608 if( t == Type::TOP ) return NULL; // Right input is dead
a61af66fc99e Initial load
duke
parents:
diff changeset
609 const TypeInt *t2 = t->isa_int();
a61af66fc99e Initial load
duke
parents:
diff changeset
610 if( !t2 || !t2->is_con() ) return NULL; // Right input is a constant
a61af66fc99e Initial load
duke
parents:
diff changeset
611 const int con = t2->get_con() & ( BitsPerInt - 1 ); // masked shift count
a61af66fc99e Initial load
duke
parents:
diff changeset
612
a61af66fc99e Initial load
duke
parents:
diff changeset
613 if ( con == 0 ) return NULL; // let Identity() handle 0 shift count
a61af66fc99e Initial load
duke
parents:
diff changeset
614
a61af66fc99e Initial load
duke
parents:
diff changeset
615 // Left input is an add of a constant?
a61af66fc99e Initial load
duke
parents:
diff changeset
616 Node *add1 = in(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
617 int add1_op = add1->Opcode();
a61af66fc99e Initial load
duke
parents:
diff changeset
618 if( add1_op == Op_AddI ) { // Left input is an add?
a61af66fc99e Initial load
duke
parents:
diff changeset
619 assert( add1 != add1->in(1), "dead loop in LShiftINode::Ideal" );
a61af66fc99e Initial load
duke
parents:
diff changeset
620 const TypeInt *t12 = phase->type(add1->in(2))->isa_int();
a61af66fc99e Initial load
duke
parents:
diff changeset
621 if( t12 && t12->is_con() ){ // Left input is an add of a con?
a61af66fc99e Initial load
duke
parents:
diff changeset
622 // Transform is legal, but check for profit. Avoid breaking 'i2s'
a61af66fc99e Initial load
duke
parents:
diff changeset
623 // and 'i2b' patterns which typically fold into 'StoreC/StoreB'.
a61af66fc99e Initial load
duke
parents:
diff changeset
624 if( con < 16 ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
625 // Compute X << con0
a61af66fc99e Initial load
duke
parents:
diff changeset
626 Node *lsh = phase->transform( new (phase->C, 3) LShiftINode( add1->in(1), in(2) ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
627 // Compute X<<con0 + (con1<<con0)
a61af66fc99e Initial load
duke
parents:
diff changeset
628 return new (phase->C, 3) AddINode( lsh, phase->intcon(t12->get_con() << con));
a61af66fc99e Initial load
duke
parents:
diff changeset
629 }
a61af66fc99e Initial load
duke
parents:
diff changeset
630 }
a61af66fc99e Initial load
duke
parents:
diff changeset
631 }
a61af66fc99e Initial load
duke
parents:
diff changeset
632
a61af66fc99e Initial load
duke
parents:
diff changeset
633 // Check for "(x>>c0)<<c0" which just masks off low bits
a61af66fc99e Initial load
duke
parents:
diff changeset
634 if( (add1_op == Op_RShiftI || add1_op == Op_URShiftI ) &&
a61af66fc99e Initial load
duke
parents:
diff changeset
635 add1->in(2) == in(2) )
a61af66fc99e Initial load
duke
parents:
diff changeset
636 // Convert to "(x & -(1<<c0))"
a61af66fc99e Initial load
duke
parents:
diff changeset
637 return new (phase->C, 3) AndINode(add1->in(1),phase->intcon( -(1<<con)));
a61af66fc99e Initial load
duke
parents:
diff changeset
638
a61af66fc99e Initial load
duke
parents:
diff changeset
639 // Check for "((x>>c0) & Y)<<c0" which just masks off more low bits
a61af66fc99e Initial load
duke
parents:
diff changeset
640 if( add1_op == Op_AndI ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
641 Node *add2 = add1->in(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
642 int add2_op = add2->Opcode();
a61af66fc99e Initial load
duke
parents:
diff changeset
643 if( (add2_op == Op_RShiftI || add2_op == Op_URShiftI ) &&
a61af66fc99e Initial load
duke
parents:
diff changeset
644 add2->in(2) == in(2) ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
645 // Convert to "(x & (Y<<c0))"
a61af66fc99e Initial load
duke
parents:
diff changeset
646 Node *y_sh = phase->transform( new (phase->C, 3) LShiftINode( add1->in(2), in(2) ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
647 return new (phase->C, 3) AndINode( add2->in(1), y_sh );
a61af66fc99e Initial load
duke
parents:
diff changeset
648 }
a61af66fc99e Initial load
duke
parents:
diff changeset
649 }
a61af66fc99e Initial load
duke
parents:
diff changeset
650
a61af66fc99e Initial load
duke
parents:
diff changeset
651 // Check for ((x & ((1<<(32-c0))-1)) << c0) which ANDs off high bits
a61af66fc99e Initial load
duke
parents:
diff changeset
652 // before shifting them away.
a61af66fc99e Initial load
duke
parents:
diff changeset
653 const jint bits_mask = right_n_bits(BitsPerJavaInteger-con);
a61af66fc99e Initial load
duke
parents:
diff changeset
654 if( add1_op == Op_AndI &&
a61af66fc99e Initial load
duke
parents:
diff changeset
655 phase->type(add1->in(2)) == TypeInt::make( bits_mask ) )
a61af66fc99e Initial load
duke
parents:
diff changeset
656 return new (phase->C, 3) LShiftINode( add1->in(1), in(2) );
a61af66fc99e Initial load
duke
parents:
diff changeset
657
a61af66fc99e Initial load
duke
parents:
diff changeset
658 return NULL;
a61af66fc99e Initial load
duke
parents:
diff changeset
659 }
a61af66fc99e Initial load
duke
parents:
diff changeset
660
a61af66fc99e Initial load
duke
parents:
diff changeset
661 //------------------------------Value------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
662 // A LShiftINode shifts its input2 left by input1 amount.
a61af66fc99e Initial load
duke
parents:
diff changeset
663 const Type *LShiftINode::Value( PhaseTransform *phase ) const {
a61af66fc99e Initial load
duke
parents:
diff changeset
664 const Type *t1 = phase->type( in(1) );
a61af66fc99e Initial load
duke
parents:
diff changeset
665 const Type *t2 = phase->type( in(2) );
a61af66fc99e Initial load
duke
parents:
diff changeset
666 // Either input is TOP ==> the result is TOP
a61af66fc99e Initial load
duke
parents:
diff changeset
667 if( t1 == Type::TOP ) return Type::TOP;
a61af66fc99e Initial load
duke
parents:
diff changeset
668 if( t2 == Type::TOP ) return Type::TOP;
a61af66fc99e Initial load
duke
parents:
diff changeset
669
a61af66fc99e Initial load
duke
parents:
diff changeset
670 // Left input is ZERO ==> the result is ZERO.
a61af66fc99e Initial load
duke
parents:
diff changeset
671 if( t1 == TypeInt::ZERO ) return TypeInt::ZERO;
a61af66fc99e Initial load
duke
parents:
diff changeset
672 // Shift by zero does nothing
a61af66fc99e Initial load
duke
parents:
diff changeset
673 if( t2 == TypeInt::ZERO ) return t1;
a61af66fc99e Initial load
duke
parents:
diff changeset
674
a61af66fc99e Initial load
duke
parents:
diff changeset
675 // Either input is BOTTOM ==> the result is BOTTOM
a61af66fc99e Initial load
duke
parents:
diff changeset
676 if( (t1 == TypeInt::INT) || (t2 == TypeInt::INT) ||
a61af66fc99e Initial load
duke
parents:
diff changeset
677 (t1 == Type::BOTTOM) || (t2 == Type::BOTTOM) )
a61af66fc99e Initial load
duke
parents:
diff changeset
678 return TypeInt::INT;
a61af66fc99e Initial load
duke
parents:
diff changeset
679
a61af66fc99e Initial load
duke
parents:
diff changeset
680 const TypeInt *r1 = t1->is_int(); // Handy access
a61af66fc99e Initial load
duke
parents:
diff changeset
681 const TypeInt *r2 = t2->is_int(); // Handy access
a61af66fc99e Initial load
duke
parents:
diff changeset
682
a61af66fc99e Initial load
duke
parents:
diff changeset
683 if (!r2->is_con())
a61af66fc99e Initial load
duke
parents:
diff changeset
684 return TypeInt::INT;
a61af66fc99e Initial load
duke
parents:
diff changeset
685
a61af66fc99e Initial load
duke
parents:
diff changeset
686 uint shift = r2->get_con();
a61af66fc99e Initial load
duke
parents:
diff changeset
687 shift &= BitsPerJavaInteger-1; // semantics of Java shifts
a61af66fc99e Initial load
duke
parents:
diff changeset
688 // Shift by a multiple of 32 does nothing:
a61af66fc99e Initial load
duke
parents:
diff changeset
689 if (shift == 0) return t1;
a61af66fc99e Initial load
duke
parents:
diff changeset
690
a61af66fc99e Initial load
duke
parents:
diff changeset
691 // If the shift is a constant, shift the bounds of the type,
a61af66fc99e Initial load
duke
parents:
diff changeset
692 // unless this could lead to an overflow.
a61af66fc99e Initial load
duke
parents:
diff changeset
693 if (!r1->is_con()) {
a61af66fc99e Initial load
duke
parents:
diff changeset
694 jint lo = r1->_lo, hi = r1->_hi;
a61af66fc99e Initial load
duke
parents:
diff changeset
695 if (((lo << shift) >> shift) == lo &&
a61af66fc99e Initial load
duke
parents:
diff changeset
696 ((hi << shift) >> shift) == hi) {
a61af66fc99e Initial load
duke
parents:
diff changeset
697 // No overflow. The range shifts up cleanly.
a61af66fc99e Initial load
duke
parents:
diff changeset
698 return TypeInt::make((jint)lo << (jint)shift,
a61af66fc99e Initial load
duke
parents:
diff changeset
699 (jint)hi << (jint)shift,
a61af66fc99e Initial load
duke
parents:
diff changeset
700 MAX2(r1->_widen,r2->_widen));
a61af66fc99e Initial load
duke
parents:
diff changeset
701 }
a61af66fc99e Initial load
duke
parents:
diff changeset
702 return TypeInt::INT;
a61af66fc99e Initial load
duke
parents:
diff changeset
703 }
a61af66fc99e Initial load
duke
parents:
diff changeset
704
a61af66fc99e Initial load
duke
parents:
diff changeset
705 return TypeInt::make( (jint)r1->get_con() << (jint)shift );
a61af66fc99e Initial load
duke
parents:
diff changeset
706 }
a61af66fc99e Initial load
duke
parents:
diff changeset
707
a61af66fc99e Initial load
duke
parents:
diff changeset
708 //=============================================================================
a61af66fc99e Initial load
duke
parents:
diff changeset
709 //------------------------------Identity---------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
710 Node *LShiftLNode::Identity( PhaseTransform *phase ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
711 const TypeInt *ti = phase->type( in(2) )->isa_int(); // shift count is an int
a61af66fc99e Initial load
duke
parents:
diff changeset
712 return ( ti && ti->is_con() && ( ti->get_con() & ( BitsPerLong - 1 ) ) == 0 ) ? in(1) : this;
a61af66fc99e Initial load
duke
parents:
diff changeset
713 }
a61af66fc99e Initial load
duke
parents:
diff changeset
714
a61af66fc99e Initial load
duke
parents:
diff changeset
715 //------------------------------Ideal------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
716 // If the right input is a constant, and the left input is an add of a
a61af66fc99e Initial load
duke
parents:
diff changeset
717 // constant, flatten the tree: (X+con1)<<con0 ==> X<<con0 + con1<<con0
a61af66fc99e Initial load
duke
parents:
diff changeset
718 Node *LShiftLNode::Ideal(PhaseGVN *phase, bool can_reshape) {
a61af66fc99e Initial load
duke
parents:
diff changeset
719 const Type *t = phase->type( in(2) );
a61af66fc99e Initial load
duke
parents:
diff changeset
720 if( t == Type::TOP ) return NULL; // Right input is dead
a61af66fc99e Initial load
duke
parents:
diff changeset
721 const TypeInt *t2 = t->isa_int();
a61af66fc99e Initial load
duke
parents:
diff changeset
722 if( !t2 || !t2->is_con() ) return NULL; // Right input is a constant
a61af66fc99e Initial load
duke
parents:
diff changeset
723 const int con = t2->get_con() & ( BitsPerLong - 1 ); // masked shift count
a61af66fc99e Initial load
duke
parents:
diff changeset
724
a61af66fc99e Initial load
duke
parents:
diff changeset
725 if ( con == 0 ) return NULL; // let Identity() handle 0 shift count
a61af66fc99e Initial load
duke
parents:
diff changeset
726
a61af66fc99e Initial load
duke
parents:
diff changeset
727 // Left input is an add of a constant?
a61af66fc99e Initial load
duke
parents:
diff changeset
728 Node *add1 = in(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
729 int add1_op = add1->Opcode();
a61af66fc99e Initial load
duke
parents:
diff changeset
730 if( add1_op == Op_AddL ) { // Left input is an add?
a61af66fc99e Initial load
duke
parents:
diff changeset
731 // Avoid dead data cycles from dead loops
a61af66fc99e Initial load
duke
parents:
diff changeset
732 assert( add1 != add1->in(1), "dead loop in LShiftLNode::Ideal" );
a61af66fc99e Initial load
duke
parents:
diff changeset
733 const TypeLong *t12 = phase->type(add1->in(2))->isa_long();
a61af66fc99e Initial load
duke
parents:
diff changeset
734 if( t12 && t12->is_con() ){ // Left input is an add of a con?
a61af66fc99e Initial load
duke
parents:
diff changeset
735 // Compute X << con0
a61af66fc99e Initial load
duke
parents:
diff changeset
736 Node *lsh = phase->transform( new (phase->C, 3) LShiftLNode( add1->in(1), in(2) ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
737 // Compute X<<con0 + (con1<<con0)
a61af66fc99e Initial load
duke
parents:
diff changeset
738 return new (phase->C, 3) AddLNode( lsh, phase->longcon(t12->get_con() << con));
a61af66fc99e Initial load
duke
parents:
diff changeset
739 }
a61af66fc99e Initial load
duke
parents:
diff changeset
740 }
a61af66fc99e Initial load
duke
parents:
diff changeset
741
a61af66fc99e Initial load
duke
parents:
diff changeset
742 // Check for "(x>>c0)<<c0" which just masks off low bits
a61af66fc99e Initial load
duke
parents:
diff changeset
743 if( (add1_op == Op_RShiftL || add1_op == Op_URShiftL ) &&
a61af66fc99e Initial load
duke
parents:
diff changeset
744 add1->in(2) == in(2) )
a61af66fc99e Initial load
duke
parents:
diff changeset
745 // Convert to "(x & -(1<<c0))"
a61af66fc99e Initial load
duke
parents:
diff changeset
746 return new (phase->C, 3) AndLNode(add1->in(1),phase->longcon( -(CONST64(1)<<con)));
a61af66fc99e Initial load
duke
parents:
diff changeset
747
a61af66fc99e Initial load
duke
parents:
diff changeset
748 // Check for "((x>>c0) & Y)<<c0" which just masks off more low bits
a61af66fc99e Initial load
duke
parents:
diff changeset
749 if( add1_op == Op_AndL ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
750 Node *add2 = add1->in(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
751 int add2_op = add2->Opcode();
a61af66fc99e Initial load
duke
parents:
diff changeset
752 if( (add2_op == Op_RShiftL || add2_op == Op_URShiftL ) &&
a61af66fc99e Initial load
duke
parents:
diff changeset
753 add2->in(2) == in(2) ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
754 // Convert to "(x & (Y<<c0))"
a61af66fc99e Initial load
duke
parents:
diff changeset
755 Node *y_sh = phase->transform( new (phase->C, 3) LShiftLNode( add1->in(2), in(2) ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
756 return new (phase->C, 3) AndLNode( add2->in(1), y_sh );
a61af66fc99e Initial load
duke
parents:
diff changeset
757 }
a61af66fc99e Initial load
duke
parents:
diff changeset
758 }
a61af66fc99e Initial load
duke
parents:
diff changeset
759
a61af66fc99e Initial load
duke
parents:
diff changeset
760 // Check for ((x & ((CONST64(1)<<(64-c0))-1)) << c0) which ANDs off high bits
a61af66fc99e Initial load
duke
parents:
diff changeset
761 // before shifting them away.
a61af66fc99e Initial load
duke
parents:
diff changeset
762 const jlong bits_mask = ((jlong)CONST64(1) << (jlong)(BitsPerJavaInteger*2 - con)) - CONST64(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
763 if( add1_op == Op_AndL &&
a61af66fc99e Initial load
duke
parents:
diff changeset
764 phase->type(add1->in(2)) == TypeLong::make( bits_mask ) )
a61af66fc99e Initial load
duke
parents:
diff changeset
765 return new (phase->C, 3) LShiftLNode( add1->in(1), in(2) );
a61af66fc99e Initial load
duke
parents:
diff changeset
766
a61af66fc99e Initial load
duke
parents:
diff changeset
767 return NULL;
a61af66fc99e Initial load
duke
parents:
diff changeset
768 }
a61af66fc99e Initial load
duke
parents:
diff changeset
769
a61af66fc99e Initial load
duke
parents:
diff changeset
770 //------------------------------Value------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
771 // A LShiftLNode shifts its input2 left by input1 amount.
a61af66fc99e Initial load
duke
parents:
diff changeset
772 const Type *LShiftLNode::Value( PhaseTransform *phase ) const {
a61af66fc99e Initial load
duke
parents:
diff changeset
773 const Type *t1 = phase->type( in(1) );
a61af66fc99e Initial load
duke
parents:
diff changeset
774 const Type *t2 = phase->type( in(2) );
a61af66fc99e Initial load
duke
parents:
diff changeset
775 // Either input is TOP ==> the result is TOP
a61af66fc99e Initial load
duke
parents:
diff changeset
776 if( t1 == Type::TOP ) return Type::TOP;
a61af66fc99e Initial load
duke
parents:
diff changeset
777 if( t2 == Type::TOP ) return Type::TOP;
a61af66fc99e Initial load
duke
parents:
diff changeset
778
a61af66fc99e Initial load
duke
parents:
diff changeset
779 // Left input is ZERO ==> the result is ZERO.
a61af66fc99e Initial load
duke
parents:
diff changeset
780 if( t1 == TypeLong::ZERO ) return TypeLong::ZERO;
a61af66fc99e Initial load
duke
parents:
diff changeset
781 // Shift by zero does nothing
a61af66fc99e Initial load
duke
parents:
diff changeset
782 if( t2 == TypeInt::ZERO ) return t1;
a61af66fc99e Initial load
duke
parents:
diff changeset
783
a61af66fc99e Initial load
duke
parents:
diff changeset
784 // Either input is BOTTOM ==> the result is BOTTOM
a61af66fc99e Initial load
duke
parents:
diff changeset
785 if( (t1 == TypeLong::LONG) || (t2 == TypeInt::INT) ||
a61af66fc99e Initial load
duke
parents:
diff changeset
786 (t1 == Type::BOTTOM) || (t2 == Type::BOTTOM) )
a61af66fc99e Initial load
duke
parents:
diff changeset
787 return TypeLong::LONG;
a61af66fc99e Initial load
duke
parents:
diff changeset
788
a61af66fc99e Initial load
duke
parents:
diff changeset
789 const TypeLong *r1 = t1->is_long(); // Handy access
a61af66fc99e Initial load
duke
parents:
diff changeset
790 const TypeInt *r2 = t2->is_int(); // Handy access
a61af66fc99e Initial load
duke
parents:
diff changeset
791
a61af66fc99e Initial load
duke
parents:
diff changeset
792 if (!r2->is_con())
a61af66fc99e Initial load
duke
parents:
diff changeset
793 return TypeLong::LONG;
a61af66fc99e Initial load
duke
parents:
diff changeset
794
a61af66fc99e Initial load
duke
parents:
diff changeset
795 uint shift = r2->get_con();
a61af66fc99e Initial load
duke
parents:
diff changeset
796 shift &= (BitsPerJavaInteger*2)-1; // semantics of Java shifts
a61af66fc99e Initial load
duke
parents:
diff changeset
797 // Shift by a multiple of 64 does nothing:
a61af66fc99e Initial load
duke
parents:
diff changeset
798 if (shift == 0) return t1;
a61af66fc99e Initial load
duke
parents:
diff changeset
799
a61af66fc99e Initial load
duke
parents:
diff changeset
800 // If the shift is a constant, shift the bounds of the type,
a61af66fc99e Initial load
duke
parents:
diff changeset
801 // unless this could lead to an overflow.
a61af66fc99e Initial load
duke
parents:
diff changeset
802 if (!r1->is_con()) {
a61af66fc99e Initial load
duke
parents:
diff changeset
803 jlong lo = r1->_lo, hi = r1->_hi;
a61af66fc99e Initial load
duke
parents:
diff changeset
804 if (((lo << shift) >> shift) == lo &&
a61af66fc99e Initial load
duke
parents:
diff changeset
805 ((hi << shift) >> shift) == hi) {
a61af66fc99e Initial load
duke
parents:
diff changeset
806 // No overflow. The range shifts up cleanly.
a61af66fc99e Initial load
duke
parents:
diff changeset
807 return TypeLong::make((jlong)lo << (jint)shift,
a61af66fc99e Initial load
duke
parents:
diff changeset
808 (jlong)hi << (jint)shift,
a61af66fc99e Initial load
duke
parents:
diff changeset
809 MAX2(r1->_widen,r2->_widen));
a61af66fc99e Initial load
duke
parents:
diff changeset
810 }
a61af66fc99e Initial load
duke
parents:
diff changeset
811 return TypeLong::LONG;
a61af66fc99e Initial load
duke
parents:
diff changeset
812 }
a61af66fc99e Initial load
duke
parents:
diff changeset
813
a61af66fc99e Initial load
duke
parents:
diff changeset
814 return TypeLong::make( (jlong)r1->get_con() << (jint)shift );
a61af66fc99e Initial load
duke
parents:
diff changeset
815 }
a61af66fc99e Initial load
duke
parents:
diff changeset
816
a61af66fc99e Initial load
duke
parents:
diff changeset
817 //=============================================================================
a61af66fc99e Initial load
duke
parents:
diff changeset
818 //------------------------------Identity---------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
819 Node *RShiftINode::Identity( PhaseTransform *phase ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
820 const TypeInt *t2 = phase->type(in(2))->isa_int();
a61af66fc99e Initial load
duke
parents:
diff changeset
821 if( !t2 ) return this;
a61af66fc99e Initial load
duke
parents:
diff changeset
822 if ( t2->is_con() && ( t2->get_con() & ( BitsPerInt - 1 ) ) == 0 )
a61af66fc99e Initial load
duke
parents:
diff changeset
823 return in(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
824
a61af66fc99e Initial load
duke
parents:
diff changeset
825 // Check for useless sign-masking
a61af66fc99e Initial load
duke
parents:
diff changeset
826 if( in(1)->Opcode() == Op_LShiftI &&
a61af66fc99e Initial load
duke
parents:
diff changeset
827 in(1)->req() == 3 &&
a61af66fc99e Initial load
duke
parents:
diff changeset
828 in(1)->in(2) == in(2) &&
a61af66fc99e Initial load
duke
parents:
diff changeset
829 t2->is_con() ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
830 uint shift = t2->get_con();
a61af66fc99e Initial load
duke
parents:
diff changeset
831 shift &= BitsPerJavaInteger-1; // semantics of Java shifts
a61af66fc99e Initial load
duke
parents:
diff changeset
832 // Compute masks for which this shifting doesn't change
a61af66fc99e Initial load
duke
parents:
diff changeset
833 int lo = (-1 << (BitsPerJavaInteger - shift-1)); // FFFF8000
a61af66fc99e Initial load
duke
parents:
diff changeset
834 int hi = ~lo; // 00007FFF
a61af66fc99e Initial load
duke
parents:
diff changeset
835 const TypeInt *t11 = phase->type(in(1)->in(1))->isa_int();
a61af66fc99e Initial load
duke
parents:
diff changeset
836 if( !t11 ) return this;
a61af66fc99e Initial load
duke
parents:
diff changeset
837 // Does actual value fit inside of mask?
a61af66fc99e Initial load
duke
parents:
diff changeset
838 if( lo <= t11->_lo && t11->_hi <= hi )
a61af66fc99e Initial load
duke
parents:
diff changeset
839 return in(1)->in(1); // Then shifting is a nop
a61af66fc99e Initial load
duke
parents:
diff changeset
840 }
a61af66fc99e Initial load
duke
parents:
diff changeset
841
a61af66fc99e Initial load
duke
parents:
diff changeset
842 return this;
a61af66fc99e Initial load
duke
parents:
diff changeset
843 }
a61af66fc99e Initial load
duke
parents:
diff changeset
844
a61af66fc99e Initial load
duke
parents:
diff changeset
845 //------------------------------Ideal------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
846 Node *RShiftINode::Ideal(PhaseGVN *phase, bool can_reshape) {
a61af66fc99e Initial load
duke
parents:
diff changeset
847 // Inputs may be TOP if they are dead.
a61af66fc99e Initial load
duke
parents:
diff changeset
848 const TypeInt *t1 = phase->type( in(1) )->isa_int();
a61af66fc99e Initial load
duke
parents:
diff changeset
849 if( !t1 ) return NULL; // Left input is an integer
a61af66fc99e Initial load
duke
parents:
diff changeset
850 const TypeInt *t2 = phase->type( in(2) )->isa_int();
a61af66fc99e Initial load
duke
parents:
diff changeset
851 if( !t2 || !t2->is_con() ) return NULL; // Right input is a constant
a61af66fc99e Initial load
duke
parents:
diff changeset
852 const TypeInt *t3; // type of in(1).in(2)
a61af66fc99e Initial load
duke
parents:
diff changeset
853 int shift = t2->get_con();
a61af66fc99e Initial load
duke
parents:
diff changeset
854 shift &= BitsPerJavaInteger-1; // semantics of Java shifts
a61af66fc99e Initial load
duke
parents:
diff changeset
855
a61af66fc99e Initial load
duke
parents:
diff changeset
856 if ( shift == 0 ) return NULL; // let Identity() handle 0 shift count
a61af66fc99e Initial load
duke
parents:
diff changeset
857
a61af66fc99e Initial load
duke
parents:
diff changeset
858 // Check for (x & 0xFF000000) >> 24, whose mask can be made smaller.
a61af66fc99e Initial load
duke
parents:
diff changeset
859 // Such expressions arise normally from shift chains like (byte)(x >> 24).
a61af66fc99e Initial load
duke
parents:
diff changeset
860 const Node *mask = in(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
861 if( mask->Opcode() == Op_AndI &&
a61af66fc99e Initial load
duke
parents:
diff changeset
862 (t3 = phase->type(mask->in(2))->isa_int()) &&
a61af66fc99e Initial load
duke
parents:
diff changeset
863 t3->is_con() ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
864 Node *x = mask->in(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
865 jint maskbits = t3->get_con();
a61af66fc99e Initial load
duke
parents:
diff changeset
866 // Convert to "(x >> shift) & (mask >> shift)"
a61af66fc99e Initial load
duke
parents:
diff changeset
867 Node *shr_nomask = phase->transform( new (phase->C, 3) RShiftINode(mask->in(1), in(2)) );
a61af66fc99e Initial load
duke
parents:
diff changeset
868 return new (phase->C, 3) AndINode(shr_nomask, phase->intcon( maskbits >> shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
869 }
a61af66fc99e Initial load
duke
parents:
diff changeset
870
a61af66fc99e Initial load
duke
parents:
diff changeset
871 // Check for "(short[i] <<16)>>16" which simply sign-extends
a61af66fc99e Initial load
duke
parents:
diff changeset
872 const Node *shl = in(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
873 if( shl->Opcode() != Op_LShiftI ) return NULL;
a61af66fc99e Initial load
duke
parents:
diff changeset
874
a61af66fc99e Initial load
duke
parents:
diff changeset
875 if( shift == 16 &&
a61af66fc99e Initial load
duke
parents:
diff changeset
876 (t3 = phase->type(shl->in(2))->isa_int()) &&
a61af66fc99e Initial load
duke
parents:
diff changeset
877 t3->is_con(16) ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
878 Node *ld = shl->in(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
879 if( ld->Opcode() == Op_LoadS ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
880 // Sign extension is just useless here. Return a RShiftI of zero instead
a61af66fc99e Initial load
duke
parents:
diff changeset
881 // returning 'ld' directly. We cannot return an old Node directly as
a61af66fc99e Initial load
duke
parents:
diff changeset
882 // that is the job of 'Identity' calls and Identity calls only work on
a61af66fc99e Initial load
duke
parents:
diff changeset
883 // direct inputs ('ld' is an extra Node removed from 'this'). The
a61af66fc99e Initial load
duke
parents:
diff changeset
884 // combined optimization requires Identity only return direct inputs.
a61af66fc99e Initial load
duke
parents:
diff changeset
885 set_req(1, ld);
a61af66fc99e Initial load
duke
parents:
diff changeset
886 set_req(2, phase->intcon(0));
a61af66fc99e Initial load
duke
parents:
diff changeset
887 return this;
a61af66fc99e Initial load
duke
parents:
diff changeset
888 }
a61af66fc99e Initial load
duke
parents:
diff changeset
889 else if( ld->Opcode() == Op_LoadC )
a61af66fc99e Initial load
duke
parents:
diff changeset
890 // Replace zero-extension-load with sign-extension-load
a61af66fc99e Initial load
duke
parents:
diff changeset
891 return new (phase->C, 3) LoadSNode( ld->in(MemNode::Control),
a61af66fc99e Initial load
duke
parents:
diff changeset
892 ld->in(MemNode::Memory),
a61af66fc99e Initial load
duke
parents:
diff changeset
893 ld->in(MemNode::Address),
a61af66fc99e Initial load
duke
parents:
diff changeset
894 ld->adr_type());
a61af66fc99e Initial load
duke
parents:
diff changeset
895 }
a61af66fc99e Initial load
duke
parents:
diff changeset
896
a61af66fc99e Initial load
duke
parents:
diff changeset
897 // Check for "(byte[i] <<24)>>24" which simply sign-extends
a61af66fc99e Initial load
duke
parents:
diff changeset
898 if( shift == 24 &&
a61af66fc99e Initial load
duke
parents:
diff changeset
899 (t3 = phase->type(shl->in(2))->isa_int()) &&
a61af66fc99e Initial load
duke
parents:
diff changeset
900 t3->is_con(24) ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
901 Node *ld = shl->in(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
902 if( ld->Opcode() == Op_LoadB ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
903 // Sign extension is just useless here
a61af66fc99e Initial load
duke
parents:
diff changeset
904 set_req(1, ld);
a61af66fc99e Initial load
duke
parents:
diff changeset
905 set_req(2, phase->intcon(0));
a61af66fc99e Initial load
duke
parents:
diff changeset
906 return this;
a61af66fc99e Initial load
duke
parents:
diff changeset
907 }
a61af66fc99e Initial load
duke
parents:
diff changeset
908 }
a61af66fc99e Initial load
duke
parents:
diff changeset
909
a61af66fc99e Initial load
duke
parents:
diff changeset
910 return NULL;
a61af66fc99e Initial load
duke
parents:
diff changeset
911 }
a61af66fc99e Initial load
duke
parents:
diff changeset
912
a61af66fc99e Initial load
duke
parents:
diff changeset
913 //------------------------------Value------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
914 // A RShiftINode shifts its input2 right by input1 amount.
a61af66fc99e Initial load
duke
parents:
diff changeset
915 const Type *RShiftINode::Value( PhaseTransform *phase ) const {
a61af66fc99e Initial load
duke
parents:
diff changeset
916 const Type *t1 = phase->type( in(1) );
a61af66fc99e Initial load
duke
parents:
diff changeset
917 const Type *t2 = phase->type( in(2) );
a61af66fc99e Initial load
duke
parents:
diff changeset
918 // Either input is TOP ==> the result is TOP
a61af66fc99e Initial load
duke
parents:
diff changeset
919 if( t1 == Type::TOP ) return Type::TOP;
a61af66fc99e Initial load
duke
parents:
diff changeset
920 if( t2 == Type::TOP ) return Type::TOP;
a61af66fc99e Initial load
duke
parents:
diff changeset
921
a61af66fc99e Initial load
duke
parents:
diff changeset
922 // Left input is ZERO ==> the result is ZERO.
a61af66fc99e Initial load
duke
parents:
diff changeset
923 if( t1 == TypeInt::ZERO ) return TypeInt::ZERO;
a61af66fc99e Initial load
duke
parents:
diff changeset
924 // Shift by zero does nothing
a61af66fc99e Initial load
duke
parents:
diff changeset
925 if( t2 == TypeInt::ZERO ) return t1;
a61af66fc99e Initial load
duke
parents:
diff changeset
926
a61af66fc99e Initial load
duke
parents:
diff changeset
927 // Either input is BOTTOM ==> the result is BOTTOM
a61af66fc99e Initial load
duke
parents:
diff changeset
928 if (t1 == Type::BOTTOM || t2 == Type::BOTTOM)
a61af66fc99e Initial load
duke
parents:
diff changeset
929 return TypeInt::INT;
a61af66fc99e Initial load
duke
parents:
diff changeset
930
a61af66fc99e Initial load
duke
parents:
diff changeset
931 if (t2 == TypeInt::INT)
a61af66fc99e Initial load
duke
parents:
diff changeset
932 return TypeInt::INT;
a61af66fc99e Initial load
duke
parents:
diff changeset
933
a61af66fc99e Initial load
duke
parents:
diff changeset
934 const TypeInt *r1 = t1->is_int(); // Handy access
a61af66fc99e Initial load
duke
parents:
diff changeset
935 const TypeInt *r2 = t2->is_int(); // Handy access
a61af66fc99e Initial load
duke
parents:
diff changeset
936
a61af66fc99e Initial load
duke
parents:
diff changeset
937 // If the shift is a constant, just shift the bounds of the type.
a61af66fc99e Initial load
duke
parents:
diff changeset
938 // For example, if the shift is 31, we just propagate sign bits.
a61af66fc99e Initial load
duke
parents:
diff changeset
939 if (r2->is_con()) {
a61af66fc99e Initial load
duke
parents:
diff changeset
940 uint shift = r2->get_con();
a61af66fc99e Initial load
duke
parents:
diff changeset
941 shift &= BitsPerJavaInteger-1; // semantics of Java shifts
a61af66fc99e Initial load
duke
parents:
diff changeset
942 // Shift by a multiple of 32 does nothing:
a61af66fc99e Initial load
duke
parents:
diff changeset
943 if (shift == 0) return t1;
a61af66fc99e Initial load
duke
parents:
diff changeset
944 // Calculate reasonably aggressive bounds for the result.
a61af66fc99e Initial load
duke
parents:
diff changeset
945 // This is necessary if we are to correctly type things
a61af66fc99e Initial load
duke
parents:
diff changeset
946 // like (x<<24>>24) == ((byte)x).
a61af66fc99e Initial load
duke
parents:
diff changeset
947 jint lo = (jint)r1->_lo >> (jint)shift;
a61af66fc99e Initial load
duke
parents:
diff changeset
948 jint hi = (jint)r1->_hi >> (jint)shift;
a61af66fc99e Initial load
duke
parents:
diff changeset
949 assert(lo <= hi, "must have valid bounds");
a61af66fc99e Initial load
duke
parents:
diff changeset
950 const TypeInt* ti = TypeInt::make(lo, hi, MAX2(r1->_widen,r2->_widen));
a61af66fc99e Initial load
duke
parents:
diff changeset
951 #ifdef ASSERT
a61af66fc99e Initial load
duke
parents:
diff changeset
952 // Make sure we get the sign-capture idiom correct.
a61af66fc99e Initial load
duke
parents:
diff changeset
953 if (shift == BitsPerJavaInteger-1) {
a61af66fc99e Initial load
duke
parents:
diff changeset
954 if (r1->_lo >= 0) assert(ti == TypeInt::ZERO, ">>31 of + is 0");
a61af66fc99e Initial load
duke
parents:
diff changeset
955 if (r1->_hi < 0) assert(ti == TypeInt::MINUS_1, ">>31 of - is -1");
a61af66fc99e Initial load
duke
parents:
diff changeset
956 }
a61af66fc99e Initial load
duke
parents:
diff changeset
957 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
958 return ti;
a61af66fc99e Initial load
duke
parents:
diff changeset
959 }
a61af66fc99e Initial load
duke
parents:
diff changeset
960
a61af66fc99e Initial load
duke
parents:
diff changeset
961 if( !r1->is_con() || !r2->is_con() )
a61af66fc99e Initial load
duke
parents:
diff changeset
962 return TypeInt::INT;
a61af66fc99e Initial load
duke
parents:
diff changeset
963
a61af66fc99e Initial load
duke
parents:
diff changeset
964 // Signed shift right
a61af66fc99e Initial load
duke
parents:
diff changeset
965 return TypeInt::make( r1->get_con() >> (r2->get_con()&31) );
a61af66fc99e Initial load
duke
parents:
diff changeset
966 }
a61af66fc99e Initial load
duke
parents:
diff changeset
967
a61af66fc99e Initial load
duke
parents:
diff changeset
968 //=============================================================================
a61af66fc99e Initial load
duke
parents:
diff changeset
969 //------------------------------Identity---------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
970 Node *RShiftLNode::Identity( PhaseTransform *phase ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
971 const TypeInt *ti = phase->type( in(2) )->isa_int(); // shift count is an int
a61af66fc99e Initial load
duke
parents:
diff changeset
972 return ( ti && ti->is_con() && ( ti->get_con() & ( BitsPerLong - 1 ) ) == 0 ) ? in(1) : this;
a61af66fc99e Initial load
duke
parents:
diff changeset
973 }
a61af66fc99e Initial load
duke
parents:
diff changeset
974
a61af66fc99e Initial load
duke
parents:
diff changeset
975 //------------------------------Value------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
976 // A RShiftLNode shifts its input2 right by input1 amount.
a61af66fc99e Initial load
duke
parents:
diff changeset
977 const Type *RShiftLNode::Value( PhaseTransform *phase ) const {
a61af66fc99e Initial load
duke
parents:
diff changeset
978 const Type *t1 = phase->type( in(1) );
a61af66fc99e Initial load
duke
parents:
diff changeset
979 const Type *t2 = phase->type( in(2) );
a61af66fc99e Initial load
duke
parents:
diff changeset
980 // Either input is TOP ==> the result is TOP
a61af66fc99e Initial load
duke
parents:
diff changeset
981 if( t1 == Type::TOP ) return Type::TOP;
a61af66fc99e Initial load
duke
parents:
diff changeset
982 if( t2 == Type::TOP ) return Type::TOP;
a61af66fc99e Initial load
duke
parents:
diff changeset
983
a61af66fc99e Initial load
duke
parents:
diff changeset
984 // Left input is ZERO ==> the result is ZERO.
a61af66fc99e Initial load
duke
parents:
diff changeset
985 if( t1 == TypeLong::ZERO ) return TypeLong::ZERO;
a61af66fc99e Initial load
duke
parents:
diff changeset
986 // Shift by zero does nothing
a61af66fc99e Initial load
duke
parents:
diff changeset
987 if( t2 == TypeInt::ZERO ) return t1;
a61af66fc99e Initial load
duke
parents:
diff changeset
988
a61af66fc99e Initial load
duke
parents:
diff changeset
989 // Either input is BOTTOM ==> the result is BOTTOM
a61af66fc99e Initial load
duke
parents:
diff changeset
990 if (t1 == Type::BOTTOM || t2 == Type::BOTTOM)
a61af66fc99e Initial load
duke
parents:
diff changeset
991 return TypeLong::LONG;
a61af66fc99e Initial load
duke
parents:
diff changeset
992
a61af66fc99e Initial load
duke
parents:
diff changeset
993 if (t2 == TypeInt::INT)
a61af66fc99e Initial load
duke
parents:
diff changeset
994 return TypeLong::LONG;
a61af66fc99e Initial load
duke
parents:
diff changeset
995
a61af66fc99e Initial load
duke
parents:
diff changeset
996 const TypeLong *r1 = t1->is_long(); // Handy access
a61af66fc99e Initial load
duke
parents:
diff changeset
997 const TypeInt *r2 = t2->is_int (); // Handy access
a61af66fc99e Initial load
duke
parents:
diff changeset
998
a61af66fc99e Initial load
duke
parents:
diff changeset
999 // If the shift is a constant, just shift the bounds of the type.
a61af66fc99e Initial load
duke
parents:
diff changeset
1000 // For example, if the shift is 63, we just propagate sign bits.
a61af66fc99e Initial load
duke
parents:
diff changeset
1001 if (r2->is_con()) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1002 uint shift = r2->get_con();
a61af66fc99e Initial load
duke
parents:
diff changeset
1003 shift &= (2*BitsPerJavaInteger)-1; // semantics of Java shifts
a61af66fc99e Initial load
duke
parents:
diff changeset
1004 // Shift by a multiple of 64 does nothing:
a61af66fc99e Initial load
duke
parents:
diff changeset
1005 if (shift == 0) return t1;
a61af66fc99e Initial load
duke
parents:
diff changeset
1006 // Calculate reasonably aggressive bounds for the result.
a61af66fc99e Initial load
duke
parents:
diff changeset
1007 // This is necessary if we are to correctly type things
a61af66fc99e Initial load
duke
parents:
diff changeset
1008 // like (x<<24>>24) == ((byte)x).
a61af66fc99e Initial load
duke
parents:
diff changeset
1009 jlong lo = (jlong)r1->_lo >> (jlong)shift;
a61af66fc99e Initial load
duke
parents:
diff changeset
1010 jlong hi = (jlong)r1->_hi >> (jlong)shift;
a61af66fc99e Initial load
duke
parents:
diff changeset
1011 assert(lo <= hi, "must have valid bounds");
a61af66fc99e Initial load
duke
parents:
diff changeset
1012 const TypeLong* tl = TypeLong::make(lo, hi, MAX2(r1->_widen,r2->_widen));
a61af66fc99e Initial load
duke
parents:
diff changeset
1013 #ifdef ASSERT
a61af66fc99e Initial load
duke
parents:
diff changeset
1014 // Make sure we get the sign-capture idiom correct.
a61af66fc99e Initial load
duke
parents:
diff changeset
1015 if (shift == (2*BitsPerJavaInteger)-1) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1016 if (r1->_lo >= 0) assert(tl == TypeLong::ZERO, ">>63 of + is 0");
a61af66fc99e Initial load
duke
parents:
diff changeset
1017 if (r1->_hi < 0) assert(tl == TypeLong::MINUS_1, ">>63 of - is -1");
a61af66fc99e Initial load
duke
parents:
diff changeset
1018 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1019 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1020 return tl;
a61af66fc99e Initial load
duke
parents:
diff changeset
1021 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1022
a61af66fc99e Initial load
duke
parents:
diff changeset
1023 return TypeLong::LONG; // Give up
a61af66fc99e Initial load
duke
parents:
diff changeset
1024 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1025
a61af66fc99e Initial load
duke
parents:
diff changeset
1026 //=============================================================================
a61af66fc99e Initial load
duke
parents:
diff changeset
1027 //------------------------------Identity---------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
1028 Node *URShiftINode::Identity( PhaseTransform *phase ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1029 const TypeInt *ti = phase->type( in(2) )->isa_int();
a61af66fc99e Initial load
duke
parents:
diff changeset
1030 if ( ti && ti->is_con() && ( ti->get_con() & ( BitsPerInt - 1 ) ) == 0 ) return in(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
1031
a61af66fc99e Initial load
duke
parents:
diff changeset
1032 // Check for "((x << LogBytesPerWord) + (wordSize-1)) >> LogBytesPerWord" which is just "x".
a61af66fc99e Initial load
duke
parents:
diff changeset
1033 // Happens during new-array length computation.
a61af66fc99e Initial load
duke
parents:
diff changeset
1034 // Safe if 'x' is in the range [0..(max_int>>LogBytesPerWord)]
a61af66fc99e Initial load
duke
parents:
diff changeset
1035 Node *add = in(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
1036 if( add->Opcode() == Op_AddI ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1037 const TypeInt *t2 = phase->type(add->in(2))->isa_int();
a61af66fc99e Initial load
duke
parents:
diff changeset
1038 if( t2 && t2->is_con(wordSize - 1) &&
a61af66fc99e Initial load
duke
parents:
diff changeset
1039 add->in(1)->Opcode() == Op_LShiftI ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1040 // Check that shift_counts are LogBytesPerWord
a61af66fc99e Initial load
duke
parents:
diff changeset
1041 Node *lshift_count = add->in(1)->in(2);
a61af66fc99e Initial load
duke
parents:
diff changeset
1042 const TypeInt *t_lshift_count = phase->type(lshift_count)->isa_int();
a61af66fc99e Initial load
duke
parents:
diff changeset
1043 if( t_lshift_count && t_lshift_count->is_con(LogBytesPerWord) &&
a61af66fc99e Initial load
duke
parents:
diff changeset
1044 t_lshift_count == phase->type(in(2)) ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1045 Node *x = add->in(1)->in(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
1046 const TypeInt *t_x = phase->type(x)->isa_int();
a61af66fc99e Initial load
duke
parents:
diff changeset
1047 if( t_x != NULL && 0 <= t_x->_lo && t_x->_hi <= (max_jint>>LogBytesPerWord) ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1048 return x;
a61af66fc99e Initial load
duke
parents:
diff changeset
1049 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1050 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1051 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1052 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1053
a61af66fc99e Initial load
duke
parents:
diff changeset
1054 return (phase->type(in(2))->higher_equal(TypeInt::ZERO)) ? in(1) : this;
a61af66fc99e Initial load
duke
parents:
diff changeset
1055 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1056
a61af66fc99e Initial load
duke
parents:
diff changeset
1057 //------------------------------Ideal------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
1058 Node *URShiftINode::Ideal(PhaseGVN *phase, bool can_reshape) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1059 const TypeInt *t2 = phase->type( in(2) )->isa_int();
a61af66fc99e Initial load
duke
parents:
diff changeset
1060 if( !t2 || !t2->is_con() ) return NULL; // Right input is a constant
a61af66fc99e Initial load
duke
parents:
diff changeset
1061 const int con = t2->get_con() & 31; // Shift count is always masked
a61af66fc99e Initial load
duke
parents:
diff changeset
1062 if ( con == 0 ) return NULL; // let Identity() handle a 0 shift count
a61af66fc99e Initial load
duke
parents:
diff changeset
1063 // We'll be wanting the right-shift amount as a mask of that many bits
a61af66fc99e Initial load
duke
parents:
diff changeset
1064 const int mask = right_n_bits(BitsPerJavaInteger - con);
a61af66fc99e Initial load
duke
parents:
diff changeset
1065
a61af66fc99e Initial load
duke
parents:
diff changeset
1066 int in1_op = in(1)->Opcode();
a61af66fc99e Initial load
duke
parents:
diff changeset
1067
a61af66fc99e Initial load
duke
parents:
diff changeset
1068 // Check for ((x>>>a)>>>b) and replace with (x>>>(a+b)) when a+b < 32
a61af66fc99e Initial load
duke
parents:
diff changeset
1069 if( in1_op == Op_URShiftI ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1070 const TypeInt *t12 = phase->type( in(1)->in(2) )->isa_int();
a61af66fc99e Initial load
duke
parents:
diff changeset
1071 if( t12 && t12->is_con() ) { // Right input is a constant
a61af66fc99e Initial load
duke
parents:
diff changeset
1072 assert( in(1) != in(1)->in(1), "dead loop in URShiftINode::Ideal" );
a61af66fc99e Initial load
duke
parents:
diff changeset
1073 const int con2 = t12->get_con() & 31; // Shift count is always masked
a61af66fc99e Initial load
duke
parents:
diff changeset
1074 const int con3 = con+con2;
a61af66fc99e Initial load
duke
parents:
diff changeset
1075 if( con3 < 32 ) // Only merge shifts if total is < 32
a61af66fc99e Initial load
duke
parents:
diff changeset
1076 return new (phase->C, 3) URShiftINode( in(1)->in(1), phase->intcon(con3) );
a61af66fc99e Initial load
duke
parents:
diff changeset
1077 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1078 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1079
a61af66fc99e Initial load
duke
parents:
diff changeset
1080 // Check for ((x << z) + Y) >>> z. Replace with x + con>>>z
a61af66fc99e Initial load
duke
parents:
diff changeset
1081 // The idiom for rounding to a power of 2 is "(Q+(2^z-1)) >>> z".
a61af66fc99e Initial load
duke
parents:
diff changeset
1082 // If Q is "X << z" the rounding is useless. Look for patterns like
a61af66fc99e Initial load
duke
parents:
diff changeset
1083 // ((X<<Z) + Y) >>> Z and replace with (X + Y>>>Z) & Z-mask.
a61af66fc99e Initial load
duke
parents:
diff changeset
1084 Node *add = in(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
1085 if( in1_op == Op_AddI ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1086 Node *lshl = add->in(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
1087 if( lshl->Opcode() == Op_LShiftI &&
a61af66fc99e Initial load
duke
parents:
diff changeset
1088 phase->type(lshl->in(2)) == t2 ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1089 Node *y_z = phase->transform( new (phase->C, 3) URShiftINode(add->in(2),in(2)) );
a61af66fc99e Initial load
duke
parents:
diff changeset
1090 Node *sum = phase->transform( new (phase->C, 3) AddINode( lshl->in(1), y_z ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
1091 return new (phase->C, 3) AndINode( sum, phase->intcon(mask) );
a61af66fc99e Initial load
duke
parents:
diff changeset
1092 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1093 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1094
a61af66fc99e Initial load
duke
parents:
diff changeset
1095 // Check for (x & mask) >>> z. Replace with (x >>> z) & (mask >>> z)
a61af66fc99e Initial load
duke
parents:
diff changeset
1096 // This shortens the mask. Also, if we are extracting a high byte and
a61af66fc99e Initial load
duke
parents:
diff changeset
1097 // storing it to a buffer, the mask will be removed completely.
a61af66fc99e Initial load
duke
parents:
diff changeset
1098 Node *andi = in(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
1099 if( in1_op == Op_AndI ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1100 const TypeInt *t3 = phase->type( andi->in(2) )->isa_int();
a61af66fc99e Initial load
duke
parents:
diff changeset
1101 if( t3 && t3->is_con() ) { // Right input is a constant
a61af66fc99e Initial load
duke
parents:
diff changeset
1102 jint mask2 = t3->get_con();
a61af66fc99e Initial load
duke
parents:
diff changeset
1103 mask2 >>= con; // *signed* shift downward (high-order zeroes do not help)
a61af66fc99e Initial load
duke
parents:
diff changeset
1104 Node *newshr = phase->transform( new (phase->C, 3) URShiftINode(andi->in(1), in(2)) );
a61af66fc99e Initial load
duke
parents:
diff changeset
1105 return new (phase->C, 3) AndINode(newshr, phase->intcon(mask2));
a61af66fc99e Initial load
duke
parents:
diff changeset
1106 // The negative values are easier to materialize than positive ones.
a61af66fc99e Initial load
duke
parents:
diff changeset
1107 // A typical case from address arithmetic is ((x & ~15) >> 4).
a61af66fc99e Initial load
duke
parents:
diff changeset
1108 // It's better to change that to ((x >> 4) & ~0) versus
a61af66fc99e Initial load
duke
parents:
diff changeset
1109 // ((x >> 4) & 0x0FFFFFFF). The difference is greatest in LP64.
a61af66fc99e Initial load
duke
parents:
diff changeset
1110 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1111 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1112
a61af66fc99e Initial load
duke
parents:
diff changeset
1113 // Check for "(X << z ) >>> z" which simply zero-extends
a61af66fc99e Initial load
duke
parents:
diff changeset
1114 Node *shl = in(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
1115 if( in1_op == Op_LShiftI &&
a61af66fc99e Initial load
duke
parents:
diff changeset
1116 phase->type(shl->in(2)) == t2 )
a61af66fc99e Initial load
duke
parents:
diff changeset
1117 return new (phase->C, 3) AndINode( shl->in(1), phase->intcon(mask) );
a61af66fc99e Initial load
duke
parents:
diff changeset
1118
a61af66fc99e Initial load
duke
parents:
diff changeset
1119 return NULL;
a61af66fc99e Initial load
duke
parents:
diff changeset
1120 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1121
a61af66fc99e Initial load
duke
parents:
diff changeset
1122 //------------------------------Value------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
1123 // A URShiftINode shifts its input2 right by input1 amount.
a61af66fc99e Initial load
duke
parents:
diff changeset
1124 const Type *URShiftINode::Value( PhaseTransform *phase ) const {
a61af66fc99e Initial load
duke
parents:
diff changeset
1125 // (This is a near clone of RShiftINode::Value.)
a61af66fc99e Initial load
duke
parents:
diff changeset
1126 const Type *t1 = phase->type( in(1) );
a61af66fc99e Initial load
duke
parents:
diff changeset
1127 const Type *t2 = phase->type( in(2) );
a61af66fc99e Initial load
duke
parents:
diff changeset
1128 // Either input is TOP ==> the result is TOP
a61af66fc99e Initial load
duke
parents:
diff changeset
1129 if( t1 == Type::TOP ) return Type::TOP;
a61af66fc99e Initial load
duke
parents:
diff changeset
1130 if( t2 == Type::TOP ) return Type::TOP;
a61af66fc99e Initial load
duke
parents:
diff changeset
1131
a61af66fc99e Initial load
duke
parents:
diff changeset
1132 // Left input is ZERO ==> the result is ZERO.
a61af66fc99e Initial load
duke
parents:
diff changeset
1133 if( t1 == TypeInt::ZERO ) return TypeInt::ZERO;
a61af66fc99e Initial load
duke
parents:
diff changeset
1134 // Shift by zero does nothing
a61af66fc99e Initial load
duke
parents:
diff changeset
1135 if( t2 == TypeInt::ZERO ) return t1;
a61af66fc99e Initial load
duke
parents:
diff changeset
1136
a61af66fc99e Initial load
duke
parents:
diff changeset
1137 // Either input is BOTTOM ==> the result is BOTTOM
a61af66fc99e Initial load
duke
parents:
diff changeset
1138 if (t1 == Type::BOTTOM || t2 == Type::BOTTOM)
a61af66fc99e Initial load
duke
parents:
diff changeset
1139 return TypeInt::INT;
a61af66fc99e Initial load
duke
parents:
diff changeset
1140
a61af66fc99e Initial load
duke
parents:
diff changeset
1141 if (t2 == TypeInt::INT)
a61af66fc99e Initial load
duke
parents:
diff changeset
1142 return TypeInt::INT;
a61af66fc99e Initial load
duke
parents:
diff changeset
1143
a61af66fc99e Initial load
duke
parents:
diff changeset
1144 const TypeInt *r1 = t1->is_int(); // Handy access
a61af66fc99e Initial load
duke
parents:
diff changeset
1145 const TypeInt *r2 = t2->is_int(); // Handy access
a61af66fc99e Initial load
duke
parents:
diff changeset
1146
a61af66fc99e Initial load
duke
parents:
diff changeset
1147 if (r2->is_con()) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1148 uint shift = r2->get_con();
a61af66fc99e Initial load
duke
parents:
diff changeset
1149 shift &= BitsPerJavaInteger-1; // semantics of Java shifts
a61af66fc99e Initial load
duke
parents:
diff changeset
1150 // Shift by a multiple of 32 does nothing:
a61af66fc99e Initial load
duke
parents:
diff changeset
1151 if (shift == 0) return t1;
a61af66fc99e Initial load
duke
parents:
diff changeset
1152 // Calculate reasonably aggressive bounds for the result.
a61af66fc99e Initial load
duke
parents:
diff changeset
1153 jint lo = (juint)r1->_lo >> (juint)shift;
a61af66fc99e Initial load
duke
parents:
diff changeset
1154 jint hi = (juint)r1->_hi >> (juint)shift;
a61af66fc99e Initial load
duke
parents:
diff changeset
1155 if (r1->_hi >= 0 && r1->_lo < 0) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1156 // If the type has both negative and positive values,
a61af66fc99e Initial load
duke
parents:
diff changeset
1157 // there are two separate sub-domains to worry about:
a61af66fc99e Initial load
duke
parents:
diff changeset
1158 // The positive half and the negative half.
a61af66fc99e Initial load
duke
parents:
diff changeset
1159 jint neg_lo = lo;
a61af66fc99e Initial load
duke
parents:
diff changeset
1160 jint neg_hi = (juint)-1 >> (juint)shift;
a61af66fc99e Initial load
duke
parents:
diff changeset
1161 jint pos_lo = (juint) 0 >> (juint)shift;
a61af66fc99e Initial load
duke
parents:
diff changeset
1162 jint pos_hi = hi;
a61af66fc99e Initial load
duke
parents:
diff changeset
1163 lo = MIN2(neg_lo, pos_lo); // == 0
a61af66fc99e Initial load
duke
parents:
diff changeset
1164 hi = MAX2(neg_hi, pos_hi); // == -1 >>> shift;
a61af66fc99e Initial load
duke
parents:
diff changeset
1165 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1166 assert(lo <= hi, "must have valid bounds");
a61af66fc99e Initial load
duke
parents:
diff changeset
1167 const TypeInt* ti = TypeInt::make(lo, hi, MAX2(r1->_widen,r2->_widen));
a61af66fc99e Initial load
duke
parents:
diff changeset
1168 #ifdef ASSERT
a61af66fc99e Initial load
duke
parents:
diff changeset
1169 // Make sure we get the sign-capture idiom correct.
a61af66fc99e Initial load
duke
parents:
diff changeset
1170 if (shift == BitsPerJavaInteger-1) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1171 if (r1->_lo >= 0) assert(ti == TypeInt::ZERO, ">>>31 of + is 0");
a61af66fc99e Initial load
duke
parents:
diff changeset
1172 if (r1->_hi < 0) assert(ti == TypeInt::ONE, ">>>31 of - is +1");
a61af66fc99e Initial load
duke
parents:
diff changeset
1173 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1174 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1175 return ti;
a61af66fc99e Initial load
duke
parents:
diff changeset
1176 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1177
a61af66fc99e Initial load
duke
parents:
diff changeset
1178 //
a61af66fc99e Initial load
duke
parents:
diff changeset
1179 // Do not support shifted oops in info for GC
a61af66fc99e Initial load
duke
parents:
diff changeset
1180 //
a61af66fc99e Initial load
duke
parents:
diff changeset
1181 // else if( t1->base() == Type::InstPtr ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1182 //
a61af66fc99e Initial load
duke
parents:
diff changeset
1183 // const TypeInstPtr *o = t1->is_instptr();
a61af66fc99e Initial load
duke
parents:
diff changeset
1184 // if( t1->singleton() )
a61af66fc99e Initial load
duke
parents:
diff changeset
1185 // return TypeInt::make( ((uint32)o->const_oop() + o->_offset) >> shift );
a61af66fc99e Initial load
duke
parents:
diff changeset
1186 // }
a61af66fc99e Initial load
duke
parents:
diff changeset
1187 // else if( t1->base() == Type::KlassPtr ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1188 // const TypeKlassPtr *o = t1->is_klassptr();
a61af66fc99e Initial load
duke
parents:
diff changeset
1189 // if( t1->singleton() )
a61af66fc99e Initial load
duke
parents:
diff changeset
1190 // return TypeInt::make( ((uint32)o->const_oop() + o->_offset) >> shift );
a61af66fc99e Initial load
duke
parents:
diff changeset
1191 // }
a61af66fc99e Initial load
duke
parents:
diff changeset
1192
a61af66fc99e Initial load
duke
parents:
diff changeset
1193 return TypeInt::INT;
a61af66fc99e Initial load
duke
parents:
diff changeset
1194 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1195
a61af66fc99e Initial load
duke
parents:
diff changeset
1196 //=============================================================================
a61af66fc99e Initial load
duke
parents:
diff changeset
1197 //------------------------------Identity---------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
1198 Node *URShiftLNode::Identity( PhaseTransform *phase ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1199 const TypeInt *ti = phase->type( in(2) )->isa_int(); // shift count is an int
a61af66fc99e Initial load
duke
parents:
diff changeset
1200 return ( ti && ti->is_con() && ( ti->get_con() & ( BitsPerLong - 1 ) ) == 0 ) ? in(1) : this;
a61af66fc99e Initial load
duke
parents:
diff changeset
1201 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1202
a61af66fc99e Initial load
duke
parents:
diff changeset
1203 //------------------------------Ideal------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
1204 Node *URShiftLNode::Ideal(PhaseGVN *phase, bool can_reshape) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1205 const TypeInt *t2 = phase->type( in(2) )->isa_int();
a61af66fc99e Initial load
duke
parents:
diff changeset
1206 if( !t2 || !t2->is_con() ) return NULL; // Right input is a constant
a61af66fc99e Initial load
duke
parents:
diff changeset
1207 const int con = t2->get_con() & ( BitsPerLong - 1 ); // Shift count is always masked
a61af66fc99e Initial load
duke
parents:
diff changeset
1208 if ( con == 0 ) return NULL; // let Identity() handle a 0 shift count
a61af66fc99e Initial load
duke
parents:
diff changeset
1209 // note: mask computation below does not work for 0 shift count
a61af66fc99e Initial load
duke
parents:
diff changeset
1210 // We'll be wanting the right-shift amount as a mask of that many bits
a61af66fc99e Initial load
duke
parents:
diff changeset
1211 const jlong mask = (((jlong)CONST64(1) << (jlong)(BitsPerJavaInteger*2 - con)) -1);
a61af66fc99e Initial load
duke
parents:
diff changeset
1212
a61af66fc99e Initial load
duke
parents:
diff changeset
1213 // Check for ((x << z) + Y) >>> z. Replace with x + con>>>z
a61af66fc99e Initial load
duke
parents:
diff changeset
1214 // The idiom for rounding to a power of 2 is "(Q+(2^z-1)) >>> z".
a61af66fc99e Initial load
duke
parents:
diff changeset
1215 // If Q is "X << z" the rounding is useless. Look for patterns like
a61af66fc99e Initial load
duke
parents:
diff changeset
1216 // ((X<<Z) + Y) >>> Z and replace with (X + Y>>>Z) & Z-mask.
a61af66fc99e Initial load
duke
parents:
diff changeset
1217 Node *add = in(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
1218 if( add->Opcode() == Op_AddL ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1219 Node *lshl = add->in(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
1220 if( lshl->Opcode() == Op_LShiftL &&
a61af66fc99e Initial load
duke
parents:
diff changeset
1221 phase->type(lshl->in(2)) == t2 ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1222 Node *y_z = phase->transform( new (phase->C, 3) URShiftLNode(add->in(2),in(2)) );
a61af66fc99e Initial load
duke
parents:
diff changeset
1223 Node *sum = phase->transform( new (phase->C, 3) AddLNode( lshl->in(1), y_z ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
1224 return new (phase->C, 3) AndLNode( sum, phase->longcon(mask) );
a61af66fc99e Initial load
duke
parents:
diff changeset
1225 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1226 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1227
a61af66fc99e Initial load
duke
parents:
diff changeset
1228 // Check for (x & mask) >>> z. Replace with (x >>> z) & (mask >>> z)
a61af66fc99e Initial load
duke
parents:
diff changeset
1229 // This shortens the mask. Also, if we are extracting a high byte and
a61af66fc99e Initial load
duke
parents:
diff changeset
1230 // storing it to a buffer, the mask will be removed completely.
a61af66fc99e Initial load
duke
parents:
diff changeset
1231 Node *andi = in(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
1232 if( andi->Opcode() == Op_AndL ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1233 const TypeLong *t3 = phase->type( andi->in(2) )->isa_long();
a61af66fc99e Initial load
duke
parents:
diff changeset
1234 if( t3 && t3->is_con() ) { // Right input is a constant
a61af66fc99e Initial load
duke
parents:
diff changeset
1235 jlong mask2 = t3->get_con();
a61af66fc99e Initial load
duke
parents:
diff changeset
1236 mask2 >>= con; // *signed* shift downward (high-order zeroes do not help)
a61af66fc99e Initial load
duke
parents:
diff changeset
1237 Node *newshr = phase->transform( new (phase->C, 3) URShiftLNode(andi->in(1), in(2)) );
a61af66fc99e Initial load
duke
parents:
diff changeset
1238 return new (phase->C, 3) AndLNode(newshr, phase->longcon(mask2));
a61af66fc99e Initial load
duke
parents:
diff changeset
1239 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1240 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1241
a61af66fc99e Initial load
duke
parents:
diff changeset
1242 // Check for "(X << z ) >>> z" which simply zero-extends
a61af66fc99e Initial load
duke
parents:
diff changeset
1243 Node *shl = in(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
1244 if( shl->Opcode() == Op_LShiftL &&
a61af66fc99e Initial load
duke
parents:
diff changeset
1245 phase->type(shl->in(2)) == t2 )
a61af66fc99e Initial load
duke
parents:
diff changeset
1246 return new (phase->C, 3) AndLNode( shl->in(1), phase->longcon(mask) );
a61af66fc99e Initial load
duke
parents:
diff changeset
1247
a61af66fc99e Initial load
duke
parents:
diff changeset
1248 return NULL;
a61af66fc99e Initial load
duke
parents:
diff changeset
1249 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1250
a61af66fc99e Initial load
duke
parents:
diff changeset
1251 //------------------------------Value------------------------------------------
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1252 // A URShiftINode shifts its input2 right by input1 amount.
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1253 const Type *URShiftLNode::Value( PhaseTransform *phase ) const {
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1254 // (This is a near clone of RShiftLNode::Value.)
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1255 const Type *t1 = phase->type( in(1) );
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1256 const Type *t2 = phase->type( in(2) );
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1257 // Either input is TOP ==> the result is TOP
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1258 if( t1 == Type::TOP ) return Type::TOP;
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1259 if( t2 == Type::TOP ) return Type::TOP;
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1260
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1261 // Left input is ZERO ==> the result is ZERO.
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1262 if( t1 == TypeLong::ZERO ) return TypeLong::ZERO;
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1263 // Shift by zero does nothing
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1264 if( t2 == TypeInt::ZERO ) return t1;
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1265
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1266 // Either input is BOTTOM ==> the result is BOTTOM
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1267 if (t1 == Type::BOTTOM || t2 == Type::BOTTOM)
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1268 return TypeLong::LONG;
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1269
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1270 if (t2 == TypeInt::INT)
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1271 return TypeLong::LONG;
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1272
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1273 const TypeLong *r1 = t1->is_long(); // Handy access
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1274 const TypeInt *r2 = t2->is_int (); // Handy access
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1275
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1276 if (r2->is_con()) {
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1277 uint shift = r2->get_con();
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1278 shift &= (2*BitsPerJavaInteger)-1; // semantics of Java shifts
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1279 // Shift by a multiple of 64 does nothing:
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1280 if (shift == 0) return t1;
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1281 // Calculate reasonably aggressive bounds for the result.
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1282 jlong lo = (julong)r1->_lo >> (juint)shift;
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1283 jlong hi = (julong)r1->_hi >> (juint)shift;
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1284 if (r1->_hi >= 0 && r1->_lo < 0) {
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1285 // If the type has both negative and positive values,
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1286 // there are two separate sub-domains to worry about:
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1287 // The positive half and the negative half.
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1288 jlong neg_lo = lo;
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1289 jlong neg_hi = (julong)-1 >> (juint)shift;
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1290 jlong pos_lo = (julong) 0 >> (juint)shift;
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1291 jlong pos_hi = hi;
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1292 //lo = MIN2(neg_lo, pos_lo); // == 0
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1293 lo = neg_lo < pos_lo ? neg_lo : pos_lo;
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1294 //hi = MAX2(neg_hi, pos_hi); // == -1 >>> shift;
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1295 hi = neg_hi > pos_hi ? neg_hi : pos_hi;
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1296 }
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1297 assert(lo <= hi, "must have valid bounds");
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1298 const TypeLong* tl = TypeLong::make(lo, hi, MAX2(r1->_widen,r2->_widen));
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1299 #ifdef ASSERT
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1300 // Make sure we get the sign-capture idiom correct.
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1301 if (shift == (2*BitsPerJavaInteger)-1) {
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1302 if (r1->_lo >= 0) assert(tl == TypeLong::ZERO, ">>>63 of + is 0");
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1303 if (r1->_hi < 0) assert(tl == TypeLong::ONE, ">>>63 of - is +1");
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1304 }
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1305 #endif
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1306 return tl;
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1307 }
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1308
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1309 return TypeLong::LONG; // Give up
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1310 }