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annotate src/cpu/sparc/vm/assembler_sparc.hpp @ 9963:a76b46d8b231
Disabled printing of inlining decisions.
author | Christian Haeubl <haeubl@ssw.jku.at> |
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date | Mon, 10 Jun 2013 12:21:58 +0200 |
parents | ffa87474d7a4 |
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0 | 1 /* |
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2 * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved. |
0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
4 * | |
5 * This code is free software; you can redistribute it and/or modify it | |
6 * under the terms of the GNU General Public License version 2 only, as | |
7 * published by the Free Software Foundation. | |
8 * | |
9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 * version 2 for more details (a copy is included in the LICENSE file that | |
13 * accompanied this code). | |
14 * | |
15 * You should have received a copy of the GNU General Public License version | |
16 * 2 along with this work; if not, write to the Free Software Foundation, | |
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
18 * | |
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
0 | 22 * |
23 */ | |
24 | |
1972 | 25 #ifndef CPU_SPARC_VM_ASSEMBLER_SPARC_HPP |
26 #define CPU_SPARC_VM_ASSEMBLER_SPARC_HPP | |
27 | |
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28 #include "asm/register.hpp" |
0 | 29 |
30 // The SPARC Assembler: Pure assembler doing NO optimizations on the instruction | |
31 // level; i.e., what you write | |
32 // is what you get. The Assembler is generating code into a CodeBuffer. | |
33 | |
34 class Assembler : public AbstractAssembler { | |
35 friend class AbstractAssembler; | |
727 | 36 friend class AddressLiteral; |
0 | 37 |
38 // code patchers need various routines like inv_wdisp() | |
39 friend class NativeInstruction; | |
40 friend class NativeGeneralJump; | |
41 friend class Relocation; | |
42 friend class Label; | |
43 | |
44 public: | |
45 // op carries format info; see page 62 & 267 | |
46 | |
47 enum ops { | |
48 call_op = 1, // fmt 1 | |
49 branch_op = 0, // also sethi (fmt2) | |
50 arith_op = 2, // fmt 3, arith & misc | |
51 ldst_op = 3 // fmt 3, load/store | |
52 }; | |
53 | |
54 enum op2s { | |
55 bpr_op2 = 3, | |
56 fb_op2 = 6, | |
57 fbp_op2 = 5, | |
58 br_op2 = 2, | |
59 bp_op2 = 1, | |
60 cb_op2 = 7, // V8 | |
61 sethi_op2 = 4 | |
62 }; | |
63 | |
64 enum op3s { | |
65 // selected op3s | |
66 add_op3 = 0x00, | |
67 and_op3 = 0x01, | |
68 or_op3 = 0x02, | |
69 xor_op3 = 0x03, | |
70 sub_op3 = 0x04, | |
71 andn_op3 = 0x05, | |
72 orn_op3 = 0x06, | |
73 xnor_op3 = 0x07, | |
74 addc_op3 = 0x08, | |
75 mulx_op3 = 0x09, | |
76 umul_op3 = 0x0a, | |
77 smul_op3 = 0x0b, | |
78 subc_op3 = 0x0c, | |
79 udivx_op3 = 0x0d, | |
80 udiv_op3 = 0x0e, | |
81 sdiv_op3 = 0x0f, | |
82 | |
83 addcc_op3 = 0x10, | |
84 andcc_op3 = 0x11, | |
85 orcc_op3 = 0x12, | |
86 xorcc_op3 = 0x13, | |
87 subcc_op3 = 0x14, | |
88 andncc_op3 = 0x15, | |
89 orncc_op3 = 0x16, | |
90 xnorcc_op3 = 0x17, | |
91 addccc_op3 = 0x18, | |
92 umulcc_op3 = 0x1a, | |
93 smulcc_op3 = 0x1b, | |
94 subccc_op3 = 0x1c, | |
95 udivcc_op3 = 0x1e, | |
96 sdivcc_op3 = 0x1f, | |
97 | |
98 taddcc_op3 = 0x20, | |
99 tsubcc_op3 = 0x21, | |
100 taddcctv_op3 = 0x22, | |
101 tsubcctv_op3 = 0x23, | |
102 mulscc_op3 = 0x24, | |
103 sll_op3 = 0x25, | |
104 sllx_op3 = 0x25, | |
105 srl_op3 = 0x26, | |
106 srlx_op3 = 0x26, | |
107 sra_op3 = 0x27, | |
108 srax_op3 = 0x27, | |
109 rdreg_op3 = 0x28, | |
110 membar_op3 = 0x28, | |
111 | |
112 flushw_op3 = 0x2b, | |
113 movcc_op3 = 0x2c, | |
114 sdivx_op3 = 0x2d, | |
115 popc_op3 = 0x2e, | |
116 movr_op3 = 0x2f, | |
117 | |
118 sir_op3 = 0x30, | |
119 wrreg_op3 = 0x30, | |
120 saved_op3 = 0x31, | |
121 | |
122 fpop1_op3 = 0x34, | |
123 fpop2_op3 = 0x35, | |
124 impdep1_op3 = 0x36, | |
125 impdep2_op3 = 0x37, | |
126 jmpl_op3 = 0x38, | |
127 rett_op3 = 0x39, | |
128 trap_op3 = 0x3a, | |
129 flush_op3 = 0x3b, | |
130 save_op3 = 0x3c, | |
131 restore_op3 = 0x3d, | |
132 done_op3 = 0x3e, | |
133 retry_op3 = 0x3e, | |
134 | |
135 lduw_op3 = 0x00, | |
136 ldub_op3 = 0x01, | |
137 lduh_op3 = 0x02, | |
138 ldd_op3 = 0x03, | |
139 stw_op3 = 0x04, | |
140 stb_op3 = 0x05, | |
141 sth_op3 = 0x06, | |
142 std_op3 = 0x07, | |
143 ldsw_op3 = 0x08, | |
144 ldsb_op3 = 0x09, | |
145 ldsh_op3 = 0x0a, | |
146 ldx_op3 = 0x0b, | |
147 | |
148 ldstub_op3 = 0x0d, | |
149 stx_op3 = 0x0e, | |
150 swap_op3 = 0x0f, | |
151 | |
152 stwa_op3 = 0x14, | |
153 stxa_op3 = 0x1e, | |
154 | |
155 ldf_op3 = 0x20, | |
156 ldfsr_op3 = 0x21, | |
157 ldqf_op3 = 0x22, | |
158 lddf_op3 = 0x23, | |
159 stf_op3 = 0x24, | |
160 stfsr_op3 = 0x25, | |
161 stqf_op3 = 0x26, | |
162 stdf_op3 = 0x27, | |
163 | |
164 prefetch_op3 = 0x2d, | |
165 | |
166 | |
167 ldc_op3 = 0x30, | |
168 ldcsr_op3 = 0x31, | |
169 lddc_op3 = 0x33, | |
170 stc_op3 = 0x34, | |
171 stcsr_op3 = 0x35, | |
172 stdcq_op3 = 0x36, | |
173 stdc_op3 = 0x37, | |
174 | |
175 casa_op3 = 0x3c, | |
176 casxa_op3 = 0x3e, | |
177 | |
3804 | 178 mftoi_op3 = 0x36, |
179 | |
0 | 180 alt_bit_op3 = 0x10, |
181 cc_bit_op3 = 0x10 | |
182 }; | |
183 | |
184 enum opfs { | |
185 // selected opfs | |
186 fmovs_opf = 0x01, | |
187 fmovd_opf = 0x02, | |
188 | |
189 fnegs_opf = 0x05, | |
190 fnegd_opf = 0x06, | |
191 | |
192 fadds_opf = 0x41, | |
193 faddd_opf = 0x42, | |
194 fsubs_opf = 0x45, | |
195 fsubd_opf = 0x46, | |
196 | |
197 fmuls_opf = 0x49, | |
198 fmuld_opf = 0x4a, | |
199 fdivs_opf = 0x4d, | |
200 fdivd_opf = 0x4e, | |
201 | |
202 fcmps_opf = 0x51, | |
203 fcmpd_opf = 0x52, | |
204 | |
205 fstox_opf = 0x81, | |
206 fdtox_opf = 0x82, | |
207 fxtos_opf = 0x84, | |
208 fxtod_opf = 0x88, | |
209 fitos_opf = 0xc4, | |
210 fdtos_opf = 0xc6, | |
211 fitod_opf = 0xc8, | |
212 fstod_opf = 0xc9, | |
213 fstoi_opf = 0xd1, | |
3804 | 214 fdtoi_opf = 0xd2, |
215 | |
216 mdtox_opf = 0x110, | |
217 mstouw_opf = 0x111, | |
218 mstosw_opf = 0x113, | |
219 mxtod_opf = 0x118, | |
220 mwtos_opf = 0x119 | |
0 | 221 }; |
222 | |
3839 | 223 enum RCondition { rc_z = 1, rc_lez = 2, rc_lz = 3, rc_nz = 5, rc_gz = 6, rc_gez = 7, rc_last = rc_gez }; |
0 | 224 |
225 enum Condition { | |
226 // for FBfcc & FBPfcc instruction | |
227 f_never = 0, | |
228 f_notEqual = 1, | |
229 f_notZero = 1, | |
230 f_lessOrGreater = 2, | |
231 f_unorderedOrLess = 3, | |
232 f_less = 4, | |
233 f_unorderedOrGreater = 5, | |
234 f_greater = 6, | |
235 f_unordered = 7, | |
236 f_always = 8, | |
237 f_equal = 9, | |
238 f_zero = 9, | |
239 f_unorderedOrEqual = 10, | |
240 f_greaterOrEqual = 11, | |
241 f_unorderedOrGreaterOrEqual = 12, | |
242 f_lessOrEqual = 13, | |
243 f_unorderedOrLessOrEqual = 14, | |
244 f_ordered = 15, | |
245 | |
246 // V8 coproc, pp 123 v8 manual | |
247 | |
248 cp_always = 8, | |
249 cp_never = 0, | |
250 cp_3 = 7, | |
251 cp_2 = 6, | |
252 cp_2or3 = 5, | |
253 cp_1 = 4, | |
254 cp_1or3 = 3, | |
255 cp_1or2 = 2, | |
256 cp_1or2or3 = 1, | |
257 cp_0 = 9, | |
258 cp_0or3 = 10, | |
259 cp_0or2 = 11, | |
260 cp_0or2or3 = 12, | |
261 cp_0or1 = 13, | |
262 cp_0or1or3 = 14, | |
263 cp_0or1or2 = 15, | |
264 | |
265 | |
266 // for integers | |
267 | |
268 never = 0, | |
269 equal = 1, | |
270 zero = 1, | |
271 lessEqual = 2, | |
272 less = 3, | |
273 lessEqualUnsigned = 4, | |
274 lessUnsigned = 5, | |
275 carrySet = 5, | |
276 negative = 6, | |
277 overflowSet = 7, | |
278 always = 8, | |
279 notEqual = 9, | |
280 notZero = 9, | |
281 greater = 10, | |
282 greaterEqual = 11, | |
283 greaterUnsigned = 12, | |
284 greaterEqualUnsigned = 13, | |
285 carryClear = 13, | |
286 positive = 14, | |
287 overflowClear = 15 | |
288 }; | |
289 | |
290 enum CC { | |
291 icc = 0, xcc = 2, | |
292 // ptr_cc is the correct condition code for a pointer or intptr_t: | |
293 ptr_cc = NOT_LP64(icc) LP64_ONLY(xcc), | |
294 fcc0 = 0, fcc1 = 1, fcc2 = 2, fcc3 = 3 | |
295 }; | |
296 | |
297 enum PrefetchFcn { | |
298 severalReads = 0, oneRead = 1, severalWritesAndPossiblyReads = 2, oneWrite = 3, page = 4 | |
299 }; | |
300 | |
301 public: | |
302 // Helper functions for groups of instructions | |
303 | |
304 enum Predict { pt = 1, pn = 0 }; // pt = predict taken | |
305 | |
306 enum Membar_mask_bits { // page 184, v9 | |
307 StoreStore = 1 << 3, | |
308 LoadStore = 1 << 2, | |
309 StoreLoad = 1 << 1, | |
310 LoadLoad = 1 << 0, | |
311 | |
312 Sync = 1 << 6, | |
313 MemIssue = 1 << 5, | |
314 Lookaside = 1 << 4 | |
315 }; | |
316 | |
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317 static bool is_in_wdisp_range(address a, address b, int nbits) { |
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318 intptr_t d = intptr_t(b) - intptr_t(a); |
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319 return is_simm(d, nbits + 2); |
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320 } |
0 | 321 |
3839 | 322 address target_distance(Label& L) { |
323 // Assembler::target(L) should be called only when | |
324 // a branch instruction is emitted since non-bound | |
325 // labels record current pc() as a branch address. | |
326 if (L.is_bound()) return target(L); | |
327 // Return current address for non-bound labels. | |
328 return pc(); | |
329 } | |
330 | |
1848 | 331 // test if label is in simm16 range in words (wdisp16). |
332 bool is_in_wdisp16_range(Label& L) { | |
3839 | 333 return is_in_wdisp_range(target_distance(L), pc(), 16); |
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334 } |
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335 // test if the distance between two addresses fits in simm30 range in words |
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336 static bool is_in_wdisp30_range(address a, address b) { |
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337 return is_in_wdisp_range(a, b, 30); |
1848 | 338 } |
339 | |
0 | 340 enum ASIs { // page 72, v9 |
3892 | 341 ASI_PRIMARY = 0x80, |
342 ASI_PRIMARY_NOFAULT = 0x82, | |
343 ASI_PRIMARY_LITTLE = 0x88, | |
3854 | 344 // Block initializing store |
345 ASI_ST_BLKINIT_PRIMARY = 0xE2, | |
346 // Most-Recently-Used (MRU) BIS variant | |
347 ASI_ST_BLKINIT_MRU_PRIMARY = 0xF2 | |
0 | 348 // add more from book as needed |
349 }; | |
350 | |
351 protected: | |
352 // helpers | |
353 | |
354 // x is supposed to fit in a field "nbits" wide | |
355 // and be sign-extended. Check the range. | |
356 | |
357 static void assert_signed_range(intptr_t x, int nbits) { | |
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358 assert(nbits == 32 || (-(1 << nbits-1) <= x && x < ( 1 << nbits-1)), |
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359 err_msg("value out of range: x=" INTPTR_FORMAT ", nbits=%d", x, nbits)); |
0 | 360 } |
361 | |
362 static void assert_signed_word_disp_range(intptr_t x, int nbits) { | |
363 assert( (x & 3) == 0, "not word aligned"); | |
364 assert_signed_range(x, nbits + 2); | |
365 } | |
366 | |
367 static void assert_unsigned_const(int x, int nbits) { | |
368 assert( juint(x) < juint(1 << nbits), "unsigned constant out of range"); | |
369 } | |
370 | |
371 // fields: note bits numbered from LSB = 0, | |
372 // fields known by inclusive bit range | |
373 | |
374 static int fmask(juint hi_bit, juint lo_bit) { | |
375 assert( hi_bit >= lo_bit && 0 <= lo_bit && hi_bit < 32, "bad bits"); | |
376 return (1 << ( hi_bit-lo_bit + 1 )) - 1; | |
377 } | |
378 | |
379 // inverse of u_field | |
380 | |
381 static int inv_u_field(int x, int hi_bit, int lo_bit) { | |
382 juint r = juint(x) >> lo_bit; | |
383 r &= fmask( hi_bit, lo_bit); | |
384 return int(r); | |
385 } | |
386 | |
387 | |
388 // signed version: extract from field and sign-extend | |
389 | |
390 static int inv_s_field(int x, int hi_bit, int lo_bit) { | |
391 int sign_shift = 31 - hi_bit; | |
392 return inv_u_field( ((x << sign_shift) >> sign_shift), hi_bit, lo_bit); | |
393 } | |
394 | |
395 // given a field that ranges from hi_bit to lo_bit (inclusive, | |
396 // LSB = 0), and an unsigned value for the field, | |
397 // shift it into the field | |
398 | |
399 #ifdef ASSERT | |
400 static int u_field(int x, int hi_bit, int lo_bit) { | |
401 assert( ( x & ~fmask(hi_bit, lo_bit)) == 0, | |
402 "value out of range"); | |
403 int r = x << lo_bit; | |
404 assert( inv_u_field(r, hi_bit, lo_bit) == x, "just checking"); | |
405 return r; | |
406 } | |
407 #else | |
408 // make sure this is inlined as it will reduce code size significantly | |
409 #define u_field(x, hi_bit, lo_bit) ((x) << (lo_bit)) | |
410 #endif | |
411 | |
412 static int inv_op( int x ) { return inv_u_field(x, 31, 30); } | |
413 static int inv_op2( int x ) { return inv_u_field(x, 24, 22); } | |
414 static int inv_op3( int x ) { return inv_u_field(x, 24, 19); } | |
415 static int inv_cond( int x ){ return inv_u_field(x, 28, 25); } | |
416 | |
417 static bool inv_immed( int x ) { return (x & Assembler::immed(true)) != 0; } | |
418 | |
419 static Register inv_rd( int x ) { return as_Register(inv_u_field(x, 29, 25)); } | |
420 static Register inv_rs1( int x ) { return as_Register(inv_u_field(x, 18, 14)); } | |
421 static Register inv_rs2( int x ) { return as_Register(inv_u_field(x, 4, 0)); } | |
422 | |
423 static int op( int x) { return u_field(x, 31, 30); } | |
424 static int rd( Register r) { return u_field(r->encoding(), 29, 25); } | |
425 static int fcn( int x) { return u_field(x, 29, 25); } | |
426 static int op3( int x) { return u_field(x, 24, 19); } | |
427 static int rs1( Register r) { return u_field(r->encoding(), 18, 14); } | |
428 static int rs2( Register r) { return u_field(r->encoding(), 4, 0); } | |
429 static int annul( bool a) { return u_field(a ? 1 : 0, 29, 29); } | |
430 static int cond( int x) { return u_field(x, 28, 25); } | |
431 static int cond_mov( int x) { return u_field(x, 17, 14); } | |
432 static int rcond( RCondition x) { return u_field(x, 12, 10); } | |
433 static int op2( int x) { return u_field(x, 24, 22); } | |
434 static int predict( bool p) { return u_field(p ? 1 : 0, 19, 19); } | |
435 static int branchcc( CC fcca) { return u_field(fcca, 21, 20); } | |
436 static int cmpcc( CC fcca) { return u_field(fcca, 26, 25); } | |
437 static int imm_asi( int x) { return u_field(x, 12, 5); } | |
438 static int immed( bool i) { return u_field(i ? 1 : 0, 13, 13); } | |
439 static int opf_low6( int w) { return u_field(w, 10, 5); } | |
440 static int opf_low5( int w) { return u_field(w, 9, 5); } | |
441 static int trapcc( CC cc) { return u_field(cc, 12, 11); } | |
442 static int sx( int i) { return u_field(i, 12, 12); } // shift x=1 means 64-bit | |
443 static int opf( int x) { return u_field(x, 13, 5); } | |
444 | |
3839 | 445 static bool is_cbcond( int x ) { |
446 return (VM_Version::has_cbcond() && (inv_cond(x) > rc_last) && | |
447 inv_op(x) == branch_op && inv_op2(x) == bpr_op2); | |
448 } | |
449 static bool is_cxb( int x ) { | |
450 assert(is_cbcond(x), "wrong instruction"); | |
451 return (x & (1<<21)) != 0; | |
452 } | |
453 static int cond_cbcond( int x) { return u_field((((x & 8)<<1) + 8 + (x & 7)), 29, 25); } | |
454 static int inv_cond_cbcond(int x) { | |
455 assert(is_cbcond(x), "wrong instruction"); | |
456 return inv_u_field(x, 27, 25) | (inv_u_field(x, 29, 29)<<3); | |
457 } | |
458 | |
0 | 459 static int opf_cc( CC c, bool useFloat ) { return u_field((useFloat ? 0 : 4) + c, 13, 11); } |
460 static int mov_cc( CC c, bool useFloat ) { return u_field(useFloat ? 0 : 1, 18, 18) | u_field(c, 12, 11); } | |
461 | |
462 static int fd( FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 29, 25); }; | |
463 static int fs1(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 18, 14); }; | |
464 static int fs2(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 4, 0); }; | |
465 | |
466 // some float instructions use this encoding on the op3 field | |
467 static int alt_op3(int op, FloatRegisterImpl::Width w) { | |
468 int r; | |
469 switch(w) { | |
470 case FloatRegisterImpl::S: r = op + 0; break; | |
471 case FloatRegisterImpl::D: r = op + 3; break; | |
472 case FloatRegisterImpl::Q: r = op + 2; break; | |
473 default: ShouldNotReachHere(); break; | |
474 } | |
475 return op3(r); | |
476 } | |
477 | |
478 | |
479 // compute inverse of simm | |
480 static int inv_simm(int x, int nbits) { | |
481 return (int)(x << (32 - nbits)) >> (32 - nbits); | |
482 } | |
483 | |
484 static int inv_simm13( int x ) { return inv_simm(x, 13); } | |
485 | |
486 // signed immediate, in low bits, nbits long | |
487 static int simm(int x, int nbits) { | |
488 assert_signed_range(x, nbits); | |
489 return x & (( 1 << nbits ) - 1); | |
490 } | |
491 | |
492 // compute inverse of wdisp16 | |
493 static intptr_t inv_wdisp16(int x, intptr_t pos) { | |
494 int lo = x & (( 1 << 14 ) - 1); | |
495 int hi = (x >> 20) & 3; | |
496 if (hi >= 2) hi |= ~1; | |
497 return (((hi << 14) | lo) << 2) + pos; | |
498 } | |
499 | |
500 // word offset, 14 bits at LSend, 2 bits at B21, B20 | |
501 static int wdisp16(intptr_t x, intptr_t off) { | |
502 intptr_t xx = x - off; | |
503 assert_signed_word_disp_range(xx, 16); | |
504 int r = (xx >> 2) & ((1 << 14) - 1) | |
505 | ( ( (xx>>(2+14)) & 3 ) << 20 ); | |
506 assert( inv_wdisp16(r, off) == x, "inverse is not inverse"); | |
507 return r; | |
508 } | |
509 | |
3839 | 510 // compute inverse of wdisp10 |
511 static intptr_t inv_wdisp10(int x, intptr_t pos) { | |
512 assert(is_cbcond(x), "wrong instruction"); | |
513 int lo = inv_u_field(x, 12, 5); | |
514 int hi = (x >> 19) & 3; | |
515 if (hi >= 2) hi |= ~1; | |
516 return (((hi << 8) | lo) << 2) + pos; | |
517 } | |
518 | |
519 // word offset for cbcond, 8 bits at [B12,B5], 2 bits at [B20,B19] | |
520 static int wdisp10(intptr_t x, intptr_t off) { | |
521 assert(VM_Version::has_cbcond(), "This CPU does not have CBCOND instruction"); | |
522 intptr_t xx = x - off; | |
523 assert_signed_word_disp_range(xx, 10); | |
524 int r = ( ( (xx >> 2 ) & ((1 << 8) - 1) ) << 5 ) | |
525 | ( ( (xx >> (2+8)) & 3 ) << 19 ); | |
526 // Have to fake cbcond instruction to pass assert in inv_wdisp10() | |
527 assert(inv_wdisp10((r | op(branch_op) | cond_cbcond(rc_last+1) | op2(bpr_op2)), off) == x, "inverse is not inverse"); | |
528 return r; | |
529 } | |
0 | 530 |
531 // word displacement in low-order nbits bits | |
532 | |
533 static intptr_t inv_wdisp( int x, intptr_t pos, int nbits ) { | |
534 int pre_sign_extend = x & (( 1 << nbits ) - 1); | |
535 int r = pre_sign_extend >= ( 1 << (nbits-1) ) | |
536 ? pre_sign_extend | ~(( 1 << nbits ) - 1) | |
537 : pre_sign_extend; | |
538 return (r << 2) + pos; | |
539 } | |
540 | |
541 static int wdisp( intptr_t x, intptr_t off, int nbits ) { | |
542 intptr_t xx = x - off; | |
543 assert_signed_word_disp_range(xx, nbits); | |
544 int r = (xx >> 2) & (( 1 << nbits ) - 1); | |
545 assert( inv_wdisp( r, off, nbits ) == x, "inverse not inverse"); | |
546 return r; | |
547 } | |
548 | |
549 | |
550 // Extract the top 32 bits in a 64 bit word | |
551 static int32_t hi32( int64_t x ) { | |
552 int32_t r = int32_t( (uint64_t)x >> 32 ); | |
553 return r; | |
554 } | |
555 | |
556 // given a sethi instruction, extract the constant, left-justified | |
557 static int inv_hi22( int x ) { | |
558 return x << 10; | |
559 } | |
560 | |
561 // create an imm22 field, given a 32-bit left-justified constant | |
562 static int hi22( int x ) { | |
563 int r = int( juint(x) >> 10 ); | |
564 assert( (r & ~((1 << 22) - 1)) == 0, "just checkin'"); | |
565 return r; | |
566 } | |
567 | |
568 // create a low10 __value__ (not a field) for a given a 32-bit constant | |
569 static int low10( int x ) { | |
570 return x & ((1 << 10) - 1); | |
571 } | |
572 | |
3804 | 573 // instruction only in VIS3 |
574 static void vis3_only() { assert( VM_Version::has_vis3(), "This instruction only works on SPARC with VIS3"); } | |
575 | |
0 | 576 // instruction only in v9 |
577 static void v9_only() { assert( VM_Version::v9_instructions_work(), "This instruction only works on SPARC V9"); } | |
578 | |
579 // instruction only in v8 | |
580 static void v8_only() { assert( VM_Version::v8_instructions_work(), "This instruction only works on SPARC V8"); } | |
581 | |
582 // instruction deprecated in v9 | |
583 static void v9_dep() { } // do nothing for now | |
584 | |
585 // some float instructions only exist for single prec. on v8 | |
586 static void v8_s_only(FloatRegisterImpl::Width w) { if (w != FloatRegisterImpl::S) v9_only(); } | |
587 | |
588 // v8 has no CC field | |
589 static void v8_no_cc(CC cc) { if (cc) v9_only(); } | |
590 | |
591 protected: | |
592 // Simple delay-slot scheme: | |
593 // In order to check the programmer, the assembler keeps track of deley slots. | |
594 // It forbids CTIs in delay slots (conservative, but should be OK). | |
595 // Also, when putting an instruction into a delay slot, you must say | |
596 // asm->delayed()->add(...), in order to check that you don't omit | |
597 // delay-slot instructions. | |
598 // To implement this, we use a simple FSA | |
599 | |
600 #ifdef ASSERT | |
601 #define CHECK_DELAY | |
602 #endif | |
603 #ifdef CHECK_DELAY | |
604 enum Delay_state { no_delay, at_delay_slot, filling_delay_slot } delay_state; | |
605 #endif | |
606 | |
607 public: | |
608 // Tells assembler next instruction must NOT be in delay slot. | |
609 // Use at start of multinstruction macros. | |
610 void assert_not_delayed() { | |
611 // This is a separate overloading to avoid creation of string constants | |
612 // in non-asserted code--with some compilers this pollutes the object code. | |
613 #ifdef CHECK_DELAY | |
614 assert_not_delayed("next instruction should not be a delay slot"); | |
615 #endif | |
616 } | |
617 void assert_not_delayed(const char* msg) { | |
618 #ifdef CHECK_DELAY | |
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619 assert(delay_state == no_delay, msg); |
0 | 620 #endif |
621 } | |
622 | |
623 protected: | |
624 // Delay slot helpers | |
625 // cti is called when emitting control-transfer instruction, | |
626 // BEFORE doing the emitting. | |
627 // Only effective when assertion-checking is enabled. | |
628 void cti() { | |
629 #ifdef CHECK_DELAY | |
630 assert_not_delayed("cti should not be in delay slot"); | |
631 #endif | |
632 } | |
633 | |
634 // called when emitting cti with a delay slot, AFTER emitting | |
635 void has_delay_slot() { | |
636 #ifdef CHECK_DELAY | |
637 assert_not_delayed("just checking"); | |
638 delay_state = at_delay_slot; | |
639 #endif | |
640 } | |
641 | |
3839 | 642 // cbcond instruction should not be generated one after an other |
643 bool cbcond_before() { | |
644 if (offset() == 0) return false; // it is first instruction | |
645 int x = *(int*)(intptr_t(pc()) - 4); // previous instruction | |
646 return is_cbcond(x); | |
647 } | |
648 | |
649 void no_cbcond_before() { | |
650 assert(offset() == 0 || !cbcond_before(), "cbcond should not follow an other cbcond"); | |
651 } | |
652 | |
3851 | 653 public: |
654 | |
3839 | 655 bool use_cbcond(Label& L) { |
656 if (!UseCBCond || cbcond_before()) return false; | |
657 intptr_t x = intptr_t(target_distance(L)) - intptr_t(pc()); | |
658 assert( (x & 3) == 0, "not word aligned"); | |
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659 return is_simm12(x); |
3839 | 660 } |
661 | |
0 | 662 // Tells assembler you know that next instruction is delayed |
663 Assembler* delayed() { | |
664 #ifdef CHECK_DELAY | |
665 assert ( delay_state == at_delay_slot, "delayed instruction is not in delay slot"); | |
666 delay_state = filling_delay_slot; | |
667 #endif | |
668 return this; | |
669 } | |
670 | |
671 void flush() { | |
672 #ifdef CHECK_DELAY | |
673 assert ( delay_state == no_delay, "ending code with a delay slot"); | |
674 #endif | |
675 AbstractAssembler::flush(); | |
676 } | |
677 | |
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678 inline void emit_int32(int); // shadows AbstractAssembler::emit_int32 |
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679 inline void emit_data(int x) { emit_int32(x); } |
0 | 680 inline void emit_data(int, RelocationHolder const&); |
681 inline void emit_data(int, relocInfo::relocType rtype); | |
682 // helper for above fcns | |
683 inline void check_delay(); | |
684 | |
685 | |
686 public: | |
687 // instructions, refer to page numbers in the SPARC Architecture Manual, V9 | |
688 | |
689 // pp 135 (addc was addx in v8) | |
690 | |
727 | 691 inline void add(Register s1, Register s2, Register d ); |
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692 inline void add(Register s1, int simm13a, Register d ); |
0 | 693 |
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694 void addcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(add_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } |
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695 void addcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(add_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
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696 void addc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(addc_op3 ) | rs1(s1) | rs2(s2) ); } |
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697 void addc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(addc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
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698 void addccc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } |
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699 void addccc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
0 | 700 |
3839 | 701 |
0 | 702 // pp 136 |
703 | |
3839 | 704 inline void bpr(RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt = relocInfo::none); |
705 inline void bpr(RCondition c, bool a, Predict p, Register s1, Label& L); | |
0 | 706 |
3851 | 707 // compare and branch |
708 inline void cbcond(Condition c, CC cc, Register s1, Register s2, Label& L); | |
709 inline void cbcond(Condition c, CC cc, Register s1, int simm5, Label& L); | |
710 | |
0 | 711 protected: // use MacroAssembler::br instead |
712 | |
713 // pp 138 | |
714 | |
715 inline void fb( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none ); | |
716 inline void fb( Condition c, bool a, Label& L ); | |
717 | |
718 // pp 141 | |
719 | |
720 inline void fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none ); | |
721 inline void fbp( Condition c, bool a, CC cc, Predict p, Label& L ); | |
722 | |
723 // pp 144 | |
724 | |
725 inline void br( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none ); | |
726 inline void br( Condition c, bool a, Label& L ); | |
727 | |
728 // pp 146 | |
729 | |
730 inline void bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none ); | |
731 inline void bp( Condition c, bool a, CC cc, Predict p, Label& L ); | |
732 | |
733 // pp 121 (V8) | |
734 | |
735 inline void cb( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none ); | |
736 inline void cb( Condition c, bool a, Label& L ); | |
737 | |
738 // pp 149 | |
739 | |
740 inline void call( address d, relocInfo::relocType rt = relocInfo::runtime_call_type ); | |
741 inline void call( Label& L, relocInfo::relocType rt = relocInfo::runtime_call_type ); | |
742 | |
3839 | 743 public: |
744 | |
0 | 745 // pp 150 |
746 | |
747 // These instructions compare the contents of s2 with the contents of | |
748 // memory at address in s1. If the values are equal, the contents of memory | |
749 // at address s1 is swapped with the data in d. If the values are not equal, | |
750 // the the contents of memory at s1 is loaded into d, without the swap. | |
751 | |
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752 void casa( Register s1, Register s2, Register d, int ia = -1 ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(casa_op3 ) | rs1(s1) | (ia == -1 ? immed(true) : imm_asi(ia)) | rs2(s2)); } |
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753 void casxa( Register s1, Register s2, Register d, int ia = -1 ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(casxa_op3) | rs1(s1) | (ia == -1 ? immed(true) : imm_asi(ia)) | rs2(s2)); } |
0 | 754 |
755 // pp 152 | |
756 | |
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757 void udiv( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(udiv_op3 ) | rs1(s1) | rs2(s2)); } |
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758 void udiv( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(udiv_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
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759 void sdiv( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sdiv_op3 ) | rs1(s1) | rs2(s2)); } |
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760 void sdiv( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sdiv_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
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761 void udivcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(udiv_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); } |
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762 void udivcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(udiv_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
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763 void sdivcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sdiv_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); } |
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764 void sdivcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sdiv_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
0 | 765 |
766 // pp 155 | |
767 | |
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768 void done() { v9_only(); cti(); emit_int32( op(arith_op) | fcn(0) | op3(done_op3) ); } |
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769 void retry() { v9_only(); cti(); emit_int32( op(arith_op) | fcn(1) | op3(retry_op3) ); } |
0 | 770 |
771 // pp 156 | |
772 | |
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773 void fadd( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x40 + w) | fs2(s2, w)); } |
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774 void fsub( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x44 + w) | fs2(s2, w)); } |
0 | 775 |
776 // pp 157 | |
777 | |
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778 void fcmp( FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2) { v8_no_cc(cc); emit_int32( op(arith_op) | cmpcc(cc) | op3(fpop2_op3) | fs1(s1, w) | opf(0x50 + w) | fs2(s2, w)); } |
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779 void fcmpe( FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2) { v8_no_cc(cc); emit_int32( op(arith_op) | cmpcc(cc) | op3(fpop2_op3) | fs1(s1, w) | opf(0x54 + w) | fs2(s2, w)); } |
0 | 780 |
781 // pp 159 | |
782 | |
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783 void ftox( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v9_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(fpop1_op3) | opf(0x80 + w) | fs2(s, w)); } |
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784 void ftoi( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::S) | op3(fpop1_op3) | opf(0xd0 + w) | fs2(s, w)); } |
0 | 785 |
786 // pp 160 | |
787 | |
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788 void ftof( FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, dw) | op3(fpop1_op3) | opf(0xc0 + sw + dw*4) | fs2(s, sw)); } |
0 | 789 |
790 // pp 161 | |
791 | |
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792 void fxtof( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v9_only(); emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x80 + w*4) | fs2(s, FloatRegisterImpl::D)); } |
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793 void fitof( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0xc0 + w*4) | fs2(s, FloatRegisterImpl::S)); } |
0 | 794 |
795 // pp 162 | |
796 | |
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797 void fmov( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v8_s_only(w); emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x00 + w) | fs2(s, w)); } |
0 | 798 |
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799 void fneg( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v8_s_only(w); emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x04 + w) | fs2(s, w)); } |
0 | 800 |
801 // page 144 sparc v8 architecture (double prec works on v8 if the source and destination registers are the same). fnegs is the only instruction available | |
802 // on v8 to do negation of single, double and quad precision floats. | |
803 | |
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804 void fneg( FloatRegisterImpl::Width w, FloatRegister sd ) { if (VM_Version::v9_instructions_work()) emit_int32( op(arith_op) | fd(sd, w) | op3(fpop1_op3) | opf(0x04 + w) | fs2(sd, w)); else emit_int32( op(arith_op) | fd(sd, w) | op3(fpop1_op3) | opf(0x05) | fs2(sd, w)); } |
0 | 805 |
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806 void fabs( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v8_s_only(w); emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x08 + w) | fs2(s, w)); } |
0 | 807 |
808 // page 144 sparc v8 architecture (double prec works on v8 if the source and destination registers are the same). fabss is the only instruction available | |
809 // on v8 to do abs operation on single/double/quad precision floats. | |
810 | |
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811 void fabs( FloatRegisterImpl::Width w, FloatRegister sd ) { if (VM_Version::v9_instructions_work()) emit_int32( op(arith_op) | fd(sd, w) | op3(fpop1_op3) | opf(0x08 + w) | fs2(sd, w)); else emit_int32( op(arith_op) | fd(sd, w) | op3(fpop1_op3) | opf(0x09) | fs2(sd, w)); } |
0 | 812 |
813 // pp 163 | |
814 | |
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815 void fmul( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x48 + w) | fs2(s2, w)); } |
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816 void fmul( FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, dw) | op3(fpop1_op3) | fs1(s1, sw) | opf(0x60 + sw + dw*4) | fs2(s2, sw)); } |
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817 void fdiv( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x4c + w) | fs2(s2, w)); } |
0 | 818 |
819 // pp 164 | |
820 | |
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821 void fsqrt( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x28 + w) | fs2(s, w)); } |
0 | 822 |
823 // pp 165 | |
824 | |
825 inline void flush( Register s1, Register s2 ); | |
826 inline void flush( Register s1, int simm13a); | |
827 | |
828 // pp 167 | |
829 | |
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830 void flushw() { v9_only(); emit_int32( op(arith_op) | op3(flushw_op3) ); } |
0 | 831 |
832 // pp 168 | |
833 | |
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834 void illtrap( int const22a) { if (const22a != 0) v9_only(); emit_int32( op(branch_op) | u_field(const22a, 21, 0) ); } |
0 | 835 // v8 unimp == illtrap(0) |
836 | |
837 // pp 169 | |
838 | |
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839 void impdep1( int id1, int const19a ) { v9_only(); emit_int32( op(arith_op) | fcn(id1) | op3(impdep1_op3) | u_field(const19a, 18, 0)); } |
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840 void impdep2( int id1, int const19a ) { v9_only(); emit_int32( op(arith_op) | fcn(id1) | op3(impdep2_op3) | u_field(const19a, 18, 0)); } |
0 | 841 |
842 // pp 149 (v8) | |
843 | |
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844 void cpop1( int opc, int cr1, int cr2, int crd ) { v8_only(); emit_int32( op(arith_op) | fcn(crd) | op3(impdep1_op3) | u_field(cr1, 18, 14) | opf(opc) | u_field(cr2, 4, 0)); } |
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845 void cpop2( int opc, int cr1, int cr2, int crd ) { v8_only(); emit_int32( op(arith_op) | fcn(crd) | op3(impdep2_op3) | u_field(cr1, 18, 14) | opf(opc) | u_field(cr2, 4, 0)); } |
0 | 846 |
847 // pp 170 | |
848 | |
849 void jmpl( Register s1, Register s2, Register d ); | |
850 void jmpl( Register s1, int simm13a, Register d, RelocationHolder const& rspec = RelocationHolder() ); | |
851 | |
852 // 171 | |
853 | |
727 | 854 inline void ldf(FloatRegisterImpl::Width w, Register s1, Register s2, FloatRegister d); |
855 inline void ldf(FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d, RelocationHolder const& rspec = RelocationHolder()); | |
856 | |
0 | 857 |
858 inline void ldfsr( Register s1, Register s2 ); | |
859 inline void ldfsr( Register s1, int simm13a); | |
860 inline void ldxfsr( Register s1, Register s2 ); | |
861 inline void ldxfsr( Register s1, int simm13a); | |
862 | |
863 // pp 94 (v8) | |
864 | |
865 inline void ldc( Register s1, Register s2, int crd ); | |
866 inline void ldc( Register s1, int simm13a, int crd); | |
867 inline void lddc( Register s1, Register s2, int crd ); | |
868 inline void lddc( Register s1, int simm13a, int crd); | |
869 inline void ldcsr( Register s1, Register s2, int crd ); | |
870 inline void ldcsr( Register s1, int simm13a, int crd); | |
871 | |
872 | |
873 // 173 | |
874 | |
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875 void ldfa( FloatRegisterImpl::Width w, Register s1, Register s2, int ia, FloatRegister d ) { v9_only(); emit_int32( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3 | alt_bit_op3, w) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } |
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876 void ldfa( FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d ) { v9_only(); emit_int32( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3 | alt_bit_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
0 | 877 |
878 // pp 175, lduw is ld on v8 | |
879 | |
880 inline void ldsb( Register s1, Register s2, Register d ); | |
881 inline void ldsb( Register s1, int simm13a, Register d); | |
882 inline void ldsh( Register s1, Register s2, Register d ); | |
883 inline void ldsh( Register s1, int simm13a, Register d); | |
884 inline void ldsw( Register s1, Register s2, Register d ); | |
885 inline void ldsw( Register s1, int simm13a, Register d); | |
886 inline void ldub( Register s1, Register s2, Register d ); | |
887 inline void ldub( Register s1, int simm13a, Register d); | |
888 inline void lduh( Register s1, Register s2, Register d ); | |
889 inline void lduh( Register s1, int simm13a, Register d); | |
890 inline void lduw( Register s1, Register s2, Register d ); | |
891 inline void lduw( Register s1, int simm13a, Register d); | |
892 inline void ldx( Register s1, Register s2, Register d ); | |
893 inline void ldx( Register s1, int simm13a, Register d); | |
894 inline void ldd( Register s1, Register s2, Register d ); | |
895 inline void ldd( Register s1, int simm13a, Register d); | |
896 | |
897 // pp 177 | |
898 | |
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899 void ldsba( Register s1, Register s2, int ia, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(ldsb_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } |
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900 void ldsba( Register s1, int simm13a, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(ldsb_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
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901 void ldsha( Register s1, Register s2, int ia, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(ldsh_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } |
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902 void ldsha( Register s1, int simm13a, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(ldsh_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
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903 void ldswa( Register s1, Register s2, int ia, Register d ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(ldsw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } |
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904 void ldswa( Register s1, int simm13a, Register d ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(ldsw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
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905 void lduba( Register s1, Register s2, int ia, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(ldub_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } |
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906 void lduba( Register s1, int simm13a, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(ldub_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
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907 void lduha( Register s1, Register s2, int ia, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(lduh_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } |
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908 void lduha( Register s1, int simm13a, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(lduh_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
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909 void lduwa( Register s1, Register s2, int ia, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(lduw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } |
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910 void lduwa( Register s1, int simm13a, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(lduw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
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911 void ldxa( Register s1, Register s2, int ia, Register d ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(ldx_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } |
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912 void ldxa( Register s1, int simm13a, Register d ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(ldx_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
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913 void ldda( Register s1, Register s2, int ia, Register d ) { v9_dep(); emit_int32( op(ldst_op) | rd(d) | op3(ldd_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } |
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914 void ldda( Register s1, int simm13a, Register d ) { v9_dep(); emit_int32( op(ldst_op) | rd(d) | op3(ldd_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
0 | 915 |
916 // pp 179 | |
917 | |
918 inline void ldstub( Register s1, Register s2, Register d ); | |
919 inline void ldstub( Register s1, int simm13a, Register d); | |
920 | |
921 // pp 180 | |
922 | |
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923 void ldstuba( Register s1, Register s2, int ia, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(ldstub_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } |
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924 void ldstuba( Register s1, int simm13a, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(ldstub_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
0 | 925 |
926 // pp 181 | |
927 | |
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928 void and3( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(and_op3 ) | rs1(s1) | rs2(s2) ); } |
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929 void and3( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(and_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
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930 void andcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(and_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } |
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931 void andcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(and_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
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932 void andn( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(andn_op3 ) | rs1(s1) | rs2(s2) ); } |
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933 void andn( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(andn_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
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934 void andncc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(andn_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } |
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935 void andncc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(andn_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
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936 void or3( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(or_op3 ) | rs1(s1) | rs2(s2) ); } |
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937 void or3( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(or_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
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938 void orcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(or_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } |
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939 void orcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(or_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
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940 void orn( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(orn_op3) | rs1(s1) | rs2(s2) ); } |
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941 void orn( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(orn_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
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942 void orncc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(orn_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } |
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943 void orncc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(orn_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
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944 void xor3( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xor_op3 ) | rs1(s1) | rs2(s2) ); } |
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945 void xor3( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xor_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
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946 void xorcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xor_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } |
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947 void xorcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xor_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
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948 void xnor( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xnor_op3 ) | rs1(s1) | rs2(s2) ); } |
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949 void xnor( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xnor_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
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950 void xnorcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xnor_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } |
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951 void xnorcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xnor_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
0 | 952 |
953 // pp 183 | |
954 | |
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955 void membar( Membar_mask_bits const7a ) { v9_only(); emit_int32( op(arith_op) | op3(membar_op3) | rs1(O7) | immed(true) | u_field( int(const7a), 6, 0)); } |
0 | 956 |
957 // pp 185 | |
958 | |
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959 void fmov( FloatRegisterImpl::Width w, Condition c, bool floatCC, CC cca, FloatRegister s2, FloatRegister d ) { v9_only(); emit_int32( op(arith_op) | fd(d, w) | op3(fpop2_op3) | cond_mov(c) | opf_cc(cca, floatCC) | opf_low6(w) | fs2(s2, w)); } |
0 | 960 |
961 // pp 189 | |
962 | |
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963 void fmov( FloatRegisterImpl::Width w, RCondition c, Register s1, FloatRegister s2, FloatRegister d ) { v9_only(); emit_int32( op(arith_op) | fd(d, w) | op3(fpop2_op3) | rs1(s1) | rcond(c) | opf_low5(4 + w) | fs2(s2, w)); } |
0 | 964 |
965 // pp 191 | |
966 | |
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967 void movcc( Condition c, bool floatCC, CC cca, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(movcc_op3) | mov_cc(cca, floatCC) | cond_mov(c) | rs2(s2) ); } |
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968 void movcc( Condition c, bool floatCC, CC cca, int simm11a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(movcc_op3) | mov_cc(cca, floatCC) | cond_mov(c) | immed(true) | simm(simm11a, 11) ); } |
0 | 969 |
970 // pp 195 | |
971 | |
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972 void movr( RCondition c, Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(movr_op3) | rs1(s1) | rcond(c) | rs2(s2) ); } |
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973 void movr( RCondition c, Register s1, int simm10a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(movr_op3) | rs1(s1) | rcond(c) | immed(true) | simm(simm10a, 10) ); } |
0 | 974 |
975 // pp 196 | |
976 | |
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977 void mulx( Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(mulx_op3 ) | rs1(s1) | rs2(s2) ); } |
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978 void mulx( Register s1, int simm13a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(mulx_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
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979 void sdivx( Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(sdivx_op3) | rs1(s1) | rs2(s2) ); } |
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980 void sdivx( Register s1, int simm13a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(sdivx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
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981 void udivx( Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(udivx_op3) | rs1(s1) | rs2(s2) ); } |
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982 void udivx( Register s1, int simm13a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(udivx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
0 | 983 |
984 // pp 197 | |
985 | |
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986 void umul( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(umul_op3 ) | rs1(s1) | rs2(s2) ); } |
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987 void umul( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(umul_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
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988 void smul( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(smul_op3 ) | rs1(s1) | rs2(s2) ); } |
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989 void smul( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(smul_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
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990 void umulcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(umul_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } |
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991 void umulcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(umul_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
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992 void smulcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(smul_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } |
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993 void smulcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(smul_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
0 | 994 |
995 // pp 199 | |
996 | |
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997 void mulscc( Register s1, Register s2, Register d ) { v9_dep(); emit_int32( op(arith_op) | rd(d) | op3(mulscc_op3) | rs1(s1) | rs2(s2) ); } |
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998 void mulscc( Register s1, int simm13a, Register d ) { v9_dep(); emit_int32( op(arith_op) | rd(d) | op3(mulscc_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
0 | 999 |
1000 // pp 201 | |
1001 | |
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1002 void nop() { emit_int32( op(branch_op) | op2(sethi_op2) ); } |
0 | 1003 |
1004 | |
1005 // pp 202 | |
1006 | |
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1007 void popc( Register s, Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(popc_op3) | rs2(s)); } |
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1008 void popc( int simm13a, Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(popc_op3) | immed(true) | simm(simm13a, 13)); } |
0 | 1009 |
1010 // pp 203 | |
1011 | |
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1012 void prefetch( Register s1, Register s2, PrefetchFcn f) { v9_only(); emit_int32( op(ldst_op) | fcn(f) | op3(prefetch_op3) | rs1(s1) | rs2(s2) ); } |
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1013 void prefetch( Register s1, int simm13a, PrefetchFcn f) { v9_only(); emit_data( op(ldst_op) | fcn(f) | op3(prefetch_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); } |
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1014 |
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1015 void prefetcha( Register s1, Register s2, int ia, PrefetchFcn f ) { v9_only(); emit_int32( op(ldst_op) | fcn(f) | op3(prefetch_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } |
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1016 void prefetcha( Register s1, int simm13a, PrefetchFcn f ) { v9_only(); emit_int32( op(ldst_op) | fcn(f) | op3(prefetch_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
0 | 1017 |
1018 // pp 208 | |
1019 | |
1020 // not implementing read privileged register | |
1021 | |
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1022 inline void rdy( Register d) { v9_dep(); emit_int32( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(0, 18, 14)); } |
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1023 inline void rdccr( Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(2, 18, 14)); } |
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1024 inline void rdasi( Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(3, 18, 14)); } |
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1025 inline void rdtick( Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(4, 18, 14)); } // Spoon! |
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1026 inline void rdpc( Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(5, 18, 14)); } |
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1027 inline void rdfprs( Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(6, 18, 14)); } |
0 | 1028 |
1029 // pp 213 | |
1030 | |
1031 inline void rett( Register s1, Register s2); | |
1032 inline void rett( Register s1, int simm13a, relocInfo::relocType rt = relocInfo::none); | |
1033 | |
1034 // pp 214 | |
1035 | |
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1036 void save( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(save_op3) | rs1(s1) | rs2(s2) ); } |
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1037 void save( Register s1, int simm13a, Register d ) { |
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1038 // make sure frame is at least large enough for the register save area |
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1039 assert(-simm13a >= 16 * wordSize, "frame too small"); |
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1040 emit_int32( op(arith_op) | rd(d) | op3(save_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); |
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1041 } |
0 | 1042 |
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1043 void restore( Register s1 = G0, Register s2 = G0, Register d = G0 ) { emit_int32( op(arith_op) | rd(d) | op3(restore_op3) | rs1(s1) | rs2(s2) ); } |
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1044 void restore( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(restore_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
0 | 1045 |
1046 // pp 216 | |
1047 | |
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1048 void saved() { v9_only(); emit_int32( op(arith_op) | fcn(0) | op3(saved_op3)); } |
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1049 void restored() { v9_only(); emit_int32( op(arith_op) | fcn(1) | op3(saved_op3)); } |
0 | 1050 |
1051 // pp 217 | |
1052 | |
1053 inline void sethi( int imm22a, Register d, RelocationHolder const& rspec = RelocationHolder() ); | |
1054 // pp 218 | |
1055 | |
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1056 void sll( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(0) | rs2(s2) ); } |
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1057 void sll( Register s1, int imm5a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0) ); } |
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1058 void srl( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(0) | rs2(s2) ); } |
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1059 void srl( Register s1, int imm5a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0) ); } |
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1060 void sra( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(0) | rs2(s2) ); } |
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1061 void sra( Register s1, int imm5a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0) ); } |
0 | 1062 |
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1063 void sllx( Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(1) | rs2(s2) ); } |
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1064 void sllx( Register s1, int imm6a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0) ); } |
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1065 void srlx( Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(1) | rs2(s2) ); } |
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1066 void srlx( Register s1, int imm6a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0) ); } |
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1067 void srax( Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(1) | rs2(s2) ); } |
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1068 void srax( Register s1, int imm6a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0) ); } |
0 | 1069 |
1070 // pp 220 | |
1071 | |
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1072 void sir( int simm13a ) { emit_int32( op(arith_op) | fcn(15) | op3(sir_op3) | immed(true) | simm(simm13a, 13)); } |
0 | 1073 |
1074 // pp 221 | |
1075 | |
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1076 void stbar() { emit_int32( op(arith_op) | op3(membar_op3) | u_field(15, 18, 14)); } |
0 | 1077 |
1078 // pp 222 | |
1079 | |
1006
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1080 inline void stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2); |
0 | 1081 inline void stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a); |
1082 | |
1083 inline void stfsr( Register s1, Register s2 ); | |
1084 inline void stfsr( Register s1, int simm13a); | |
1085 inline void stxfsr( Register s1, Register s2 ); | |
1086 inline void stxfsr( Register s1, int simm13a); | |
1087 | |
1088 // pp 224 | |
1089 | |
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1090 void stfa( FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2, int ia ) { v9_only(); emit_int32( op(ldst_op) | fd(d, w) | alt_op3(stf_op3 | alt_bit_op3, w) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } |
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1091 void stfa( FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a ) { v9_only(); emit_int32( op(ldst_op) | fd(d, w) | alt_op3(stf_op3 | alt_bit_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
0 | 1092 |
1093 // p 226 | |
1094 | |
1095 inline void stb( Register d, Register s1, Register s2 ); | |
1096 inline void stb( Register d, Register s1, int simm13a); | |
1097 inline void sth( Register d, Register s1, Register s2 ); | |
1098 inline void sth( Register d, Register s1, int simm13a); | |
1099 inline void stw( Register d, Register s1, Register s2 ); | |
1100 inline void stw( Register d, Register s1, int simm13a); | |
1101 inline void stx( Register d, Register s1, Register s2 ); | |
1102 inline void stx( Register d, Register s1, int simm13a); | |
1103 inline void std( Register d, Register s1, Register s2 ); | |
1104 inline void std( Register d, Register s1, int simm13a); | |
1105 | |
1106 // pp 177 | |
1107 | |
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1108 void stba( Register d, Register s1, Register s2, int ia ) { emit_int32( op(ldst_op) | rd(d) | op3(stb_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } |
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1109 void stba( Register d, Register s1, int simm13a ) { emit_int32( op(ldst_op) | rd(d) | op3(stb_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
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1110 void stha( Register d, Register s1, Register s2, int ia ) { emit_int32( op(ldst_op) | rd(d) | op3(sth_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } |
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1111 void stha( Register d, Register s1, int simm13a ) { emit_int32( op(ldst_op) | rd(d) | op3(sth_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
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1112 void stwa( Register d, Register s1, Register s2, int ia ) { emit_int32( op(ldst_op) | rd(d) | op3(stw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } |
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1113 void stwa( Register d, Register s1, int simm13a ) { emit_int32( op(ldst_op) | rd(d) | op3(stw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
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1114 void stxa( Register d, Register s1, Register s2, int ia ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(stx_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } |
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1115 void stxa( Register d, Register s1, int simm13a ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(stx_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
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1116 void stda( Register d, Register s1, Register s2, int ia ) { emit_int32( op(ldst_op) | rd(d) | op3(std_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } |
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1117 void stda( Register d, Register s1, int simm13a ) { emit_int32( op(ldst_op) | rd(d) | op3(std_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
0 | 1118 |
1119 // pp 97 (v8) | |
1120 | |
1121 inline void stc( int crd, Register s1, Register s2 ); | |
1122 inline void stc( int crd, Register s1, int simm13a); | |
1123 inline void stdc( int crd, Register s1, Register s2 ); | |
1124 inline void stdc( int crd, Register s1, int simm13a); | |
1125 inline void stcsr( int crd, Register s1, Register s2 ); | |
1126 inline void stcsr( int crd, Register s1, int simm13a); | |
1127 inline void stdcq( int crd, Register s1, Register s2 ); | |
1128 inline void stdcq( int crd, Register s1, int simm13a); | |
1129 | |
1130 // pp 230 | |
1131 | |
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1132 void sub( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sub_op3 ) | rs1(s1) | rs2(s2) ); } |
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1133 void sub( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sub_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
2008 | 1134 |
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1135 void subcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sub_op3 | cc_bit_op3 ) | rs1(s1) | rs2(s2) ); } |
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1136 void subcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sub_op3 | cc_bit_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
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1137 void subc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(subc_op3 ) | rs1(s1) | rs2(s2) ); } |
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1138 void subc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(subc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
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1139 void subccc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(subc_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } |
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1140 void subccc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(subc_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
0 | 1141 |
1142 // pp 231 | |
1143 | |
1144 inline void swap( Register s1, Register s2, Register d ); | |
1145 inline void swap( Register s1, int simm13a, Register d); | |
1146 | |
1147 // pp 232 | |
1148 | |
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1149 void swapa( Register s1, Register s2, int ia, Register d ) { v9_dep(); emit_int32( op(ldst_op) | rd(d) | op3(swap_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } |
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1150 void swapa( Register s1, int simm13a, Register d ) { v9_dep(); emit_int32( op(ldst_op) | rd(d) | op3(swap_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
0 | 1151 |
1152 // pp 234, note op in book is wrong, see pp 268 | |
1153 | |
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1154 void taddcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(taddcc_op3 ) | rs1(s1) | rs2(s2) ); } |
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1155 void taddcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(taddcc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
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1156 void taddcctv( Register s1, Register s2, Register d ) { v9_dep(); emit_int32( op(arith_op) | rd(d) | op3(taddcctv_op3) | rs1(s1) | rs2(s2) ); } |
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1157 void taddcctv( Register s1, int simm13a, Register d ) { v9_dep(); emit_int32( op(arith_op) | rd(d) | op3(taddcctv_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
0 | 1158 |
1159 // pp 235 | |
1160 | |
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1161 void tsubcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(tsubcc_op3 ) | rs1(s1) | rs2(s2) ); } |
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1162 void tsubcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(tsubcc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
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1163 void tsubcctv( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(tsubcctv_op3) | rs1(s1) | rs2(s2) ); } |
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1164 void tsubcctv( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(tsubcctv_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } |
0 | 1165 |
1166 // pp 237 | |
1167 | |
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1168 void trap( Condition c, CC cc, Register s1, Register s2 ) { v8_no_cc(cc); emit_int32( op(arith_op) | cond(c) | op3(trap_op3) | rs1(s1) | trapcc(cc) | rs2(s2)); } |
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1169 void trap( Condition c, CC cc, Register s1, int trapa ) { v8_no_cc(cc); emit_int32( op(arith_op) | cond(c) | op3(trap_op3) | rs1(s1) | trapcc(cc) | immed(true) | u_field(trapa, 6, 0)); } |
0 | 1170 // simple uncond. trap |
1171 void trap( int trapa ) { trap( always, icc, G0, trapa ); } | |
1172 | |
1173 // pp 239 omit write priv register for now | |
1174 | |
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1175 inline void wry( Register d) { v9_dep(); emit_int32( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(0, 29, 25)); } |
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1176 inline void wrccr(Register s) { v9_only(); emit_int32( op(arith_op) | rs1(s) | op3(wrreg_op3) | u_field(2, 29, 25)); } |
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1177 inline void wrccr(Register s, int simm13a) { v9_only(); emit_int32( op(arith_op) | |
0 | 1178 rs1(s) | |
1179 op3(wrreg_op3) | | |
1180 u_field(2, 29, 25) | | |
3892 | 1181 immed(true) | |
0 | 1182 simm(simm13a, 13)); } |
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1183 inline void wrasi(Register d) { v9_only(); emit_int32( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(3, 29, 25)); } |
3892 | 1184 // wrasi(d, imm) stores (d xor imm) to asi |
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1185 inline void wrasi(Register d, int simm13a) { v9_only(); emit_int32( op(arith_op) | rs1(d) | op3(wrreg_op3) | |
3892 | 1186 u_field(3, 29, 25) | immed(true) | simm(simm13a, 13)); } |
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1187 inline void wrfprs( Register d) { v9_only(); emit_int32( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(6, 29, 25)); } |
0 | 1188 |
3804 | 1189 |
1190 // VIS3 instructions | |
1191 | |
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1192 void movstosw( FloatRegister s, Register d ) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mstosw_opf) | fs2(s, FloatRegisterImpl::S)); } |
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1193 void movstouw( FloatRegister s, Register d ) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mstouw_opf) | fs2(s, FloatRegisterImpl::S)); } |
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1194 void movdtox( FloatRegister s, Register d ) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mdtox_opf) | fs2(s, FloatRegisterImpl::D)); } |
3804 | 1195 |
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1196 void movwtos( Register s, FloatRegister d ) { vis3_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::S) | op3(mftoi_op3) | opf(mwtos_opf) | rs2(s)); } |
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1197 void movxtod( Register s, FloatRegister d ) { vis3_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(mftoi_op3) | opf(mxtod_opf) | rs2(s)); } |
3804 | 1198 |
0 | 1199 // Creation |
1200 Assembler(CodeBuffer* code) : AbstractAssembler(code) { | |
1201 #ifdef CHECK_DELAY | |
1202 delay_state = no_delay; | |
1203 #endif | |
1204 } | |
1205 }; | |
1206 | |
1972 | 1207 #endif // CPU_SPARC_VM_ASSEMBLER_SPARC_HPP |