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annotate src/cpu/sparc/vm/nativeInst_sparc.hpp @ 18527:b31ae5af9fa3
Merge.
author | Doug Simon <doug.simon@oracle.com> |
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date | Wed, 26 Nov 2014 12:51:31 +0100 |
parents | 89152779163c |
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0 | 1 /* |
17524 | 2 * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. |
0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
4 * | |
5 * This code is free software; you can redistribute it and/or modify it | |
6 * under the terms of the GNU General Public License version 2 only, as | |
7 * published by the Free Software Foundation. | |
8 * | |
9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 * version 2 for more details (a copy is included in the LICENSE file that | |
13 * accompanied this code). | |
14 * | |
15 * You should have received a copy of the GNU General Public License version | |
16 * 2 along with this work; if not, write to the Free Software Foundation, | |
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
18 * | |
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
0 | 22 * |
23 */ | |
24 | |
1972 | 25 #ifndef CPU_SPARC_VM_NATIVEINST_SPARC_HPP |
26 #define CPU_SPARC_VM_NATIVEINST_SPARC_HPP | |
27 | |
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28 #include "asm/macroAssembler.hpp" |
1972 | 29 #include "memory/allocation.hpp" |
30 #include "runtime/icache.hpp" | |
31 #include "runtime/os.hpp" | |
32 #include "utilities/top.hpp" | |
33 | |
0 | 34 // We have interface for the following instructions: |
35 // - NativeInstruction | |
36 // - - NativeCall | |
37 // - - NativeFarCall | |
38 // - - NativeMovConstReg | |
39 // - - NativeMovConstRegPatching | |
40 // - - NativeMovRegMem | |
41 // - - NativeMovRegMemPatching | |
42 // - - NativeJump | |
43 // - - NativeGeneralJump | |
44 // - - NativeIllegalInstruction | |
45 // The base class for different kinds of native instruction abstractions. | |
46 // Provides the primitive operations to manipulate code relative to this. | |
47 class NativeInstruction VALUE_OBJ_CLASS_SPEC { | |
48 friend class Relocation; | |
49 | |
50 public: | |
51 enum Sparc_specific_constants { | |
52 nop_instruction_size = 4 | |
53 }; | |
54 | |
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55 bool is_dtrace_trap(); |
0 | 56 bool is_nop() { return long_at(0) == nop_instruction(); } |
57 bool is_call() { return is_op(long_at(0), Assembler::call_op); } | |
11233 | 58 bool is_call_reg() { return is_op(long_at(0), Assembler::arith_op); } |
0 | 59 bool is_sethi() { return (is_op2(long_at(0), Assembler::sethi_op2) |
60 && inv_rd(long_at(0)) != G0); } | |
61 | |
62 bool sets_cc() { | |
63 // conservative (returns true for some instructions that do not set the | |
64 // the condition code, such as, "save". | |
65 // Does not return true for the deprecated tagged instructions, such as, TADDcc | |
66 int x = long_at(0); | |
67 return (is_op(x, Assembler::arith_op) && | |
68 (inv_op3(x) & Assembler::cc_bit_op3) == Assembler::cc_bit_op3); | |
69 } | |
70 bool is_illegal(); | |
71 bool is_zombie() { | |
72 int x = long_at(0); | |
73 return is_op3(x, | |
10997 | 74 Assembler::ldsw_op3, |
0 | 75 Assembler::ldst_op) |
76 && Assembler::inv_rs1(x) == G0 | |
77 && Assembler::inv_rd(x) == O7; | |
78 } | |
79 bool is_ic_miss_trap(); // Inline-cache uses a trap to detect a miss | |
80 bool is_return() { | |
81 // is it the output of MacroAssembler::ret or MacroAssembler::retl? | |
82 int x = long_at(0); | |
83 const int pc_return_offset = 8; // see frame_sparc.hpp | |
84 return is_op3(x, Assembler::jmpl_op3, Assembler::arith_op) | |
85 && (inv_rs1(x) == I7 || inv_rs1(x) == O7) | |
86 && inv_immed(x) && inv_simm(x, 13) == pc_return_offset | |
87 && inv_rd(x) == G0; | |
88 } | |
89 bool is_int_jump() { | |
90 // is it the output of MacroAssembler::b? | |
91 int x = long_at(0); | |
92 return is_op2(x, Assembler::bp_op2) || is_op2(x, Assembler::br_op2); | |
93 } | |
94 bool is_float_jump() { | |
95 // is it the output of MacroAssembler::fb? | |
96 int x = long_at(0); | |
97 return is_op2(x, Assembler::fbp_op2) || is_op2(x, Assembler::fb_op2); | |
98 } | |
99 bool is_jump() { | |
100 return is_int_jump() || is_float_jump(); | |
101 } | |
102 bool is_cond_jump() { | |
103 int x = long_at(0); | |
104 return (is_int_jump() && Assembler::inv_cond(x) != Assembler::always) || | |
105 (is_float_jump() && Assembler::inv_cond(x) != Assembler::f_always); | |
106 } | |
107 | |
108 bool is_stack_bang() { | |
109 int x = long_at(0); | |
110 return is_op3(x, Assembler::stw_op3, Assembler::ldst_op) && | |
111 (inv_rd(x) == G0) && (inv_rs1(x) == SP) && (inv_rs2(x) == G3_scratch); | |
112 } | |
113 | |
114 bool is_prefetch() { | |
115 int x = long_at(0); | |
116 return is_op3(x, Assembler::prefetch_op3, Assembler::ldst_op); | |
117 } | |
118 | |
119 bool is_membar() { | |
120 int x = long_at(0); | |
121 return is_op3(x, Assembler::membar_op3, Assembler::arith_op) && | |
122 (inv_rd(x) == G0) && (inv_rs1(x) == O7); | |
123 } | |
124 | |
125 bool is_safepoint_poll() { | |
126 int x = long_at(0); | |
127 #ifdef _LP64 | |
128 return is_op3(x, Assembler::ldx_op3, Assembler::ldst_op) && | |
129 #else | |
130 return is_op3(x, Assembler::lduw_op3, Assembler::ldst_op) && | |
131 #endif | |
132 (inv_rd(x) == G0) && (inv_immed(x) ? Assembler::inv_simm13(x) == 0 : inv_rs2(x) == G0); | |
133 } | |
134 | |
135 bool is_zero_test(Register ®); | |
136 bool is_load_store_with_small_offset(Register reg); | |
137 | |
138 public: | |
139 #ifdef ASSERT | |
140 static int rdpc_instruction() { return Assembler::op(Assembler::arith_op ) | Assembler::op3(Assembler::rdreg_op3) | Assembler::u_field(5, 18, 14) | Assembler::rd(O7); } | |
141 #else | |
142 // Temporary fix: in optimized mode, u_field is a macro for efficiency reasons (see Assembler::u_field) - needs to be fixed | |
143 static int rdpc_instruction() { return Assembler::op(Assembler::arith_op ) | Assembler::op3(Assembler::rdreg_op3) | u_field(5, 18, 14) | Assembler::rd(O7); } | |
144 #endif | |
145 static int nop_instruction() { return Assembler::op(Assembler::branch_op) | Assembler::op2(Assembler::sethi_op2); } | |
146 static int illegal_instruction(); // the output of __ breakpoint_trap() | |
147 static int call_instruction(address destination, address pc) { return Assembler::op(Assembler::call_op) | Assembler::wdisp((intptr_t)destination, (intptr_t)pc, 30); } | |
148 | |
149 static int branch_instruction(Assembler::op2s op2val, Assembler::Condition c, bool a) { | |
150 return Assembler::op(Assembler::branch_op) | Assembler::op2(op2val) | Assembler::annul(a) | Assembler::cond(c); | |
151 } | |
152 | |
153 static int op3_instruction(Assembler::ops opval, Register rd, Assembler::op3s op3val, Register rs1, int simm13a) { | |
154 return Assembler::op(opval) | Assembler::rd(rd) | Assembler::op3(op3val) | Assembler::rs1(rs1) | Assembler::immed(true) | Assembler::simm(simm13a, 13); | |
155 } | |
156 | |
157 static int sethi_instruction(Register rd, int imm22a) { | |
158 return Assembler::op(Assembler::branch_op) | Assembler::rd(rd) | Assembler::op2(Assembler::sethi_op2) | Assembler::hi22(imm22a); | |
159 } | |
160 | |
161 protected: | |
162 address addr_at(int offset) const { return address(this) + offset; } | |
163 int long_at(int offset) const { return *(int*)addr_at(offset); } | |
164 void set_long_at(int offset, int i); /* deals with I-cache */ | |
165 void set_jlong_at(int offset, jlong i); /* deals with I-cache */ | |
166 void set_addr_at(int offset, address x); /* deals with I-cache */ | |
167 | |
168 address instruction_address() const { return addr_at(0); } | |
169 address next_instruction_address() const { return addr_at(BytesPerInstWord); } | |
170 | |
171 static bool is_op( int x, Assembler::ops opval) { | |
172 return Assembler::inv_op(x) == opval; | |
173 } | |
174 static bool is_op2(int x, Assembler::op2s op2val) { | |
175 return Assembler::inv_op(x) == Assembler::branch_op && Assembler::inv_op2(x) == op2val; | |
176 } | |
177 static bool is_op3(int x, Assembler::op3s op3val, Assembler::ops opval) { | |
178 return Assembler::inv_op(x) == opval && Assembler::inv_op3(x) == op3val; | |
179 } | |
180 | |
181 // utilities to help subclasses decode: | |
182 static Register inv_rd( int x ) { return Assembler::inv_rd( x); } | |
183 static Register inv_rs1( int x ) { return Assembler::inv_rs1(x); } | |
184 static Register inv_rs2( int x ) { return Assembler::inv_rs2(x); } | |
185 | |
186 static bool inv_immed( int x ) { return Assembler::inv_immed(x); } | |
187 static bool inv_annul( int x ) { return (Assembler::annul(true) & x) != 0; } | |
188 static int inv_cond( int x ) { return Assembler::inv_cond(x); } | |
189 | |
190 static int inv_op( int x ) { return Assembler::inv_op( x); } | |
191 static int inv_op2( int x ) { return Assembler::inv_op2(x); } | |
192 static int inv_op3( int x ) { return Assembler::inv_op3(x); } | |
193 | |
194 static int inv_simm( int x, int nbits ) { return Assembler::inv_simm(x, nbits); } | |
195 static intptr_t inv_wdisp( int x, int nbits ) { return Assembler::inv_wdisp( x, 0, nbits); } | |
196 static intptr_t inv_wdisp16( int x ) { return Assembler::inv_wdisp16(x, 0); } | |
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197 static int branch_destination_offset(int x) { return MacroAssembler::branch_destination(x, 0); } |
0 | 198 static int patch_branch_destination_offset(int dest_offset, int x) { |
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199 return MacroAssembler::patched_branch(dest_offset, x, 0); |
0 | 200 } |
201 | |
202 // utility for checking if x is either of 2 small constants | |
203 static bool is_either(int x, int k1, int k2) { | |
204 // return x == k1 || x == k2; | |
205 return (1 << x) & (1 << k1 | 1 << k2); | |
206 } | |
207 | |
208 // utility for checking overflow of signed instruction fields | |
209 static bool fits_in_simm(int x, int nbits) { | |
210 // cf. Assembler::assert_signed_range() | |
211 // return -(1 << nbits-1) <= x && x < ( 1 << nbits-1), | |
212 return (unsigned)(x + (1 << nbits-1)) < (unsigned)(1 << nbits); | |
213 } | |
214 | |
215 // set a signed immediate field | |
216 static int set_simm(int insn, int imm, int nbits) { | |
217 return (insn &~ Assembler::simm(-1, nbits)) | Assembler::simm(imm, nbits); | |
218 } | |
219 | |
220 // set a wdisp field (disp should be the difference of two addresses) | |
221 static int set_wdisp(int insn, intptr_t disp, int nbits) { | |
222 return (insn &~ Assembler::wdisp((intptr_t)-4, (intptr_t)0, nbits)) | Assembler::wdisp(disp, 0, nbits); | |
223 } | |
224 | |
225 static int set_wdisp16(int insn, intptr_t disp) { | |
226 return (insn &~ Assembler::wdisp16((intptr_t)-4, 0)) | Assembler::wdisp16(disp, 0); | |
227 } | |
228 | |
229 // get a simm13 field from an arithmetic or memory instruction | |
230 static int get_simm13(int insn) { | |
231 assert(is_either(Assembler::inv_op(insn), | |
232 Assembler::arith_op, Assembler::ldst_op) && | |
233 (insn & Assembler::immed(true)), "must have a simm13 field"); | |
234 return Assembler::inv_simm(insn, 13); | |
235 } | |
236 | |
237 // set the simm13 field of an arithmetic or memory instruction | |
238 static bool set_simm13(int insn, int imm) { | |
239 get_simm13(insn); // tickle the assertion check | |
240 return set_simm(insn, imm, 13); | |
241 } | |
242 | |
243 // combine the fields of a sethi stream (7 instructions ) and an add, jmp or ld/st | |
244 static intptr_t data64( address pc, int arith_insn ) { | |
245 assert(is_op2(*(unsigned int *)pc, Assembler::sethi_op2), "must be sethi"); | |
246 intptr_t hi = (intptr_t)gethi( (unsigned int *)pc ); | |
247 intptr_t lo = (intptr_t)get_simm13(arith_insn); | |
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248 assert((unsigned)lo < (1 << 10), "offset field of set_metadata must be 10 bits"); |
0 | 249 return hi | lo; |
250 } | |
251 | |
252 // Regenerate the instruction sequence that performs the 64 bit | |
253 // sethi. This only does the sethi. The disp field (bottom 10 bits) | |
605 | 254 // must be handled separately. |
0 | 255 static void set_data64_sethi(address instaddr, intptr_t x); |
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256 static void verify_data64_sethi(address instaddr, intptr_t x); |
0 | 257 |
258 // combine the fields of a sethi/simm13 pair (simm13 = or, add, jmpl, ld/st) | |
259 static int data32(int sethi_insn, int arith_insn) { | |
260 assert(is_op2(sethi_insn, Assembler::sethi_op2), "must be sethi"); | |
261 int hi = Assembler::inv_hi22(sethi_insn); | |
262 int lo = get_simm13(arith_insn); | |
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263 assert((unsigned)lo < (1 << 10), "offset field of set_metadata must be 10 bits"); |
0 | 264 return hi | lo; |
265 } | |
266 | |
267 static int set_data32_sethi(int sethi_insn, int imm) { | |
268 // note that Assembler::hi22 clips the low 10 bits for us | |
269 assert(is_op2(sethi_insn, Assembler::sethi_op2), "must be sethi"); | |
270 return (sethi_insn &~ Assembler::hi22(-1)) | Assembler::hi22(imm); | |
271 } | |
272 | |
273 static int set_data32_simm13(int arith_insn, int imm) { | |
274 get_simm13(arith_insn); // tickle the assertion check | |
275 int imm10 = Assembler::low10(imm); | |
276 return (arith_insn &~ Assembler::simm(-1, 13)) | Assembler::simm(imm10, 13); | |
277 } | |
278 | |
279 static int low10(int imm) { | |
280 return Assembler::low10(imm); | |
281 } | |
282 | |
283 // Perform the inverse of the LP64 Macroassembler::sethi | |
284 // routine. Extracts the 54 bits of address from the instruction | |
285 // stream. This routine must agree with the sethi routine in | |
286 // assembler_inline_sparc.hpp | |
287 static address gethi( unsigned int *pc ) { | |
288 int i = 0; | |
289 uintptr_t adr; | |
290 // We first start out with the real sethi instruction | |
291 assert(is_op2(*pc, Assembler::sethi_op2), "in gethi - must be sethi"); | |
292 adr = (unsigned int)Assembler::inv_hi22( *(pc++) ); | |
293 i++; | |
294 while ( i < 7 ) { | |
295 // We're done if we hit a nop | |
296 if ( (int)*pc == nop_instruction() ) break; | |
297 assert ( Assembler::inv_op(*pc) == Assembler::arith_op, "in gethi - must be arith_op" ); | |
298 switch ( Assembler::inv_op3(*pc) ) { | |
299 case Assembler::xor_op3: | |
300 adr ^= (intptr_t)get_simm13( *pc ); | |
301 return ( (address)adr ); | |
302 break; | |
303 case Assembler::sll_op3: | |
304 adr <<= ( *pc & 0x3f ); | |
305 break; | |
306 case Assembler::or_op3: | |
307 adr |= (intptr_t)get_simm13( *pc ); | |
308 break; | |
309 default: | |
310 assert ( 0, "in gethi - Should not reach here" ); | |
311 break; | |
312 } | |
313 pc++; | |
314 i++; | |
315 } | |
316 return ( (address)adr ); | |
317 } | |
318 | |
319 public: | |
320 void verify(); | |
321 void print(); | |
322 | |
323 // unit test stuff | |
324 static void test() {} // override for testing | |
325 | |
326 inline friend NativeInstruction* nativeInstruction_at(address address); | |
327 }; | |
328 | |
329 inline NativeInstruction* nativeInstruction_at(address address) { | |
330 NativeInstruction* inst = (NativeInstruction*)address; | |
331 #ifdef ASSERT | |
332 inst->verify(); | |
333 #endif | |
334 return inst; | |
335 } | |
336 | |
337 | |
338 | |
339 //----------------------------------------------------------------------------- | |
340 | |
341 // The NativeCall is an abstraction for accessing/manipulating native call imm32 instructions. | |
342 // (used to manipulate inline caches, primitive & dll calls, etc.) | |
343 inline NativeCall* nativeCall_at(address instr); | |
344 inline NativeCall* nativeCall_overwriting_at(address instr, | |
345 address destination); | |
346 inline NativeCall* nativeCall_before(address return_address); | |
347 class NativeCall: public NativeInstruction { | |
348 public: | |
349 enum Sparc_specific_constants { | |
350 instruction_size = 8, | |
351 return_address_offset = 8, | |
352 call_displacement_width = 30, | |
353 displacement_offset = 0, | |
354 instruction_offset = 0 | |
355 }; | |
356 address instruction_address() const { return addr_at(0); } | |
357 address next_instruction_address() const { return addr_at(instruction_size); } | |
358 address return_address() const { return addr_at(return_address_offset); } | |
359 | |
360 address destination() const { return inv_wdisp(long_at(0), call_displacement_width) + instruction_address(); } | |
361 address displacement_address() const { return addr_at(displacement_offset); } | |
362 void set_destination(address dest) { set_long_at(0, set_wdisp(long_at(0), dest - instruction_address(), call_displacement_width)); } | |
363 void set_destination_mt_safe(address dest); | |
364 | |
365 void verify_alignment() {} // do nothing on sparc | |
366 void verify(); | |
367 void print(); | |
368 | |
369 // unit test stuff | |
370 static void test(); | |
371 | |
372 // Creation | |
373 friend inline NativeCall* nativeCall_at(address instr); | |
374 friend NativeCall* nativeCall_overwriting_at(address instr, address destination = NULL) { | |
375 // insert a "blank" call: | |
376 NativeCall* call = (NativeCall*)instr; | |
377 call->set_long_at(0 * BytesPerInstWord, call_instruction(destination, instr)); | |
378 call->set_long_at(1 * BytesPerInstWord, nop_instruction()); | |
379 assert(call->addr_at(2 * BytesPerInstWord) - instr == instruction_size, "instruction size"); | |
380 // check its structure now: | |
381 assert(nativeCall_at(instr)->destination() == destination, "correct call destination"); | |
382 return call; | |
383 } | |
384 | |
385 friend inline NativeCall* nativeCall_before(address return_address) { | |
386 NativeCall* call = (NativeCall*)(return_address - return_address_offset); | |
387 #ifdef ASSERT | |
388 call->verify(); | |
389 #endif | |
390 return call; | |
391 } | |
392 | |
393 static bool is_call_at(address instr) { | |
394 return nativeInstruction_at(instr)->is_call(); | |
395 } | |
396 | |
397 static bool is_call_before(address instr) { | |
398 return nativeInstruction_at(instr - return_address_offset)->is_call(); | |
399 } | |
400 | |
401 static bool is_call_to(address instr, address target) { | |
402 return nativeInstruction_at(instr)->is_call() && | |
403 nativeCall_at(instr)->destination() == target; | |
404 } | |
405 | |
406 // MT-safe patching of a call instruction. | |
407 static void insert(address code_pos, address entry) { | |
408 (void)nativeCall_overwriting_at(code_pos, entry); | |
409 } | |
410 | |
411 static void replace_mt_safe(address instr_addr, address code_buffer); | |
412 }; | |
413 inline NativeCall* nativeCall_at(address instr) { | |
414 NativeCall* call = (NativeCall*)instr; | |
415 #ifdef ASSERT | |
416 call->verify(); | |
417 #endif | |
418 return call; | |
419 } | |
420 | |
11233 | 421 class NativeCallReg: public NativeInstruction { |
422 public: | |
423 enum Sparc_specific_constants { | |
424 instruction_size = 8, | |
425 return_address_offset = 8, | |
426 instruction_offset = 0 | |
427 }; | |
428 | |
429 address next_instruction_address() const { | |
430 return addr_at(instruction_size); | |
431 } | |
432 }; | |
433 | |
0 | 434 // The NativeFarCall is an abstraction for accessing/manipulating native call-anywhere |
435 // instructions in the sparcv9 vm. Used to call native methods which may be loaded | |
436 // anywhere in the address space, possibly out of reach of a call instruction. | |
437 | |
438 #ifndef _LP64 | |
439 | |
440 // On 32-bit systems, a far call is the same as a near one. | |
441 class NativeFarCall; | |
442 inline NativeFarCall* nativeFarCall_at(address instr); | |
443 class NativeFarCall : public NativeCall { | |
444 public: | |
445 friend inline NativeFarCall* nativeFarCall_at(address instr) { return (NativeFarCall*)nativeCall_at(instr); } | |
446 friend NativeFarCall* nativeFarCall_overwriting_at(address instr, address destination = NULL) | |
447 { return (NativeFarCall*)nativeCall_overwriting_at(instr, destination); } | |
448 friend NativeFarCall* nativeFarCall_before(address return_address) | |
449 { return (NativeFarCall*)nativeCall_before(return_address); } | |
450 }; | |
451 | |
452 #else | |
453 | |
454 // The format of this extended-range call is: | |
455 // jumpl_to addr, lreg | |
456 // == sethi %hi54(addr), O7 ; jumpl O7, %lo10(addr), O7 ; <delay> | |
457 // That is, it is essentially the same as a NativeJump. | |
458 class NativeFarCall; | |
459 inline NativeFarCall* nativeFarCall_overwriting_at(address instr, address destination); | |
460 inline NativeFarCall* nativeFarCall_at(address instr); | |
461 class NativeFarCall: public NativeInstruction { | |
462 public: | |
463 enum Sparc_specific_constants { | |
464 // instruction_size includes the delay slot instruction. | |
465 instruction_size = 9 * BytesPerInstWord, | |
466 return_address_offset = 9 * BytesPerInstWord, | |
467 jmpl_offset = 7 * BytesPerInstWord, | |
468 displacement_offset = 0, | |
469 instruction_offset = 0 | |
470 }; | |
471 address instruction_address() const { return addr_at(0); } | |
472 address next_instruction_address() const { return addr_at(instruction_size); } | |
473 address return_address() const { return addr_at(return_address_offset); } | |
474 | |
475 address destination() const { | |
476 return (address) data64(addr_at(0), long_at(jmpl_offset)); | |
477 } | |
478 address displacement_address() const { return addr_at(displacement_offset); } | |
479 void set_destination(address dest); | |
480 | |
481 bool destination_is_compiled_verified_entry_point(); | |
482 | |
483 void verify(); | |
484 void print(); | |
485 | |
486 // unit test stuff | |
487 static void test(); | |
488 | |
489 // Creation | |
490 friend inline NativeFarCall* nativeFarCall_at(address instr) { | |
491 NativeFarCall* call = (NativeFarCall*)instr; | |
492 #ifdef ASSERT | |
493 call->verify(); | |
494 #endif | |
495 return call; | |
496 } | |
497 | |
498 friend inline NativeFarCall* nativeFarCall_overwriting_at(address instr, address destination = NULL) { | |
499 Unimplemented(); | |
500 NativeFarCall* call = (NativeFarCall*)instr; | |
501 return call; | |
502 } | |
503 | |
504 friend NativeFarCall* nativeFarCall_before(address return_address) { | |
505 NativeFarCall* call = (NativeFarCall*)(return_address - return_address_offset); | |
506 #ifdef ASSERT | |
507 call->verify(); | |
508 #endif | |
509 return call; | |
510 } | |
511 | |
512 static bool is_call_at(address instr); | |
513 | |
514 // MT-safe patching of a call instruction. | |
515 static void insert(address code_pos, address entry) { | |
516 (void)nativeFarCall_overwriting_at(code_pos, entry); | |
517 } | |
518 static void replace_mt_safe(address instr_addr, address code_buffer); | |
519 }; | |
520 | |
521 #endif // _LP64 | |
522 | |
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523 // An interface for accessing/manipulating native set_metadata imm, reg instructions. |
0 | 524 // (used to manipulate inlined data references, etc.) |
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525 // set_metadata imm, reg |
0 | 526 // == sethi %hi22(imm), reg ; add reg, %lo10(imm), reg |
527 class NativeMovConstReg; | |
528 inline NativeMovConstReg* nativeMovConstReg_at(address address); | |
529 class NativeMovConstReg: public NativeInstruction { | |
530 public: | |
531 enum Sparc_specific_constants { | |
532 sethi_offset = 0, | |
533 #ifdef _LP64 | |
534 add_offset = 7 * BytesPerInstWord, | |
535 instruction_size = 8 * BytesPerInstWord | |
536 #else | |
537 add_offset = 4, | |
538 instruction_size = 8 | |
539 #endif | |
540 }; | |
541 | |
542 address instruction_address() const { return addr_at(0); } | |
543 address next_instruction_address() const { return addr_at(instruction_size); } | |
544 | |
545 // (The [set_]data accessor respects oop_type relocs also.) | |
546 intptr_t data() const; | |
547 void set_data(intptr_t x); | |
548 | |
549 // report the destination register | |
550 Register destination() { return inv_rd(long_at(sethi_offset)); } | |
551 | |
552 void verify(); | |
553 void print(); | |
554 | |
555 // unit test stuff | |
556 static void test(); | |
557 | |
558 // Creation | |
559 friend inline NativeMovConstReg* nativeMovConstReg_at(address address) { | |
560 NativeMovConstReg* test = (NativeMovConstReg*)address; | |
561 #ifdef ASSERT | |
562 test->verify(); | |
563 #endif | |
564 return test; | |
565 } | |
566 | |
567 | |
568 friend NativeMovConstReg* nativeMovConstReg_before(address address) { | |
569 NativeMovConstReg* test = (NativeMovConstReg*)(address - instruction_size); | |
570 #ifdef ASSERT | |
571 test->verify(); | |
572 #endif | |
573 return test; | |
574 } | |
575 | |
576 }; | |
577 | |
578 | |
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579 // An interface for accessing/manipulating native set_metadata imm, reg instructions. |
0 | 580 // (used to manipulate inlined data references, etc.) |
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581 // set_metadata imm, reg |
0 | 582 // == sethi %hi22(imm), reg; nop; add reg, %lo10(imm), reg |
583 // | |
584 // Note that it is identical to NativeMovConstReg with the exception of a nop between the | |
585 // sethi and the add. The nop is required to be in the delay slot of the call instruction | |
586 // which overwrites the sethi during patching. | |
587 class NativeMovConstRegPatching; | |
588 inline NativeMovConstRegPatching* nativeMovConstRegPatching_at(address address);class NativeMovConstRegPatching: public NativeInstruction { | |
589 public: | |
590 enum Sparc_specific_constants { | |
591 sethi_offset = 0, | |
592 #ifdef _LP64 | |
593 nop_offset = 7 * BytesPerInstWord, | |
594 #else | |
595 nop_offset = sethi_offset + BytesPerInstWord, | |
596 #endif | |
597 add_offset = nop_offset + BytesPerInstWord, | |
598 instruction_size = add_offset + BytesPerInstWord | |
599 }; | |
600 | |
601 address instruction_address() const { return addr_at(0); } | |
602 address next_instruction_address() const { return addr_at(instruction_size); } | |
603 | |
604 // (The [set_]data accessor respects oop_type relocs also.) | |
605 int data() const; | |
606 void set_data(int x); | |
607 | |
608 // report the destination register | |
609 Register destination() { return inv_rd(long_at(sethi_offset)); } | |
610 | |
611 void verify(); | |
612 void print(); | |
613 | |
614 // unit test stuff | |
615 static void test(); | |
616 | |
617 // Creation | |
618 friend inline NativeMovConstRegPatching* nativeMovConstRegPatching_at(address address) { | |
619 NativeMovConstRegPatching* test = (NativeMovConstRegPatching*)address; | |
620 #ifdef ASSERT | |
621 test->verify(); | |
622 #endif | |
623 return test; | |
624 } | |
625 | |
626 | |
627 friend NativeMovConstRegPatching* nativeMovConstRegPatching_before(address address) { | |
628 NativeMovConstRegPatching* test = (NativeMovConstRegPatching*)(address - instruction_size); | |
629 #ifdef ASSERT | |
630 test->verify(); | |
631 #endif | |
632 return test; | |
633 } | |
634 | |
635 }; | |
636 | |
637 | |
638 // An interface for accessing/manipulating native memory ops | |
639 // ld* [reg + offset], reg | |
640 // st* reg, [reg + offset] | |
641 // sethi %hi(imm), reg; add reg, %lo(imm), reg; ld* [reg1 + reg], reg2 | |
642 // sethi %hi(imm), reg; add reg, %lo(imm), reg; st* reg2, [reg1 + reg] | |
643 // Ops covered: {lds,ldu,st}{w,b,h}, {ld,st}{d,x} | |
644 // | |
645 class NativeMovRegMem; | |
646 inline NativeMovRegMem* nativeMovRegMem_at (address address); | |
647 class NativeMovRegMem: public NativeInstruction { | |
648 public: | |
649 enum Sparc_specific_constants { | |
650 op3_mask_ld = 1 << Assembler::lduw_op3 | | |
651 1 << Assembler::ldub_op3 | | |
652 1 << Assembler::lduh_op3 | | |
653 1 << Assembler::ldd_op3 | | |
654 1 << Assembler::ldsw_op3 | | |
655 1 << Assembler::ldsb_op3 | | |
656 1 << Assembler::ldsh_op3 | | |
657 1 << Assembler::ldx_op3, | |
658 op3_mask_st = 1 << Assembler::stw_op3 | | |
659 1 << Assembler::stb_op3 | | |
660 1 << Assembler::sth_op3 | | |
661 1 << Assembler::std_op3 | | |
662 1 << Assembler::stx_op3, | |
663 op3_ldst_int_limit = Assembler::ldf_op3, | |
664 op3_mask_ldf = 1 << (Assembler::ldf_op3 - op3_ldst_int_limit) | | |
665 1 << (Assembler::lddf_op3 - op3_ldst_int_limit), | |
666 op3_mask_stf = 1 << (Assembler::stf_op3 - op3_ldst_int_limit) | | |
667 1 << (Assembler::stdf_op3 - op3_ldst_int_limit), | |
668 | |
669 offset_width = 13, | |
670 sethi_offset = 0, | |
671 #ifdef _LP64 | |
672 add_offset = 7 * BytesPerInstWord, | |
673 #else | |
674 add_offset = 4, | |
675 #endif | |
676 ldst_offset = add_offset + BytesPerInstWord | |
677 }; | |
678 bool is_immediate() const { | |
679 // check if instruction is ld* [reg + offset], reg or st* reg, [reg + offset] | |
680 int i0 = long_at(0); | |
681 return (is_op(i0, Assembler::ldst_op)); | |
682 } | |
683 | |
684 address instruction_address() const { return addr_at(0); } | |
685 address next_instruction_address() const { | |
686 #ifdef _LP64 | |
687 return addr_at(is_immediate() ? 4 : (7 * BytesPerInstWord)); | |
688 #else | |
689 return addr_at(is_immediate() ? 4 : 12); | |
690 #endif | |
691 } | |
692 intptr_t offset() const { | |
693 return is_immediate()? inv_simm(long_at(0), offset_width) : | |
694 nativeMovConstReg_at(addr_at(0))->data(); | |
695 } | |
696 void set_offset(intptr_t x) { | |
697 if (is_immediate()) { | |
698 guarantee(fits_in_simm(x, offset_width), "data block offset overflow"); | |
699 set_long_at(0, set_simm(long_at(0), x, offset_width)); | |
700 } else | |
701 nativeMovConstReg_at(addr_at(0))->set_data(x); | |
702 } | |
703 | |
704 void add_offset_in_bytes(intptr_t radd_offset) { | |
705 set_offset (offset() + radd_offset); | |
706 } | |
707 | |
708 void copy_instruction_to(address new_instruction_address); | |
709 | |
710 void verify(); | |
711 void print (); | |
712 | |
713 // unit test stuff | |
714 static void test(); | |
715 | |
716 private: | |
717 friend inline NativeMovRegMem* nativeMovRegMem_at (address address) { | |
718 NativeMovRegMem* test = (NativeMovRegMem*)address; | |
719 #ifdef ASSERT | |
720 test->verify(); | |
721 #endif | |
722 return test; | |
723 } | |
724 }; | |
725 | |
726 | |
727 // An interface for accessing/manipulating native memory ops | |
728 // ld* [reg + offset], reg | |
729 // st* reg, [reg + offset] | |
730 // sethi %hi(imm), reg; nop; add reg, %lo(imm), reg; ld* [reg1 + reg], reg2 | |
731 // sethi %hi(imm), reg; nop; add reg, %lo(imm), reg; st* reg2, [reg1 + reg] | |
732 // Ops covered: {lds,ldu,st}{w,b,h}, {ld,st}{d,x} | |
733 // | |
734 // Note that it is identical to NativeMovRegMem with the exception of a nop between the | |
735 // sethi and the add. The nop is required to be in the delay slot of the call instruction | |
736 // which overwrites the sethi during patching. | |
737 class NativeMovRegMemPatching; | |
738 inline NativeMovRegMemPatching* nativeMovRegMemPatching_at (address address); | |
739 class NativeMovRegMemPatching: public NativeInstruction { | |
740 public: | |
741 enum Sparc_specific_constants { | |
742 op3_mask_ld = 1 << Assembler::lduw_op3 | | |
743 1 << Assembler::ldub_op3 | | |
744 1 << Assembler::lduh_op3 | | |
745 1 << Assembler::ldd_op3 | | |
746 1 << Assembler::ldsw_op3 | | |
747 1 << Assembler::ldsb_op3 | | |
748 1 << Assembler::ldsh_op3 | | |
749 1 << Assembler::ldx_op3, | |
750 op3_mask_st = 1 << Assembler::stw_op3 | | |
751 1 << Assembler::stb_op3 | | |
752 1 << Assembler::sth_op3 | | |
753 1 << Assembler::std_op3 | | |
754 1 << Assembler::stx_op3, | |
755 op3_ldst_int_limit = Assembler::ldf_op3, | |
756 op3_mask_ldf = 1 << (Assembler::ldf_op3 - op3_ldst_int_limit) | | |
757 1 << (Assembler::lddf_op3 - op3_ldst_int_limit), | |
758 op3_mask_stf = 1 << (Assembler::stf_op3 - op3_ldst_int_limit) | | |
759 1 << (Assembler::stdf_op3 - op3_ldst_int_limit), | |
760 | |
761 offset_width = 13, | |
762 sethi_offset = 0, | |
763 #ifdef _LP64 | |
764 nop_offset = 7 * BytesPerInstWord, | |
765 #else | |
766 nop_offset = 4, | |
767 #endif | |
768 add_offset = nop_offset + BytesPerInstWord, | |
769 ldst_offset = add_offset + BytesPerInstWord | |
770 }; | |
771 bool is_immediate() const { | |
772 // check if instruction is ld* [reg + offset], reg or st* reg, [reg + offset] | |
773 int i0 = long_at(0); | |
774 return (is_op(i0, Assembler::ldst_op)); | |
775 } | |
776 | |
777 address instruction_address() const { return addr_at(0); } | |
778 address next_instruction_address() const { | |
779 return addr_at(is_immediate()? 4 : 16); | |
780 } | |
781 int offset() const { | |
782 return is_immediate()? inv_simm(long_at(0), offset_width) : | |
783 nativeMovConstRegPatching_at(addr_at(0))->data(); | |
784 } | |
785 void set_offset(int x) { | |
786 if (is_immediate()) { | |
787 guarantee(fits_in_simm(x, offset_width), "data block offset overflow"); | |
788 set_long_at(0, set_simm(long_at(0), x, offset_width)); | |
789 } | |
790 else | |
791 nativeMovConstRegPatching_at(addr_at(0))->set_data(x); | |
792 } | |
793 | |
794 void add_offset_in_bytes(intptr_t radd_offset) { | |
795 set_offset (offset() + radd_offset); | |
796 } | |
797 | |
798 void copy_instruction_to(address new_instruction_address); | |
799 | |
800 void verify(); | |
801 void print (); | |
802 | |
803 // unit test stuff | |
804 static void test(); | |
805 | |
806 private: | |
807 friend inline NativeMovRegMemPatching* nativeMovRegMemPatching_at (address address) { | |
808 NativeMovRegMemPatching* test = (NativeMovRegMemPatching*)address; | |
809 #ifdef ASSERT | |
810 test->verify(); | |
811 #endif | |
812 return test; | |
813 } | |
814 }; | |
815 | |
816 | |
817 // An interface for accessing/manipulating native jumps | |
818 // jump_to addr | |
819 // == sethi %hi22(addr), temp ; jumpl reg, %lo10(addr), G0 ; <delay> | |
820 // jumpl_to addr, lreg | |
821 // == sethi %hi22(addr), temp ; jumpl reg, %lo10(addr), lreg ; <delay> | |
822 class NativeJump; | |
823 inline NativeJump* nativeJump_at(address address); | |
824 class NativeJump: public NativeInstruction { | |
825 private: | |
826 void guarantee_displacement(int disp, int width) { | |
827 guarantee(fits_in_simm(disp, width + 2), "branch displacement overflow"); | |
828 } | |
829 | |
830 public: | |
831 enum Sparc_specific_constants { | |
832 sethi_offset = 0, | |
833 #ifdef _LP64 | |
834 jmpl_offset = 7 * BytesPerInstWord, | |
835 instruction_size = 9 * BytesPerInstWord // includes delay slot | |
836 #else | |
837 jmpl_offset = 1 * BytesPerInstWord, | |
838 instruction_size = 3 * BytesPerInstWord // includes delay slot | |
839 #endif | |
840 }; | |
841 | |
842 address instruction_address() const { return addr_at(0); } | |
843 address next_instruction_address() const { return addr_at(instruction_size); } | |
844 | |
845 #ifdef _LP64 | |
846 address jump_destination() const { | |
847 return (address) data64(instruction_address(), long_at(jmpl_offset)); | |
848 } | |
849 void set_jump_destination(address dest) { | |
850 set_data64_sethi( instruction_address(), (intptr_t)dest); | |
851 set_long_at(jmpl_offset, set_data32_simm13( long_at(jmpl_offset), (intptr_t)dest)); | |
852 } | |
853 #else | |
854 address jump_destination() const { | |
855 return (address) data32(long_at(sethi_offset), long_at(jmpl_offset)); | |
856 } | |
857 void set_jump_destination(address dest) { | |
858 set_long_at(sethi_offset, set_data32_sethi( long_at(sethi_offset), (intptr_t)dest)); | |
859 set_long_at(jmpl_offset, set_data32_simm13( long_at(jmpl_offset), (intptr_t)dest)); | |
860 } | |
861 #endif | |
862 | |
863 // Creation | |
864 friend inline NativeJump* nativeJump_at(address address) { | |
865 NativeJump* jump = (NativeJump*)address; | |
866 #ifdef ASSERT | |
867 jump->verify(); | |
868 #endif | |
869 return jump; | |
870 } | |
871 | |
872 void verify(); | |
873 void print(); | |
874 | |
875 // Unit testing stuff | |
876 static void test(); | |
877 | |
878 // Insertion of native jump instruction | |
879 static void insert(address code_pos, address entry); | |
880 // MT-safe insertion of native jump at verified method entry | |
881 static void check_verified_entry_alignment(address entry, address verified_entry) { | |
882 // nothing to do for sparc. | |
883 } | |
884 static void patch_verified_entry(address entry, address verified_entry, address dest); | |
885 }; | |
886 | |
887 | |
888 | |
889 // Despite the name, handles only simple branches. | |
890 class NativeGeneralJump; | |
891 inline NativeGeneralJump* nativeGeneralJump_at(address address); | |
892 class NativeGeneralJump: public NativeInstruction { | |
893 public: | |
894 enum Sparc_specific_constants { | |
895 instruction_size = 8 | |
896 }; | |
897 | |
898 address instruction_address() const { return addr_at(0); } | |
899 address jump_destination() const { return addr_at(0) + branch_destination_offset(long_at(0)); } | |
900 void set_jump_destination(address dest) { | |
901 int patched_instr = patch_branch_destination_offset(dest - addr_at(0), long_at(0)); | |
902 set_long_at(0, patched_instr); | |
903 } | |
904 NativeInstruction *delay_slot_instr() { return nativeInstruction_at(addr_at(4));} | |
905 void fill_delay_slot(int instr) { set_long_at(4, instr);} | |
906 Assembler::Condition condition() { | |
907 int x = long_at(0); | |
908 return (Assembler::Condition) Assembler::inv_cond(x); | |
909 } | |
910 | |
911 // Creation | |
912 friend inline NativeGeneralJump* nativeGeneralJump_at(address address) { | |
913 NativeGeneralJump* jump = (NativeGeneralJump*)(address); | |
914 #ifdef ASSERT | |
915 jump->verify(); | |
916 #endif | |
917 return jump; | |
918 } | |
919 | |
920 // Insertion of native general jump instruction | |
921 static void insert_unconditional(address code_pos, address entry); | |
922 static void replace_mt_safe(address instr_addr, address code_buffer); | |
923 | |
924 void verify(); | |
925 }; | |
926 | |
927 | |
928 class NativeIllegalInstruction: public NativeInstruction { | |
929 public: | |
930 enum Sparc_specific_constants { | |
931 instruction_size = 4 | |
932 }; | |
933 | |
934 // Insert illegal opcode as specific address | |
935 static void insert(address code_pos); | |
936 }; | |
1972 | 937 |
938 #endif // CPU_SPARC_VM_NATIVEINST_SPARC_HPP |