annotate src/cpu/x86/vm/stubGenerator_x86_32.cpp @ 11080:b800986664f4

7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32 Summary: add intrinsics using new instruction to interpreter, C1, C2, for suitable x86; add test Reviewed-by: kvn, twisti
author drchase
date Tue, 02 Jul 2013 20:42:12 -0400
parents ef57c43512d6
children 980532a806a5
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1 /*
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2 * Copyright (c) 1999, 2013, Oracle and/or its affiliates. All rights reserved.
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3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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4 *
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5 * This code is free software; you can redistribute it and/or modify it
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6 * under the terms of the GNU General Public License version 2 only, as
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7 * published by the Free Software Foundation.
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8 *
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9 * This code is distributed in the hope that it will be useful, but WITHOUT
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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12 * version 2 for more details (a copy is included in the LICENSE file that
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13 * accompanied this code).
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14 *
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15 * You should have received a copy of the GNU General Public License version
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16 * 2 along with this work; if not, write to the Free Software Foundation,
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17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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18 *
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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20 * or visit www.oracle.com if you need additional information or have any
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21 * questions.
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22 *
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23 */
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24
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25 #include "precompiled.hpp"
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26 #include "asm/macroAssembler.hpp"
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27 #include "asm/macroAssembler.inline.hpp"
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28 #include "interpreter/interpreter.hpp"
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29 #include "nativeInst_x86.hpp"
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30 #include "oops/instanceOop.hpp"
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31 #include "oops/method.hpp"
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32 #include "oops/objArrayKlass.hpp"
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33 #include "oops/oop.inline.hpp"
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34 #include "prims/methodHandles.hpp"
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35 #include "runtime/frame.inline.hpp"
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36 #include "runtime/handles.inline.hpp"
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37 #include "runtime/sharedRuntime.hpp"
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38 #include "runtime/stubCodeGenerator.hpp"
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39 #include "runtime/stubRoutines.hpp"
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40 #include "runtime/thread.inline.hpp"
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41 #include "utilities/top.hpp"
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42 #ifdef COMPILER2
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43 #include "opto/runtime.hpp"
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44 #endif
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45
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46 // Declaration and definition of StubGenerator (no .hpp file).
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47 // For a more detailed description of the stub routine structure
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48 // see the comment in stubRoutines.hpp
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49
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50 #define __ _masm->
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51 #define a__ ((Assembler*)_masm)->
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52
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53 #ifdef PRODUCT
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54 #define BLOCK_COMMENT(str) /* nothing */
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55 #else
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56 #define BLOCK_COMMENT(str) __ block_comment(str)
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57 #endif
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58
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59 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
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60
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61 const int MXCSR_MASK = 0xFFC0; // Mask out any pending exceptions
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62 const int FPU_CNTRL_WRD_MASK = 0xFFFF;
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63
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64 // -------------------------------------------------------------------------------------------------------------------------
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65 // Stub Code definitions
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66
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67 static address handle_unsafe_access() {
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68 JavaThread* thread = JavaThread::current();
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69 address pc = thread->saved_exception_pc();
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70 // pc is the instruction which we must emulate
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71 // doing a no-op is fine: return garbage from the load
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72 // therefore, compute npc
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73 address npc = Assembler::locate_next_instruction(pc);
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74
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75 // request an async exception
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76 thread->set_pending_unsafe_access_error();
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77
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78 // return address of next instruction to execute
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79 return npc;
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80 }
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81
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82 class StubGenerator: public StubCodeGenerator {
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83 private:
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84
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85 #ifdef PRODUCT
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86 #define inc_counter_np(counter) ((void)0)
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87 #else
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88 void inc_counter_np_(int& counter) {
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89 __ incrementl(ExternalAddress((address)&counter));
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90 }
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91 #define inc_counter_np(counter) \
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92 BLOCK_COMMENT("inc_counter " #counter); \
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93 inc_counter_np_(counter);
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94 #endif //PRODUCT
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95
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96 void inc_copy_counter_np(BasicType t) {
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97 #ifndef PRODUCT
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98 switch (t) {
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99 case T_BYTE: inc_counter_np(SharedRuntime::_jbyte_array_copy_ctr); return;
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100 case T_SHORT: inc_counter_np(SharedRuntime::_jshort_array_copy_ctr); return;
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101 case T_INT: inc_counter_np(SharedRuntime::_jint_array_copy_ctr); return;
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102 case T_LONG: inc_counter_np(SharedRuntime::_jlong_array_copy_ctr); return;
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103 case T_OBJECT: inc_counter_np(SharedRuntime::_oop_array_copy_ctr); return;
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104 }
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105 ShouldNotReachHere();
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106 #endif //PRODUCT
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107 }
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108
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109 //------------------------------------------------------------------------------------------------------------------------
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110 // Call stubs are used to call Java from C
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111 //
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112 // [ return_from_Java ] <--- rsp
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113 // [ argument word n ]
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114 // ...
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115 // -N [ argument word 1 ]
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116 // -7 [ Possible padding for stack alignment ]
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117 // -6 [ Possible padding for stack alignment ]
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118 // -5 [ Possible padding for stack alignment ]
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119 // -4 [ mxcsr save ] <--- rsp_after_call
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120 // -3 [ saved rbx, ]
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121 // -2 [ saved rsi ]
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122 // -1 [ saved rdi ]
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123 // 0 [ saved rbp, ] <--- rbp,
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124 // 1 [ return address ]
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125 // 2 [ ptr. to call wrapper ]
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126 // 3 [ result ]
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127 // 4 [ result_type ]
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128 // 5 [ method ]
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129 // 6 [ entry_point ]
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130 // 7 [ parameters ]
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131 // 8 [ parameter_size ]
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132 // 9 [ thread ]
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133
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134
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135 address generate_call_stub(address& return_address) {
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136 StubCodeMark mark(this, "StubRoutines", "call_stub");
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137 address start = __ pc();
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138
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139 // stub code parameters / addresses
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140 assert(frame::entry_frame_call_wrapper_offset == 2, "adjust this code");
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141 bool sse_save = false;
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142 const Address rsp_after_call(rbp, -4 * wordSize); // same as in generate_catch_exception()!
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143 const int locals_count_in_bytes (4*wordSize);
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144 const Address mxcsr_save (rbp, -4 * wordSize);
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145 const Address saved_rbx (rbp, -3 * wordSize);
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146 const Address saved_rsi (rbp, -2 * wordSize);
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147 const Address saved_rdi (rbp, -1 * wordSize);
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148 const Address result (rbp, 3 * wordSize);
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149 const Address result_type (rbp, 4 * wordSize);
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150 const Address method (rbp, 5 * wordSize);
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151 const Address entry_point (rbp, 6 * wordSize);
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152 const Address parameters (rbp, 7 * wordSize);
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153 const Address parameter_size(rbp, 8 * wordSize);
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154 const Address thread (rbp, 9 * wordSize); // same as in generate_catch_exception()!
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155 sse_save = UseSSE > 0;
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156
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157 // stub code
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158 __ enter();
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159 __ movptr(rcx, parameter_size); // parameter counter
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160 __ shlptr(rcx, Interpreter::logStackElementSize); // convert parameter count to bytes
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161 __ addptr(rcx, locals_count_in_bytes); // reserve space for register saves
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162 __ subptr(rsp, rcx);
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163 __ andptr(rsp, -(StackAlignmentInBytes)); // Align stack
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164
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165 // save rdi, rsi, & rbx, according to C calling conventions
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166 __ movptr(saved_rdi, rdi);
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167 __ movptr(saved_rsi, rsi);
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168 __ movptr(saved_rbx, rbx);
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169 // save and initialize %mxcsr
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170 if (sse_save) {
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171 Label skip_ldmx;
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172 __ stmxcsr(mxcsr_save);
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173 __ movl(rax, mxcsr_save);
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174 __ andl(rax, MXCSR_MASK); // Only check control and mask bits
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175 ExternalAddress mxcsr_std(StubRoutines::addr_mxcsr_std());
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176 __ cmp32(rax, mxcsr_std);
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177 __ jcc(Assembler::equal, skip_ldmx);
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178 __ ldmxcsr(mxcsr_std);
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179 __ bind(skip_ldmx);
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180 }
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181
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182 // make sure the control word is correct.
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183 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
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184
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185 #ifdef ASSERT
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186 // make sure we have no pending exceptions
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187 { Label L;
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188 __ movptr(rcx, thread);
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189 __ cmpptr(Address(rcx, Thread::pending_exception_offset()), (int32_t)NULL_WORD);
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190 __ jcc(Assembler::equal, L);
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191 __ stop("StubRoutines::call_stub: entered with pending exception");
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192 __ bind(L);
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193 }
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194 #endif
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195
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196 // pass parameters if any
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197 BLOCK_COMMENT("pass parameters if any");
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198 Label parameters_done;
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199 __ movl(rcx, parameter_size); // parameter counter
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200 __ testl(rcx, rcx);
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201 __ jcc(Assembler::zero, parameters_done);
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202
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203 // parameter passing loop
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204
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205 Label loop;
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206 // Copy Java parameters in reverse order (receiver last)
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207 // Note that the argument order is inverted in the process
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208 // source is rdx[rcx: N-1..0]
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209 // dest is rsp[rbx: 0..N-1]
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210
304
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211 __ movptr(rdx, parameters); // parameter pointer
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212 __ xorptr(rbx, rbx);
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213
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214 __ BIND(loop);
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215
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216 // get parameter
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217 __ movptr(rax, Address(rdx, rcx, Interpreter::stackElementScale(), -wordSize));
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218 __ movptr(Address(rsp, rbx, Interpreter::stackElementScale(),
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219 Interpreter::expr_offset_in_bytes(0)), rax); // store parameter
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220 __ increment(rbx);
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221 __ decrement(rcx);
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222 __ jcc(Assembler::notZero, loop);
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223
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224 // call Java function
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225 __ BIND(parameters_done);
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226 __ movptr(rbx, method); // get Method*
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227 __ movptr(rax, entry_point); // get entry_point
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228 __ mov(rsi, rsp); // set sender sp
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229 BLOCK_COMMENT("call Java function");
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230 __ call(rax);
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231
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232 BLOCK_COMMENT("call_stub_return_address:");
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233 return_address = __ pc();
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234
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235 #ifdef COMPILER2
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236 {
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237 Label L_skip;
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238 if (UseSSE >= 2) {
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239 __ verify_FPU(0, "call_stub_return");
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240 } else {
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241 for (int i = 1; i < 8; i++) {
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242 __ ffree(i);
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243 }
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244
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245 // UseSSE <= 1 so double result should be left on TOS
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246 __ movl(rsi, result_type);
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247 __ cmpl(rsi, T_DOUBLE);
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248 __ jcc(Assembler::equal, L_skip);
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249 if (UseSSE == 0) {
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250 // UseSSE == 0 so float result should be left on TOS
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251 __ cmpl(rsi, T_FLOAT);
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252 __ jcc(Assembler::equal, L_skip);
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253 }
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254 __ ffree(0);
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255 }
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256 __ BIND(L_skip);
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257 }
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258 #endif // COMPILER2
0
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259
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260 // store result depending on type
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261 // (everything that is not T_LONG, T_FLOAT or T_DOUBLE is treated as T_INT)
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262 __ movptr(rdi, result);
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263 Label is_long, is_float, is_double, exit;
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264 __ movl(rsi, result_type);
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265 __ cmpl(rsi, T_LONG);
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266 __ jcc(Assembler::equal, is_long);
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267 __ cmpl(rsi, T_FLOAT);
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268 __ jcc(Assembler::equal, is_float);
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269 __ cmpl(rsi, T_DOUBLE);
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270 __ jcc(Assembler::equal, is_double);
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271
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272 // handle T_INT case
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273 __ movl(Address(rdi, 0), rax);
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274 __ BIND(exit);
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275
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276 // check that FPU stack is empty
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277 __ verify_FPU(0, "generate_call_stub");
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278
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279 // pop parameters
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280 __ lea(rsp, rsp_after_call);
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281
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282 // restore %mxcsr
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283 if (sse_save) {
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284 __ ldmxcsr(mxcsr_save);
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285 }
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286
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287 // restore rdi, rsi and rbx,
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288 __ movptr(rbx, saved_rbx);
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289 __ movptr(rsi, saved_rsi);
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290 __ movptr(rdi, saved_rdi);
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291 __ addptr(rsp, 4*wordSize);
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292
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293 // return
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294 __ pop(rbp);
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295 __ ret(0);
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296
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297 // handle return types different from T_INT
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298 __ BIND(is_long);
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299 __ movl(Address(rdi, 0 * wordSize), rax);
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300 __ movl(Address(rdi, 1 * wordSize), rdx);
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301 __ jmp(exit);
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302
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303 __ BIND(is_float);
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304 // interpreter uses xmm0 for return values
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305 if (UseSSE >= 1) {
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306 __ movflt(Address(rdi, 0), xmm0);
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307 } else {
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308 __ fstp_s(Address(rdi, 0));
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309 }
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310 __ jmp(exit);
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311
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312 __ BIND(is_double);
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313 // interpreter uses xmm0 for return values
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314 if (UseSSE >= 2) {
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315 __ movdbl(Address(rdi, 0), xmm0);
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316 } else {
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317 __ fstp_d(Address(rdi, 0));
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318 }
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319 __ jmp(exit);
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320
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321 return start;
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322 }
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323
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324
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325 //------------------------------------------------------------------------------------------------------------------------
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326 // Return point for a Java call if there's an exception thrown in Java code.
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327 // The exception is caught and transformed into a pending exception stored in
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328 // JavaThread that can be tested from within the VM.
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329 //
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330 // Note: Usually the parameters are removed by the callee. In case of an exception
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331 // crossing an activation frame boundary, that is not the case if the callee
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332 // is compiled code => need to setup the rsp.
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333 //
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334 // rax,: exception oop
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335
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336 address generate_catch_exception() {
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337 StubCodeMark mark(this, "StubRoutines", "catch_exception");
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338 const Address rsp_after_call(rbp, -4 * wordSize); // same as in generate_call_stub()!
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339 const Address thread (rbp, 9 * wordSize); // same as in generate_call_stub()!
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340 address start = __ pc();
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341
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342 // get thread directly
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343 __ movptr(rcx, thread);
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344 #ifdef ASSERT
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345 // verify that threads correspond
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346 { Label L;
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347 __ get_thread(rbx);
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348 __ cmpptr(rbx, rcx);
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349 __ jcc(Assembler::equal, L);
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350 __ stop("StubRoutines::catch_exception: threads must correspond");
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351 __ bind(L);
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352 }
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353 #endif
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354 // set pending exception
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355 __ verify_oop(rax);
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356 __ movptr(Address(rcx, Thread::pending_exception_offset()), rax );
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357 __ lea(Address(rcx, Thread::exception_file_offset ()),
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358 ExternalAddress((address)__FILE__));
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359 __ movl(Address(rcx, Thread::exception_line_offset ()), __LINE__ );
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360 // complete return to VM
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361 assert(StubRoutines::_call_stub_return_address != NULL, "_call_stub_return_address must have been generated before");
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362 __ jump(RuntimeAddress(StubRoutines::_call_stub_return_address));
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363
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364 return start;
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365 }
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366
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367
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368 //------------------------------------------------------------------------------------------------------------------------
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369 // Continuation point for runtime calls returning with a pending exception.
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370 // The pending exception check happened in the runtime or native call stub.
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371 // The pending exception in Thread is converted into a Java-level exception.
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372 //
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373 // Contract with Java-level exception handlers:
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374 // rax: exception
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375 // rdx: throwing pc
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376 //
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377 // NOTE: At entry of this stub, exception-pc must be on stack !!
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378
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379 address generate_forward_exception() {
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380 StubCodeMark mark(this, "StubRoutines", "forward exception");
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381 address start = __ pc();
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382 const Register thread = rcx;
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383
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384 // other registers used in this stub
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385 const Register exception_oop = rax;
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386 const Register handler_addr = rbx;
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387 const Register exception_pc = rdx;
0
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388
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389 // Upon entry, the sp points to the return address returning into Java
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390 // (interpreted or compiled) code; i.e., the return address becomes the
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391 // throwing pc.
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392 //
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393 // Arguments pushed before the runtime call are still on the stack but
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394 // the exception handler will reset the stack pointer -> ignore them.
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395 // A potential result in registers can be ignored as well.
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396
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397 #ifdef ASSERT
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398 // make sure this code is only executed if there is a pending exception
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399 { Label L;
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400 __ get_thread(thread);
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401 __ cmpptr(Address(thread, Thread::pending_exception_offset()), (int32_t)NULL_WORD);
0
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402 __ jcc(Assembler::notEqual, L);
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parents:
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403 __ stop("StubRoutines::forward exception: no pending exception (1)");
a61af66fc99e Initial load
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parents:
diff changeset
404 __ bind(L);
a61af66fc99e Initial load
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parents:
diff changeset
405 }
a61af66fc99e Initial load
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parents:
diff changeset
406 #endif
a61af66fc99e Initial load
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parents:
diff changeset
407
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parents:
diff changeset
408 // compute exception handler into rbx,
1295
3cf667df43ef 6919934: JSR 292 needs to support x86 C1
twisti
parents: 1192
diff changeset
409 __ get_thread(thread);
3cf667df43ef 6919934: JSR 292 needs to support x86 C1
twisti
parents: 1192
diff changeset
410 __ movptr(exception_pc, Address(rsp, 0));
0
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parents:
diff changeset
411 BLOCK_COMMENT("call exception_handler_for_return_address");
1295
3cf667df43ef 6919934: JSR 292 needs to support x86 C1
twisti
parents: 1192
diff changeset
412 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::exception_handler_for_return_address), thread, exception_pc);
3cf667df43ef 6919934: JSR 292 needs to support x86 C1
twisti
parents: 1192
diff changeset
413 __ mov(handler_addr, rax);
0
a61af66fc99e Initial load
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parents:
diff changeset
414
1295
3cf667df43ef 6919934: JSR 292 needs to support x86 C1
twisti
parents: 1192
diff changeset
415 // setup rax & rdx, remove return address & clear pending exception
3cf667df43ef 6919934: JSR 292 needs to support x86 C1
twisti
parents: 1192
diff changeset
416 __ get_thread(thread);
3cf667df43ef 6919934: JSR 292 needs to support x86 C1
twisti
parents: 1192
diff changeset
417 __ pop(exception_pc);
3cf667df43ef 6919934: JSR 292 needs to support x86 C1
twisti
parents: 1192
diff changeset
418 __ movptr(exception_oop, Address(thread, Thread::pending_exception_offset()));
3cf667df43ef 6919934: JSR 292 needs to support x86 C1
twisti
parents: 1192
diff changeset
419 __ movptr(Address(thread, Thread::pending_exception_offset()), NULL_WORD);
0
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parents:
diff changeset
420
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parents:
diff changeset
421 #ifdef ASSERT
a61af66fc99e Initial load
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parents:
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422 // make sure exception is set
a61af66fc99e Initial load
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parents:
diff changeset
423 { Label L;
1295
3cf667df43ef 6919934: JSR 292 needs to support x86 C1
twisti
parents: 1192
diff changeset
424 __ testptr(exception_oop, exception_oop);
0
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parents:
diff changeset
425 __ jcc(Assembler::notEqual, L);
a61af66fc99e Initial load
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parents:
diff changeset
426 __ stop("StubRoutines::forward exception: no pending exception (2)");
a61af66fc99e Initial load
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parents:
diff changeset
427 __ bind(L);
a61af66fc99e Initial load
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parents:
diff changeset
428 }
a61af66fc99e Initial load
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parents:
diff changeset
429 #endif
a61af66fc99e Initial load
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parents:
diff changeset
430
1295
3cf667df43ef 6919934: JSR 292 needs to support x86 C1
twisti
parents: 1192
diff changeset
431 // Verify that there is really a valid exception in RAX.
3cf667df43ef 6919934: JSR 292 needs to support x86 C1
twisti
parents: 1192
diff changeset
432 __ verify_oop(exception_oop);
3cf667df43ef 6919934: JSR 292 needs to support x86 C1
twisti
parents: 1192
diff changeset
433
0
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parents:
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434 // continue at exception handler (return address removed)
1295
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twisti
parents: 1192
diff changeset
435 // rax: exception
3cf667df43ef 6919934: JSR 292 needs to support x86 C1
twisti
parents: 1192
diff changeset
436 // rbx: exception handler
0
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parents:
diff changeset
437 // rdx: throwing pc
1295
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twisti
parents: 1192
diff changeset
438 __ jmp(handler_addr);
0
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parents:
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439
a61af66fc99e Initial load
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parents:
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440 return start;
a61af66fc99e Initial load
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parents:
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441 }
a61af66fc99e Initial load
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parents:
diff changeset
442
a61af66fc99e Initial load
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parents:
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443
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parents:
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444 //----------------------------------------------------------------------------------------------------
a61af66fc99e Initial load
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parents:
diff changeset
445 // Support for jint Atomic::xchg(jint exchange_value, volatile jint* dest)
a61af66fc99e Initial load
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parents:
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446 //
a61af66fc99e Initial load
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parents:
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447 // xchg exists as far back as 8086, lock needed for MP only
a61af66fc99e Initial load
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parents:
diff changeset
448 // Stack layout immediately after call:
a61af66fc99e Initial load
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parents:
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449 //
a61af66fc99e Initial load
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parents:
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450 // 0 [ret addr ] <--- rsp
a61af66fc99e Initial load
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parents:
diff changeset
451 // 1 [ ex ]
a61af66fc99e Initial load
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parents:
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452 // 2 [ dest ]
a61af66fc99e Initial load
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parents:
diff changeset
453 //
a61af66fc99e Initial load
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parents:
diff changeset
454 // Result: *dest <- ex, return (old *dest)
a61af66fc99e Initial load
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parents:
diff changeset
455 //
a61af66fc99e Initial load
duke
parents:
diff changeset
456 // Note: win32 does not currently use this code
a61af66fc99e Initial load
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parents:
diff changeset
457
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duke
parents:
diff changeset
458 address generate_atomic_xchg() {
a61af66fc99e Initial load
duke
parents:
diff changeset
459 StubCodeMark mark(this, "StubRoutines", "atomic_xchg");
a61af66fc99e Initial load
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parents:
diff changeset
460 address start = __ pc();
a61af66fc99e Initial load
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parents:
diff changeset
461
304
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parents: 249
diff changeset
462 __ push(rdx);
0
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parents:
diff changeset
463 Address exchange(rsp, 2 * wordSize);
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parents:
diff changeset
464 Address dest_addr(rsp, 3 * wordSize);
a61af66fc99e Initial load
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parents:
diff changeset
465 __ movl(rax, exchange);
304
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parents: 249
diff changeset
466 __ movptr(rdx, dest_addr);
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never
parents: 249
diff changeset
467 __ xchgl(rax, Address(rdx, 0));
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
468 __ pop(rdx);
0
a61af66fc99e Initial load
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parents:
diff changeset
469 __ ret(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
470
a61af66fc99e Initial load
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parents:
diff changeset
471 return start;
a61af66fc99e Initial load
duke
parents:
diff changeset
472 }
a61af66fc99e Initial load
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parents:
diff changeset
473
a61af66fc99e Initial load
duke
parents:
diff changeset
474 //----------------------------------------------------------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
475 // Support for void verify_mxcsr()
a61af66fc99e Initial load
duke
parents:
diff changeset
476 //
a61af66fc99e Initial load
duke
parents:
diff changeset
477 // This routine is used with -Xcheck:jni to verify that native
a61af66fc99e Initial load
duke
parents:
diff changeset
478 // JNI code does not return to Java code without restoring the
a61af66fc99e Initial load
duke
parents:
diff changeset
479 // MXCSR register to our expected state.
a61af66fc99e Initial load
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parents:
diff changeset
480
a61af66fc99e Initial load
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parents:
diff changeset
481
a61af66fc99e Initial load
duke
parents:
diff changeset
482 address generate_verify_mxcsr() {
a61af66fc99e Initial load
duke
parents:
diff changeset
483 StubCodeMark mark(this, "StubRoutines", "verify_mxcsr");
a61af66fc99e Initial load
duke
parents:
diff changeset
484 address start = __ pc();
a61af66fc99e Initial load
duke
parents:
diff changeset
485
a61af66fc99e Initial load
duke
parents:
diff changeset
486 const Address mxcsr_save(rsp, 0);
a61af66fc99e Initial load
duke
parents:
diff changeset
487
a61af66fc99e Initial load
duke
parents:
diff changeset
488 if (CheckJNICalls && UseSSE > 0 ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
489 Label ok_ret;
a61af66fc99e Initial load
duke
parents:
diff changeset
490 ExternalAddress mxcsr_std(StubRoutines::addr_mxcsr_std());
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
491 __ push(rax);
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
492 __ subptr(rsp, wordSize); // allocate a temp location
0
a61af66fc99e Initial load
duke
parents:
diff changeset
493 __ stmxcsr(mxcsr_save);
a61af66fc99e Initial load
duke
parents:
diff changeset
494 __ movl(rax, mxcsr_save);
a61af66fc99e Initial load
duke
parents:
diff changeset
495 __ andl(rax, MXCSR_MASK);
a61af66fc99e Initial load
duke
parents:
diff changeset
496 __ cmp32(rax, mxcsr_std);
a61af66fc99e Initial load
duke
parents:
diff changeset
497 __ jcc(Assembler::equal, ok_ret);
a61af66fc99e Initial load
duke
parents:
diff changeset
498
a61af66fc99e Initial load
duke
parents:
diff changeset
499 __ warn("MXCSR changed by native JNI code.");
a61af66fc99e Initial load
duke
parents:
diff changeset
500
a61af66fc99e Initial load
duke
parents:
diff changeset
501 __ ldmxcsr(mxcsr_std);
a61af66fc99e Initial load
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parents:
diff changeset
502
a61af66fc99e Initial load
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parents:
diff changeset
503 __ bind(ok_ret);
304
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never
parents: 249
diff changeset
504 __ addptr(rsp, wordSize);
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
505 __ pop(rax);
0
a61af66fc99e Initial load
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parents:
diff changeset
506 }
a61af66fc99e Initial load
duke
parents:
diff changeset
507
a61af66fc99e Initial load
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parents:
diff changeset
508 __ ret(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
509
a61af66fc99e Initial load
duke
parents:
diff changeset
510 return start;
a61af66fc99e Initial load
duke
parents:
diff changeset
511 }
a61af66fc99e Initial load
duke
parents:
diff changeset
512
a61af66fc99e Initial load
duke
parents:
diff changeset
513
a61af66fc99e Initial load
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parents:
diff changeset
514 //---------------------------------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
515 // Support for void verify_fpu_cntrl_wrd()
a61af66fc99e Initial load
duke
parents:
diff changeset
516 //
a61af66fc99e Initial load
duke
parents:
diff changeset
517 // This routine is used with -Xcheck:jni to verify that native
a61af66fc99e Initial load
duke
parents:
diff changeset
518 // JNI code does not return to Java code without restoring the
a61af66fc99e Initial load
duke
parents:
diff changeset
519 // FP control word to our expected state.
a61af66fc99e Initial load
duke
parents:
diff changeset
520
a61af66fc99e Initial load
duke
parents:
diff changeset
521 address generate_verify_fpu_cntrl_wrd() {
a61af66fc99e Initial load
duke
parents:
diff changeset
522 StubCodeMark mark(this, "StubRoutines", "verify_spcw");
a61af66fc99e Initial load
duke
parents:
diff changeset
523 address start = __ pc();
a61af66fc99e Initial load
duke
parents:
diff changeset
524
a61af66fc99e Initial load
duke
parents:
diff changeset
525 const Address fpu_cntrl_wrd_save(rsp, 0);
a61af66fc99e Initial load
duke
parents:
diff changeset
526
a61af66fc99e Initial load
duke
parents:
diff changeset
527 if (CheckJNICalls) {
a61af66fc99e Initial load
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parents:
diff changeset
528 Label ok_ret;
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
529 __ push(rax);
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
530 __ subptr(rsp, wordSize); // allocate a temp location
0
a61af66fc99e Initial load
duke
parents:
diff changeset
531 __ fnstcw(fpu_cntrl_wrd_save);
a61af66fc99e Initial load
duke
parents:
diff changeset
532 __ movl(rax, fpu_cntrl_wrd_save);
a61af66fc99e Initial load
duke
parents:
diff changeset
533 __ andl(rax, FPU_CNTRL_WRD_MASK);
a61af66fc99e Initial load
duke
parents:
diff changeset
534 ExternalAddress fpu_std(StubRoutines::addr_fpu_cntrl_wrd_std());
a61af66fc99e Initial load
duke
parents:
diff changeset
535 __ cmp32(rax, fpu_std);
a61af66fc99e Initial load
duke
parents:
diff changeset
536 __ jcc(Assembler::equal, ok_ret);
a61af66fc99e Initial load
duke
parents:
diff changeset
537
a61af66fc99e Initial load
duke
parents:
diff changeset
538 __ warn("Floating point control word changed by native JNI code.");
a61af66fc99e Initial load
duke
parents:
diff changeset
539
a61af66fc99e Initial load
duke
parents:
diff changeset
540 __ fldcw(fpu_std);
a61af66fc99e Initial load
duke
parents:
diff changeset
541
a61af66fc99e Initial load
duke
parents:
diff changeset
542 __ bind(ok_ret);
304
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never
parents: 249
diff changeset
543 __ addptr(rsp, wordSize);
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
544 __ pop(rax);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
545 }
a61af66fc99e Initial load
duke
parents:
diff changeset
546
a61af66fc99e Initial load
duke
parents:
diff changeset
547 __ ret(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
548
a61af66fc99e Initial load
duke
parents:
diff changeset
549 return start;
a61af66fc99e Initial load
duke
parents:
diff changeset
550 }
a61af66fc99e Initial load
duke
parents:
diff changeset
551
a61af66fc99e Initial load
duke
parents:
diff changeset
552 //---------------------------------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
553 // Wrapper for slow-case handling of double-to-integer conversion
a61af66fc99e Initial load
duke
parents:
diff changeset
554 // d2i or f2i fast case failed either because it is nan or because
a61af66fc99e Initial load
duke
parents:
diff changeset
555 // of under/overflow.
a61af66fc99e Initial load
duke
parents:
diff changeset
556 // Input: FPU TOS: float value
a61af66fc99e Initial load
duke
parents:
diff changeset
557 // Output: rax, (rdx): integer (long) result
a61af66fc99e Initial load
duke
parents:
diff changeset
558
a61af66fc99e Initial load
duke
parents:
diff changeset
559 address generate_d2i_wrapper(BasicType t, address fcn) {
a61af66fc99e Initial load
duke
parents:
diff changeset
560 StubCodeMark mark(this, "StubRoutines", "d2i_wrapper");
a61af66fc99e Initial load
duke
parents:
diff changeset
561 address start = __ pc();
a61af66fc99e Initial load
duke
parents:
diff changeset
562
a61af66fc99e Initial load
duke
parents:
diff changeset
563 // Capture info about frame layout
a61af66fc99e Initial load
duke
parents:
diff changeset
564 enum layout { FPUState_off = 0,
a61af66fc99e Initial load
duke
parents:
diff changeset
565 rbp_off = FPUStateSizeInWords,
a61af66fc99e Initial load
duke
parents:
diff changeset
566 rdi_off,
a61af66fc99e Initial load
duke
parents:
diff changeset
567 rsi_off,
a61af66fc99e Initial load
duke
parents:
diff changeset
568 rcx_off,
a61af66fc99e Initial load
duke
parents:
diff changeset
569 rbx_off,
a61af66fc99e Initial load
duke
parents:
diff changeset
570 saved_argument_off,
a61af66fc99e Initial load
duke
parents:
diff changeset
571 saved_argument_off2, // 2nd half of double
a61af66fc99e Initial load
duke
parents:
diff changeset
572 framesize
a61af66fc99e Initial load
duke
parents:
diff changeset
573 };
a61af66fc99e Initial load
duke
parents:
diff changeset
574
a61af66fc99e Initial load
duke
parents:
diff changeset
575 assert(FPUStateSizeInWords == 27, "update stack layout");
a61af66fc99e Initial load
duke
parents:
diff changeset
576
a61af66fc99e Initial load
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parents:
diff changeset
577 // Save outgoing argument to stack across push_FPU_state()
304
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never
parents: 249
diff changeset
578 __ subptr(rsp, wordSize * 2);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
579 __ fstp_d(Address(rsp, 0));
a61af66fc99e Initial load
duke
parents:
diff changeset
580
a61af66fc99e Initial load
duke
parents:
diff changeset
581 // Save CPU & FPU state
304
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never
parents: 249
diff changeset
582 __ push(rbx);
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
583 __ push(rcx);
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
584 __ push(rsi);
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
585 __ push(rdi);
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
586 __ push(rbp);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
587 __ push_FPU_state();
a61af66fc99e Initial load
duke
parents:
diff changeset
588
a61af66fc99e Initial load
duke
parents:
diff changeset
589 // push_FPU_state() resets the FP top of stack
a61af66fc99e Initial load
duke
parents:
diff changeset
590 // Load original double into FP top of stack
a61af66fc99e Initial load
duke
parents:
diff changeset
591 __ fld_d(Address(rsp, saved_argument_off * wordSize));
a61af66fc99e Initial load
duke
parents:
diff changeset
592 // Store double into stack as outgoing argument
304
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never
parents: 249
diff changeset
593 __ subptr(rsp, wordSize*2);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
594 __ fst_d(Address(rsp, 0));
a61af66fc99e Initial load
duke
parents:
diff changeset
595
a61af66fc99e Initial load
duke
parents:
diff changeset
596 // Prepare FPU for doing math in C-land
a61af66fc99e Initial load
duke
parents:
diff changeset
597 __ empty_FPU_stack();
a61af66fc99e Initial load
duke
parents:
diff changeset
598 // Call the C code to massage the double. Result in EAX
a61af66fc99e Initial load
duke
parents:
diff changeset
599 if (t == T_INT)
a61af66fc99e Initial load
duke
parents:
diff changeset
600 { BLOCK_COMMENT("SharedRuntime::d2i"); }
a61af66fc99e Initial load
duke
parents:
diff changeset
601 else if (t == T_LONG)
a61af66fc99e Initial load
duke
parents:
diff changeset
602 { BLOCK_COMMENT("SharedRuntime::d2l"); }
a61af66fc99e Initial load
duke
parents:
diff changeset
603 __ call_VM_leaf( fcn, 2 );
a61af66fc99e Initial load
duke
parents:
diff changeset
604
a61af66fc99e Initial load
duke
parents:
diff changeset
605 // Restore CPU & FPU state
a61af66fc99e Initial load
duke
parents:
diff changeset
606 __ pop_FPU_state();
304
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never
parents: 249
diff changeset
607 __ pop(rbp);
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
608 __ pop(rdi);
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
609 __ pop(rsi);
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
610 __ pop(rcx);
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
611 __ pop(rbx);
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
612 __ addptr(rsp, wordSize * 2);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
613
a61af66fc99e Initial load
duke
parents:
diff changeset
614 __ ret(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
615
a61af66fc99e Initial load
duke
parents:
diff changeset
616 return start;
a61af66fc99e Initial load
duke
parents:
diff changeset
617 }
a61af66fc99e Initial load
duke
parents:
diff changeset
618
a61af66fc99e Initial load
duke
parents:
diff changeset
619
a61af66fc99e Initial load
duke
parents:
diff changeset
620 //---------------------------------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
621 // The following routine generates a subroutine to throw an asynchronous
a61af66fc99e Initial load
duke
parents:
diff changeset
622 // UnknownError when an unsafe access gets a fault that could not be
a61af66fc99e Initial load
duke
parents:
diff changeset
623 // reasonably prevented by the programmer. (Example: SIGBUS/OBJERR.)
a61af66fc99e Initial load
duke
parents:
diff changeset
624 address generate_handler_for_unsafe_access() {
a61af66fc99e Initial load
duke
parents:
diff changeset
625 StubCodeMark mark(this, "StubRoutines", "handler_for_unsafe_access");
a61af66fc99e Initial load
duke
parents:
diff changeset
626 address start = __ pc();
a61af66fc99e Initial load
duke
parents:
diff changeset
627
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
628 __ push(0); // hole for return address-to-be
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
629 __ pusha(); // push registers
0
a61af66fc99e Initial load
duke
parents:
diff changeset
630 Address next_pc(rsp, RegisterImpl::number_of_registers * BytesPerWord);
a61af66fc99e Initial load
duke
parents:
diff changeset
631 BLOCK_COMMENT("call handle_unsafe_access");
a61af66fc99e Initial load
duke
parents:
diff changeset
632 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, handle_unsafe_access)));
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
633 __ movptr(next_pc, rax); // stuff next address
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
634 __ popa();
0
a61af66fc99e Initial load
duke
parents:
diff changeset
635 __ ret(0); // jump to next address
a61af66fc99e Initial load
duke
parents:
diff changeset
636
a61af66fc99e Initial load
duke
parents:
diff changeset
637 return start;
a61af66fc99e Initial load
duke
parents:
diff changeset
638 }
a61af66fc99e Initial load
duke
parents:
diff changeset
639
a61af66fc99e Initial load
duke
parents:
diff changeset
640
a61af66fc99e Initial load
duke
parents:
diff changeset
641 //----------------------------------------------------------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
642 // Non-destructive plausibility checks for oops
a61af66fc99e Initial load
duke
parents:
diff changeset
643
a61af66fc99e Initial load
duke
parents:
diff changeset
644 address generate_verify_oop() {
a61af66fc99e Initial load
duke
parents:
diff changeset
645 StubCodeMark mark(this, "StubRoutines", "verify_oop");
a61af66fc99e Initial load
duke
parents:
diff changeset
646 address start = __ pc();
a61af66fc99e Initial load
duke
parents:
diff changeset
647
a61af66fc99e Initial load
duke
parents:
diff changeset
648 // Incoming arguments on stack after saving rax,:
a61af66fc99e Initial load
duke
parents:
diff changeset
649 //
a61af66fc99e Initial load
duke
parents:
diff changeset
650 // [tos ]: saved rdx
a61af66fc99e Initial load
duke
parents:
diff changeset
651 // [tos + 1]: saved EFLAGS
a61af66fc99e Initial load
duke
parents:
diff changeset
652 // [tos + 2]: return address
a61af66fc99e Initial load
duke
parents:
diff changeset
653 // [tos + 3]: char* error message
a61af66fc99e Initial load
duke
parents:
diff changeset
654 // [tos + 4]: oop object to verify
a61af66fc99e Initial load
duke
parents:
diff changeset
655 // [tos + 5]: saved rax, - saved by caller and bashed
a61af66fc99e Initial load
duke
parents:
diff changeset
656
a61af66fc99e Initial load
duke
parents:
diff changeset
657 Label exit, error;
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
658 __ pushf();
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
659 __ incrementl(ExternalAddress((address) StubRoutines::verify_oop_count_addr()));
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
660 __ push(rdx); // save rdx
0
a61af66fc99e Initial load
duke
parents:
diff changeset
661 // make sure object is 'reasonable'
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
662 __ movptr(rax, Address(rsp, 4 * wordSize)); // get object
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
663 __ testptr(rax, rax);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
664 __ jcc(Assembler::zero, exit); // if obj is NULL it is ok
a61af66fc99e Initial load
duke
parents:
diff changeset
665
a61af66fc99e Initial load
duke
parents:
diff changeset
666 // Check if the oop is in the right area of memory
a61af66fc99e Initial load
duke
parents:
diff changeset
667 const int oop_mask = Universe::verify_oop_mask();
a61af66fc99e Initial load
duke
parents:
diff changeset
668 const int oop_bits = Universe::verify_oop_bits();
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
669 __ mov(rdx, rax);
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
670 __ andptr(rdx, oop_mask);
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
671 __ cmpptr(rdx, oop_bits);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
672 __ jcc(Assembler::notZero, error);
a61af66fc99e Initial load
duke
parents:
diff changeset
673
6725
da91efe96a93 6964458: Reimplement class meta-data storage to use native memory
coleenp
parents: 6266
diff changeset
674 // make sure klass is 'reasonable', which is not zero.
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
675 __ movptr(rax, Address(rax, oopDesc::klass_offset_in_bytes())); // get klass
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
676 __ testptr(rax, rax);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
677 __ jcc(Assembler::zero, error); // if klass is NULL it is broken
6725
da91efe96a93 6964458: Reimplement class meta-data storage to use native memory
coleenp
parents: 6266
diff changeset
678 // TODO: Future assert that klass is lower 4g memory for UseCompressedKlassPointers
0
a61af66fc99e Initial load
duke
parents:
diff changeset
679
a61af66fc99e Initial load
duke
parents:
diff changeset
680 // return if everything seems ok
a61af66fc99e Initial load
duke
parents:
diff changeset
681 __ bind(exit);
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
682 __ movptr(rax, Address(rsp, 5 * wordSize)); // get saved rax, back
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
683 __ pop(rdx); // restore rdx
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
684 __ popf(); // restore EFLAGS
0
a61af66fc99e Initial load
duke
parents:
diff changeset
685 __ ret(3 * wordSize); // pop arguments
a61af66fc99e Initial load
duke
parents:
diff changeset
686
a61af66fc99e Initial load
duke
parents:
diff changeset
687 // handle errors
a61af66fc99e Initial load
duke
parents:
diff changeset
688 __ bind(error);
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
689 __ movptr(rax, Address(rsp, 5 * wordSize)); // get saved rax, back
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
690 __ pop(rdx); // get saved rdx back
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
691 __ popf(); // get saved EFLAGS off stack -- will be ignored
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
692 __ pusha(); // push registers (eip = return address & msg are already pushed)
0
a61af66fc99e Initial load
duke
parents:
diff changeset
693 BLOCK_COMMENT("call MacroAssembler::debug");
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
694 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32)));
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
695 __ popa();
0
a61af66fc99e Initial load
duke
parents:
diff changeset
696 __ ret(3 * wordSize); // pop arguments
a61af66fc99e Initial load
duke
parents:
diff changeset
697 return start;
a61af66fc99e Initial load
duke
parents:
diff changeset
698 }
a61af66fc99e Initial load
duke
parents:
diff changeset
699
a61af66fc99e Initial load
duke
parents:
diff changeset
700 //
a61af66fc99e Initial load
duke
parents:
diff changeset
701 // Generate pre-barrier for array stores
a61af66fc99e Initial load
duke
parents:
diff changeset
702 //
a61af66fc99e Initial load
duke
parents:
diff changeset
703 // Input:
a61af66fc99e Initial load
duke
parents:
diff changeset
704 // start - starting address
845
df6caf649ff7 6700789: G1: Enable use of compressed oops with G1 heaps
ysr
parents: 710
diff changeset
705 // count - element count
2324
0ac769a57c64 6627983: G1: Bad oop deference during marking
iveresov
parents: 2321
diff changeset
706 void gen_write_ref_array_pre_barrier(Register start, Register count, bool uninitialized_target) {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
707 assert_different_registers(start, count);
a61af66fc99e Initial load
duke
parents:
diff changeset
708 BarrierSet* bs = Universe::heap()->barrier_set();
a61af66fc99e Initial load
duke
parents:
diff changeset
709 switch (bs->kind()) {
a61af66fc99e Initial load
duke
parents:
diff changeset
710 case BarrierSet::G1SATBCT:
a61af66fc99e Initial load
duke
parents:
diff changeset
711 case BarrierSet::G1SATBCTLogging:
2324
0ac769a57c64 6627983: G1: Bad oop deference during marking
iveresov
parents: 2321
diff changeset
712 // With G1, don't generate the call if we statically know that the target in uninitialized
0ac769a57c64 6627983: G1: Bad oop deference during marking
iveresov
parents: 2321
diff changeset
713 if (!uninitialized_target) {
0ac769a57c64 6627983: G1: Bad oop deference during marking
iveresov
parents: 2321
diff changeset
714 __ pusha(); // push registers
0ac769a57c64 6627983: G1: Bad oop deference during marking
iveresov
parents: 2321
diff changeset
715 __ call_VM_leaf(CAST_FROM_FN_PTR(address, BarrierSet::static_write_ref_array_pre),
0ac769a57c64 6627983: G1: Bad oop deference during marking
iveresov
parents: 2321
diff changeset
716 start, count);
0ac769a57c64 6627983: G1: Bad oop deference during marking
iveresov
parents: 2321
diff changeset
717 __ popa();
0ac769a57c64 6627983: G1: Bad oop deference during marking
iveresov
parents: 2321
diff changeset
718 }
0
a61af66fc99e Initial load
duke
parents:
diff changeset
719 break;
a61af66fc99e Initial load
duke
parents:
diff changeset
720 case BarrierSet::CardTableModRef:
a61af66fc99e Initial load
duke
parents:
diff changeset
721 case BarrierSet::CardTableExtension:
a61af66fc99e Initial load
duke
parents:
diff changeset
722 case BarrierSet::ModRef:
a61af66fc99e Initial load
duke
parents:
diff changeset
723 break;
a61af66fc99e Initial load
duke
parents:
diff changeset
724 default :
a61af66fc99e Initial load
duke
parents:
diff changeset
725 ShouldNotReachHere();
a61af66fc99e Initial load
duke
parents:
diff changeset
726
a61af66fc99e Initial load
duke
parents:
diff changeset
727 }
a61af66fc99e Initial load
duke
parents:
diff changeset
728 }
a61af66fc99e Initial load
duke
parents:
diff changeset
729
a61af66fc99e Initial load
duke
parents:
diff changeset
730
a61af66fc99e Initial load
duke
parents:
diff changeset
731 //
a61af66fc99e Initial load
duke
parents:
diff changeset
732 // Generate a post-barrier for an array store
a61af66fc99e Initial load
duke
parents:
diff changeset
733 //
a61af66fc99e Initial load
duke
parents:
diff changeset
734 // start - starting address
a61af66fc99e Initial load
duke
parents:
diff changeset
735 // count - element count
a61af66fc99e Initial load
duke
parents:
diff changeset
736 //
a61af66fc99e Initial load
duke
parents:
diff changeset
737 // The two input registers are overwritten.
a61af66fc99e Initial load
duke
parents:
diff changeset
738 //
a61af66fc99e Initial load
duke
parents:
diff changeset
739 void gen_write_ref_array_post_barrier(Register start, Register count) {
a61af66fc99e Initial load
duke
parents:
diff changeset
740 BarrierSet* bs = Universe::heap()->barrier_set();
a61af66fc99e Initial load
duke
parents:
diff changeset
741 assert_different_registers(start, count);
a61af66fc99e Initial load
duke
parents:
diff changeset
742 switch (bs->kind()) {
a61af66fc99e Initial load
duke
parents:
diff changeset
743 case BarrierSet::G1SATBCT:
a61af66fc99e Initial load
duke
parents:
diff changeset
744 case BarrierSet::G1SATBCTLogging:
a61af66fc99e Initial load
duke
parents:
diff changeset
745 {
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
746 __ pusha(); // push registers
1192
776fb94f33cc 6918006: G1: spill space must be reserved on the stack for barrier calls on Windows x64
apetrusenko
parents: 1174
diff changeset
747 __ call_VM_leaf(CAST_FROM_FN_PTR(address, BarrierSet::static_write_ref_array_post),
776fb94f33cc 6918006: G1: spill space must be reserved on the stack for barrier calls on Windows x64
apetrusenko
parents: 1174
diff changeset
748 start, count);
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
749 __ popa();
0
a61af66fc99e Initial load
duke
parents:
diff changeset
750 }
a61af66fc99e Initial load
duke
parents:
diff changeset
751 break;
a61af66fc99e Initial load
duke
parents:
diff changeset
752
a61af66fc99e Initial load
duke
parents:
diff changeset
753 case BarrierSet::CardTableModRef:
a61af66fc99e Initial load
duke
parents:
diff changeset
754 case BarrierSet::CardTableExtension:
a61af66fc99e Initial load
duke
parents:
diff changeset
755 {
a61af66fc99e Initial load
duke
parents:
diff changeset
756 CardTableModRefBS* ct = (CardTableModRefBS*)bs;
a61af66fc99e Initial load
duke
parents:
diff changeset
757 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
a61af66fc99e Initial load
duke
parents:
diff changeset
758
a61af66fc99e Initial load
duke
parents:
diff changeset
759 Label L_loop;
a61af66fc99e Initial load
duke
parents:
diff changeset
760 const Register end = count; // elements count; end == start+count-1
a61af66fc99e Initial load
duke
parents:
diff changeset
761 assert_different_registers(start, end);
a61af66fc99e Initial load
duke
parents:
diff changeset
762
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
763 __ lea(end, Address(start, count, Address::times_ptr, -wordSize));
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
764 __ shrptr(start, CardTableModRefBS::card_shift);
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
765 __ shrptr(end, CardTableModRefBS::card_shift);
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
766 __ subptr(end, start); // end --> count
0
a61af66fc99e Initial load
duke
parents:
diff changeset
767 __ BIND(L_loop);
249
910a4cb98e9e 6717457: Internal Error (src/share/vm/code/relocInfo.hpp:1089)
never
parents: 19
diff changeset
768 intptr_t disp = (intptr_t) ct->byte_map_base;
910a4cb98e9e 6717457: Internal Error (src/share/vm/code/relocInfo.hpp:1089)
never
parents: 19
diff changeset
769 Address cardtable(start, count, Address::times_1, disp);
910a4cb98e9e 6717457: Internal Error (src/share/vm/code/relocInfo.hpp:1089)
never
parents: 19
diff changeset
770 __ movb(cardtable, 0);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
771 __ decrement(count);
a61af66fc99e Initial load
duke
parents:
diff changeset
772 __ jcc(Assembler::greaterEqual, L_loop);
a61af66fc99e Initial load
duke
parents:
diff changeset
773 }
a61af66fc99e Initial load
duke
parents:
diff changeset
774 break;
a61af66fc99e Initial load
duke
parents:
diff changeset
775 case BarrierSet::ModRef:
a61af66fc99e Initial load
duke
parents:
diff changeset
776 break;
a61af66fc99e Initial load
duke
parents:
diff changeset
777 default :
a61af66fc99e Initial load
duke
parents:
diff changeset
778 ShouldNotReachHere();
a61af66fc99e Initial load
duke
parents:
diff changeset
779
a61af66fc99e Initial load
duke
parents:
diff changeset
780 }
a61af66fc99e Initial load
duke
parents:
diff changeset
781 }
a61af66fc99e Initial load
duke
parents:
diff changeset
782
405
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
783
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
784 // Copy 64 bytes chunks
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
785 //
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
786 // Inputs:
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
787 // from - source array address
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
788 // to_from - destination array address - from
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
789 // qword_count - 8-bytes element count, negative
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
790 //
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
791 void xmm_copy_forward(Register from, Register to_from, Register qword_count) {
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
792 assert( UseSSE >= 2, "supported cpu only" );
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
793 Label L_copy_64_bytes_loop, L_copy_64_bytes, L_copy_8_bytes, L_exit;
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
794 // Copy 64-byte chunks
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
795 __ jmpb(L_copy_64_bytes);
1365
6476042f815c 6940701: Don't align loops in stubs for Niagara sparc
kvn
parents: 1299
diff changeset
796 __ align(OptoLoopAlignment);
405
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
797 __ BIND(L_copy_64_bytes_loop);
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
798
7475
e2e6bf86682c 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 7427
diff changeset
799 if (UseUnalignedLoadStores) {
e2e6bf86682c 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 7427
diff changeset
800 if (UseAVX >= 2) {
e2e6bf86682c 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 7427
diff changeset
801 __ vmovdqu(xmm0, Address(from, 0));
e2e6bf86682c 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 7427
diff changeset
802 __ vmovdqu(Address(from, to_from, Address::times_1, 0), xmm0);
e2e6bf86682c 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 7427
diff changeset
803 __ vmovdqu(xmm1, Address(from, 32));
e2e6bf86682c 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 7427
diff changeset
804 __ vmovdqu(Address(from, to_from, Address::times_1, 32), xmm1);
e2e6bf86682c 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 7427
diff changeset
805 } else {
e2e6bf86682c 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 7427
diff changeset
806 __ movdqu(xmm0, Address(from, 0));
e2e6bf86682c 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 7427
diff changeset
807 __ movdqu(Address(from, to_from, Address::times_1, 0), xmm0);
e2e6bf86682c 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 7427
diff changeset
808 __ movdqu(xmm1, Address(from, 16));
e2e6bf86682c 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 7427
diff changeset
809 __ movdqu(Address(from, to_from, Address::times_1, 16), xmm1);
e2e6bf86682c 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 7427
diff changeset
810 __ movdqu(xmm2, Address(from, 32));
e2e6bf86682c 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 7427
diff changeset
811 __ movdqu(Address(from, to_from, Address::times_1, 32), xmm2);
e2e6bf86682c 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 7427
diff changeset
812 __ movdqu(xmm3, Address(from, 48));
e2e6bf86682c 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 7427
diff changeset
813 __ movdqu(Address(from, to_from, Address::times_1, 48), xmm3);
e2e6bf86682c 8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents: 7427
diff changeset
814 }
405
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
815 } else {
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
816 __ movq(xmm0, Address(from, 0));
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
817 __ movq(Address(from, to_from, Address::times_1, 0), xmm0);
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
818 __ movq(xmm1, Address(from, 8));
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
819 __ movq(Address(from, to_from, Address::times_1, 8), xmm1);
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
820 __ movq(xmm2, Address(from, 16));
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
821 __ movq(Address(from, to_from, Address::times_1, 16), xmm2);
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
822 __ movq(xmm3, Address(from, 24));
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
823 __ movq(Address(from, to_from, Address::times_1, 24), xmm3);
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
824 __ movq(xmm4, Address(from, 32));
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
825 __ movq(Address(from, to_from, Address::times_1, 32), xmm4);
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
826 __ movq(xmm5, Address(from, 40));
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
827 __ movq(Address(from, to_from, Address::times_1, 40), xmm5);
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
828 __ movq(xmm6, Address(from, 48));
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
829 __ movq(Address(from, to_from, Address::times_1, 48), xmm6);
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
830 __ movq(xmm7, Address(from, 56));
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
831 __ movq(Address(from, to_from, Address::times_1, 56), xmm7);
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
832 }
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
833
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
834 __ addl(from, 64);
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
835 __ BIND(L_copy_64_bytes);
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
836 __ subl(qword_count, 8);
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
837 __ jcc(Assembler::greaterEqual, L_copy_64_bytes_loop);
8873
e961c11b85fe 8011102: Clear AVX registers after return from JNI call
kvn
parents: 7475
diff changeset
838
e961c11b85fe 8011102: Clear AVX registers after return from JNI call
kvn
parents: 7475
diff changeset
839 if (UseUnalignedLoadStores && (UseAVX >= 2)) {
e961c11b85fe 8011102: Clear AVX registers after return from JNI call
kvn
parents: 7475
diff changeset
840 // clean upper bits of YMM registers
e961c11b85fe 8011102: Clear AVX registers after return from JNI call
kvn
parents: 7475
diff changeset
841 __ vzeroupper();
e961c11b85fe 8011102: Clear AVX registers after return from JNI call
kvn
parents: 7475
diff changeset
842 }
405
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
843 __ addl(qword_count, 8);
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
844 __ jccb(Assembler::zero, L_exit);
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
845 //
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
846 // length is too short, just copy qwords
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
847 //
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
848 __ BIND(L_copy_8_bytes);
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
849 __ movq(xmm0, Address(from, 0));
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
850 __ movq(Address(from, to_from, Address::times_1), xmm0);
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
851 __ addl(from, 8);
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
852 __ decrement(qword_count);
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
853 __ jcc(Assembler::greater, L_copy_8_bytes);
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
854 __ BIND(L_exit);
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
855 }
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
856
0
a61af66fc99e Initial load
duke
parents:
diff changeset
857 // Copy 64 bytes chunks
a61af66fc99e Initial load
duke
parents:
diff changeset
858 //
a61af66fc99e Initial load
duke
parents:
diff changeset
859 // Inputs:
a61af66fc99e Initial load
duke
parents:
diff changeset
860 // from - source array address
a61af66fc99e Initial load
duke
parents:
diff changeset
861 // to_from - destination array address - from
a61af66fc99e Initial load
duke
parents:
diff changeset
862 // qword_count - 8-bytes element count, negative
a61af66fc99e Initial load
duke
parents:
diff changeset
863 //
a61af66fc99e Initial load
duke
parents:
diff changeset
864 void mmx_copy_forward(Register from, Register to_from, Register qword_count) {
405
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
865 assert( VM_Version::supports_mmx(), "supported cpu only" );
0
a61af66fc99e Initial load
duke
parents:
diff changeset
866 Label L_copy_64_bytes_loop, L_copy_64_bytes, L_copy_8_bytes, L_exit;
a61af66fc99e Initial load
duke
parents:
diff changeset
867 // Copy 64-byte chunks
a61af66fc99e Initial load
duke
parents:
diff changeset
868 __ jmpb(L_copy_64_bytes);
1365
6476042f815c 6940701: Don't align loops in stubs for Niagara sparc
kvn
parents: 1299
diff changeset
869 __ align(OptoLoopAlignment);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
870 __ BIND(L_copy_64_bytes_loop);
a61af66fc99e Initial load
duke
parents:
diff changeset
871 __ movq(mmx0, Address(from, 0));
a61af66fc99e Initial load
duke
parents:
diff changeset
872 __ movq(mmx1, Address(from, 8));
a61af66fc99e Initial load
duke
parents:
diff changeset
873 __ movq(mmx2, Address(from, 16));
a61af66fc99e Initial load
duke
parents:
diff changeset
874 __ movq(Address(from, to_from, Address::times_1, 0), mmx0);
a61af66fc99e Initial load
duke
parents:
diff changeset
875 __ movq(mmx3, Address(from, 24));
a61af66fc99e Initial load
duke
parents:
diff changeset
876 __ movq(Address(from, to_from, Address::times_1, 8), mmx1);
a61af66fc99e Initial load
duke
parents:
diff changeset
877 __ movq(mmx4, Address(from, 32));
a61af66fc99e Initial load
duke
parents:
diff changeset
878 __ movq(Address(from, to_from, Address::times_1, 16), mmx2);
a61af66fc99e Initial load
duke
parents:
diff changeset
879 __ movq(mmx5, Address(from, 40));
a61af66fc99e Initial load
duke
parents:
diff changeset
880 __ movq(Address(from, to_from, Address::times_1, 24), mmx3);
a61af66fc99e Initial load
duke
parents:
diff changeset
881 __ movq(mmx6, Address(from, 48));
a61af66fc99e Initial load
duke
parents:
diff changeset
882 __ movq(Address(from, to_from, Address::times_1, 32), mmx4);
a61af66fc99e Initial load
duke
parents:
diff changeset
883 __ movq(mmx7, Address(from, 56));
a61af66fc99e Initial load
duke
parents:
diff changeset
884 __ movq(Address(from, to_from, Address::times_1, 40), mmx5);
a61af66fc99e Initial load
duke
parents:
diff changeset
885 __ movq(Address(from, to_from, Address::times_1, 48), mmx6);
a61af66fc99e Initial load
duke
parents:
diff changeset
886 __ movq(Address(from, to_from, Address::times_1, 56), mmx7);
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
887 __ addptr(from, 64);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
888 __ BIND(L_copy_64_bytes);
a61af66fc99e Initial load
duke
parents:
diff changeset
889 __ subl(qword_count, 8);
a61af66fc99e Initial load
duke
parents:
diff changeset
890 __ jcc(Assembler::greaterEqual, L_copy_64_bytes_loop);
a61af66fc99e Initial load
duke
parents:
diff changeset
891 __ addl(qword_count, 8);
a61af66fc99e Initial load
duke
parents:
diff changeset
892 __ jccb(Assembler::zero, L_exit);
a61af66fc99e Initial load
duke
parents:
diff changeset
893 //
a61af66fc99e Initial load
duke
parents:
diff changeset
894 // length is too short, just copy qwords
a61af66fc99e Initial load
duke
parents:
diff changeset
895 //
a61af66fc99e Initial load
duke
parents:
diff changeset
896 __ BIND(L_copy_8_bytes);
a61af66fc99e Initial load
duke
parents:
diff changeset
897 __ movq(mmx0, Address(from, 0));
a61af66fc99e Initial load
duke
parents:
diff changeset
898 __ movq(Address(from, to_from, Address::times_1), mmx0);
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
899 __ addptr(from, 8);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
900 __ decrement(qword_count);
a61af66fc99e Initial load
duke
parents:
diff changeset
901 __ jcc(Assembler::greater, L_copy_8_bytes);
a61af66fc99e Initial load
duke
parents:
diff changeset
902 __ BIND(L_exit);
a61af66fc99e Initial load
duke
parents:
diff changeset
903 __ emms();
a61af66fc99e Initial load
duke
parents:
diff changeset
904 }
a61af66fc99e Initial load
duke
parents:
diff changeset
905
a61af66fc99e Initial load
duke
parents:
diff changeset
906 address generate_disjoint_copy(BasicType t, bool aligned,
a61af66fc99e Initial load
duke
parents:
diff changeset
907 Address::ScaleFactor sf,
2324
0ac769a57c64 6627983: G1: Bad oop deference during marking
iveresov
parents: 2321
diff changeset
908 address* entry, const char *name,
0ac769a57c64 6627983: G1: Bad oop deference during marking
iveresov
parents: 2321
diff changeset
909 bool dest_uninitialized = false) {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
910 __ align(CodeEntryAlignment);
a61af66fc99e Initial load
duke
parents:
diff changeset
911 StubCodeMark mark(this, "StubRoutines", name);
a61af66fc99e Initial load
duke
parents:
diff changeset
912 address start = __ pc();
a61af66fc99e Initial load
duke
parents:
diff changeset
913
a61af66fc99e Initial load
duke
parents:
diff changeset
914 Label L_0_count, L_exit, L_skip_align1, L_skip_align2, L_copy_byte;
a61af66fc99e Initial load
duke
parents:
diff changeset
915 Label L_copy_2_bytes, L_copy_4_bytes, L_copy_64_bytes;
a61af66fc99e Initial load
duke
parents:
diff changeset
916
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
917 int shift = Address::times_ptr - sf;
0
a61af66fc99e Initial load
duke
parents:
diff changeset
918
a61af66fc99e Initial load
duke
parents:
diff changeset
919 const Register from = rsi; // source array address
a61af66fc99e Initial load
duke
parents:
diff changeset
920 const Register to = rdi; // destination array address
a61af66fc99e Initial load
duke
parents:
diff changeset
921 const Register count = rcx; // elements count
a61af66fc99e Initial load
duke
parents:
diff changeset
922 const Register to_from = to; // (to - from)
a61af66fc99e Initial load
duke
parents:
diff changeset
923 const Register saved_to = rdx; // saved destination array address
a61af66fc99e Initial load
duke
parents:
diff changeset
924
a61af66fc99e Initial load
duke
parents:
diff changeset
925 __ enter(); // required for proper stackwalking of RuntimeStub frame
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
926 __ push(rsi);
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
927 __ push(rdi);
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
928 __ movptr(from , Address(rsp, 12+ 4));
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
929 __ movptr(to , Address(rsp, 12+ 8));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
930 __ movl(count, Address(rsp, 12+ 12));
2313
d89a22843c62 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 2245
diff changeset
931
d89a22843c62 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 2245
diff changeset
932 if (entry != NULL) {
d89a22843c62 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 2245
diff changeset
933 *entry = __ pc(); // Entry point from conjoint arraycopy stub.
d89a22843c62 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 2245
diff changeset
934 BLOCK_COMMENT("Entry:");
d89a22843c62 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 2245
diff changeset
935 }
d89a22843c62 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 2245
diff changeset
936
0
a61af66fc99e Initial load
duke
parents:
diff changeset
937 if (t == T_OBJECT) {
a61af66fc99e Initial load
duke
parents:
diff changeset
938 __ testl(count, count);
a61af66fc99e Initial load
duke
parents:
diff changeset
939 __ jcc(Assembler::zero, L_0_count);
2324
0ac769a57c64 6627983: G1: Bad oop deference during marking
iveresov
parents: 2321
diff changeset
940 gen_write_ref_array_pre_barrier(to, count, dest_uninitialized);
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
941 __ mov(saved_to, to); // save 'to'
0
a61af66fc99e Initial load
duke
parents:
diff changeset
942 }
a61af66fc99e Initial load
duke
parents:
diff changeset
943
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
944 __ subptr(to, from); // to --> to_from
0
a61af66fc99e Initial load
duke
parents:
diff changeset
945 __ cmpl(count, 2<<shift); // Short arrays (< 8 bytes) copy by element
a61af66fc99e Initial load
duke
parents:
diff changeset
946 __ jcc(Assembler::below, L_copy_4_bytes); // use unsigned cmp
405
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
947 if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
948 // align source address at 4 bytes address boundary
a61af66fc99e Initial load
duke
parents:
diff changeset
949 if (t == T_BYTE) {
a61af66fc99e Initial load
duke
parents:
diff changeset
950 // One byte misalignment happens only for byte arrays
a61af66fc99e Initial load
duke
parents:
diff changeset
951 __ testl(from, 1);
a61af66fc99e Initial load
duke
parents:
diff changeset
952 __ jccb(Assembler::zero, L_skip_align1);
a61af66fc99e Initial load
duke
parents:
diff changeset
953 __ movb(rax, Address(from, 0));
a61af66fc99e Initial load
duke
parents:
diff changeset
954 __ movb(Address(from, to_from, Address::times_1, 0), rax);
a61af66fc99e Initial load
duke
parents:
diff changeset
955 __ increment(from);
a61af66fc99e Initial load
duke
parents:
diff changeset
956 __ decrement(count);
a61af66fc99e Initial load
duke
parents:
diff changeset
957 __ BIND(L_skip_align1);
a61af66fc99e Initial load
duke
parents:
diff changeset
958 }
a61af66fc99e Initial load
duke
parents:
diff changeset
959 // Two bytes misalignment happens only for byte and short (char) arrays
a61af66fc99e Initial load
duke
parents:
diff changeset
960 __ testl(from, 2);
a61af66fc99e Initial load
duke
parents:
diff changeset
961 __ jccb(Assembler::zero, L_skip_align2);
a61af66fc99e Initial load
duke
parents:
diff changeset
962 __ movw(rax, Address(from, 0));
a61af66fc99e Initial load
duke
parents:
diff changeset
963 __ movw(Address(from, to_from, Address::times_1, 0), rax);
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
964 __ addptr(from, 2);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
965 __ subl(count, 1<<(shift-1));
a61af66fc99e Initial load
duke
parents:
diff changeset
966 __ BIND(L_skip_align2);
a61af66fc99e Initial load
duke
parents:
diff changeset
967 }
a61af66fc99e Initial load
duke
parents:
diff changeset
968 if (!VM_Version::supports_mmx()) {
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
969 __ mov(rax, count); // save 'count'
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
970 __ shrl(count, shift); // bytes count
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
971 __ addptr(to_from, from);// restore 'to'
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
972 __ rep_mov();
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
973 __ subptr(to_from, from);// restore 'to_from'
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
974 __ mov(count, rax); // restore 'count'
0
a61af66fc99e Initial load
duke
parents:
diff changeset
975 __ jmpb(L_copy_2_bytes); // all dwords were copied
a61af66fc99e Initial load
duke
parents:
diff changeset
976 } else {
405
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
977 if (!UseUnalignedLoadStores) {
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
978 // align to 8 bytes, we know we are 4 byte aligned to start
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
979 __ testptr(from, 4);
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
980 __ jccb(Assembler::zero, L_copy_64_bytes);
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
981 __ movl(rax, Address(from, 0));
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
982 __ movl(Address(from, to_from, Address::times_1, 0), rax);
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
983 __ addptr(from, 4);
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
984 __ subl(count, 1<<shift);
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
985 }
0
a61af66fc99e Initial load
duke
parents:
diff changeset
986 __ BIND(L_copy_64_bytes);
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
987 __ mov(rax, count);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
988 __ shrl(rax, shift+1); // 8 bytes chunk count
a61af66fc99e Initial load
duke
parents:
diff changeset
989 //
a61af66fc99e Initial load
duke
parents:
diff changeset
990 // Copy 8-byte chunks through MMX registers, 8 per iteration of the loop
a61af66fc99e Initial load
duke
parents:
diff changeset
991 //
405
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
992 if (UseXMMForArrayCopy) {
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
993 xmm_copy_forward(from, to_from, rax);
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
994 } else {
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
995 mmx_copy_forward(from, to_from, rax);
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
996 }
0
a61af66fc99e Initial load
duke
parents:
diff changeset
997 }
a61af66fc99e Initial load
duke
parents:
diff changeset
998 // copy tailing dword
a61af66fc99e Initial load
duke
parents:
diff changeset
999 __ BIND(L_copy_4_bytes);
a61af66fc99e Initial load
duke
parents:
diff changeset
1000 __ testl(count, 1<<shift);
a61af66fc99e Initial load
duke
parents:
diff changeset
1001 __ jccb(Assembler::zero, L_copy_2_bytes);
a61af66fc99e Initial load
duke
parents:
diff changeset
1002 __ movl(rax, Address(from, 0));
a61af66fc99e Initial load
duke
parents:
diff changeset
1003 __ movl(Address(from, to_from, Address::times_1, 0), rax);
a61af66fc99e Initial load
duke
parents:
diff changeset
1004 if (t == T_BYTE || t == T_SHORT) {
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1005 __ addptr(from, 4);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1006 __ BIND(L_copy_2_bytes);
a61af66fc99e Initial load
duke
parents:
diff changeset
1007 // copy tailing word
a61af66fc99e Initial load
duke
parents:
diff changeset
1008 __ testl(count, 1<<(shift-1));
a61af66fc99e Initial load
duke
parents:
diff changeset
1009 __ jccb(Assembler::zero, L_copy_byte);
a61af66fc99e Initial load
duke
parents:
diff changeset
1010 __ movw(rax, Address(from, 0));
a61af66fc99e Initial load
duke
parents:
diff changeset
1011 __ movw(Address(from, to_from, Address::times_1, 0), rax);
a61af66fc99e Initial load
duke
parents:
diff changeset
1012 if (t == T_BYTE) {
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1013 __ addptr(from, 2);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1014 __ BIND(L_copy_byte);
a61af66fc99e Initial load
duke
parents:
diff changeset
1015 // copy tailing byte
a61af66fc99e Initial load
duke
parents:
diff changeset
1016 __ testl(count, 1);
a61af66fc99e Initial load
duke
parents:
diff changeset
1017 __ jccb(Assembler::zero, L_exit);
a61af66fc99e Initial load
duke
parents:
diff changeset
1018 __ movb(rax, Address(from, 0));
a61af66fc99e Initial load
duke
parents:
diff changeset
1019 __ movb(Address(from, to_from, Address::times_1, 0), rax);
a61af66fc99e Initial load
duke
parents:
diff changeset
1020 __ BIND(L_exit);
a61af66fc99e Initial load
duke
parents:
diff changeset
1021 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
1022 __ BIND(L_copy_byte);
a61af66fc99e Initial load
duke
parents:
diff changeset
1023 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1024 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
1025 __ BIND(L_copy_2_bytes);
a61af66fc99e Initial load
duke
parents:
diff changeset
1026 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1027
a61af66fc99e Initial load
duke
parents:
diff changeset
1028 if (t == T_OBJECT) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1029 __ movl(count, Address(rsp, 12+12)); // reread 'count'
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1030 __ mov(to, saved_to); // restore 'to'
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1031 gen_write_ref_array_post_barrier(to, count);
a61af66fc99e Initial load
duke
parents:
diff changeset
1032 __ BIND(L_0_count);
a61af66fc99e Initial load
duke
parents:
diff changeset
1033 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1034 inc_copy_counter_np(t);
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1035 __ pop(rdi);
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1036 __ pop(rsi);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1037 __ leave(); // required for proper stackwalking of RuntimeStub frame
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1038 __ xorptr(rax, rax); // return 0
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1039 __ ret(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
1040 return start;
a61af66fc99e Initial load
duke
parents:
diff changeset
1041 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1042
a61af66fc99e Initial load
duke
parents:
diff changeset
1043
1763
d6f45b55c972 4809552: Optimize Arrays.fill(...)
never
parents: 1552
diff changeset
1044 address generate_fill(BasicType t, bool aligned, const char *name) {
d6f45b55c972 4809552: Optimize Arrays.fill(...)
never
parents: 1552
diff changeset
1045 __ align(CodeEntryAlignment);
d6f45b55c972 4809552: Optimize Arrays.fill(...)
never
parents: 1552
diff changeset
1046 StubCodeMark mark(this, "StubRoutines", name);
d6f45b55c972 4809552: Optimize Arrays.fill(...)
never
parents: 1552
diff changeset
1047 address start = __ pc();
d6f45b55c972 4809552: Optimize Arrays.fill(...)
never
parents: 1552
diff changeset
1048
d6f45b55c972 4809552: Optimize Arrays.fill(...)
never
parents: 1552
diff changeset
1049 BLOCK_COMMENT("Entry:");
d6f45b55c972 4809552: Optimize Arrays.fill(...)
never
parents: 1552
diff changeset
1050
d6f45b55c972 4809552: Optimize Arrays.fill(...)
never
parents: 1552
diff changeset
1051 const Register to = rdi; // source array address
d6f45b55c972 4809552: Optimize Arrays.fill(...)
never
parents: 1552
diff changeset
1052 const Register value = rdx; // value
d6f45b55c972 4809552: Optimize Arrays.fill(...)
never
parents: 1552
diff changeset
1053 const Register count = rsi; // elements count
d6f45b55c972 4809552: Optimize Arrays.fill(...)
never
parents: 1552
diff changeset
1054
d6f45b55c972 4809552: Optimize Arrays.fill(...)
never
parents: 1552
diff changeset
1055 __ enter(); // required for proper stackwalking of RuntimeStub frame
d6f45b55c972 4809552: Optimize Arrays.fill(...)
never
parents: 1552
diff changeset
1056 __ push(rsi);
d6f45b55c972 4809552: Optimize Arrays.fill(...)
never
parents: 1552
diff changeset
1057 __ push(rdi);
d6f45b55c972 4809552: Optimize Arrays.fill(...)
never
parents: 1552
diff changeset
1058 __ movptr(to , Address(rsp, 12+ 4));
d6f45b55c972 4809552: Optimize Arrays.fill(...)
never
parents: 1552
diff changeset
1059 __ movl(value, Address(rsp, 12+ 8));
d6f45b55c972 4809552: Optimize Arrays.fill(...)
never
parents: 1552
diff changeset
1060 __ movl(count, Address(rsp, 12+ 12));
d6f45b55c972 4809552: Optimize Arrays.fill(...)
never
parents: 1552
diff changeset
1061
d6f45b55c972 4809552: Optimize Arrays.fill(...)
never
parents: 1552
diff changeset
1062 __ generate_fill(t, aligned, to, value, count, rax, xmm0);
d6f45b55c972 4809552: Optimize Arrays.fill(...)
never
parents: 1552
diff changeset
1063
d6f45b55c972 4809552: Optimize Arrays.fill(...)
never
parents: 1552
diff changeset
1064 __ pop(rdi);
d6f45b55c972 4809552: Optimize Arrays.fill(...)
never
parents: 1552
diff changeset
1065 __ pop(rsi);
d6f45b55c972 4809552: Optimize Arrays.fill(...)
never
parents: 1552
diff changeset
1066 __ leave(); // required for proper stackwalking of RuntimeStub frame
d6f45b55c972 4809552: Optimize Arrays.fill(...)
never
parents: 1552
diff changeset
1067 __ ret(0);
d6f45b55c972 4809552: Optimize Arrays.fill(...)
never
parents: 1552
diff changeset
1068 return start;
d6f45b55c972 4809552: Optimize Arrays.fill(...)
never
parents: 1552
diff changeset
1069 }
d6f45b55c972 4809552: Optimize Arrays.fill(...)
never
parents: 1552
diff changeset
1070
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1071 address generate_conjoint_copy(BasicType t, bool aligned,
a61af66fc99e Initial load
duke
parents:
diff changeset
1072 Address::ScaleFactor sf,
a61af66fc99e Initial load
duke
parents:
diff changeset
1073 address nooverlap_target,
2324
0ac769a57c64 6627983: G1: Bad oop deference during marking
iveresov
parents: 2321
diff changeset
1074 address* entry, const char *name,
0ac769a57c64 6627983: G1: Bad oop deference during marking
iveresov
parents: 2321
diff changeset
1075 bool dest_uninitialized = false) {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1076 __ align(CodeEntryAlignment);
a61af66fc99e Initial load
duke
parents:
diff changeset
1077 StubCodeMark mark(this, "StubRoutines", name);
a61af66fc99e Initial load
duke
parents:
diff changeset
1078 address start = __ pc();
a61af66fc99e Initial load
duke
parents:
diff changeset
1079
a61af66fc99e Initial load
duke
parents:
diff changeset
1080 Label L_0_count, L_exit, L_skip_align1, L_skip_align2, L_copy_byte;
a61af66fc99e Initial load
duke
parents:
diff changeset
1081 Label L_copy_2_bytes, L_copy_4_bytes, L_copy_8_bytes, L_copy_8_bytes_loop;
a61af66fc99e Initial load
duke
parents:
diff changeset
1082
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1083 int shift = Address::times_ptr - sf;
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1084
a61af66fc99e Initial load
duke
parents:
diff changeset
1085 const Register src = rax; // source array address
a61af66fc99e Initial load
duke
parents:
diff changeset
1086 const Register dst = rdx; // destination array address
a61af66fc99e Initial load
duke
parents:
diff changeset
1087 const Register from = rsi; // source array address
a61af66fc99e Initial load
duke
parents:
diff changeset
1088 const Register to = rdi; // destination array address
a61af66fc99e Initial load
duke
parents:
diff changeset
1089 const Register count = rcx; // elements count
a61af66fc99e Initial load
duke
parents:
diff changeset
1090 const Register end = rax; // array end address
a61af66fc99e Initial load
duke
parents:
diff changeset
1091
a61af66fc99e Initial load
duke
parents:
diff changeset
1092 __ enter(); // required for proper stackwalking of RuntimeStub frame
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1093 __ push(rsi);
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1094 __ push(rdi);
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1095 __ movptr(src , Address(rsp, 12+ 4)); // from
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1096 __ movptr(dst , Address(rsp, 12+ 8)); // to
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1097 __ movl2ptr(count, Address(rsp, 12+12)); // count
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1098
a61af66fc99e Initial load
duke
parents:
diff changeset
1099 if (entry != NULL) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1100 *entry = __ pc(); // Entry point from generic arraycopy stub.
a61af66fc99e Initial load
duke
parents:
diff changeset
1101 BLOCK_COMMENT("Entry:");
a61af66fc99e Initial load
duke
parents:
diff changeset
1102 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1103
2313
d89a22843c62 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 2245
diff changeset
1104 // nooverlap_target expects arguments in rsi and rdi.
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1105 __ mov(from, src);
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1106 __ mov(to , dst);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1107
2313
d89a22843c62 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 2245
diff changeset
1108 // arrays overlap test: dispatch to disjoint stub if necessary.
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1109 RuntimeAddress nooverlap(nooverlap_target);
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1110 __ cmpptr(dst, src);
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1111 __ lea(end, Address(src, count, sf, 0)); // src + count * elem_size
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1112 __ jump_cc(Assembler::belowEqual, nooverlap);
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1113 __ cmpptr(dst, end);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1114 __ jump_cc(Assembler::aboveEqual, nooverlap);
a61af66fc99e Initial load
duke
parents:
diff changeset
1115
2313
d89a22843c62 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 2245
diff changeset
1116 if (t == T_OBJECT) {
d89a22843c62 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 2245
diff changeset
1117 __ testl(count, count);
d89a22843c62 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 2245
diff changeset
1118 __ jcc(Assembler::zero, L_0_count);
2324
0ac769a57c64 6627983: G1: Bad oop deference during marking
iveresov
parents: 2321
diff changeset
1119 gen_write_ref_array_pre_barrier(dst, count, dest_uninitialized);
2313
d89a22843c62 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 2245
diff changeset
1120 }
d89a22843c62 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 2245
diff changeset
1121
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1122 // copy from high to low
a61af66fc99e Initial load
duke
parents:
diff changeset
1123 __ cmpl(count, 2<<shift); // Short arrays (< 8 bytes) copy by element
a61af66fc99e Initial load
duke
parents:
diff changeset
1124 __ jcc(Assembler::below, L_copy_4_bytes); // use unsigned cmp
a61af66fc99e Initial load
duke
parents:
diff changeset
1125 if (t == T_BYTE || t == T_SHORT) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1126 // Align the end of destination array at 4 bytes address boundary
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1127 __ lea(end, Address(dst, count, sf, 0));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1128 if (t == T_BYTE) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1129 // One byte misalignment happens only for byte arrays
a61af66fc99e Initial load
duke
parents:
diff changeset
1130 __ testl(end, 1);
a61af66fc99e Initial load
duke
parents:
diff changeset
1131 __ jccb(Assembler::zero, L_skip_align1);
a61af66fc99e Initial load
duke
parents:
diff changeset
1132 __ decrement(count);
a61af66fc99e Initial load
duke
parents:
diff changeset
1133 __ movb(rdx, Address(from, count, sf, 0));
a61af66fc99e Initial load
duke
parents:
diff changeset
1134 __ movb(Address(to, count, sf, 0), rdx);
a61af66fc99e Initial load
duke
parents:
diff changeset
1135 __ BIND(L_skip_align1);
a61af66fc99e Initial load
duke
parents:
diff changeset
1136 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1137 // Two bytes misalignment happens only for byte and short (char) arrays
a61af66fc99e Initial load
duke
parents:
diff changeset
1138 __ testl(end, 2);
a61af66fc99e Initial load
duke
parents:
diff changeset
1139 __ jccb(Assembler::zero, L_skip_align2);
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1140 __ subptr(count, 1<<(shift-1));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1141 __ movw(rdx, Address(from, count, sf, 0));
a61af66fc99e Initial load
duke
parents:
diff changeset
1142 __ movw(Address(to, count, sf, 0), rdx);
a61af66fc99e Initial load
duke
parents:
diff changeset
1143 __ BIND(L_skip_align2);
a61af66fc99e Initial load
duke
parents:
diff changeset
1144 __ cmpl(count, 2<<shift); // Short arrays (< 8 bytes) copy by element
a61af66fc99e Initial load
duke
parents:
diff changeset
1145 __ jcc(Assembler::below, L_copy_4_bytes);
a61af66fc99e Initial load
duke
parents:
diff changeset
1146 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1147
a61af66fc99e Initial load
duke
parents:
diff changeset
1148 if (!VM_Version::supports_mmx()) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1149 __ std();
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1150 __ mov(rax, count); // Save 'count'
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1151 __ mov(rdx, to); // Save 'to'
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1152 __ lea(rsi, Address(from, count, sf, -4));
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1153 __ lea(rdi, Address(to , count, sf, -4));
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1154 __ shrptr(count, shift); // bytes count
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1155 __ rep_mov();
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1156 __ cld();
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1157 __ mov(count, rax); // restore 'count'
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1158 __ andl(count, (1<<shift)-1); // mask the number of rest elements
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1159 __ movptr(from, Address(rsp, 12+4)); // reread 'from'
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1160 __ mov(to, rdx); // restore 'to'
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1161 __ jmpb(L_copy_2_bytes); // all dword were copied
a61af66fc99e Initial load
duke
parents:
diff changeset
1162 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
1163 // Align to 8 bytes the end of array. It is aligned to 4 bytes already.
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1164 __ testptr(end, 4);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1165 __ jccb(Assembler::zero, L_copy_8_bytes);
a61af66fc99e Initial load
duke
parents:
diff changeset
1166 __ subl(count, 1<<shift);
a61af66fc99e Initial load
duke
parents:
diff changeset
1167 __ movl(rdx, Address(from, count, sf, 0));
a61af66fc99e Initial load
duke
parents:
diff changeset
1168 __ movl(Address(to, count, sf, 0), rdx);
a61af66fc99e Initial load
duke
parents:
diff changeset
1169 __ jmpb(L_copy_8_bytes);
a61af66fc99e Initial load
duke
parents:
diff changeset
1170
1365
6476042f815c 6940701: Don't align loops in stubs for Niagara sparc
kvn
parents: 1299
diff changeset
1171 __ align(OptoLoopAlignment);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1172 // Move 8 bytes
a61af66fc99e Initial load
duke
parents:
diff changeset
1173 __ BIND(L_copy_8_bytes_loop);
405
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
1174 if (UseXMMForArrayCopy) {
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
1175 __ movq(xmm0, Address(from, count, sf, 0));
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
1176 __ movq(Address(to, count, sf, 0), xmm0);
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
1177 } else {
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
1178 __ movq(mmx0, Address(from, count, sf, 0));
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
1179 __ movq(Address(to, count, sf, 0), mmx0);
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
1180 }
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1181 __ BIND(L_copy_8_bytes);
a61af66fc99e Initial load
duke
parents:
diff changeset
1182 __ subl(count, 2<<shift);
a61af66fc99e Initial load
duke
parents:
diff changeset
1183 __ jcc(Assembler::greaterEqual, L_copy_8_bytes_loop);
a61af66fc99e Initial load
duke
parents:
diff changeset
1184 __ addl(count, 2<<shift);
405
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
1185 if (!UseXMMForArrayCopy) {
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
1186 __ emms();
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
1187 }
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1188 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1189 __ BIND(L_copy_4_bytes);
a61af66fc99e Initial load
duke
parents:
diff changeset
1190 // copy prefix qword
a61af66fc99e Initial load
duke
parents:
diff changeset
1191 __ testl(count, 1<<shift);
a61af66fc99e Initial load
duke
parents:
diff changeset
1192 __ jccb(Assembler::zero, L_copy_2_bytes);
a61af66fc99e Initial load
duke
parents:
diff changeset
1193 __ movl(rdx, Address(from, count, sf, -4));
a61af66fc99e Initial load
duke
parents:
diff changeset
1194 __ movl(Address(to, count, sf, -4), rdx);
a61af66fc99e Initial load
duke
parents:
diff changeset
1195
a61af66fc99e Initial load
duke
parents:
diff changeset
1196 if (t == T_BYTE || t == T_SHORT) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1197 __ subl(count, (1<<shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
1198 __ BIND(L_copy_2_bytes);
a61af66fc99e Initial load
duke
parents:
diff changeset
1199 // copy prefix dword
a61af66fc99e Initial load
duke
parents:
diff changeset
1200 __ testl(count, 1<<(shift-1));
a61af66fc99e Initial load
duke
parents:
diff changeset
1201 __ jccb(Assembler::zero, L_copy_byte);
a61af66fc99e Initial load
duke
parents:
diff changeset
1202 __ movw(rdx, Address(from, count, sf, -2));
a61af66fc99e Initial load
duke
parents:
diff changeset
1203 __ movw(Address(to, count, sf, -2), rdx);
a61af66fc99e Initial load
duke
parents:
diff changeset
1204 if (t == T_BYTE) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1205 __ subl(count, 1<<(shift-1));
a61af66fc99e Initial load
duke
parents:
diff changeset
1206 __ BIND(L_copy_byte);
a61af66fc99e Initial load
duke
parents:
diff changeset
1207 // copy prefix byte
a61af66fc99e Initial load
duke
parents:
diff changeset
1208 __ testl(count, 1);
a61af66fc99e Initial load
duke
parents:
diff changeset
1209 __ jccb(Assembler::zero, L_exit);
a61af66fc99e Initial load
duke
parents:
diff changeset
1210 __ movb(rdx, Address(from, 0));
a61af66fc99e Initial load
duke
parents:
diff changeset
1211 __ movb(Address(to, 0), rdx);
a61af66fc99e Initial load
duke
parents:
diff changeset
1212 __ BIND(L_exit);
a61af66fc99e Initial load
duke
parents:
diff changeset
1213 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
1214 __ BIND(L_copy_byte);
a61af66fc99e Initial load
duke
parents:
diff changeset
1215 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1216 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
1217 __ BIND(L_copy_2_bytes);
a61af66fc99e Initial load
duke
parents:
diff changeset
1218 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1219 if (t == T_OBJECT) {
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1220 __ movl2ptr(count, Address(rsp, 12+12)); // reread count
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1221 gen_write_ref_array_post_barrier(to, count);
a61af66fc99e Initial load
duke
parents:
diff changeset
1222 __ BIND(L_0_count);
a61af66fc99e Initial load
duke
parents:
diff changeset
1223 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1224 inc_copy_counter_np(t);
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1225 __ pop(rdi);
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1226 __ pop(rsi);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1227 __ leave(); // required for proper stackwalking of RuntimeStub frame
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1228 __ xorptr(rax, rax); // return 0
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1229 __ ret(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
1230 return start;
a61af66fc99e Initial load
duke
parents:
diff changeset
1231 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1232
a61af66fc99e Initial load
duke
parents:
diff changeset
1233
a61af66fc99e Initial load
duke
parents:
diff changeset
1234 address generate_disjoint_long_copy(address* entry, const char *name) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1235 __ align(CodeEntryAlignment);
a61af66fc99e Initial load
duke
parents:
diff changeset
1236 StubCodeMark mark(this, "StubRoutines", name);
a61af66fc99e Initial load
duke
parents:
diff changeset
1237 address start = __ pc();
a61af66fc99e Initial load
duke
parents:
diff changeset
1238
a61af66fc99e Initial load
duke
parents:
diff changeset
1239 Label L_copy_8_bytes, L_copy_8_bytes_loop;
a61af66fc99e Initial load
duke
parents:
diff changeset
1240 const Register from = rax; // source array address
a61af66fc99e Initial load
duke
parents:
diff changeset
1241 const Register to = rdx; // destination array address
a61af66fc99e Initial load
duke
parents:
diff changeset
1242 const Register count = rcx; // elements count
a61af66fc99e Initial load
duke
parents:
diff changeset
1243 const Register to_from = rdx; // (to - from)
a61af66fc99e Initial load
duke
parents:
diff changeset
1244
a61af66fc99e Initial load
duke
parents:
diff changeset
1245 __ enter(); // required for proper stackwalking of RuntimeStub frame
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1246 __ movptr(from , Address(rsp, 8+0)); // from
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1247 __ movptr(to , Address(rsp, 8+4)); // to
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1248 __ movl2ptr(count, Address(rsp, 8+8)); // count
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1249
a61af66fc99e Initial load
duke
parents:
diff changeset
1250 *entry = __ pc(); // Entry point from conjoint arraycopy stub.
a61af66fc99e Initial load
duke
parents:
diff changeset
1251 BLOCK_COMMENT("Entry:");
a61af66fc99e Initial load
duke
parents:
diff changeset
1252
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1253 __ subptr(to, from); // to --> to_from
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1254 if (VM_Version::supports_mmx()) {
405
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
1255 if (UseXMMForArrayCopy) {
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
1256 xmm_copy_forward(from, to_from, count);
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
1257 } else {
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
1258 mmx_copy_forward(from, to_from, count);
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
1259 }
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1260 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
1261 __ jmpb(L_copy_8_bytes);
1365
6476042f815c 6940701: Don't align loops in stubs for Niagara sparc
kvn
parents: 1299
diff changeset
1262 __ align(OptoLoopAlignment);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1263 __ BIND(L_copy_8_bytes_loop);
a61af66fc99e Initial load
duke
parents:
diff changeset
1264 __ fild_d(Address(from, 0));
a61af66fc99e Initial load
duke
parents:
diff changeset
1265 __ fistp_d(Address(from, to_from, Address::times_1));
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1266 __ addptr(from, 8);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1267 __ BIND(L_copy_8_bytes);
a61af66fc99e Initial load
duke
parents:
diff changeset
1268 __ decrement(count);
a61af66fc99e Initial load
duke
parents:
diff changeset
1269 __ jcc(Assembler::greaterEqual, L_copy_8_bytes_loop);
a61af66fc99e Initial load
duke
parents:
diff changeset
1270 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1271 inc_copy_counter_np(T_LONG);
a61af66fc99e Initial load
duke
parents:
diff changeset
1272 __ leave(); // required for proper stackwalking of RuntimeStub frame
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1273 __ xorptr(rax, rax); // return 0
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1274 __ ret(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
1275 return start;
a61af66fc99e Initial load
duke
parents:
diff changeset
1276 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1277
a61af66fc99e Initial load
duke
parents:
diff changeset
1278 address generate_conjoint_long_copy(address nooverlap_target,
a61af66fc99e Initial load
duke
parents:
diff changeset
1279 address* entry, const char *name) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1280 __ align(CodeEntryAlignment);
a61af66fc99e Initial load
duke
parents:
diff changeset
1281 StubCodeMark mark(this, "StubRoutines", name);
a61af66fc99e Initial load
duke
parents:
diff changeset
1282 address start = __ pc();
a61af66fc99e Initial load
duke
parents:
diff changeset
1283
a61af66fc99e Initial load
duke
parents:
diff changeset
1284 Label L_copy_8_bytes, L_copy_8_bytes_loop;
a61af66fc99e Initial load
duke
parents:
diff changeset
1285 const Register from = rax; // source array address
a61af66fc99e Initial load
duke
parents:
diff changeset
1286 const Register to = rdx; // destination array address
a61af66fc99e Initial load
duke
parents:
diff changeset
1287 const Register count = rcx; // elements count
a61af66fc99e Initial load
duke
parents:
diff changeset
1288 const Register end_from = rax; // source array end address
a61af66fc99e Initial load
duke
parents:
diff changeset
1289
a61af66fc99e Initial load
duke
parents:
diff changeset
1290 __ enter(); // required for proper stackwalking of RuntimeStub frame
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1291 __ movptr(from , Address(rsp, 8+0)); // from
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1292 __ movptr(to , Address(rsp, 8+4)); // to
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1293 __ movl2ptr(count, Address(rsp, 8+8)); // count
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1294
a61af66fc99e Initial load
duke
parents:
diff changeset
1295 *entry = __ pc(); // Entry point from generic arraycopy stub.
a61af66fc99e Initial load
duke
parents:
diff changeset
1296 BLOCK_COMMENT("Entry:");
a61af66fc99e Initial load
duke
parents:
diff changeset
1297
a61af66fc99e Initial load
duke
parents:
diff changeset
1298 // arrays overlap test
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1299 __ cmpptr(to, from);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1300 RuntimeAddress nooverlap(nooverlap_target);
a61af66fc99e Initial load
duke
parents:
diff changeset
1301 __ jump_cc(Assembler::belowEqual, nooverlap);
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1302 __ lea(end_from, Address(from, count, Address::times_8, 0));
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1303 __ cmpptr(to, end_from);
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1304 __ movptr(from, Address(rsp, 8)); // from
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1305 __ jump_cc(Assembler::aboveEqual, nooverlap);
a61af66fc99e Initial load
duke
parents:
diff changeset
1306
a61af66fc99e Initial load
duke
parents:
diff changeset
1307 __ jmpb(L_copy_8_bytes);
a61af66fc99e Initial load
duke
parents:
diff changeset
1308
1365
6476042f815c 6940701: Don't align loops in stubs for Niagara sparc
kvn
parents: 1299
diff changeset
1309 __ align(OptoLoopAlignment);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1310 __ BIND(L_copy_8_bytes_loop);
a61af66fc99e Initial load
duke
parents:
diff changeset
1311 if (VM_Version::supports_mmx()) {
405
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
1312 if (UseXMMForArrayCopy) {
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
1313 __ movq(xmm0, Address(from, count, Address::times_8));
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
1314 __ movq(Address(to, count, Address::times_8), xmm0);
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
1315 } else {
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
1316 __ movq(mmx0, Address(from, count, Address::times_8));
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
1317 __ movq(Address(to, count, Address::times_8), mmx0);
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
1318 }
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1319 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
1320 __ fild_d(Address(from, count, Address::times_8));
a61af66fc99e Initial load
duke
parents:
diff changeset
1321 __ fistp_d(Address(to, count, Address::times_8));
a61af66fc99e Initial load
duke
parents:
diff changeset
1322 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1323 __ BIND(L_copy_8_bytes);
a61af66fc99e Initial load
duke
parents:
diff changeset
1324 __ decrement(count);
a61af66fc99e Initial load
duke
parents:
diff changeset
1325 __ jcc(Assembler::greaterEqual, L_copy_8_bytes_loop);
a61af66fc99e Initial load
duke
parents:
diff changeset
1326
405
2649e5276dd7 6532536: Optimize arraycopy stubs for Intel cpus
kvn
parents: 362
diff changeset
1327 if (VM_Version::supports_mmx() && !UseXMMForArrayCopy) {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1328 __ emms();
a61af66fc99e Initial load
duke
parents:
diff changeset
1329 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1330 inc_copy_counter_np(T_LONG);
a61af66fc99e Initial load
duke
parents:
diff changeset
1331 __ leave(); // required for proper stackwalking of RuntimeStub frame
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1332 __ xorptr(rax, rax); // return 0
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1333 __ ret(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
1334 return start;
a61af66fc99e Initial load
duke
parents:
diff changeset
1335 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1336
a61af66fc99e Initial load
duke
parents:
diff changeset
1337
a61af66fc99e Initial load
duke
parents:
diff changeset
1338 // Helper for generating a dynamic type check.
a61af66fc99e Initial load
duke
parents:
diff changeset
1339 // The sub_klass must be one of {rbx, rdx, rsi}.
a61af66fc99e Initial load
duke
parents:
diff changeset
1340 // The temp is killed.
a61af66fc99e Initial load
duke
parents:
diff changeset
1341 void generate_type_check(Register sub_klass,
a61af66fc99e Initial load
duke
parents:
diff changeset
1342 Address& super_check_offset_addr,
a61af66fc99e Initial load
duke
parents:
diff changeset
1343 Address& super_klass_addr,
a61af66fc99e Initial load
duke
parents:
diff changeset
1344 Register temp,
644
c517646eef23 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 533
diff changeset
1345 Label* L_success, Label* L_failure) {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1346 BLOCK_COMMENT("type_check:");
a61af66fc99e Initial load
duke
parents:
diff changeset
1347
a61af66fc99e Initial load
duke
parents:
diff changeset
1348 Label L_fallthrough;
644
c517646eef23 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 533
diff changeset
1349 #define LOCAL_JCC(assembler_con, label_ptr) \
c517646eef23 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 533
diff changeset
1350 if (label_ptr != NULL) __ jcc(assembler_con, *(label_ptr)); \
c517646eef23 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 533
diff changeset
1351 else __ jcc(assembler_con, L_fallthrough) /*omit semi*/
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1352
644
c517646eef23 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 533
diff changeset
1353 // The following is a strange variation of the fast path which requires
c517646eef23 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 533
diff changeset
1354 // one less register, because needed values are on the argument stack.
c517646eef23 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 533
diff changeset
1355 // __ check_klass_subtype_fast_path(sub_klass, *super_klass*, temp,
c517646eef23 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 533
diff changeset
1356 // L_success, L_failure, NULL);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1357 assert_different_registers(sub_klass, temp);
a61af66fc99e Initial load
duke
parents:
diff changeset
1358
4762
069ab3f976d3 7118863: Move sizeof(klassOopDesc) into the *Klass::*_offset_in_bytes() functions
stefank
parents: 3960
diff changeset
1359 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1360
a61af66fc99e Initial load
duke
parents:
diff changeset
1361 // if the pointers are equal, we are done (e.g., String[] elements)
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1362 __ cmpptr(sub_klass, super_klass_addr);
644
c517646eef23 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 533
diff changeset
1363 LOCAL_JCC(Assembler::equal, L_success);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1364
a61af66fc99e Initial load
duke
parents:
diff changeset
1365 // check the supertype display:
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1366 __ movl2ptr(temp, super_check_offset_addr);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1367 Address super_check_addr(sub_klass, temp, Address::times_1, 0);
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1368 __ movptr(temp, super_check_addr); // load displayed supertype
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1369 __ cmpptr(temp, super_klass_addr); // test the super type
644
c517646eef23 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 533
diff changeset
1370 LOCAL_JCC(Assembler::equal, L_success);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1371
a61af66fc99e Initial load
duke
parents:
diff changeset
1372 // if it was a primary super, we can just fail immediately
a61af66fc99e Initial load
duke
parents:
diff changeset
1373 __ cmpl(super_check_offset_addr, sc_offset);
644
c517646eef23 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 533
diff changeset
1374 LOCAL_JCC(Assembler::notEqual, L_failure);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1375
644
c517646eef23 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 533
diff changeset
1376 // The repne_scan instruction uses fixed registers, which will get spilled.
c517646eef23 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 533
diff changeset
1377 // We happen to know this works best when super_klass is in rax.
c517646eef23 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 533
diff changeset
1378 Register super_klass = temp;
c517646eef23 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 533
diff changeset
1379 __ movptr(super_klass, super_klass_addr);
c517646eef23 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 533
diff changeset
1380 __ check_klass_subtype_slow_path(sub_klass, super_klass, noreg, noreg,
c517646eef23 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 533
diff changeset
1381 L_success, L_failure);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1382
644
c517646eef23 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 533
diff changeset
1383 __ bind(L_fallthrough);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1384
644
c517646eef23 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 533
diff changeset
1385 if (L_success == NULL) { BLOCK_COMMENT("L_success:"); }
c517646eef23 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 533
diff changeset
1386 if (L_failure == NULL) { BLOCK_COMMENT("L_failure:"); }
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1387
644
c517646eef23 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 533
diff changeset
1388 #undef LOCAL_JCC
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1389 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1390
a61af66fc99e Initial load
duke
parents:
diff changeset
1391 //
a61af66fc99e Initial load
duke
parents:
diff changeset
1392 // Generate checkcasting array copy stub
a61af66fc99e Initial load
duke
parents:
diff changeset
1393 //
a61af66fc99e Initial load
duke
parents:
diff changeset
1394 // Input:
a61af66fc99e Initial load
duke
parents:
diff changeset
1395 // 4(rsp) - source array address
a61af66fc99e Initial load
duke
parents:
diff changeset
1396 // 8(rsp) - destination array address
a61af66fc99e Initial load
duke
parents:
diff changeset
1397 // 12(rsp) - element count, can be zero
a61af66fc99e Initial load
duke
parents:
diff changeset
1398 // 16(rsp) - size_t ckoff (super_check_offset)
a61af66fc99e Initial load
duke
parents:
diff changeset
1399 // 20(rsp) - oop ckval (super_klass)
a61af66fc99e Initial load
duke
parents:
diff changeset
1400 //
a61af66fc99e Initial load
duke
parents:
diff changeset
1401 // Output:
a61af66fc99e Initial load
duke
parents:
diff changeset
1402 // rax, == 0 - success
a61af66fc99e Initial load
duke
parents:
diff changeset
1403 // rax, == -1^K - failure, where K is partial transfer count
a61af66fc99e Initial load
duke
parents:
diff changeset
1404 //
2324
0ac769a57c64 6627983: G1: Bad oop deference during marking
iveresov
parents: 2321
diff changeset
1405 address generate_checkcast_copy(const char *name, address* entry, bool dest_uninitialized = false) {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1406 __ align(CodeEntryAlignment);
a61af66fc99e Initial load
duke
parents:
diff changeset
1407 StubCodeMark mark(this, "StubRoutines", name);
a61af66fc99e Initial load
duke
parents:
diff changeset
1408 address start = __ pc();
a61af66fc99e Initial load
duke
parents:
diff changeset
1409
a61af66fc99e Initial load
duke
parents:
diff changeset
1410 Label L_load_element, L_store_element, L_do_card_marks, L_done;
a61af66fc99e Initial load
duke
parents:
diff changeset
1411
a61af66fc99e Initial load
duke
parents:
diff changeset
1412 // register use:
a61af66fc99e Initial load
duke
parents:
diff changeset
1413 // rax, rdx, rcx -- loop control (end_from, end_to, count)
a61af66fc99e Initial load
duke
parents:
diff changeset
1414 // rdi, rsi -- element access (oop, klass)
a61af66fc99e Initial load
duke
parents:
diff changeset
1415 // rbx, -- temp
a61af66fc99e Initial load
duke
parents:
diff changeset
1416 const Register from = rax; // source array address
a61af66fc99e Initial load
duke
parents:
diff changeset
1417 const Register to = rdx; // destination array address
a61af66fc99e Initial load
duke
parents:
diff changeset
1418 const Register length = rcx; // elements count
a61af66fc99e Initial load
duke
parents:
diff changeset
1419 const Register elem = rdi; // each oop copied
a61af66fc99e Initial load
duke
parents:
diff changeset
1420 const Register elem_klass = rsi; // each elem._klass (sub_klass)
a61af66fc99e Initial load
duke
parents:
diff changeset
1421 const Register temp = rbx; // lone remaining temp
a61af66fc99e Initial load
duke
parents:
diff changeset
1422
a61af66fc99e Initial load
duke
parents:
diff changeset
1423 __ enter(); // required for proper stackwalking of RuntimeStub frame
a61af66fc99e Initial load
duke
parents:
diff changeset
1424
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1425 __ push(rsi);
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1426 __ push(rdi);
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1427 __ push(rbx);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1428
a61af66fc99e Initial load
duke
parents:
diff changeset
1429 Address from_arg(rsp, 16+ 4); // from
a61af66fc99e Initial load
duke
parents:
diff changeset
1430 Address to_arg(rsp, 16+ 8); // to
a61af66fc99e Initial load
duke
parents:
diff changeset
1431 Address length_arg(rsp, 16+12); // elements count
a61af66fc99e Initial load
duke
parents:
diff changeset
1432 Address ckoff_arg(rsp, 16+16); // super_check_offset
a61af66fc99e Initial load
duke
parents:
diff changeset
1433 Address ckval_arg(rsp, 16+20); // super_klass
a61af66fc99e Initial load
duke
parents:
diff changeset
1434
a61af66fc99e Initial load
duke
parents:
diff changeset
1435 // Load up:
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1436 __ movptr(from, from_arg);
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1437 __ movptr(to, to_arg);
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1438 __ movl2ptr(length, length_arg);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1439
2313
d89a22843c62 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 2245
diff changeset
1440 if (entry != NULL) {
d89a22843c62 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 2245
diff changeset
1441 *entry = __ pc(); // Entry point from generic arraycopy stub.
d89a22843c62 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 2245
diff changeset
1442 BLOCK_COMMENT("Entry:");
d89a22843c62 7020521: arraycopy stubs place prebarriers incorrectly
iveresov
parents: 2245
diff changeset
1443 }
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1444
a61af66fc99e Initial load
duke
parents:
diff changeset
1445 //---------------------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
1446 // Assembler stub will be used for this call to arraycopy
a61af66fc99e Initial load
duke
parents:
diff changeset
1447 // if the two arrays are subtypes of Object[] but the
a61af66fc99e Initial load
duke
parents:
diff changeset
1448 // destination array type is not equal to or a supertype
a61af66fc99e Initial load
duke
parents:
diff changeset
1449 // of the source type. Each element must be separately
a61af66fc99e Initial load
duke
parents:
diff changeset
1450 // checked.
a61af66fc99e Initial load
duke
parents:
diff changeset
1451
a61af66fc99e Initial load
duke
parents:
diff changeset
1452 // Loop-invariant addresses. They are exclusive end pointers.
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1453 Address end_from_addr(from, length, Address::times_ptr, 0);
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1454 Address end_to_addr(to, length, Address::times_ptr, 0);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1455
a61af66fc99e Initial load
duke
parents:
diff changeset
1456 Register end_from = from; // re-use
a61af66fc99e Initial load
duke
parents:
diff changeset
1457 Register end_to = to; // re-use
a61af66fc99e Initial load
duke
parents:
diff changeset
1458 Register count = length; // re-use
a61af66fc99e Initial load
duke
parents:
diff changeset
1459
a61af66fc99e Initial load
duke
parents:
diff changeset
1460 // Loop-variant addresses. They assume post-incremented count < 0.
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1461 Address from_element_addr(end_from, count, Address::times_ptr, 0);
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1462 Address to_element_addr(end_to, count, Address::times_ptr, 0);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1463 Address elem_klass_addr(elem, oopDesc::klass_offset_in_bytes());
a61af66fc99e Initial load
duke
parents:
diff changeset
1464
a61af66fc99e Initial load
duke
parents:
diff changeset
1465 // Copy from low to high addresses, indexed from the end of each array.
2324
0ac769a57c64 6627983: G1: Bad oop deference during marking
iveresov
parents: 2321
diff changeset
1466 gen_write_ref_array_pre_barrier(to, count, dest_uninitialized);
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1467 __ lea(end_from, end_from_addr);
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1468 __ lea(end_to, end_to_addr);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1469 assert(length == count, ""); // else fix next line:
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1470 __ negptr(count); // negate and test the length
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1471 __ jccb(Assembler::notZero, L_load_element);
a61af66fc99e Initial load
duke
parents:
diff changeset
1472
a61af66fc99e Initial load
duke
parents:
diff changeset
1473 // Empty array: Nothing to do.
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1474 __ xorptr(rax, rax); // return 0 on (trivial) success
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1475 __ jmp(L_done);
a61af66fc99e Initial load
duke
parents:
diff changeset
1476
a61af66fc99e Initial load
duke
parents:
diff changeset
1477 // ======== begin loop ========
a61af66fc99e Initial load
duke
parents:
diff changeset
1478 // (Loop is rotated; its entry is L_load_element.)
a61af66fc99e Initial load
duke
parents:
diff changeset
1479 // Loop control:
a61af66fc99e Initial load
duke
parents:
diff changeset
1480 // for (count = -count; count != 0; count++)
a61af66fc99e Initial load
duke
parents:
diff changeset
1481 // Base pointers src, dst are biased by 8*count,to last element.
1365
6476042f815c 6940701: Don't align loops in stubs for Niagara sparc
kvn
parents: 1299
diff changeset
1482 __ align(OptoLoopAlignment);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1483
a61af66fc99e Initial load
duke
parents:
diff changeset
1484 __ BIND(L_store_element);
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1485 __ movptr(to_element_addr, elem); // store the oop
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1486 __ increment(count); // increment the count toward zero
a61af66fc99e Initial load
duke
parents:
diff changeset
1487 __ jccb(Assembler::zero, L_do_card_marks);
a61af66fc99e Initial load
duke
parents:
diff changeset
1488
a61af66fc99e Initial load
duke
parents:
diff changeset
1489 // ======== loop entry is here ========
a61af66fc99e Initial load
duke
parents:
diff changeset
1490 __ BIND(L_load_element);
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1491 __ movptr(elem, from_element_addr); // load the oop
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1492 __ testptr(elem, elem);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1493 __ jccb(Assembler::zero, L_store_element);
a61af66fc99e Initial load
duke
parents:
diff changeset
1494
a61af66fc99e Initial load
duke
parents:
diff changeset
1495 // (Could do a trick here: Remember last successful non-null
a61af66fc99e Initial load
duke
parents:
diff changeset
1496 // element stored and make a quick oop equality check on it.)
a61af66fc99e Initial load
duke
parents:
diff changeset
1497
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1498 __ movptr(elem_klass, elem_klass_addr); // query the object klass
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1499 generate_type_check(elem_klass, ckoff_arg, ckval_arg, temp,
a61af66fc99e Initial load
duke
parents:
diff changeset
1500 &L_store_element, NULL);
10324
3f281b313240 8010927: Kitchensink crashed with SIGSEGV, Problematic frame: v ~StubRoutines::checkcast_arraycopy
kvn
parents: 8873
diff changeset
1501 // (On fall-through, we have failed the element type check.)
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1502 // ======== end loop ========
a61af66fc99e Initial load
duke
parents:
diff changeset
1503
a61af66fc99e Initial load
duke
parents:
diff changeset
1504 // It was a real error; we must depend on the caller to finish the job.
19
a73cc31728fe 6614036: REGRESSION: Java server x86 VM intermittently crash with SIGSEGV (0xb)
rasbold
parents: 16
diff changeset
1505 // Register "count" = -1 * number of *remaining* oops, length_arg = *total* oops.
a73cc31728fe 6614036: REGRESSION: Java server x86 VM intermittently crash with SIGSEGV (0xb)
rasbold
parents: 16
diff changeset
1506 // Emit GC store barriers for the oops we have copied (length_arg + count),
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1507 // and report their number to the caller.
10324
3f281b313240 8010927: Kitchensink crashed with SIGSEGV, Problematic frame: v ~StubRoutines::checkcast_arraycopy
kvn
parents: 8873
diff changeset
1508 assert_different_registers(to, count, rax);
3f281b313240 8010927: Kitchensink crashed with SIGSEGV, Problematic frame: v ~StubRoutines::checkcast_arraycopy
kvn
parents: 8873
diff changeset
1509 Label L_post_barrier;
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1510 __ addl(count, length_arg); // transfers = (length - remaining)
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1511 __ movl2ptr(rax, count); // save the value
10324
3f281b313240 8010927: Kitchensink crashed with SIGSEGV, Problematic frame: v ~StubRoutines::checkcast_arraycopy
kvn
parents: 8873
diff changeset
1512 __ notptr(rax); // report (-1^K) to caller (does not affect flags)
3f281b313240 8010927: Kitchensink crashed with SIGSEGV, Problematic frame: v ~StubRoutines::checkcast_arraycopy
kvn
parents: 8873
diff changeset
1513 __ jccb(Assembler::notZero, L_post_barrier);
3f281b313240 8010927: Kitchensink crashed with SIGSEGV, Problematic frame: v ~StubRoutines::checkcast_arraycopy
kvn
parents: 8873
diff changeset
1514 __ jmp(L_done); // K == 0, nothing was copied, skip post barrier
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1515
a61af66fc99e Initial load
duke
parents:
diff changeset
1516 // Come here on success only.
a61af66fc99e Initial load
duke
parents:
diff changeset
1517 __ BIND(L_do_card_marks);
10324
3f281b313240 8010927: Kitchensink crashed with SIGSEGV, Problematic frame: v ~StubRoutines::checkcast_arraycopy
kvn
parents: 8873
diff changeset
1518 __ xorptr(rax, rax); // return 0 on success
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1519 __ movl2ptr(count, length_arg);
10324
3f281b313240 8010927: Kitchensink crashed with SIGSEGV, Problematic frame: v ~StubRoutines::checkcast_arraycopy
kvn
parents: 8873
diff changeset
1520
3f281b313240 8010927: Kitchensink crashed with SIGSEGV, Problematic frame: v ~StubRoutines::checkcast_arraycopy
kvn
parents: 8873
diff changeset
1521 __ BIND(L_post_barrier);
3f281b313240 8010927: Kitchensink crashed with SIGSEGV, Problematic frame: v ~StubRoutines::checkcast_arraycopy
kvn
parents: 8873
diff changeset
1522 __ movptr(to, to_arg); // reload
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1523 gen_write_ref_array_post_barrier(to, count);
a61af66fc99e Initial load
duke
parents:
diff changeset
1524
a61af66fc99e Initial load
duke
parents:
diff changeset
1525 // Common exit point (success or failure).
a61af66fc99e Initial load
duke
parents:
diff changeset
1526 __ BIND(L_done);
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1527 __ pop(rbx);
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1528 __ pop(rdi);
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1529 __ pop(rsi);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1530 inc_counter_np(SharedRuntime::_checkcast_array_copy_ctr);
a61af66fc99e Initial load
duke
parents:
diff changeset
1531 __ leave(); // required for proper stackwalking of RuntimeStub frame
a61af66fc99e Initial load
duke
parents:
diff changeset
1532 __ ret(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
1533
a61af66fc99e Initial load
duke
parents:
diff changeset
1534 return start;
a61af66fc99e Initial load
duke
parents:
diff changeset
1535 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1536
a61af66fc99e Initial load
duke
parents:
diff changeset
1537 //
a61af66fc99e Initial load
duke
parents:
diff changeset
1538 // Generate 'unsafe' array copy stub
a61af66fc99e Initial load
duke
parents:
diff changeset
1539 // Though just as safe as the other stubs, it takes an unscaled
a61af66fc99e Initial load
duke
parents:
diff changeset
1540 // size_t argument instead of an element count.
a61af66fc99e Initial load
duke
parents:
diff changeset
1541 //
a61af66fc99e Initial load
duke
parents:
diff changeset
1542 // Input:
a61af66fc99e Initial load
duke
parents:
diff changeset
1543 // 4(rsp) - source array address
a61af66fc99e Initial load
duke
parents:
diff changeset
1544 // 8(rsp) - destination array address
a61af66fc99e Initial load
duke
parents:
diff changeset
1545 // 12(rsp) - byte count, can be zero
a61af66fc99e Initial load
duke
parents:
diff changeset
1546 //
a61af66fc99e Initial load
duke
parents:
diff changeset
1547 // Output:
a61af66fc99e Initial load
duke
parents:
diff changeset
1548 // rax, == 0 - success
a61af66fc99e Initial load
duke
parents:
diff changeset
1549 // rax, == -1 - need to call System.arraycopy
a61af66fc99e Initial load
duke
parents:
diff changeset
1550 //
a61af66fc99e Initial load
duke
parents:
diff changeset
1551 // Examines the alignment of the operands and dispatches
a61af66fc99e Initial load
duke
parents:
diff changeset
1552 // to a long, int, short, or byte copy loop.
a61af66fc99e Initial load
duke
parents:
diff changeset
1553 //
a61af66fc99e Initial load
duke
parents:
diff changeset
1554 address generate_unsafe_copy(const char *name,
a61af66fc99e Initial load
duke
parents:
diff changeset
1555 address byte_copy_entry,
a61af66fc99e Initial load
duke
parents:
diff changeset
1556 address short_copy_entry,
a61af66fc99e Initial load
duke
parents:
diff changeset
1557 address int_copy_entry,
a61af66fc99e Initial load
duke
parents:
diff changeset
1558 address long_copy_entry) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1559
a61af66fc99e Initial load
duke
parents:
diff changeset
1560 Label L_long_aligned, L_int_aligned, L_short_aligned;
a61af66fc99e Initial load
duke
parents:
diff changeset
1561
a61af66fc99e Initial load
duke
parents:
diff changeset
1562 __ align(CodeEntryAlignment);
a61af66fc99e Initial load
duke
parents:
diff changeset
1563 StubCodeMark mark(this, "StubRoutines", name);
a61af66fc99e Initial load
duke
parents:
diff changeset
1564 address start = __ pc();
a61af66fc99e Initial load
duke
parents:
diff changeset
1565
a61af66fc99e Initial load
duke
parents:
diff changeset
1566 const Register from = rax; // source array address
a61af66fc99e Initial load
duke
parents:
diff changeset
1567 const Register to = rdx; // destination array address
a61af66fc99e Initial load
duke
parents:
diff changeset
1568 const Register count = rcx; // elements count
a61af66fc99e Initial load
duke
parents:
diff changeset
1569
a61af66fc99e Initial load
duke
parents:
diff changeset
1570 __ enter(); // required for proper stackwalking of RuntimeStub frame
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1571 __ push(rsi);
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1572 __ push(rdi);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1573 Address from_arg(rsp, 12+ 4); // from
a61af66fc99e Initial load
duke
parents:
diff changeset
1574 Address to_arg(rsp, 12+ 8); // to
a61af66fc99e Initial load
duke
parents:
diff changeset
1575 Address count_arg(rsp, 12+12); // byte count
a61af66fc99e Initial load
duke
parents:
diff changeset
1576
a61af66fc99e Initial load
duke
parents:
diff changeset
1577 // Load up:
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1578 __ movptr(from , from_arg);
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1579 __ movptr(to , to_arg);
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1580 __ movl2ptr(count, count_arg);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1581
a61af66fc99e Initial load
duke
parents:
diff changeset
1582 // bump this on entry, not on exit:
a61af66fc99e Initial load
duke
parents:
diff changeset
1583 inc_counter_np(SharedRuntime::_unsafe_array_copy_ctr);
a61af66fc99e Initial load
duke
parents:
diff changeset
1584
a61af66fc99e Initial load
duke
parents:
diff changeset
1585 const Register bits = rsi;
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1586 __ mov(bits, from);
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1587 __ orptr(bits, to);
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1588 __ orptr(bits, count);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1589
a61af66fc99e Initial load
duke
parents:
diff changeset
1590 __ testl(bits, BytesPerLong-1);
a61af66fc99e Initial load
duke
parents:
diff changeset
1591 __ jccb(Assembler::zero, L_long_aligned);
a61af66fc99e Initial load
duke
parents:
diff changeset
1592
a61af66fc99e Initial load
duke
parents:
diff changeset
1593 __ testl(bits, BytesPerInt-1);
a61af66fc99e Initial load
duke
parents:
diff changeset
1594 __ jccb(Assembler::zero, L_int_aligned);
a61af66fc99e Initial load
duke
parents:
diff changeset
1595
a61af66fc99e Initial load
duke
parents:
diff changeset
1596 __ testl(bits, BytesPerShort-1);
a61af66fc99e Initial load
duke
parents:
diff changeset
1597 __ jump_cc(Assembler::notZero, RuntimeAddress(byte_copy_entry));
a61af66fc99e Initial load
duke
parents:
diff changeset
1598
a61af66fc99e Initial load
duke
parents:
diff changeset
1599 __ BIND(L_short_aligned);
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1600 __ shrptr(count, LogBytesPerShort); // size => short_count
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1601 __ movl(count_arg, count); // update 'count'
a61af66fc99e Initial load
duke
parents:
diff changeset
1602 __ jump(RuntimeAddress(short_copy_entry));
a61af66fc99e Initial load
duke
parents:
diff changeset
1603
a61af66fc99e Initial load
duke
parents:
diff changeset
1604 __ BIND(L_int_aligned);
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1605 __ shrptr(count, LogBytesPerInt); // size => int_count
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1606 __ movl(count_arg, count); // update 'count'
a61af66fc99e Initial load
duke
parents:
diff changeset
1607 __ jump(RuntimeAddress(int_copy_entry));
a61af66fc99e Initial load
duke
parents:
diff changeset
1608
a61af66fc99e Initial load
duke
parents:
diff changeset
1609 __ BIND(L_long_aligned);
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1610 __ shrptr(count, LogBytesPerLong); // size => qword_count
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1611 __ movl(count_arg, count); // update 'count'
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1612 __ pop(rdi); // Do pops here since jlong_arraycopy stub does not do it.
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1613 __ pop(rsi);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1614 __ jump(RuntimeAddress(long_copy_entry));
a61af66fc99e Initial load
duke
parents:
diff changeset
1615
a61af66fc99e Initial load
duke
parents:
diff changeset
1616 return start;
a61af66fc99e Initial load
duke
parents:
diff changeset
1617 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1618
a61af66fc99e Initial load
duke
parents:
diff changeset
1619
a61af66fc99e Initial load
duke
parents:
diff changeset
1620 // Perform range checks on the proposed arraycopy.
a61af66fc99e Initial load
duke
parents:
diff changeset
1621 // Smashes src_pos and dst_pos. (Uses them up for temps.)
a61af66fc99e Initial load
duke
parents:
diff changeset
1622 void arraycopy_range_checks(Register src,
a61af66fc99e Initial load
duke
parents:
diff changeset
1623 Register src_pos,
a61af66fc99e Initial load
duke
parents:
diff changeset
1624 Register dst,
a61af66fc99e Initial load
duke
parents:
diff changeset
1625 Register dst_pos,
a61af66fc99e Initial load
duke
parents:
diff changeset
1626 Address& length,
a61af66fc99e Initial load
duke
parents:
diff changeset
1627 Label& L_failed) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1628 BLOCK_COMMENT("arraycopy_range_checks:");
a61af66fc99e Initial load
duke
parents:
diff changeset
1629 const Register src_end = src_pos; // source array end position
a61af66fc99e Initial load
duke
parents:
diff changeset
1630 const Register dst_end = dst_pos; // destination array end position
a61af66fc99e Initial load
duke
parents:
diff changeset
1631 __ addl(src_end, length); // src_pos + length
a61af66fc99e Initial load
duke
parents:
diff changeset
1632 __ addl(dst_end, length); // dst_pos + length
a61af66fc99e Initial load
duke
parents:
diff changeset
1633
a61af66fc99e Initial load
duke
parents:
diff changeset
1634 // if (src_pos + length > arrayOop(src)->length() ) FAIL;
a61af66fc99e Initial load
duke
parents:
diff changeset
1635 __ cmpl(src_end, Address(src, arrayOopDesc::length_offset_in_bytes()));
a61af66fc99e Initial load
duke
parents:
diff changeset
1636 __ jcc(Assembler::above, L_failed);
a61af66fc99e Initial load
duke
parents:
diff changeset
1637
a61af66fc99e Initial load
duke
parents:
diff changeset
1638 // if (dst_pos + length > arrayOop(dst)->length() ) FAIL;
a61af66fc99e Initial load
duke
parents:
diff changeset
1639 __ cmpl(dst_end, Address(dst, arrayOopDesc::length_offset_in_bytes()));
a61af66fc99e Initial load
duke
parents:
diff changeset
1640 __ jcc(Assembler::above, L_failed);
a61af66fc99e Initial load
duke
parents:
diff changeset
1641
a61af66fc99e Initial load
duke
parents:
diff changeset
1642 BLOCK_COMMENT("arraycopy_range_checks done");
a61af66fc99e Initial load
duke
parents:
diff changeset
1643 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1644
a61af66fc99e Initial load
duke
parents:
diff changeset
1645
a61af66fc99e Initial load
duke
parents:
diff changeset
1646 //
a61af66fc99e Initial load
duke
parents:
diff changeset
1647 // Generate generic array copy stubs
a61af66fc99e Initial load
duke
parents:
diff changeset
1648 //
a61af66fc99e Initial load
duke
parents:
diff changeset
1649 // Input:
a61af66fc99e Initial load
duke
parents:
diff changeset
1650 // 4(rsp) - src oop
a61af66fc99e Initial load
duke
parents:
diff changeset
1651 // 8(rsp) - src_pos
a61af66fc99e Initial load
duke
parents:
diff changeset
1652 // 12(rsp) - dst oop
a61af66fc99e Initial load
duke
parents:
diff changeset
1653 // 16(rsp) - dst_pos
a61af66fc99e Initial load
duke
parents:
diff changeset
1654 // 20(rsp) - element count
a61af66fc99e Initial load
duke
parents:
diff changeset
1655 //
a61af66fc99e Initial load
duke
parents:
diff changeset
1656 // Output:
a61af66fc99e Initial load
duke
parents:
diff changeset
1657 // rax, == 0 - success
a61af66fc99e Initial load
duke
parents:
diff changeset
1658 // rax, == -1^K - failure, where K is partial transfer count
a61af66fc99e Initial load
duke
parents:
diff changeset
1659 //
a61af66fc99e Initial load
duke
parents:
diff changeset
1660 address generate_generic_copy(const char *name,
a61af66fc99e Initial load
duke
parents:
diff changeset
1661 address entry_jbyte_arraycopy,
a61af66fc99e Initial load
duke
parents:
diff changeset
1662 address entry_jshort_arraycopy,
a61af66fc99e Initial load
duke
parents:
diff changeset
1663 address entry_jint_arraycopy,
a61af66fc99e Initial load
duke
parents:
diff changeset
1664 address entry_oop_arraycopy,
a61af66fc99e Initial load
duke
parents:
diff changeset
1665 address entry_jlong_arraycopy,
a61af66fc99e Initial load
duke
parents:
diff changeset
1666 address entry_checkcast_arraycopy) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1667 Label L_failed, L_failed_0, L_objArray;
a61af66fc99e Initial load
duke
parents:
diff changeset
1668
a61af66fc99e Initial load
duke
parents:
diff changeset
1669 { int modulus = CodeEntryAlignment;
a61af66fc99e Initial load
duke
parents:
diff changeset
1670 int target = modulus - 5; // 5 = sizeof jmp(L_failed)
a61af66fc99e Initial load
duke
parents:
diff changeset
1671 int advance = target - (__ offset() % modulus);
a61af66fc99e Initial load
duke
parents:
diff changeset
1672 if (advance < 0) advance += modulus;
a61af66fc99e Initial load
duke
parents:
diff changeset
1673 if (advance > 0) __ nop(advance);
a61af66fc99e Initial load
duke
parents:
diff changeset
1674 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1675 StubCodeMark mark(this, "StubRoutines", name);
a61af66fc99e Initial load
duke
parents:
diff changeset
1676
a61af66fc99e Initial load
duke
parents:
diff changeset
1677 // Short-hop target to L_failed. Makes for denser prologue code.
a61af66fc99e Initial load
duke
parents:
diff changeset
1678 __ BIND(L_failed_0);
a61af66fc99e Initial load
duke
parents:
diff changeset
1679 __ jmp(L_failed);
a61af66fc99e Initial load
duke
parents:
diff changeset
1680 assert(__ offset() % CodeEntryAlignment == 0, "no further alignment needed");
a61af66fc99e Initial load
duke
parents:
diff changeset
1681
a61af66fc99e Initial load
duke
parents:
diff changeset
1682 __ align(CodeEntryAlignment);
a61af66fc99e Initial load
duke
parents:
diff changeset
1683 address start = __ pc();
a61af66fc99e Initial load
duke
parents:
diff changeset
1684
a61af66fc99e Initial load
duke
parents:
diff changeset
1685 __ enter(); // required for proper stackwalking of RuntimeStub frame
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1686 __ push(rsi);
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1687 __ push(rdi);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1688
a61af66fc99e Initial load
duke
parents:
diff changeset
1689 // bump this on entry, not on exit:
a61af66fc99e Initial load
duke
parents:
diff changeset
1690 inc_counter_np(SharedRuntime::_generic_array_copy_ctr);
a61af66fc99e Initial load
duke
parents:
diff changeset
1691
a61af66fc99e Initial load
duke
parents:
diff changeset
1692 // Input values
a61af66fc99e Initial load
duke
parents:
diff changeset
1693 Address SRC (rsp, 12+ 4);
a61af66fc99e Initial load
duke
parents:
diff changeset
1694 Address SRC_POS (rsp, 12+ 8);
a61af66fc99e Initial load
duke
parents:
diff changeset
1695 Address DST (rsp, 12+12);
a61af66fc99e Initial load
duke
parents:
diff changeset
1696 Address DST_POS (rsp, 12+16);
a61af66fc99e Initial load
duke
parents:
diff changeset
1697 Address LENGTH (rsp, 12+20);
a61af66fc99e Initial load
duke
parents:
diff changeset
1698
a61af66fc99e Initial load
duke
parents:
diff changeset
1699 //-----------------------------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
1700 // Assembler stub will be used for this call to arraycopy
a61af66fc99e Initial load
duke
parents:
diff changeset
1701 // if the following conditions are met:
a61af66fc99e Initial load
duke
parents:
diff changeset
1702 //
a61af66fc99e Initial load
duke
parents:
diff changeset
1703 // (1) src and dst must not be null.
a61af66fc99e Initial load
duke
parents:
diff changeset
1704 // (2) src_pos must not be negative.
a61af66fc99e Initial load
duke
parents:
diff changeset
1705 // (3) dst_pos must not be negative.
a61af66fc99e Initial load
duke
parents:
diff changeset
1706 // (4) length must not be negative.
a61af66fc99e Initial load
duke
parents:
diff changeset
1707 // (5) src klass and dst klass should be the same and not NULL.
a61af66fc99e Initial load
duke
parents:
diff changeset
1708 // (6) src and dst should be arrays.
a61af66fc99e Initial load
duke
parents:
diff changeset
1709 // (7) src_pos + length must not exceed length of src.
a61af66fc99e Initial load
duke
parents:
diff changeset
1710 // (8) dst_pos + length must not exceed length of dst.
a61af66fc99e Initial load
duke
parents:
diff changeset
1711 //
a61af66fc99e Initial load
duke
parents:
diff changeset
1712
a61af66fc99e Initial load
duke
parents:
diff changeset
1713 const Register src = rax; // source array oop
a61af66fc99e Initial load
duke
parents:
diff changeset
1714 const Register src_pos = rsi;
a61af66fc99e Initial load
duke
parents:
diff changeset
1715 const Register dst = rdx; // destination array oop
a61af66fc99e Initial load
duke
parents:
diff changeset
1716 const Register dst_pos = rdi;
a61af66fc99e Initial load
duke
parents:
diff changeset
1717 const Register length = rcx; // transfer count
a61af66fc99e Initial load
duke
parents:
diff changeset
1718
a61af66fc99e Initial load
duke
parents:
diff changeset
1719 // if (src == NULL) return -1;
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1720 __ movptr(src, SRC); // src oop
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1721 __ testptr(src, src);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1722 __ jccb(Assembler::zero, L_failed_0);
a61af66fc99e Initial load
duke
parents:
diff changeset
1723
a61af66fc99e Initial load
duke
parents:
diff changeset
1724 // if (src_pos < 0) return -1;
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1725 __ movl2ptr(src_pos, SRC_POS); // src_pos
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1726 __ testl(src_pos, src_pos);
a61af66fc99e Initial load
duke
parents:
diff changeset
1727 __ jccb(Assembler::negative, L_failed_0);
a61af66fc99e Initial load
duke
parents:
diff changeset
1728
a61af66fc99e Initial load
duke
parents:
diff changeset
1729 // if (dst == NULL) return -1;
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1730 __ movptr(dst, DST); // dst oop
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1731 __ testptr(dst, dst);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1732 __ jccb(Assembler::zero, L_failed_0);
a61af66fc99e Initial load
duke
parents:
diff changeset
1733
a61af66fc99e Initial load
duke
parents:
diff changeset
1734 // if (dst_pos < 0) return -1;
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1735 __ movl2ptr(dst_pos, DST_POS); // dst_pos
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1736 __ testl(dst_pos, dst_pos);
a61af66fc99e Initial load
duke
parents:
diff changeset
1737 __ jccb(Assembler::negative, L_failed_0);
a61af66fc99e Initial load
duke
parents:
diff changeset
1738
a61af66fc99e Initial load
duke
parents:
diff changeset
1739 // if (length < 0) return -1;
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1740 __ movl2ptr(length, LENGTH); // length
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1741 __ testl(length, length);
a61af66fc99e Initial load
duke
parents:
diff changeset
1742 __ jccb(Assembler::negative, L_failed_0);
a61af66fc99e Initial load
duke
parents:
diff changeset
1743
a61af66fc99e Initial load
duke
parents:
diff changeset
1744 // if (src->klass() == NULL) return -1;
a61af66fc99e Initial load
duke
parents:
diff changeset
1745 Address src_klass_addr(src, oopDesc::klass_offset_in_bytes());
a61af66fc99e Initial load
duke
parents:
diff changeset
1746 Address dst_klass_addr(dst, oopDesc::klass_offset_in_bytes());
a61af66fc99e Initial load
duke
parents:
diff changeset
1747 const Register rcx_src_klass = rcx; // array klass
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1748 __ movptr(rcx_src_klass, Address(src, oopDesc::klass_offset_in_bytes()));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1749
a61af66fc99e Initial load
duke
parents:
diff changeset
1750 #ifdef ASSERT
a61af66fc99e Initial load
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parents:
diff changeset
1751 // assert(src->klass() != NULL);
a61af66fc99e Initial load
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parents:
diff changeset
1752 BLOCK_COMMENT("assert klasses not null");
a61af66fc99e Initial load
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parents:
diff changeset
1753 { Label L1, L2;
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
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parents: 249
diff changeset
1754 __ testptr(rcx_src_klass, rcx_src_klass);
0
a61af66fc99e Initial load
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parents:
diff changeset
1755 __ jccb(Assembler::notZero, L2); // it is broken if klass is NULL
a61af66fc99e Initial load
duke
parents:
diff changeset
1756 __ bind(L1);
a61af66fc99e Initial load
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parents:
diff changeset
1757 __ stop("broken null klass");
a61af66fc99e Initial load
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parents:
diff changeset
1758 __ bind(L2);
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1759 __ cmpptr(dst_klass_addr, (int32_t)NULL_WORD);
0
a61af66fc99e Initial load
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parents:
diff changeset
1760 __ jccb(Assembler::equal, L1); // this would be broken also
a61af66fc99e Initial load
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parents:
diff changeset
1761 BLOCK_COMMENT("assert done");
a61af66fc99e Initial load
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parents:
diff changeset
1762 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1763 #endif //ASSERT
a61af66fc99e Initial load
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parents:
diff changeset
1764
a61af66fc99e Initial load
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parents:
diff changeset
1765 // Load layout helper (32-bits)
a61af66fc99e Initial load
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parents:
diff changeset
1766 //
a61af66fc99e Initial load
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parents:
diff changeset
1767 // |array_tag| | header_size | element_type | |log2_element_size|
a61af66fc99e Initial load
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parents:
diff changeset
1768 // 32 30 24 16 8 2 0
a61af66fc99e Initial load
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parents:
diff changeset
1769 //
a61af66fc99e Initial load
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parents:
diff changeset
1770 // array_tag: typeArray = 0x3, objArray = 0x2, non-array = 0x0
a61af66fc99e Initial load
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parents:
diff changeset
1771 //
a61af66fc99e Initial load
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parents:
diff changeset
1772
4762
069ab3f976d3 7118863: Move sizeof(klassOopDesc) into the *Klass::*_offset_in_bytes() functions
stefank
parents: 3960
diff changeset
1773 int lh_offset = in_bytes(Klass::layout_helper_offset());
0
a61af66fc99e Initial load
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parents:
diff changeset
1774 Address src_klass_lh_addr(rcx_src_klass, lh_offset);
a61af66fc99e Initial load
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parents:
diff changeset
1775
a61af66fc99e Initial load
duke
parents:
diff changeset
1776 // Handle objArrays completely differently...
a61af66fc99e Initial load
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parents:
diff changeset
1777 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
a61af66fc99e Initial load
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parents:
diff changeset
1778 __ cmpl(src_klass_lh_addr, objArray_lh);
a61af66fc99e Initial load
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parents:
diff changeset
1779 __ jcc(Assembler::equal, L_objArray);
a61af66fc99e Initial load
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parents:
diff changeset
1780
a61af66fc99e Initial load
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parents:
diff changeset
1781 // if (src->klass() != dst->klass()) return -1;
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
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parents: 249
diff changeset
1782 __ cmpptr(rcx_src_klass, dst_klass_addr);
0
a61af66fc99e Initial load
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parents:
diff changeset
1783 __ jccb(Assembler::notEqual, L_failed_0);
a61af66fc99e Initial load
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parents:
diff changeset
1784
a61af66fc99e Initial load
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parents:
diff changeset
1785 const Register rcx_lh = rcx; // layout helper
a61af66fc99e Initial load
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parents:
diff changeset
1786 assert(rcx_lh == rcx_src_klass, "known alias");
a61af66fc99e Initial load
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parents:
diff changeset
1787 __ movl(rcx_lh, src_klass_lh_addr);
a61af66fc99e Initial load
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parents:
diff changeset
1788
a61af66fc99e Initial load
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parents:
diff changeset
1789 // if (!src->is_Array()) return -1;
a61af66fc99e Initial load
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parents:
diff changeset
1790 __ cmpl(rcx_lh, Klass::_lh_neutral_value);
a61af66fc99e Initial load
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parents:
diff changeset
1791 __ jcc(Assembler::greaterEqual, L_failed_0); // signed cmp
a61af66fc99e Initial load
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parents:
diff changeset
1792
a61af66fc99e Initial load
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parents:
diff changeset
1793 // At this point, it is known to be a typeArray (array_tag 0x3).
a61af66fc99e Initial load
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parents:
diff changeset
1794 #ifdef ASSERT
a61af66fc99e Initial load
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parents:
diff changeset
1795 { Label L;
a61af66fc99e Initial load
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parents:
diff changeset
1796 __ cmpl(rcx_lh, (Klass::_lh_array_tag_type_value << Klass::_lh_array_tag_shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
1797 __ jcc(Assembler::greaterEqual, L); // signed cmp
a61af66fc99e Initial load
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parents:
diff changeset
1798 __ stop("must be a primitive array");
a61af66fc99e Initial load
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parents:
diff changeset
1799 __ bind(L);
a61af66fc99e Initial load
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parents:
diff changeset
1800 }
a61af66fc99e Initial load
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parents:
diff changeset
1801 #endif
a61af66fc99e Initial load
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parents:
diff changeset
1802
a61af66fc99e Initial load
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parents:
diff changeset
1803 assert_different_registers(src, src_pos, dst, dst_pos, rcx_lh);
a61af66fc99e Initial load
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parents:
diff changeset
1804 arraycopy_range_checks(src, src_pos, dst, dst_pos, LENGTH, L_failed);
a61af66fc99e Initial load
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parents:
diff changeset
1805
6831
d8ce2825b193 8000213: NPG: Should have renamed arrayKlass and typeArrayKlass
coleenp
parents: 6725
diff changeset
1806 // TypeArrayKlass
0
a61af66fc99e Initial load
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parents:
diff changeset
1807 //
a61af66fc99e Initial load
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parents:
diff changeset
1808 // src_addr = (src + array_header_in_bytes()) + (src_pos << log2elemsize);
a61af66fc99e Initial load
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parents:
diff changeset
1809 // dst_addr = (dst + array_header_in_bytes()) + (dst_pos << log2elemsize);
a61af66fc99e Initial load
duke
parents:
diff changeset
1810 //
a61af66fc99e Initial load
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parents:
diff changeset
1811 const Register rsi_offset = rsi; // array offset
a61af66fc99e Initial load
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parents:
diff changeset
1812 const Register src_array = src; // src array offset
a61af66fc99e Initial load
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parents:
diff changeset
1813 const Register dst_array = dst; // dst array offset
a61af66fc99e Initial load
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parents:
diff changeset
1814 const Register rdi_elsize = rdi; // log2 element size
a61af66fc99e Initial load
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parents:
diff changeset
1815
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1816 __ mov(rsi_offset, rcx_lh);
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1817 __ shrptr(rsi_offset, Klass::_lh_header_size_shift);
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1818 __ andptr(rsi_offset, Klass::_lh_header_size_mask); // array_offset
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1819 __ addptr(src_array, rsi_offset); // src array offset
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1820 __ addptr(dst_array, rsi_offset); // dst array offset
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1821 __ andptr(rcx_lh, Klass::_lh_log2_element_size_mask); // log2 elsize
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1822
a61af66fc99e Initial load
duke
parents:
diff changeset
1823 // next registers should be set before the jump to corresponding stub
a61af66fc99e Initial load
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parents:
diff changeset
1824 const Register from = src; // source array address
a61af66fc99e Initial load
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parents:
diff changeset
1825 const Register to = dst; // destination array address
a61af66fc99e Initial load
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parents:
diff changeset
1826 const Register count = rcx; // elements count
a61af66fc99e Initial load
duke
parents:
diff changeset
1827 // some of them should be duplicated on stack
a61af66fc99e Initial load
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parents:
diff changeset
1828 #define FROM Address(rsp, 12+ 4)
a61af66fc99e Initial load
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parents:
diff changeset
1829 #define TO Address(rsp, 12+ 8) // Not used now
a61af66fc99e Initial load
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parents:
diff changeset
1830 #define COUNT Address(rsp, 12+12) // Only for oop arraycopy
a61af66fc99e Initial load
duke
parents:
diff changeset
1831
a61af66fc99e Initial load
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parents:
diff changeset
1832 BLOCK_COMMENT("scale indexes to element size");
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1833 __ movl2ptr(rsi, SRC_POS); // src_pos
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1834 __ shlptr(rsi); // src_pos << rcx (log2 elsize)
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1835 assert(src_array == from, "");
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1836 __ addptr(from, rsi); // from = src_array + SRC_POS << log2 elsize
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1837 __ movl2ptr(rdi, DST_POS); // dst_pos
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1838 __ shlptr(rdi); // dst_pos << rcx (log2 elsize)
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1839 assert(dst_array == to, "");
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1840 __ addptr(to, rdi); // to = dst_array + DST_POS << log2 elsize
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1841 __ movptr(FROM, from); // src_addr
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1842 __ mov(rdi_elsize, rcx_lh); // log2 elsize
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1843 __ movl2ptr(count, LENGTH); // elements count
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1844
a61af66fc99e Initial load
duke
parents:
diff changeset
1845 BLOCK_COMMENT("choose copy loop based on element size");
a61af66fc99e Initial load
duke
parents:
diff changeset
1846 __ cmpl(rdi_elsize, 0);
a61af66fc99e Initial load
duke
parents:
diff changeset
1847
a61af66fc99e Initial load
duke
parents:
diff changeset
1848 __ jump_cc(Assembler::equal, RuntimeAddress(entry_jbyte_arraycopy));
a61af66fc99e Initial load
duke
parents:
diff changeset
1849 __ cmpl(rdi_elsize, LogBytesPerShort);
a61af66fc99e Initial load
duke
parents:
diff changeset
1850 __ jump_cc(Assembler::equal, RuntimeAddress(entry_jshort_arraycopy));
a61af66fc99e Initial load
duke
parents:
diff changeset
1851 __ cmpl(rdi_elsize, LogBytesPerInt);
a61af66fc99e Initial load
duke
parents:
diff changeset
1852 __ jump_cc(Assembler::equal, RuntimeAddress(entry_jint_arraycopy));
a61af66fc99e Initial load
duke
parents:
diff changeset
1853 #ifdef ASSERT
a61af66fc99e Initial load
duke
parents:
diff changeset
1854 __ cmpl(rdi_elsize, LogBytesPerLong);
a61af66fc99e Initial load
duke
parents:
diff changeset
1855 __ jccb(Assembler::notEqual, L_failed);
a61af66fc99e Initial load
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parents:
diff changeset
1856 #endif
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1857 __ pop(rdi); // Do pops here since jlong_arraycopy stub does not do it.
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1858 __ pop(rsi);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1859 __ jump(RuntimeAddress(entry_jlong_arraycopy));
a61af66fc99e Initial load
duke
parents:
diff changeset
1860
a61af66fc99e Initial load
duke
parents:
diff changeset
1861 __ BIND(L_failed);
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1862 __ xorptr(rax, rax);
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1863 __ notptr(rax); // return -1
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1864 __ pop(rdi);
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1865 __ pop(rsi);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1866 __ leave(); // required for proper stackwalking of RuntimeStub frame
a61af66fc99e Initial load
duke
parents:
diff changeset
1867 __ ret(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
1868
6831
d8ce2825b193 8000213: NPG: Should have renamed arrayKlass and typeArrayKlass
coleenp
parents: 6725
diff changeset
1869 // ObjArrayKlass
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1870 __ BIND(L_objArray);
a61af66fc99e Initial load
duke
parents:
diff changeset
1871 // live at this point: rcx_src_klass, src[_pos], dst[_pos]
a61af66fc99e Initial load
duke
parents:
diff changeset
1872
a61af66fc99e Initial load
duke
parents:
diff changeset
1873 Label L_plain_copy, L_checkcast_copy;
a61af66fc99e Initial load
duke
parents:
diff changeset
1874 // test array classes for subtyping
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1875 __ cmpptr(rcx_src_klass, dst_klass_addr); // usual case is exact equality
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1876 __ jccb(Assembler::notEqual, L_checkcast_copy);
a61af66fc99e Initial load
duke
parents:
diff changeset
1877
a61af66fc99e Initial load
duke
parents:
diff changeset
1878 // Identically typed arrays can be copied without element-wise checks.
a61af66fc99e Initial load
duke
parents:
diff changeset
1879 assert_different_registers(src, src_pos, dst, dst_pos, rcx_src_klass);
a61af66fc99e Initial load
duke
parents:
diff changeset
1880 arraycopy_range_checks(src, src_pos, dst, dst_pos, LENGTH, L_failed);
a61af66fc99e Initial load
duke
parents:
diff changeset
1881
a61af66fc99e Initial load
duke
parents:
diff changeset
1882 __ BIND(L_plain_copy);
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1883 __ movl2ptr(count, LENGTH); // elements count
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1884 __ movl2ptr(src_pos, SRC_POS); // reload src_pos
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1885 __ lea(from, Address(src, src_pos, Address::times_ptr,
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1886 arrayOopDesc::base_offset_in_bytes(T_OBJECT))); // src_addr
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1887 __ movl2ptr(dst_pos, DST_POS); // reload dst_pos
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1888 __ lea(to, Address(dst, dst_pos, Address::times_ptr,
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1889 arrayOopDesc::base_offset_in_bytes(T_OBJECT))); // dst_addr
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1890 __ movptr(FROM, from); // src_addr
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1891 __ movptr(TO, to); // dst_addr
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1892 __ movl(COUNT, count); // count
a61af66fc99e Initial load
duke
parents:
diff changeset
1893 __ jump(RuntimeAddress(entry_oop_arraycopy));
a61af66fc99e Initial load
duke
parents:
diff changeset
1894
a61af66fc99e Initial load
duke
parents:
diff changeset
1895 __ BIND(L_checkcast_copy);
a61af66fc99e Initial load
duke
parents:
diff changeset
1896 // live at this point: rcx_src_klass, dst[_pos], src[_pos]
a61af66fc99e Initial load
duke
parents:
diff changeset
1897 {
a61af66fc99e Initial load
duke
parents:
diff changeset
1898 // Handy offsets:
6831
d8ce2825b193 8000213: NPG: Should have renamed arrayKlass and typeArrayKlass
coleenp
parents: 6725
diff changeset
1899 int ek_offset = in_bytes(ObjArrayKlass::element_klass_offset());
4762
069ab3f976d3 7118863: Move sizeof(klassOopDesc) into the *Klass::*_offset_in_bytes() functions
stefank
parents: 3960
diff changeset
1900 int sco_offset = in_bytes(Klass::super_check_offset_offset());
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1901
a61af66fc99e Initial load
duke
parents:
diff changeset
1902 Register rsi_dst_klass = rsi;
a61af66fc99e Initial load
duke
parents:
diff changeset
1903 Register rdi_temp = rdi;
a61af66fc99e Initial load
duke
parents:
diff changeset
1904 assert(rsi_dst_klass == src_pos, "expected alias w/ src_pos");
a61af66fc99e Initial load
duke
parents:
diff changeset
1905 assert(rdi_temp == dst_pos, "expected alias w/ dst_pos");
a61af66fc99e Initial load
duke
parents:
diff changeset
1906 Address dst_klass_lh_addr(rsi_dst_klass, lh_offset);
a61af66fc99e Initial load
duke
parents:
diff changeset
1907
a61af66fc99e Initial load
duke
parents:
diff changeset
1908 // Before looking at dst.length, make sure dst is also an objArray.
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1909 __ movptr(rsi_dst_klass, dst_klass_addr);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1910 __ cmpl(dst_klass_lh_addr, objArray_lh);
a61af66fc99e Initial load
duke
parents:
diff changeset
1911 __ jccb(Assembler::notEqual, L_failed);
a61af66fc99e Initial load
duke
parents:
diff changeset
1912
a61af66fc99e Initial load
duke
parents:
diff changeset
1913 // It is safe to examine both src.length and dst.length.
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1914 __ movl2ptr(src_pos, SRC_POS); // reload rsi
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1915 arraycopy_range_checks(src, src_pos, dst, dst_pos, LENGTH, L_failed);
a61af66fc99e Initial load
duke
parents:
diff changeset
1916 // (Now src_pos and dst_pos are killed, but not src and dst.)
a61af66fc99e Initial load
duke
parents:
diff changeset
1917
a61af66fc99e Initial load
duke
parents:
diff changeset
1918 // We'll need this temp (don't forget to pop it after the type check).
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1919 __ push(rbx);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1920 Register rbx_src_klass = rbx;
a61af66fc99e Initial load
duke
parents:
diff changeset
1921
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1922 __ mov(rbx_src_klass, rcx_src_klass); // spill away from rcx
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1923 __ movptr(rsi_dst_klass, dst_klass_addr);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1924 Address super_check_offset_addr(rsi_dst_klass, sco_offset);
a61af66fc99e Initial load
duke
parents:
diff changeset
1925 Label L_fail_array_check;
a61af66fc99e Initial load
duke
parents:
diff changeset
1926 generate_type_check(rbx_src_klass,
a61af66fc99e Initial load
duke
parents:
diff changeset
1927 super_check_offset_addr, dst_klass_addr,
a61af66fc99e Initial load
duke
parents:
diff changeset
1928 rdi_temp, NULL, &L_fail_array_check);
a61af66fc99e Initial load
duke
parents:
diff changeset
1929 // (On fall-through, we have passed the array type check.)
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1930 __ pop(rbx);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1931 __ jmp(L_plain_copy);
a61af66fc99e Initial load
duke
parents:
diff changeset
1932
a61af66fc99e Initial load
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parents:
diff changeset
1933 __ BIND(L_fail_array_check);
a61af66fc99e Initial load
duke
parents:
diff changeset
1934 // Reshuffle arguments so we can call checkcast_arraycopy:
a61af66fc99e Initial load
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parents:
diff changeset
1935
a61af66fc99e Initial load
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parents:
diff changeset
1936 // match initial saves for checkcast_arraycopy
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1937 // push(rsi); // already done; see above
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1938 // push(rdi); // already done; see above
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1939 // push(rbx); // already done; see above
0
a61af66fc99e Initial load
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parents:
diff changeset
1940
a61af66fc99e Initial load
duke
parents:
diff changeset
1941 // Marshal outgoing arguments now, freeing registers.
a61af66fc99e Initial load
duke
parents:
diff changeset
1942 Address from_arg(rsp, 16+ 4); // from
a61af66fc99e Initial load
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parents:
diff changeset
1943 Address to_arg(rsp, 16+ 8); // to
a61af66fc99e Initial load
duke
parents:
diff changeset
1944 Address length_arg(rsp, 16+12); // elements count
a61af66fc99e Initial load
duke
parents:
diff changeset
1945 Address ckoff_arg(rsp, 16+16); // super_check_offset
a61af66fc99e Initial load
duke
parents:
diff changeset
1946 Address ckval_arg(rsp, 16+20); // super_klass
a61af66fc99e Initial load
duke
parents:
diff changeset
1947
a61af66fc99e Initial load
duke
parents:
diff changeset
1948 Address SRC_POS_arg(rsp, 16+ 8);
a61af66fc99e Initial load
duke
parents:
diff changeset
1949 Address DST_POS_arg(rsp, 16+16);
a61af66fc99e Initial load
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parents:
diff changeset
1950 Address LENGTH_arg(rsp, 16+20);
a61af66fc99e Initial load
duke
parents:
diff changeset
1951 // push rbx, changed the incoming offsets (why not just use rbp,??)
a61af66fc99e Initial load
duke
parents:
diff changeset
1952 // assert(SRC_POS_arg.disp() == SRC_POS.disp() + 4, "");
a61af66fc99e Initial load
duke
parents:
diff changeset
1953
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1954 __ movptr(rbx, Address(rsi_dst_klass, ek_offset));
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1955 __ movl2ptr(length, LENGTH_arg); // reload elements count
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1956 __ movl2ptr(src_pos, SRC_POS_arg); // reload src_pos
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1957 __ movl2ptr(dst_pos, DST_POS_arg); // reload dst_pos
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1958
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1959 __ movptr(ckval_arg, rbx); // destination element type
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1960 __ movl(rbx, Address(rbx, sco_offset));
a61af66fc99e Initial load
duke
parents:
diff changeset
1961 __ movl(ckoff_arg, rbx); // corresponding class check offset
a61af66fc99e Initial load
duke
parents:
diff changeset
1962
a61af66fc99e Initial load
duke
parents:
diff changeset
1963 __ movl(length_arg, length); // outgoing length argument
a61af66fc99e Initial load
duke
parents:
diff changeset
1964
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1965 __ lea(from, Address(src, src_pos, Address::times_ptr,
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1966 arrayOopDesc::base_offset_in_bytes(T_OBJECT)));
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1967 __ movptr(from_arg, from);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1968
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1969 __ lea(to, Address(dst, dst_pos, Address::times_ptr,
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1970 arrayOopDesc::base_offset_in_bytes(T_OBJECT)));
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
1971 __ movptr(to_arg, to);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1972 __ jump(RuntimeAddress(entry_checkcast_arraycopy));
a61af66fc99e Initial load
duke
parents:
diff changeset
1973 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1974
a61af66fc99e Initial load
duke
parents:
diff changeset
1975 return start;
a61af66fc99e Initial load
duke
parents:
diff changeset
1976 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1977
a61af66fc99e Initial load
duke
parents:
diff changeset
1978 void generate_arraycopy_stubs() {
a61af66fc99e Initial load
duke
parents:
diff changeset
1979 address entry;
a61af66fc99e Initial load
duke
parents:
diff changeset
1980 address entry_jbyte_arraycopy;
a61af66fc99e Initial load
duke
parents:
diff changeset
1981 address entry_jshort_arraycopy;
a61af66fc99e Initial load
duke
parents:
diff changeset
1982 address entry_jint_arraycopy;
a61af66fc99e Initial load
duke
parents:
diff changeset
1983 address entry_oop_arraycopy;
a61af66fc99e Initial load
duke
parents:
diff changeset
1984 address entry_jlong_arraycopy;
a61af66fc99e Initial load
duke
parents:
diff changeset
1985 address entry_checkcast_arraycopy;
a61af66fc99e Initial load
duke
parents:
diff changeset
1986
a61af66fc99e Initial load
duke
parents:
diff changeset
1987 StubRoutines::_arrayof_jbyte_disjoint_arraycopy =
a61af66fc99e Initial load
duke
parents:
diff changeset
1988 generate_disjoint_copy(T_BYTE, true, Address::times_1, &entry,
a61af66fc99e Initial load
duke
parents:
diff changeset
1989 "arrayof_jbyte_disjoint_arraycopy");
a61af66fc99e Initial load
duke
parents:
diff changeset
1990 StubRoutines::_arrayof_jbyte_arraycopy =
a61af66fc99e Initial load
duke
parents:
diff changeset
1991 generate_conjoint_copy(T_BYTE, true, Address::times_1, entry,
a61af66fc99e Initial load
duke
parents:
diff changeset
1992 NULL, "arrayof_jbyte_arraycopy");
a61af66fc99e Initial load
duke
parents:
diff changeset
1993 StubRoutines::_jbyte_disjoint_arraycopy =
a61af66fc99e Initial load
duke
parents:
diff changeset
1994 generate_disjoint_copy(T_BYTE, false, Address::times_1, &entry,
a61af66fc99e Initial load
duke
parents:
diff changeset
1995 "jbyte_disjoint_arraycopy");
a61af66fc99e Initial load
duke
parents:
diff changeset
1996 StubRoutines::_jbyte_arraycopy =
a61af66fc99e Initial load
duke
parents:
diff changeset
1997 generate_conjoint_copy(T_BYTE, false, Address::times_1, entry,
a61af66fc99e Initial load
duke
parents:
diff changeset
1998 &entry_jbyte_arraycopy, "jbyte_arraycopy");
a61af66fc99e Initial load
duke
parents:
diff changeset
1999
a61af66fc99e Initial load
duke
parents:
diff changeset
2000 StubRoutines::_arrayof_jshort_disjoint_arraycopy =
a61af66fc99e Initial load
duke
parents:
diff changeset
2001 generate_disjoint_copy(T_SHORT, true, Address::times_2, &entry,
a61af66fc99e Initial load
duke
parents:
diff changeset
2002 "arrayof_jshort_disjoint_arraycopy");
a61af66fc99e Initial load
duke
parents:
diff changeset
2003 StubRoutines::_arrayof_jshort_arraycopy =
a61af66fc99e Initial load
duke
parents:
diff changeset
2004 generate_conjoint_copy(T_SHORT, true, Address::times_2, entry,
a61af66fc99e Initial load
duke
parents:
diff changeset
2005 NULL, "arrayof_jshort_arraycopy");
a61af66fc99e Initial load
duke
parents:
diff changeset
2006 StubRoutines::_jshort_disjoint_arraycopy =
a61af66fc99e Initial load
duke
parents:
diff changeset
2007 generate_disjoint_copy(T_SHORT, false, Address::times_2, &entry,
a61af66fc99e Initial load
duke
parents:
diff changeset
2008 "jshort_disjoint_arraycopy");
a61af66fc99e Initial load
duke
parents:
diff changeset
2009 StubRoutines::_jshort_arraycopy =
a61af66fc99e Initial load
duke
parents:
diff changeset
2010 generate_conjoint_copy(T_SHORT, false, Address::times_2, entry,
a61af66fc99e Initial load
duke
parents:
diff changeset
2011 &entry_jshort_arraycopy, "jshort_arraycopy");
a61af66fc99e Initial load
duke
parents:
diff changeset
2012
a61af66fc99e Initial load
duke
parents:
diff changeset
2013 // Next arrays are always aligned on 4 bytes at least.
a61af66fc99e Initial load
duke
parents:
diff changeset
2014 StubRoutines::_jint_disjoint_arraycopy =
a61af66fc99e Initial load
duke
parents:
diff changeset
2015 generate_disjoint_copy(T_INT, true, Address::times_4, &entry,
a61af66fc99e Initial load
duke
parents:
diff changeset
2016 "jint_disjoint_arraycopy");
a61af66fc99e Initial load
duke
parents:
diff changeset
2017 StubRoutines::_jint_arraycopy =
a61af66fc99e Initial load
duke
parents:
diff changeset
2018 generate_conjoint_copy(T_INT, true, Address::times_4, entry,
a61af66fc99e Initial load
duke
parents:
diff changeset
2019 &entry_jint_arraycopy, "jint_arraycopy");
a61af66fc99e Initial load
duke
parents:
diff changeset
2020
a61af66fc99e Initial load
duke
parents:
diff changeset
2021 StubRoutines::_oop_disjoint_arraycopy =
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
2022 generate_disjoint_copy(T_OBJECT, true, Address::times_ptr, &entry,
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2023 "oop_disjoint_arraycopy");
a61af66fc99e Initial load
duke
parents:
diff changeset
2024 StubRoutines::_oop_arraycopy =
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
2025 generate_conjoint_copy(T_OBJECT, true, Address::times_ptr, entry,
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2026 &entry_oop_arraycopy, "oop_arraycopy");
a61af66fc99e Initial load
duke
parents:
diff changeset
2027
2324
0ac769a57c64 6627983: G1: Bad oop deference during marking
iveresov
parents: 2321
diff changeset
2028 StubRoutines::_oop_disjoint_arraycopy_uninit =
0ac769a57c64 6627983: G1: Bad oop deference during marking
iveresov
parents: 2321
diff changeset
2029 generate_disjoint_copy(T_OBJECT, true, Address::times_ptr, &entry,
0ac769a57c64 6627983: G1: Bad oop deference during marking
iveresov
parents: 2321
diff changeset
2030 "oop_disjoint_arraycopy_uninit",
0ac769a57c64 6627983: G1: Bad oop deference during marking
iveresov
parents: 2321
diff changeset
2031 /*dest_uninitialized*/true);
0ac769a57c64 6627983: G1: Bad oop deference during marking
iveresov
parents: 2321
diff changeset
2032 StubRoutines::_oop_arraycopy_uninit =
0ac769a57c64 6627983: G1: Bad oop deference during marking
iveresov
parents: 2321
diff changeset
2033 generate_conjoint_copy(T_OBJECT, true, Address::times_ptr, entry,
0ac769a57c64 6627983: G1: Bad oop deference during marking
iveresov
parents: 2321
diff changeset
2034 NULL, "oop_arraycopy_uninit",
0ac769a57c64 6627983: G1: Bad oop deference during marking
iveresov
parents: 2321
diff changeset
2035 /*dest_uninitialized*/true);
0ac769a57c64 6627983: G1: Bad oop deference during marking
iveresov
parents: 2321
diff changeset
2036
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2037 StubRoutines::_jlong_disjoint_arraycopy =
a61af66fc99e Initial load
duke
parents:
diff changeset
2038 generate_disjoint_long_copy(&entry, "jlong_disjoint_arraycopy");
a61af66fc99e Initial load
duke
parents:
diff changeset
2039 StubRoutines::_jlong_arraycopy =
a61af66fc99e Initial load
duke
parents:
diff changeset
2040 generate_conjoint_long_copy(entry, &entry_jlong_arraycopy,
a61af66fc99e Initial load
duke
parents:
diff changeset
2041 "jlong_arraycopy");
a61af66fc99e Initial load
duke
parents:
diff changeset
2042
1763
d6f45b55c972 4809552: Optimize Arrays.fill(...)
never
parents: 1552
diff changeset
2043 StubRoutines::_jbyte_fill = generate_fill(T_BYTE, false, "jbyte_fill");
d6f45b55c972 4809552: Optimize Arrays.fill(...)
never
parents: 1552
diff changeset
2044 StubRoutines::_jshort_fill = generate_fill(T_SHORT, false, "jshort_fill");
d6f45b55c972 4809552: Optimize Arrays.fill(...)
never
parents: 1552
diff changeset
2045 StubRoutines::_jint_fill = generate_fill(T_INT, false, "jint_fill");
d6f45b55c972 4809552: Optimize Arrays.fill(...)
never
parents: 1552
diff changeset
2046 StubRoutines::_arrayof_jbyte_fill = generate_fill(T_BYTE, true, "arrayof_jbyte_fill");
d6f45b55c972 4809552: Optimize Arrays.fill(...)
never
parents: 1552
diff changeset
2047 StubRoutines::_arrayof_jshort_fill = generate_fill(T_SHORT, true, "arrayof_jshort_fill");
d6f45b55c972 4809552: Optimize Arrays.fill(...)
never
parents: 1552
diff changeset
2048 StubRoutines::_arrayof_jint_fill = generate_fill(T_INT, true, "arrayof_jint_fill");
d6f45b55c972 4809552: Optimize Arrays.fill(...)
never
parents: 1552
diff changeset
2049
2324
0ac769a57c64 6627983: G1: Bad oop deference during marking
iveresov
parents: 2321
diff changeset
2050 StubRoutines::_arrayof_jint_disjoint_arraycopy = StubRoutines::_jint_disjoint_arraycopy;
0ac769a57c64 6627983: G1: Bad oop deference during marking
iveresov
parents: 2321
diff changeset
2051 StubRoutines::_arrayof_oop_disjoint_arraycopy = StubRoutines::_oop_disjoint_arraycopy;
0ac769a57c64 6627983: G1: Bad oop deference during marking
iveresov
parents: 2321
diff changeset
2052 StubRoutines::_arrayof_oop_disjoint_arraycopy_uninit = StubRoutines::_oop_disjoint_arraycopy_uninit;
0ac769a57c64 6627983: G1: Bad oop deference during marking
iveresov
parents: 2321
diff changeset
2053 StubRoutines::_arrayof_jlong_disjoint_arraycopy = StubRoutines::_jlong_disjoint_arraycopy;
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2054
2324
0ac769a57c64 6627983: G1: Bad oop deference during marking
iveresov
parents: 2321
diff changeset
2055 StubRoutines::_arrayof_jint_arraycopy = StubRoutines::_jint_arraycopy;
0ac769a57c64 6627983: G1: Bad oop deference during marking
iveresov
parents: 2321
diff changeset
2056 StubRoutines::_arrayof_oop_arraycopy = StubRoutines::_oop_arraycopy;
0ac769a57c64 6627983: G1: Bad oop deference during marking
iveresov
parents: 2321
diff changeset
2057 StubRoutines::_arrayof_oop_arraycopy_uninit = StubRoutines::_oop_arraycopy_uninit;
0ac769a57c64 6627983: G1: Bad oop deference during marking
iveresov
parents: 2321
diff changeset
2058 StubRoutines::_arrayof_jlong_arraycopy = StubRoutines::_jlong_arraycopy;
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2059
a61af66fc99e Initial load
duke
parents:
diff changeset
2060 StubRoutines::_checkcast_arraycopy =
2324
0ac769a57c64 6627983: G1: Bad oop deference during marking
iveresov
parents: 2321
diff changeset
2061 generate_checkcast_copy("checkcast_arraycopy", &entry_checkcast_arraycopy);
0ac769a57c64 6627983: G1: Bad oop deference during marking
iveresov
parents: 2321
diff changeset
2062 StubRoutines::_checkcast_arraycopy_uninit =
0ac769a57c64 6627983: G1: Bad oop deference during marking
iveresov
parents: 2321
diff changeset
2063 generate_checkcast_copy("checkcast_arraycopy_uninit", NULL, /*dest_uninitialized*/true);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2064
a61af66fc99e Initial load
duke
parents:
diff changeset
2065 StubRoutines::_unsafe_arraycopy =
a61af66fc99e Initial load
duke
parents:
diff changeset
2066 generate_unsafe_copy("unsafe_arraycopy",
a61af66fc99e Initial load
duke
parents:
diff changeset
2067 entry_jbyte_arraycopy,
a61af66fc99e Initial load
duke
parents:
diff changeset
2068 entry_jshort_arraycopy,
a61af66fc99e Initial load
duke
parents:
diff changeset
2069 entry_jint_arraycopy,
a61af66fc99e Initial load
duke
parents:
diff changeset
2070 entry_jlong_arraycopy);
a61af66fc99e Initial load
duke
parents:
diff changeset
2071
a61af66fc99e Initial load
duke
parents:
diff changeset
2072 StubRoutines::_generic_arraycopy =
a61af66fc99e Initial load
duke
parents:
diff changeset
2073 generate_generic_copy("generic_arraycopy",
a61af66fc99e Initial load
duke
parents:
diff changeset
2074 entry_jbyte_arraycopy,
a61af66fc99e Initial load
duke
parents:
diff changeset
2075 entry_jshort_arraycopy,
a61af66fc99e Initial load
duke
parents:
diff changeset
2076 entry_jint_arraycopy,
a61af66fc99e Initial load
duke
parents:
diff changeset
2077 entry_oop_arraycopy,
a61af66fc99e Initial load
duke
parents:
diff changeset
2078 entry_jlong_arraycopy,
a61af66fc99e Initial load
duke
parents:
diff changeset
2079 entry_checkcast_arraycopy);
a61af66fc99e Initial load
duke
parents:
diff changeset
2080 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2081
1174
ddb7834449d0 6849984: Value methods for platform dependent math functions constant fold incorrectly
never
parents: 845
diff changeset
2082 void generate_math_stubs() {
ddb7834449d0 6849984: Value methods for platform dependent math functions constant fold incorrectly
never
parents: 845
diff changeset
2083 {
ddb7834449d0 6849984: Value methods for platform dependent math functions constant fold incorrectly
never
parents: 845
diff changeset
2084 StubCodeMark mark(this, "StubRoutines", "log");
ddb7834449d0 6849984: Value methods for platform dependent math functions constant fold incorrectly
never
parents: 845
diff changeset
2085 StubRoutines::_intrinsic_log = (double (*)(double)) __ pc();
ddb7834449d0 6849984: Value methods for platform dependent math functions constant fold incorrectly
never
parents: 845
diff changeset
2086
ddb7834449d0 6849984: Value methods for platform dependent math functions constant fold incorrectly
never
parents: 845
diff changeset
2087 __ fld_d(Address(rsp, 4));
ddb7834449d0 6849984: Value methods for platform dependent math functions constant fold incorrectly
never
parents: 845
diff changeset
2088 __ flog();
ddb7834449d0 6849984: Value methods for platform dependent math functions constant fold incorrectly
never
parents: 845
diff changeset
2089 __ ret(0);
ddb7834449d0 6849984: Value methods for platform dependent math functions constant fold incorrectly
never
parents: 845
diff changeset
2090 }
ddb7834449d0 6849984: Value methods for platform dependent math functions constant fold incorrectly
never
parents: 845
diff changeset
2091 {
ddb7834449d0 6849984: Value methods for platform dependent math functions constant fold incorrectly
never
parents: 845
diff changeset
2092 StubCodeMark mark(this, "StubRoutines", "log10");
ddb7834449d0 6849984: Value methods for platform dependent math functions constant fold incorrectly
never
parents: 845
diff changeset
2093 StubRoutines::_intrinsic_log10 = (double (*)(double)) __ pc();
ddb7834449d0 6849984: Value methods for platform dependent math functions constant fold incorrectly
never
parents: 845
diff changeset
2094
ddb7834449d0 6849984: Value methods for platform dependent math functions constant fold incorrectly
never
parents: 845
diff changeset
2095 __ fld_d(Address(rsp, 4));
ddb7834449d0 6849984: Value methods for platform dependent math functions constant fold incorrectly
never
parents: 845
diff changeset
2096 __ flog10();
ddb7834449d0 6849984: Value methods for platform dependent math functions constant fold incorrectly
never
parents: 845
diff changeset
2097 __ ret(0);
ddb7834449d0 6849984: Value methods for platform dependent math functions constant fold incorrectly
never
parents: 845
diff changeset
2098 }
ddb7834449d0 6849984: Value methods for platform dependent math functions constant fold incorrectly
never
parents: 845
diff changeset
2099 {
ddb7834449d0 6849984: Value methods for platform dependent math functions constant fold incorrectly
never
parents: 845
diff changeset
2100 StubCodeMark mark(this, "StubRoutines", "sin");
ddb7834449d0 6849984: Value methods for platform dependent math functions constant fold incorrectly
never
parents: 845
diff changeset
2101 StubRoutines::_intrinsic_sin = (double (*)(double)) __ pc();
ddb7834449d0 6849984: Value methods for platform dependent math functions constant fold incorrectly
never
parents: 845
diff changeset
2102
ddb7834449d0 6849984: Value methods for platform dependent math functions constant fold incorrectly
never
parents: 845
diff changeset
2103 __ fld_d(Address(rsp, 4));
ddb7834449d0 6849984: Value methods for platform dependent math functions constant fold incorrectly
never
parents: 845
diff changeset
2104 __ trigfunc('s');
ddb7834449d0 6849984: Value methods for platform dependent math functions constant fold incorrectly
never
parents: 845
diff changeset
2105 __ ret(0);
ddb7834449d0 6849984: Value methods for platform dependent math functions constant fold incorrectly
never
parents: 845
diff changeset
2106 }
ddb7834449d0 6849984: Value methods for platform dependent math functions constant fold incorrectly
never
parents: 845
diff changeset
2107 {
ddb7834449d0 6849984: Value methods for platform dependent math functions constant fold incorrectly
never
parents: 845
diff changeset
2108 StubCodeMark mark(this, "StubRoutines", "cos");
ddb7834449d0 6849984: Value methods for platform dependent math functions constant fold incorrectly
never
parents: 845
diff changeset
2109 StubRoutines::_intrinsic_cos = (double (*)(double)) __ pc();
ddb7834449d0 6849984: Value methods for platform dependent math functions constant fold incorrectly
never
parents: 845
diff changeset
2110
ddb7834449d0 6849984: Value methods for platform dependent math functions constant fold incorrectly
never
parents: 845
diff changeset
2111 __ fld_d(Address(rsp, 4));
ddb7834449d0 6849984: Value methods for platform dependent math functions constant fold incorrectly
never
parents: 845
diff changeset
2112 __ trigfunc('c');
ddb7834449d0 6849984: Value methods for platform dependent math functions constant fold incorrectly
never
parents: 845
diff changeset
2113 __ ret(0);
ddb7834449d0 6849984: Value methods for platform dependent math functions constant fold incorrectly
never
parents: 845
diff changeset
2114 }
ddb7834449d0 6849984: Value methods for platform dependent math functions constant fold incorrectly
never
parents: 845
diff changeset
2115 {
ddb7834449d0 6849984: Value methods for platform dependent math functions constant fold incorrectly
never
parents: 845
diff changeset
2116 StubCodeMark mark(this, "StubRoutines", "tan");
ddb7834449d0 6849984: Value methods for platform dependent math functions constant fold incorrectly
never
parents: 845
diff changeset
2117 StubRoutines::_intrinsic_tan = (double (*)(double)) __ pc();
ddb7834449d0 6849984: Value methods for platform dependent math functions constant fold incorrectly
never
parents: 845
diff changeset
2118
ddb7834449d0 6849984: Value methods for platform dependent math functions constant fold incorrectly
never
parents: 845
diff changeset
2119 __ fld_d(Address(rsp, 4));
ddb7834449d0 6849984: Value methods for platform dependent math functions constant fold incorrectly
never
parents: 845
diff changeset
2120 __ trigfunc('t');
ddb7834449d0 6849984: Value methods for platform dependent math functions constant fold incorrectly
never
parents: 845
diff changeset
2121 __ ret(0);
ddb7834449d0 6849984: Value methods for platform dependent math functions constant fold incorrectly
never
parents: 845
diff changeset
2122 }
6084
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 4771
diff changeset
2123 {
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 4771
diff changeset
2124 StubCodeMark mark(this, "StubRoutines", "exp");
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 4771
diff changeset
2125 StubRoutines::_intrinsic_exp = (double (*)(double)) __ pc();
1174
ddb7834449d0 6849984: Value methods for platform dependent math functions constant fold incorrectly
never
parents: 845
diff changeset
2126
6084
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 4771
diff changeset
2127 __ fld_d(Address(rsp, 4));
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 4771
diff changeset
2128 __ exp_with_fallback(0);
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 4771
diff changeset
2129 __ ret(0);
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 4771
diff changeset
2130 }
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 4771
diff changeset
2131 {
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 4771
diff changeset
2132 StubCodeMark mark(this, "StubRoutines", "pow");
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 4771
diff changeset
2133 StubRoutines::_intrinsic_pow = (double (*)(double,double)) __ pc();
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 4771
diff changeset
2134
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 4771
diff changeset
2135 __ fld_d(Address(rsp, 12));
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 4771
diff changeset
2136 __ fld_d(Address(rsp, 4));
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 4771
diff changeset
2137 __ pow_with_fallback(0);
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 4771
diff changeset
2138 __ ret(0);
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 4771
diff changeset
2139 }
1174
ddb7834449d0 6849984: Value methods for platform dependent math functions constant fold incorrectly
never
parents: 845
diff changeset
2140 }
ddb7834449d0 6849984: Value methods for platform dependent math functions constant fold incorrectly
never
parents: 845
diff changeset
2141
6894
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2142 // AES intrinsic stubs
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2143 enum {AESBlockSize = 16};
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2144
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2145 address generate_key_shuffle_mask() {
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2146 __ align(16);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2147 StubCodeMark mark(this, "StubRoutines", "key_shuffle_mask");
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2148 address start = __ pc();
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2149 __ emit_data(0x00010203, relocInfo::none, 0 );
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2150 __ emit_data(0x04050607, relocInfo::none, 0 );
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2151 __ emit_data(0x08090a0b, relocInfo::none, 0 );
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2152 __ emit_data(0x0c0d0e0f, relocInfo::none, 0 );
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2153 return start;
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2154 }
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2155
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2156 // Utility routine for loading a 128-bit key word in little endian format
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2157 // can optionally specify that the shuffle mask is already in an xmmregister
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2158 void load_key(XMMRegister xmmdst, Register key, int offset, XMMRegister xmm_shuf_mask=NULL) {
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2159 __ movdqu(xmmdst, Address(key, offset));
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2160 if (xmm_shuf_mask != NULL) {
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2161 __ pshufb(xmmdst, xmm_shuf_mask);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2162 } else {
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2163 __ pshufb(xmmdst, ExternalAddress(StubRoutines::x86::key_shuffle_mask_addr()));
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2164 }
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2165 }
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2166
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2167 // aesenc using specified key+offset
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2168 // can optionally specify that the shuffle mask is already in an xmmregister
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2169 void aes_enc_key(XMMRegister xmmdst, XMMRegister xmmtmp, Register key, int offset, XMMRegister xmm_shuf_mask=NULL) {
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2170 load_key(xmmtmp, key, offset, xmm_shuf_mask);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2171 __ aesenc(xmmdst, xmmtmp);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2172 }
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2173
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2174 // aesdec using specified key+offset
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2175 // can optionally specify that the shuffle mask is already in an xmmregister
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2176 void aes_dec_key(XMMRegister xmmdst, XMMRegister xmmtmp, Register key, int offset, XMMRegister xmm_shuf_mask=NULL) {
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2177 load_key(xmmtmp, key, offset, xmm_shuf_mask);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2178 __ aesdec(xmmdst, xmmtmp);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2179 }
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2180
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2181
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2182 // Arguments:
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2183 //
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2184 // Inputs:
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2185 // c_rarg0 - source byte array address
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2186 // c_rarg1 - destination byte array address
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2187 // c_rarg2 - K (key) in little endian int array
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2188 //
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2189 address generate_aescrypt_encryptBlock() {
7427
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2190 assert(UseAES, "need AES instructions and misaligned SSE support");
6894
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2191 __ align(CodeEntryAlignment);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2192 StubCodeMark mark(this, "StubRoutines", "aescrypt_encryptBlock");
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2193 Label L_doLast;
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2194 address start = __ pc();
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2195
7427
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2196 const Register from = rdx; // source array address
6894
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2197 const Register to = rdx; // destination array address
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2198 const Register key = rcx; // key array address
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2199 const Register keylen = rax;
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2200 const Address from_param(rbp, 8+0);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2201 const Address to_param (rbp, 8+4);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2202 const Address key_param (rbp, 8+8);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2203
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2204 const XMMRegister xmm_result = xmm0;
7427
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2205 const XMMRegister xmm_key_shuf_mask = xmm1;
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2206 const XMMRegister xmm_temp1 = xmm2;
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2207 const XMMRegister xmm_temp2 = xmm3;
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2208 const XMMRegister xmm_temp3 = xmm4;
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2209 const XMMRegister xmm_temp4 = xmm5;
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2210
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2211 __ enter(); // required for proper stackwalking of RuntimeStub frame
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2212 __ movptr(from, from_param);
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2213 __ movptr(key, key_param);
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2214
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2215 // keylen could be only {11, 13, 15} * 4 = {44, 52, 60}
6894
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2216 __ movl(keylen, Address(key, arrayOopDesc::length_offset_in_bytes() - arrayOopDesc::base_offset_in_bytes(T_INT)));
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2217
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2218 __ movdqu(xmm_key_shuf_mask, ExternalAddress(StubRoutines::x86::key_shuffle_mask_addr()));
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2219 __ movdqu(xmm_result, Address(from, 0)); // get 16 bytes of input
7427
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2220 __ movptr(to, to_param);
6894
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2221
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2222 // For encryption, the java expanded key ordering is just what we need
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2223
7427
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2224 load_key(xmm_temp1, key, 0x00, xmm_key_shuf_mask);
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2225 __ pxor(xmm_result, xmm_temp1);
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2226
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2227 load_key(xmm_temp1, key, 0x10, xmm_key_shuf_mask);
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2228 load_key(xmm_temp2, key, 0x20, xmm_key_shuf_mask);
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2229 load_key(xmm_temp3, key, 0x30, xmm_key_shuf_mask);
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2230 load_key(xmm_temp4, key, 0x40, xmm_key_shuf_mask);
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2231
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2232 __ aesenc(xmm_result, xmm_temp1);
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2233 __ aesenc(xmm_result, xmm_temp2);
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2234 __ aesenc(xmm_result, xmm_temp3);
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2235 __ aesenc(xmm_result, xmm_temp4);
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2236
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2237 load_key(xmm_temp1, key, 0x50, xmm_key_shuf_mask);
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2238 load_key(xmm_temp2, key, 0x60, xmm_key_shuf_mask);
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2239 load_key(xmm_temp3, key, 0x70, xmm_key_shuf_mask);
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2240 load_key(xmm_temp4, key, 0x80, xmm_key_shuf_mask);
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2241
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2242 __ aesenc(xmm_result, xmm_temp1);
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2243 __ aesenc(xmm_result, xmm_temp2);
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2244 __ aesenc(xmm_result, xmm_temp3);
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2245 __ aesenc(xmm_result, xmm_temp4);
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2246
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2247 load_key(xmm_temp1, key, 0x90, xmm_key_shuf_mask);
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2248 load_key(xmm_temp2, key, 0xa0, xmm_key_shuf_mask);
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2249
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2250 __ cmpl(keylen, 44);
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2251 __ jccb(Assembler::equal, L_doLast);
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2252
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2253 __ aesenc(xmm_result, xmm_temp1);
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2254 __ aesenc(xmm_result, xmm_temp2);
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2255
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2256 load_key(xmm_temp1, key, 0xb0, xmm_key_shuf_mask);
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2257 load_key(xmm_temp2, key, 0xc0, xmm_key_shuf_mask);
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2258
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2259 __ cmpl(keylen, 52);
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2260 __ jccb(Assembler::equal, L_doLast);
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2261
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2262 __ aesenc(xmm_result, xmm_temp1);
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2263 __ aesenc(xmm_result, xmm_temp2);
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2264
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2265 load_key(xmm_temp1, key, 0xd0, xmm_key_shuf_mask);
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2266 load_key(xmm_temp2, key, 0xe0, xmm_key_shuf_mask);
6894
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2267
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2268 __ BIND(L_doLast);
7427
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2269 __ aesenc(xmm_result, xmm_temp1);
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2270 __ aesenclast(xmm_result, xmm_temp2);
6894
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2271 __ movdqu(Address(to, 0), xmm_result); // store the result
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2272 __ xorptr(rax, rax); // return 0
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2273 __ leave(); // required for proper stackwalking of RuntimeStub frame
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2274 __ ret(0);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2275
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2276 return start;
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2277 }
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2278
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2279
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2280 // Arguments:
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2281 //
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2282 // Inputs:
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2283 // c_rarg0 - source byte array address
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2284 // c_rarg1 - destination byte array address
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2285 // c_rarg2 - K (key) in little endian int array
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2286 //
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2287 address generate_aescrypt_decryptBlock() {
7427
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2288 assert(UseAES, "need AES instructions and misaligned SSE support");
6894
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2289 __ align(CodeEntryAlignment);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2290 StubCodeMark mark(this, "StubRoutines", "aescrypt_decryptBlock");
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2291 Label L_doLast;
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2292 address start = __ pc();
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2293
7427
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2294 const Register from = rdx; // source array address
6894
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2295 const Register to = rdx; // destination array address
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2296 const Register key = rcx; // key array address
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2297 const Register keylen = rax;
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2298 const Address from_param(rbp, 8+0);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2299 const Address to_param (rbp, 8+4);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2300 const Address key_param (rbp, 8+8);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2301
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2302 const XMMRegister xmm_result = xmm0;
7427
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2303 const XMMRegister xmm_key_shuf_mask = xmm1;
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2304 const XMMRegister xmm_temp1 = xmm2;
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2305 const XMMRegister xmm_temp2 = xmm3;
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2306 const XMMRegister xmm_temp3 = xmm4;
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2307 const XMMRegister xmm_temp4 = xmm5;
6894
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2308
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2309 __ enter(); // required for proper stackwalking of RuntimeStub frame
7427
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2310 __ movptr(from, from_param);
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2311 __ movptr(key, key_param);
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2312
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2313 // keylen could be only {11, 13, 15} * 4 = {44, 52, 60}
6894
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2314 __ movl(keylen, Address(key, arrayOopDesc::length_offset_in_bytes() - arrayOopDesc::base_offset_in_bytes(T_INT)));
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2315
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2316 __ movdqu(xmm_key_shuf_mask, ExternalAddress(StubRoutines::x86::key_shuffle_mask_addr()));
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2317 __ movdqu(xmm_result, Address(from, 0));
7427
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2318 __ movptr(to, to_param);
6894
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2319
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2320 // for decryption java expanded key ordering is rotated one position from what we want
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2321 // so we start from 0x10 here and hit 0x00 last
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2322 // we don't know if the key is aligned, hence not using load-execute form
7427
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2323 load_key(xmm_temp1, key, 0x10, xmm_key_shuf_mask);
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2324 load_key(xmm_temp2, key, 0x20, xmm_key_shuf_mask);
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2325 load_key(xmm_temp3, key, 0x30, xmm_key_shuf_mask);
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2326 load_key(xmm_temp4, key, 0x40, xmm_key_shuf_mask);
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2327
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2328 __ pxor (xmm_result, xmm_temp1);
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2329 __ aesdec(xmm_result, xmm_temp2);
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2330 __ aesdec(xmm_result, xmm_temp3);
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2331 __ aesdec(xmm_result, xmm_temp4);
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2332
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2333 load_key(xmm_temp1, key, 0x50, xmm_key_shuf_mask);
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2334 load_key(xmm_temp2, key, 0x60, xmm_key_shuf_mask);
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2335 load_key(xmm_temp3, key, 0x70, xmm_key_shuf_mask);
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2336 load_key(xmm_temp4, key, 0x80, xmm_key_shuf_mask);
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2337
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2338 __ aesdec(xmm_result, xmm_temp1);
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2339 __ aesdec(xmm_result, xmm_temp2);
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2340 __ aesdec(xmm_result, xmm_temp3);
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2341 __ aesdec(xmm_result, xmm_temp4);
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2342
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2343 load_key(xmm_temp1, key, 0x90, xmm_key_shuf_mask);
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2344 load_key(xmm_temp2, key, 0xa0, xmm_key_shuf_mask);
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2345 load_key(xmm_temp3, key, 0x00, xmm_key_shuf_mask);
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2346
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2347 __ cmpl(keylen, 44);
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2348 __ jccb(Assembler::equal, L_doLast);
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2349
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2350 __ aesdec(xmm_result, xmm_temp1);
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2351 __ aesdec(xmm_result, xmm_temp2);
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2352
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2353 load_key(xmm_temp1, key, 0xb0, xmm_key_shuf_mask);
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2354 load_key(xmm_temp2, key, 0xc0, xmm_key_shuf_mask);
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2355
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2356 __ cmpl(keylen, 52);
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2357 __ jccb(Assembler::equal, L_doLast);
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2358
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2359 __ aesdec(xmm_result, xmm_temp1);
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2360 __ aesdec(xmm_result, xmm_temp2);
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2361
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2362 load_key(xmm_temp1, key, 0xd0, xmm_key_shuf_mask);
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2363 load_key(xmm_temp2, key, 0xe0, xmm_key_shuf_mask);
6894
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2364
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2365 __ BIND(L_doLast);
7427
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2366 __ aesdec(xmm_result, xmm_temp1);
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2367 __ aesdec(xmm_result, xmm_temp2);
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2368
6894
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2369 // for decryption the aesdeclast operation is always on key+0x00
7427
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2370 __ aesdeclast(xmm_result, xmm_temp3);
6894
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2371 __ movdqu(Address(to, 0), xmm_result); // store the result
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2372 __ xorptr(rax, rax); // return 0
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2373 __ leave(); // required for proper stackwalking of RuntimeStub frame
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2374 __ ret(0);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2375
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2376 return start;
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2377 }
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2378
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2379 void handleSOERegisters(bool saving) {
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2380 const int saveFrameSizeInBytes = 4 * wordSize;
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2381 const Address saved_rbx (rbp, -3 * wordSize);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2382 const Address saved_rsi (rbp, -2 * wordSize);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2383 const Address saved_rdi (rbp, -1 * wordSize);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2384
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2385 if (saving) {
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2386 __ subptr(rsp, saveFrameSizeInBytes);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2387 __ movptr(saved_rsi, rsi);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2388 __ movptr(saved_rdi, rdi);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2389 __ movptr(saved_rbx, rbx);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2390 } else {
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2391 // restoring
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2392 __ movptr(rsi, saved_rsi);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2393 __ movptr(rdi, saved_rdi);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2394 __ movptr(rbx, saved_rbx);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2395 }
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2396 }
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2397
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2398 // Arguments:
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2399 //
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2400 // Inputs:
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2401 // c_rarg0 - source byte array address
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2402 // c_rarg1 - destination byte array address
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2403 // c_rarg2 - K (key) in little endian int array
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2404 // c_rarg3 - r vector byte array address
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2405 // c_rarg4 - input length
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2406 //
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2407 address generate_cipherBlockChaining_encryptAESCrypt() {
7427
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2408 assert(UseAES, "need AES instructions and misaligned SSE support");
6894
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2409 __ align(CodeEntryAlignment);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2410 StubCodeMark mark(this, "StubRoutines", "cipherBlockChaining_encryptAESCrypt");
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2411 address start = __ pc();
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2412
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2413 Label L_exit, L_key_192_256, L_key_256, L_loopTop_128, L_loopTop_192, L_loopTop_256;
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2414 const Register from = rsi; // source array address
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2415 const Register to = rdx; // destination array address
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2416 const Register key = rcx; // key array address
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2417 const Register rvec = rdi; // r byte array initialized from initvector array address
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2418 // and left with the results of the last encryption block
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2419 const Register len_reg = rbx; // src len (must be multiple of blocksize 16)
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2420 const Register pos = rax;
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2421
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2422 // xmm register assignments for the loops below
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2423 const XMMRegister xmm_result = xmm0;
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2424 const XMMRegister xmm_temp = xmm1;
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2425 // first 6 keys preloaded into xmm2-xmm7
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2426 const int XMM_REG_NUM_KEY_FIRST = 2;
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2427 const int XMM_REG_NUM_KEY_LAST = 7;
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2428 const XMMRegister xmm_key0 = as_XMMRegister(XMM_REG_NUM_KEY_FIRST);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2429
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2430 __ enter(); // required for proper stackwalking of RuntimeStub frame
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2431 handleSOERegisters(true /*saving*/);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2432
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2433 // load registers from incoming parameters
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2434 const Address from_param(rbp, 8+0);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2435 const Address to_param (rbp, 8+4);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2436 const Address key_param (rbp, 8+8);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2437 const Address rvec_param (rbp, 8+12);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2438 const Address len_param (rbp, 8+16);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2439 __ movptr(from , from_param);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2440 __ movptr(to , to_param);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2441 __ movptr(key , key_param);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2442 __ movptr(rvec , rvec_param);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2443 __ movptr(len_reg , len_param);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2444
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2445 const XMMRegister xmm_key_shuf_mask = xmm_temp; // used temporarily to swap key bytes up front
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2446 __ movdqu(xmm_key_shuf_mask, ExternalAddress(StubRoutines::x86::key_shuffle_mask_addr()));
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2447 // load up xmm regs 2 thru 7 with keys 0-5
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2448 for (int rnum = XMM_REG_NUM_KEY_FIRST, offset = 0x00; rnum <= XMM_REG_NUM_KEY_LAST; rnum++) {
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2449 load_key(as_XMMRegister(rnum), key, offset, xmm_key_shuf_mask);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2450 offset += 0x10;
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2451 }
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2452
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2453 __ movdqu(xmm_result, Address(rvec, 0x00)); // initialize xmm_result with r vec
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2454
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2455 // now split to different paths depending on the keylen (len in ints of AESCrypt.KLE array (52=192, or 60=256))
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2456 __ movl(rax, Address(key, arrayOopDesc::length_offset_in_bytes() - arrayOopDesc::base_offset_in_bytes(T_INT)));
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2457 __ cmpl(rax, 44);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2458 __ jcc(Assembler::notEqual, L_key_192_256);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2459
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2460 // 128 bit code follows here
7427
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2461 __ movl(pos, 0);
6894
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2462 __ align(OptoLoopAlignment);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2463 __ BIND(L_loopTop_128);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2464 __ movdqu(xmm_temp, Address(from, pos, Address::times_1, 0)); // get next 16 bytes of input
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2465 __ pxor (xmm_result, xmm_temp); // xor with the current r vector
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2466
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2467 __ pxor (xmm_result, xmm_key0); // do the aes rounds
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2468 for (int rnum = XMM_REG_NUM_KEY_FIRST + 1; rnum <= XMM_REG_NUM_KEY_LAST; rnum++) {
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2469 __ aesenc(xmm_result, as_XMMRegister(rnum));
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2470 }
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2471 for (int key_offset = 0x60; key_offset <= 0x90; key_offset += 0x10) {
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2472 aes_enc_key(xmm_result, xmm_temp, key, key_offset);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2473 }
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2474 load_key(xmm_temp, key, 0xa0);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2475 __ aesenclast(xmm_result, xmm_temp);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2476
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2477 __ movdqu(Address(to, pos, Address::times_1, 0), xmm_result); // store into the next 16 bytes of output
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2478 // no need to store r to memory until we exit
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2479 __ addptr(pos, AESBlockSize);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2480 __ subptr(len_reg, AESBlockSize);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2481 __ jcc(Assembler::notEqual, L_loopTop_128);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2482
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2483 __ BIND(L_exit);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2484 __ movdqu(Address(rvec, 0), xmm_result); // final value of r stored in rvec of CipherBlockChaining object
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2485
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2486 handleSOERegisters(false /*restoring*/);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2487 __ movl(rax, 0); // return 0 (why?)
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2488 __ leave(); // required for proper stackwalking of RuntimeStub frame
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2489 __ ret(0);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2490
7427
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2491 __ BIND(L_key_192_256);
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2492 // here rax = len in ints of AESCrypt.KLE array (52=192, or 60=256)
6894
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2493 __ cmpl(rax, 52);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2494 __ jcc(Assembler::notEqual, L_key_256);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2495
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2496 // 192-bit code follows here (could be changed to use more xmm registers)
7427
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2497 __ movl(pos, 0);
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2498 __ align(OptoLoopAlignment);
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2499 __ BIND(L_loopTop_192);
6894
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2500 __ movdqu(xmm_temp, Address(from, pos, Address::times_1, 0)); // get next 16 bytes of input
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2501 __ pxor (xmm_result, xmm_temp); // xor with the current r vector
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2502
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2503 __ pxor (xmm_result, xmm_key0); // do the aes rounds
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2504 for (int rnum = XMM_REG_NUM_KEY_FIRST + 1; rnum <= XMM_REG_NUM_KEY_LAST; rnum++) {
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2505 __ aesenc(xmm_result, as_XMMRegister(rnum));
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2506 }
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2507 for (int key_offset = 0x60; key_offset <= 0xb0; key_offset += 0x10) {
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2508 aes_enc_key(xmm_result, xmm_temp, key, key_offset);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2509 }
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2510 load_key(xmm_temp, key, 0xc0);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2511 __ aesenclast(xmm_result, xmm_temp);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2512
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2513 __ movdqu(Address(to, pos, Address::times_1, 0), xmm_result); // store into the next 16 bytes of output
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2514 // no need to store r to memory until we exit
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2515 __ addptr(pos, AESBlockSize);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2516 __ subptr(len_reg, AESBlockSize);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2517 __ jcc(Assembler::notEqual, L_loopTop_192);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2518 __ jmp(L_exit);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2519
7427
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2520 __ BIND(L_key_256);
6894
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2521 // 256-bit code follows here (could be changed to use more xmm registers)
7427
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2522 __ movl(pos, 0);
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2523 __ align(OptoLoopAlignment);
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2524 __ BIND(L_loopTop_256);
6894
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2525 __ movdqu(xmm_temp, Address(from, pos, Address::times_1, 0)); // get next 16 bytes of input
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2526 __ pxor (xmm_result, xmm_temp); // xor with the current r vector
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2527
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2528 __ pxor (xmm_result, xmm_key0); // do the aes rounds
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2529 for (int rnum = XMM_REG_NUM_KEY_FIRST + 1; rnum <= XMM_REG_NUM_KEY_LAST; rnum++) {
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2530 __ aesenc(xmm_result, as_XMMRegister(rnum));
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2531 }
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2532 for (int key_offset = 0x60; key_offset <= 0xd0; key_offset += 0x10) {
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2533 aes_enc_key(xmm_result, xmm_temp, key, key_offset);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2534 }
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2535 load_key(xmm_temp, key, 0xe0);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2536 __ aesenclast(xmm_result, xmm_temp);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2537
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2538 __ movdqu(Address(to, pos, Address::times_1, 0), xmm_result); // store into the next 16 bytes of output
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2539 // no need to store r to memory until we exit
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2540 __ addptr(pos, AESBlockSize);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2541 __ subptr(len_reg, AESBlockSize);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2542 __ jcc(Assembler::notEqual, L_loopTop_256);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2543 __ jmp(L_exit);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2544
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2545 return start;
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2546 }
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2547
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2548
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2549 // CBC AES Decryption.
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2550 // In 32-bit stub, because of lack of registers we do not try to parallelize 4 blocks at a time.
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2551 //
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2552 // Arguments:
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2553 //
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2554 // Inputs:
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2555 // c_rarg0 - source byte array address
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2556 // c_rarg1 - destination byte array address
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2557 // c_rarg2 - K (key) in little endian int array
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2558 // c_rarg3 - r vector byte array address
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2559 // c_rarg4 - input length
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2560 //
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2561
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2562 address generate_cipherBlockChaining_decryptAESCrypt() {
7427
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2563 assert(UseAES, "need AES instructions and misaligned SSE support");
6894
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2564 __ align(CodeEntryAlignment);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2565 StubCodeMark mark(this, "StubRoutines", "cipherBlockChaining_decryptAESCrypt");
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2566 address start = __ pc();
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2567
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2568 Label L_exit, L_key_192_256, L_key_256;
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2569 Label L_singleBlock_loopTop_128;
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2570 Label L_singleBlock_loopTop_192, L_singleBlock_loopTop_256;
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2571 const Register from = rsi; // source array address
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2572 const Register to = rdx; // destination array address
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2573 const Register key = rcx; // key array address
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2574 const Register rvec = rdi; // r byte array initialized from initvector array address
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2575 // and left with the results of the last encryption block
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2576 const Register len_reg = rbx; // src len (must be multiple of blocksize 16)
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2577 const Register pos = rax;
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2578
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2579 // xmm register assignments for the loops below
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2580 const XMMRegister xmm_result = xmm0;
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2581 const XMMRegister xmm_temp = xmm1;
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2582 // first 6 keys preloaded into xmm2-xmm7
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2583 const int XMM_REG_NUM_KEY_FIRST = 2;
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2584 const int XMM_REG_NUM_KEY_LAST = 7;
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2585 const int FIRST_NON_REG_KEY_offset = 0x70;
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2586 const XMMRegister xmm_key_first = as_XMMRegister(XMM_REG_NUM_KEY_FIRST);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2587
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2588 __ enter(); // required for proper stackwalking of RuntimeStub frame
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2589 handleSOERegisters(true /*saving*/);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2590
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2591 // load registers from incoming parameters
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2592 const Address from_param(rbp, 8+0);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2593 const Address to_param (rbp, 8+4);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2594 const Address key_param (rbp, 8+8);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2595 const Address rvec_param (rbp, 8+12);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2596 const Address len_param (rbp, 8+16);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2597 __ movptr(from , from_param);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2598 __ movptr(to , to_param);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2599 __ movptr(key , key_param);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2600 __ movptr(rvec , rvec_param);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2601 __ movptr(len_reg , len_param);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2602
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2603 // the java expanded key ordering is rotated one position from what we want
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2604 // so we start from 0x10 here and hit 0x00 last
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2605 const XMMRegister xmm_key_shuf_mask = xmm1; // used temporarily to swap key bytes up front
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2606 __ movdqu(xmm_key_shuf_mask, ExternalAddress(StubRoutines::x86::key_shuffle_mask_addr()));
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2607 // load up xmm regs 2 thru 6 with first 5 keys
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2608 for (int rnum = XMM_REG_NUM_KEY_FIRST, offset = 0x10; rnum <= XMM_REG_NUM_KEY_LAST; rnum++) {
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2609 load_key(as_XMMRegister(rnum), key, offset, xmm_key_shuf_mask);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2610 offset += 0x10;
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2611 }
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2612
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2613 // inside here, use the rvec register to point to previous block cipher
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2614 // with which we xor at the end of each newly decrypted block
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2615 const Register prev_block_cipher_ptr = rvec;
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2616
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2617 // now split to different paths depending on the keylen (len in ints of AESCrypt.KLE array (52=192, or 60=256))
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2618 __ movl(rax, Address(key, arrayOopDesc::length_offset_in_bytes() - arrayOopDesc::base_offset_in_bytes(T_INT)));
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2619 __ cmpl(rax, 44);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2620 __ jcc(Assembler::notEqual, L_key_192_256);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2621
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2622
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2623 // 128-bit code follows here, parallelized
7427
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2624 __ movl(pos, 0);
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2625 __ align(OptoLoopAlignment);
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2626 __ BIND(L_singleBlock_loopTop_128);
6894
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2627 __ cmpptr(len_reg, 0); // any blocks left??
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2628 __ jcc(Assembler::equal, L_exit);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2629 __ movdqu(xmm_result, Address(from, pos, Address::times_1, 0)); // get next 16 bytes of cipher input
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2630 __ pxor (xmm_result, xmm_key_first); // do the aes dec rounds
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2631 for (int rnum = XMM_REG_NUM_KEY_FIRST + 1; rnum <= XMM_REG_NUM_KEY_LAST; rnum++) {
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2632 __ aesdec(xmm_result, as_XMMRegister(rnum));
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2633 }
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2634 for (int key_offset = FIRST_NON_REG_KEY_offset; key_offset <= 0xa0; key_offset += 0x10) { // 128-bit runs up to key offset a0
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2635 aes_dec_key(xmm_result, xmm_temp, key, key_offset);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2636 }
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2637 load_key(xmm_temp, key, 0x00); // final key is stored in java expanded array at offset 0
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2638 __ aesdeclast(xmm_result, xmm_temp);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2639 __ movdqu(xmm_temp, Address(prev_block_cipher_ptr, 0x00));
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2640 __ pxor (xmm_result, xmm_temp); // xor with the current r vector
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2641 __ movdqu(Address(to, pos, Address::times_1, 0), xmm_result); // store into the next 16 bytes of output
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2642 // no need to store r to memory until we exit
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2643 __ lea(prev_block_cipher_ptr, Address(from, pos, Address::times_1, 0)); // set up new ptr
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2644 __ addptr(pos, AESBlockSize);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2645 __ subptr(len_reg, AESBlockSize);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2646 __ jmp(L_singleBlock_loopTop_128);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2647
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2648
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2649 __ BIND(L_exit);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2650 __ movdqu(xmm_temp, Address(prev_block_cipher_ptr, 0x00));
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2651 __ movptr(rvec , rvec_param); // restore this since used in loop
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2652 __ movdqu(Address(rvec, 0), xmm_temp); // final value of r stored in rvec of CipherBlockChaining object
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2653 handleSOERegisters(false /*restoring*/);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2654 __ movl(rax, 0); // return 0 (why?)
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2655 __ leave(); // required for proper stackwalking of RuntimeStub frame
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2656 __ ret(0);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2657
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2658
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2659 __ BIND(L_key_192_256);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2660 // here rax = len in ints of AESCrypt.KLE array (52=192, or 60=256)
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2661 __ cmpl(rax, 52);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2662 __ jcc(Assembler::notEqual, L_key_256);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2663
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2664 // 192-bit code follows here (could be optimized to use parallelism)
7427
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2665 __ movl(pos, 0);
6894
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2666 __ align(OptoLoopAlignment);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2667 __ BIND(L_singleBlock_loopTop_192);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2668 __ movdqu(xmm_result, Address(from, pos, Address::times_1, 0)); // get next 16 bytes of cipher input
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2669 __ pxor (xmm_result, xmm_key_first); // do the aes dec rounds
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2670 for (int rnum = XMM_REG_NUM_KEY_FIRST + 1; rnum <= XMM_REG_NUM_KEY_LAST; rnum++) {
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2671 __ aesdec(xmm_result, as_XMMRegister(rnum));
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2672 }
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2673 for (int key_offset = FIRST_NON_REG_KEY_offset; key_offset <= 0xc0; key_offset += 0x10) { // 192-bit runs up to key offset c0
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2674 aes_dec_key(xmm_result, xmm_temp, key, key_offset);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2675 }
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2676 load_key(xmm_temp, key, 0x00); // final key is stored in java expanded array at offset 0
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2677 __ aesdeclast(xmm_result, xmm_temp);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2678 __ movdqu(xmm_temp, Address(prev_block_cipher_ptr, 0x00));
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2679 __ pxor (xmm_result, xmm_temp); // xor with the current r vector
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2680 __ movdqu(Address(to, pos, Address::times_1, 0), xmm_result); // store into the next 16 bytes of output
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2681 // no need to store r to memory until we exit
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2682 __ lea(prev_block_cipher_ptr, Address(from, pos, Address::times_1, 0)); // set up new ptr
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2683 __ addptr(pos, AESBlockSize);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2684 __ subptr(len_reg, AESBlockSize);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2685 __ jcc(Assembler::notEqual,L_singleBlock_loopTop_192);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2686 __ jmp(L_exit);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2687
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2688 __ BIND(L_key_256);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2689 // 256-bit code follows here (could be optimized to use parallelism)
7427
2c7f594145dc 8004835: Improve AES intrinsics on x86
kvn
parents: 7206
diff changeset
2690 __ movl(pos, 0);
6894
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2691 __ align(OptoLoopAlignment);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2692 __ BIND(L_singleBlock_loopTop_256);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2693 __ movdqu(xmm_result, Address(from, pos, Address::times_1, 0)); // get next 16 bytes of cipher input
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2694 __ pxor (xmm_result, xmm_key_first); // do the aes dec rounds
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2695 for (int rnum = XMM_REG_NUM_KEY_FIRST + 1; rnum <= XMM_REG_NUM_KEY_LAST; rnum++) {
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2696 __ aesdec(xmm_result, as_XMMRegister(rnum));
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2697 }
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2698 for (int key_offset = FIRST_NON_REG_KEY_offset; key_offset <= 0xe0; key_offset += 0x10) { // 256-bit runs up to key offset e0
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2699 aes_dec_key(xmm_result, xmm_temp, key, key_offset);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2700 }
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2701 load_key(xmm_temp, key, 0x00); // final key is stored in java expanded array at offset 0
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2702 __ aesdeclast(xmm_result, xmm_temp);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2703 __ movdqu(xmm_temp, Address(prev_block_cipher_ptr, 0x00));
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2704 __ pxor (xmm_result, xmm_temp); // xor with the current r vector
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2705 __ movdqu(Address(to, pos, Address::times_1, 0), xmm_result); // store into the next 16 bytes of output
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2706 // no need to store r to memory until we exit
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2707 __ lea(prev_block_cipher_ptr, Address(from, pos, Address::times_1, 0)); // set up new ptr
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2708 __ addptr(pos, AESBlockSize);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2709 __ subptr(len_reg, AESBlockSize);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2710 __ jcc(Assembler::notEqual,L_singleBlock_loopTop_256);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2711 __ jmp(L_exit);
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2712
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2713 return start;
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2714 }
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2715
11080
b800986664f4 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 10973
diff changeset
2716 /**
b800986664f4 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 10973
diff changeset
2717 * Arguments:
b800986664f4 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 10973
diff changeset
2718 *
b800986664f4 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 10973
diff changeset
2719 * Inputs:
b800986664f4 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 10973
diff changeset
2720 * rsp(4) - int crc
b800986664f4 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 10973
diff changeset
2721 * rsp(8) - byte* buf
b800986664f4 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 10973
diff changeset
2722 * rsp(12) - int length
b800986664f4 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 10973
diff changeset
2723 *
b800986664f4 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 10973
diff changeset
2724 * Ouput:
b800986664f4 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 10973
diff changeset
2725 * rax - int crc result
b800986664f4 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 10973
diff changeset
2726 */
b800986664f4 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 10973
diff changeset
2727 address generate_updateBytesCRC32() {
b800986664f4 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 10973
diff changeset
2728 assert(UseCRC32Intrinsics, "need AVX and CLMUL instructions");
b800986664f4 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 10973
diff changeset
2729
b800986664f4 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 10973
diff changeset
2730 __ align(CodeEntryAlignment);
b800986664f4 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 10973
diff changeset
2731 StubCodeMark mark(this, "StubRoutines", "updateBytesCRC32");
b800986664f4 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 10973
diff changeset
2732
b800986664f4 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 10973
diff changeset
2733 address start = __ pc();
b800986664f4 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 10973
diff changeset
2734
b800986664f4 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 10973
diff changeset
2735 const Register crc = rdx; // crc
b800986664f4 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 10973
diff changeset
2736 const Register buf = rsi; // source java byte array address
b800986664f4 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 10973
diff changeset
2737 const Register len = rcx; // length
b800986664f4 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 10973
diff changeset
2738 const Register table = rdi; // crc_table address (reuse register)
b800986664f4 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 10973
diff changeset
2739 const Register tmp = rbx;
b800986664f4 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 10973
diff changeset
2740 assert_different_registers(crc, buf, len, table, tmp, rax);
b800986664f4 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 10973
diff changeset
2741
b800986664f4 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 10973
diff changeset
2742 BLOCK_COMMENT("Entry:");
b800986664f4 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 10973
diff changeset
2743 __ enter(); // required for proper stackwalking of RuntimeStub frame
b800986664f4 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 10973
diff changeset
2744 __ push(rsi);
b800986664f4 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 10973
diff changeset
2745 __ push(rdi);
b800986664f4 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 10973
diff changeset
2746 __ push(rbx);
b800986664f4 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 10973
diff changeset
2747
b800986664f4 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 10973
diff changeset
2748 Address crc_arg(rbp, 8 + 0);
b800986664f4 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 10973
diff changeset
2749 Address buf_arg(rbp, 8 + 4);
b800986664f4 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 10973
diff changeset
2750 Address len_arg(rbp, 8 + 8);
b800986664f4 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 10973
diff changeset
2751
b800986664f4 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 10973
diff changeset
2752 // Load up:
b800986664f4 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 10973
diff changeset
2753 __ movl(crc, crc_arg);
b800986664f4 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 10973
diff changeset
2754 __ movptr(buf, buf_arg);
b800986664f4 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 10973
diff changeset
2755 __ movl(len, len_arg);
b800986664f4 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 10973
diff changeset
2756
b800986664f4 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 10973
diff changeset
2757 __ kernel_crc32(crc, buf, len, table, tmp);
b800986664f4 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 10973
diff changeset
2758
b800986664f4 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 10973
diff changeset
2759 __ movl(rax, crc);
b800986664f4 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 10973
diff changeset
2760 __ pop(rbx);
b800986664f4 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 10973
diff changeset
2761 __ pop(rdi);
b800986664f4 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 10973
diff changeset
2762 __ pop(rsi);
b800986664f4 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 10973
diff changeset
2763 __ leave(); // required for proper stackwalking of RuntimeStub frame
b800986664f4 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 10973
diff changeset
2764 __ ret(0);
b800986664f4 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 10973
diff changeset
2765
b800986664f4 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 10973
diff changeset
2766 return start;
b800986664f4 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 10973
diff changeset
2767 }
b800986664f4 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 10973
diff changeset
2768
6894
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2769
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2770 public:
a61af66fc99e Initial load
duke
parents:
diff changeset
2771 // Information about frame layout at time of blocking runtime call.
a61af66fc99e Initial load
duke
parents:
diff changeset
2772 // Note that we only have to preserve callee-saved registers since
a61af66fc99e Initial load
duke
parents:
diff changeset
2773 // the compilers are responsible for supplying a continuation point
a61af66fc99e Initial load
duke
parents:
diff changeset
2774 // if they expect all registers to be preserved.
a61af66fc99e Initial load
duke
parents:
diff changeset
2775 enum layout {
a61af66fc99e Initial load
duke
parents:
diff changeset
2776 thread_off, // last_java_sp
3781
d83ac25d0304 7055355: JSR 292: crash while throwing WrongMethodTypeException
never
parents: 2324
diff changeset
2777 arg1_off,
d83ac25d0304 7055355: JSR 292: crash while throwing WrongMethodTypeException
never
parents: 2324
diff changeset
2778 arg2_off,
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2779 rbp_off, // callee saved register
a61af66fc99e Initial load
duke
parents:
diff changeset
2780 ret_pc,
a61af66fc99e Initial load
duke
parents:
diff changeset
2781 framesize
a61af66fc99e Initial load
duke
parents:
diff changeset
2782 };
a61af66fc99e Initial load
duke
parents:
diff changeset
2783
a61af66fc99e Initial load
duke
parents:
diff changeset
2784 private:
a61af66fc99e Initial load
duke
parents:
diff changeset
2785
a61af66fc99e Initial load
duke
parents:
diff changeset
2786 #undef __
a61af66fc99e Initial load
duke
parents:
diff changeset
2787 #define __ masm->
a61af66fc99e Initial load
duke
parents:
diff changeset
2788
a61af66fc99e Initial load
duke
parents:
diff changeset
2789 //------------------------------------------------------------------------------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
2790 // Continuation point for throwing of implicit exceptions that are not handled in
a61af66fc99e Initial load
duke
parents:
diff changeset
2791 // the current activation. Fabricates an exception oop and initiates normal
a61af66fc99e Initial load
duke
parents:
diff changeset
2792 // exception dispatching in this frame.
a61af66fc99e Initial load
duke
parents:
diff changeset
2793 //
a61af66fc99e Initial load
duke
parents:
diff changeset
2794 // Previously the compiler (c2) allowed for callee save registers on Java calls.
a61af66fc99e Initial load
duke
parents:
diff changeset
2795 // This is no longer true after adapter frames were removed but could possibly
a61af66fc99e Initial load
duke
parents:
diff changeset
2796 // be brought back in the future if the interpreter code was reworked and it
a61af66fc99e Initial load
duke
parents:
diff changeset
2797 // was deemed worthwhile. The comment below was left to describe what must
a61af66fc99e Initial load
duke
parents:
diff changeset
2798 // happen here if callee saves were resurrected. As it stands now this stub
a61af66fc99e Initial load
duke
parents:
diff changeset
2799 // could actually be a vanilla BufferBlob and have now oopMap at all.
a61af66fc99e Initial load
duke
parents:
diff changeset
2800 // Since it doesn't make much difference we've chosen to leave it the
a61af66fc99e Initial load
duke
parents:
diff changeset
2801 // way it was in the callee save days and keep the comment.
a61af66fc99e Initial load
duke
parents:
diff changeset
2802
a61af66fc99e Initial load
duke
parents:
diff changeset
2803 // If we need to preserve callee-saved values we need a callee-saved oop map and
a61af66fc99e Initial load
duke
parents:
diff changeset
2804 // therefore have to make these stubs into RuntimeStubs rather than BufferBlobs.
a61af66fc99e Initial load
duke
parents:
diff changeset
2805 // If the compiler needs all registers to be preserved between the fault
a61af66fc99e Initial load
duke
parents:
diff changeset
2806 // point and the exception handler then it must assume responsibility for that in
a61af66fc99e Initial load
duke
parents:
diff changeset
2807 // AbstractCompiler::continuation_for_implicit_null_exception or
a61af66fc99e Initial load
duke
parents:
diff changeset
2808 // continuation_for_implicit_division_by_zero_exception. All other implicit
a61af66fc99e Initial load
duke
parents:
diff changeset
2809 // exceptions (e.g., NullPointerException or AbstractMethodError on entry) are
a61af66fc99e Initial load
duke
parents:
diff changeset
2810 // either at call sites or otherwise assume that stack unwinding will be initiated,
a61af66fc99e Initial load
duke
parents:
diff changeset
2811 // so caller saved registers were assumed volatile in the compiler.
a61af66fc99e Initial load
duke
parents:
diff changeset
2812 address generate_throw_exception(const char* name, address runtime_entry,
3937
c565834fb592 7088020: SEGV in JNIHandleBlock::release_block
never
parents: 3781
diff changeset
2813 Register arg1 = noreg, Register arg2 = noreg) {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2814
a61af66fc99e Initial load
duke
parents:
diff changeset
2815 int insts_size = 256;
a61af66fc99e Initial load
duke
parents:
diff changeset
2816 int locs_size = 32;
a61af66fc99e Initial load
duke
parents:
diff changeset
2817
a61af66fc99e Initial load
duke
parents:
diff changeset
2818 CodeBuffer code(name, insts_size, locs_size);
a61af66fc99e Initial load
duke
parents:
diff changeset
2819 OopMapSet* oop_maps = new OopMapSet();
a61af66fc99e Initial load
duke
parents:
diff changeset
2820 MacroAssembler* masm = new MacroAssembler(&code);
a61af66fc99e Initial load
duke
parents:
diff changeset
2821
a61af66fc99e Initial load
duke
parents:
diff changeset
2822 address start = __ pc();
a61af66fc99e Initial load
duke
parents:
diff changeset
2823
a61af66fc99e Initial load
duke
parents:
diff changeset
2824 // This is an inlined and slightly modified version of call_VM
a61af66fc99e Initial load
duke
parents:
diff changeset
2825 // which has the ability to fetch the return PC out of
a61af66fc99e Initial load
duke
parents:
diff changeset
2826 // thread-local storage and also sets up last_Java_sp slightly
a61af66fc99e Initial load
duke
parents:
diff changeset
2827 // differently than the real call_VM
a61af66fc99e Initial load
duke
parents:
diff changeset
2828 Register java_thread = rbx;
a61af66fc99e Initial load
duke
parents:
diff changeset
2829 __ get_thread(java_thread);
a61af66fc99e Initial load
duke
parents:
diff changeset
2830
a61af66fc99e Initial load
duke
parents:
diff changeset
2831 __ enter(); // required for proper stackwalking of RuntimeStub frame
a61af66fc99e Initial load
duke
parents:
diff changeset
2832
a61af66fc99e Initial load
duke
parents:
diff changeset
2833 // pc and rbp, already pushed
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
2834 __ subptr(rsp, (framesize-2) * wordSize); // prolog
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2835
a61af66fc99e Initial load
duke
parents:
diff changeset
2836 // Frame is now completed as far as size and linkage.
a61af66fc99e Initial load
duke
parents:
diff changeset
2837
a61af66fc99e Initial load
duke
parents:
diff changeset
2838 int frame_complete = __ pc() - start;
a61af66fc99e Initial load
duke
parents:
diff changeset
2839
a61af66fc99e Initial load
duke
parents:
diff changeset
2840 // push java thread (becomes first argument of C function)
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
2841 __ movptr(Address(rsp, thread_off * wordSize), java_thread);
3781
d83ac25d0304 7055355: JSR 292: crash while throwing WrongMethodTypeException
never
parents: 2324
diff changeset
2842 if (arg1 != noreg) {
d83ac25d0304 7055355: JSR 292: crash while throwing WrongMethodTypeException
never
parents: 2324
diff changeset
2843 __ movptr(Address(rsp, arg1_off * wordSize), arg1);
d83ac25d0304 7055355: JSR 292: crash while throwing WrongMethodTypeException
never
parents: 2324
diff changeset
2844 }
d83ac25d0304 7055355: JSR 292: crash while throwing WrongMethodTypeException
never
parents: 2324
diff changeset
2845 if (arg2 != noreg) {
d83ac25d0304 7055355: JSR 292: crash while throwing WrongMethodTypeException
never
parents: 2324
diff changeset
2846 assert(arg1 != noreg, "missing reg arg");
d83ac25d0304 7055355: JSR 292: crash while throwing WrongMethodTypeException
never
parents: 2324
diff changeset
2847 __ movptr(Address(rsp, arg2_off * wordSize), arg2);
d83ac25d0304 7055355: JSR 292: crash while throwing WrongMethodTypeException
never
parents: 2324
diff changeset
2848 }
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2849
a61af66fc99e Initial load
duke
parents:
diff changeset
2850 // Set up last_Java_sp and last_Java_fp
a61af66fc99e Initial load
duke
parents:
diff changeset
2851 __ set_last_Java_frame(java_thread, rsp, rbp, NULL);
a61af66fc99e Initial load
duke
parents:
diff changeset
2852
a61af66fc99e Initial load
duke
parents:
diff changeset
2853 // Call runtime
a61af66fc99e Initial load
duke
parents:
diff changeset
2854 BLOCK_COMMENT("call runtime_entry");
a61af66fc99e Initial load
duke
parents:
diff changeset
2855 __ call(RuntimeAddress(runtime_entry));
a61af66fc99e Initial load
duke
parents:
diff changeset
2856 // Generate oop map
a61af66fc99e Initial load
duke
parents:
diff changeset
2857 OopMap* map = new OopMap(framesize, 0);
a61af66fc99e Initial load
duke
parents:
diff changeset
2858 oop_maps->add_gc_map(__ pc() - start, map);
a61af66fc99e Initial load
duke
parents:
diff changeset
2859
a61af66fc99e Initial load
duke
parents:
diff changeset
2860 // restore the thread (cannot use the pushed argument since arguments
a61af66fc99e Initial load
duke
parents:
diff changeset
2861 // may be overwritten by C code generated by an optimizing compiler);
a61af66fc99e Initial load
duke
parents:
diff changeset
2862 // however can use the register value directly if it is callee saved.
a61af66fc99e Initial load
duke
parents:
diff changeset
2863 __ get_thread(java_thread);
a61af66fc99e Initial load
duke
parents:
diff changeset
2864
a61af66fc99e Initial load
duke
parents:
diff changeset
2865 __ reset_last_Java_frame(java_thread, true, false);
a61af66fc99e Initial load
duke
parents:
diff changeset
2866
a61af66fc99e Initial load
duke
parents:
diff changeset
2867 __ leave(); // required for proper stackwalking of RuntimeStub frame
a61af66fc99e Initial load
duke
parents:
diff changeset
2868
a61af66fc99e Initial load
duke
parents:
diff changeset
2869 // check for pending exceptions
a61af66fc99e Initial load
duke
parents:
diff changeset
2870 #ifdef ASSERT
a61af66fc99e Initial load
duke
parents:
diff changeset
2871 Label L;
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
2872 __ cmpptr(Address(java_thread, Thread::pending_exception_offset()), (int32_t)NULL_WORD);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2873 __ jcc(Assembler::notEqual, L);
a61af66fc99e Initial load
duke
parents:
diff changeset
2874 __ should_not_reach_here();
a61af66fc99e Initial load
duke
parents:
diff changeset
2875 __ bind(L);
a61af66fc99e Initial load
duke
parents:
diff changeset
2876 #endif /* ASSERT */
a61af66fc99e Initial load
duke
parents:
diff changeset
2877 __ jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
a61af66fc99e Initial load
duke
parents:
diff changeset
2878
a61af66fc99e Initial load
duke
parents:
diff changeset
2879
a61af66fc99e Initial load
duke
parents:
diff changeset
2880 RuntimeStub* stub = RuntimeStub::new_runtime_stub(name, &code, frame_complete, framesize, oop_maps, false);
a61af66fc99e Initial load
duke
parents:
diff changeset
2881 return stub->entry_point();
a61af66fc99e Initial load
duke
parents:
diff changeset
2882 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2883
a61af66fc99e Initial load
duke
parents:
diff changeset
2884
a61af66fc99e Initial load
duke
parents:
diff changeset
2885 void create_control_words() {
a61af66fc99e Initial load
duke
parents:
diff changeset
2886 // Round to nearest, 53-bit mode, exceptions masked
a61af66fc99e Initial load
duke
parents:
diff changeset
2887 StubRoutines::_fpu_cntrl_wrd_std = 0x027F;
a61af66fc99e Initial load
duke
parents:
diff changeset
2888 // Round to zero, 53-bit mode, exception mased
a61af66fc99e Initial load
duke
parents:
diff changeset
2889 StubRoutines::_fpu_cntrl_wrd_trunc = 0x0D7F;
a61af66fc99e Initial load
duke
parents:
diff changeset
2890 // Round to nearest, 24-bit mode, exceptions masked
a61af66fc99e Initial load
duke
parents:
diff changeset
2891 StubRoutines::_fpu_cntrl_wrd_24 = 0x007F;
a61af66fc99e Initial load
duke
parents:
diff changeset
2892 // Round to nearest, 64-bit mode, exceptions masked
a61af66fc99e Initial load
duke
parents:
diff changeset
2893 StubRoutines::_fpu_cntrl_wrd_64 = 0x037F;
a61af66fc99e Initial load
duke
parents:
diff changeset
2894 // Round to nearest, 64-bit mode, exceptions masked
a61af66fc99e Initial load
duke
parents:
diff changeset
2895 StubRoutines::_mxcsr_std = 0x1F80;
a61af66fc99e Initial load
duke
parents:
diff changeset
2896 // Note: the following two constants are 80-bit values
a61af66fc99e Initial load
duke
parents:
diff changeset
2897 // layout is critical for correct loading by FPU.
a61af66fc99e Initial load
duke
parents:
diff changeset
2898 // Bias for strict fp multiply/divide
a61af66fc99e Initial load
duke
parents:
diff changeset
2899 StubRoutines::_fpu_subnormal_bias1[0]= 0x00000000; // 2^(-15360) == 0x03ff 8000 0000 0000 0000
a61af66fc99e Initial load
duke
parents:
diff changeset
2900 StubRoutines::_fpu_subnormal_bias1[1]= 0x80000000;
a61af66fc99e Initial load
duke
parents:
diff changeset
2901 StubRoutines::_fpu_subnormal_bias1[2]= 0x03ff;
a61af66fc99e Initial load
duke
parents:
diff changeset
2902 // Un-Bias for strict fp multiply/divide
a61af66fc99e Initial load
duke
parents:
diff changeset
2903 StubRoutines::_fpu_subnormal_bias2[0]= 0x00000000; // 2^(+15360) == 0x7bff 8000 0000 0000 0000
a61af66fc99e Initial load
duke
parents:
diff changeset
2904 StubRoutines::_fpu_subnormal_bias2[1]= 0x80000000;
a61af66fc99e Initial load
duke
parents:
diff changeset
2905 StubRoutines::_fpu_subnormal_bias2[2]= 0x7bff;
a61af66fc99e Initial load
duke
parents:
diff changeset
2906 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2907
a61af66fc99e Initial load
duke
parents:
diff changeset
2908 //---------------------------------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
2909 // Initialization
a61af66fc99e Initial load
duke
parents:
diff changeset
2910
a61af66fc99e Initial load
duke
parents:
diff changeset
2911 void generate_initial() {
a61af66fc99e Initial load
duke
parents:
diff changeset
2912 // Generates all stubs and initializes the entry points
a61af66fc99e Initial load
duke
parents:
diff changeset
2913
a61af66fc99e Initial load
duke
parents:
diff changeset
2914 //------------------------------------------------------------------------------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
2915 // entry points that exist in all platforms
a61af66fc99e Initial load
duke
parents:
diff changeset
2916 // Note: This is code that could be shared among different platforms - however the benefit seems to be smaller than
a61af66fc99e Initial load
duke
parents:
diff changeset
2917 // the disadvantage of having a much more complicated generator structure. See also comment in stubRoutines.hpp.
a61af66fc99e Initial load
duke
parents:
diff changeset
2918 StubRoutines::_forward_exception_entry = generate_forward_exception();
a61af66fc99e Initial load
duke
parents:
diff changeset
2919
a61af66fc99e Initial load
duke
parents:
diff changeset
2920 StubRoutines::_call_stub_entry =
a61af66fc99e Initial load
duke
parents:
diff changeset
2921 generate_call_stub(StubRoutines::_call_stub_return_address);
a61af66fc99e Initial load
duke
parents:
diff changeset
2922 // is referenced by megamorphic call
a61af66fc99e Initial load
duke
parents:
diff changeset
2923 StubRoutines::_catch_exception_entry = generate_catch_exception();
a61af66fc99e Initial load
duke
parents:
diff changeset
2924
a61af66fc99e Initial load
duke
parents:
diff changeset
2925 // These are currently used by Solaris/Intel
a61af66fc99e Initial load
duke
parents:
diff changeset
2926 StubRoutines::_atomic_xchg_entry = generate_atomic_xchg();
a61af66fc99e Initial load
duke
parents:
diff changeset
2927
a61af66fc99e Initial load
duke
parents:
diff changeset
2928 StubRoutines::_handler_for_unsafe_access_entry =
a61af66fc99e Initial load
duke
parents:
diff changeset
2929 generate_handler_for_unsafe_access();
a61af66fc99e Initial load
duke
parents:
diff changeset
2930
a61af66fc99e Initial load
duke
parents:
diff changeset
2931 // platform dependent
a61af66fc99e Initial load
duke
parents:
diff changeset
2932 create_control_words();
a61af66fc99e Initial load
duke
parents:
diff changeset
2933
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
2934 StubRoutines::x86::_verify_mxcsr_entry = generate_verify_mxcsr();
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 249
diff changeset
2935 StubRoutines::x86::_verify_fpu_cntrl_wrd_entry = generate_verify_fpu_cntrl_wrd();
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2936 StubRoutines::_d2i_wrapper = generate_d2i_wrapper(T_INT,
a61af66fc99e Initial load
duke
parents:
diff changeset
2937 CAST_FROM_FN_PTR(address, SharedRuntime::d2i));
a61af66fc99e Initial load
duke
parents:
diff changeset
2938 StubRoutines::_d2l_wrapper = generate_d2i_wrapper(T_LONG,
a61af66fc99e Initial load
duke
parents:
diff changeset
2939 CAST_FROM_FN_PTR(address, SharedRuntime::d2l));
3781
d83ac25d0304 7055355: JSR 292: crash while throwing WrongMethodTypeException
never
parents: 2324
diff changeset
2940
d83ac25d0304 7055355: JSR 292: crash while throwing WrongMethodTypeException
never
parents: 2324
diff changeset
2941 // Build this early so it's available for the interpreter
4743
dca455dea3a7 7116216: StackOverflow GC crash
bdelsart
parents: 3960
diff changeset
2942 StubRoutines::_throw_StackOverflowError_entry = generate_throw_exception("StackOverflowError throw_exception", CAST_FROM_FN_PTR(address, SharedRuntime::throw_StackOverflowError));
11080
b800986664f4 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 10973
diff changeset
2943
b800986664f4 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 10973
diff changeset
2944 if (UseCRC32Intrinsics) {
b800986664f4 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 10973
diff changeset
2945 // set table address before stub generation which use it
b800986664f4 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 10973
diff changeset
2946 StubRoutines::_crc_table_adr = (address)StubRoutines::x86::_crc_table;
b800986664f4 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 10973
diff changeset
2947 StubRoutines::_updateBytesCRC32 = generate_updateBytesCRC32();
b800986664f4 7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents: 10973
diff changeset
2948 }
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2949 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2950
a61af66fc99e Initial load
duke
parents:
diff changeset
2951
a61af66fc99e Initial load
duke
parents:
diff changeset
2952 void generate_all() {
a61af66fc99e Initial load
duke
parents:
diff changeset
2953 // Generates all stubs and initializes the entry points
a61af66fc99e Initial load
duke
parents:
diff changeset
2954
a61af66fc99e Initial load
duke
parents:
diff changeset
2955 // These entry points require SharedInfo::stack0 to be set up in non-core builds
a61af66fc99e Initial load
duke
parents:
diff changeset
2956 // and need to be relocatable, so they each fabricate a RuntimeStub internally.
3937
c565834fb592 7088020: SEGV in JNIHandleBlock::release_block
never
parents: 3781
diff changeset
2957 StubRoutines::_throw_AbstractMethodError_entry = generate_throw_exception("AbstractMethodError throw_exception", CAST_FROM_FN_PTR(address, SharedRuntime::throw_AbstractMethodError));
c565834fb592 7088020: SEGV in JNIHandleBlock::release_block
never
parents: 3781
diff changeset
2958 StubRoutines::_throw_IncompatibleClassChangeError_entry= generate_throw_exception("IncompatibleClassChangeError throw_exception", CAST_FROM_FN_PTR(address, SharedRuntime::throw_IncompatibleClassChangeError));
c565834fb592 7088020: SEGV in JNIHandleBlock::release_block
never
parents: 3781
diff changeset
2959 StubRoutines::_throw_NullPointerException_at_call_entry= generate_throw_exception("NullPointerException at call throw_exception", CAST_FROM_FN_PTR(address, SharedRuntime::throw_NullPointerException_at_call));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2960
a61af66fc99e Initial load
duke
parents:
diff changeset
2961 //------------------------------------------------------------------------------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
2962 // entry points that are platform specific
a61af66fc99e Initial load
duke
parents:
diff changeset
2963
a61af66fc99e Initial load
duke
parents:
diff changeset
2964 // support for verify_oop (must happen after universe_init)
a61af66fc99e Initial load
duke
parents:
diff changeset
2965 StubRoutines::_verify_oop_subroutine_entry = generate_verify_oop();
a61af66fc99e Initial load
duke
parents:
diff changeset
2966
a61af66fc99e Initial load
duke
parents:
diff changeset
2967 // arraycopy stubs used by compilers
a61af66fc99e Initial load
duke
parents:
diff changeset
2968 generate_arraycopy_stubs();
710
e5b0439ef4ae 6655638: dynamic languages need method handles
jrose
parents: 647
diff changeset
2969
1174
ddb7834449d0 6849984: Value methods for platform dependent math functions constant fold incorrectly
never
parents: 845
diff changeset
2970 generate_math_stubs();
6894
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2971
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2972 // don't bother generating these AES intrinsic stubs unless global flag is set
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2973 if (UseAESIntrinsics) {
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2974 StubRoutines::x86::_key_shuffle_mask_addr = generate_key_shuffle_mask(); // might be needed by the others
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2975
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2976 StubRoutines::_aescrypt_encryptBlock = generate_aescrypt_encryptBlock();
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2977 StubRoutines::_aescrypt_decryptBlock = generate_aescrypt_decryptBlock();
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2978 StubRoutines::_cipherBlockChaining_encryptAESCrypt = generate_cipherBlockChaining_encryptAESCrypt();
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2979 StubRoutines::_cipherBlockChaining_decryptAESCrypt = generate_cipherBlockChaining_decryptAESCrypt();
a3ecd773a7b9 7184394: add intrinsics to use AES instructions
kvn
parents: 6831
diff changeset
2980 }
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2981 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2982
a61af66fc99e Initial load
duke
parents:
diff changeset
2983
a61af66fc99e Initial load
duke
parents:
diff changeset
2984 public:
a61af66fc99e Initial load
duke
parents:
diff changeset
2985 StubGenerator(CodeBuffer* code, bool all) : StubCodeGenerator(code) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2986 if (all) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2987 generate_all();
a61af66fc99e Initial load
duke
parents:
diff changeset
2988 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2989 generate_initial();
a61af66fc99e Initial load
duke
parents:
diff changeset
2990 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2991 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2992 }; // end class declaration
a61af66fc99e Initial load
duke
parents:
diff changeset
2993
a61af66fc99e Initial load
duke
parents:
diff changeset
2994
a61af66fc99e Initial load
duke
parents:
diff changeset
2995 void StubGenerator_generate(CodeBuffer* code, bool all) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2996 StubGenerator g(code, all);
a61af66fc99e Initial load
duke
parents:
diff changeset
2997 }