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annotate src/cpu/ppc/vm/ppc.ad @ 17793:c668f307a4c0
8031319: PPC64: Some fixes in ppc and aix coding.
Reviewed-by: kvn
| author | goetz |
|---|---|
| date | Tue, 07 Jan 2014 17:24:59 +0100 |
| parents | ad3b94907eed |
| children | 0c521b3f32dd |
| rev | line source |
|---|---|
| 14445 | 1 // |
| 2 // Copyright (c) 2011, 2013, Oracle and/or its affiliates. All rights reserved. | |
| 3 // Copyright 2012, 2013 SAP AG. All rights reserved. | |
| 4 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
| 5 // | |
| 6 // This code is free software; you can redistribute it and/or modify it | |
| 7 // under the terms of the GNU General Public License version 2 only, as | |
| 8 // published by the Free Software Foundation. | |
| 9 // | |
| 10 // This code is distributed in the hope that it will be useful, but WITHOUT | |
| 11 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 12 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 13 // version 2 for more details (a copy is included in the LICENSE file that | |
| 14 // accompanied this code). | |
| 15 // | |
| 16 // You should have received a copy of the GNU General Public License version | |
| 17 // 2 along with this work; if not, write to the Free Software Foundation, | |
| 18 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 19 // | |
| 20 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA | |
| 21 // or visit www.oracle.com if you need additional information or have any | |
| 22 // questions. | |
| 23 // | |
| 24 // | |
| 25 | |
| 26 // | |
| 27 // PPC64 Architecture Description File | |
| 28 // | |
| 29 | |
| 30 //----------REGISTER DEFINITION BLOCK------------------------------------------ | |
| 31 // This information is used by the matcher and the register allocator to | |
| 32 // describe individual registers and classes of registers within the target | |
| 33 // architecture. | |
| 34 register %{ | |
| 35 //----------Architecture Description Register Definitions---------------------- | |
| 36 // General Registers | |
| 37 // "reg_def" name (register save type, C convention save type, | |
| 38 // ideal register type, encoding); | |
| 39 // | |
| 40 // Register Save Types: | |
| 41 // | |
| 42 // NS = No-Save: The register allocator assumes that these registers | |
| 43 // can be used without saving upon entry to the method, & | |
| 44 // that they do not need to be saved at call sites. | |
| 45 // | |
| 46 // SOC = Save-On-Call: The register allocator assumes that these registers | |
| 47 // can be used without saving upon entry to the method, | |
| 48 // but that they must be saved at call sites. | |
| 49 // These are called "volatiles" on ppc. | |
| 50 // | |
| 51 // SOE = Save-On-Entry: The register allocator assumes that these registers | |
| 52 // must be saved before using them upon entry to the | |
| 53 // method, but they do not need to be saved at call | |
| 54 // sites. | |
| 55 // These are called "nonvolatiles" on ppc. | |
| 56 // | |
| 57 // AS = Always-Save: The register allocator assumes that these registers | |
| 58 // must be saved before using them upon entry to the | |
| 59 // method, & that they must be saved at call sites. | |
| 60 // | |
| 61 // Ideal Register Type is used to determine how to save & restore a | |
| 62 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get | |
| 63 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI. | |
| 64 // | |
| 65 // The encoding number is the actual bit-pattern placed into the opcodes. | |
| 66 // | |
| 67 // PPC64 register definitions, based on the 64-bit PowerPC ELF ABI | |
| 68 // Supplement Version 1.7 as of 2003-10-29. | |
| 69 // | |
| 70 // For each 64-bit register we must define two registers: the register | |
| 71 // itself, e.g. R3, and a corresponding virtual other (32-bit-)'half', | |
| 72 // e.g. R3_H, which is needed by the allocator, but is not used | |
| 73 // for stores, loads, etc. | |
| 74 | |
| 75 // ---------------------------- | |
| 76 // Integer/Long Registers | |
| 77 // ---------------------------- | |
| 78 | |
| 79 // PPC64 has 32 64-bit integer registers. | |
| 80 | |
| 81 // types: v = volatile, nv = non-volatile, s = system | |
| 82 reg_def R0 ( SOC, SOC, Op_RegI, 0, R0->as_VMReg() ); // v used in prologs | |
| 83 reg_def R0_H ( SOC, SOC, Op_RegI, 99, R0->as_VMReg()->next() ); | |
| 84 reg_def R1 ( NS, NS, Op_RegI, 1, R1->as_VMReg() ); // s SP | |
| 85 reg_def R1_H ( NS, NS, Op_RegI, 99, R1->as_VMReg()->next() ); | |
| 86 reg_def R2 ( SOC, SOC, Op_RegI, 2, R2->as_VMReg() ); // v TOC | |
| 87 reg_def R2_H ( SOC, SOC, Op_RegI, 99, R2->as_VMReg()->next() ); | |
| 88 reg_def R3 ( SOC, SOC, Op_RegI, 3, R3->as_VMReg() ); // v iarg1 & iret | |
| 89 reg_def R3_H ( SOC, SOC, Op_RegI, 99, R3->as_VMReg()->next() ); | |
| 90 reg_def R4 ( SOC, SOC, Op_RegI, 4, R4->as_VMReg() ); // iarg2 | |
| 91 reg_def R4_H ( SOC, SOC, Op_RegI, 99, R4->as_VMReg()->next() ); | |
| 92 reg_def R5 ( SOC, SOC, Op_RegI, 5, R5->as_VMReg() ); // v iarg3 | |
| 93 reg_def R5_H ( SOC, SOC, Op_RegI, 99, R5->as_VMReg()->next() ); | |
| 94 reg_def R6 ( SOC, SOC, Op_RegI, 6, R6->as_VMReg() ); // v iarg4 | |
| 95 reg_def R6_H ( SOC, SOC, Op_RegI, 99, R6->as_VMReg()->next() ); | |
| 96 reg_def R7 ( SOC, SOC, Op_RegI, 7, R7->as_VMReg() ); // v iarg5 | |
| 97 reg_def R7_H ( SOC, SOC, Op_RegI, 99, R7->as_VMReg()->next() ); | |
| 98 reg_def R8 ( SOC, SOC, Op_RegI, 8, R8->as_VMReg() ); // v iarg6 | |
| 99 reg_def R8_H ( SOC, SOC, Op_RegI, 99, R8->as_VMReg()->next() ); | |
| 100 reg_def R9 ( SOC, SOC, Op_RegI, 9, R9->as_VMReg() ); // v iarg7 | |
| 101 reg_def R9_H ( SOC, SOC, Op_RegI, 99, R9->as_VMReg()->next() ); | |
| 102 reg_def R10 ( SOC, SOC, Op_RegI, 10, R10->as_VMReg() ); // v iarg8 | |
| 103 reg_def R10_H( SOC, SOC, Op_RegI, 99, R10->as_VMReg()->next()); | |
| 104 reg_def R11 ( SOC, SOC, Op_RegI, 11, R11->as_VMReg() ); // v ENV / scratch | |
| 105 reg_def R11_H( SOC, SOC, Op_RegI, 99, R11->as_VMReg()->next()); | |
| 106 reg_def R12 ( SOC, SOC, Op_RegI, 12, R12->as_VMReg() ); // v scratch | |
| 107 reg_def R12_H( SOC, SOC, Op_RegI, 99, R12->as_VMReg()->next()); | |
| 108 reg_def R13 ( NS, NS, Op_RegI, 13, R13->as_VMReg() ); // s system thread id | |
| 109 reg_def R13_H( NS, NS, Op_RegI, 99, R13->as_VMReg()->next()); | |
| 110 reg_def R14 ( SOC, SOE, Op_RegI, 14, R14->as_VMReg() ); // nv | |
| 111 reg_def R14_H( SOC, SOE, Op_RegI, 99, R14->as_VMReg()->next()); | |
| 112 reg_def R15 ( SOC, SOE, Op_RegI, 15, R15->as_VMReg() ); // nv | |
| 113 reg_def R15_H( SOC, SOE, Op_RegI, 99, R15->as_VMReg()->next()); | |
| 114 reg_def R16 ( SOC, SOE, Op_RegI, 16, R16->as_VMReg() ); // nv | |
| 115 reg_def R16_H( SOC, SOE, Op_RegI, 99, R16->as_VMReg()->next()); | |
| 116 reg_def R17 ( SOC, SOE, Op_RegI, 17, R17->as_VMReg() ); // nv | |
| 117 reg_def R17_H( SOC, SOE, Op_RegI, 99, R17->as_VMReg()->next()); | |
| 118 reg_def R18 ( SOC, SOE, Op_RegI, 18, R18->as_VMReg() ); // nv | |
| 119 reg_def R18_H( SOC, SOE, Op_RegI, 99, R18->as_VMReg()->next()); | |
| 120 reg_def R19 ( SOC, SOE, Op_RegI, 19, R19->as_VMReg() ); // nv | |
| 121 reg_def R19_H( SOC, SOE, Op_RegI, 99, R19->as_VMReg()->next()); | |
| 122 reg_def R20 ( SOC, SOE, Op_RegI, 20, R20->as_VMReg() ); // nv | |
| 123 reg_def R20_H( SOC, SOE, Op_RegI, 99, R20->as_VMReg()->next()); | |
| 124 reg_def R21 ( SOC, SOE, Op_RegI, 21, R21->as_VMReg() ); // nv | |
| 125 reg_def R21_H( SOC, SOE, Op_RegI, 99, R21->as_VMReg()->next()); | |
| 126 reg_def R22 ( SOC, SOE, Op_RegI, 22, R22->as_VMReg() ); // nv | |
| 127 reg_def R22_H( SOC, SOE, Op_RegI, 99, R22->as_VMReg()->next()); | |
| 128 reg_def R23 ( SOC, SOE, Op_RegI, 23, R23->as_VMReg() ); // nv | |
| 129 reg_def R23_H( SOC, SOE, Op_RegI, 99, R23->as_VMReg()->next()); | |
| 130 reg_def R24 ( SOC, SOE, Op_RegI, 24, R24->as_VMReg() ); // nv | |
| 131 reg_def R24_H( SOC, SOE, Op_RegI, 99, R24->as_VMReg()->next()); | |
| 132 reg_def R25 ( SOC, SOE, Op_RegI, 25, R25->as_VMReg() ); // nv | |
| 133 reg_def R25_H( SOC, SOE, Op_RegI, 99, R25->as_VMReg()->next()); | |
| 134 reg_def R26 ( SOC, SOE, Op_RegI, 26, R26->as_VMReg() ); // nv | |
| 135 reg_def R26_H( SOC, SOE, Op_RegI, 99, R26->as_VMReg()->next()); | |
| 136 reg_def R27 ( SOC, SOE, Op_RegI, 27, R27->as_VMReg() ); // nv | |
| 137 reg_def R27_H( SOC, SOE, Op_RegI, 99, R27->as_VMReg()->next()); | |
| 138 reg_def R28 ( SOC, SOE, Op_RegI, 28, R28->as_VMReg() ); // nv | |
| 139 reg_def R28_H( SOC, SOE, Op_RegI, 99, R28->as_VMReg()->next()); | |
| 140 reg_def R29 ( SOC, SOE, Op_RegI, 29, R29->as_VMReg() ); // nv | |
| 141 reg_def R29_H( SOC, SOE, Op_RegI, 99, R29->as_VMReg()->next()); | |
| 142 reg_def R30 ( SOC, SOE, Op_RegI, 30, R30->as_VMReg() ); // nv | |
| 143 reg_def R30_H( SOC, SOE, Op_RegI, 99, R30->as_VMReg()->next()); | |
| 144 reg_def R31 ( SOC, SOE, Op_RegI, 31, R31->as_VMReg() ); // nv | |
| 145 reg_def R31_H( SOC, SOE, Op_RegI, 99, R31->as_VMReg()->next()); | |
| 146 | |
| 147 | |
| 148 // ---------------------------- | |
| 149 // Float/Double Registers | |
| 150 // ---------------------------- | |
| 151 | |
| 152 // Double Registers | |
| 153 // The rules of ADL require that double registers be defined in pairs. | |
| 154 // Each pair must be two 32-bit values, but not necessarily a pair of | |
| 155 // single float registers. In each pair, ADLC-assigned register numbers | |
| 156 // must be adjacent, with the lower number even. Finally, when the | |
| 157 // CPU stores such a register pair to memory, the word associated with | |
| 158 // the lower ADLC-assigned number must be stored to the lower address. | |
| 159 | |
| 160 // PPC64 has 32 64-bit floating-point registers. Each can store a single | |
| 161 // or double precision floating-point value. | |
| 162 | |
| 163 // types: v = volatile, nv = non-volatile, s = system | |
| 164 reg_def F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg() ); // v scratch | |
| 165 reg_def F0_H ( SOC, SOC, Op_RegF, 99, F0->as_VMReg()->next() ); | |
| 166 reg_def F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg() ); // v farg1 & fret | |
| 167 reg_def F1_H ( SOC, SOC, Op_RegF, 99, F1->as_VMReg()->next() ); | |
| 168 reg_def F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg() ); // v farg2 | |
| 169 reg_def F2_H ( SOC, SOC, Op_RegF, 99, F2->as_VMReg()->next() ); | |
| 170 reg_def F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg() ); // v farg3 | |
| 171 reg_def F3_H ( SOC, SOC, Op_RegF, 99, F3->as_VMReg()->next() ); | |
| 172 reg_def F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg() ); // v farg4 | |
| 173 reg_def F4_H ( SOC, SOC, Op_RegF, 99, F4->as_VMReg()->next() ); | |
| 174 reg_def F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg() ); // v farg5 | |
| 175 reg_def F5_H ( SOC, SOC, Op_RegF, 99, F5->as_VMReg()->next() ); | |
| 176 reg_def F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg() ); // v farg6 | |
| 177 reg_def F6_H ( SOC, SOC, Op_RegF, 99, F6->as_VMReg()->next() ); | |
| 178 reg_def F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg() ); // v farg7 | |
| 179 reg_def F7_H ( SOC, SOC, Op_RegF, 99, F7->as_VMReg()->next() ); | |
| 180 reg_def F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg() ); // v farg8 | |
| 181 reg_def F8_H ( SOC, SOC, Op_RegF, 99, F8->as_VMReg()->next() ); | |
| 182 reg_def F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg() ); // v farg9 | |
| 183 reg_def F9_H ( SOC, SOC, Op_RegF, 99, F9->as_VMReg()->next() ); | |
| 184 reg_def F10 ( SOC, SOC, Op_RegF, 10, F10->as_VMReg() ); // v farg10 | |
| 185 reg_def F10_H( SOC, SOC, Op_RegF, 99, F10->as_VMReg()->next()); | |
| 186 reg_def F11 ( SOC, SOC, Op_RegF, 11, F11->as_VMReg() ); // v farg11 | |
| 187 reg_def F11_H( SOC, SOC, Op_RegF, 99, F11->as_VMReg()->next()); | |
| 188 reg_def F12 ( SOC, SOC, Op_RegF, 12, F12->as_VMReg() ); // v farg12 | |
| 189 reg_def F12_H( SOC, SOC, Op_RegF, 99, F12->as_VMReg()->next()); | |
| 190 reg_def F13 ( SOC, SOC, Op_RegF, 13, F13->as_VMReg() ); // v farg13 | |
| 191 reg_def F13_H( SOC, SOC, Op_RegF, 99, F13->as_VMReg()->next()); | |
| 192 reg_def F14 ( SOC, SOE, Op_RegF, 14, F14->as_VMReg() ); // nv | |
| 193 reg_def F14_H( SOC, SOE, Op_RegF, 99, F14->as_VMReg()->next()); | |
| 194 reg_def F15 ( SOC, SOE, Op_RegF, 15, F15->as_VMReg() ); // nv | |
| 195 reg_def F15_H( SOC, SOE, Op_RegF, 99, F15->as_VMReg()->next()); | |
| 196 reg_def F16 ( SOC, SOE, Op_RegF, 16, F16->as_VMReg() ); // nv | |
| 197 reg_def F16_H( SOC, SOE, Op_RegF, 99, F16->as_VMReg()->next()); | |
| 198 reg_def F17 ( SOC, SOE, Op_RegF, 17, F17->as_VMReg() ); // nv | |
| 199 reg_def F17_H( SOC, SOE, Op_RegF, 99, F17->as_VMReg()->next()); | |
| 200 reg_def F18 ( SOC, SOE, Op_RegF, 18, F18->as_VMReg() ); // nv | |
| 201 reg_def F18_H( SOC, SOE, Op_RegF, 99, F18->as_VMReg()->next()); | |
| 202 reg_def F19 ( SOC, SOE, Op_RegF, 19, F19->as_VMReg() ); // nv | |
| 203 reg_def F19_H( SOC, SOE, Op_RegF, 99, F19->as_VMReg()->next()); | |
| 204 reg_def F20 ( SOC, SOE, Op_RegF, 20, F20->as_VMReg() ); // nv | |
| 205 reg_def F20_H( SOC, SOE, Op_RegF, 99, F20->as_VMReg()->next()); | |
| 206 reg_def F21 ( SOC, SOE, Op_RegF, 21, F21->as_VMReg() ); // nv | |
| 207 reg_def F21_H( SOC, SOE, Op_RegF, 99, F21->as_VMReg()->next()); | |
| 208 reg_def F22 ( SOC, SOE, Op_RegF, 22, F22->as_VMReg() ); // nv | |
| 209 reg_def F22_H( SOC, SOE, Op_RegF, 99, F22->as_VMReg()->next()); | |
| 210 reg_def F23 ( SOC, SOE, Op_RegF, 23, F23->as_VMReg() ); // nv | |
| 211 reg_def F23_H( SOC, SOE, Op_RegF, 99, F23->as_VMReg()->next()); | |
| 212 reg_def F24 ( SOC, SOE, Op_RegF, 24, F24->as_VMReg() ); // nv | |
| 213 reg_def F24_H( SOC, SOE, Op_RegF, 99, F24->as_VMReg()->next()); | |
| 214 reg_def F25 ( SOC, SOE, Op_RegF, 25, F25->as_VMReg() ); // nv | |
| 215 reg_def F25_H( SOC, SOE, Op_RegF, 99, F25->as_VMReg()->next()); | |
| 216 reg_def F26 ( SOC, SOE, Op_RegF, 26, F26->as_VMReg() ); // nv | |
| 217 reg_def F26_H( SOC, SOE, Op_RegF, 99, F26->as_VMReg()->next()); | |
| 218 reg_def F27 ( SOC, SOE, Op_RegF, 27, F27->as_VMReg() ); // nv | |
| 219 reg_def F27_H( SOC, SOE, Op_RegF, 99, F27->as_VMReg()->next()); | |
| 220 reg_def F28 ( SOC, SOE, Op_RegF, 28, F28->as_VMReg() ); // nv | |
| 221 reg_def F28_H( SOC, SOE, Op_RegF, 99, F28->as_VMReg()->next()); | |
| 222 reg_def F29 ( SOC, SOE, Op_RegF, 29, F29->as_VMReg() ); // nv | |
| 223 reg_def F29_H( SOC, SOE, Op_RegF, 99, F29->as_VMReg()->next()); | |
| 224 reg_def F30 ( SOC, SOE, Op_RegF, 30, F30->as_VMReg() ); // nv | |
| 225 reg_def F30_H( SOC, SOE, Op_RegF, 99, F30->as_VMReg()->next()); | |
| 226 reg_def F31 ( SOC, SOE, Op_RegF, 31, F31->as_VMReg() ); // nv | |
| 227 reg_def F31_H( SOC, SOE, Op_RegF, 99, F31->as_VMReg()->next()); | |
| 228 | |
| 229 // ---------------------------- | |
| 230 // Special Registers | |
| 231 // ---------------------------- | |
| 232 | |
| 233 // Condition Codes Flag Registers | |
| 234 | |
| 235 // PPC64 has 8 condition code "registers" which are all contained | |
| 236 // in the CR register. | |
| 237 | |
| 238 // types: v = volatile, nv = non-volatile, s = system | |
| 239 reg_def CCR0(SOC, SOC, Op_RegFlags, 0, CCR0->as_VMReg()); // v | |
| 240 reg_def CCR1(SOC, SOC, Op_RegFlags, 1, CCR1->as_VMReg()); // v | |
| 241 reg_def CCR2(SOC, SOC, Op_RegFlags, 2, CCR2->as_VMReg()); // nv | |
| 242 reg_def CCR3(SOC, SOC, Op_RegFlags, 3, CCR3->as_VMReg()); // nv | |
| 243 reg_def CCR4(SOC, SOC, Op_RegFlags, 4, CCR4->as_VMReg()); // nv | |
| 244 reg_def CCR5(SOC, SOC, Op_RegFlags, 5, CCR5->as_VMReg()); // v | |
| 245 reg_def CCR6(SOC, SOC, Op_RegFlags, 6, CCR6->as_VMReg()); // v | |
| 246 reg_def CCR7(SOC, SOC, Op_RegFlags, 7, CCR7->as_VMReg()); // v | |
| 247 | |
| 248 // Special registers of PPC64 | |
| 249 | |
| 250 reg_def SR_XER( SOC, SOC, Op_RegP, 0, SR_XER->as_VMReg()); // v | |
| 251 reg_def SR_LR( SOC, SOC, Op_RegP, 1, SR_LR->as_VMReg()); // v | |
| 252 reg_def SR_CTR( SOC, SOC, Op_RegP, 2, SR_CTR->as_VMReg()); // v | |
| 253 reg_def SR_VRSAVE( SOC, SOC, Op_RegP, 3, SR_VRSAVE->as_VMReg()); // v | |
| 254 reg_def SR_SPEFSCR(SOC, SOC, Op_RegP, 4, SR_SPEFSCR->as_VMReg()); // v | |
| 255 reg_def SR_PPR( SOC, SOC, Op_RegP, 5, SR_PPR->as_VMReg()); // v | |
| 256 | |
| 257 | |
| 258 // ---------------------------- | |
| 259 // Specify priority of register selection within phases of register | |
| 260 // allocation. Highest priority is first. A useful heuristic is to | |
| 261 // give registers a low priority when they are required by machine | |
| 262 // instructions, like EAX and EDX on I486, and choose no-save registers | |
| 263 // before save-on-call, & save-on-call before save-on-entry. Registers | |
| 264 // which participate in fixed calling sequences should come last. | |
| 265 // Registers which are used as pairs must fall on an even boundary. | |
| 266 | |
| 267 // It's worth about 1% on SPEC geomean to get this right. | |
| 268 | |
| 269 // Chunk0, chunk1, and chunk2 form the MachRegisterNumbers enumeration | |
| 270 // in adGlobals_ppc64.hpp which defines the <register>_num values, e.g. | |
| 271 // R3_num. Therefore, R3_num may not be (and in reality is not) | |
| 272 // the same as R3->encoding()! Furthermore, we cannot make any | |
| 273 // assumptions on ordering, e.g. R3_num may be less than R2_num. | |
| 274 // Additionally, the function | |
| 275 // static enum RC rc_class(OptoReg::Name reg ) | |
| 276 // maps a given <register>_num value to its chunk type (except for flags) | |
| 277 // and its current implementation relies on chunk0 and chunk1 having a | |
| 278 // size of 64 each. | |
| 279 | |
| 280 // If you change this allocation class, please have a look at the | |
| 281 // default values for the parameters RoundRobinIntegerRegIntervalStart | |
| 282 // and RoundRobinFloatRegIntervalStart | |
| 283 | |
| 284 alloc_class chunk0 ( | |
| 285 // Chunk0 contains *all* 64 integer registers halves. | |
| 286 | |
| 287 // "non-volatile" registers | |
| 288 R14, R14_H, | |
| 289 R15, R15_H, | |
| 290 R17, R17_H, | |
| 291 R18, R18_H, | |
| 292 R19, R19_H, | |
| 293 R20, R20_H, | |
| 294 R21, R21_H, | |
| 295 R22, R22_H, | |
| 296 R23, R23_H, | |
| 297 R24, R24_H, | |
| 298 R25, R25_H, | |
| 299 R26, R26_H, | |
| 300 R27, R27_H, | |
| 301 R28, R28_H, | |
| 302 R29, R29_H, | |
| 303 R30, R30_H, | |
| 304 R31, R31_H, | |
| 305 | |
| 306 // scratch/special registers | |
| 307 R11, R11_H, | |
| 308 R12, R12_H, | |
| 309 | |
| 310 // argument registers | |
| 311 R10, R10_H, | |
| 312 R9, R9_H, | |
| 313 R8, R8_H, | |
| 314 R7, R7_H, | |
| 315 R6, R6_H, | |
| 316 R5, R5_H, | |
| 317 R4, R4_H, | |
| 318 R3, R3_H, | |
| 319 | |
| 320 // special registers, not available for allocation | |
| 321 R16, R16_H, // R16_thread | |
| 322 R13, R13_H, // system thread id | |
| 323 R2, R2_H, // may be used for TOC | |
| 324 R1, R1_H, // SP | |
| 325 R0, R0_H // R0 (scratch) | |
| 326 ); | |
| 327 | |
| 328 // If you change this allocation class, please have a look at the | |
| 329 // default values for the parameters RoundRobinIntegerRegIntervalStart | |
| 330 // and RoundRobinFloatRegIntervalStart | |
| 331 | |
| 332 alloc_class chunk1 ( | |
| 333 // Chunk1 contains *all* 64 floating-point registers halves. | |
| 334 | |
| 335 // scratch register | |
| 336 F0, F0_H, | |
| 337 | |
| 338 // argument registers | |
| 339 F13, F13_H, | |
| 340 F12, F12_H, | |
| 341 F11, F11_H, | |
| 342 F10, F10_H, | |
| 343 F9, F9_H, | |
| 344 F8, F8_H, | |
| 345 F7, F7_H, | |
| 346 F6, F6_H, | |
| 347 F5, F5_H, | |
| 348 F4, F4_H, | |
| 349 F3, F3_H, | |
| 350 F2, F2_H, | |
| 351 F1, F1_H, | |
| 352 | |
| 353 // non-volatile registers | |
| 354 F14, F14_H, | |
| 355 F15, F15_H, | |
| 356 F16, F16_H, | |
| 357 F17, F17_H, | |
| 358 F18, F18_H, | |
| 359 F19, F19_H, | |
| 360 F20, F20_H, | |
| 361 F21, F21_H, | |
| 362 F22, F22_H, | |
| 363 F23, F23_H, | |
| 364 F24, F24_H, | |
| 365 F25, F25_H, | |
| 366 F26, F26_H, | |
| 367 F27, F27_H, | |
| 368 F28, F28_H, | |
| 369 F29, F29_H, | |
| 370 F30, F30_H, | |
| 371 F31, F31_H | |
| 372 ); | |
| 373 | |
| 374 alloc_class chunk2 ( | |
| 375 // Chunk2 contains *all* 8 condition code registers. | |
| 376 | |
| 377 CCR0, | |
| 378 CCR1, | |
| 379 CCR2, | |
| 380 CCR3, | |
| 381 CCR4, | |
| 382 CCR5, | |
| 383 CCR6, | |
| 384 CCR7 | |
| 385 ); | |
| 386 | |
| 387 alloc_class chunk3 ( | |
| 388 // special registers | |
| 389 // These registers are not allocated, but used for nodes generated by postalloc expand. | |
| 390 SR_XER, | |
| 391 SR_LR, | |
| 392 SR_CTR, | |
| 393 SR_VRSAVE, | |
| 394 SR_SPEFSCR, | |
| 395 SR_PPR | |
| 396 ); | |
| 397 | |
| 398 //-------Architecture Description Register Classes----------------------- | |
| 399 | |
| 400 // Several register classes are automatically defined based upon | |
| 401 // information in this architecture description. | |
| 402 | |
| 403 // 1) reg_class inline_cache_reg ( as defined in frame section ) | |
| 404 // 2) reg_class compiler_method_oop_reg ( as defined in frame section ) | |
| 405 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section ) | |
| 406 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ ) | |
| 407 // | |
| 408 | |
| 409 // ---------------------------- | |
| 410 // 32 Bit Register Classes | |
| 411 // ---------------------------- | |
| 412 | |
| 413 // We specify registers twice, once as read/write, and once read-only. | |
| 414 // We use the read-only registers for source operands. With this, we | |
| 415 // can include preset read only registers in this class, as a hard-coded | |
| 416 // '0'-register. (We used to simulate this on ppc.) | |
| 417 | |
| 418 // 32 bit registers that can be read and written i.e. these registers | |
| 419 // can be dest (or src) of normal instructions. | |
| 420 reg_class bits32_reg_rw( | |
| 421 /*R0*/ // R0 | |
| 422 /*R1*/ // SP | |
| 423 R2, // TOC | |
| 424 R3, | |
| 425 R4, | |
| 426 R5, | |
| 427 R6, | |
| 428 R7, | |
| 429 R8, | |
| 430 R9, | |
| 431 R10, | |
| 432 R11, | |
| 433 R12, | |
| 434 /*R13*/ // system thread id | |
| 435 R14, | |
| 436 R15, | |
| 437 /*R16*/ // R16_thread | |
| 438 R17, | |
| 439 R18, | |
| 440 R19, | |
| 441 R20, | |
| 442 R21, | |
| 443 R22, | |
| 444 R23, | |
| 445 R24, | |
| 446 R25, | |
| 447 R26, | |
| 448 R27, | |
| 449 R28, | |
| 450 /*R29*/ // global TOC | |
| 451 /*R30*/ // Narrow Oop Base | |
| 452 R31 | |
| 453 ); | |
| 454 | |
| 455 // 32 bit registers that can only be read i.e. these registers can | |
| 456 // only be src of all instructions. | |
| 457 reg_class bits32_reg_ro( | |
| 458 /*R0*/ // R0 | |
| 459 /*R1*/ // SP | |
| 460 R2 // TOC | |
| 461 R3, | |
| 462 R4, | |
| 463 R5, | |
| 464 R6, | |
| 465 R7, | |
| 466 R8, | |
| 467 R9, | |
| 468 R10, | |
| 469 R11, | |
| 470 R12, | |
| 471 /*R13*/ // system thread id | |
| 472 R14, | |
| 473 R15, | |
| 474 /*R16*/ // R16_thread | |
| 475 R17, | |
| 476 R18, | |
| 477 R19, | |
| 478 R20, | |
| 479 R21, | |
| 480 R22, | |
| 481 R23, | |
| 482 R24, | |
| 483 R25, | |
| 484 R26, | |
| 485 R27, | |
| 486 R28, | |
| 487 /*R29*/ | |
| 488 /*R30*/ // Narrow Oop Base | |
| 489 R31 | |
| 490 ); | |
| 491 | |
| 492 // Complement-required-in-pipeline operands for narrow oops. | |
| 493 reg_class bits32_reg_ro_not_complement ( | |
| 494 /*R0*/ // R0 | |
| 495 R1, // SP | |
| 496 R2, // TOC | |
| 497 R3, | |
| 498 R4, | |
| 499 R5, | |
| 500 R6, | |
| 501 R7, | |
| 502 R8, | |
| 503 R9, | |
| 504 R10, | |
| 505 R11, | |
| 506 R12, | |
| 507 /*R13,*/ // system thread id | |
| 508 R14, | |
| 509 R15, | |
| 510 R16, // R16_thread | |
| 511 R17, | |
| 512 R18, | |
| 513 R19, | |
| 514 R20, | |
| 515 R21, | |
| 516 R22, | |
| 517 /*R23, | |
| 518 R24, | |
| 519 R25, | |
| 520 R26, | |
| 521 R27, | |
| 522 R28,*/ | |
| 523 /*R29,*/ // TODO: let allocator handle TOC!! | |
| 524 /*R30,*/ | |
| 525 R31 | |
| 526 ); | |
| 527 | |
| 528 // Complement-required-in-pipeline operands for narrow oops. | |
| 529 // See 64-bit declaration. | |
| 530 reg_class bits32_reg_ro_complement ( | |
| 531 R23, | |
| 532 R24, | |
| 533 R25, | |
| 534 R26, | |
| 535 R27, | |
| 536 R28 | |
| 537 ); | |
| 538 | |
| 539 reg_class rscratch1_bits32_reg(R11); | |
| 540 reg_class rscratch2_bits32_reg(R12); | |
| 541 reg_class rarg1_bits32_reg(R3); | |
| 542 reg_class rarg2_bits32_reg(R4); | |
| 543 reg_class rarg3_bits32_reg(R5); | |
| 544 reg_class rarg4_bits32_reg(R6); | |
| 545 | |
| 546 // ---------------------------- | |
| 547 // 64 Bit Register Classes | |
| 548 // ---------------------------- | |
| 549 // 64-bit build means 64-bit pointers means hi/lo pairs | |
| 550 | |
| 551 reg_class rscratch1_bits64_reg(R11_H, R11); | |
| 552 reg_class rscratch2_bits64_reg(R12_H, R12); | |
| 553 reg_class rarg1_bits64_reg(R3_H, R3); | |
| 554 reg_class rarg2_bits64_reg(R4_H, R4); | |
| 555 reg_class rarg3_bits64_reg(R5_H, R5); | |
| 556 reg_class rarg4_bits64_reg(R6_H, R6); | |
| 557 // Thread register, 'written' by tlsLoadP, see there. | |
| 558 reg_class thread_bits64_reg(R16_H, R16); | |
| 559 | |
| 560 reg_class r19_bits64_reg(R19_H, R19); | |
| 561 | |
| 562 // 64 bit registers that can be read and written i.e. these registers | |
| 563 // can be dest (or src) of normal instructions. | |
| 564 reg_class bits64_reg_rw( | |
| 565 /*R0_H, R0*/ // R0 | |
| 566 /*R1_H, R1*/ // SP | |
| 567 R2_H, R2, // TOC | |
| 568 R3_H, R3, | |
| 569 R4_H, R4, | |
| 570 R5_H, R5, | |
| 571 R6_H, R6, | |
| 572 R7_H, R7, | |
| 573 R8_H, R8, | |
| 574 R9_H, R9, | |
| 575 R10_H, R10, | |
| 576 R11_H, R11, | |
| 577 R12_H, R12, | |
| 578 /*R13_H, R13*/ // system thread id | |
| 579 R14_H, R14, | |
| 580 R15_H, R15, | |
| 581 /*R16_H, R16*/ // R16_thread | |
| 582 R17_H, R17, | |
| 583 R18_H, R18, | |
| 584 R19_H, R19, | |
| 585 R20_H, R20, | |
| 586 R21_H, R21, | |
| 587 R22_H, R22, | |
| 588 R23_H, R23, | |
| 589 R24_H, R24, | |
| 590 R25_H, R25, | |
| 591 R26_H, R26, | |
| 592 R27_H, R27, | |
| 593 R28_H, R28, | |
| 594 /*R29_H, R29*/ | |
| 595 /*R30_H, R30*/ | |
| 596 R31_H, R31 | |
| 597 ); | |
| 598 | |
| 599 // 64 bit registers used excluding r2, r11 and r12 | |
| 600 // Used to hold the TOC to avoid collisions with expanded LeafCall which uses | |
| 601 // r2, r11 and r12 internally. | |
| 602 reg_class bits64_reg_leaf_call( | |
| 603 /*R0_H, R0*/ // R0 | |
| 604 /*R1_H, R1*/ // SP | |
| 605 /*R2_H, R2*/ // TOC | |
| 606 R3_H, R3, | |
| 607 R4_H, R4, | |
| 608 R5_H, R5, | |
| 609 R6_H, R6, | |
| 610 R7_H, R7, | |
| 611 R8_H, R8, | |
| 612 R9_H, R9, | |
| 613 R10_H, R10, | |
| 614 /*R11_H, R11*/ | |
| 615 /*R12_H, R12*/ | |
| 616 /*R13_H, R13*/ // system thread id | |
| 617 R14_H, R14, | |
| 618 R15_H, R15, | |
| 619 /*R16_H, R16*/ // R16_thread | |
| 620 R17_H, R17, | |
| 621 R18_H, R18, | |
| 622 R19_H, R19, | |
| 623 R20_H, R20, | |
| 624 R21_H, R21, | |
| 625 R22_H, R22, | |
| 626 R23_H, R23, | |
| 627 R24_H, R24, | |
| 628 R25_H, R25, | |
| 629 R26_H, R26, | |
| 630 R27_H, R27, | |
| 631 R28_H, R28, | |
| 632 /*R29_H, R29*/ | |
| 633 /*R30_H, R30*/ | |
| 634 R31_H, R31 | |
| 635 ); | |
| 636 | |
| 637 // Used to hold the TOC to avoid collisions with expanded DynamicCall | |
| 638 // which uses r19 as inline cache internally and expanded LeafCall which uses | |
| 639 // r2, r11 and r12 internally. | |
| 640 reg_class bits64_constant_table_base( | |
| 641 /*R0_H, R0*/ // R0 | |
| 642 /*R1_H, R1*/ // SP | |
| 643 /*R2_H, R2*/ // TOC | |
| 644 R3_H, R3, | |
| 645 R4_H, R4, | |
| 646 R5_H, R5, | |
| 647 R6_H, R6, | |
| 648 R7_H, R7, | |
| 649 R8_H, R8, | |
| 650 R9_H, R9, | |
| 651 R10_H, R10, | |
| 652 /*R11_H, R11*/ | |
| 653 /*R12_H, R12*/ | |
| 654 /*R13_H, R13*/ // system thread id | |
| 655 R14_H, R14, | |
| 656 R15_H, R15, | |
| 657 /*R16_H, R16*/ // R16_thread | |
| 658 R17_H, R17, | |
| 659 R18_H, R18, | |
| 660 /*R19_H, R19*/ | |
| 661 R20_H, R20, | |
| 662 R21_H, R21, | |
| 663 R22_H, R22, | |
| 664 R23_H, R23, | |
| 665 R24_H, R24, | |
| 666 R25_H, R25, | |
| 667 R26_H, R26, | |
| 668 R27_H, R27, | |
| 669 R28_H, R28, | |
| 670 /*R29_H, R29*/ | |
| 671 /*R30_H, R30*/ | |
| 672 R31_H, R31 | |
| 673 ); | |
| 674 | |
| 675 // 64 bit registers that can only be read i.e. these registers can | |
| 676 // only be src of all instructions. | |
| 677 reg_class bits64_reg_ro( | |
| 678 /*R0_H, R0*/ // R0 | |
| 679 R1_H, R1, | |
| 680 R2_H, R2, // TOC | |
| 681 R3_H, R3, | |
| 682 R4_H, R4, | |
| 683 R5_H, R5, | |
| 684 R6_H, R6, | |
| 685 R7_H, R7, | |
| 686 R8_H, R8, | |
| 687 R9_H, R9, | |
| 688 R10_H, R10, | |
| 689 R11_H, R11, | |
| 690 R12_H, R12, | |
| 691 /*R13_H, R13*/ // system thread id | |
| 692 R14_H, R14, | |
| 693 R15_H, R15, | |
| 694 R16_H, R16, // R16_thread | |
| 695 R17_H, R17, | |
| 696 R18_H, R18, | |
| 697 R19_H, R19, | |
| 698 R20_H, R20, | |
| 699 R21_H, R21, | |
| 700 R22_H, R22, | |
| 701 R23_H, R23, | |
| 702 R24_H, R24, | |
| 703 R25_H, R25, | |
| 704 R26_H, R26, | |
| 705 R27_H, R27, | |
| 706 R28_H, R28, | |
| 707 /*R29_H, R29*/ // TODO: let allocator handle TOC!! | |
| 708 /*R30_H, R30,*/ | |
| 709 R31_H, R31 | |
| 710 ); | |
| 711 | |
| 712 // Complement-required-in-pipeline operands. | |
| 713 reg_class bits64_reg_ro_not_complement ( | |
| 714 /*R0_H, R0*/ // R0 | |
| 715 R1_H, R1, // SP | |
| 716 R2_H, R2, // TOC | |
| 717 R3_H, R3, | |
| 718 R4_H, R4, | |
| 719 R5_H, R5, | |
| 720 R6_H, R6, | |
| 721 R7_H, R7, | |
| 722 R8_H, R8, | |
| 723 R9_H, R9, | |
| 724 R10_H, R10, | |
| 725 R11_H, R11, | |
| 726 R12_H, R12, | |
| 727 /*R13_H, R13*/ // system thread id | |
| 728 R14_H, R14, | |
| 729 R15_H, R15, | |
| 730 R16_H, R16, // R16_thread | |
| 731 R17_H, R17, | |
| 732 R18_H, R18, | |
| 733 R19_H, R19, | |
| 734 R20_H, R20, | |
| 735 R21_H, R21, | |
| 736 R22_H, R22, | |
| 737 /*R23_H, R23, | |
| 738 R24_H, R24, | |
| 739 R25_H, R25, | |
| 740 R26_H, R26, | |
| 741 R27_H, R27, | |
| 742 R28_H, R28,*/ | |
| 743 /*R29_H, R29*/ // TODO: let allocator handle TOC!! | |
| 744 /*R30_H, R30,*/ | |
| 745 R31_H, R31 | |
| 746 ); | |
| 747 | |
| 748 // Complement-required-in-pipeline operands. | |
| 749 // This register mask is used for the trap instructions that implement | |
| 750 // the null checks on AIX. The trap instruction first computes the | |
| 751 // complement of the value it shall trap on. Because of this, the | |
| 752 // instruction can not be scheduled in the same cycle as an other | |
| 753 // instruction reading the normal value of the same register. So we | |
| 754 // force the value to check into 'bits64_reg_ro_not_complement' | |
| 755 // and then copy it to 'bits64_reg_ro_complement' for the trap. | |
| 756 reg_class bits64_reg_ro_complement ( | |
| 757 R23_H, R23, | |
| 758 R24_H, R24, | |
| 759 R25_H, R25, | |
| 760 R26_H, R26, | |
| 761 R27_H, R27, | |
| 762 R28_H, R28 | |
| 763 ); | |
| 764 | |
| 765 | |
| 766 // ---------------------------- | |
| 767 // Special Class for Condition Code Flags Register | |
| 768 | |
| 769 reg_class int_flags( | |
| 770 /*CCR0*/ // scratch | |
| 771 /*CCR1*/ // scratch | |
| 772 /*CCR2*/ // nv! | |
| 773 /*CCR3*/ // nv! | |
| 774 /*CCR4*/ // nv! | |
| 775 CCR5, | |
| 776 CCR6, | |
| 777 CCR7 | |
| 778 ); | |
| 779 | |
| 780 reg_class int_flags_CR0(CCR0); | |
| 781 reg_class int_flags_CR1(CCR1); | |
| 782 reg_class int_flags_CR6(CCR6); | |
| 783 reg_class ctr_reg(SR_CTR); | |
| 784 | |
| 785 // ---------------------------- | |
| 786 // Float Register Classes | |
| 787 // ---------------------------- | |
| 788 | |
| 789 reg_class flt_reg( | |
| 790 /*F0*/ // scratch | |
| 791 F1, | |
| 792 F2, | |
| 793 F3, | |
| 794 F4, | |
| 795 F5, | |
| 796 F6, | |
| 797 F7, | |
| 798 F8, | |
| 799 F9, | |
| 800 F10, | |
| 801 F11, | |
| 802 F12, | |
| 803 F13, | |
| 804 F14, // nv! | |
| 805 F15, // nv! | |
| 806 F16, // nv! | |
| 807 F17, // nv! | |
| 808 F18, // nv! | |
| 809 F19, // nv! | |
| 810 F20, // nv! | |
| 811 F21, // nv! | |
| 812 F22, // nv! | |
| 813 F23, // nv! | |
| 814 F24, // nv! | |
| 815 F25, // nv! | |
| 816 F26, // nv! | |
| 817 F27, // nv! | |
| 818 F28, // nv! | |
| 819 F29, // nv! | |
| 820 F30, // nv! | |
| 821 F31 // nv! | |
| 822 ); | |
| 823 | |
| 824 // Double precision float registers have virtual `high halves' that | |
| 825 // are needed by the allocator. | |
| 826 reg_class dbl_reg( | |
| 827 /*F0, F0_H*/ // scratch | |
| 828 F1, F1_H, | |
| 829 F2, F2_H, | |
| 830 F3, F3_H, | |
| 831 F4, F4_H, | |
| 832 F5, F5_H, | |
| 833 F6, F6_H, | |
| 834 F7, F7_H, | |
| 835 F8, F8_H, | |
| 836 F9, F9_H, | |
| 837 F10, F10_H, | |
| 838 F11, F11_H, | |
| 839 F12, F12_H, | |
| 840 F13, F13_H, | |
| 841 F14, F14_H, // nv! | |
| 842 F15, F15_H, // nv! | |
| 843 F16, F16_H, // nv! | |
| 844 F17, F17_H, // nv! | |
| 845 F18, F18_H, // nv! | |
| 846 F19, F19_H, // nv! | |
| 847 F20, F20_H, // nv! | |
| 848 F21, F21_H, // nv! | |
| 849 F22, F22_H, // nv! | |
| 850 F23, F23_H, // nv! | |
| 851 F24, F24_H, // nv! | |
| 852 F25, F25_H, // nv! | |
| 853 F26, F26_H, // nv! | |
| 854 F27, F27_H, // nv! | |
| 855 F28, F28_H, // nv! | |
| 856 F29, F29_H, // nv! | |
| 857 F30, F30_H, // nv! | |
| 858 F31, F31_H // nv! | |
| 859 ); | |
| 860 | |
| 861 %} | |
| 862 | |
| 863 //----------DEFINITION BLOCK--------------------------------------------------- | |
| 864 // Define name --> value mappings to inform the ADLC of an integer valued name | |
| 865 // Current support includes integer values in the range [0, 0x7FFFFFFF] | |
| 866 // Format: | |
| 867 // int_def <name> ( <int_value>, <expression>); | |
| 868 // Generated Code in ad_<arch>.hpp | |
| 869 // #define <name> (<expression>) | |
| 870 // // value == <int_value> | |
| 871 // Generated code in ad_<arch>.cpp adlc_verification() | |
| 872 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>"); | |
| 873 // | |
| 874 definitions %{ | |
| 875 // The default cost (of an ALU instruction). | |
| 876 int_def DEFAULT_COST_LOW ( 30, 30); | |
| 877 int_def DEFAULT_COST ( 100, 100); | |
| 878 int_def HUGE_COST (1000000, 1000000); | |
| 879 | |
| 880 // Memory refs | |
| 881 int_def MEMORY_REF_COST_LOW ( 200, DEFAULT_COST * 2); | |
| 882 int_def MEMORY_REF_COST ( 300, DEFAULT_COST * 3); | |
| 883 | |
| 884 // Branches are even more expensive. | |
| 885 int_def BRANCH_COST ( 900, DEFAULT_COST * 9); | |
| 886 int_def CALL_COST ( 1300, DEFAULT_COST * 13); | |
| 887 %} | |
| 888 | |
| 889 | |
| 890 //----------SOURCE BLOCK------------------------------------------------------- | |
| 891 // This is a block of C++ code which provides values, functions, and | |
| 892 // definitions necessary in the rest of the architecture description. | |
| 893 source_hpp %{ | |
| 894 // Returns true if Node n is followed by a MemBar node that | |
| 895 // will do an acquire. If so, this node must not do the acquire | |
| 896 // operation. | |
| 897 bool followed_by_acquire(const Node *n); | |
| 898 %} | |
| 899 | |
| 900 source %{ | |
| 901 | |
| 902 // Optimize load-acquire. | |
| 903 // | |
| 904 // Check if acquire is unnecessary due to following operation that does | |
| 905 // acquire anyways. | |
| 906 // Walk the pattern: | |
| 907 // | |
| 908 // n: Load.acq | |
| 909 // | | |
| 910 // MemBarAcquire | |
| 911 // | | | |
| 912 // Proj(ctrl) Proj(mem) | |
| 913 // | | | |
| 914 // MemBarRelease/Volatile | |
| 915 // | |
| 916 bool followed_by_acquire(const Node *load) { | |
| 917 assert(load->is_Load(), "So far implemented only for loads."); | |
| 918 | |
| 919 // Find MemBarAcquire. | |
| 920 const Node *mba = NULL; | |
| 921 for (DUIterator_Fast imax, i = load->fast_outs(imax); i < imax; i++) { | |
| 922 const Node *out = load->fast_out(i); | |
| 923 if (out->Opcode() == Op_MemBarAcquire) { | |
| 924 if (out->in(0) == load) continue; // Skip control edge, membar should be found via precedence edge. | |
| 925 mba = out; | |
| 926 break; | |
| 927 } | |
| 928 } | |
| 929 if (!mba) return false; | |
| 930 | |
| 931 // Find following MemBar node. | |
| 932 // | |
| 933 // The following node must be reachable by control AND memory | |
| 934 // edge to assure no other operations are in between the two nodes. | |
| 935 // | |
| 936 // So first get the Proj node, mem_proj, to use it to iterate forward. | |
| 937 Node *mem_proj = NULL; | |
| 938 for (DUIterator_Fast imax, i = mba->fast_outs(imax); i < imax; i++) { | |
| 939 mem_proj = mba->fast_out(i); // Throw out-of-bounds if proj not found | |
| 940 assert(mem_proj->is_Proj(), "only projections here"); | |
| 941 ProjNode *proj = mem_proj->as_Proj(); | |
| 942 if (proj->_con == TypeFunc::Memory && | |
| 943 !Compile::current()->node_arena()->contains(mem_proj)) // Unmatched old-space only | |
| 944 break; | |
| 945 } | |
| 946 assert(mem_proj->as_Proj()->_con == TypeFunc::Memory, "Graph broken"); | |
| 947 | |
| 948 // Search MemBar behind Proj. If there are other memory operations | |
| 949 // behind the Proj we lost. | |
| 950 for (DUIterator_Fast jmax, j = mem_proj->fast_outs(jmax); j < jmax; j++) { | |
| 951 Node *x = mem_proj->fast_out(j); | |
| 952 // Proj might have an edge to a store or load node which precedes the membar. | |
| 953 if (x->is_Mem()) return false; | |
| 954 | |
| 955 // On PPC64 release and volatile are implemented by an instruction | |
| 956 // that also has acquire semantics. I.e. there is no need for an | |
| 957 // acquire before these. | |
| 958 int xop = x->Opcode(); | |
| 959 if (xop == Op_MemBarRelease || xop == Op_MemBarVolatile) { | |
| 960 // Make sure we're not missing Call/Phi/MergeMem by checking | |
| 961 // control edges. The control edge must directly lead back | |
| 962 // to the MemBarAcquire | |
| 963 Node *ctrl_proj = x->in(0); | |
| 964 if (ctrl_proj->is_Proj() && ctrl_proj->in(0) == mba) { | |
| 965 return true; | |
| 966 } | |
| 967 } | |
| 968 } | |
| 969 | |
| 970 return false; | |
| 971 } | |
| 972 | |
| 973 #define __ _masm. | |
| 974 | |
| 975 // Tertiary op of a LoadP or StoreP encoding. | |
| 976 #define REGP_OP true | |
| 977 | |
| 978 // **************************************************************************** | |
| 979 | |
| 980 // REQUIRED FUNCTIONALITY | |
| 981 | |
| 982 // !!!!! Special hack to get all type of calls to specify the byte offset | |
| 983 // from the start of the call to the point where the return address | |
| 984 // will point. | |
| 985 | |
| 986 // PPC port: Removed use of lazy constant construct. | |
| 987 | |
| 988 int MachCallStaticJavaNode::ret_addr_offset() { | |
| 989 // It's only a single branch-and-link instruction. | |
| 990 return 4; | |
| 991 } | |
| 992 | |
| 993 int MachCallDynamicJavaNode::ret_addr_offset() { | |
| 994 // Offset is 4 with postalloc expanded calls (bl is one instruction). We use | |
| 995 // postalloc expanded calls if we use inline caches and do not update method data. | |
| 996 if (UseInlineCaches) | |
| 997 return 4; | |
| 998 | |
| 999 int vtable_index = this->_vtable_index; | |
| 1000 if (vtable_index < 0) { | |
| 1001 // Must be invalid_vtable_index, not nonvirtual_vtable_index. | |
| 1002 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value"); | |
| 1003 return 12; | |
| 1004 } else { | |
| 1005 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); | |
| 1006 return 24; | |
| 1007 } | |
| 1008 } | |
| 1009 | |
| 1010 int MachCallRuntimeNode::ret_addr_offset() { | |
| 1011 return 40; | |
| 1012 } | |
| 1013 | |
| 1014 //============================================================================= | |
| 1015 | |
| 1016 // condition code conversions | |
| 1017 | |
| 1018 static int cc_to_boint(int cc) { | |
| 1019 return Assembler::bcondCRbiIs0 | (cc & 8); | |
| 1020 } | |
| 1021 | |
| 1022 static int cc_to_inverse_boint(int cc) { | |
| 1023 return Assembler::bcondCRbiIs0 | (8-(cc & 8)); | |
| 1024 } | |
| 1025 | |
| 1026 static int cc_to_biint(int cc, int flags_reg) { | |
| 1027 return (flags_reg << 2) | (cc & 3); | |
| 1028 } | |
| 1029 | |
| 1030 //============================================================================= | |
| 1031 | |
| 1032 // Compute padding required for nodes which need alignment. The padding | |
| 1033 // is the number of bytes (not instructions) which will be inserted before | |
| 1034 // the instruction. The padding must match the size of a NOP instruction. | |
| 1035 | |
| 1036 int string_indexOf_imm1_charNode::compute_padding(int current_offset) const { | |
| 1037 return (3*4-current_offset)&31; | |
| 1038 } | |
| 1039 | |
| 1040 int string_indexOf_imm1Node::compute_padding(int current_offset) const { | |
| 1041 return (2*4-current_offset)&31; | |
| 1042 } | |
| 1043 | |
| 1044 int string_indexOf_immNode::compute_padding(int current_offset) const { | |
| 1045 return (3*4-current_offset)&31; | |
| 1046 } | |
| 1047 | |
| 1048 int string_indexOfNode::compute_padding(int current_offset) const { | |
| 1049 return (1*4-current_offset)&31; | |
| 1050 } | |
| 1051 | |
| 1052 int string_compareNode::compute_padding(int current_offset) const { | |
| 1053 return (4*4-current_offset)&31; | |
| 1054 } | |
| 1055 | |
| 1056 int string_equals_immNode::compute_padding(int current_offset) const { | |
| 1057 if (opnd_array(3)->constant() < 16) return 0; // Don't insert nops for short version (loop completely unrolled). | |
| 1058 return (2*4-current_offset)&31; | |
| 1059 } | |
| 1060 | |
| 1061 int string_equalsNode::compute_padding(int current_offset) const { | |
| 1062 return (7*4-current_offset)&31; | |
| 1063 } | |
| 1064 | |
| 1065 int inlineCallClearArrayNode::compute_padding(int current_offset) const { | |
| 1066 return (2*4-current_offset)&31; | |
| 1067 } | |
| 1068 | |
| 1069 //============================================================================= | |
| 1070 | |
| 1071 // Indicate if the safepoint node needs the polling page as an input. | |
| 1072 bool SafePointNode::needs_polling_address_input() { | |
| 1073 // The address is loaded from thread by a seperate node. | |
| 1074 return true; | |
| 1075 } | |
| 1076 | |
| 1077 //============================================================================= | |
| 1078 | |
| 1079 // Emit an interrupt that is caught by the debugger (for debugging compiler). | |
| 1080 void emit_break(CodeBuffer &cbuf) { | |
| 1081 MacroAssembler _masm(&cbuf); | |
| 1082 __ illtrap(); | |
| 1083 } | |
| 1084 | |
| 1085 #ifndef PRODUCT | |
| 1086 void MachBreakpointNode::format(PhaseRegAlloc *ra_, outputStream *st) const { | |
| 1087 st->print("BREAKPOINT"); | |
| 1088 } | |
| 1089 #endif | |
| 1090 | |
| 1091 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1092 emit_break(cbuf); | |
| 1093 } | |
| 1094 | |
| 1095 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const { | |
| 1096 return MachNode::size(ra_); | |
| 1097 } | |
| 1098 | |
| 1099 //============================================================================= | |
| 1100 | |
| 1101 void emit_nop(CodeBuffer &cbuf) { | |
| 1102 MacroAssembler _masm(&cbuf); | |
| 1103 __ nop(); | |
| 1104 } | |
| 1105 | |
| 1106 static inline void emit_long(CodeBuffer &cbuf, int value) { | |
| 1107 *((int*)(cbuf.insts_end())) = value; | |
| 1108 cbuf.set_insts_end(cbuf.insts_end() + BytesPerInstWord); | |
| 1109 } | |
| 1110 | |
| 1111 //============================================================================= | |
| 1112 | |
| 1113 // Emit a trampoline stub for a call to a target which is too far away. | |
| 1114 // | |
| 1115 // code sequences: | |
| 1116 // | |
| 1117 // call-site: | |
| 1118 // branch-and-link to <destination> or <trampoline stub> | |
| 1119 // | |
| 1120 // Related trampoline stub for this call-site in the stub section: | |
| 1121 // load the call target from the constant pool | |
| 1122 // branch via CTR (LR/link still points to the call-site above) | |
| 1123 | |
| 1124 const uint trampoline_stub_size = 6 * BytesPerInstWord; | |
| 1125 | |
| 1126 void emit_trampoline_stub(MacroAssembler &_masm, int destination_toc_offset, int insts_call_instruction_offset) { | |
| 1127 // Start the stub. | |
| 1128 address stub = __ start_a_stub(Compile::MAX_stubs_size/2); | |
| 1129 if (stub == NULL) { | |
| 1130 Compile::current()->env()->record_out_of_memory_failure(); | |
| 1131 return; | |
| 1132 } | |
| 1133 | |
| 1134 // For java_to_interp stubs we use R11_scratch1 as scratch register | |
| 1135 // and in call trampoline stubs we use R12_scratch2. This way we | |
| 1136 // can distinguish them (see is_NativeCallTrampolineStub_at()). | |
| 1137 Register reg_scratch = R12_scratch2; | |
| 1138 | |
| 1139 // Create a trampoline stub relocation which relates this trampoline stub | |
| 1140 // with the call instruction at insts_call_instruction_offset in the | |
| 1141 // instructions code-section. | |
| 1142 __ relocate(trampoline_stub_Relocation::spec(__ code()->insts()->start() + insts_call_instruction_offset)); | |
| 1143 const int stub_start_offset = __ offset(); | |
| 1144 | |
| 1145 // Now, create the trampoline stub's code: | |
| 1146 // - load the TOC | |
| 1147 // - load the call target from the constant pool | |
| 1148 // - call | |
| 1149 __ calculate_address_from_global_toc(reg_scratch, __ method_toc()); | |
| 1150 __ ld_largeoffset_unchecked(reg_scratch, destination_toc_offset, reg_scratch, false); | |
| 1151 __ mtctr(reg_scratch); | |
| 1152 __ bctr(); | |
| 1153 | |
| 1154 const address stub_start_addr = __ addr_at(stub_start_offset); | |
| 1155 | |
| 1156 // FIXME: Assert that the trampoline stub can be identified and patched. | |
| 1157 | |
| 1158 // Assert that the encoded destination_toc_offset can be identified and that it is correct. | |
| 1159 assert(destination_toc_offset == NativeCallTrampolineStub_at(stub_start_addr)->destination_toc_offset(), | |
| 1160 "encoded offset into the constant pool must match"); | |
| 1161 // Trampoline_stub_size should be good. | |
| 1162 assert((uint)(__ offset() - stub_start_offset) <= trampoline_stub_size, "should be good size"); | |
| 1163 assert(is_NativeCallTrampolineStub_at(stub_start_addr), "doesn't look like a trampoline"); | |
| 1164 | |
| 1165 // End the stub. | |
| 1166 __ end_a_stub(); | |
| 1167 } | |
| 1168 | |
| 1169 // Size of trampoline stub, this doesn't need to be accurate but it must | |
| 1170 // be larger or equal to the real size of the stub. | |
| 1171 // Used for optimization in Compile::Shorten_branches. | |
| 1172 uint size_call_trampoline() { | |
| 1173 return trampoline_stub_size; | |
| 1174 } | |
| 1175 | |
| 1176 // Number of relocation entries needed by trampoline stub. | |
| 1177 // Used for optimization in Compile::Shorten_branches. | |
| 1178 uint reloc_call_trampoline() { | |
| 1179 return 5; | |
| 1180 } | |
| 1181 | |
| 1182 //============================================================================= | |
| 1183 | |
| 1184 // Emit an inline branch-and-link call and a related trampoline stub. | |
| 1185 // | |
| 1186 // code sequences: | |
| 1187 // | |
| 1188 // call-site: | |
| 1189 // branch-and-link to <destination> or <trampoline stub> | |
| 1190 // | |
| 1191 // Related trampoline stub for this call-site in the stub section: | |
| 1192 // load the call target from the constant pool | |
| 1193 // branch via CTR (LR/link still points to the call-site above) | |
| 1194 // | |
| 1195 | |
| 1196 typedef struct { | |
| 1197 int insts_call_instruction_offset; | |
| 1198 int ret_addr_offset; | |
| 1199 } EmitCallOffsets; | |
| 1200 | |
| 1201 // Emit a branch-and-link instruction that branches to a trampoline. | |
| 1202 // - Remember the offset of the branch-and-link instruction. | |
| 1203 // - Add a relocation at the branch-and-link instruction. | |
| 1204 // - Emit a branch-and-link. | |
| 1205 // - Remember the return pc offset. | |
| 1206 EmitCallOffsets emit_call_with_trampoline_stub(MacroAssembler &_masm, address entry_point, relocInfo::relocType rtype) { | |
| 1207 EmitCallOffsets offsets = { -1, -1 }; | |
| 1208 const int start_offset = __ offset(); | |
| 1209 offsets.insts_call_instruction_offset = __ offset(); | |
| 1210 | |
| 1211 // No entry point given, use the current pc. | |
| 1212 if (entry_point == NULL) entry_point = __ pc(); | |
| 1213 | |
| 1214 if (!Compile::current()->in_scratch_emit_size()) { | |
| 1215 // Put the entry point as a constant into the constant pool. | |
| 1216 const address entry_point_toc_addr = __ address_constant(entry_point, RelocationHolder::none); | |
| 1217 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr); | |
| 1218 | |
| 1219 // Emit the trampoline stub which will be related to the branch-and-link below. | |
| 1220 emit_trampoline_stub(_masm, entry_point_toc_offset, offsets.insts_call_instruction_offset); | |
| 1221 __ relocate(rtype); | |
| 1222 } | |
| 1223 | |
| 1224 // Note: At this point we do not have the address of the trampoline | |
| 1225 // stub, and the entry point might be too far away for bl, so __ pc() | |
| 1226 // serves as dummy and the bl will be patched later. | |
| 1227 __ bl((address) __ pc()); | |
| 1228 | |
| 1229 offsets.ret_addr_offset = __ offset() - start_offset; | |
| 1230 | |
| 1231 return offsets; | |
| 1232 } | |
| 1233 | |
| 1234 //============================================================================= | |
| 1235 | |
| 1236 // Factory for creating loadConL* nodes for large/small constant pool. | |
| 1237 | |
| 1238 static inline jlong replicate_immF(float con) { | |
| 1239 // Replicate float con 2 times and pack into vector. | |
| 1240 int val = *((int*)&con); | |
| 1241 jlong lval = val; | |
| 1242 lval = (lval << 32) | (lval & 0xFFFFFFFFl); | |
| 1243 return lval; | |
| 1244 } | |
| 1245 | |
| 1246 //============================================================================= | |
| 1247 | |
| 1248 const RegMask& MachConstantBaseNode::_out_RegMask = BITS64_CONSTANT_TABLE_BASE_mask(); | |
| 1249 int Compile::ConstantTable::calculate_table_base_offset() const { | |
| 1250 return 0; // absolute addressing, no offset | |
| 1251 } | |
| 1252 | |
| 1253 bool MachConstantBaseNode::requires_postalloc_expand() const { return true; } | |
| 1254 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) { | |
| 1255 Compile *C = ra_->C; | |
| 1256 | |
| 1257 iRegPdstOper *op_dst = new (C) iRegPdstOper(); | |
| 1258 MachNode *m1 = new (C) loadToc_hiNode(); | |
| 1259 MachNode *m2 = new (C) loadToc_loNode(); | |
| 1260 | |
| 1261 m1->add_req(NULL); | |
| 1262 m2->add_req(NULL, m1); | |
| 1263 m1->_opnds[0] = op_dst; | |
| 1264 m2->_opnds[0] = op_dst; | |
| 1265 m2->_opnds[1] = op_dst; | |
| 1266 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); | |
| 1267 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); | |
| 1268 nodes->push(m1); | |
| 1269 nodes->push(m2); | |
| 1270 } | |
| 1271 | |
| 1272 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const { | |
| 1273 // Is postalloc expanded. | |
| 1274 ShouldNotReachHere(); | |
| 1275 } | |
| 1276 | |
| 1277 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const { | |
| 1278 return 0; | |
| 1279 } | |
| 1280 | |
| 1281 #ifndef PRODUCT | |
| 1282 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const { | |
| 1283 st->print("-- \t// MachConstantBaseNode (empty encoding)"); | |
| 1284 } | |
| 1285 #endif | |
| 1286 | |
| 1287 //============================================================================= | |
| 1288 | |
| 1289 #ifndef PRODUCT | |
| 1290 void MachPrologNode::format(PhaseRegAlloc *ra_, outputStream *st) const { | |
| 1291 Compile* C = ra_->C; | |
| 1292 const long framesize = C->frame_slots() << LogBytesPerInt; | |
| 1293 | |
| 1294 st->print("PROLOG\n\t"); | |
| 1295 if (C->need_stack_bang(framesize)) { | |
| 1296 st->print("stack_overflow_check\n\t"); | |
| 1297 } | |
| 1298 | |
| 1299 if (!false /* TODO: PPC port C->is_frameless_method()*/) { | |
| 1300 st->print("save return pc\n\t"); | |
| 1301 st->print("push frame %d\n\t", -framesize); | |
| 1302 } | |
| 1303 } | |
| 1304 #endif | |
| 1305 | |
| 1306 // Macro used instead of the common __ to emulate the pipes of PPC. | |
| 1307 // Instead of e.g. __ ld(...) one hase to write ___(ld) ld(...) This enables the | |
| 1308 // micro scheduler to cope with "hand written" assembler like in the prolog. Though | |
| 1309 // still no scheduling of this code is possible, the micro scheduler is aware of the | |
| 1310 // code and can update its internal data. The following mechanism is used to achieve this: | |
| 1311 // The micro scheduler calls size() of each compound node during scheduling. size() does a | |
| 1312 // dummy emit and only during this dummy emit C->hb_scheduling() is not NULL. | |
| 1313 #if 0 // TODO: PPC port | |
| 1314 #define ___(op) if (UsePower6SchedulerPPC64 && C->hb_scheduling()) \ | |
| 1315 C->hb_scheduling()->_pdScheduling->PdEmulatePipe(ppc64Opcode_##op); \ | |
| 1316 _masm. | |
| 1317 #define ___stop if (UsePower6SchedulerPPC64 && C->hb_scheduling()) \ | |
| 1318 C->hb_scheduling()->_pdScheduling->PdEmulatePipe(archOpcode_none) | |
| 1319 #define ___advance if (UsePower6SchedulerPPC64 && C->hb_scheduling()) \ | |
| 1320 C->hb_scheduling()->_pdScheduling->advance_offset | |
| 1321 #else | |
| 1322 #define ___(op) if (UsePower6SchedulerPPC64) \ | |
| 1323 Unimplemented(); \ | |
| 1324 _masm. | |
| 1325 #define ___stop if (UsePower6SchedulerPPC64) \ | |
| 1326 Unimplemented() | |
| 1327 #define ___advance if (UsePower6SchedulerPPC64) \ | |
| 1328 Unimplemented() | |
| 1329 #endif | |
| 1330 | |
| 1331 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1332 Compile* C = ra_->C; | |
| 1333 MacroAssembler _masm(&cbuf); | |
| 1334 | |
| 1335 const long framesize = ((long)C->frame_slots()) << LogBytesPerInt; | |
| 1336 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment"); | |
| 1337 | |
| 1338 const bool method_is_frameless = false /* TODO: PPC port C->is_frameless_method()*/; | |
| 1339 | |
| 1340 const Register return_pc = R20; // Must match return_addr() in frame section. | |
| 1341 const Register callers_sp = R21; | |
| 1342 const Register push_frame_temp = R22; | |
| 1343 const Register toc_temp = R23; | |
| 1344 assert_different_registers(R11, return_pc, callers_sp, push_frame_temp, toc_temp); | |
| 1345 | |
| 1346 if (method_is_frameless) { | |
| 1347 // Add nop at beginning of all frameless methods to prevent any | |
| 1348 // oop instructions from getting overwritten by make_not_entrant | |
| 1349 // (patching attempt would fail). | |
| 1350 ___(nop) nop(); | |
| 1351 } else { | |
| 1352 // Get return pc. | |
| 1353 ___(mflr) mflr(return_pc); | |
| 1354 } | |
| 1355 | |
| 1356 // Calls to C2R adapters often do not accept exceptional returns. | |
| 1357 // We require that their callers must bang for them. But be | |
| 1358 // careful, because some VM calls (such as call site linkage) can | |
| 1359 // use several kilobytes of stack. But the stack safety zone should | |
| 1360 // account for that. See bugs 4446381, 4468289, 4497237. | |
| 1361 if (C->need_stack_bang(framesize) && UseStackBanging) { | |
| 1362 // Unfortunately we cannot use the function provided in | |
| 1363 // assembler.cpp as we have to emulate the pipes. So I had to | |
| 1364 // insert the code of generate_stack_overflow_check(), see | |
| 1365 // assembler.cpp for some illuminative comments. | |
| 1366 const int page_size = os::vm_page_size(); | |
| 1367 int bang_end = StackShadowPages*page_size; | |
| 1368 | |
| 1369 // This is how far the previous frame's stack banging extended. | |
| 1370 const int bang_end_safe = bang_end; | |
| 1371 | |
| 1372 if (framesize > page_size) { | |
| 1373 bang_end += framesize; | |
| 1374 } | |
| 1375 | |
| 1376 int bang_offset = bang_end_safe; | |
| 1377 | |
| 1378 while (bang_offset <= bang_end) { | |
| 1379 // Need at least one stack bang at end of shadow zone. | |
| 1380 | |
| 1381 // Again I had to copy code, this time from assembler_ppc64.cpp, | |
| 1382 // bang_stack_with_offset - see there for comments. | |
| 1383 | |
| 1384 // Stack grows down, caller passes positive offset. | |
| 1385 assert(bang_offset > 0, "must bang with positive offset"); | |
| 1386 | |
| 1387 long stdoffset = -bang_offset; | |
| 1388 | |
| 1389 if (Assembler::is_simm(stdoffset, 16)) { | |
| 1390 // Signed 16 bit offset, a simple std is ok. | |
| 1391 if (UseLoadInstructionsForStackBangingPPC64) { | |
| 1392 ___(ld) ld(R0, (int)(signed short)stdoffset, R1_SP); | |
| 1393 } else { | |
| 1394 ___(std) std(R0, (int)(signed short)stdoffset, R1_SP); | |
| 1395 } | |
| 1396 } else if (Assembler::is_simm(stdoffset, 31)) { | |
| 1397 // Use largeoffset calculations for addis & ld/std. | |
| 1398 const int hi = MacroAssembler::largeoffset_si16_si16_hi(stdoffset); | |
| 1399 const int lo = MacroAssembler::largeoffset_si16_si16_lo(stdoffset); | |
| 1400 | |
| 1401 Register tmp = R11; | |
| 1402 ___(addis) addis(tmp, R1_SP, hi); | |
| 1403 if (UseLoadInstructionsForStackBangingPPC64) { | |
| 1404 ___(ld) ld(R0, lo, tmp); | |
| 1405 } else { | |
| 1406 ___(std) std(R0, lo, tmp); | |
| 1407 } | |
| 1408 } else { | |
| 1409 ShouldNotReachHere(); | |
| 1410 } | |
| 1411 | |
| 1412 bang_offset += page_size; | |
| 1413 } | |
| 1414 // R11 trashed | |
| 1415 } // C->need_stack_bang(framesize) && UseStackBanging | |
| 1416 | |
| 1417 unsigned int bytes = (unsigned int)framesize; | |
| 1418 long offset = Assembler::align_addr(bytes, frame::alignment_in_bytes); | |
| 1419 ciMethod *currMethod = C -> method(); | |
| 1420 | |
| 1421 // Optimized version for most common case. | |
| 1422 if (UsePower6SchedulerPPC64 && | |
| 17793 | 1423 !method_is_frameless && Assembler::is_simm((int)(-offset), 16) && |
| 14445 | 1424 !(false /* ConstantsALot TODO: PPC port*/)) { |
| 1425 ___(or) mr(callers_sp, R1_SP); | |
| 17793 | 1426 ___(std) std(return_pc, _abi(lr), R1_SP); |
| 1427 ___(stdu) stdu(R1_SP, -offset, R1_SP); | |
| 14445 | 1428 return; |
| 1429 } | |
| 1430 | |
| 1431 if (!method_is_frameless) { | |
| 1432 // Get callers sp. | |
| 1433 ___(or) mr(callers_sp, R1_SP); | |
| 1434 | |
| 1435 // Push method's frame, modifies SP. | |
| 1436 assert(Assembler::is_uimm(framesize, 32U), "wrong type"); | |
| 1437 // The ABI is already accounted for in 'framesize' via the | |
| 1438 // 'out_preserve' area. | |
| 1439 Register tmp = push_frame_temp; | |
| 1440 // Had to insert code of push_frame((unsigned int)framesize, push_frame_temp). | |
| 1441 if (Assembler::is_simm(-offset, 16)) { | |
| 1442 ___(stdu) stdu(R1_SP, -offset, R1_SP); | |
| 1443 } else { | |
| 1444 long x = -offset; | |
| 1445 // Had to insert load_const(tmp, -offset). | |
| 1446 ___(addis) lis( tmp, (int)((signed short)(((x >> 32) & 0xffff0000) >> 16))); | |
| 1447 ___(ori) ori( tmp, tmp, ((x >> 32) & 0x0000ffff)); | |
| 1448 ___(rldicr) sldi(tmp, tmp, 32); | |
| 1449 ___(oris) oris(tmp, tmp, (x & 0xffff0000) >> 16); | |
| 1450 ___(ori) ori( tmp, tmp, (x & 0x0000ffff)); | |
| 1451 | |
| 1452 ___(stdux) stdux(R1_SP, R1_SP, tmp); | |
| 1453 } | |
| 1454 } | |
| 1455 #if 0 // TODO: PPC port | |
| 1456 // For testing large constant pools, emit a lot of constants to constant pool. | |
| 1457 // "Randomize" const_size. | |
| 1458 if (ConstantsALot) { | |
| 1459 const int num_consts = const_size(); | |
| 1460 for (int i = 0; i < num_consts; i++) { | |
| 1461 __ long_constant(0xB0B5B00BBABE); | |
| 1462 } | |
| 1463 } | |
| 1464 #endif | |
| 1465 if (!method_is_frameless) { | |
| 1466 // Save return pc. | |
| 1467 ___(std) std(return_pc, _abi(lr), callers_sp); | |
| 1468 } | |
| 1469 } | |
| 1470 #undef ___ | |
| 1471 #undef ___stop | |
| 17793 | 1472 #undef ___advance |
| 14445 | 1473 |
| 1474 uint MachPrologNode::size(PhaseRegAlloc *ra_) const { | |
| 1475 // Variable size. determine dynamically. | |
| 1476 return MachNode::size(ra_); | |
| 1477 } | |
| 1478 | |
| 1479 int MachPrologNode::reloc() const { | |
| 1480 // Return number of relocatable values contained in this instruction. | |
| 1481 return 1; // 1 reloc entry for load_const(toc). | |
| 1482 } | |
| 1483 | |
| 1484 //============================================================================= | |
| 1485 | |
| 1486 #ifndef PRODUCT | |
| 1487 void MachEpilogNode::format(PhaseRegAlloc *ra_, outputStream *st) const { | |
| 1488 Compile* C = ra_->C; | |
| 1489 | |
| 1490 st->print("EPILOG\n\t"); | |
| 1491 st->print("restore return pc\n\t"); | |
| 1492 st->print("pop frame\n\t"); | |
| 1493 | |
| 1494 if (do_polling() && C->is_method_compilation()) { | |
| 1495 st->print("touch polling page\n\t"); | |
| 1496 } | |
| 1497 } | |
| 1498 #endif | |
| 1499 | |
| 1500 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1501 Compile* C = ra_->C; | |
| 1502 MacroAssembler _masm(&cbuf); | |
| 1503 | |
| 1504 const long framesize = ((long)C->frame_slots()) << LogBytesPerInt; | |
| 1505 assert(framesize >= 0, "negative frame-size?"); | |
| 1506 | |
| 1507 const bool method_needs_polling = do_polling() && C->is_method_compilation(); | |
| 1508 const bool method_is_frameless = false /* TODO: PPC port C->is_frameless_method()*/; | |
| 1509 const Register return_pc = R11; | |
| 1510 const Register polling_page = R12; | |
| 1511 | |
| 1512 if (!method_is_frameless) { | |
| 1513 // Restore return pc relative to callers' sp. | |
| 1514 __ ld(return_pc, ((int)framesize) + _abi(lr), R1_SP); | |
| 1515 } | |
| 1516 | |
| 1517 if (method_needs_polling) { | |
| 1518 if (LoadPollAddressFromThread) { | |
| 1519 // TODO: PPC port __ ld(polling_page, in_bytes(JavaThread::poll_address_offset()), R16_thread); | |
| 1520 Unimplemented(); | |
| 1521 } else { | |
| 1522 __ load_const_optimized(polling_page, (long)(address) os::get_polling_page()); // TODO: PPC port: get_standard_polling_page() | |
| 1523 } | |
| 1524 } | |
| 1525 | |
| 1526 if (!method_is_frameless) { | |
| 1527 // Move return pc to LR. | |
| 1528 __ mtlr(return_pc); | |
| 1529 // Pop frame (fixed frame-size). | |
| 1530 __ addi(R1_SP, R1_SP, (int)framesize); | |
| 1531 } | |
| 1532 | |
| 1533 if (method_needs_polling) { | |
| 1534 // We need to mark the code position where the load from the safepoint | |
| 1535 // polling page was emitted as relocInfo::poll_return_type here. | |
| 1536 __ relocate(relocInfo::poll_return_type); | |
| 1537 __ load_from_polling_page(polling_page); | |
| 1538 } | |
| 1539 } | |
| 1540 | |
| 1541 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const { | |
| 1542 // Variable size. Determine dynamically. | |
| 1543 return MachNode::size(ra_); | |
| 1544 } | |
| 1545 | |
| 1546 int MachEpilogNode::reloc() const { | |
| 1547 // Return number of relocatable values contained in this instruction. | |
| 1548 return 1; // 1 for load_from_polling_page. | |
| 1549 } | |
| 1550 | |
| 1551 const Pipeline * MachEpilogNode::pipeline() const { | |
| 1552 return MachNode::pipeline_class(); | |
| 1553 } | |
| 1554 | |
| 1555 // This method seems to be obsolete. It is declared in machnode.hpp | |
| 1556 // and defined in all *.ad files, but it is never called. Should we | |
| 1557 // get rid of it? | |
| 1558 int MachEpilogNode::safepoint_offset() const { | |
| 1559 assert(do_polling(), "no return for this epilog node"); | |
| 1560 return 0; | |
| 1561 } | |
| 1562 | |
| 1563 #if 0 // TODO: PPC port | |
| 1564 void MachLoadPollAddrLateNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const { | |
| 1565 MacroAssembler _masm(&cbuf); | |
| 1566 if (LoadPollAddressFromThread) { | |
| 1567 _masm.ld(R11, in_bytes(JavaThread::poll_address_offset()), R16_thread); | |
| 1568 } else { | |
| 1569 _masm.nop(); | |
| 1570 } | |
| 1571 } | |
| 1572 | |
| 1573 uint MachLoadPollAddrLateNode::size(PhaseRegAlloc* ra_) const { | |
| 1574 if (LoadPollAddressFromThread) { | |
| 1575 return 4; | |
| 1576 } else { | |
| 1577 return 4; | |
| 1578 } | |
| 1579 } | |
| 1580 | |
| 1581 #ifndef PRODUCT | |
| 1582 void MachLoadPollAddrLateNode::format(PhaseRegAlloc* ra_, outputStream* st) const { | |
| 1583 st->print_cr(" LD R11, PollAddressOffset, R16_thread \t// LoadPollAddressFromThread"); | |
| 1584 } | |
| 1585 #endif | |
| 1586 | |
| 1587 const RegMask &MachLoadPollAddrLateNode::out_RegMask() const { | |
| 1588 return RSCRATCH1_BITS64_REG_mask(); | |
| 1589 } | |
| 1590 #endif // PPC port | |
| 1591 | |
| 1592 // ============================================================================= | |
| 1593 | |
| 1594 // Figure out which register class each belongs in: rc_int, rc_float or | |
| 1595 // rc_stack. | |
| 1596 enum RC { rc_bad, rc_int, rc_float, rc_stack }; | |
| 1597 | |
| 1598 static enum RC rc_class(OptoReg::Name reg) { | |
| 1599 // Return the register class for the given register. The given register | |
| 1600 // reg is a <register>_num value, which is an index into the MachRegisterNumbers | |
| 1601 // enumeration in adGlobals_ppc64.hpp. | |
| 1602 | |
| 1603 if (reg == OptoReg::Bad) return rc_bad; | |
| 1604 | |
| 1605 // We have 64 integer register halves, starting at index 0. | |
| 1606 if (reg < 64) return rc_int; | |
| 1607 | |
| 1608 // We have 64 floating-point register halves, starting at index 64. | |
| 1609 if (reg < 64+64) return rc_float; | |
| 1610 | |
| 1611 // Between float regs & stack are the flags regs. | |
| 1612 assert(OptoReg::is_stack(reg), "blow up if spilling flags"); | |
| 1613 | |
| 1614 return rc_stack; | |
| 1615 } | |
| 1616 | |
| 1617 static int ld_st_helper(CodeBuffer *cbuf, const char *op_str, uint opcode, int reg, int offset, | |
| 1618 bool do_print, Compile* C, outputStream *st) { | |
| 1619 | |
| 1620 assert(opcode == Assembler::LD_OPCODE || | |
| 1621 opcode == Assembler::STD_OPCODE || | |
| 1622 opcode == Assembler::LWZ_OPCODE || | |
| 1623 opcode == Assembler::STW_OPCODE || | |
| 1624 opcode == Assembler::LFD_OPCODE || | |
| 1625 opcode == Assembler::STFD_OPCODE || | |
| 1626 opcode == Assembler::LFS_OPCODE || | |
| 1627 opcode == Assembler::STFS_OPCODE, | |
| 1628 "opcode not supported"); | |
| 1629 | |
| 1630 if (cbuf) { | |
| 1631 int d = | |
| 1632 (Assembler::LD_OPCODE == opcode || Assembler::STD_OPCODE == opcode) ? | |
| 1633 Assembler::ds(offset+0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/) | |
| 1634 : Assembler::d1(offset+0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/); // Makes no difference in opt build. | |
| 1635 emit_long(*cbuf, opcode | Assembler::rt(Matcher::_regEncode[reg]) | d | Assembler::ra(R1_SP)); | |
| 1636 } | |
| 1637 #ifndef PRODUCT | |
| 1638 else if (do_print) { | |
| 1639 st->print("%-7s %s, [R1_SP + #%d+%d] \t// spill copy", | |
| 1640 op_str, | |
| 1641 Matcher::regName[reg], | |
| 1642 offset, 0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/); | |
| 1643 } | |
| 1644 #endif | |
| 1645 return 4; // size | |
| 1646 } | |
| 1647 | |
| 1648 uint MachSpillCopyNode::implementation(CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream *st) const { | |
| 1649 Compile* C = ra_->C; | |
| 1650 | |
| 1651 // Get registers to move. | |
| 1652 OptoReg::Name src_hi = ra_->get_reg_second(in(1)); | |
| 1653 OptoReg::Name src_lo = ra_->get_reg_first(in(1)); | |
| 1654 OptoReg::Name dst_hi = ra_->get_reg_second(this); | |
| 1655 OptoReg::Name dst_lo = ra_->get_reg_first(this); | |
| 1656 | |
| 1657 enum RC src_hi_rc = rc_class(src_hi); | |
| 1658 enum RC src_lo_rc = rc_class(src_lo); | |
| 1659 enum RC dst_hi_rc = rc_class(dst_hi); | |
| 1660 enum RC dst_lo_rc = rc_class(dst_lo); | |
| 1661 | |
| 1662 assert(src_lo != OptoReg::Bad && dst_lo != OptoReg::Bad, "must move at least 1 register"); | |
| 1663 if (src_hi != OptoReg::Bad) | |
| 1664 assert((src_lo&1)==0 && src_lo+1==src_hi && | |
| 1665 (dst_lo&1)==0 && dst_lo+1==dst_hi, | |
| 1666 "expected aligned-adjacent pairs"); | |
| 1667 // Generate spill code! | |
| 1668 int size = 0; | |
| 1669 | |
| 1670 if (src_lo == dst_lo && src_hi == dst_hi) | |
| 1671 return size; // Self copy, no move. | |
| 1672 | |
| 1673 // -------------------------------------- | |
| 1674 // Memory->Memory Spill. Use R0 to hold the value. | |
| 1675 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) { | |
| 1676 int src_offset = ra_->reg2offset(src_lo); | |
| 1677 int dst_offset = ra_->reg2offset(dst_lo); | |
| 1678 if (src_hi != OptoReg::Bad) { | |
| 1679 assert(src_hi_rc==rc_stack && dst_hi_rc==rc_stack, | |
| 1680 "expected same type of move for high parts"); | |
| 1681 size += ld_st_helper(cbuf, "LD ", Assembler::LD_OPCODE, R0_num, src_offset, !do_size, C, st); | |
| 1682 if (!cbuf && !do_size) st->print("\n\t"); | |
| 1683 size += ld_st_helper(cbuf, "STD ", Assembler::STD_OPCODE, R0_num, dst_offset, !do_size, C, st); | |
| 1684 } else { | |
| 1685 size += ld_st_helper(cbuf, "LWZ ", Assembler::LWZ_OPCODE, R0_num, src_offset, !do_size, C, st); | |
| 1686 if (!cbuf && !do_size) st->print("\n\t"); | |
| 1687 size += ld_st_helper(cbuf, "STW ", Assembler::STW_OPCODE, R0_num, dst_offset, !do_size, C, st); | |
| 1688 } | |
| 1689 return size; | |
| 1690 } | |
| 1691 | |
| 1692 // -------------------------------------- | |
| 1693 // Check for float->int copy; requires a trip through memory. | |
| 1694 if (src_lo_rc == rc_float && dst_lo_rc == rc_int) { | |
| 1695 Unimplemented(); | |
| 1696 } | |
| 1697 | |
| 1698 // -------------------------------------- | |
| 1699 // Check for integer reg-reg copy. | |
| 1700 if (src_lo_rc == rc_int && dst_lo_rc == rc_int) { | |
| 1701 Register Rsrc = as_Register(Matcher::_regEncode[src_lo]); | |
| 1702 Register Rdst = as_Register(Matcher::_regEncode[dst_lo]); | |
| 1703 size = (Rsrc != Rdst) ? 4 : 0; | |
| 1704 | |
| 1705 if (cbuf) { | |
| 1706 MacroAssembler _masm(cbuf); | |
| 1707 if (size) { | |
| 1708 __ mr(Rdst, Rsrc); | |
| 1709 } | |
| 1710 } | |
| 1711 #ifndef PRODUCT | |
| 1712 else if (!do_size) { | |
| 1713 if (size) { | |
| 1714 st->print("%-7s %s, %s \t// spill copy", "MR", Matcher::regName[dst_lo], Matcher::regName[src_lo]); | |
| 1715 } else { | |
| 1716 st->print("%-7s %s, %s \t// spill copy", "MR-NOP", Matcher::regName[dst_lo], Matcher::regName[src_lo]); | |
| 1717 } | |
| 1718 } | |
| 1719 #endif | |
| 1720 return size; | |
| 1721 } | |
| 1722 | |
| 1723 // Check for integer store. | |
| 1724 if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) { | |
| 1725 int dst_offset = ra_->reg2offset(dst_lo); | |
| 1726 if (src_hi != OptoReg::Bad) { | |
| 1727 assert(src_hi_rc==rc_int && dst_hi_rc==rc_stack, | |
| 1728 "expected same type of move for high parts"); | |
| 1729 size += ld_st_helper(cbuf, "STD ", Assembler::STD_OPCODE, src_lo, dst_offset, !do_size, C, st); | |
| 1730 } else { | |
| 1731 size += ld_st_helper(cbuf, "STW ", Assembler::STW_OPCODE, src_lo, dst_offset, !do_size, C, st); | |
| 1732 } | |
| 1733 return size; | |
| 1734 } | |
| 1735 | |
| 1736 // Check for integer load. | |
| 1737 if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) { | |
| 1738 int src_offset = ra_->reg2offset(src_lo); | |
| 1739 if (src_hi != OptoReg::Bad) { | |
| 1740 assert(dst_hi_rc==rc_int && src_hi_rc==rc_stack, | |
| 1741 "expected same type of move for high parts"); | |
| 1742 size += ld_st_helper(cbuf, "LD ", Assembler::LD_OPCODE, dst_lo, src_offset, !do_size, C, st); | |
| 1743 } else { | |
| 1744 size += ld_st_helper(cbuf, "LWZ ", Assembler::LWZ_OPCODE, dst_lo, src_offset, !do_size, C, st); | |
| 1745 } | |
| 1746 return size; | |
| 1747 } | |
| 1748 | |
| 1749 // Check for float reg-reg copy. | |
| 1750 if (src_lo_rc == rc_float && dst_lo_rc == rc_float) { | |
| 1751 if (cbuf) { | |
| 1752 MacroAssembler _masm(cbuf); | |
| 1753 FloatRegister Rsrc = as_FloatRegister(Matcher::_regEncode[src_lo]); | |
| 1754 FloatRegister Rdst = as_FloatRegister(Matcher::_regEncode[dst_lo]); | |
| 1755 __ fmr(Rdst, Rsrc); | |
| 1756 } | |
| 1757 #ifndef PRODUCT | |
| 1758 else if (!do_size) { | |
| 1759 st->print("%-7s %s, %s \t// spill copy", "FMR", Matcher::regName[dst_lo], Matcher::regName[src_lo]); | |
| 1760 } | |
| 1761 #endif | |
| 1762 return 4; | |
| 1763 } | |
| 1764 | |
| 1765 // Check for float store. | |
| 1766 if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) { | |
| 1767 int dst_offset = ra_->reg2offset(dst_lo); | |
| 1768 if (src_hi != OptoReg::Bad) { | |
| 1769 assert(src_hi_rc==rc_float && dst_hi_rc==rc_stack, | |
| 1770 "expected same type of move for high parts"); | |
| 1771 size += ld_st_helper(cbuf, "STFD", Assembler::STFD_OPCODE, src_lo, dst_offset, !do_size, C, st); | |
| 1772 } else { | |
| 1773 size += ld_st_helper(cbuf, "STFS", Assembler::STFS_OPCODE, src_lo, dst_offset, !do_size, C, st); | |
| 1774 } | |
| 1775 return size; | |
| 1776 } | |
| 1777 | |
| 1778 // Check for float load. | |
| 1779 if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) { | |
| 1780 int src_offset = ra_->reg2offset(src_lo); | |
| 1781 if (src_hi != OptoReg::Bad) { | |
| 1782 assert(dst_hi_rc==rc_float && src_hi_rc==rc_stack, | |
| 1783 "expected same type of move for high parts"); | |
| 1784 size += ld_st_helper(cbuf, "LFD ", Assembler::LFD_OPCODE, dst_lo, src_offset, !do_size, C, st); | |
| 1785 } else { | |
| 1786 size += ld_st_helper(cbuf, "LFS ", Assembler::LFS_OPCODE, dst_lo, src_offset, !do_size, C, st); | |
| 1787 } | |
| 1788 return size; | |
| 1789 } | |
| 1790 | |
| 1791 // -------------------------------------------------------------------- | |
| 1792 // Check for hi bits still needing moving. Only happens for misaligned | |
| 1793 // arguments to native calls. | |
| 1794 if (src_hi == dst_hi) | |
| 1795 return size; // Self copy; no move. | |
| 1796 | |
| 1797 assert(src_hi_rc != rc_bad && dst_hi_rc != rc_bad, "src_hi & dst_hi cannot be Bad"); | |
| 1798 ShouldNotReachHere(); // Unimplemented | |
| 1799 return 0; | |
| 1800 } | |
| 1801 | |
| 1802 #ifndef PRODUCT | |
| 1803 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream *st) const { | |
| 1804 if (!ra_) | |
| 1805 st->print("N%d = SpillCopy(N%d)", _idx, in(1)->_idx); | |
| 1806 else | |
| 1807 implementation(NULL, ra_, false, st); | |
| 1808 } | |
| 1809 #endif | |
| 1810 | |
| 1811 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1812 implementation(&cbuf, ra_, false, NULL); | |
| 1813 } | |
| 1814 | |
| 1815 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const { | |
| 1816 return implementation(NULL, ra_, true, NULL); | |
| 1817 } | |
| 1818 | |
| 1819 #if 0 // TODO: PPC port | |
| 1820 ArchOpcode MachSpillCopyNode_archOpcode(MachSpillCopyNode *n, PhaseRegAlloc *ra_) { | |
| 1821 #ifndef PRODUCT | |
| 1822 if (ra_->node_regs_max_index() == 0) return archOpcode_undefined; | |
| 1823 #endif | |
| 1824 assert(ra_->node_regs_max_index() != 0, ""); | |
| 1825 | |
| 1826 // Get registers to move. | |
| 1827 OptoReg::Name src_hi = ra_->get_reg_second(n->in(1)); | |
| 1828 OptoReg::Name src_lo = ra_->get_reg_first(n->in(1)); | |
| 1829 OptoReg::Name dst_hi = ra_->get_reg_second(n); | |
| 1830 OptoReg::Name dst_lo = ra_->get_reg_first(n); | |
| 1831 | |
| 1832 enum RC src_lo_rc = rc_class(src_lo); | |
| 1833 enum RC dst_lo_rc = rc_class(dst_lo); | |
| 1834 | |
| 1835 if (src_lo == dst_lo && src_hi == dst_hi) | |
| 1836 return ppc64Opcode_none; // Self copy, no move. | |
| 1837 | |
| 1838 // -------------------------------------- | |
| 1839 // Memory->Memory Spill. Use R0 to hold the value. | |
| 1840 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) { | |
| 1841 return ppc64Opcode_compound; | |
| 1842 } | |
| 1843 | |
| 1844 // -------------------------------------- | |
| 1845 // Check for float->int copy; requires a trip through memory. | |
| 1846 if (src_lo_rc == rc_float && dst_lo_rc == rc_int) { | |
| 1847 Unimplemented(); | |
| 1848 } | |
| 1849 | |
| 1850 // -------------------------------------- | |
| 1851 // Check for integer reg-reg copy. | |
| 1852 if (src_lo_rc == rc_int && dst_lo_rc == rc_int) { | |
| 1853 Register Rsrc = as_Register(Matcher::_regEncode[src_lo]); | |
| 1854 Register Rdst = as_Register(Matcher::_regEncode[dst_lo]); | |
| 1855 if (Rsrc == Rdst) { | |
| 1856 return ppc64Opcode_none; | |
| 1857 } else { | |
| 1858 return ppc64Opcode_or; | |
| 1859 } | |
| 1860 } | |
| 1861 | |
| 1862 // Check for integer store. | |
| 1863 if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) { | |
| 1864 if (src_hi != OptoReg::Bad) { | |
| 1865 return ppc64Opcode_std; | |
| 1866 } else { | |
| 1867 return ppc64Opcode_stw; | |
| 1868 } | |
| 1869 } | |
| 1870 | |
| 1871 // Check for integer load. | |
| 1872 if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) { | |
| 1873 if (src_hi != OptoReg::Bad) { | |
| 1874 return ppc64Opcode_ld; | |
| 1875 } else { | |
| 1876 return ppc64Opcode_lwz; | |
| 1877 } | |
| 1878 } | |
| 1879 | |
| 1880 // Check for float reg-reg copy. | |
| 1881 if (src_lo_rc == rc_float && dst_lo_rc == rc_float) { | |
| 1882 return ppc64Opcode_fmr; | |
| 1883 } | |
| 1884 | |
| 1885 // Check for float store. | |
| 1886 if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) { | |
| 1887 if (src_hi != OptoReg::Bad) { | |
| 1888 return ppc64Opcode_stfd; | |
| 1889 } else { | |
| 1890 return ppc64Opcode_stfs; | |
| 1891 } | |
| 1892 } | |
| 1893 | |
| 1894 // Check for float load. | |
| 1895 if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) { | |
| 1896 if (src_hi != OptoReg::Bad) { | |
| 1897 return ppc64Opcode_lfd; | |
| 1898 } else { | |
| 1899 return ppc64Opcode_lfs; | |
| 1900 } | |
| 1901 } | |
| 1902 | |
| 1903 // -------------------------------------------------------------------- | |
| 1904 // Check for hi bits still needing moving. Only happens for misaligned | |
| 1905 // arguments to native calls. | |
| 1906 if (src_hi == dst_hi) | |
| 1907 return ppc64Opcode_none; // Self copy; no move. | |
| 1908 | |
| 1909 ShouldNotReachHere(); | |
| 1910 return ppc64Opcode_undefined; | |
| 1911 } | |
| 1912 #endif // PPC port | |
| 1913 | |
| 1914 #ifndef PRODUCT | |
| 1915 void MachNopNode::format(PhaseRegAlloc *ra_, outputStream *st) const { | |
| 1916 st->print("NOP \t// %d nops to pad for loops.", _count); | |
| 1917 } | |
| 1918 #endif | |
| 1919 | |
| 1920 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *) const { | |
| 1921 MacroAssembler _masm(&cbuf); | |
| 1922 // _count contains the number of nops needed for padding. | |
| 1923 for (int i = 0; i < _count; i++) { | |
| 1924 __ nop(); | |
| 1925 } | |
| 1926 } | |
| 1927 | |
| 1928 uint MachNopNode::size(PhaseRegAlloc *ra_) const { | |
| 1929 return _count * 4; | |
| 1930 } | |
| 1931 | |
| 1932 #ifndef PRODUCT | |
| 1933 void BoxLockNode::format(PhaseRegAlloc *ra_, outputStream *st) const { | |
| 1934 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
| 1935 int reg = ra_->get_reg_first(this); | |
| 1936 st->print("ADDI %s, SP, %d \t// box node", Matcher::regName[reg], offset); | |
| 1937 } | |
| 1938 #endif | |
| 1939 | |
| 1940 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1941 MacroAssembler _masm(&cbuf); | |
| 1942 | |
| 1943 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
| 1944 int reg = ra_->get_encode(this); | |
| 1945 | |
| 1946 if (Assembler::is_simm(offset, 16)) { | |
| 1947 __ addi(as_Register(reg), R1, offset); | |
| 1948 } else { | |
| 1949 ShouldNotReachHere(); | |
| 1950 } | |
| 1951 } | |
| 1952 | |
| 1953 uint BoxLockNode::size(PhaseRegAlloc *ra_) const { | |
| 1954 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_). | |
| 1955 return 4; | |
| 1956 } | |
| 1957 | |
| 1958 #ifndef PRODUCT | |
| 1959 void MachUEPNode::format(PhaseRegAlloc *ra_, outputStream *st) const { | |
| 1960 st->print_cr("---- MachUEPNode ----"); | |
| 1961 st->print_cr("..."); | |
| 1962 } | |
| 1963 #endif | |
| 1964 | |
| 1965 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1966 // This is the unverified entry point. | |
| 1967 MacroAssembler _masm(&cbuf); | |
| 1968 | |
| 1969 // Inline_cache contains a klass. | |
| 1970 Register ic_klass = as_Register(Matcher::inline_cache_reg_encode()); | |
| 1971 Register receiver_klass = R0; // tmp | |
| 1972 | |
| 1973 assert_different_registers(ic_klass, receiver_klass, R11_scratch1, R3_ARG1); | |
| 1974 assert(R11_scratch1 == R11, "need prologue scratch register"); | |
| 1975 | |
| 1976 // Check for NULL argument if we don't have implicit null checks. | |
| 1977 if (!ImplicitNullChecks || !os::zero_page_read_protected()) { | |
| 1978 if (TrapBasedNullChecks) { | |
| 1979 __ trap_null_check(R3_ARG1); | |
| 1980 } else { | |
| 1981 Label valid; | |
| 1982 __ cmpdi(CCR0, R3_ARG1, 0); | |
| 1983 __ bne_predict_taken(CCR0, valid); | |
| 1984 // We have a null argument, branch to ic_miss_stub. | |
| 1985 __ b64_patchable((address)SharedRuntime::get_ic_miss_stub(), | |
| 1986 relocInfo::runtime_call_type); | |
| 1987 __ bind(valid); | |
| 1988 } | |
| 1989 } | |
| 1990 // Assume argument is not NULL, load klass from receiver. | |
| 1991 __ load_klass(receiver_klass, R3_ARG1); | |
| 1992 | |
| 1993 if (TrapBasedICMissChecks) { | |
| 1994 __ trap_ic_miss_check(receiver_klass, ic_klass); | |
| 1995 } else { | |
| 1996 Label valid; | |
| 1997 __ cmpd(CCR0, receiver_klass, ic_klass); | |
| 1998 __ beq_predict_taken(CCR0, valid); | |
| 1999 // We have an unexpected klass, branch to ic_miss_stub. | |
| 2000 __ b64_patchable((address)SharedRuntime::get_ic_miss_stub(), | |
| 2001 relocInfo::runtime_call_type); | |
| 2002 __ bind(valid); | |
| 2003 } | |
| 2004 | |
| 2005 // Argument is valid and klass is as expected, continue. | |
| 2006 } | |
| 2007 | |
| 2008 #if 0 // TODO: PPC port | |
| 2009 // Optimize UEP code on z (save a load_const() call in main path). | |
| 2010 int MachUEPNode::ep_offset() { | |
| 2011 return 0; | |
| 2012 } | |
| 2013 #endif | |
| 2014 | |
| 2015 uint MachUEPNode::size(PhaseRegAlloc *ra_) const { | |
| 2016 // Variable size. Determine dynamically. | |
| 2017 return MachNode::size(ra_); | |
| 2018 } | |
| 2019 | |
| 2020 //============================================================================= | |
| 2021 | |
| 2022 uint size_exception_handler() { | |
| 2023 // The exception_handler is a b64_patchable. | |
| 2024 return MacroAssembler::b64_patchable_size; | |
| 2025 } | |
| 2026 | |
| 2027 uint size_deopt_handler() { | |
| 2028 // The deopt_handler is a bl64_patchable. | |
| 2029 return MacroAssembler::bl64_patchable_size; | |
| 2030 } | |
| 2031 | |
| 2032 int emit_exception_handler(CodeBuffer &cbuf) { | |
| 2033 MacroAssembler _masm(&cbuf); | |
| 2034 | |
| 2035 address base = __ start_a_stub(size_exception_handler()); | |
| 2036 if (base == NULL) return 0; // CodeBuffer::expand failed | |
| 2037 | |
| 2038 int offset = __ offset(); | |
| 2039 __ b64_patchable((address)OptoRuntime::exception_blob()->content_begin(), | |
| 2040 relocInfo::runtime_call_type); | |
| 2041 assert(__ offset() - offset == (int)size_exception_handler(), "must be fixed size"); | |
| 2042 __ end_a_stub(); | |
| 2043 | |
| 2044 return offset; | |
| 2045 } | |
| 2046 | |
| 2047 // The deopt_handler is like the exception handler, but it calls to | |
| 2048 // the deoptimization blob instead of jumping to the exception blob. | |
| 2049 int emit_deopt_handler(CodeBuffer& cbuf) { | |
| 2050 MacroAssembler _masm(&cbuf); | |
| 2051 | |
| 2052 address base = __ start_a_stub(size_deopt_handler()); | |
| 2053 if (base == NULL) return 0; // CodeBuffer::expand failed | |
| 2054 | |
| 2055 int offset = __ offset(); | |
| 2056 __ bl64_patchable((address)SharedRuntime::deopt_blob()->unpack(), | |
| 2057 relocInfo::runtime_call_type); | |
| 2058 assert(__ offset() - offset == (int) size_deopt_handler(), "must be fixed size"); | |
| 2059 __ end_a_stub(); | |
| 2060 | |
| 2061 return offset; | |
| 2062 } | |
| 2063 | |
| 2064 //============================================================================= | |
| 2065 | |
| 2066 // Use a frame slots bias for frameless methods if accessing the stack. | |
| 2067 static int frame_slots_bias(int reg_enc, PhaseRegAlloc* ra_) { | |
| 2068 if (as_Register(reg_enc) == R1_SP) { | |
| 2069 return 0; // TODO: PPC port ra_->C->frame_slots_sp_bias_in_bytes(); | |
| 2070 } | |
| 2071 return 0; | |
| 2072 } | |
| 2073 | |
| 2074 const bool Matcher::match_rule_supported(int opcode) { | |
| 2075 if (!has_match_rule(opcode)) | |
| 2076 return false; | |
| 2077 | |
| 2078 switch (opcode) { | |
| 2079 case Op_CountLeadingZerosI: | |
| 2080 case Op_CountLeadingZerosL: | |
| 2081 case Op_CountTrailingZerosI: | |
| 2082 case Op_CountTrailingZerosL: | |
| 2083 if (!UseCountLeadingZerosInstructionsPPC64) | |
| 2084 return false; | |
| 2085 break; | |
| 2086 | |
| 2087 case Op_PopCountI: | |
| 2088 case Op_PopCountL: | |
| 2089 return (UsePopCountInstruction && VM_Version::has_popcntw()); | |
| 2090 | |
| 2091 case Op_StrComp: | |
| 2092 return SpecialStringCompareTo; | |
| 2093 case Op_StrEquals: | |
| 2094 return SpecialStringEquals; | |
| 2095 case Op_StrIndexOf: | |
| 2096 return SpecialStringIndexOf; | |
| 2097 } | |
| 2098 | |
| 2099 return true; // Per default match rules are supported. | |
| 2100 } | |
| 2101 | |
| 2102 int Matcher::regnum_to_fpu_offset(int regnum) { | |
| 2103 // No user for this method? | |
| 2104 Unimplemented(); | |
| 2105 return 999; | |
| 2106 } | |
| 2107 | |
| 2108 const bool Matcher::convL2FSupported(void) { | |
| 2109 // fcfids can do the conversion (>= Power7). | |
| 2110 // fcfid + frsp showed rounding problem when result should be 0x3f800001. | |
| 2111 return VM_Version::has_fcfids(); // False means that conversion is done by runtime call. | |
| 2112 } | |
| 2113 | |
| 2114 // Vector width in bytes. | |
| 2115 const int Matcher::vector_width_in_bytes(BasicType bt) { | |
| 2116 assert(MaxVectorSize == 8, ""); | |
| 2117 return 8; | |
| 2118 } | |
| 2119 | |
| 2120 // Vector ideal reg. | |
| 2121 const int Matcher::vector_ideal_reg(int size) { | |
| 2122 assert(MaxVectorSize == 8 && size == 8, ""); | |
| 2123 return Op_RegL; | |
| 2124 } | |
| 2125 | |
| 2126 const int Matcher::vector_shift_count_ideal_reg(int size) { | |
| 2127 fatal("vector shift is not supported"); | |
| 2128 return Node::NotAMachineReg; | |
| 2129 } | |
| 2130 | |
| 2131 // Limits on vector size (number of elements) loaded into vector. | |
| 2132 const int Matcher::max_vector_size(const BasicType bt) { | |
| 2133 assert(is_java_primitive(bt), "only primitive type vectors"); | |
| 2134 return vector_width_in_bytes(bt)/type2aelembytes(bt); | |
| 2135 } | |
| 2136 | |
| 2137 const int Matcher::min_vector_size(const BasicType bt) { | |
| 2138 return max_vector_size(bt); // Same as max. | |
| 2139 } | |
| 2140 | |
| 2141 // PPC doesn't support misaligned vectors store/load. | |
| 2142 const bool Matcher::misaligned_vectors_ok() { | |
| 2143 return false; | |
| 2144 } | |
| 2145 | |
| 2146 // RETURNS: whether this branch offset is short enough that a short | |
| 2147 // branch can be used. | |
| 2148 // | |
| 2149 // If the platform does not provide any short branch variants, then | |
| 2150 // this method should return `false' for offset 0. | |
| 2151 // | |
| 2152 // `Compile::Fill_buffer' will decide on basis of this information | |
| 2153 // whether to do the pass `Compile::Shorten_branches' at all. | |
| 2154 // | |
| 2155 // And `Compile::Shorten_branches' will decide on basis of this | |
| 2156 // information whether to replace particular branch sites by short | |
| 2157 // ones. | |
| 2158 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) { | |
| 2159 // Is the offset within the range of a ppc64 pc relative branch? | |
| 2160 bool b; | |
| 2161 | |
| 2162 const int safety_zone = 3 * BytesPerInstWord; | |
| 2163 b = Assembler::is_simm((offset<0 ? offset-safety_zone : offset+safety_zone), | |
| 2164 29 - 16 + 1 + 2); | |
| 2165 return b; | |
| 2166 } | |
| 2167 | |
| 2168 const bool Matcher::isSimpleConstant64(jlong value) { | |
| 2169 // Probably always true, even if a temp register is required. | |
| 2170 return true; | |
| 2171 } | |
| 2172 /* TODO: PPC port | |
| 2173 // Make a new machine dependent decode node (with its operands). | |
| 2174 MachTypeNode *Matcher::make_decode_node(Compile *C) { | |
| 2175 assert(Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0, | |
| 2176 "This method is only implemented for unscaled cOops mode so far"); | |
| 2177 MachTypeNode *decode = new (C) decodeN_unscaledNode(); | |
| 2178 decode->set_opnd_array(0, new (C) iRegPdstOper()); | |
| 2179 decode->set_opnd_array(1, new (C) iRegNsrcOper()); | |
| 2180 return decode; | |
| 2181 } | |
| 2182 */ | |
| 2183 // Threshold size for cleararray. | |
| 2184 const int Matcher::init_array_short_size = 8 * BytesPerLong; | |
| 2185 | |
| 2186 // false => size gets scaled to BytesPerLong, ok. | |
| 2187 const bool Matcher::init_array_count_is_in_bytes = false; | |
| 2188 | |
| 2189 // Use conditional move (CMOVL) on Power7. | |
| 2190 const int Matcher::long_cmove_cost() { return 0; } // this only makes long cmoves more expensive than int cmoves | |
| 2191 | |
| 2192 // Suppress CMOVF. Conditional move available (sort of) on PPC64 only from P7 onwards. Not exploited yet. | |
| 2193 // fsel doesn't accept a condition register as input, so this would be slightly different. | |
| 2194 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; } | |
| 2195 | |
| 2196 // Power6 requires postalloc expand (see block.cpp for description of postalloc expand). | |
| 2197 const bool Matcher::require_postalloc_expand = true; | |
| 2198 | |
| 2199 // Should the Matcher clone shifts on addressing modes, expecting them to | |
| 2200 // be subsumed into complex addressing expressions or compute them into | |
| 2201 // registers? True for Intel but false for most RISCs. | |
| 2202 const bool Matcher::clone_shift_expressions = false; | |
| 2203 | |
| 2204 // Do we need to mask the count passed to shift instructions or does | |
| 2205 // the cpu only look at the lower 5/6 bits anyway? | |
| 2206 // Off, as masks are generated in expand rules where required. | |
| 2207 // Constant shift counts are handled in Ideal phase. | |
| 2208 const bool Matcher::need_masked_shift_count = false; | |
| 2209 | |
| 2210 // This affects two different things: | |
| 2211 // - how Decode nodes are matched | |
| 2212 // - how ImplicitNullCheck opportunities are recognized | |
| 2213 // If true, the matcher will try to remove all Decodes and match them | |
| 2214 // (as operands) into nodes. NullChecks are not prepared to deal with | |
| 2215 // Decodes by final_graph_reshaping(). | |
| 2216 // If false, final_graph_reshaping() forces the decode behind the Cmp | |
| 2217 // for a NullCheck. The matcher matches the Decode node into a register. | |
| 2218 // Implicit_null_check optimization moves the Decode along with the | |
| 2219 // memory operation back up before the NullCheck. | |
| 2220 bool Matcher::narrow_oop_use_complex_address() { | |
| 2221 // TODO: PPC port if (MatchDecodeNodes) return true; | |
| 2222 return false; | |
| 2223 } | |
| 2224 | |
| 2225 bool Matcher::narrow_klass_use_complex_address() { | |
| 2226 NOT_LP64(ShouldNotCallThis()); | |
| 2227 assert(UseCompressedClassPointers, "only for compressed klass code"); | |
| 2228 // TODO: PPC port if (MatchDecodeNodes) return true; | |
| 2229 return false; | |
| 2230 } | |
| 2231 | |
| 2232 // Is it better to copy float constants, or load them directly from memory? | |
| 2233 // Intel can load a float constant from a direct address, requiring no | |
| 2234 // extra registers. Most RISCs will have to materialize an address into a | |
| 2235 // register first, so they would do better to copy the constant from stack. | |
| 2236 const bool Matcher::rematerialize_float_constants = false; | |
| 2237 | |
| 2238 // If CPU can load and store mis-aligned doubles directly then no fixup is | |
| 2239 // needed. Else we split the double into 2 integer pieces and move it | |
| 2240 // piece-by-piece. Only happens when passing doubles into C code as the | |
| 2241 // Java calling convention forces doubles to be aligned. | |
| 2242 const bool Matcher::misaligned_doubles_ok = true; | |
| 2243 | |
| 2244 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) { | |
| 2245 Unimplemented(); | |
| 2246 } | |
| 2247 | |
| 2248 // Advertise here if the CPU requires explicit rounding operations | |
| 2249 // to implement the UseStrictFP mode. | |
| 2250 const bool Matcher::strict_fp_requires_explicit_rounding = false; | |
| 2251 | |
| 2252 // Do floats take an entire double register or just half? | |
| 2253 // | |
| 2254 // A float occupies a ppc64 double register. For the allocator, a | |
| 2255 // ppc64 double register appears as a pair of float registers. | |
| 2256 bool Matcher::float_in_double() { return true; } | |
| 2257 | |
| 2258 // Do ints take an entire long register or just half? | |
| 2259 // The relevant question is how the int is callee-saved: | |
| 2260 // the whole long is written but de-opt'ing will have to extract | |
| 2261 // the relevant 32 bits. | |
| 2262 const bool Matcher::int_in_long = true; | |
| 2263 | |
| 2264 // Constants for c2c and c calling conventions. | |
| 2265 | |
| 2266 const MachRegisterNumbers iarg_reg[8] = { | |
| 2267 R3_num, R4_num, R5_num, R6_num, | |
| 2268 R7_num, R8_num, R9_num, R10_num | |
| 2269 }; | |
| 2270 | |
| 2271 const MachRegisterNumbers farg_reg[13] = { | |
| 2272 F1_num, F2_num, F3_num, F4_num, | |
| 2273 F5_num, F6_num, F7_num, F8_num, | |
| 2274 F9_num, F10_num, F11_num, F12_num, | |
| 2275 F13_num | |
| 2276 }; | |
| 2277 | |
| 2278 const int num_iarg_registers = sizeof(iarg_reg) / sizeof(iarg_reg[0]); | |
| 2279 | |
| 2280 const int num_farg_registers = sizeof(farg_reg) / sizeof(farg_reg[0]); | |
| 2281 | |
| 2282 // Return whether or not this register is ever used as an argument. This | |
| 2283 // function is used on startup to build the trampoline stubs in generateOptoStub. | |
| 2284 // Registers not mentioned will be killed by the VM call in the trampoline, and | |
| 2285 // arguments in those registers not be available to the callee. | |
| 2286 bool Matcher::can_be_java_arg(int reg) { | |
| 2287 // We return true for all registers contained in iarg_reg[] and | |
| 2288 // farg_reg[] and their virtual halves. | |
| 2289 // We must include the virtual halves in order to get STDs and LDs | |
| 2290 // instead of STWs and LWs in the trampoline stubs. | |
| 2291 | |
| 2292 if ( reg == R3_num || reg == R3_H_num | |
| 2293 || reg == R4_num || reg == R4_H_num | |
| 2294 || reg == R5_num || reg == R5_H_num | |
| 2295 || reg == R6_num || reg == R6_H_num | |
| 2296 || reg == R7_num || reg == R7_H_num | |
| 2297 || reg == R8_num || reg == R8_H_num | |
| 2298 || reg == R9_num || reg == R9_H_num | |
| 2299 || reg == R10_num || reg == R10_H_num) | |
| 2300 return true; | |
| 2301 | |
| 2302 if ( reg == F1_num || reg == F1_H_num | |
| 2303 || reg == F2_num || reg == F2_H_num | |
| 2304 || reg == F3_num || reg == F3_H_num | |
| 2305 || reg == F4_num || reg == F4_H_num | |
| 2306 || reg == F5_num || reg == F5_H_num | |
| 2307 || reg == F6_num || reg == F6_H_num | |
| 2308 || reg == F7_num || reg == F7_H_num | |
| 2309 || reg == F8_num || reg == F8_H_num | |
| 2310 || reg == F9_num || reg == F9_H_num | |
| 2311 || reg == F10_num || reg == F10_H_num | |
| 2312 || reg == F11_num || reg == F11_H_num | |
| 2313 || reg == F12_num || reg == F12_H_num | |
| 2314 || reg == F13_num || reg == F13_H_num) | |
| 2315 return true; | |
| 2316 | |
| 2317 return false; | |
| 2318 } | |
| 2319 | |
| 2320 bool Matcher::is_spillable_arg(int reg) { | |
| 2321 return can_be_java_arg(reg); | |
| 2322 } | |
| 2323 | |
| 2324 bool Matcher::use_asm_for_ldiv_by_con(jlong divisor) { | |
| 2325 return false; | |
| 2326 } | |
| 2327 | |
| 2328 // Register for DIVI projection of divmodI. | |
| 2329 RegMask Matcher::divI_proj_mask() { | |
| 2330 ShouldNotReachHere(); | |
| 2331 return RegMask(); | |
| 2332 } | |
| 2333 | |
| 2334 // Register for MODI projection of divmodI. | |
| 2335 RegMask Matcher::modI_proj_mask() { | |
| 2336 ShouldNotReachHere(); | |
| 2337 return RegMask(); | |
| 2338 } | |
| 2339 | |
| 2340 // Register for DIVL projection of divmodL. | |
| 2341 RegMask Matcher::divL_proj_mask() { | |
| 2342 ShouldNotReachHere(); | |
| 2343 return RegMask(); | |
| 2344 } | |
| 2345 | |
| 2346 // Register for MODL projection of divmodL. | |
| 2347 RegMask Matcher::modL_proj_mask() { | |
| 2348 ShouldNotReachHere(); | |
| 2349 return RegMask(); | |
| 2350 } | |
| 2351 | |
| 2352 const RegMask Matcher::method_handle_invoke_SP_save_mask() { | |
| 2353 return RegMask(); | |
| 2354 } | |
| 2355 | |
| 2356 const RegMask Matcher::mathExactI_result_proj_mask() { | |
| 2357 return RARG4_BITS64_REG_mask(); | |
| 2358 } | |
| 2359 | |
| 2360 const RegMask Matcher::mathExactL_result_proj_mask() { | |
| 2361 return RARG4_BITS64_REG_mask(); | |
| 2362 } | |
| 2363 | |
| 2364 const RegMask Matcher::mathExactI_flags_proj_mask() { | |
| 2365 return INT_FLAGS_mask(); | |
| 2366 } | |
| 2367 | |
| 2368 %} | |
| 2369 | |
| 2370 //----------ENCODING BLOCK----------------------------------------------------- | |
| 2371 // This block specifies the encoding classes used by the compiler to output | |
| 2372 // byte streams. Encoding classes are parameterized macros used by | |
| 2373 // Machine Instruction Nodes in order to generate the bit encoding of the | |
| 2374 // instruction. Operands specify their base encoding interface with the | |
| 2375 // interface keyword. There are currently supported four interfaces, | |
| 2376 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an | |
| 2377 // operand to generate a function which returns its register number when | |
| 2378 // queried. CONST_INTER causes an operand to generate a function which | |
| 2379 // returns the value of the constant when queried. MEMORY_INTER causes an | |
| 2380 // operand to generate four functions which return the Base Register, the | |
| 2381 // Index Register, the Scale Value, and the Offset Value of the operand when | |
| 2382 // queried. COND_INTER causes an operand to generate six functions which | |
| 2383 // return the encoding code (ie - encoding bits for the instruction) | |
| 2384 // associated with each basic boolean condition for a conditional instruction. | |
| 2385 // | |
| 2386 // Instructions specify two basic values for encoding. Again, a function | |
| 2387 // is available to check if the constant displacement is an oop. They use the | |
| 2388 // ins_encode keyword to specify their encoding classes (which must be | |
| 2389 // a sequence of enc_class names, and their parameters, specified in | |
| 2390 // the encoding block), and they use the | |
| 2391 // opcode keyword to specify, in order, their primary, secondary, and | |
| 2392 // tertiary opcode. Only the opcode sections which a particular instruction | |
| 2393 // needs for encoding need to be specified. | |
| 2394 encode %{ | |
| 2395 enc_class enc_unimplemented %{ | |
| 2396 // TODO: PPC port $archOpcode(ppc64Opcode_compound); | |
| 2397 MacroAssembler _masm(&cbuf); | |
| 2398 __ unimplemented("Unimplemented mach node encoding in AD file.", 13); | |
| 2399 %} | |
| 2400 | |
| 2401 enc_class enc_untested %{ | |
| 2402 #ifdef ASSERT | |
| 2403 // TODO: PPC port $archOpcode(ppc64Opcode_compound); | |
| 2404 MacroAssembler _masm(&cbuf); | |
| 2405 __ untested("Untested mach node encoding in AD file."); | |
| 2406 #else | |
| 2407 // TODO: PPC port $archOpcode(ppc64Opcode_none); | |
| 2408 #endif | |
| 2409 %} | |
| 2410 | |
| 2411 enc_class enc_lbz(iRegIdst dst, memory mem) %{ | |
| 2412 // TODO: PPC port $archOpcode(ppc64Opcode_lbz); | |
| 2413 MacroAssembler _masm(&cbuf); | |
| 2414 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); | |
| 2415 __ lbz($dst$$Register, Idisp, $mem$$base$$Register); | |
| 2416 %} | |
| 2417 | |
| 2418 // Load acquire. | |
| 2419 enc_class enc_lbz_ac(iRegIdst dst, memory mem) %{ | |
| 2420 // TODO: PPC port $archOpcode(ppc64Opcode_compound); | |
| 2421 MacroAssembler _masm(&cbuf); | |
| 2422 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); | |
| 2423 __ lbz($dst$$Register, Idisp, $mem$$base$$Register); | |
| 2424 __ twi_0($dst$$Register); | |
| 2425 __ isync(); | |
| 2426 %} | |
| 2427 | |
| 2428 enc_class enc_lhz(iRegIdst dst, memory mem) %{ | |
| 2429 // TODO: PPC port $archOpcode(ppc64Opcode_lhz); | |
| 2430 | |
| 2431 MacroAssembler _masm(&cbuf); | |
| 2432 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); | |
| 2433 __ lhz($dst$$Register, Idisp, $mem$$base$$Register); | |
| 2434 %} | |
| 2435 | |
| 2436 // Load acquire. | |
| 2437 enc_class enc_lhz_ac(iRegIdst dst, memory mem) %{ | |
| 2438 // TODO: PPC port $archOpcode(ppc64Opcode_compound); | |
| 2439 | |
| 2440 MacroAssembler _masm(&cbuf); | |
| 2441 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); | |
| 2442 __ lhz($dst$$Register, Idisp, $mem$$base$$Register); | |
| 2443 __ twi_0($dst$$Register); | |
| 2444 __ isync(); | |
| 2445 %} | |
| 2446 | |
| 2447 enc_class enc_lwz(iRegIdst dst, memory mem) %{ | |
| 2448 // TODO: PPC port $archOpcode(ppc64Opcode_lwz); | |
| 2449 | |
| 2450 MacroAssembler _masm(&cbuf); | |
| 2451 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); | |
| 2452 __ lwz($dst$$Register, Idisp, $mem$$base$$Register); | |
| 2453 %} | |
| 2454 | |
| 2455 // Load acquire. | |
| 2456 enc_class enc_lwz_ac(iRegIdst dst, memory mem) %{ | |
| 2457 // TODO: PPC port $archOpcode(ppc64Opcode_compound); | |
| 2458 | |
| 2459 MacroAssembler _masm(&cbuf); | |
| 2460 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); | |
| 2461 __ lwz($dst$$Register, Idisp, $mem$$base$$Register); | |
| 2462 __ twi_0($dst$$Register); | |
| 2463 __ isync(); | |
| 2464 %} | |
| 2465 | |
| 2466 enc_class enc_ld(iRegLdst dst, memoryAlg4 mem) %{ | |
| 2467 // TODO: PPC port $archOpcode(ppc64Opcode_ld); | |
| 2468 MacroAssembler _masm(&cbuf); | |
| 2469 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); | |
| 2470 // Operand 'ds' requires 4-alignment. | |
| 2471 assert((Idisp & 0x3) == 0, "unaligned offset"); | |
| 2472 __ ld($dst$$Register, Idisp, $mem$$base$$Register); | |
| 2473 %} | |
| 2474 | |
| 2475 // Load acquire. | |
| 2476 enc_class enc_ld_ac(iRegLdst dst, memoryAlg4 mem) %{ | |
| 2477 // TODO: PPC port $archOpcode(ppc64Opcode_compound); | |
| 2478 MacroAssembler _masm(&cbuf); | |
| 2479 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); | |
| 2480 // Operand 'ds' requires 4-alignment. | |
| 2481 assert((Idisp & 0x3) == 0, "unaligned offset"); | |
| 2482 __ ld($dst$$Register, Idisp, $mem$$base$$Register); | |
| 2483 __ twi_0($dst$$Register); | |
| 2484 __ isync(); | |
| 2485 %} | |
| 2486 | |
| 2487 enc_class enc_lfd(RegF dst, memory mem) %{ | |
| 2488 // TODO: PPC port $archOpcode(ppc64Opcode_lfd); | |
| 2489 MacroAssembler _masm(&cbuf); | |
| 2490 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); | |
| 2491 __ lfd($dst$$FloatRegister, Idisp, $mem$$base$$Register); | |
| 2492 %} | |
| 2493 | |
| 2494 enc_class enc_load_long_constL(iRegLdst dst, immL src, iRegLdst toc) %{ | |
| 2495 // TODO: PPC port $archOpcode(ppc64Opcode_ld); | |
| 2496 | |
| 2497 MacroAssembler _masm(&cbuf); | |
| 2498 int toc_offset = 0; | |
| 2499 | |
| 2500 if (!ra_->C->in_scratch_emit_size()) { | |
| 2501 address const_toc_addr; | |
| 2502 // Create a non-oop constant, no relocation needed. | |
| 2503 // If it is an IC, it has a virtual_call_Relocation. | |
| 2504 const_toc_addr = __ long_constant((jlong)$src$$constant); | |
| 2505 | |
| 2506 // Get the constant's TOC offset. | |
| 2507 toc_offset = __ offset_to_method_toc(const_toc_addr); | |
| 2508 | |
| 2509 // Keep the current instruction offset in mind. | |
| 2510 ((loadConLNode*)this)->_cbuf_insts_offset = __ offset(); | |
| 2511 } | |
| 2512 | |
| 2513 __ ld($dst$$Register, toc_offset, $toc$$Register); | |
| 2514 %} | |
| 2515 | |
| 2516 enc_class enc_load_long_constL_hi(iRegLdst dst, iRegLdst toc, immL src) %{ | |
| 2517 // TODO: PPC port $archOpcode(ppc64Opcode_addis); | |
| 2518 | |
| 2519 MacroAssembler _masm(&cbuf); | |
| 2520 | |
| 2521 if (!ra_->C->in_scratch_emit_size()) { | |
| 2522 address const_toc_addr; | |
| 2523 // Create a non-oop constant, no relocation needed. | |
| 2524 // If it is an IC, it has a virtual_call_Relocation. | |
| 2525 const_toc_addr = __ long_constant((jlong)$src$$constant); | |
| 2526 | |
| 2527 // Get the constant's TOC offset. | |
| 2528 const int toc_offset = __ offset_to_method_toc(const_toc_addr); | |
| 2529 // Store the toc offset of the constant. | |
| 2530 ((loadConL_hiNode*)this)->_const_toc_offset = toc_offset; | |
| 2531 | |
| 2532 // Also keep the current instruction offset in mind. | |
| 2533 ((loadConL_hiNode*)this)->_cbuf_insts_offset = __ offset(); | |
| 2534 } | |
| 2535 | |
| 2536 __ addis($dst$$Register, $toc$$Register, MacroAssembler::largeoffset_si16_si16_hi(_const_toc_offset)); | |
| 2537 %} | |
| 2538 | |
| 2539 %} // encode | |
| 2540 | |
| 2541 source %{ | |
| 2542 | |
| 2543 typedef struct { | |
| 2544 loadConL_hiNode *_large_hi; | |
| 2545 loadConL_loNode *_large_lo; | |
| 2546 loadConLNode *_small; | |
| 2547 MachNode *_last; | |
| 2548 } loadConLNodesTuple; | |
| 2549 | |
| 2550 loadConLNodesTuple loadConLNodesTuple_create(Compile *C, PhaseRegAlloc *ra_, Node *toc, immLOper *immSrc, | |
| 2551 OptoReg::Name reg_second, OptoReg::Name reg_first) { | |
| 2552 loadConLNodesTuple nodes; | |
| 2553 | |
| 2554 const bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000; | |
| 2555 if (large_constant_pool) { | |
| 2556 // Create new nodes. | |
| 2557 loadConL_hiNode *m1 = new (C) loadConL_hiNode(); | |
| 2558 loadConL_loNode *m2 = new (C) loadConL_loNode(); | |
| 2559 | |
| 2560 // inputs for new nodes | |
| 2561 m1->add_req(NULL, toc); | |
| 2562 m2->add_req(NULL, m1); | |
| 2563 | |
| 2564 // operands for new nodes | |
| 2565 m1->_opnds[0] = new (C) iRegLdstOper(); // dst | |
| 2566 m1->_opnds[1] = immSrc; // src | |
| 2567 m1->_opnds[2] = new (C) iRegPdstOper(); // toc | |
| 2568 m2->_opnds[0] = new (C) iRegLdstOper(); // dst | |
| 2569 m2->_opnds[1] = immSrc; // src | |
| 2570 m2->_opnds[2] = new (C) iRegLdstOper(); // base | |
| 2571 | |
| 2572 // Initialize ins_attrib TOC fields. | |
| 2573 m1->_const_toc_offset = -1; | |
| 2574 m2->_const_toc_offset_hi_node = m1; | |
| 2575 | |
| 2576 // Initialize ins_attrib instruction offset. | |
| 2577 m1->_cbuf_insts_offset = -1; | |
| 2578 | |
| 2579 // register allocation for new nodes | |
| 2580 ra_->set_pair(m1->_idx, reg_second, reg_first); | |
| 2581 ra_->set_pair(m2->_idx, reg_second, reg_first); | |
| 2582 | |
| 2583 // Create result. | |
| 2584 nodes._large_hi = m1; | |
| 2585 nodes._large_lo = m2; | |
| 2586 nodes._small = NULL; | |
| 2587 nodes._last = nodes._large_lo; | |
| 2588 assert(m2->bottom_type()->isa_long(), "must be long"); | |
| 2589 } else { | |
| 2590 loadConLNode *m2 = new (C) loadConLNode(); | |
| 2591 | |
| 2592 // inputs for new nodes | |
| 2593 m2->add_req(NULL, toc); | |
| 2594 | |
| 2595 // operands for new nodes | |
| 2596 m2->_opnds[0] = new (C) iRegLdstOper(); // dst | |
| 2597 m2->_opnds[1] = immSrc; // src | |
| 2598 m2->_opnds[2] = new (C) iRegPdstOper(); // toc | |
| 2599 | |
| 2600 // Initialize ins_attrib instruction offset. | |
| 2601 m2->_cbuf_insts_offset = -1; | |
| 2602 | |
| 2603 // register allocation for new nodes | |
| 2604 ra_->set_pair(m2->_idx, reg_second, reg_first); | |
| 2605 | |
| 2606 // Create result. | |
| 2607 nodes._large_hi = NULL; | |
| 2608 nodes._large_lo = NULL; | |
| 2609 nodes._small = m2; | |
| 2610 nodes._last = nodes._small; | |
| 2611 assert(m2->bottom_type()->isa_long(), "must be long"); | |
| 2612 } | |
| 2613 | |
| 2614 return nodes; | |
| 2615 } | |
| 2616 | |
| 2617 %} // source | |
| 2618 | |
| 2619 encode %{ | |
| 2620 // Postalloc expand emitter for loading a long constant from the method's TOC. | |
| 2621 // Enc_class needed as consttanttablebase is not supported by postalloc | |
| 2622 // expand. | |
| 2623 enc_class postalloc_expand_load_long_constant(iRegLdst dst, immL src, iRegLdst toc) %{ | |
| 2624 // Create new nodes. | |
| 2625 loadConLNodesTuple loadConLNodes = | |
| 2626 loadConLNodesTuple_create(C, ra_, n_toc, op_src, | |
| 2627 ra_->get_reg_second(this), ra_->get_reg_first(this)); | |
| 2628 | |
| 2629 // Push new nodes. | |
| 2630 if (loadConLNodes._large_hi) nodes->push(loadConLNodes._large_hi); | |
| 2631 if (loadConLNodes._last) nodes->push(loadConLNodes._last); | |
| 2632 | |
| 2633 // some asserts | |
| 2634 assert(nodes->length() >= 1, "must have created at least 1 node"); | |
| 2635 assert(loadConLNodes._last->bottom_type()->isa_long(), "must be long"); | |
| 2636 %} | |
| 2637 | |
| 2638 enc_class enc_load_long_constP(iRegLdst dst, immP src, iRegLdst toc) %{ | |
| 2639 // TODO: PPC port $archOpcode(ppc64Opcode_ld); | |
| 2640 | |
| 2641 MacroAssembler _masm(&cbuf); | |
| 2642 int toc_offset = 0; | |
| 2643 | |
| 2644 if (!ra_->C->in_scratch_emit_size()) { | |
| 2645 intptr_t val = $src$$constant; | |
| 2646 relocInfo::relocType constant_reloc = $src->constant_reloc(); // src | |
| 2647 address const_toc_addr; | |
| 2648 if (constant_reloc == relocInfo::oop_type) { | |
| 2649 // Create an oop constant and a corresponding relocation. | |
| 2650 AddressLiteral a = __ allocate_oop_address((jobject)val); | |
| 2651 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none); | |
| 2652 __ relocate(a.rspec()); | |
| 2653 } else if (constant_reloc == relocInfo::metadata_type) { | |
| 2654 AddressLiteral a = __ allocate_metadata_address((Metadata *)val); | |
| 2655 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none); | |
| 2656 __ relocate(a.rspec()); | |
| 2657 } else { | |
| 2658 // Create a non-oop constant, no relocation needed. | |
| 2659 const_toc_addr = __ long_constant((jlong)$src$$constant); | |
| 2660 } | |
| 2661 | |
| 2662 // Get the constant's TOC offset. | |
| 2663 toc_offset = __ offset_to_method_toc(const_toc_addr); | |
| 2664 } | |
| 2665 | |
| 2666 __ ld($dst$$Register, toc_offset, $toc$$Register); | |
| 2667 %} | |
| 2668 | |
| 2669 enc_class enc_load_long_constP_hi(iRegLdst dst, immP src, iRegLdst toc) %{ | |
| 2670 // TODO: PPC port $archOpcode(ppc64Opcode_addis); | |
| 2671 | |
| 2672 MacroAssembler _masm(&cbuf); | |
| 2673 if (!ra_->C->in_scratch_emit_size()) { | |
| 2674 intptr_t val = $src$$constant; | |
| 2675 relocInfo::relocType constant_reloc = $src->constant_reloc(); // src | |
| 2676 address const_toc_addr; | |
| 2677 if (constant_reloc == relocInfo::oop_type) { | |
| 2678 // Create an oop constant and a corresponding relocation. | |
| 2679 AddressLiteral a = __ allocate_oop_address((jobject)val); | |
| 2680 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none); | |
| 2681 __ relocate(a.rspec()); | |
| 2682 } else if (constant_reloc == relocInfo::metadata_type) { | |
| 2683 AddressLiteral a = __ allocate_metadata_address((Metadata *)val); | |
| 2684 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none); | |
| 2685 __ relocate(a.rspec()); | |
| 2686 } else { // non-oop pointers, e.g. card mark base, heap top | |
| 2687 // Create a non-oop constant, no relocation needed. | |
| 2688 const_toc_addr = __ long_constant((jlong)$src$$constant); | |
| 2689 } | |
| 2690 | |
| 2691 // Get the constant's TOC offset. | |
| 2692 const int toc_offset = __ offset_to_method_toc(const_toc_addr); | |
| 2693 // Store the toc offset of the constant. | |
| 2694 ((loadConP_hiNode*)this)->_const_toc_offset = toc_offset; | |
| 2695 } | |
| 2696 | |
| 2697 __ addis($dst$$Register, $toc$$Register, MacroAssembler::largeoffset_si16_si16_hi(_const_toc_offset)); | |
| 2698 %} | |
| 2699 | |
| 2700 // Postalloc expand emitter for loading a ptr constant from the method's TOC. | |
| 2701 // Enc_class needed as consttanttablebase is not supported by postalloc | |
| 2702 // expand. | |
| 2703 enc_class postalloc_expand_load_ptr_constant(iRegPdst dst, immP src, iRegLdst toc) %{ | |
| 2704 const bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000; | |
| 2705 if (large_constant_pool) { | |
| 2706 // Create new nodes. | |
| 2707 loadConP_hiNode *m1 = new (C) loadConP_hiNode(); | |
| 2708 loadConP_loNode *m2 = new (C) loadConP_loNode(); | |
| 2709 | |
| 2710 // inputs for new nodes | |
| 2711 m1->add_req(NULL, n_toc); | |
| 2712 m2->add_req(NULL, m1); | |
| 2713 | |
| 2714 // operands for new nodes | |
| 2715 m1->_opnds[0] = new (C) iRegPdstOper(); // dst | |
| 2716 m1->_opnds[1] = op_src; // src | |
| 2717 m1->_opnds[2] = new (C) iRegPdstOper(); // toc | |
| 2718 m2->_opnds[0] = new (C) iRegPdstOper(); // dst | |
| 2719 m2->_opnds[1] = op_src; // src | |
| 2720 m2->_opnds[2] = new (C) iRegLdstOper(); // base | |
| 2721 | |
| 2722 // Initialize ins_attrib TOC fields. | |
| 2723 m1->_const_toc_offset = -1; | |
| 2724 m2->_const_toc_offset_hi_node = m1; | |
| 2725 | |
| 2726 // Register allocation for new nodes. | |
| 2727 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); | |
| 2728 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); | |
| 2729 | |
| 2730 nodes->push(m1); | |
| 2731 nodes->push(m2); | |
| 2732 assert(m2->bottom_type()->isa_ptr(), "must be ptr"); | |
| 2733 } else { | |
| 2734 loadConPNode *m2 = new (C) loadConPNode(); | |
| 2735 | |
| 2736 // inputs for new nodes | |
| 2737 m2->add_req(NULL, n_toc); | |
| 2738 | |
| 2739 // operands for new nodes | |
| 2740 m2->_opnds[0] = new (C) iRegPdstOper(); // dst | |
| 2741 m2->_opnds[1] = op_src; // src | |
| 2742 m2->_opnds[2] = new (C) iRegPdstOper(); // toc | |
| 2743 | |
| 2744 // Register allocation for new nodes. | |
| 2745 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); | |
| 2746 | |
| 2747 nodes->push(m2); | |
| 2748 assert(m2->bottom_type()->isa_ptr(), "must be ptr"); | |
| 2749 } | |
| 2750 %} | |
| 2751 | |
| 2752 // Enc_class needed as consttanttablebase is not supported by postalloc | |
| 2753 // expand. | |
| 2754 enc_class postalloc_expand_load_float_constant(regF dst, immF src, iRegLdst toc) %{ | |
| 2755 bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000; | |
| 2756 | |
| 2757 MachNode *m2; | |
| 2758 if (large_constant_pool) { | |
| 2759 m2 = new (C) loadConFCompNode(); | |
| 2760 } else { | |
| 2761 m2 = new (C) loadConFNode(); | |
| 2762 } | |
| 2763 // inputs for new nodes | |
| 2764 m2->add_req(NULL, n_toc); | |
| 2765 | |
| 2766 // operands for new nodes | |
| 2767 m2->_opnds[0] = op_dst; | |
| 2768 m2->_opnds[1] = op_src; | |
| 2769 m2->_opnds[2] = new (C) iRegPdstOper(); // constanttablebase | |
| 2770 | |
| 2771 // register allocation for new nodes | |
| 2772 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); | |
| 2773 nodes->push(m2); | |
| 2774 %} | |
| 2775 | |
| 2776 // Enc_class needed as consttanttablebase is not supported by postalloc | |
| 2777 // expand. | |
| 2778 enc_class postalloc_expand_load_double_constant(regD dst, immD src, iRegLdst toc) %{ | |
| 2779 bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000; | |
| 2780 | |
| 2781 MachNode *m2; | |
| 2782 if (large_constant_pool) { | |
| 2783 m2 = new (C) loadConDCompNode(); | |
| 2784 } else { | |
| 2785 m2 = new (C) loadConDNode(); | |
| 2786 } | |
| 2787 // inputs for new nodes | |
| 2788 m2->add_req(NULL, n_toc); | |
| 2789 | |
| 2790 // operands for new nodes | |
| 2791 m2->_opnds[0] = op_dst; | |
| 2792 m2->_opnds[1] = op_src; | |
| 2793 m2->_opnds[2] = new (C) iRegPdstOper(); // constanttablebase | |
| 2794 | |
| 2795 // register allocation for new nodes | |
| 2796 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); | |
| 2797 nodes->push(m2); | |
| 2798 %} | |
| 2799 | |
| 2800 enc_class enc_stw(iRegIsrc src, memory mem) %{ | |
| 2801 // TODO: PPC port $archOpcode(ppc64Opcode_stw); | |
| 2802 MacroAssembler _masm(&cbuf); | |
| 2803 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); | |
| 2804 __ stw($src$$Register, Idisp, $mem$$base$$Register); | |
| 2805 %} | |
| 2806 | |
| 2807 enc_class enc_std(iRegIsrc src, memoryAlg4 mem) %{ | |
| 2808 // TODO: PPC port $archOpcode(ppc64Opcode_std); | |
| 2809 MacroAssembler _masm(&cbuf); | |
| 2810 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); | |
| 2811 // Operand 'ds' requires 4-alignment. | |
| 2812 assert((Idisp & 0x3) == 0, "unaligned offset"); | |
| 2813 __ std($src$$Register, Idisp, $mem$$base$$Register); | |
| 2814 %} | |
| 2815 | |
| 2816 enc_class enc_stfs(RegF src, memory mem) %{ | |
| 2817 // TODO: PPC port $archOpcode(ppc64Opcode_stfs); | |
| 2818 MacroAssembler _masm(&cbuf); | |
| 2819 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); | |
| 2820 __ stfs($src$$FloatRegister, Idisp, $mem$$base$$Register); | |
| 2821 %} | |
| 2822 | |
| 2823 enc_class enc_stfd(RegF src, memory mem) %{ | |
| 2824 // TODO: PPC port $archOpcode(ppc64Opcode_stfd); | |
| 2825 MacroAssembler _masm(&cbuf); | |
| 2826 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); | |
| 2827 __ stfd($src$$FloatRegister, Idisp, $mem$$base$$Register); | |
| 2828 %} | |
| 2829 | |
| 2830 // Use release_store for card-marking to ensure that previous | |
| 2831 // oop-stores are visible before the card-mark change. | |
| 2832 enc_class enc_cms_card_mark(memory mem, iRegLdst releaseFieldAddr) %{ | |
| 2833 // TODO: PPC port $archOpcode(ppc64Opcode_compound); | |
| 2834 // FIXME: Implement this as a cmove and use a fixed condition code | |
| 2835 // register which is written on every transition to compiled code, | |
| 2836 // e.g. in call-stub and when returning from runtime stubs. | |
| 2837 // | |
| 2838 // Proposed code sequence for the cmove implementation: | |
| 2839 // | |
| 2840 // Label skip_release; | |
| 2841 // __ beq(CCRfixed, skip_release); | |
| 2842 // __ release(); | |
| 2843 // __ bind(skip_release); | |
| 2844 // __ stb(card mark); | |
| 2845 | |
| 2846 MacroAssembler _masm(&cbuf); | |
| 2847 Label skip_storestore; | |
| 2848 | |
| 2849 #if 0 // TODO: PPC port | |
| 2850 // Check CMSCollectorCardTableModRefBSExt::_requires_release and do the | |
| 2851 // StoreStore barrier conditionally. | |
| 2852 __ lwz(R0, 0, $releaseFieldAddr$$Register); | |
| 2853 __ cmpwi(CCR0, R0, 0); | |
| 17793 | 2854 __ beq_predict_taken(CCR0, skip_storestore); |
| 14445 | 2855 #endif |
| 2856 __ li(R0, 0); | |
| 2857 __ membar(Assembler::StoreStore); | |
| 2858 #if 0 // TODO: PPC port | |
| 2859 __ bind(skip_storestore); | |
| 2860 #endif | |
| 2861 | |
| 2862 // Do the store. | |
| 2863 if ($mem$$index == 0) { | |
| 2864 __ stb(R0, $mem$$disp, $mem$$base$$Register); | |
| 2865 } else { | |
| 2866 assert(0 == $mem$$disp, "no displacement possible with indexed load/stores on ppc"); | |
| 2867 __ stbx(R0, $mem$$base$$Register, $mem$$index$$Register); | |
| 2868 } | |
| 2869 %} | |
| 2870 | |
| 2871 enc_class postalloc_expand_encode_oop(iRegNdst dst, iRegPdst src, flagsReg crx) %{ | |
| 2872 | |
| 2873 if (VM_Version::has_isel()) { | |
| 2874 // use isel instruction with Power 7 | |
| 2875 cmpP_reg_imm16Node *n_compare = new (C) cmpP_reg_imm16Node(); | |
| 2876 encodeP_subNode *n_sub_base = new (C) encodeP_subNode(); | |
| 2877 encodeP_shiftNode *n_shift = new (C) encodeP_shiftNode(); | |
| 2878 cond_set_0_oopNode *n_cond_set = new (C) cond_set_0_oopNode(); | |
| 2879 | |
| 2880 n_compare->add_req(n_region, n_src); | |
| 2881 n_compare->_opnds[0] = op_crx; | |
| 2882 n_compare->_opnds[1] = op_src; | |
| 2883 n_compare->_opnds[2] = new (C) immL16Oper(0); | |
| 2884 | |
| 2885 n_sub_base->add_req(n_region, n_src); | |
| 2886 n_sub_base->_opnds[0] = op_dst; | |
| 2887 n_sub_base->_opnds[1] = op_src; | |
| 2888 n_sub_base->_bottom_type = _bottom_type; | |
| 2889 | |
| 2890 n_shift->add_req(n_region, n_sub_base); | |
| 2891 n_shift->_opnds[0] = op_dst; | |
| 2892 n_shift->_opnds[1] = op_dst; | |
| 2893 n_shift->_bottom_type = _bottom_type; | |
| 2894 | |
| 2895 n_cond_set->add_req(n_region, n_compare, n_shift); | |
| 2896 n_cond_set->_opnds[0] = op_dst; | |
| 2897 n_cond_set->_opnds[1] = op_crx; | |
| 2898 n_cond_set->_opnds[2] = op_dst; | |
| 2899 n_cond_set->_bottom_type = _bottom_type; | |
| 2900 | |
| 2901 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx)); | |
| 2902 ra_->set_pair(n_sub_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); | |
| 2903 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); | |
| 2904 ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); | |
| 2905 | |
| 2906 nodes->push(n_compare); | |
| 2907 nodes->push(n_sub_base); | |
| 2908 nodes->push(n_shift); | |
| 2909 nodes->push(n_cond_set); | |
| 2910 | |
| 2911 } else { | |
| 2912 // before Power 7 | |
| 2913 moveRegNode *n_move = new (C) moveRegNode(); | |
| 2914 cmpP_reg_imm16Node *n_compare = new (C) cmpP_reg_imm16Node(); | |
| 2915 encodeP_shiftNode *n_shift = new (C) encodeP_shiftNode(); | |
| 2916 cond_sub_baseNode *n_sub_base = new (C) cond_sub_baseNode(); | |
| 2917 | |
| 2918 n_move->add_req(n_region, n_src); | |
| 2919 n_move->_opnds[0] = op_dst; | |
| 2920 n_move->_opnds[1] = op_src; | |
| 2921 ra_->set_oop(n_move, true); // Until here, 'n_move' still produces an oop. | |
| 2922 | |
| 2923 n_compare->add_req(n_region, n_src); | |
| 2924 n_compare->add_prec(n_move); | |
| 2925 | |
| 2926 n_compare->_opnds[0] = op_crx; | |
| 2927 n_compare->_opnds[1] = op_src; | |
| 2928 n_compare->_opnds[2] = new (C) immL16Oper(0); | |
| 2929 | |
| 2930 n_sub_base->add_req(n_region, n_compare, n_src); | |
| 2931 n_sub_base->_opnds[0] = op_dst; | |
| 2932 n_sub_base->_opnds[1] = op_crx; | |
| 2933 n_sub_base->_opnds[2] = op_src; | |
| 2934 n_sub_base->_bottom_type = _bottom_type; | |
| 2935 | |
| 2936 n_shift->add_req(n_region, n_sub_base); | |
| 2937 n_shift->_opnds[0] = op_dst; | |
| 2938 n_shift->_opnds[1] = op_dst; | |
| 2939 n_shift->_bottom_type = _bottom_type; | |
| 2940 | |
| 2941 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); | |
| 2942 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx)); | |
| 2943 ra_->set_pair(n_sub_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); | |
| 2944 ra_->set_pair(n_move->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); | |
| 2945 | |
| 2946 nodes->push(n_move); | |
| 2947 nodes->push(n_compare); | |
| 2948 nodes->push(n_sub_base); | |
| 2949 nodes->push(n_shift); | |
| 2950 } | |
| 2951 | |
| 2952 assert(!(ra_->is_oop(this)), "sanity"); // This is not supposed to be GC'ed. | |
| 2953 %} | |
| 2954 | |
| 2955 enc_class postalloc_expand_encode_oop_not_null(iRegNdst dst, iRegPdst src) %{ | |
| 2956 | |
| 2957 encodeP_subNode *n1 = new (C) encodeP_subNode(); | |
| 2958 n1->add_req(n_region, n_src); | |
| 2959 n1->_opnds[0] = op_dst; | |
| 2960 n1->_opnds[1] = op_src; | |
| 2961 n1->_bottom_type = _bottom_type; | |
| 2962 | |
| 2963 encodeP_shiftNode *n2 = new (C) encodeP_shiftNode(); | |
| 2964 n2->add_req(n_region, n1); | |
| 2965 n2->_opnds[0] = op_dst; | |
| 2966 n2->_opnds[1] = op_dst; | |
| 2967 n2->_bottom_type = _bottom_type; | |
| 2968 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); | |
| 2969 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); | |
| 2970 | |
| 2971 nodes->push(n1); | |
| 2972 nodes->push(n2); | |
| 2973 assert(!(ra_->is_oop(this)), "sanity"); // This is not supposed to be GC'ed. | |
| 2974 %} | |
| 2975 | |
| 2976 enc_class postalloc_expand_decode_oop(iRegPdst dst, iRegNsrc src, flagsReg crx) %{ | |
| 2977 decodeN_shiftNode *n_shift = new (C) decodeN_shiftNode(); | |
| 2978 cmpN_reg_imm0Node *n_compare = new (C) cmpN_reg_imm0Node(); | |
| 2979 | |
| 2980 n_compare->add_req(n_region, n_src); | |
| 2981 n_compare->_opnds[0] = op_crx; | |
| 2982 n_compare->_opnds[1] = op_src; | |
| 2983 n_compare->_opnds[2] = new (C) immN_0Oper(TypeNarrowOop::NULL_PTR); | |
| 2984 | |
| 2985 n_shift->add_req(n_region, n_src); | |
| 2986 n_shift->_opnds[0] = op_dst; | |
| 2987 n_shift->_opnds[1] = op_src; | |
| 2988 n_shift->_bottom_type = _bottom_type; | |
| 2989 | |
| 2990 if (VM_Version::has_isel()) { | |
| 2991 // use isel instruction with Power 7 | |
| 2992 | |
| 2993 decodeN_addNode *n_add_base = new (C) decodeN_addNode(); | |
| 2994 n_add_base->add_req(n_region, n_shift); | |
| 2995 n_add_base->_opnds[0] = op_dst; | |
| 2996 n_add_base->_opnds[1] = op_dst; | |
| 2997 n_add_base->_bottom_type = _bottom_type; | |
| 2998 | |
| 2999 cond_set_0_ptrNode *n_cond_set = new (C) cond_set_0_ptrNode(); | |
| 3000 n_cond_set->add_req(n_region, n_compare, n_add_base); | |
| 3001 n_cond_set->_opnds[0] = op_dst; | |
| 3002 n_cond_set->_opnds[1] = op_crx; | |
| 3003 n_cond_set->_opnds[2] = op_dst; | |
| 3004 n_cond_set->_bottom_type = _bottom_type; | |
| 3005 | |
| 3006 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!"); | |
| 3007 ra_->set_oop(n_cond_set, true); | |
| 3008 | |
| 3009 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); | |
| 3010 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx)); | |
| 3011 ra_->set_pair(n_add_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); | |
| 3012 ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); | |
| 3013 | |
| 3014 nodes->push(n_compare); | |
| 3015 nodes->push(n_shift); | |
| 3016 nodes->push(n_add_base); | |
| 3017 nodes->push(n_cond_set); | |
| 3018 | |
| 3019 } else { | |
| 3020 // before Power 7 | |
| 3021 cond_add_baseNode *n_add_base = new (C) cond_add_baseNode(); | |
| 3022 | |
| 3023 n_add_base->add_req(n_region, n_compare, n_shift); | |
| 3024 n_add_base->_opnds[0] = op_dst; | |
| 3025 n_add_base->_opnds[1] = op_crx; | |
| 3026 n_add_base->_opnds[2] = op_dst; | |
| 3027 n_add_base->_bottom_type = _bottom_type; | |
| 3028 | |
| 3029 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!"); | |
| 3030 ra_->set_oop(n_add_base, true); | |
| 3031 | |
| 3032 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); | |
| 3033 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx)); | |
| 3034 ra_->set_pair(n_add_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); | |
| 3035 | |
| 3036 nodes->push(n_compare); | |
| 3037 nodes->push(n_shift); | |
| 3038 nodes->push(n_add_base); | |
| 3039 } | |
| 3040 %} | |
| 3041 | |
| 3042 enc_class postalloc_expand_decode_oop_not_null(iRegPdst dst, iRegNsrc src) %{ | |
| 3043 decodeN_shiftNode *n1 = new (C) decodeN_shiftNode(); | |
| 3044 n1->add_req(n_region, n_src); | |
| 3045 n1->_opnds[0] = op_dst; | |
| 3046 n1->_opnds[1] = op_src; | |
| 3047 n1->_bottom_type = _bottom_type; | |
| 3048 | |
| 3049 decodeN_addNode *n2 = new (C) decodeN_addNode(); | |
| 3050 n2->add_req(n_region, n1); | |
| 3051 n2->_opnds[0] = op_dst; | |
| 3052 n2->_opnds[1] = op_dst; | |
| 3053 n2->_bottom_type = _bottom_type; | |
| 3054 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); | |
| 3055 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); | |
| 3056 | |
| 3057 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!"); | |
| 3058 ra_->set_oop(n2, true); | |
| 3059 | |
| 3060 nodes->push(n1); | |
| 3061 nodes->push(n2); | |
| 3062 %} | |
| 3063 | |
| 3064 enc_class enc_cmove_reg(iRegIdst dst, flagsReg crx, iRegIsrc src, cmpOp cmp) %{ | |
| 3065 // TODO: PPC port $archOpcode(ppc64Opcode_cmove); | |
| 3066 | |
| 3067 MacroAssembler _masm(&cbuf); | |
| 3068 int cc = $cmp$$cmpcode; | |
| 3069 int flags_reg = $crx$$reg; | |
| 3070 Label done; | |
| 3071 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding"); | |
| 3072 // Branch if not (cmp crx). | |
| 3073 __ bc(cc_to_inverse_boint(cc), cc_to_biint(cc, flags_reg), done); | |
| 3074 __ mr($dst$$Register, $src$$Register); | |
| 3075 // TODO PPC port __ endgroup_if_needed(_size == 12); | |
| 3076 __ bind(done); | |
| 3077 %} | |
| 3078 | |
| 3079 enc_class enc_cmove_imm(iRegIdst dst, flagsReg crx, immI16 src, cmpOp cmp) %{ | |
| 3080 // TODO: PPC port $archOpcode(ppc64Opcode_cmove); | |
| 3081 | |
| 3082 MacroAssembler _masm(&cbuf); | |
| 3083 Label done; | |
| 3084 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding"); | |
| 3085 // Branch if not (cmp crx). | |
| 3086 __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done); | |
| 3087 __ li($dst$$Register, $src$$constant); | |
| 3088 // TODO PPC port __ endgroup_if_needed(_size == 12); | |
| 3089 __ bind(done); | |
| 3090 %} | |
| 3091 | |
| 3092 // New atomics. | |
| 3093 enc_class enc_GetAndAddI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{ | |
| 3094 // TODO: PPC port $archOpcode(ppc64Opcode_compound); | |
| 3095 | |
| 3096 MacroAssembler _masm(&cbuf); | |
| 3097 Register Rtmp = R0; | |
| 3098 Register Rres = $res$$Register; | |
| 3099 Register Rsrc = $src$$Register; | |
| 3100 Register Rptr = $mem_ptr$$Register; | |
| 3101 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr); | |
| 3102 Register Rold = RegCollision ? Rtmp : Rres; | |
| 3103 | |
| 3104 Label Lretry; | |
| 3105 __ bind(Lretry); | |
| 3106 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update()); | |
| 3107 __ add(Rtmp, Rsrc, Rold); | |
| 3108 __ stwcx_(Rtmp, Rptr); | |
| 3109 if (UseStaticBranchPredictionInCompareAndSwapPPC64) { | |
| 3110 __ bne_predict_not_taken(CCR0, Lretry); | |
| 3111 } else { | |
| 3112 __ bne( CCR0, Lretry); | |
| 3113 } | |
| 3114 if (RegCollision) __ subf(Rres, Rsrc, Rtmp); | |
| 3115 __ fence(); | |
| 3116 %} | |
| 3117 | |
| 3118 enc_class enc_GetAndAddL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{ | |
| 3119 // TODO: PPC port $archOpcode(ppc64Opcode_compound); | |
| 3120 | |
| 3121 MacroAssembler _masm(&cbuf); | |
| 3122 Register Rtmp = R0; | |
| 3123 Register Rres = $res$$Register; | |
| 3124 Register Rsrc = $src$$Register; | |
| 3125 Register Rptr = $mem_ptr$$Register; | |
| 3126 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr); | |
| 3127 Register Rold = RegCollision ? Rtmp : Rres; | |
| 3128 | |
| 3129 Label Lretry; | |
| 3130 __ bind(Lretry); | |
| 3131 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update()); | |
| 3132 __ add(Rtmp, Rsrc, Rold); | |
| 3133 __ stdcx_(Rtmp, Rptr); | |
| 3134 if (UseStaticBranchPredictionInCompareAndSwapPPC64) { | |
| 3135 __ bne_predict_not_taken(CCR0, Lretry); | |
| 3136 } else { | |
| 3137 __ bne( CCR0, Lretry); | |
| 3138 } | |
| 3139 if (RegCollision) __ subf(Rres, Rsrc, Rtmp); | |
| 3140 __ fence(); | |
| 3141 %} | |
| 3142 | |
| 3143 enc_class enc_GetAndSetI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{ | |
| 3144 // TODO: PPC port $archOpcode(ppc64Opcode_compound); | |
| 3145 | |
| 3146 MacroAssembler _masm(&cbuf); | |
| 3147 Register Rtmp = R0; | |
| 3148 Register Rres = $res$$Register; | |
| 3149 Register Rsrc = $src$$Register; | |
| 3150 Register Rptr = $mem_ptr$$Register; | |
| 3151 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr); | |
| 3152 Register Rold = RegCollision ? Rtmp : Rres; | |
| 3153 | |
| 3154 Label Lretry; | |
| 3155 __ bind(Lretry); | |
| 3156 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update()); | |
| 3157 __ stwcx_(Rsrc, Rptr); | |
| 3158 if (UseStaticBranchPredictionInCompareAndSwapPPC64) { | |
| 3159 __ bne_predict_not_taken(CCR0, Lretry); | |
| 3160 } else { | |
| 3161 __ bne( CCR0, Lretry); | |
| 3162 } | |
| 3163 if (RegCollision) __ mr(Rres, Rtmp); | |
| 3164 __ fence(); | |
| 3165 %} | |
| 3166 | |
| 3167 enc_class enc_GetAndSetL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{ | |
| 3168 // TODO: PPC port $archOpcode(ppc64Opcode_compound); | |
| 3169 | |
| 3170 MacroAssembler _masm(&cbuf); | |
| 3171 Register Rtmp = R0; | |
| 3172 Register Rres = $res$$Register; | |
| 3173 Register Rsrc = $src$$Register; | |
| 3174 Register Rptr = $mem_ptr$$Register; | |
| 3175 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr); | |
| 3176 Register Rold = RegCollision ? Rtmp : Rres; | |
| 3177 | |
| 3178 Label Lretry; | |
| 3179 __ bind(Lretry); | |
| 3180 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update()); | |
| 3181 __ stdcx_(Rsrc, Rptr); | |
| 3182 if (UseStaticBranchPredictionInCompareAndSwapPPC64) { | |
| 3183 __ bne_predict_not_taken(CCR0, Lretry); | |
| 3184 } else { | |
| 3185 __ bne( CCR0, Lretry); | |
| 3186 } | |
| 3187 if (RegCollision) __ mr(Rres, Rtmp); | |
| 3188 __ fence(); | |
| 3189 %} | |
| 3190 | |
| 3191 // This enc_class is needed so that scheduler gets proper | |
| 3192 // input mapping for latency computation. | |
| 3193 enc_class enc_andc(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ | |
| 3194 // TODO: PPC port $archOpcode(ppc64Opcode_andc); | |
| 3195 MacroAssembler _masm(&cbuf); | |
| 3196 __ andc($dst$$Register, $src1$$Register, $src2$$Register); | |
| 3197 %} | |
| 3198 | |
| 3199 enc_class enc_convI2B_regI__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx, immI16 zero, immI16 notzero) %{ | |
| 3200 // TODO: PPC port $archOpcode(ppc64Opcode_compound); | |
| 3201 | |
| 3202 MacroAssembler _masm(&cbuf); | |
| 3203 | |
| 3204 Label done; | |
| 3205 __ cmpwi($crx$$CondRegister, $src$$Register, 0); | |
| 3206 __ li($dst$$Register, $zero$$constant); | |
| 3207 __ beq($crx$$CondRegister, done); | |
| 3208 __ li($dst$$Register, $notzero$$constant); | |
| 3209 __ bind(done); | |
| 3210 %} | |
| 3211 | |
| 3212 enc_class enc_convP2B_regP__cmove(iRegIdst dst, iRegPsrc src, flagsReg crx, immI16 zero, immI16 notzero) %{ | |
| 3213 // TODO: PPC port $archOpcode(ppc64Opcode_compound); | |
| 3214 | |
| 3215 MacroAssembler _masm(&cbuf); | |
| 3216 | |
| 3217 Label done; | |
| 3218 __ cmpdi($crx$$CondRegister, $src$$Register, 0); | |
| 3219 __ li($dst$$Register, $zero$$constant); | |
| 3220 __ beq($crx$$CondRegister, done); | |
| 3221 __ li($dst$$Register, $notzero$$constant); | |
| 3222 __ bind(done); | |
| 3223 %} | |
| 3224 | |
| 3225 enc_class enc_cmove_bso_stackSlotL(iRegLdst dst, flagsReg crx, stackSlotL mem ) %{ | |
| 3226 // TODO: PPC port $archOpcode(ppc64Opcode_cmove); | |
| 3227 | |
| 3228 MacroAssembler _masm(&cbuf); | |
| 3229 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); | |
| 3230 Label done; | |
| 3231 __ bso($crx$$CondRegister, done); | |
| 3232 __ ld($dst$$Register, Idisp, $mem$$base$$Register); | |
| 3233 // TODO PPC port __ endgroup_if_needed(_size == 12); | |
| 3234 __ bind(done); | |
| 3235 %} | |
| 3236 | |
| 3237 enc_class enc_bc(flagsReg crx, cmpOp cmp, Label lbl) %{ | |
| 3238 // TODO: PPC port $archOpcode(ppc64Opcode_bc); | |
| 3239 | |
| 3240 MacroAssembler _masm(&cbuf); | |
| 3241 Label d; // dummy | |
| 3242 __ bind(d); | |
| 3243 Label* p = ($lbl$$label); | |
| 3244 // `p' is `NULL' when this encoding class is used only to | |
| 3245 // determine the size of the encoded instruction. | |
| 3246 Label& l = (NULL == p)? d : *(p); | |
| 3247 int cc = $cmp$$cmpcode; | |
| 3248 int flags_reg = $crx$$reg; | |
| 3249 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding"); | |
| 3250 int bhint = Assembler::bhintNoHint; | |
| 3251 | |
| 3252 if (UseStaticBranchPredictionForUncommonPathsPPC64) { | |
| 3253 if (_prob <= PROB_NEVER) { | |
| 3254 bhint = Assembler::bhintIsNotTaken; | |
| 3255 } else if (_prob >= PROB_ALWAYS) { | |
| 3256 bhint = Assembler::bhintIsTaken; | |
| 3257 } | |
| 3258 } | |
| 3259 | |
| 3260 __ bc(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)), | |
| 3261 cc_to_biint(cc, flags_reg), | |
| 3262 l); | |
| 3263 %} | |
| 3264 | |
| 3265 enc_class enc_bc_far(flagsReg crx, cmpOp cmp, Label lbl) %{ | |
| 3266 // The scheduler doesn't know about branch shortening, so we set the opcode | |
| 3267 // to ppc64Opcode_bc in order to hide this detail from the scheduler. | |
| 3268 // TODO: PPC port $archOpcode(ppc64Opcode_bc); | |
| 3269 | |
| 3270 MacroAssembler _masm(&cbuf); | |
| 3271 Label d; // dummy | |
| 3272 __ bind(d); | |
| 3273 Label* p = ($lbl$$label); | |
| 3274 // `p' is `NULL' when this encoding class is used only to | |
| 3275 // determine the size of the encoded instruction. | |
| 3276 Label& l = (NULL == p)? d : *(p); | |
| 3277 int cc = $cmp$$cmpcode; | |
| 3278 int flags_reg = $crx$$reg; | |
| 3279 int bhint = Assembler::bhintNoHint; | |
| 3280 | |
| 3281 if (UseStaticBranchPredictionForUncommonPathsPPC64) { | |
| 3282 if (_prob <= PROB_NEVER) { | |
| 3283 bhint = Assembler::bhintIsNotTaken; | |
| 3284 } else if (_prob >= PROB_ALWAYS) { | |
| 3285 bhint = Assembler::bhintIsTaken; | |
| 3286 } | |
| 3287 } | |
| 3288 | |
| 3289 // Tell the conditional far branch to optimize itself when being relocated. | |
| 3290 __ bc_far(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)), | |
| 3291 cc_to_biint(cc, flags_reg), | |
| 3292 l, | |
| 3293 MacroAssembler::bc_far_optimize_on_relocate); | |
| 3294 %} | |
| 3295 | |
| 3296 // Branch used with Power6 scheduling (can be shortened without changing the node). | |
| 3297 enc_class enc_bc_short_far(flagsReg crx, cmpOp cmp, Label lbl) %{ | |
| 3298 // The scheduler doesn't know about branch shortening, so we set the opcode | |
| 3299 // to ppc64Opcode_bc in order to hide this detail from the scheduler. | |
| 3300 // TODO: PPC port $archOpcode(ppc64Opcode_bc); | |
| 3301 | |
| 3302 MacroAssembler _masm(&cbuf); | |
| 3303 Label d; // dummy | |
| 3304 __ bind(d); | |
| 3305 Label* p = ($lbl$$label); | |
| 3306 // `p' is `NULL' when this encoding class is used only to | |
| 3307 // determine the size of the encoded instruction. | |
| 3308 Label& l = (NULL == p)? d : *(p); | |
| 3309 int cc = $cmp$$cmpcode; | |
| 3310 int flags_reg = $crx$$reg; | |
| 3311 int bhint = Assembler::bhintNoHint; | |
| 3312 | |
| 3313 if (UseStaticBranchPredictionForUncommonPathsPPC64) { | |
| 3314 if (_prob <= PROB_NEVER) { | |
| 3315 bhint = Assembler::bhintIsNotTaken; | |
| 3316 } else if (_prob >= PROB_ALWAYS) { | |
| 3317 bhint = Assembler::bhintIsTaken; | |
| 3318 } | |
| 3319 } | |
| 3320 | |
| 3321 #if 0 // TODO: PPC port | |
| 3322 if (_size == 8) { | |
| 3323 // Tell the conditional far branch to optimize itself when being relocated. | |
| 3324 __ bc_far(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)), | |
| 3325 cc_to_biint(cc, flags_reg), | |
| 3326 l, | |
| 3327 MacroAssembler::bc_far_optimize_on_relocate); | |
| 3328 } else { | |
| 3329 __ bc (Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)), | |
| 3330 cc_to_biint(cc, flags_reg), | |
| 3331 l); | |
| 3332 } | |
| 3333 #endif | |
| 3334 Unimplemented(); | |
| 3335 %} | |
| 3336 | |
| 3337 // Postalloc expand emitter for loading a replicatef float constant from | |
| 3338 // the method's TOC. | |
| 3339 // Enc_class needed as consttanttablebase is not supported by postalloc | |
| 3340 // expand. | |
| 3341 enc_class postalloc_expand_load_replF_constant(iRegLdst dst, immF src, iRegLdst toc) %{ | |
| 3342 // Create new nodes. | |
| 3343 | |
| 3344 // Make an operand with the bit pattern to load as float. | |
| 3345 immLOper *op_repl = new (C) immLOper((jlong)replicate_immF(op_src->constantF())); | |
| 3346 | |
| 3347 loadConLNodesTuple loadConLNodes = | |
| 3348 loadConLNodesTuple_create(C, ra_, n_toc, op_repl, | |
| 3349 ra_->get_reg_second(this), ra_->get_reg_first(this)); | |
| 3350 | |
| 3351 // Push new nodes. | |
| 3352 if (loadConLNodes._large_hi) nodes->push(loadConLNodes._large_hi); | |
| 3353 if (loadConLNodes._last) nodes->push(loadConLNodes._last); | |
| 3354 | |
| 3355 assert(nodes->length() >= 1, "must have created at least 1 node"); | |
| 3356 assert(loadConLNodes._last->bottom_type()->isa_long(), "must be long"); | |
| 3357 %} | |
| 3358 | |
| 3359 // This enc_class is needed so that scheduler gets proper | |
| 3360 // input mapping for latency computation. | |
| 3361 enc_class enc_poll(immI dst, iRegLdst poll) %{ | |
| 3362 // TODO: PPC port $archOpcode(ppc64Opcode_ld); | |
| 3363 // Fake operand dst needed for PPC scheduler. | |
| 3364 assert($dst$$constant == 0x0, "dst must be 0x0"); | |
| 3365 | |
| 3366 MacroAssembler _masm(&cbuf); | |
| 3367 // Mark the code position where the load from the safepoint | |
| 3368 // polling page was emitted as relocInfo::poll_type. | |
| 3369 __ relocate(relocInfo::poll_type); | |
| 3370 __ load_from_polling_page($poll$$Register); | |
| 3371 %} | |
| 3372 | |
| 3373 // A Java static call or a runtime call. | |
| 3374 // | |
| 3375 // Branch-and-link relative to a trampoline. | |
| 3376 // The trampoline loads the target address and does a long branch to there. | |
| 3377 // In case we call java, the trampoline branches to a interpreter_stub | |
| 3378 // which loads the inline cache and the real call target from the constant pool. | |
| 3379 // | |
| 3380 // This basically looks like this: | |
| 3381 // | |
| 3382 // >>>> consts -+ -+ | |
| 3383 // | |- offset1 | |
| 3384 // [call target1] | <-+ | |
| 3385 // [IC cache] |- offset2 | |
| 3386 // [call target2] <--+ | |
| 3387 // | |
| 3388 // <<<< consts | |
| 3389 // >>>> insts | |
| 3390 // | |
| 3391 // bl offset16 -+ -+ ??? // How many bits available? | |
| 3392 // | | | |
| 3393 // <<<< insts | | | |
| 3394 // >>>> stubs | | | |
| 3395 // | |- trampoline_stub_Reloc | |
| 3396 // trampoline stub: | <-+ | |
| 3397 // r2 = toc | | |
| 3398 // r2 = [r2 + offset1] | // Load call target1 from const section | |
| 3399 // mtctr r2 | | |
| 3400 // bctr |- static_stub_Reloc | |
| 3401 // comp_to_interp_stub: <---+ | |
| 3402 // r1 = toc | |
| 3403 // ICreg = [r1 + IC_offset] // Load IC from const section | |
| 3404 // r1 = [r1 + offset2] // Load call target2 from const section | |
| 3405 // mtctr r1 | |
| 3406 // bctr | |
| 3407 // | |
| 3408 // <<<< stubs | |
| 3409 // | |
| 3410 // The call instruction in the code either | |
| 3411 // - Branches directly to a compiled method if the offset is encodable in instruction. | |
| 3412 // - Branches to the trampoline stub if the offset to the compiled method is not encodable. | |
| 3413 // - Branches to the compiled_to_interp stub if the target is interpreted. | |
| 3414 // | |
| 3415 // Further there are three relocations from the loads to the constants in | |
| 3416 // the constant section. | |
| 3417 // | |
| 3418 // Usage of r1 and r2 in the stubs allows to distinguish them. | |
| 3419 enc_class enc_java_static_call(method meth) %{ | |
| 3420 // TODO: PPC port $archOpcode(ppc64Opcode_bl); | |
| 3421 | |
| 3422 MacroAssembler _masm(&cbuf); | |
| 3423 address entry_point = (address)$meth$$method; | |
| 3424 | |
| 3425 if (!_method) { | |
| 3426 // A call to a runtime wrapper, e.g. new, new_typeArray_Java, uncommon_trap. | |
| 3427 emit_call_with_trampoline_stub(_masm, entry_point, relocInfo::runtime_call_type); | |
| 3428 } else { | |
| 3429 // Remember the offset not the address. | |
| 3430 const int start_offset = __ offset(); | |
| 3431 // The trampoline stub. | |
| 3432 if (!Compile::current()->in_scratch_emit_size()) { | |
| 3433 // No entry point given, use the current pc. | |
| 3434 // Make sure branch fits into | |
| 3435 if (entry_point == 0) entry_point = __ pc(); | |
| 3436 | |
| 3437 // Put the entry point as a constant into the constant pool. | |
| 3438 const address entry_point_toc_addr = __ address_constant(entry_point, RelocationHolder::none); | |
| 3439 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr); | |
| 3440 | |
| 3441 // Emit the trampoline stub which will be related to the branch-and-link below. | |
| 3442 emit_trampoline_stub(_masm, entry_point_toc_offset, start_offset); | |
| 3443 __ relocate(_optimized_virtual ? | |
| 3444 relocInfo::opt_virtual_call_type : relocInfo::static_call_type); | |
| 3445 } | |
| 3446 | |
| 3447 // The real call. | |
| 3448 // Note: At this point we do not have the address of the trampoline | |
| 3449 // stub, and the entry point might be too far away for bl, so __ pc() | |
| 3450 // serves as dummy and the bl will be patched later. | |
| 3451 cbuf.set_insts_mark(); | |
| 3452 __ bl(__ pc()); // Emits a relocation. | |
| 3453 | |
| 3454 // The stub for call to interpreter. | |
| 3455 CompiledStaticCall::emit_to_interp_stub(cbuf); | |
| 3456 } | |
| 3457 %} | |
| 3458 | |
| 3459 // Emit a method handle call. | |
| 3460 // | |
| 3461 // Method handle calls from compiled to compiled are going thru a | |
| 3462 // c2i -> i2c adapter, extending the frame for their arguments. The | |
| 3463 // caller however, returns directly to the compiled callee, that has | |
| 3464 // to cope with the extended frame. We restore the original frame by | |
| 3465 // loading the callers sp and adding the calculated framesize. | |
| 3466 enc_class enc_java_handle_call(method meth) %{ | |
| 3467 // TODO: PPC port $archOpcode(ppc64Opcode_compound); | |
| 3468 | |
| 3469 MacroAssembler _masm(&cbuf); | |
| 3470 address entry_point = (address)$meth$$method; | |
| 3471 | |
| 3472 // Remember the offset not the address. | |
| 3473 const int start_offset = __ offset(); | |
| 3474 // The trampoline stub. | |
| 3475 if (!ra_->C->in_scratch_emit_size()) { | |
| 3476 // No entry point given, use the current pc. | |
| 3477 // Make sure branch fits into | |
| 3478 if (entry_point == 0) entry_point = __ pc(); | |
| 3479 | |
| 3480 // Put the entry point as a constant into the constant pool. | |
| 3481 const address entry_point_toc_addr = __ address_constant(entry_point, RelocationHolder::none); | |
| 3482 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr); | |
| 3483 | |
| 3484 // Emit the trampoline stub which will be related to the branch-and-link below. | |
| 3485 emit_trampoline_stub(_masm, entry_point_toc_offset, start_offset); | |
| 3486 assert(_optimized_virtual, "methodHandle call should be a virtual call"); | |
| 3487 __ relocate(relocInfo::opt_virtual_call_type); | |
| 3488 } | |
| 3489 | |
| 3490 // The real call. | |
| 3491 // Note: At this point we do not have the address of the trampoline | |
| 3492 // stub, and the entry point might be too far away for bl, so __ pc() | |
| 3493 // serves as dummy and the bl will be patched later. | |
| 3494 cbuf.set_insts_mark(); | |
| 3495 __ bl(__ pc()); // Emits a relocation. | |
| 3496 | |
| 3497 assert(_method, "execute next statement conditionally"); | |
| 3498 // The stub for call to interpreter. | |
| 3499 CompiledStaticCall::emit_to_interp_stub(cbuf); | |
| 3500 | |
| 3501 // Restore original sp. | |
| 3502 __ ld(R11_scratch1, 0, R1_SP); // Load caller sp. | |
| 3503 const long framesize = ra_->C->frame_slots() << LogBytesPerInt; | |
| 3504 unsigned int bytes = (unsigned int)framesize; | |
| 3505 long offset = Assembler::align_addr(bytes, frame::alignment_in_bytes); | |
| 3506 if (Assembler::is_simm(-offset, 16)) { | |
| 3507 __ addi(R1_SP, R11_scratch1, -offset); | |
| 3508 } else { | |
| 3509 __ load_const_optimized(R12_scratch2, -offset); | |
| 3510 __ add(R1_SP, R11_scratch1, R12_scratch2); | |
| 3511 } | |
| 3512 #ifdef ASSERT | |
| 3513 __ ld(R12_scratch2, 0, R1_SP); // Load from unextended_sp. | |
| 3514 __ cmpd(CCR0, R11_scratch1, R12_scratch2); | |
| 3515 __ asm_assert_eq("backlink changed", 0x8000); | |
| 3516 #endif | |
| 3517 // If fails should store backlink before unextending. | |
| 3518 | |
| 17793 | 3519 if (ra_->C->env()->failing()) { |
| 14445 | 3520 return; |
| 17793 | 3521 } |
| 14445 | 3522 %} |
| 3523 | |
| 3524 // Second node of expanded dynamic call - the call. | |
| 3525 enc_class enc_java_dynamic_call_sched(method meth) %{ | |
| 3526 // TODO: PPC port $archOpcode(ppc64Opcode_bl); | |
| 3527 | |
| 3528 MacroAssembler _masm(&cbuf); | |
| 3529 | |
| 3530 if (!ra_->C->in_scratch_emit_size()) { | |
| 3531 // Create a call trampoline stub for the given method. | |
| 3532 const address entry_point = !($meth$$method) ? 0 : (address)$meth$$method; | |
| 3533 const address entry_point_const = __ address_constant(entry_point, RelocationHolder::none); | |
| 3534 const int entry_point_const_toc_offset = __ offset_to_method_toc(entry_point_const); | |
| 3535 emit_trampoline_stub(_masm, entry_point_const_toc_offset, __ offset()); | |
| 3536 | |
| 3537 if (ra_->C->env()->failing()) | |
| 3538 return; | |
| 3539 | |
| 3540 // Build relocation at call site with ic position as data. | |
| 3541 assert((_load_ic_hi_node != NULL && _load_ic_node == NULL) || | |
| 3542 (_load_ic_hi_node == NULL && _load_ic_node != NULL), | |
| 3543 "must have one, but can't have both"); | |
| 3544 assert((_load_ic_hi_node != NULL && _load_ic_hi_node->_cbuf_insts_offset != -1) || | |
| 3545 (_load_ic_node != NULL && _load_ic_node->_cbuf_insts_offset != -1), | |
| 3546 "must contain instruction offset"); | |
| 3547 const int virtual_call_oop_addr_offset = _load_ic_hi_node != NULL | |
| 3548 ? _load_ic_hi_node->_cbuf_insts_offset | |
| 3549 : _load_ic_node->_cbuf_insts_offset; | |
| 3550 const address virtual_call_oop_addr = __ addr_at(virtual_call_oop_addr_offset); | |
| 3551 assert(MacroAssembler::is_load_const_from_method_toc_at(virtual_call_oop_addr), | |
| 3552 "should be load from TOC"); | |
| 3553 | |
| 3554 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr)); | |
| 3555 } | |
| 3556 | |
| 3557 // At this point I do not have the address of the trampoline stub, | |
| 3558 // and the entry point might be too far away for bl. Pc() serves | |
| 3559 // as dummy and bl will be patched later. | |
| 3560 __ bl((address) __ pc()); | |
| 3561 %} | |
| 3562 | |
| 3563 // postalloc expand emitter for virtual calls. | |
| 3564 enc_class postalloc_expand_java_dynamic_call_sched(method meth, iRegLdst toc) %{ | |
| 3565 | |
| 3566 // Create the nodes for loading the IC from the TOC. | |
| 3567 loadConLNodesTuple loadConLNodes_IC = | |
| 3568 loadConLNodesTuple_create(C, ra_, n_toc, new (C) immLOper((jlong)Universe::non_oop_word()), | |
| 3569 OptoReg::Name(R19_H_num), OptoReg::Name(R19_num)); | |
| 3570 | |
| 3571 // Create the call node. | |
| 3572 CallDynamicJavaDirectSchedNode *call = new (C) CallDynamicJavaDirectSchedNode(); | |
| 3573 call->_method_handle_invoke = _method_handle_invoke; | |
| 3574 call->_vtable_index = _vtable_index; | |
| 3575 call->_method = _method; | |
| 3576 call->_bci = _bci; | |
| 3577 call->_optimized_virtual = _optimized_virtual; | |
| 3578 call->_tf = _tf; | |
| 3579 call->_entry_point = _entry_point; | |
| 3580 call->_cnt = _cnt; | |
| 3581 call->_argsize = _argsize; | |
| 3582 call->_oop_map = _oop_map; | |
| 3583 call->_jvms = _jvms; | |
| 3584 call->_jvmadj = _jvmadj; | |
| 3585 call->_in_rms = _in_rms; | |
| 3586 call->_nesting = _nesting; | |
| 3587 | |
| 3588 // New call needs all inputs of old call. | |
| 3589 // Req... | |
| 3590 for (uint i = 0; i < req(); ++i) { | |
|
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3591 // The expanded node does not need toc any more. |
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3592 // Add the inline cache constant here instead. This expresses the |
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3593 // register of the inline cache must be live at the call. |
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3594 // Else we would have to adapt JVMState by -1. |
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3595 if (i == mach_constant_base_node_input()) { |
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3596 call->add_req(loadConLNodes_IC._last); |
| 14445 | 3597 } else { |
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3598 call->add_req(in(i)); |
| 14445 | 3599 } |
| 3600 } | |
| 3601 // ...as well as prec | |
|
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3602 for (uint i = req(); i < len(); ++i) { |
| 14445 | 3603 call->add_prec(in(i)); |
| 3604 } | |
| 3605 | |
| 3606 // Remember nodes loading the inline cache into r19. | |
| 3607 call->_load_ic_hi_node = loadConLNodes_IC._large_hi; | |
| 3608 call->_load_ic_node = loadConLNodes_IC._small; | |
| 3609 | |
| 3610 // Operands for new nodes. | |
| 3611 call->_opnds[0] = _opnds[0]; | |
| 3612 call->_opnds[1] = _opnds[1]; | |
| 3613 | |
| 3614 // Only the inline cache is associated with a register. | |
| 3615 assert(Matcher::inline_cache_reg() == OptoReg::Name(R19_num), "ic reg should be R19"); | |
| 3616 | |
| 3617 // Push new nodes. | |
| 3618 if (loadConLNodes_IC._large_hi) nodes->push(loadConLNodes_IC._large_hi); | |
| 3619 if (loadConLNodes_IC._last) nodes->push(loadConLNodes_IC._last); | |
| 3620 nodes->push(call); | |
| 3621 %} | |
| 3622 | |
| 3623 // Compound version of call dynamic | |
| 3624 enc_class enc_java_dynamic_call(method meth, iRegLdst toc) %{ | |
| 3625 // TODO: PPC port $archOpcode(ppc64Opcode_compound); | |
| 3626 MacroAssembler _masm(&cbuf); | |
| 3627 int start_offset = __ offset(); | |
| 3628 | |
| 3629 Register Rtoc = (ra_) ? $constanttablebase : R2_TOC; | |
| 3630 #if 0 | |
| 3631 if (_vtable_index < 0) { | |
| 3632 // Must be invalid_vtable_index, not nonvirtual_vtable_index. | |
| 3633 assert(_vtable_index == Method::invalid_vtable_index, "correct sentinel value"); | |
| 3634 Register ic_reg = as_Register(Matcher::inline_cache_reg_encode()); | |
|
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3635 AddressLiteral meta = __ allocate_metadata_address((Metadata *)Universe::non_oop_word()); |
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3636 |
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3637 address virtual_call_meta_addr = __ pc(); |
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3638 __ load_const_from_method_toc(ic_reg, meta, Rtoc); |
| 14445 | 3639 // CALL to fixup routine. Fixup routine uses ScopeDesc info |
| 3640 // to determine who we intended to call. | |
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3641 __ relocate(virtual_call_Relocation::spec(virtual_call_meta_addr)); |
| 14445 | 3642 emit_call_with_trampoline_stub(_masm, (address)$meth$$method, relocInfo::none); |
| 3643 assert(((MachCallDynamicJavaNode*)this)->ret_addr_offset() == __ offset() - start_offset, | |
| 3644 "Fix constant in ret_addr_offset()"); | |
| 3645 } else { | |
| 3646 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); | |
| 3647 // Go thru the vtable. Get receiver klass. Receiver already | |
| 3648 // checked for non-null. If we'll go thru a C2I adapter, the | |
| 3649 // interpreter expects method in R19_method. | |
| 3650 | |
| 3651 __ load_klass(R11_scratch1, R3); | |
| 3652 | |
| 3653 int entry_offset = InstanceKlass::vtable_start_offset() + _vtable_index * vtableEntry::size(); | |
| 3654 int v_off = entry_offset * wordSize + vtableEntry::method_offset_in_bytes(); | |
| 3655 __ li(R19_method, v_off); | |
| 3656 __ ldx(R19_method/*method oop*/, R19_method/*method offset*/, R11_scratch1/*class*/); | |
| 3657 // NOTE: for vtable dispatches, the vtable entry will never be | |
| 3658 // null. However it may very well end up in handle_wrong_method | |
| 3659 // if the method is abstract for the particular class. | |
| 3660 __ ld(R11_scratch1, in_bytes(Method::from_compiled_offset()), R19_method); | |
| 3661 // Call target. Either compiled code or C2I adapter. | |
| 3662 __ mtctr(R11_scratch1); | |
| 3663 __ bctrl(); | |
| 3664 if (((MachCallDynamicJavaNode*)this)->ret_addr_offset() != __ offset() - start_offset) { | |
| 3665 tty->print(" %d, %d\n", ((MachCallDynamicJavaNode*)this)->ret_addr_offset(),__ offset() - start_offset); | |
| 3666 } | |
| 3667 assert(((MachCallDynamicJavaNode*)this)->ret_addr_offset() == __ offset() - start_offset, | |
| 3668 "Fix constant in ret_addr_offset()"); | |
| 3669 } | |
| 3670 #endif | |
|
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3671 guarantee(0, "Fix handling of toc edge: messes up derived/base pairs."); |
| 14445 | 3672 Unimplemented(); // ret_addr_offset not yet fixed. Depends on compressed oops (load klass!). |
| 3673 %} | |
| 3674 | |
| 3675 // a runtime call | |
| 3676 enc_class enc_java_to_runtime_call (method meth) %{ | |
| 3677 // TODO: PPC port $archOpcode(ppc64Opcode_compound); | |
| 3678 | |
| 3679 MacroAssembler _masm(&cbuf); | |
| 3680 const address start_pc = __ pc(); | |
| 3681 | |
| 3682 // The function we're going to call. | |
| 3683 FunctionDescriptor fdtemp; | |
| 3684 const FunctionDescriptor* fd = !($meth$$method) ? &fdtemp : (FunctionDescriptor*)$meth$$method; | |
| 3685 | |
| 3686 Register Rtoc = R12_scratch2; | |
| 3687 // Calculate the method's TOC. | |
| 3688 __ calculate_address_from_global_toc(Rtoc, __ method_toc()); | |
| 3689 // Put entry, env, toc into the constant pool, this needs up to 3 constant | |
| 3690 // pool entries; call_c_using_toc will optimize the call. | |
| 3691 __ call_c_using_toc(fd, relocInfo::runtime_call_type, Rtoc); | |
| 3692 | |
| 3693 // Check the ret_addr_offset. | |
| 3694 assert(((MachCallRuntimeNode*)this)->ret_addr_offset() == __ last_calls_return_pc() - start_pc, | |
| 3695 "Fix constant in ret_addr_offset()"); | |
| 3696 %} | |
| 3697 | |
| 3698 // Move to ctr for leaf call. | |
| 3699 // This enc_class is needed so that scheduler gets proper | |
| 3700 // input mapping for latency computation. | |
| 3701 enc_class enc_leaf_call_mtctr(iRegLsrc src) %{ | |
| 3702 // TODO: PPC port $archOpcode(ppc64Opcode_mtctr); | |
| 3703 MacroAssembler _masm(&cbuf); | |
| 3704 __ mtctr($src$$Register); | |
| 3705 %} | |
| 3706 | |
| 3707 // postalloc expand emitter for runtime leaf calls. | |
| 3708 enc_class postalloc_expand_java_to_runtime_call(method meth, iRegLdst toc) %{ | |
| 3709 // Get the struct that describes the function we are about to call. | |
| 3710 FunctionDescriptor* fd = (FunctionDescriptor*) this->entry_point(); | |
| 3711 assert(fd, "need fd here"); | |
| 3712 // new nodes | |
| 3713 loadConLNodesTuple loadConLNodes_Entry; | |
| 3714 loadConLNodesTuple loadConLNodes_Env; | |
| 3715 loadConLNodesTuple loadConLNodes_Toc; | |
| 3716 MachNode *mtctr = NULL; | |
| 3717 MachCallLeafNode *call = NULL; | |
| 3718 | |
| 3719 // Create nodes and operands for loading the entry point. | |
| 3720 loadConLNodes_Entry = loadConLNodesTuple_create(C, ra_, n_toc, new (C) immLOper((jlong) fd->entry()), | |
| 3721 OptoReg::Name(R12_H_num), OptoReg::Name(R12_num)); | |
| 3722 | |
| 3723 | |
| 3724 // Create nodes and operands for loading the env pointer. | |
| 3725 if (fd->env() != NULL) { | |
| 3726 loadConLNodes_Env = loadConLNodesTuple_create(C, ra_, n_toc, new (C) immLOper((jlong) fd->env()), | |
| 3727 OptoReg::Name(R11_H_num), OptoReg::Name(R11_num)); | |
| 3728 } else { | |
| 3729 loadConLNodes_Env._large_hi = NULL; | |
| 3730 loadConLNodes_Env._large_lo = NULL; | |
| 3731 loadConLNodes_Env._small = NULL; | |
| 3732 loadConLNodes_Env._last = new (C) loadConL16Node(); | |
| 3733 loadConLNodes_Env._last->_opnds[0] = new (C) iRegLdstOper(); | |
| 3734 loadConLNodes_Env._last->_opnds[1] = new (C) immL16Oper(0); | |
| 3735 ra_->set_pair(loadConLNodes_Env._last->_idx, OptoReg::Name(R11_H_num), OptoReg::Name(R11_num)); | |
| 3736 } | |
| 3737 | |
| 3738 // Create nodes and operands for loading the Toc point. | |
| 3739 loadConLNodes_Toc = loadConLNodesTuple_create(C, ra_, n_toc, new (C) immLOper((jlong) fd->toc()), | |
| 3740 OptoReg::Name(R2_H_num), OptoReg::Name(R2_num)); | |
| 3741 // mtctr node | |
| 3742 mtctr = new (C) CallLeafDirect_mtctrNode(); | |
| 3743 | |
| 3744 assert(loadConLNodes_Entry._last != NULL, "entry must exist"); | |
| 3745 mtctr->add_req(0, loadConLNodes_Entry._last); | |
| 3746 | |
| 3747 mtctr->_opnds[0] = new (C) iRegLdstOper(); | |
| 3748 mtctr->_opnds[1] = new (C) iRegLdstOper(); | |
| 3749 | |
| 3750 // call node | |
| 3751 call = new (C) CallLeafDirectNode(); | |
| 3752 | |
| 3753 call->_opnds[0] = _opnds[0]; | |
| 3754 call->_opnds[1] = new (C) methodOper((intptr_t) fd->entry()); // may get set later | |
| 3755 | |
| 3756 // Make the new call node look like the old one. | |
| 3757 call->_name = _name; | |
| 3758 call->_tf = _tf; | |
| 3759 call->_entry_point = _entry_point; | |
| 3760 call->_cnt = _cnt; | |
| 3761 call->_argsize = _argsize; | |
| 3762 call->_oop_map = _oop_map; | |
| 3763 guarantee(!_jvms, "You must clone the jvms and adapt the offsets by fix_jvms()."); | |
| 3764 call->_jvms = NULL; | |
| 3765 call->_jvmadj = _jvmadj; | |
| 3766 call->_in_rms = _in_rms; | |
| 3767 call->_nesting = _nesting; | |
| 3768 | |
| 3769 | |
| 3770 // New call needs all inputs of old call. | |
| 3771 // Req... | |
| 3772 for (uint i = 0; i < req(); ++i) { | |
|
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3773 if (i != mach_constant_base_node_input()) { |
| 14445 | 3774 call->add_req(in(i)); |
| 3775 } | |
| 3776 } | |
| 3777 | |
| 3778 // These must be reqired edges, as the registers are live up to | |
| 3779 // the call. Else the constants are handled as kills. | |
|
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3780 call->add_req(mtctr); |
| 14445 | 3781 call->add_req(loadConLNodes_Env._last); |
| 3782 call->add_req(loadConLNodes_Toc._last); | |
| 3783 | |
| 3784 // ...as well as prec | |
| 3785 for (uint i = req(); i < len(); ++i) { | |
| 3786 call->add_prec(in(i)); | |
| 3787 } | |
| 3788 | |
| 3789 // registers | |
| 3790 ra_->set1(mtctr->_idx, OptoReg::Name(SR_CTR_num)); | |
| 3791 | |
| 3792 // Insert the new nodes. | |
| 3793 if (loadConLNodes_Entry._large_hi) nodes->push(loadConLNodes_Entry._large_hi); | |
| 3794 if (loadConLNodes_Entry._last) nodes->push(loadConLNodes_Entry._last); | |
| 3795 if (loadConLNodes_Env._large_hi) nodes->push(loadConLNodes_Env._large_hi); | |
| 3796 if (loadConLNodes_Env._last) nodes->push(loadConLNodes_Env._last); | |
| 3797 if (loadConLNodes_Toc._large_hi) nodes->push(loadConLNodes_Toc._large_hi); | |
| 3798 if (loadConLNodes_Toc._last) nodes->push(loadConLNodes_Toc._last); | |
| 3799 nodes->push(mtctr); | |
| 3800 nodes->push(call); | |
| 3801 %} | |
| 3802 %} | |
| 3803 | |
| 3804 //----------FRAME-------------------------------------------------------------- | |
| 3805 // Definition of frame structure and management information. | |
| 3806 | |
| 3807 frame %{ | |
| 3808 // What direction does stack grow in (assumed to be same for native & Java). | |
| 3809 stack_direction(TOWARDS_LOW); | |
| 3810 | |
| 3811 // These two registers define part of the calling convention between | |
| 3812 // compiled code and the interpreter. | |
| 3813 | |
|
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3814 // Inline Cache Register or method for I2C. |
| 14445 | 3815 inline_cache_reg(R19); // R19_method |
| 3816 | |
| 3817 // Method Oop Register when calling interpreter. | |
| 3818 interpreter_method_oop_reg(R19); // R19_method | |
| 3819 | |
| 3820 // Optional: name the operand used by cisc-spilling to access | |
| 3821 // [stack_pointer + offset]. | |
| 3822 cisc_spilling_operand_name(indOffset); | |
| 3823 | |
| 3824 // Number of stack slots consumed by a Monitor enter. | |
| 3825 sync_stack_slots((frame::jit_monitor_size / VMRegImpl::stack_slot_size)); | |
| 3826 | |
| 3827 // Compiled code's Frame Pointer. | |
| 3828 frame_pointer(R1); // R1_SP | |
| 3829 | |
| 3830 // Interpreter stores its frame pointer in a register which is | |
| 3831 // stored to the stack by I2CAdaptors. I2CAdaptors convert from | |
| 3832 // interpreted java to compiled java. | |
| 3833 // | |
| 3834 // R14_state holds pointer to caller's cInterpreter. | |
| 3835 interpreter_frame_pointer(R14); // R14_state | |
| 3836 | |
| 3837 stack_alignment(frame::alignment_in_bytes); | |
| 3838 | |
| 3839 in_preserve_stack_slots((frame::jit_in_preserve_size / VMRegImpl::stack_slot_size)); | |
| 3840 | |
| 3841 // Number of outgoing stack slots killed above the | |
| 3842 // out_preserve_stack_slots for calls to C. Supports the var-args | |
| 3843 // backing area for register parms. | |
| 3844 // | |
| 3845 varargs_C_out_slots_killed(((frame::abi_112_size - frame::jit_out_preserve_size) / VMRegImpl::stack_slot_size)); | |
| 3846 | |
| 3847 // The after-PROLOG location of the return address. Location of | |
| 3848 // return address specifies a type (REG or STACK) and a number | |
| 3849 // representing the register number (i.e. - use a register name) or | |
| 3850 // stack slot. | |
| 3851 // | |
| 3852 // A: Link register is stored in stack slot ... | |
| 3853 // M: ... but it's in the caller's frame according to PPC-64 ABI. | |
| 3854 // J: Therefore, we make sure that the link register is also in R11_scratch1 | |
| 3855 // at the end of the prolog. | |
| 3856 // B: We use R20, now. | |
| 3857 //return_addr(REG R20); | |
| 3858 | |
| 3859 // G: After reading the comments made by all the luminaries on their | |
| 3860 // failure to tell the compiler where the return address really is, | |
| 3861 // I hardly dare to try myself. However, I'm convinced it's in slot | |
| 3862 // 4 what apparently works and saves us some spills. | |
| 3863 return_addr(STACK 4); | |
| 3864 | |
| 3865 // This is the body of the function | |
| 3866 // | |
| 3867 // void Matcher::calling_convention(OptoRegPair* sig, // array of ideal regs | |
| 3868 // uint length, // length of array | |
| 3869 // bool is_outgoing) | |
| 3870 // | |
| 3871 // The `sig' array is to be updated. sig[j] represents the location | |
| 3872 // of the j-th argument, either a register or a stack slot. | |
| 3873 | |
| 3874 // Comment taken from i486.ad: | |
| 3875 // Body of function which returns an integer array locating | |
| 3876 // arguments either in registers or in stack slots. Passed an array | |
| 3877 // of ideal registers called "sig" and a "length" count. Stack-slot | |
| 3878 // offsets are based on outgoing arguments, i.e. a CALLER setting up | |
| 3879 // arguments for a CALLEE. Incoming stack arguments are | |
| 3880 // automatically biased by the preserve_stack_slots field above. | |
| 3881 calling_convention %{ | |
| 3882 // No difference between ingoing/outgoing. Just pass false. | |
| 3883 SharedRuntime::java_calling_convention(sig_bt, regs, length, false); | |
| 3884 %} | |
| 3885 | |
| 3886 // Comment taken from i486.ad: | |
| 3887 // Body of function which returns an integer array locating | |
| 3888 // arguments either in registers or in stack slots. Passed an array | |
| 3889 // of ideal registers called "sig" and a "length" count. Stack-slot | |
| 3890 // offsets are based on outgoing arguments, i.e. a CALLER setting up | |
| 3891 // arguments for a CALLEE. Incoming stack arguments are | |
| 3892 // automatically biased by the preserve_stack_slots field above. | |
| 3893 c_calling_convention %{ | |
| 3894 // This is obviously always outgoing. | |
| 3895 // C argument in register AND stack slot. | |
| 3896 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length); | |
| 3897 %} | |
| 3898 | |
| 3899 // Location of native (C/C++) and interpreter return values. This | |
| 3900 // is specified to be the same as Java. In the 32-bit VM, long | |
| 3901 // values are actually returned from native calls in O0:O1 and | |
| 3902 // returned to the interpreter in I0:I1. The copying to and from | |
| 3903 // the register pairs is done by the appropriate call and epilog | |
| 3904 // opcodes. This simplifies the register allocator. | |
| 3905 c_return_value %{ | |
| 3906 assert((ideal_reg >= Op_RegI && ideal_reg <= Op_RegL) || | |
| 3907 (ideal_reg == Op_RegN && Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0), | |
| 3908 "only return normal values"); | |
| 3909 // enum names from opcodes.hpp: Op_Node Op_Set Op_RegN Op_RegI Op_RegP Op_RegF Op_RegD Op_RegL | |
| 3910 static int typeToRegLo[Op_RegL+1] = { 0, 0, R3_num, R3_num, R3_num, F1_num, F1_num, R3_num }; | |
| 3911 static int typeToRegHi[Op_RegL+1] = { 0, 0, OptoReg::Bad, R3_H_num, R3_H_num, OptoReg::Bad, F1_H_num, R3_H_num }; | |
| 3912 return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]); | |
| 3913 %} | |
| 3914 | |
| 3915 // Location of compiled Java return values. Same as C | |
| 3916 return_value %{ | |
| 3917 assert((ideal_reg >= Op_RegI && ideal_reg <= Op_RegL) || | |
| 3918 (ideal_reg == Op_RegN && Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0), | |
| 3919 "only return normal values"); | |
| 3920 // enum names from opcodes.hpp: Op_Node Op_Set Op_RegN Op_RegI Op_RegP Op_RegF Op_RegD Op_RegL | |
| 3921 static int typeToRegLo[Op_RegL+1] = { 0, 0, R3_num, R3_num, R3_num, F1_num, F1_num, R3_num }; | |
| 3922 static int typeToRegHi[Op_RegL+1] = { 0, 0, OptoReg::Bad, R3_H_num, R3_H_num, OptoReg::Bad, F1_H_num, R3_H_num }; | |
| 3923 return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]); | |
| 3924 %} | |
| 3925 %} | |
| 3926 | |
| 3927 | |
| 3928 //----------ATTRIBUTES--------------------------------------------------------- | |
| 3929 | |
| 3930 //----------Operand Attributes------------------------------------------------- | |
| 3931 op_attrib op_cost(1); // Required cost attribute. | |
| 3932 | |
| 3933 //----------Instruction Attributes--------------------------------------------- | |
| 3934 | |
| 3935 // Cost attribute. required. | |
| 3936 ins_attrib ins_cost(DEFAULT_COST); | |
| 3937 | |
| 3938 // Is this instruction a non-matching short branch variant of some | |
| 3939 // long branch? Not required. | |
| 3940 ins_attrib ins_short_branch(0); | |
| 3941 | |
| 3942 ins_attrib ins_is_TrapBasedCheckNode(true); | |
| 3943 | |
| 3944 // Number of constants. | |
| 3945 // This instruction uses the given number of constants | |
| 3946 // (optional attribute). | |
| 3947 // This is needed to determine in time whether the constant pool will | |
| 3948 // exceed 4000 entries. Before postalloc_expand the overall number of constants | |
| 3949 // is determined. It's also used to compute the constant pool size | |
| 3950 // in Output(). | |
| 3951 ins_attrib ins_num_consts(0); | |
| 3952 | |
| 3953 // Required alignment attribute (must be a power of 2) specifies the | |
| 3954 // alignment that some part of the instruction (not necessarily the | |
| 3955 // start) requires. If > 1, a compute_padding() function must be | |
| 3956 // provided for the instruction. | |
| 3957 ins_attrib ins_alignment(1); | |
| 3958 | |
| 3959 // Enforce/prohibit rematerializations. | |
| 3960 // - If an instruction is attributed with 'ins_cannot_rematerialize(true)' | |
| 3961 // then rematerialization of that instruction is prohibited and the | |
| 3962 // instruction's value will be spilled if necessary. | |
| 3963 // Causes that MachNode::rematerialize() returns false. | |
| 3964 // - If an instruction is attributed with 'ins_should_rematerialize(true)' | |
| 3965 // then rematerialization should be enforced and a copy of the instruction | |
| 3966 // should be inserted if possible; rematerialization is not guaranteed. | |
| 3967 // Note: this may result in rematerializations in front of every use. | |
| 3968 // Causes that MachNode::rematerialize() can return true. | |
| 3969 // (optional attribute) | |
| 3970 ins_attrib ins_cannot_rematerialize(false); | |
| 3971 ins_attrib ins_should_rematerialize(false); | |
| 3972 | |
| 3973 // Instruction has variable size depending on alignment. | |
| 3974 ins_attrib ins_variable_size_depending_on_alignment(false); | |
| 3975 | |
| 3976 // Instruction is a nop. | |
| 3977 ins_attrib ins_is_nop(false); | |
| 3978 | |
| 3979 // Instruction is mapped to a MachIfFastLock node (instead of MachFastLock). | |
| 3980 ins_attrib ins_use_mach_if_fast_lock_node(false); | |
| 3981 | |
| 3982 // Field for the toc offset of a constant. | |
| 3983 // | |
| 3984 // This is needed if the toc offset is not encodable as an immediate in | |
| 3985 // the PPC load instruction. If so, the upper (hi) bits of the offset are | |
| 3986 // added to the toc, and from this a load with immediate is performed. | |
| 3987 // With postalloc expand, we get two nodes that require the same offset | |
| 3988 // but which don't know about each other. The offset is only known | |
| 3989 // when the constant is added to the constant pool during emitting. | |
| 3990 // It is generated in the 'hi'-node adding the upper bits, and saved | |
| 3991 // in this node. The 'lo'-node has a link to the 'hi'-node and reads | |
| 3992 // the offset from there when it gets encoded. | |
| 3993 ins_attrib ins_field_const_toc_offset(0); | |
| 3994 ins_attrib ins_field_const_toc_offset_hi_node(0); | |
| 3995 | |
| 3996 // A field that can hold the instructions offset in the code buffer. | |
| 3997 // Set in the nodes emitter. | |
| 3998 ins_attrib ins_field_cbuf_insts_offset(-1); | |
| 3999 | |
| 4000 // Fields for referencing a call's load-IC-node. | |
| 4001 // If the toc offset can not be encoded as an immediate in a load, we | |
| 4002 // use two nodes. | |
| 4003 ins_attrib ins_field_load_ic_hi_node(0); | |
| 4004 ins_attrib ins_field_load_ic_node(0); | |
| 4005 | |
| 4006 //----------OPERANDS----------------------------------------------------------- | |
| 4007 // Operand definitions must precede instruction definitions for correct | |
| 4008 // parsing in the ADLC because operands constitute user defined types | |
| 4009 // which are used in instruction definitions. | |
| 4010 // | |
| 4011 // Formats are generated automatically for constants and base registers. | |
| 4012 | |
| 4013 //----------Simple Operands---------------------------------------------------- | |
| 4014 // Immediate Operands | |
| 4015 | |
| 4016 // Integer Immediate: 32-bit | |
| 4017 operand immI() %{ | |
| 4018 match(ConI); | |
| 4019 op_cost(40); | |
| 4020 format %{ %} | |
| 4021 interface(CONST_INTER); | |
| 4022 %} | |
| 4023 | |
| 4024 operand immI8() %{ | |
| 4025 predicate(Assembler::is_simm(n->get_int(), 8)); | |
| 4026 op_cost(0); | |
| 4027 match(ConI); | |
| 4028 format %{ %} | |
| 4029 interface(CONST_INTER); | |
| 4030 %} | |
| 4031 | |
| 4032 // Integer Immediate: 16-bit | |
| 4033 operand immI16() %{ | |
| 4034 predicate(Assembler::is_simm(n->get_int(), 16)); | |
| 4035 op_cost(0); | |
| 4036 match(ConI); | |
| 4037 format %{ %} | |
| 4038 interface(CONST_INTER); | |
| 4039 %} | |
| 4040 | |
| 4041 // Integer Immediate: 32-bit, where lowest 16 bits are 0x0000. | |
| 4042 operand immIhi16() %{ | |
| 4043 predicate(((n->get_int() & 0xffff0000) != 0) && ((n->get_int() & 0xffff) == 0)); | |
| 4044 match(ConI); | |
| 4045 op_cost(0); | |
| 4046 format %{ %} | |
| 4047 interface(CONST_INTER); | |
| 4048 %} | |
| 4049 | |
| 4050 operand immInegpow2() %{ | |
| 4051 predicate(is_power_of_2_long((jlong) (julong) (juint) (-(n->get_int())))); | |
| 4052 match(ConI); | |
| 4053 op_cost(0); | |
| 4054 format %{ %} | |
| 4055 interface(CONST_INTER); | |
| 4056 %} | |
| 4057 | |
| 4058 operand immIpow2minus1() %{ | |
| 4059 predicate(is_power_of_2_long((((jlong) (n->get_int()))+1))); | |
| 4060 match(ConI); | |
| 4061 op_cost(0); | |
| 4062 format %{ %} | |
| 4063 interface(CONST_INTER); | |
| 4064 %} | |
| 4065 | |
| 4066 operand immIpowerOf2() %{ | |
| 4067 predicate(is_power_of_2_long((((jlong) (julong) (juint) (n->get_int()))))); | |
| 4068 match(ConI); | |
| 4069 op_cost(0); | |
| 4070 format %{ %} | |
| 4071 interface(CONST_INTER); | |
| 4072 %} | |
| 4073 | |
| 4074 // Unsigned Integer Immediate: the values 0-31 | |
| 4075 operand uimmI5() %{ | |
| 4076 predicate(Assembler::is_uimm(n->get_int(), 5)); | |
| 4077 match(ConI); | |
| 4078 op_cost(0); | |
| 4079 format %{ %} | |
| 4080 interface(CONST_INTER); | |
| 4081 %} | |
| 4082 | |
| 4083 // Unsigned Integer Immediate: 6-bit | |
| 4084 operand uimmI6() %{ | |
| 4085 predicate(Assembler::is_uimm(n->get_int(), 6)); | |
| 4086 match(ConI); | |
| 4087 op_cost(0); | |
| 4088 format %{ %} | |
| 4089 interface(CONST_INTER); | |
| 4090 %} | |
| 4091 | |
| 4092 // Unsigned Integer Immediate: 6-bit int, greater than 32 | |
| 4093 operand uimmI6_ge32() %{ | |
| 4094 predicate(Assembler::is_uimm(n->get_int(), 6) && n->get_int() >= 32); | |
| 4095 match(ConI); | |
| 4096 op_cost(0); | |
| 4097 format %{ %} | |
| 4098 interface(CONST_INTER); | |
| 4099 %} | |
| 4100 | |
| 4101 // Unsigned Integer Immediate: 15-bit | |
| 4102 operand uimmI15() %{ | |
| 4103 predicate(Assembler::is_uimm(n->get_int(), 15)); | |
| 4104 match(ConI); | |
| 4105 op_cost(0); | |
| 4106 format %{ %} | |
| 4107 interface(CONST_INTER); | |
| 4108 %} | |
| 4109 | |
| 4110 // Unsigned Integer Immediate: 16-bit | |
| 4111 operand uimmI16() %{ | |
| 4112 predicate(Assembler::is_uimm(n->get_int(), 16)); | |
| 4113 match(ConI); | |
| 4114 op_cost(0); | |
| 4115 format %{ %} | |
| 4116 interface(CONST_INTER); | |
| 4117 %} | |
| 4118 | |
| 4119 // constant 'int 0'. | |
| 4120 operand immI_0() %{ | |
| 4121 predicate(n->get_int() == 0); | |
| 4122 match(ConI); | |
| 4123 op_cost(0); | |
| 4124 format %{ %} | |
| 4125 interface(CONST_INTER); | |
| 4126 %} | |
| 4127 | |
| 4128 // constant 'int 1'. | |
| 4129 operand immI_1() %{ | |
| 4130 predicate(n->get_int() == 1); | |
| 4131 match(ConI); | |
| 4132 op_cost(0); | |
| 4133 format %{ %} | |
| 4134 interface(CONST_INTER); | |
| 4135 %} | |
| 4136 | |
| 4137 // constant 'int -1'. | |
| 4138 operand immI_minus1() %{ | |
| 4139 predicate(n->get_int() == -1); | |
| 4140 match(ConI); | |
| 4141 op_cost(0); | |
| 4142 format %{ %} | |
| 4143 interface(CONST_INTER); | |
| 4144 %} | |
| 4145 | |
| 4146 // int value 16. | |
| 4147 operand immI_16() %{ | |
| 4148 predicate(n->get_int() == 16); | |
| 4149 match(ConI); | |
| 4150 op_cost(0); | |
| 4151 format %{ %} | |
| 4152 interface(CONST_INTER); | |
| 4153 %} | |
| 4154 | |
| 4155 // int value 24. | |
| 4156 operand immI_24() %{ | |
| 4157 predicate(n->get_int() == 24); | |
| 4158 match(ConI); | |
| 4159 op_cost(0); | |
| 4160 format %{ %} | |
| 4161 interface(CONST_INTER); | |
| 4162 %} | |
| 4163 | |
| 4164 // Compressed oops constants | |
| 4165 // Pointer Immediate | |
| 4166 operand immN() %{ | |
| 4167 match(ConN); | |
| 4168 | |
| 4169 op_cost(10); | |
| 4170 format %{ %} | |
| 4171 interface(CONST_INTER); | |
| 4172 %} | |
| 4173 | |
| 4174 // NULL Pointer Immediate | |
| 4175 operand immN_0() %{ | |
| 4176 predicate(n->get_narrowcon() == 0); | |
| 4177 match(ConN); | |
| 4178 | |
| 4179 op_cost(0); | |
| 4180 format %{ %} | |
| 4181 interface(CONST_INTER); | |
| 4182 %} | |
| 4183 | |
| 4184 // Compressed klass constants | |
| 4185 operand immNKlass() %{ | |
| 4186 match(ConNKlass); | |
| 4187 | |
| 4188 op_cost(0); | |
| 4189 format %{ %} | |
| 4190 interface(CONST_INTER); | |
| 4191 %} | |
| 4192 | |
| 4193 // This operand can be used to avoid matching of an instruct | |
| 4194 // with chain rule. | |
| 4195 operand immNKlass_NM() %{ | |
| 4196 match(ConNKlass); | |
| 4197 predicate(false); | |
| 4198 op_cost(0); | |
| 4199 format %{ %} | |
| 4200 interface(CONST_INTER); | |
| 4201 %} | |
| 4202 | |
| 4203 // Pointer Immediate: 64-bit | |
| 4204 operand immP() %{ | |
| 4205 match(ConP); | |
| 4206 op_cost(0); | |
| 4207 format %{ %} | |
| 4208 interface(CONST_INTER); | |
| 4209 %} | |
| 4210 | |
| 4211 // Operand to avoid match of loadConP. | |
| 4212 // This operand can be used to avoid matching of an instruct | |
| 4213 // with chain rule. | |
| 4214 operand immP_NM() %{ | |
| 4215 match(ConP); | |
| 4216 predicate(false); | |
| 4217 op_cost(0); | |
| 4218 format %{ %} | |
| 4219 interface(CONST_INTER); | |
| 4220 %} | |
| 4221 | |
| 4222 // costant 'pointer 0'. | |
| 4223 operand immP_0() %{ | |
| 4224 predicate(n->get_ptr() == 0); | |
| 4225 match(ConP); | |
| 4226 op_cost(0); | |
| 4227 format %{ %} | |
| 4228 interface(CONST_INTER); | |
| 4229 %} | |
| 4230 | |
| 4231 // pointer 0x0 or 0x1 | |
| 4232 operand immP_0or1() %{ | |
| 4233 predicate((n->get_ptr() == 0) || (n->get_ptr() == 1)); | |
| 4234 match(ConP); | |
| 4235 op_cost(0); | |
| 4236 format %{ %} | |
| 4237 interface(CONST_INTER); | |
| 4238 %} | |
| 4239 | |
| 4240 operand immL() %{ | |
| 4241 match(ConL); | |
| 4242 op_cost(40); | |
| 4243 format %{ %} | |
| 4244 interface(CONST_INTER); | |
| 4245 %} | |
| 4246 | |
| 4247 // Long Immediate: 16-bit | |
| 4248 operand immL16() %{ | |
| 4249 predicate(Assembler::is_simm(n->get_long(), 16)); | |
| 4250 match(ConL); | |
| 4251 op_cost(0); | |
| 4252 format %{ %} | |
| 4253 interface(CONST_INTER); | |
| 4254 %} | |
| 4255 | |
| 4256 // Long Immediate: 16-bit, 4-aligned | |
| 4257 operand immL16Alg4() %{ | |
| 4258 predicate(Assembler::is_simm(n->get_long(), 16) && ((n->get_long() & 0x3) == 0)); | |
| 4259 match(ConL); | |
| 4260 op_cost(0); | |
| 4261 format %{ %} | |
| 4262 interface(CONST_INTER); | |
| 4263 %} | |
| 4264 | |
| 4265 // Long Immediate: 32-bit, where lowest 16 bits are 0x0000. | |
| 4266 operand immL32hi16() %{ | |
| 4267 predicate(Assembler::is_simm(n->get_long(), 32) && ((n->get_long() & 0xffffL) == 0L)); | |
| 4268 match(ConL); | |
| 4269 op_cost(0); | |
| 4270 format %{ %} | |
| 4271 interface(CONST_INTER); | |
| 4272 %} | |
| 4273 | |
| 4274 // Long Immediate: 32-bit | |
| 4275 operand immL32() %{ | |
| 4276 predicate(Assembler::is_simm(n->get_long(), 32)); | |
| 4277 match(ConL); | |
| 4278 op_cost(0); | |
| 4279 format %{ %} | |
| 4280 interface(CONST_INTER); | |
| 4281 %} | |
| 4282 | |
| 4283 // Long Immediate: 64-bit, where highest 16 bits are not 0x0000. | |
| 4284 operand immLhighest16() %{ | |
| 4285 predicate((n->get_long() & 0xffff000000000000L) != 0L && (n->get_long() & 0x0000ffffffffffffL) == 0L); | |
| 4286 match(ConL); | |
| 4287 op_cost(0); | |
| 4288 format %{ %} | |
| 4289 interface(CONST_INTER); | |
| 4290 %} | |
| 4291 | |
| 4292 operand immLnegpow2() %{ | |
| 4293 predicate(is_power_of_2_long((jlong)-(n->get_long()))); | |
| 4294 match(ConL); | |
| 4295 op_cost(0); | |
| 4296 format %{ %} | |
| 4297 interface(CONST_INTER); | |
| 4298 %} | |
| 4299 | |
| 4300 operand immLpow2minus1() %{ | |
| 4301 predicate(is_power_of_2_long((((jlong) (n->get_long()))+1)) && | |
| 4302 (n->get_long() != (jlong)0xffffffffffffffffL)); | |
| 4303 match(ConL); | |
| 4304 op_cost(0); | |
| 4305 format %{ %} | |
| 4306 interface(CONST_INTER); | |
| 4307 %} | |
| 4308 | |
| 4309 // constant 'long 0'. | |
| 4310 operand immL_0() %{ | |
| 4311 predicate(n->get_long() == 0L); | |
| 4312 match(ConL); | |
| 4313 op_cost(0); | |
| 4314 format %{ %} | |
| 4315 interface(CONST_INTER); | |
| 4316 %} | |
| 4317 | |
| 4318 // constat ' long -1'. | |
| 4319 operand immL_minus1() %{ | |
| 4320 predicate(n->get_long() == -1L); | |
| 4321 match(ConL); | |
| 4322 op_cost(0); | |
| 4323 format %{ %} | |
| 4324 interface(CONST_INTER); | |
| 4325 %} | |
| 4326 | |
| 4327 // Long Immediate: low 32-bit mask | |
| 4328 operand immL_32bits() %{ | |
| 4329 predicate(n->get_long() == 0xFFFFFFFFL); | |
| 4330 match(ConL); | |
| 4331 op_cost(0); | |
| 4332 format %{ %} | |
| 4333 interface(CONST_INTER); | |
| 4334 %} | |
| 4335 | |
| 4336 // Unsigned Long Immediate: 16-bit | |
| 4337 operand uimmL16() %{ | |
| 4338 predicate(Assembler::is_uimm(n->get_long(), 16)); | |
| 4339 match(ConL); | |
| 4340 op_cost(0); | |
| 4341 format %{ %} | |
| 4342 interface(CONST_INTER); | |
| 4343 %} | |
| 4344 | |
| 4345 // Float Immediate | |
| 4346 operand immF() %{ | |
| 4347 match(ConF); | |
| 4348 op_cost(40); | |
| 4349 format %{ %} | |
| 4350 interface(CONST_INTER); | |
| 4351 %} | |
| 4352 | |
| 4353 // constant 'float +0.0'. | |
| 4354 operand immF_0() %{ | |
| 4355 predicate((n->getf() == 0) && | |
| 4356 (fpclassify(n->getf()) == FP_ZERO) && (signbit(n->getf()) == 0)); | |
| 4357 match(ConF); | |
| 4358 op_cost(0); | |
| 4359 format %{ %} | |
| 4360 interface(CONST_INTER); | |
| 4361 %} | |
| 4362 | |
| 4363 // Double Immediate | |
| 4364 operand immD() %{ | |
| 4365 match(ConD); | |
| 4366 op_cost(40); | |
| 4367 format %{ %} | |
| 4368 interface(CONST_INTER); | |
| 4369 %} | |
| 4370 | |
| 4371 // Integer Register Operands | |
| 4372 // Integer Destination Register | |
| 4373 // See definition of reg_class bits32_reg_rw. | |
| 4374 operand iRegIdst() %{ | |
| 4375 constraint(ALLOC_IN_RC(bits32_reg_rw)); | |
| 4376 match(RegI); | |
| 4377 match(rscratch1RegI); | |
| 4378 match(rscratch2RegI); | |
| 4379 match(rarg1RegI); | |
| 4380 match(rarg2RegI); | |
| 4381 match(rarg3RegI); | |
| 4382 match(rarg4RegI); | |
| 4383 format %{ %} | |
| 4384 interface(REG_INTER); | |
| 4385 %} | |
| 4386 | |
| 4387 // Integer Source Register | |
| 4388 // See definition of reg_class bits32_reg_ro. | |
| 4389 operand iRegIsrc() %{ | |
| 4390 constraint(ALLOC_IN_RC(bits32_reg_ro)); | |
| 4391 match(RegI); | |
| 4392 match(rscratch1RegI); | |
| 4393 match(rscratch2RegI); | |
| 4394 match(rarg1RegI); | |
| 4395 match(rarg2RegI); | |
| 4396 match(rarg3RegI); | |
| 4397 match(rarg4RegI); | |
| 4398 format %{ %} | |
| 4399 interface(REG_INTER); | |
| 4400 %} | |
| 4401 | |
| 4402 operand rscratch1RegI() %{ | |
| 4403 constraint(ALLOC_IN_RC(rscratch1_bits32_reg)); | |
| 4404 match(iRegIdst); | |
| 4405 format %{ %} | |
| 4406 interface(REG_INTER); | |
| 4407 %} | |
| 4408 | |
| 4409 operand rscratch2RegI() %{ | |
| 4410 constraint(ALLOC_IN_RC(rscratch2_bits32_reg)); | |
| 4411 match(iRegIdst); | |
| 4412 format %{ %} | |
| 4413 interface(REG_INTER); | |
| 4414 %} | |
| 4415 | |
| 4416 operand rarg1RegI() %{ | |
| 4417 constraint(ALLOC_IN_RC(rarg1_bits32_reg)); | |
| 4418 match(iRegIdst); | |
| 4419 format %{ %} | |
| 4420 interface(REG_INTER); | |
| 4421 %} | |
| 4422 | |
| 4423 operand rarg2RegI() %{ | |
| 4424 constraint(ALLOC_IN_RC(rarg2_bits32_reg)); | |
| 4425 match(iRegIdst); | |
| 4426 format %{ %} | |
| 4427 interface(REG_INTER); | |
| 4428 %} | |
| 4429 | |
| 4430 operand rarg3RegI() %{ | |
| 4431 constraint(ALLOC_IN_RC(rarg3_bits32_reg)); | |
| 4432 match(iRegIdst); | |
| 4433 format %{ %} | |
| 4434 interface(REG_INTER); | |
| 4435 %} | |
| 4436 | |
| 4437 operand rarg4RegI() %{ | |
| 4438 constraint(ALLOC_IN_RC(rarg4_bits32_reg)); | |
| 4439 match(iRegIdst); | |
| 4440 format %{ %} | |
| 4441 interface(REG_INTER); | |
| 4442 %} | |
| 4443 | |
| 4444 operand rarg1RegL() %{ | |
| 4445 constraint(ALLOC_IN_RC(rarg1_bits64_reg)); | |
| 4446 match(iRegLdst); | |
| 4447 format %{ %} | |
| 4448 interface(REG_INTER); | |
| 4449 %} | |
| 4450 | |
| 4451 operand rarg2RegL() %{ | |
| 4452 constraint(ALLOC_IN_RC(rarg2_bits64_reg)); | |
| 4453 match(iRegLdst); | |
| 4454 format %{ %} | |
| 4455 interface(REG_INTER); | |
| 4456 %} | |
| 4457 | |
| 4458 operand rarg3RegL() %{ | |
| 4459 constraint(ALLOC_IN_RC(rarg3_bits64_reg)); | |
| 4460 match(iRegLdst); | |
| 4461 format %{ %} | |
| 4462 interface(REG_INTER); | |
| 4463 %} | |
| 4464 | |
| 4465 operand rarg4RegL() %{ | |
| 4466 constraint(ALLOC_IN_RC(rarg4_bits64_reg)); | |
| 4467 match(iRegLdst); | |
| 4468 format %{ %} | |
| 4469 interface(REG_INTER); | |
| 4470 %} | |
| 4471 | |
| 4472 // Pointer Destination Register | |
| 4473 // See definition of reg_class bits64_reg_rw. | |
| 4474 operand iRegPdst() %{ | |
| 4475 constraint(ALLOC_IN_RC(bits64_reg_rw)); | |
| 4476 match(RegP); | |
| 4477 match(rscratch1RegP); | |
| 4478 match(rscratch2RegP); | |
| 4479 match(rarg1RegP); | |
| 4480 match(rarg2RegP); | |
| 4481 match(rarg3RegP); | |
| 4482 match(rarg4RegP); | |
| 4483 format %{ %} | |
| 4484 interface(REG_INTER); | |
| 4485 %} | |
| 4486 | |
| 4487 // Pointer Destination Register | |
| 4488 // Operand not using r11 and r12 (killed in epilog). | |
| 4489 operand iRegPdstNoScratch() %{ | |
| 4490 constraint(ALLOC_IN_RC(bits64_reg_leaf_call)); | |
| 4491 match(RegP); | |
| 4492 match(rarg1RegP); | |
| 4493 match(rarg2RegP); | |
| 4494 match(rarg3RegP); | |
| 4495 match(rarg4RegP); | |
| 4496 format %{ %} | |
| 4497 interface(REG_INTER); | |
| 4498 %} | |
| 4499 | |
| 4500 // Pointer Source Register | |
| 4501 // See definition of reg_class bits64_reg_ro. | |
| 4502 operand iRegPsrc() %{ | |
| 4503 constraint(ALLOC_IN_RC(bits64_reg_ro)); | |
| 4504 match(RegP); | |
| 4505 match(iRegPdst); | |
| 4506 match(rscratch1RegP); | |
| 4507 match(rscratch2RegP); | |
| 4508 match(rarg1RegP); | |
| 4509 match(rarg2RegP); | |
| 4510 match(rarg3RegP); | |
| 4511 match(rarg4RegP); | |
| 4512 match(threadRegP); | |
| 4513 format %{ %} | |
| 4514 interface(REG_INTER); | |
| 4515 %} | |
| 4516 | |
| 4517 // Thread operand. | |
| 4518 operand threadRegP() %{ | |
| 4519 constraint(ALLOC_IN_RC(thread_bits64_reg)); | |
| 4520 match(iRegPdst); | |
| 4521 format %{ "R16" %} | |
| 4522 interface(REG_INTER); | |
| 4523 %} | |
| 4524 | |
| 4525 operand rscratch1RegP() %{ | |
| 4526 constraint(ALLOC_IN_RC(rscratch1_bits64_reg)); | |
| 4527 match(iRegPdst); | |
| 4528 format %{ "R11" %} | |
| 4529 interface(REG_INTER); | |
| 4530 %} | |
| 4531 | |
| 4532 operand rscratch2RegP() %{ | |
| 4533 constraint(ALLOC_IN_RC(rscratch2_bits64_reg)); | |
| 4534 match(iRegPdst); | |
| 4535 format %{ %} | |
| 4536 interface(REG_INTER); | |
| 4537 %} | |
| 4538 | |
| 4539 operand rarg1RegP() %{ | |
| 4540 constraint(ALLOC_IN_RC(rarg1_bits64_reg)); | |
| 4541 match(iRegPdst); | |
| 4542 format %{ %} | |
| 4543 interface(REG_INTER); | |
| 4544 %} | |
| 4545 | |
| 4546 operand rarg2RegP() %{ | |
| 4547 constraint(ALLOC_IN_RC(rarg2_bits64_reg)); | |
| 4548 match(iRegPdst); | |
| 4549 format %{ %} | |
| 4550 interface(REG_INTER); | |
| 4551 %} | |
| 4552 | |
| 4553 operand rarg3RegP() %{ | |
| 4554 constraint(ALLOC_IN_RC(rarg3_bits64_reg)); | |
| 4555 match(iRegPdst); | |
| 4556 format %{ %} | |
| 4557 interface(REG_INTER); | |
| 4558 %} | |
| 4559 | |
| 4560 operand rarg4RegP() %{ | |
| 4561 constraint(ALLOC_IN_RC(rarg4_bits64_reg)); | |
| 4562 match(iRegPdst); | |
| 4563 format %{ %} | |
| 4564 interface(REG_INTER); | |
| 4565 %} | |
| 4566 | |
| 4567 operand iRegNsrc() %{ | |
| 4568 constraint(ALLOC_IN_RC(bits32_reg_ro)); | |
| 4569 match(RegN); | |
| 4570 match(iRegNdst); | |
| 4571 | |
| 4572 format %{ %} | |
| 4573 interface(REG_INTER); | |
| 4574 %} | |
| 4575 | |
| 4576 operand iRegNdst() %{ | |
| 4577 constraint(ALLOC_IN_RC(bits32_reg_rw)); | |
| 4578 match(RegN); | |
| 4579 | |
| 4580 format %{ %} | |
| 4581 interface(REG_INTER); | |
| 4582 %} | |
| 4583 | |
| 4584 // Long Destination Register | |
| 4585 // See definition of reg_class bits64_reg_rw. | |
| 4586 operand iRegLdst() %{ | |
| 4587 constraint(ALLOC_IN_RC(bits64_reg_rw)); | |
| 4588 match(RegL); | |
| 4589 match(rscratch1RegL); | |
| 4590 match(rscratch2RegL); | |
| 4591 format %{ %} | |
| 4592 interface(REG_INTER); | |
| 4593 %} | |
| 4594 | |
| 4595 // Long Source Register | |
| 4596 // See definition of reg_class bits64_reg_ro. | |
| 4597 operand iRegLsrc() %{ | |
| 4598 constraint(ALLOC_IN_RC(bits64_reg_ro)); | |
| 4599 match(RegL); | |
| 4600 match(iRegLdst); | |
| 4601 match(rscratch1RegL); | |
| 4602 match(rscratch2RegL); | |
| 4603 format %{ %} | |
| 4604 interface(REG_INTER); | |
| 4605 %} | |
| 4606 | |
| 4607 // Special operand for ConvL2I. | |
| 4608 operand iRegL2Isrc(iRegLsrc reg) %{ | |
| 4609 constraint(ALLOC_IN_RC(bits64_reg_ro)); | |
| 4610 match(ConvL2I reg); | |
| 4611 format %{ "ConvL2I($reg)" %} | |
| 4612 interface(REG_INTER) | |
| 4613 %} | |
| 4614 | |
| 4615 operand rscratch1RegL() %{ | |
| 4616 constraint(ALLOC_IN_RC(rscratch1_bits64_reg)); | |
| 4617 match(RegL); | |
| 4618 format %{ %} | |
| 4619 interface(REG_INTER); | |
| 4620 %} | |
| 4621 | |
| 4622 operand rscratch2RegL() %{ | |
| 4623 constraint(ALLOC_IN_RC(rscratch2_bits64_reg)); | |
| 4624 match(RegL); | |
| 4625 format %{ %} | |
| 4626 interface(REG_INTER); | |
| 4627 %} | |
| 4628 | |
| 4629 // Condition Code Flag Registers | |
| 4630 operand flagsReg() %{ | |
| 4631 constraint(ALLOC_IN_RC(int_flags)); | |
| 4632 match(RegFlags); | |
| 4633 format %{ %} | |
| 4634 interface(REG_INTER); | |
| 4635 %} | |
| 4636 | |
| 4637 // Condition Code Flag Register CR0 | |
| 4638 operand flagsRegCR0() %{ | |
| 4639 constraint(ALLOC_IN_RC(int_flags_CR0)); | |
| 4640 match(RegFlags); | |
| 4641 format %{ "CR0" %} | |
| 4642 interface(REG_INTER); | |
| 4643 %} | |
| 4644 | |
| 4645 operand flagsRegCR1() %{ | |
| 4646 constraint(ALLOC_IN_RC(int_flags_CR1)); | |
| 4647 match(RegFlags); | |
| 4648 format %{ "CR1" %} | |
| 4649 interface(REG_INTER); | |
| 4650 %} | |
| 4651 | |
| 4652 operand flagsRegCR6() %{ | |
| 4653 constraint(ALLOC_IN_RC(int_flags_CR6)); | |
| 4654 match(RegFlags); | |
| 4655 format %{ "CR6" %} | |
| 4656 interface(REG_INTER); | |
| 4657 %} | |
| 4658 | |
| 4659 operand regCTR() %{ | |
| 4660 constraint(ALLOC_IN_RC(ctr_reg)); | |
| 4661 // RegFlags should work. Introducing a RegSpecial type would cause a | |
| 4662 // lot of changes. | |
| 4663 match(RegFlags); | |
| 4664 format %{"SR_CTR" %} | |
| 4665 interface(REG_INTER); | |
| 4666 %} | |
| 4667 | |
| 4668 operand regD() %{ | |
| 4669 constraint(ALLOC_IN_RC(dbl_reg)); | |
| 4670 match(RegD); | |
| 4671 format %{ %} | |
| 4672 interface(REG_INTER); | |
| 4673 %} | |
| 4674 | |
| 4675 operand regF() %{ | |
| 4676 constraint(ALLOC_IN_RC(flt_reg)); | |
| 4677 match(RegF); | |
| 4678 format %{ %} | |
| 4679 interface(REG_INTER); | |
| 4680 %} | |
| 4681 | |
| 4682 // Special Registers | |
| 4683 | |
| 4684 // Method Register | |
| 4685 operand inline_cache_regP(iRegPdst reg) %{ | |
| 4686 constraint(ALLOC_IN_RC(r19_bits64_reg)); // inline_cache_reg | |
| 4687 match(reg); | |
| 4688 format %{ %} | |
| 4689 interface(REG_INTER); | |
| 4690 %} | |
| 4691 | |
| 4692 operand compiler_method_oop_regP(iRegPdst reg) %{ | |
| 4693 constraint(ALLOC_IN_RC(rscratch1_bits64_reg)); // compiler_method_oop_reg | |
| 4694 match(reg); | |
| 4695 format %{ %} | |
| 4696 interface(REG_INTER); | |
| 4697 %} | |
| 4698 | |
| 4699 operand interpreter_method_oop_regP(iRegPdst reg) %{ | |
| 4700 constraint(ALLOC_IN_RC(r19_bits64_reg)); // interpreter_method_oop_reg | |
| 4701 match(reg); | |
| 4702 format %{ %} | |
| 4703 interface(REG_INTER); | |
| 4704 %} | |
| 4705 | |
| 4706 // Operands to remove register moves in unscaled mode. | |
| 4707 // Match read/write registers with an EncodeP node if neither shift nor add are required. | |
| 4708 operand iRegP2N(iRegPsrc reg) %{ | |
| 4709 predicate(false /* TODO: PPC port MatchDecodeNodes*/&& Universe::narrow_oop_shift() == 0); | |
| 4710 constraint(ALLOC_IN_RC(bits64_reg_ro)); | |
| 4711 match(EncodeP reg); | |
| 4712 format %{ "$reg" %} | |
| 4713 interface(REG_INTER) | |
| 4714 %} | |
| 4715 | |
| 4716 operand iRegN2P(iRegNsrc reg) %{ | |
| 4717 predicate(false /* TODO: PPC port MatchDecodeNodes*/); | |
| 4718 constraint(ALLOC_IN_RC(bits32_reg_ro)); | |
| 4719 match(DecodeN reg); | |
| 4720 match(DecodeNKlass reg); | |
| 4721 format %{ "$reg" %} | |
| 4722 interface(REG_INTER) | |
| 4723 %} | |
| 4724 | |
| 4725 //----------Complex Operands--------------------------------------------------- | |
| 4726 // Indirect Memory Reference | |
| 4727 operand indirect(iRegPsrc reg) %{ | |
| 4728 constraint(ALLOC_IN_RC(bits64_reg_ro)); | |
| 4729 match(reg); | |
| 4730 op_cost(100); | |
| 4731 format %{ "[$reg]" %} | |
| 4732 interface(MEMORY_INTER) %{ | |
| 4733 base($reg); | |
| 4734 index(0x0); | |
| 4735 scale(0x0); | |
| 4736 disp(0x0); | |
| 4737 %} | |
| 4738 %} | |
| 4739 | |
| 4740 // Indirect with Offset | |
| 4741 operand indOffset16(iRegPsrc reg, immL16 offset) %{ | |
| 4742 constraint(ALLOC_IN_RC(bits64_reg_ro)); | |
| 4743 match(AddP reg offset); | |
| 4744 op_cost(100); | |
| 4745 format %{ "[$reg + $offset]" %} | |
| 4746 interface(MEMORY_INTER) %{ | |
| 4747 base($reg); | |
| 4748 index(0x0); | |
| 4749 scale(0x0); | |
| 4750 disp($offset); | |
| 4751 %} | |
| 4752 %} | |
| 4753 | |
| 4754 // Indirect with 4-aligned Offset | |
| 4755 operand indOffset16Alg4(iRegPsrc reg, immL16Alg4 offset) %{ | |
| 4756 constraint(ALLOC_IN_RC(bits64_reg_ro)); | |
| 4757 match(AddP reg offset); | |
| 4758 op_cost(100); | |
| 4759 format %{ "[$reg + $offset]" %} | |
| 4760 interface(MEMORY_INTER) %{ | |
| 4761 base($reg); | |
| 4762 index(0x0); | |
| 4763 scale(0x0); | |
| 4764 disp($offset); | |
| 4765 %} | |
| 4766 %} | |
| 4767 | |
| 4768 //----------Complex Operands for Compressed OOPs------------------------------- | |
| 4769 // Compressed OOPs with narrow_oop_shift == 0. | |
| 4770 | |
| 4771 // Indirect Memory Reference, compressed OOP | |
| 4772 operand indirectNarrow(iRegNsrc reg) %{ | |
| 4773 predicate(false /* TODO: PPC port MatchDecodeNodes*/); | |
| 4774 constraint(ALLOC_IN_RC(bits64_reg_ro)); | |
| 4775 match(DecodeN reg); | |
| 4776 match(DecodeNKlass reg); | |
| 4777 op_cost(100); | |
| 4778 format %{ "[$reg]" %} | |
| 4779 interface(MEMORY_INTER) %{ | |
| 4780 base($reg); | |
| 4781 index(0x0); | |
| 4782 scale(0x0); | |
| 4783 disp(0x0); | |
| 4784 %} | |
| 4785 %} | |
| 4786 | |
| 4787 // Indirect with Offset, compressed OOP | |
| 4788 operand indOffset16Narrow(iRegNsrc reg, immL16 offset) %{ | |
| 4789 predicate(false /* TODO: PPC port MatchDecodeNodes*/); | |
| 4790 constraint(ALLOC_IN_RC(bits64_reg_ro)); | |
| 4791 match(AddP (DecodeN reg) offset); | |
| 4792 match(AddP (DecodeNKlass reg) offset); | |
| 4793 op_cost(100); | |
| 4794 format %{ "[$reg + $offset]" %} | |
| 4795 interface(MEMORY_INTER) %{ | |
| 4796 base($reg); | |
| 4797 index(0x0); | |
| 4798 scale(0x0); | |
| 4799 disp($offset); | |
| 4800 %} | |
| 4801 %} | |
| 4802 | |
| 4803 // Indirect with 4-aligned Offset, compressed OOP | |
| 4804 operand indOffset16NarrowAlg4(iRegNsrc reg, immL16Alg4 offset) %{ | |
| 4805 predicate(false /* TODO: PPC port MatchDecodeNodes*/); | |
| 4806 constraint(ALLOC_IN_RC(bits64_reg_ro)); | |
| 4807 match(AddP (DecodeN reg) offset); | |
| 4808 match(AddP (DecodeNKlass reg) offset); | |
| 4809 op_cost(100); | |
| 4810 format %{ "[$reg + $offset]" %} | |
| 4811 interface(MEMORY_INTER) %{ | |
| 4812 base($reg); | |
| 4813 index(0x0); | |
| 4814 scale(0x0); | |
| 4815 disp($offset); | |
| 4816 %} | |
| 4817 %} | |
| 4818 | |
| 4819 //----------Special Memory Operands-------------------------------------------- | |
| 4820 // Stack Slot Operand | |
| 4821 // | |
| 4822 // This operand is used for loading and storing temporary values on | |
| 4823 // the stack where a match requires a value to flow through memory. | |
| 4824 operand stackSlotI(sRegI reg) %{ | |
| 4825 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4826 op_cost(100); | |
| 4827 //match(RegI); | |
| 4828 format %{ "[sp+$reg]" %} | |
| 4829 interface(MEMORY_INTER) %{ | |
| 4830 base(0x1); // R1_SP | |
| 4831 index(0x0); | |
| 4832 scale(0x0); | |
| 4833 disp($reg); // Stack Offset | |
| 4834 %} | |
| 4835 %} | |
| 4836 | |
| 4837 operand stackSlotL(sRegL reg) %{ | |
| 4838 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4839 op_cost(100); | |
| 4840 //match(RegL); | |
| 4841 format %{ "[sp+$reg]" %} | |
| 4842 interface(MEMORY_INTER) %{ | |
| 4843 base(0x1); // R1_SP | |
| 4844 index(0x0); | |
| 4845 scale(0x0); | |
| 4846 disp($reg); // Stack Offset | |
| 4847 %} | |
| 4848 %} | |
| 4849 | |
| 4850 operand stackSlotP(sRegP reg) %{ | |
| 4851 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4852 op_cost(100); | |
| 4853 //match(RegP); | |
| 4854 format %{ "[sp+$reg]" %} | |
| 4855 interface(MEMORY_INTER) %{ | |
| 4856 base(0x1); // R1_SP | |
| 4857 index(0x0); | |
| 4858 scale(0x0); | |
| 4859 disp($reg); // Stack Offset | |
| 4860 %} | |
| 4861 %} | |
| 4862 | |
| 4863 operand stackSlotF(sRegF reg) %{ | |
| 4864 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4865 op_cost(100); | |
| 4866 //match(RegF); | |
| 4867 format %{ "[sp+$reg]" %} | |
| 4868 interface(MEMORY_INTER) %{ | |
| 4869 base(0x1); // R1_SP | |
| 4870 index(0x0); | |
| 4871 scale(0x0); | |
| 4872 disp($reg); // Stack Offset | |
| 4873 %} | |
| 4874 %} | |
| 4875 | |
| 4876 operand stackSlotD(sRegD reg) %{ | |
| 4877 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4878 op_cost(100); | |
| 4879 //match(RegD); | |
| 4880 format %{ "[sp+$reg]" %} | |
| 4881 interface(MEMORY_INTER) %{ | |
| 4882 base(0x1); // R1_SP | |
| 4883 index(0x0); | |
| 4884 scale(0x0); | |
| 4885 disp($reg); // Stack Offset | |
| 4886 %} | |
| 4887 %} | |
| 4888 | |
| 4889 // Operands for expressing Control Flow | |
| 4890 // NOTE: Label is a predefined operand which should not be redefined in | |
| 4891 // the AD file. It is generically handled within the ADLC. | |
| 4892 | |
| 4893 //----------Conditional Branch Operands---------------------------------------- | |
| 4894 // Comparison Op | |
| 4895 // | |
| 4896 // This is the operation of the comparison, and is limited to the | |
| 4897 // following set of codes: L (<), LE (<=), G (>), GE (>=), E (==), NE | |
| 4898 // (!=). | |
| 4899 // | |
| 4900 // Other attributes of the comparison, such as unsignedness, are specified | |
| 4901 // by the comparison instruction that sets a condition code flags register. | |
| 4902 // That result is represented by a flags operand whose subtype is appropriate | |
| 4903 // to the unsignedness (etc.) of the comparison. | |
| 4904 // | |
| 4905 // Later, the instruction which matches both the Comparison Op (a Bool) and | |
| 4906 // the flags (produced by the Cmp) specifies the coding of the comparison op | |
| 4907 // by matching a specific subtype of Bool operand below. | |
| 4908 | |
| 4909 // When used for floating point comparisons: unordered same as less. | |
| 4910 operand cmpOp() %{ | |
| 4911 match(Bool); | |
| 4912 format %{ "" %} | |
| 4913 interface(COND_INTER) %{ | |
| 4914 // BO only encodes bit 4 of bcondCRbiIsX, as bits 1-3 are always '100'. | |
| 4915 // BO & BI | |
| 4916 equal(0xA); // 10 10: bcondCRbiIs1 & Condition::equal | |
| 4917 not_equal(0x2); // 00 10: bcondCRbiIs0 & Condition::equal | |
| 4918 less(0x8); // 10 00: bcondCRbiIs1 & Condition::less | |
| 4919 greater_equal(0x0); // 00 00: bcondCRbiIs0 & Condition::less | |
| 4920 less_equal(0x1); // 00 01: bcondCRbiIs0 & Condition::greater | |
| 4921 greater(0x9); // 10 01: bcondCRbiIs1 & Condition::greater | |
| 4922 overflow(0xB); // 10 11: bcondCRbiIs1 & Condition::summary_overflow | |
| 4923 no_overflow(0x3); // 00 11: bcondCRbiIs0 & Condition::summary_overflow | |
| 4924 %} | |
| 4925 %} | |
| 4926 | |
| 4927 //----------OPERAND CLASSES---------------------------------------------------- | |
| 4928 // Operand Classes are groups of operands that are used to simplify | |
| 4929 // instruction definitions by not requiring the AD writer to specify | |
| 4930 // seperate instructions for every form of operand when the | |
| 4931 // instruction accepts multiple operand types with the same basic | |
| 4932 // encoding and format. The classic case of this is memory operands. | |
| 4933 // Indirect is not included since its use is limited to Compare & Swap. | |
| 4934 | |
| 4935 opclass memory(indirect, indOffset16 /*, indIndex, tlsReference*/, indirectNarrow, indOffset16Narrow); | |
| 4936 // Memory operand where offsets are 4-aligned. Required for ld, std. | |
| 4937 opclass memoryAlg4(indirect, indOffset16Alg4, indirectNarrow, indOffset16NarrowAlg4); | |
| 4938 opclass indirectMemory(indirect, indirectNarrow); | |
| 4939 | |
| 4940 // Special opclass for I and ConvL2I. | |
| 4941 opclass iRegIsrc_iRegL2Isrc(iRegIsrc, iRegL2Isrc); | |
| 4942 | |
| 4943 // Operand classes to match encode and decode. iRegN_P2N is only used | |
| 4944 // for storeN. I have never seen an encode node elsewhere. | |
| 4945 opclass iRegN_P2N(iRegNsrc, iRegP2N); | |
| 4946 opclass iRegP_N2P(iRegPsrc, iRegN2P); | |
| 4947 | |
| 4948 //----------PIPELINE----------------------------------------------------------- | |
| 4949 | |
| 4950 pipeline %{ | |
| 4951 | |
| 4952 // See J.M.Tendler et al. "Power4 system microarchitecture", IBM | |
| 4953 // J. Res. & Dev., No. 1, Jan. 2002. | |
| 4954 | |
| 4955 //----------ATTRIBUTES--------------------------------------------------------- | |
| 4956 attributes %{ | |
| 4957 | |
| 4958 // Power4 instructions are of fixed length. | |
| 4959 fixed_size_instructions; | |
| 4960 | |
| 4961 // TODO: if `bundle' means number of instructions fetched | |
| 4962 // per cycle, this is 8. If `bundle' means Power4 `group', that is | |
| 4963 // max instructions issued per cycle, this is 5. | |
| 4964 max_instructions_per_bundle = 8; | |
| 4965 | |
| 4966 // A Power4 instruction is 4 bytes long. | |
| 4967 instruction_unit_size = 4; | |
| 4968 | |
| 4969 // The Power4 processor fetches 64 bytes... | |
| 4970 instruction_fetch_unit_size = 64; | |
| 4971 | |
| 4972 // ...in one line | |
| 4973 instruction_fetch_units = 1 | |
| 4974 | |
| 4975 // Unused, list one so that array generated by adlc is not empty. | |
| 4976 // Aix compiler chokes if _nop_count = 0. | |
| 4977 nops(fxNop); | |
| 4978 %} | |
| 4979 | |
| 4980 //----------RESOURCES---------------------------------------------------------- | |
| 4981 // Resources are the functional units available to the machine | |
| 4982 resources( | |
| 4983 PPC_BR, // branch unit | |
| 4984 PPC_CR, // condition unit | |
| 4985 PPC_FX1, // integer arithmetic unit 1 | |
| 4986 PPC_FX2, // integer arithmetic unit 2 | |
| 4987 PPC_LDST1, // load/store unit 1 | |
| 4988 PPC_LDST2, // load/store unit 2 | |
| 4989 PPC_FP1, // float arithmetic unit 1 | |
| 4990 PPC_FP2, // float arithmetic unit 2 | |
| 4991 PPC_LDST = PPC_LDST1 | PPC_LDST2, | |
| 4992 PPC_FX = PPC_FX1 | PPC_FX2, | |
| 4993 PPC_FP = PPC_FP1 | PPC_FP2 | |
| 4994 ); | |
| 4995 | |
| 4996 //----------PIPELINE DESCRIPTION----------------------------------------------- | |
| 4997 // Pipeline Description specifies the stages in the machine's pipeline | |
| 4998 pipe_desc( | |
| 4999 // Power4 longest pipeline path | |
| 5000 PPC_IF, // instruction fetch | |
| 5001 PPC_IC, | |
| 5002 //PPC_BP, // branch prediction | |
| 5003 PPC_D0, // decode | |
| 5004 PPC_D1, // decode | |
| 5005 PPC_D2, // decode | |
| 5006 PPC_D3, // decode | |
| 5007 PPC_Xfer1, | |
| 5008 PPC_GD, // group definition | |
| 5009 PPC_MP, // map | |
| 5010 PPC_ISS, // issue | |
| 5011 PPC_RF, // resource fetch | |
| 5012 PPC_EX1, // execute (all units) | |
| 5013 PPC_EX2, // execute (FP, LDST) | |
| 5014 PPC_EX3, // execute (FP, LDST) | |
| 5015 PPC_EX4, // execute (FP) | |
| 5016 PPC_EX5, // execute (FP) | |
| 5017 PPC_EX6, // execute (FP) | |
| 5018 PPC_WB, // write back | |
| 5019 PPC_Xfer2, | |
| 5020 PPC_CP | |
| 5021 ); | |
| 5022 | |
| 5023 //----------PIPELINE CLASSES--------------------------------------------------- | |
| 5024 // Pipeline Classes describe the stages in which input and output are | |
| 5025 // referenced by the hardware pipeline. | |
| 5026 | |
| 5027 // Simple pipeline classes. | |
| 5028 | |
| 5029 // Default pipeline class. | |
| 5030 pipe_class pipe_class_default() %{ | |
| 5031 single_instruction; | |
| 5032 fixed_latency(2); | |
| 5033 %} | |
| 5034 | |
| 5035 // Pipeline class for empty instructions. | |
| 5036 pipe_class pipe_class_empty() %{ | |
| 5037 single_instruction; | |
| 5038 fixed_latency(0); | |
| 5039 %} | |
| 5040 | |
| 5041 // Pipeline class for compares. | |
| 5042 pipe_class pipe_class_compare() %{ | |
| 5043 single_instruction; | |
| 5044 fixed_latency(16); | |
| 5045 %} | |
| 5046 | |
| 5047 // Pipeline class for traps. | |
| 5048 pipe_class pipe_class_trap() %{ | |
| 5049 single_instruction; | |
| 5050 fixed_latency(100); | |
| 5051 %} | |
| 5052 | |
| 5053 // Pipeline class for memory operations. | |
| 5054 pipe_class pipe_class_memory() %{ | |
| 5055 single_instruction; | |
| 5056 fixed_latency(16); | |
| 5057 %} | |
| 5058 | |
| 5059 // Pipeline class for call. | |
| 5060 pipe_class pipe_class_call() %{ | |
| 5061 single_instruction; | |
| 5062 fixed_latency(100); | |
| 5063 %} | |
| 5064 | |
| 5065 // Define the class for the Nop node. | |
| 5066 define %{ | |
| 5067 MachNop = pipe_class_default; | |
| 5068 %} | |
| 5069 | |
| 5070 %} | |
| 5071 | |
| 5072 //----------INSTRUCTIONS------------------------------------------------------- | |
| 5073 | |
| 5074 // Naming of instructions: | |
| 5075 // opA_operB / opA_operB_operC: | |
| 5076 // Operation 'op' with one or two source operands 'oper'. Result | |
| 5077 // type is A, source operand types are B and C. | |
| 5078 // Iff A == B == C, B and C are left out. | |
| 5079 // | |
| 5080 // The instructions are ordered according to the following scheme: | |
| 5081 // - loads | |
| 5082 // - load constants | |
| 5083 // - prefetch | |
| 5084 // - store | |
| 5085 // - encode/decode | |
| 5086 // - membar | |
| 5087 // - conditional moves | |
| 5088 // - compare & swap | |
| 5089 // - arithmetic and logic operations | |
| 5090 // * int: Add, Sub, Mul, Div, Mod | |
| 5091 // * int: lShift, arShift, urShift, rot | |
| 5092 // * float: Add, Sub, Mul, Div | |
| 5093 // * and, or, xor ... | |
| 5094 // - register moves: float <-> int, reg <-> stack, repl | |
| 5095 // - cast (high level type cast, XtoP, castPP, castII, not_null etc. | |
| 5096 // - conv (low level type cast requiring bit changes (sign extend etc) | |
| 5097 // - compares, range & zero checks. | |
| 5098 // - branches | |
| 5099 // - complex operations, intrinsics, min, max, replicate | |
| 5100 // - lock | |
| 5101 // - Calls | |
| 5102 // | |
| 5103 // If there are similar instructions with different types they are sorted: | |
| 5104 // int before float | |
| 5105 // small before big | |
| 5106 // signed before unsigned | |
| 5107 // e.g., loadS before loadUS before loadI before loadF. | |
| 5108 | |
| 5109 | |
| 5110 //----------Load/Store Instructions-------------------------------------------- | |
| 5111 | |
| 5112 //----------Load Instructions-------------------------------------------------- | |
| 5113 | |
| 5114 // Converts byte to int. | |
| 5115 // As convB2I_reg, but without match rule. The match rule of convB2I_reg | |
| 5116 // reuses the 'amount' operand, but adlc expects that operand specification | |
| 5117 // and operands in match rule are equivalent. | |
| 5118 instruct convB2I_reg_2(iRegIdst dst, iRegIsrc src) %{ | |
| 5119 effect(DEF dst, USE src); | |
| 5120 format %{ "EXTSB $dst, $src \t// byte->int" %} | |
| 5121 size(4); | |
| 5122 ins_encode %{ | |
| 5123 // TODO: PPC port $archOpcode(ppc64Opcode_extsb); | |
| 5124 __ extsb($dst$$Register, $src$$Register); | |
| 5125 %} | |
| 5126 ins_pipe(pipe_class_default); | |
| 5127 %} | |
| 5128 | |
| 5129 instruct loadUB_indirect(iRegIdst dst, indirectMemory mem) %{ | |
| 5130 // match-rule, false predicate | |
| 5131 match(Set dst (LoadB mem)); | |
| 5132 predicate(false); | |
| 5133 | |
| 5134 format %{ "LBZ $dst, $mem" %} | |
| 5135 size(4); | |
| 5136 ins_encode( enc_lbz(dst, mem) ); | |
| 5137 ins_pipe(pipe_class_memory); | |
| 5138 %} | |
| 5139 | |
| 5140 instruct loadUB_indirect_ac(iRegIdst dst, indirectMemory mem) %{ | |
| 5141 // match-rule, false predicate | |
| 5142 match(Set dst (LoadB mem)); | |
| 5143 predicate(false); | |
| 5144 | |
| 5145 format %{ "LBZ $dst, $mem\n\t" | |
| 5146 "TWI $dst\n\t" | |
| 5147 "ISYNC" %} | |
| 5148 size(12); | |
| 5149 ins_encode( enc_lbz_ac(dst, mem) ); | |
| 5150 ins_pipe(pipe_class_memory); | |
| 5151 %} | |
| 5152 | |
| 5153 // Load Byte (8bit signed). LoadB = LoadUB + ConvUB2B. | |
| 5154 instruct loadB_indirect_Ex(iRegIdst dst, indirectMemory mem) %{ | |
| 5155 match(Set dst (LoadB mem)); | |
| 5156 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); | |
| 5157 ins_cost(MEMORY_REF_COST + DEFAULT_COST); | |
| 5158 expand %{ | |
| 5159 iRegIdst tmp; | |
| 5160 loadUB_indirect(tmp, mem); | |
| 5161 convB2I_reg_2(dst, tmp); | |
| 5162 %} | |
| 5163 %} | |
| 5164 | |
| 5165 instruct loadB_indirect_ac_Ex(iRegIdst dst, indirectMemory mem) %{ | |
| 5166 match(Set dst (LoadB mem)); | |
| 5167 ins_cost(3*MEMORY_REF_COST + DEFAULT_COST); | |
| 5168 expand %{ | |
| 5169 iRegIdst tmp; | |
| 5170 loadUB_indirect_ac(tmp, mem); | |
| 5171 convB2I_reg_2(dst, tmp); | |
| 5172 %} | |
| 5173 %} | |
| 5174 | |
| 5175 instruct loadUB_indOffset16(iRegIdst dst, indOffset16 mem) %{ | |
| 5176 // match-rule, false predicate | |
| 5177 match(Set dst (LoadB mem)); | |
| 5178 predicate(false); | |
| 5179 | |
| 5180 format %{ "LBZ $dst, $mem" %} | |
| 5181 size(4); | |
| 5182 ins_encode( enc_lbz(dst, mem) ); | |
| 5183 ins_pipe(pipe_class_memory); | |
| 5184 %} | |
| 5185 | |
| 5186 instruct loadUB_indOffset16_ac(iRegIdst dst, indOffset16 mem) %{ | |
| 5187 // match-rule, false predicate | |
| 5188 match(Set dst (LoadB mem)); | |
| 5189 predicate(false); | |
| 5190 | |
| 5191 format %{ "LBZ $dst, $mem\n\t" | |
| 5192 "TWI $dst\n\t" | |
| 5193 "ISYNC" %} | |
| 5194 size(12); | |
| 5195 ins_encode( enc_lbz_ac(dst, mem) ); | |
| 5196 ins_pipe(pipe_class_memory); | |
| 5197 %} | |
| 5198 | |
| 5199 // Load Byte (8bit signed). LoadB = LoadUB + ConvUB2B. | |
| 5200 instruct loadB_indOffset16_Ex(iRegIdst dst, indOffset16 mem) %{ | |
| 5201 match(Set dst (LoadB mem)); | |
| 5202 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); | |
| 5203 ins_cost(MEMORY_REF_COST + DEFAULT_COST); | |
| 5204 | |
| 5205 expand %{ | |
| 5206 iRegIdst tmp; | |
| 5207 loadUB_indOffset16(tmp, mem); | |
| 5208 convB2I_reg_2(dst, tmp); | |
| 5209 %} | |
| 5210 %} | |
| 5211 | |
| 5212 instruct loadB_indOffset16_ac_Ex(iRegIdst dst, indOffset16 mem) %{ | |
| 5213 match(Set dst (LoadB mem)); | |
| 5214 ins_cost(3*MEMORY_REF_COST + DEFAULT_COST); | |
| 5215 | |
| 5216 expand %{ | |
| 5217 iRegIdst tmp; | |
| 5218 loadUB_indOffset16_ac(tmp, mem); | |
| 5219 convB2I_reg_2(dst, tmp); | |
| 5220 %} | |
| 5221 %} | |
| 5222 | |
| 5223 // Load Unsigned Byte (8bit UNsigned) into an int reg. | |
| 5224 instruct loadUB(iRegIdst dst, memory mem) %{ | |
| 5225 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); | |
| 5226 match(Set dst (LoadUB mem)); | |
| 5227 ins_cost(MEMORY_REF_COST); | |
| 5228 | |
| 5229 format %{ "LBZ $dst, $mem \t// byte, zero-extend to int" %} | |
| 5230 size(4); | |
| 5231 ins_encode( enc_lbz(dst, mem) ); | |
| 5232 ins_pipe(pipe_class_memory); | |
| 5233 %} | |
| 5234 | |
| 5235 // Load Unsigned Byte (8bit UNsigned) acquire. | |
| 5236 instruct loadUB_ac(iRegIdst dst, memory mem) %{ | |
| 5237 match(Set dst (LoadUB mem)); | |
| 5238 ins_cost(3*MEMORY_REF_COST); | |
| 5239 | |
| 5240 format %{ "LBZ $dst, $mem \t// byte, zero-extend to int, acquire\n\t" | |
| 5241 "TWI $dst\n\t" | |
| 5242 "ISYNC" %} | |
| 5243 size(12); | |
| 5244 ins_encode( enc_lbz_ac(dst, mem) ); | |
| 5245 ins_pipe(pipe_class_memory); | |
| 5246 %} | |
| 5247 | |
| 5248 // Load Unsigned Byte (8bit UNsigned) into a Long Register. | |
| 5249 instruct loadUB2L(iRegLdst dst, memory mem) %{ | |
| 5250 match(Set dst (ConvI2L (LoadUB mem))); | |
| 5251 predicate(_kids[0]->_leaf->as_Load()->is_unordered() || followed_by_acquire(_kids[0]->_leaf)); | |
| 5252 ins_cost(MEMORY_REF_COST); | |
| 5253 | |
| 5254 format %{ "LBZ $dst, $mem \t// byte, zero-extend to long" %} | |
| 5255 size(4); | |
| 5256 ins_encode( enc_lbz(dst, mem) ); | |
| 5257 ins_pipe(pipe_class_memory); | |
| 5258 %} | |
| 5259 | |
| 5260 instruct loadUB2L_ac(iRegLdst dst, memory mem) %{ | |
| 5261 match(Set dst (ConvI2L (LoadUB mem))); | |
| 5262 ins_cost(3*MEMORY_REF_COST); | |
| 5263 | |
| 5264 format %{ "LBZ $dst, $mem \t// byte, zero-extend to long, acquire\n\t" | |
| 5265 "TWI $dst\n\t" | |
| 5266 "ISYNC" %} | |
| 5267 size(12); | |
| 5268 ins_encode( enc_lbz_ac(dst, mem) ); | |
| 5269 ins_pipe(pipe_class_memory); | |
| 5270 %} | |
| 5271 | |
| 5272 // Load Short (16bit signed) | |
| 5273 instruct loadS(iRegIdst dst, memory mem) %{ | |
| 5274 match(Set dst (LoadS mem)); | |
| 5275 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); | |
| 5276 ins_cost(MEMORY_REF_COST); | |
| 5277 | |
| 5278 format %{ "LHA $dst, $mem" %} | |
| 5279 size(4); | |
| 5280 ins_encode %{ | |
| 5281 // TODO: PPC port $archOpcode(ppc64Opcode_lha); | |
| 5282 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); | |
| 5283 __ lha($dst$$Register, Idisp, $mem$$base$$Register); | |
| 5284 %} | |
| 5285 ins_pipe(pipe_class_memory); | |
| 5286 %} | |
| 5287 | |
| 5288 // Load Short (16bit signed) acquire. | |
| 5289 instruct loadS_ac(iRegIdst dst, memory mem) %{ | |
| 5290 match(Set dst (LoadS mem)); | |
| 5291 ins_cost(3*MEMORY_REF_COST); | |
| 5292 | |
| 5293 format %{ "LHA $dst, $mem\t acquire\n\t" | |
| 5294 "TWI $dst\n\t" | |
| 5295 "ISYNC" %} | |
| 5296 size(12); | |
| 5297 ins_encode %{ | |
| 5298 // TODO: PPC port $archOpcode(ppc64Opcode_compound); | |
| 5299 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); | |
| 5300 __ lha($dst$$Register, Idisp, $mem$$base$$Register); | |
| 5301 __ twi_0($dst$$Register); | |
| 5302 __ isync(); | |
| 5303 %} | |
| 5304 ins_pipe(pipe_class_memory); | |
| 5305 %} | |
| 5306 | |
| 5307 // Load Char (16bit unsigned) | |
| 5308 instruct loadUS(iRegIdst dst, memory mem) %{ | |
| 5309 match(Set dst (LoadUS mem)); | |
| 5310 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); | |
| 5311 ins_cost(MEMORY_REF_COST); | |
| 5312 | |
| 5313 format %{ "LHZ $dst, $mem" %} | |
| 5314 size(4); | |
| 5315 ins_encode( enc_lhz(dst, mem) ); | |
| 5316 ins_pipe(pipe_class_memory); | |
| 5317 %} | |
| 5318 | |
| 5319 // Load Char (16bit unsigned) acquire. | |
| 5320 instruct loadUS_ac(iRegIdst dst, memory mem) %{ | |
| 5321 match(Set dst (LoadUS mem)); | |
| 5322 ins_cost(3*MEMORY_REF_COST); | |
| 5323 | |
| 5324 format %{ "LHZ $dst, $mem \t// acquire\n\t" | |
| 5325 "TWI $dst\n\t" | |
| 5326 "ISYNC" %} | |
| 5327 size(12); | |
| 5328 ins_encode( enc_lhz_ac(dst, mem) ); | |
| 5329 ins_pipe(pipe_class_memory); | |
| 5330 %} | |
| 5331 | |
| 5332 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register. | |
| 5333 instruct loadUS2L(iRegLdst dst, memory mem) %{ | |
| 5334 match(Set dst (ConvI2L (LoadUS mem))); | |
| 5335 predicate(_kids[0]->_leaf->as_Load()->is_unordered() || followed_by_acquire(_kids[0]->_leaf)); | |
| 5336 ins_cost(MEMORY_REF_COST); | |
| 5337 | |
| 5338 format %{ "LHZ $dst, $mem \t// short, zero-extend to long" %} | |
| 5339 size(4); | |
| 5340 ins_encode( enc_lhz(dst, mem) ); | |
| 5341 ins_pipe(pipe_class_memory); | |
| 5342 %} | |
| 5343 | |
| 5344 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register acquire. | |
| 5345 instruct loadUS2L_ac(iRegLdst dst, memory mem) %{ | |
| 5346 match(Set dst (ConvI2L (LoadUS mem))); | |
| 5347 ins_cost(3*MEMORY_REF_COST); | |
| 5348 | |
| 5349 format %{ "LHZ $dst, $mem \t// short, zero-extend to long, acquire\n\t" | |
| 5350 "TWI $dst\n\t" | |
| 5351 "ISYNC" %} | |
| 5352 size(12); | |
| 5353 ins_encode( enc_lhz_ac(dst, mem) ); | |
| 5354 ins_pipe(pipe_class_memory); | |
| 5355 %} | |
| 5356 | |
| 5357 // Load Integer. | |
| 5358 instruct loadI(iRegIdst dst, memory mem) %{ | |
| 5359 match(Set dst (LoadI mem)); | |
| 5360 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); | |
| 5361 ins_cost(MEMORY_REF_COST); | |
| 5362 | |
| 5363 format %{ "LWZ $dst, $mem" %} | |
| 5364 size(4); | |
| 5365 ins_encode( enc_lwz(dst, mem) ); | |
| 5366 ins_pipe(pipe_class_memory); | |
| 5367 %} | |
| 5368 | |
| 5369 // Load Integer acquire. | |
| 5370 instruct loadI_ac(iRegIdst dst, memory mem) %{ | |
| 5371 match(Set dst (LoadI mem)); | |
| 5372 ins_cost(3*MEMORY_REF_COST); | |
| 5373 | |
| 5374 format %{ "LWZ $dst, $mem \t// load acquire\n\t" | |
| 5375 "TWI $dst\n\t" | |
| 5376 "ISYNC" %} | |
| 5377 size(12); | |
| 5378 ins_encode( enc_lwz_ac(dst, mem) ); | |
| 5379 ins_pipe(pipe_class_memory); | |
| 5380 %} | |
| 5381 | |
| 5382 // Match loading integer and casting it to unsigned int in | |
| 5383 // long register. | |
| 5384 // LoadI + ConvI2L + AndL 0xffffffff. | |
| 5385 instruct loadUI2L(iRegLdst dst, memory mem, immL_32bits mask) %{ | |
| 5386 match(Set dst (AndL (ConvI2L (LoadI mem)) mask)); | |
| 5387 predicate(_kids[0]->_kids[0]->_leaf->as_Load()->is_unordered()); | |
| 5388 ins_cost(MEMORY_REF_COST); | |
| 5389 | |
| 5390 format %{ "LWZ $dst, $mem \t// zero-extend to long" %} | |
| 5391 size(4); | |
| 5392 ins_encode( enc_lwz(dst, mem) ); | |
| 5393 ins_pipe(pipe_class_memory); | |
| 5394 %} | |
| 5395 | |
| 5396 // Match loading integer and casting it to long. | |
| 5397 instruct loadI2L(iRegLdst dst, memory mem) %{ | |
| 5398 match(Set dst (ConvI2L (LoadI mem))); | |
| 5399 predicate(_kids[0]->_leaf->as_Load()->is_unordered()); | |
| 5400 ins_cost(MEMORY_REF_COST); | |
| 5401 | |
| 5402 format %{ "LWA $dst, $mem \t// loadI2L" %} | |
| 5403 size(4); | |
| 5404 ins_encode %{ | |
| 5405 // TODO: PPC port $archOpcode(ppc64Opcode_lwa); | |
| 5406 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); | |
| 5407 __ lwa($dst$$Register, Idisp, $mem$$base$$Register); | |
| 5408 %} | |
| 5409 ins_pipe(pipe_class_memory); | |
| 5410 %} | |
| 5411 | |
| 5412 // Match loading integer and casting it to long - acquire. | |
| 5413 instruct loadI2L_ac(iRegLdst dst, memory mem) %{ | |
| 5414 match(Set dst (ConvI2L (LoadI mem))); | |
| 5415 ins_cost(3*MEMORY_REF_COST); | |
| 5416 | |
| 5417 format %{ "LWA $dst, $mem \t// loadI2L acquire" | |
| 5418 "TWI $dst\n\t" | |
| 5419 "ISYNC" %} | |
| 5420 size(12); | |
| 5421 ins_encode %{ | |
| 5422 // TODO: PPC port $archOpcode(ppc64Opcode_lwa); | |
| 5423 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); | |
| 5424 __ lwa($dst$$Register, Idisp, $mem$$base$$Register); | |
| 5425 __ twi_0($dst$$Register); | |
| 5426 __ isync(); | |
| 5427 %} | |
| 5428 ins_pipe(pipe_class_memory); | |
| 5429 %} | |
| 5430 | |
| 5431 // Load Long - aligned | |
| 5432 instruct loadL(iRegLdst dst, memoryAlg4 mem) %{ | |
| 5433 match(Set dst (LoadL mem)); | |
| 5434 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); | |
| 5435 ins_cost(MEMORY_REF_COST); | |
| 5436 | |
| 5437 format %{ "LD $dst, $mem \t// long" %} | |
| 5438 size(4); | |
| 5439 ins_encode( enc_ld(dst, mem) ); | |
| 5440 ins_pipe(pipe_class_memory); | |
| 5441 %} | |
| 5442 | |
| 5443 // Load Long - aligned acquire. | |
| 5444 instruct loadL_ac(iRegLdst dst, memoryAlg4 mem) %{ | |
| 5445 match(Set dst (LoadL mem)); | |
| 5446 ins_cost(3*MEMORY_REF_COST); | |
| 5447 | |
| 5448 format %{ "LD $dst, $mem \t// long acquire\n\t" | |
| 5449 "TWI $dst\n\t" | |
| 5450 "ISYNC" %} | |
| 5451 size(12); | |
| 5452 ins_encode( enc_ld_ac(dst, mem) ); | |
| 5453 ins_pipe(pipe_class_memory); | |
| 5454 %} | |
| 5455 | |
| 5456 // Load Long - UNaligned | |
| 5457 instruct loadL_unaligned(iRegLdst dst, memoryAlg4 mem) %{ | |
| 5458 match(Set dst (LoadL_unaligned mem)); | |
| 5459 // predicate(...) // Unaligned_ac is not needed (and wouldn't make sense). | |
| 5460 ins_cost(MEMORY_REF_COST); | |
| 5461 | |
| 5462 format %{ "LD $dst, $mem \t// unaligned long" %} | |
| 5463 size(4); | |
| 5464 ins_encode( enc_ld(dst, mem) ); | |
| 5465 ins_pipe(pipe_class_memory); | |
| 5466 %} | |
| 5467 | |
| 5468 // Load nodes for superwords | |
| 5469 | |
| 5470 // Load Aligned Packed Byte | |
| 5471 instruct loadV8(iRegLdst dst, memoryAlg4 mem) %{ | |
| 5472 predicate(n->as_LoadVector()->memory_size() == 8); | |
| 5473 match(Set dst (LoadVector mem)); | |
| 5474 ins_cost(MEMORY_REF_COST); | |
| 5475 | |
| 5476 format %{ "LD $dst, $mem \t// load 8-byte Vector" %} | |
| 5477 size(4); | |
| 5478 ins_encode( enc_ld(dst, mem) ); | |
| 5479 ins_pipe(pipe_class_memory); | |
| 5480 %} | |
| 5481 | |
| 5482 // Load Range, range = array length (=jint) | |
| 5483 instruct loadRange(iRegIdst dst, memory mem) %{ | |
| 5484 match(Set dst (LoadRange mem)); | |
| 5485 ins_cost(MEMORY_REF_COST); | |
| 5486 | |
| 5487 format %{ "LWZ $dst, $mem \t// range" %} | |
| 5488 size(4); | |
| 5489 ins_encode( enc_lwz(dst, mem) ); | |
| 5490 ins_pipe(pipe_class_memory); | |
| 5491 %} | |
| 5492 | |
| 5493 // Load Compressed Pointer | |
| 5494 instruct loadN(iRegNdst dst, memory mem) %{ | |
| 5495 match(Set dst (LoadN mem)); | |
| 5496 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); | |
| 5497 ins_cost(MEMORY_REF_COST); | |
| 5498 | |
| 5499 format %{ "LWZ $dst, $mem \t// load compressed ptr" %} | |
| 5500 size(4); | |
| 5501 ins_encode( enc_lwz(dst, mem) ); | |
| 5502 ins_pipe(pipe_class_memory); | |
| 5503 %} | |
| 5504 | |
| 5505 // Load Compressed Pointer acquire. | |
| 5506 instruct loadN_ac(iRegNdst dst, memory mem) %{ | |
| 5507 match(Set dst (LoadN mem)); | |
| 5508 ins_cost(3*MEMORY_REF_COST); | |
| 5509 | |
| 5510 format %{ "LWZ $dst, $mem \t// load acquire compressed ptr\n\t" | |
| 5511 "TWI $dst\n\t" | |
| 5512 "ISYNC" %} | |
| 5513 size(12); | |
| 5514 ins_encode( enc_lwz_ac(dst, mem) ); | |
| 5515 ins_pipe(pipe_class_memory); | |
| 5516 %} | |
| 5517 | |
| 5518 // Load Compressed Pointer and decode it if narrow_oop_shift == 0. | |
| 5519 instruct loadN2P_unscaled(iRegPdst dst, memory mem) %{ | |
| 5520 match(Set dst (DecodeN (LoadN mem))); | |
| 5521 predicate(_kids[0]->_leaf->as_Load()->is_unordered() && Universe::narrow_oop_shift() == 0); | |
| 5522 ins_cost(MEMORY_REF_COST); | |
| 5523 | |
| 5524 format %{ "LWZ $dst, $mem \t// DecodeN (unscaled)" %} | |
| 5525 size(4); | |
| 5526 ins_encode( enc_lwz(dst, mem) ); | |
| 5527 ins_pipe(pipe_class_memory); | |
| 5528 %} | |
| 5529 | |
| 5530 // Load Pointer | |
| 5531 instruct loadP(iRegPdst dst, memoryAlg4 mem) %{ | |
| 5532 match(Set dst (LoadP mem)); | |
| 5533 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); | |
| 5534 ins_cost(MEMORY_REF_COST); | |
| 5535 | |
| 5536 format %{ "LD $dst, $mem \t// ptr" %} | |
| 5537 size(4); | |
| 5538 ins_encode( enc_ld(dst, mem) ); | |
| 5539 ins_pipe(pipe_class_memory); | |
| 5540 %} | |
| 5541 | |
| 5542 // Load Pointer acquire. | |
| 5543 instruct loadP_ac(iRegPdst dst, memoryAlg4 mem) %{ | |
| 5544 match(Set dst (LoadP mem)); | |
| 5545 ins_cost(3*MEMORY_REF_COST); | |
| 5546 | |
| 5547 format %{ "LD $dst, $mem \t// ptr acquire\n\t" | |
| 5548 "TWI $dst\n\t" | |
| 5549 "ISYNC" %} | |
| 5550 size(12); | |
| 5551 ins_encode( enc_ld_ac(dst, mem) ); | |
| 5552 ins_pipe(pipe_class_memory); | |
| 5553 %} | |
| 5554 | |
| 5555 // LoadP + CastP2L | |
| 5556 instruct loadP2X(iRegLdst dst, memoryAlg4 mem) %{ | |
| 5557 match(Set dst (CastP2X (LoadP mem))); | |
| 5558 predicate(_kids[0]->_leaf->as_Load()->is_unordered()); | |
| 5559 ins_cost(MEMORY_REF_COST); | |
| 5560 | |
| 5561 format %{ "LD $dst, $mem \t// ptr + p2x" %} | |
| 5562 size(4); | |
| 5563 ins_encode( enc_ld(dst, mem) ); | |
| 5564 ins_pipe(pipe_class_memory); | |
| 5565 %} | |
| 5566 | |
| 5567 // Load compressed klass pointer. | |
| 5568 instruct loadNKlass(iRegNdst dst, memory mem) %{ | |
| 5569 match(Set dst (LoadNKlass mem)); | |
| 5570 ins_cost(MEMORY_REF_COST); | |
| 5571 | |
| 5572 format %{ "LWZ $dst, $mem \t// compressed klass ptr" %} | |
| 5573 size(4); | |
| 5574 ins_encode( enc_lwz(dst, mem) ); | |
| 5575 ins_pipe(pipe_class_memory); | |
| 5576 %} | |
| 5577 | |
| 5578 //// Load compressed klass and decode it if narrow_klass_shift == 0. | |
| 5579 //// TODO: will narrow_klass_shift ever be 0? | |
| 5580 //instruct decodeNKlass2Klass(iRegPdst dst, memory mem) %{ | |
| 5581 // match(Set dst (DecodeNKlass (LoadNKlass mem))); | |
| 5582 // predicate(false /* TODO: PPC port Universe::narrow_klass_shift() == 0*); | |
| 5583 // ins_cost(MEMORY_REF_COST); | |
| 5584 // | |
| 5585 // format %{ "LWZ $dst, $mem \t// DecodeNKlass (unscaled)" %} | |
| 5586 // size(4); | |
| 5587 // ins_encode( enc_lwz(dst, mem) ); | |
| 5588 // ins_pipe(pipe_class_memory); | |
| 5589 //%} | |
| 5590 | |
| 5591 // Load Klass Pointer | |
| 5592 instruct loadKlass(iRegPdst dst, memoryAlg4 mem) %{ | |
| 5593 match(Set dst (LoadKlass mem)); | |
| 5594 ins_cost(MEMORY_REF_COST); | |
| 5595 | |
| 5596 format %{ "LD $dst, $mem \t// klass ptr" %} | |
| 5597 size(4); | |
| 5598 ins_encode( enc_ld(dst, mem) ); | |
| 5599 ins_pipe(pipe_class_memory); | |
| 5600 %} | |
| 5601 | |
| 5602 // Load Float | |
| 5603 instruct loadF(regF dst, memory mem) %{ | |
| 5604 match(Set dst (LoadF mem)); | |
| 5605 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); | |
| 5606 ins_cost(MEMORY_REF_COST); | |
| 5607 | |
| 5608 format %{ "LFS $dst, $mem" %} | |
| 5609 size(4); | |
| 5610 ins_encode %{ | |
| 5611 // TODO: PPC port $archOpcode(ppc64Opcode_lfs); | |
| 5612 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); | |
| 5613 __ lfs($dst$$FloatRegister, Idisp, $mem$$base$$Register); | |
| 5614 %} | |
| 5615 ins_pipe(pipe_class_memory); | |
| 5616 %} | |
| 5617 | |
| 5618 // Load Float acquire. | |
| 5619 instruct loadF_ac(regF dst, memory mem) %{ | |
| 5620 match(Set dst (LoadF mem)); | |
| 5621 ins_cost(3*MEMORY_REF_COST); | |
| 5622 | |
| 5623 format %{ "LFS $dst, $mem \t// acquire\n\t" | |
| 5624 "FCMPU cr0, $dst, $dst\n\t" | |
| 5625 "BNE cr0, next\n" | |
| 5626 "next:\n\t" | |
| 5627 "ISYNC" %} | |
| 5628 size(16); | |
| 5629 ins_encode %{ | |
| 5630 // TODO: PPC port $archOpcode(ppc64Opcode_compound); | |
| 5631 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); | |
| 5632 Label next; | |
| 5633 __ lfs($dst$$FloatRegister, Idisp, $mem$$base$$Register); | |
| 5634 __ fcmpu(CCR0, $dst$$FloatRegister, $dst$$FloatRegister); | |
| 5635 __ bne(CCR0, next); | |
| 5636 __ bind(next); | |
| 5637 __ isync(); | |
| 5638 %} | |
| 5639 ins_pipe(pipe_class_memory); | |
| 5640 %} | |
| 5641 | |
| 5642 // Load Double - aligned | |
| 5643 instruct loadD(regD dst, memory mem) %{ | |
| 5644 match(Set dst (LoadD mem)); | |
| 5645 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); | |
| 5646 ins_cost(MEMORY_REF_COST); | |
| 5647 | |
| 5648 format %{ "LFD $dst, $mem" %} | |
| 5649 size(4); | |
| 5650 ins_encode( enc_lfd(dst, mem) ); | |
| 5651 ins_pipe(pipe_class_memory); | |
| 5652 %} | |
| 5653 | |
| 5654 // Load Double - aligned acquire. | |
| 5655 instruct loadD_ac(regD dst, memory mem) %{ | |
| 5656 match(Set dst (LoadD mem)); | |
| 5657 ins_cost(3*MEMORY_REF_COST); | |
| 5658 | |
| 5659 format %{ "LFD $dst, $mem \t// acquire\n\t" | |
| 5660 "FCMPU cr0, $dst, $dst\n\t" | |
| 5661 "BNE cr0, next\n" | |
| 5662 "next:\n\t" | |
| 5663 "ISYNC" %} | |
| 5664 size(16); | |
| 5665 ins_encode %{ | |
| 5666 // TODO: PPC port $archOpcode(ppc64Opcode_compound); | |
| 5667 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); | |
| 5668 Label next; | |
| 5669 __ lfd($dst$$FloatRegister, Idisp, $mem$$base$$Register); | |
| 5670 __ fcmpu(CCR0, $dst$$FloatRegister, $dst$$FloatRegister); | |
| 5671 __ bne(CCR0, next); | |
| 5672 __ bind(next); | |
| 5673 __ isync(); | |
| 5674 %} | |
| 5675 ins_pipe(pipe_class_memory); | |
| 5676 %} | |
| 5677 | |
| 5678 // Load Double - UNaligned | |
| 5679 instruct loadD_unaligned(regD dst, memory mem) %{ | |
| 5680 match(Set dst (LoadD_unaligned mem)); | |
| 5681 // predicate(...) // Unaligned_ac is not needed (and wouldn't make sense). | |
| 5682 ins_cost(MEMORY_REF_COST); | |
| 5683 | |
| 5684 format %{ "LFD $dst, $mem" %} | |
| 5685 size(4); | |
| 5686 ins_encode( enc_lfd(dst, mem) ); | |
| 5687 ins_pipe(pipe_class_memory); | |
| 5688 %} | |
| 5689 | |
| 5690 //----------Constants-------------------------------------------------------- | |
| 5691 | |
| 5692 // Load MachConstantTableBase: add hi offset to global toc. | |
| 5693 // TODO: Handle hidden register r29 in bundler! | |
| 5694 instruct loadToc_hi(iRegLdst dst) %{ | |
| 5695 effect(DEF dst); | |
| 5696 ins_cost(DEFAULT_COST); | |
| 5697 | |
| 5698 format %{ "ADDIS $dst, R29, DISP.hi \t// load TOC hi" %} | |
| 5699 size(4); | |
| 5700 ins_encode %{ | |
| 5701 // TODO: PPC port $archOpcode(ppc64Opcode_addis); | |
| 5702 __ calculate_address_from_global_toc_hi16only($dst$$Register, __ method_toc()); | |
| 5703 %} | |
| 5704 ins_pipe(pipe_class_default); | |
| 5705 %} | |
| 5706 | |
| 5707 // Load MachConstantTableBase: add lo offset to global toc. | |
| 5708 instruct loadToc_lo(iRegLdst dst, iRegLdst src) %{ | |
| 5709 effect(DEF dst, USE src); | |
| 5710 ins_cost(DEFAULT_COST); | |
| 5711 | |
| 5712 format %{ "ADDI $dst, $src, DISP.lo \t// load TOC lo" %} | |
| 5713 size(4); | |
| 5714 ins_encode %{ | |
| 5715 // TODO: PPC port $archOpcode(ppc64Opcode_ori); | |
| 5716 __ calculate_address_from_global_toc_lo16only($dst$$Register, __ method_toc()); | |
| 5717 %} | |
| 5718 ins_pipe(pipe_class_default); | |
| 5719 %} | |
| 5720 | |
| 5721 // Load 16-bit integer constant 0xssss???? | |
| 5722 instruct loadConI16(iRegIdst dst, immI16 src) %{ | |
| 5723 match(Set dst src); | |
| 5724 | |
| 5725 format %{ "LI $dst, $src" %} | |
| 5726 size(4); | |
| 5727 ins_encode %{ | |
| 5728 // TODO: PPC port $archOpcode(ppc64Opcode_addi); | |
| 5729 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF))); | |
| 5730 %} | |
| 5731 ins_pipe(pipe_class_default); | |
| 5732 %} | |
| 5733 | |
| 5734 // Load integer constant 0x????0000 | |
| 5735 instruct loadConIhi16(iRegIdst dst, immIhi16 src) %{ | |
| 5736 match(Set dst src); | |
| 5737 ins_cost(DEFAULT_COST); | |
| 5738 | |
| 5739 format %{ "LIS $dst, $src.hi" %} | |
| 5740 size(4); | |
| 5741 ins_encode %{ | |
| 5742 // TODO: PPC port $archOpcode(ppc64Opcode_addis); | |
| 5743 // Lis sign extends 16-bit src then shifts it 16 bit to the left. | |
| 5744 __ lis($dst$$Register, (int)((short)(($src$$constant & 0xFFFF0000) >> 16))); | |
| 5745 %} | |
| 5746 ins_pipe(pipe_class_default); | |
| 5747 %} | |
| 5748 | |
| 5749 // Part 2 of loading 32 bit constant: hi16 is is src1 (properly shifted | |
| 5750 // and sign extended), this adds the low 16 bits. | |
| 5751 instruct loadConI32_lo16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{ | |
| 5752 // no match-rule, false predicate | |
| 5753 effect(DEF dst, USE src1, USE src2); | |
| 5754 predicate(false); | |
| 5755 | |
| 5756 format %{ "ORI $dst, $src1.hi, $src2.lo" %} | |
| 5757 size(4); | |
| 5758 ins_encode %{ | |
| 5759 // TODO: PPC port $archOpcode(ppc64Opcode_ori); | |
| 5760 __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF); | |
| 5761 %} | |
| 5762 ins_pipe(pipe_class_default); | |
| 5763 %} | |
| 5764 | |
| 5765 instruct loadConI_Ex(iRegIdst dst, immI src) %{ | |
| 5766 match(Set dst src); | |
| 5767 ins_cost(DEFAULT_COST*2); | |
| 5768 | |
| 5769 expand %{ | |
| 5770 // Would like to use $src$$constant. | |
| 5771 immI16 srcLo %{ _opnds[1]->constant() %} | |
| 5772 // srcHi can be 0000 if srcLo sign-extends to a negative number. | |
| 5773 immIhi16 srcHi %{ _opnds[1]->constant() %} | |
| 5774 iRegIdst tmpI; | |
| 5775 loadConIhi16(tmpI, srcHi); | |
| 5776 loadConI32_lo16(dst, tmpI, srcLo); | |
| 5777 %} | |
| 5778 %} | |
| 5779 | |
| 5780 // No constant pool entries required. | |
| 5781 instruct loadConL16(iRegLdst dst, immL16 src) %{ | |
| 5782 match(Set dst src); | |
| 5783 | |
| 5784 format %{ "LI $dst, $src \t// long" %} | |
| 5785 size(4); | |
| 5786 ins_encode %{ | |
| 5787 // TODO: PPC port $archOpcode(ppc64Opcode_addi); | |
| 5788 __ li($dst$$Register, (int)((short) ($src$$constant & 0xFFFF))); | |
| 5789 %} | |
| 5790 ins_pipe(pipe_class_default); | |
| 5791 %} | |
| 5792 | |
| 5793 // Load long constant 0xssssssss????0000 | |
| 5794 instruct loadConL32hi16(iRegLdst dst, immL32hi16 src) %{ | |
| 5795 match(Set dst src); | |
| 5796 ins_cost(DEFAULT_COST); | |
| 5797 | |
| 5798 format %{ "LIS $dst, $src.hi \t// long" %} | |
| 5799 size(4); | |
| 5800 ins_encode %{ | |
| 5801 // TODO: PPC port $archOpcode(ppc64Opcode_addis); | |
| 5802 __ lis($dst$$Register, (int)((short)(($src$$constant & 0xFFFF0000) >> 16))); | |
| 5803 %} | |
| 5804 ins_pipe(pipe_class_default); | |
| 5805 %} | |
| 5806 | |
| 5807 // To load a 32 bit constant: merge lower 16 bits into already loaded | |
| 5808 // high 16 bits. | |
| 5809 instruct loadConL32_lo16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{ | |
| 5810 // no match-rule, false predicate | |
| 5811 effect(DEF dst, USE src1, USE src2); | |
| 5812 predicate(false); | |
| 5813 | |
| 5814 format %{ "ORI $dst, $src1, $src2.lo" %} | |
| 5815 size(4); | |
| 5816 ins_encode %{ | |
| 5817 // TODO: PPC port $archOpcode(ppc64Opcode_ori); | |
| 5818 __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF); | |
| 5819 %} | |
| 5820 ins_pipe(pipe_class_default); | |
| 5821 %} | |
| 5822 | |
| 5823 // Load 32-bit long constant | |
| 5824 instruct loadConL32_Ex(iRegLdst dst, immL32 src) %{ | |
| 5825 match(Set dst src); | |
| 5826 ins_cost(DEFAULT_COST*2); | |
| 5827 | |
| 5828 expand %{ | |
| 5829 // Would like to use $src$$constant. | |
| 5830 immL16 srcLo %{ _opnds[1]->constant() /*& 0x0000FFFFL */%} | |
| 5831 // srcHi can be 0000 if srcLo sign-extends to a negative number. | |
| 5832 immL32hi16 srcHi %{ _opnds[1]->constant() /*& 0xFFFF0000L */%} | |
| 5833 iRegLdst tmpL; | |
| 5834 loadConL32hi16(tmpL, srcHi); | |
| 5835 loadConL32_lo16(dst, tmpL, srcLo); | |
| 5836 %} | |
| 5837 %} | |
| 5838 | |
| 5839 // Load long constant 0x????000000000000. | |
| 5840 instruct loadConLhighest16_Ex(iRegLdst dst, immLhighest16 src) %{ | |
| 5841 match(Set dst src); | |
| 5842 ins_cost(DEFAULT_COST); | |
| 5843 | |
| 5844 expand %{ | |
| 5845 immL32hi16 srcHi %{ _opnds[1]->constant() >> 32 /*& 0xFFFF0000L */%} | |
| 5846 immI shift32 %{ 32 %} | |
| 5847 iRegLdst tmpL; | |
| 5848 loadConL32hi16(tmpL, srcHi); | |
| 5849 lshiftL_regL_immI(dst, tmpL, shift32); | |
| 5850 %} | |
| 5851 %} | |
| 5852 | |
| 5853 // Expand node for constant pool load: small offset. | |
| 5854 instruct loadConL(iRegLdst dst, immL src, iRegLdst toc) %{ | |
| 5855 effect(DEF dst, USE src, USE toc); | |
| 5856 ins_cost(MEMORY_REF_COST); | |
| 5857 | |
| 5858 ins_num_consts(1); | |
| 5859 // Needed so that CallDynamicJavaDirect can compute the address of this | |
| 5860 // instruction for relocation. | |
| 5861 ins_field_cbuf_insts_offset(int); | |
| 5862 | |
| 5863 format %{ "LD $dst, offset, $toc \t// load long $src from TOC" %} | |
| 5864 size(4); | |
| 5865 ins_encode( enc_load_long_constL(dst, src, toc) ); | |
| 5866 ins_pipe(pipe_class_memory); | |
| 5867 %} | |
| 5868 | |
| 5869 // Expand node for constant pool load: large offset. | |
| 5870 instruct loadConL_hi(iRegLdst dst, immL src, iRegLdst toc) %{ | |
| 5871 effect(DEF dst, USE src, USE toc); | |
| 5872 predicate(false); | |
| 5873 | |
| 5874 ins_num_consts(1); | |
| 5875 ins_field_const_toc_offset(int); | |
| 5876 // Needed so that CallDynamicJavaDirect can compute the address of this | |
| 5877 // instruction for relocation. | |
| 5878 ins_field_cbuf_insts_offset(int); | |
| 5879 | |
| 5880 format %{ "ADDIS $dst, $toc, offset \t// load long $src from TOC (hi)" %} | |
| 5881 size(4); | |
| 5882 ins_encode( enc_load_long_constL_hi(dst, toc, src) ); | |
| 5883 ins_pipe(pipe_class_default); | |
| 5884 %} | |
| 5885 | |
| 5886 // Expand node for constant pool load: large offset. | |
| 5887 // No constant pool entries required. | |
| 5888 instruct loadConL_lo(iRegLdst dst, immL src, iRegLdst base) %{ | |
| 5889 effect(DEF dst, USE src, USE base); | |
| 5890 predicate(false); | |
| 5891 | |
| 5892 ins_field_const_toc_offset_hi_node(loadConL_hiNode*); | |
| 5893 | |
| 5894 format %{ "LD $dst, offset, $base \t// load long $src from TOC (lo)" %} | |
| 5895 size(4); | |
| 5896 ins_encode %{ | |
| 5897 // TODO: PPC port $archOpcode(ppc64Opcode_ld); | |
| 5898 int offset = ra_->C->in_scratch_emit_size() ? 0 : _const_toc_offset_hi_node->_const_toc_offset; | |
| 5899 __ ld($dst$$Register, MacroAssembler::largeoffset_si16_si16_lo(offset), $base$$Register); | |
| 5900 %} | |
| 5901 ins_pipe(pipe_class_memory); | |
| 5902 %} | |
| 5903 | |
| 5904 // Load long constant from constant table. Expand in case of | |
| 5905 // offset > 16 bit is needed. | |
| 5906 // Adlc adds toc node MachConstantTableBase. | |
| 5907 instruct loadConL_Ex(iRegLdst dst, immL src) %{ | |
| 5908 match(Set dst src); | |
| 5909 ins_cost(MEMORY_REF_COST); | |
| 5910 | |
| 5911 format %{ "LD $dst, offset, $constanttablebase\t// load long $src from table, postalloc expanded" %} | |
| 5912 // We can not inline the enc_class for the expand as that does not support constanttablebase. | |
| 5913 postalloc_expand( postalloc_expand_load_long_constant(dst, src, constanttablebase) ); | |
| 5914 %} | |
| 5915 | |
| 5916 // Load NULL as compressed oop. | |
| 5917 instruct loadConN0(iRegNdst dst, immN_0 src) %{ | |
| 5918 match(Set dst src); | |
| 5919 ins_cost(DEFAULT_COST); | |
| 5920 | |
| 5921 format %{ "LI $dst, $src \t// compressed ptr" %} | |
| 5922 size(4); | |
| 5923 ins_encode %{ | |
| 5924 // TODO: PPC port $archOpcode(ppc64Opcode_addi); | |
| 5925 __ li($dst$$Register, 0); | |
| 5926 %} | |
| 5927 ins_pipe(pipe_class_default); | |
| 5928 %} | |
| 5929 | |
| 5930 // Load hi part of compressed oop constant. | |
| 5931 instruct loadConN_hi(iRegNdst dst, immN src) %{ | |
| 5932 effect(DEF dst, USE src); | |
| 5933 ins_cost(DEFAULT_COST); | |
| 5934 | |
| 5935 format %{ "LIS $dst, $src \t// narrow oop hi" %} | |
| 5936 size(4); | |
| 5937 ins_encode %{ | |
| 5938 // TODO: PPC port $archOpcode(ppc64Opcode_addis); | |
| 5939 __ lis($dst$$Register, (int)(short)(($src$$constant >> 16) & 0xffff)); | |
| 5940 %} | |
| 5941 ins_pipe(pipe_class_default); | |
| 5942 %} | |
| 5943 | |
| 5944 // Add lo part of compressed oop constant to already loaded hi part. | |
| 5945 instruct loadConN_lo(iRegNdst dst, iRegNsrc src1, immN src2) %{ | |
| 5946 effect(DEF dst, USE src1, USE src2); | |
| 5947 ins_cost(DEFAULT_COST); | |
| 5948 | |
| 5949 format %{ "ORI $dst, $src1, $src2 \t// narrow oop lo" %} | |
| 5950 size(4); | |
| 5951 ins_encode %{ | |
| 5952 // TODO: PPC port $archOpcode(ppc64Opcode_addi); | |
| 5953 assert(__ oop_recorder() != NULL, "this assembler needs an OopRecorder"); | |
| 5954 int oop_index = __ oop_recorder()->find_index((jobject)$src2$$constant); | |
| 5955 RelocationHolder rspec = oop_Relocation::spec(oop_index); | |
| 5956 __ relocate(rspec, 1); | |
| 5957 __ ori($dst$$Register, $src1$$Register, $src2$$constant & 0xffff); | |
| 5958 %} | |
| 5959 ins_pipe(pipe_class_default); | |
| 5960 %} | |
| 5961 | |
| 5962 // Needed to postalloc expand loadConN: ConN is loaded as ConI | |
| 5963 // leaving the upper 32 bits with sign-extension bits. | |
| 5964 // This clears these bits: dst = src & 0xFFFFFFFF. | |
| 5965 // TODO: Eventually call this maskN_regN_FFFFFFFF. | |
| 5966 instruct clearMs32b(iRegNdst dst, iRegNsrc src) %{ | |
| 5967 effect(DEF dst, USE src); | |
| 5968 predicate(false); | |
| 5969 | |
| 5970 format %{ "MASK $dst, $src, 0xFFFFFFFF" %} // mask | |
| 5971 size(4); | |
| 5972 ins_encode %{ | |
| 5973 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); | |
| 5974 __ clrldi($dst$$Register, $src$$Register, 0x20); | |
| 5975 %} | |
| 5976 ins_pipe(pipe_class_default); | |
| 5977 %} | |
| 5978 | |
| 5979 // Loading ConN must be postalloc expanded so that edges between | |
| 5980 // the nodes are safe. They may not interfere with a safepoint. | |
| 5981 // GL TODO: This needs three instructions: better put this into the constant pool. | |
| 5982 instruct loadConN_Ex(iRegNdst dst, immN src) %{ | |
| 5983 match(Set dst src); | |
| 5984 ins_cost(DEFAULT_COST*2); | |
| 5985 | |
| 5986 format %{ "LoadN $dst, $src \t// postalloc expanded" %} // mask | |
| 5987 postalloc_expand %{ | |
| 5988 MachNode *m1 = new (C) loadConN_hiNode(); | |
| 5989 MachNode *m2 = new (C) loadConN_loNode(); | |
| 5990 MachNode *m3 = new (C) clearMs32bNode(); | |
| 5991 m1->add_req(NULL); | |
| 5992 m2->add_req(NULL, m1); | |
| 5993 m3->add_req(NULL, m2); | |
| 5994 m1->_opnds[0] = op_dst; | |
| 5995 m1->_opnds[1] = op_src; | |
| 5996 m2->_opnds[0] = op_dst; | |
| 5997 m2->_opnds[1] = op_dst; | |
| 5998 m2->_opnds[2] = op_src; | |
| 5999 m3->_opnds[0] = op_dst; | |
| 6000 m3->_opnds[1] = op_dst; | |
| 6001 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); | |
| 6002 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); | |
| 6003 ra_->set_pair(m3->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); | |
| 6004 nodes->push(m1); | |
| 6005 nodes->push(m2); | |
| 6006 nodes->push(m3); | |
| 6007 %} | |
| 6008 %} | |
| 6009 | |
| 6010 instruct loadConNKlass_hi(iRegNdst dst, immNKlass src) %{ | |
| 6011 effect(DEF dst, USE src); | |
| 6012 ins_cost(DEFAULT_COST); | |
| 6013 | |
| 6014 format %{ "LIS $dst, $src \t// narrow oop hi" %} | |
| 6015 size(4); | |
| 6016 ins_encode %{ | |
| 6017 // TODO: PPC port $archOpcode(ppc64Opcode_addis); | |
| 6018 intptr_t Csrc = Klass::encode_klass((Klass *)$src$$constant); | |
| 6019 __ lis($dst$$Register, (int)(short)((Csrc >> 16) & 0xffff)); | |
| 6020 %} | |
| 6021 ins_pipe(pipe_class_default); | |
| 6022 %} | |
| 6023 | |
| 6024 // This needs a match rule so that build_oop_map knows this is | |
| 6025 // not a narrow oop. | |
| 6026 instruct loadConNKlass_lo(iRegNdst dst, immNKlass_NM src1, iRegNsrc src2) %{ | |
| 6027 match(Set dst src1); | |
| 6028 effect(TEMP src2); | |
| 6029 ins_cost(DEFAULT_COST); | |
| 6030 | |
| 6031 format %{ "ADDI $dst, $src1, $src2 \t// narrow oop lo" %} | |
| 6032 size(4); | |
| 6033 ins_encode %{ | |
| 6034 // TODO: PPC port $archOpcode(ppc64Opcode_addi); | |
| 6035 intptr_t Csrc = Klass::encode_klass((Klass *)$src1$$constant); | |
| 6036 assert(__ oop_recorder() != NULL, "this assembler needs an OopRecorder"); | |
| 6037 int klass_index = __ oop_recorder()->find_index((Klass *)$src1$$constant); | |
| 6038 RelocationHolder rspec = metadata_Relocation::spec(klass_index); | |
| 6039 | |
| 6040 __ relocate(rspec, 1); | |
| 6041 __ ori($dst$$Register, $src2$$Register, Csrc & 0xffff); | |
| 6042 %} | |
| 6043 ins_pipe(pipe_class_default); | |
| 6044 %} | |
| 6045 | |
| 6046 // Loading ConNKlass must be postalloc expanded so that edges between | |
| 6047 // the nodes are safe. They may not interfere with a safepoint. | |
| 6048 instruct loadConNKlass_Ex(iRegNdst dst, immNKlass src) %{ | |
| 6049 match(Set dst src); | |
| 6050 ins_cost(DEFAULT_COST*2); | |
| 6051 | |
| 6052 format %{ "LoadN $dst, $src \t// postalloc expanded" %} // mask | |
| 6053 postalloc_expand %{ | |
| 6054 // Load high bits into register. Sign extended. | |
| 6055 MachNode *m1 = new (C) loadConNKlass_hiNode(); | |
| 6056 m1->add_req(NULL); | |
| 6057 m1->_opnds[0] = op_dst; | |
| 6058 m1->_opnds[1] = op_src; | |
| 6059 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); | |
| 6060 nodes->push(m1); | |
| 6061 | |
| 6062 MachNode *m2 = m1; | |
| 6063 if (!Assembler::is_uimm((jlong)Klass::encode_klass((Klass *)op_src->constant()), 31)) { | |
| 6064 // Value might be 1-extended. Mask out these bits. | |
| 6065 m2 = new (C) clearMs32bNode(); | |
| 6066 m2->add_req(NULL, m1); | |
| 6067 m2->_opnds[0] = op_dst; | |
| 6068 m2->_opnds[1] = op_dst; | |
| 6069 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); | |
| 6070 nodes->push(m2); | |
| 6071 } | |
| 6072 | |
| 6073 MachNode *m3 = new (C) loadConNKlass_loNode(); | |
| 6074 m3->add_req(NULL, m2); | |
| 6075 m3->_opnds[0] = op_dst; | |
| 6076 m3->_opnds[1] = op_src; | |
| 6077 m3->_opnds[2] = op_dst; | |
| 6078 ra_->set_pair(m3->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); | |
| 6079 nodes->push(m3); | |
| 6080 %} | |
| 6081 %} | |
| 6082 | |
| 6083 // 0x1 is used in object initialization (initial object header). | |
| 6084 // No constant pool entries required. | |
| 6085 instruct loadConP0or1(iRegPdst dst, immP_0or1 src) %{ | |
| 6086 match(Set dst src); | |
| 6087 | |
| 6088 format %{ "LI $dst, $src \t// ptr" %} | |
| 6089 size(4); | |
| 6090 ins_encode %{ | |
| 6091 // TODO: PPC port $archOpcode(ppc64Opcode_addi); | |
| 6092 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF))); | |
| 6093 %} | |
| 6094 ins_pipe(pipe_class_default); | |
| 6095 %} | |
| 6096 | |
| 6097 // Expand node for constant pool load: small offset. | |
| 6098 // The match rule is needed to generate the correct bottom_type(), | |
| 6099 // however this node should never match. The use of predicate is not | |
| 6100 // possible since ADLC forbids predicates for chain rules. The higher | |
| 6101 // costs do not prevent matching in this case. For that reason the | |
| 6102 // operand immP_NM with predicate(false) is used. | |
| 6103 instruct loadConP(iRegPdst dst, immP_NM src, iRegLdst toc) %{ | |
| 6104 match(Set dst src); | |
| 6105 effect(TEMP toc); | |
| 6106 | |
| 6107 ins_num_consts(1); | |
| 6108 | |
| 6109 format %{ "LD $dst, offset, $toc \t// load ptr $src from TOC" %} | |
| 6110 size(4); | |
| 6111 ins_encode( enc_load_long_constP(dst, src, toc) ); | |
| 6112 ins_pipe(pipe_class_memory); | |
| 6113 %} | |
| 6114 | |
| 6115 // Expand node for constant pool load: large offset. | |
| 6116 instruct loadConP_hi(iRegPdst dst, immP_NM src, iRegLdst toc) %{ | |
| 6117 effect(DEF dst, USE src, USE toc); | |
| 6118 predicate(false); | |
| 6119 | |
| 6120 ins_num_consts(1); | |
| 6121 ins_field_const_toc_offset(int); | |
| 6122 | |
| 6123 format %{ "ADDIS $dst, $toc, offset \t// load ptr $src from TOC (hi)" %} | |
| 6124 size(4); | |
| 6125 ins_encode( enc_load_long_constP_hi(dst, src, toc) ); | |
| 6126 ins_pipe(pipe_class_default); | |
| 6127 %} | |
| 6128 | |
| 6129 // Expand node for constant pool load: large offset. | |
| 6130 instruct loadConP_lo(iRegPdst dst, immP_NM src, iRegLdst base) %{ | |
| 6131 match(Set dst src); | |
| 6132 effect(TEMP base); | |
| 6133 | |
| 6134 ins_field_const_toc_offset_hi_node(loadConP_hiNode*); | |
| 6135 | |
| 6136 format %{ "LD $dst, offset, $base \t// load ptr $src from TOC (lo)" %} | |
| 6137 size(4); | |
| 6138 ins_encode %{ | |
| 6139 // TODO: PPC port $archOpcode(ppc64Opcode_ld); | |
|
17791
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8030863: PPC64: (part 220): ConstantTableBase for calls between args and jvms
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parents:
14445
diff
changeset
|
6140 int offset = ra_->C->in_scratch_emit_size() ? 0 : _const_toc_offset_hi_node->_const_toc_offset; |
|
ad3b94907eed
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parents:
14445
diff
changeset
|
6141 __ ld($dst$$Register, MacroAssembler::largeoffset_si16_si16_lo(offset), $base$$Register); |
| 14445 | 6142 %} |
| 6143 ins_pipe(pipe_class_memory); | |
| 6144 %} | |
| 6145 | |
| 6146 // Load pointer constant from constant table. Expand in case an | |
| 6147 // offset > 16 bit is needed. | |
| 6148 // Adlc adds toc node MachConstantTableBase. | |
| 6149 instruct loadConP_Ex(iRegPdst dst, immP src) %{ | |
| 6150 match(Set dst src); | |
| 6151 ins_cost(MEMORY_REF_COST); | |
| 6152 | |
| 6153 // This rule does not use "expand" because then | |
| 6154 // the result type is not known to be an Oop. An ADLC | |
| 6155 // enhancement will be needed to make that work - not worth it! | |
| 6156 | |
| 6157 // If this instruction rematerializes, it prolongs the live range | |
| 6158 // of the toc node, causing illegal graphs. | |
| 6159 // assert(edge_from_to(_reg_node[reg_lo],def)) fails in verify_good_schedule(). | |
| 6160 ins_cannot_rematerialize(true); | |
| 6161 | |
| 6162 format %{ "LD $dst, offset, $constanttablebase \t// load ptr $src from table, postalloc expanded" %} | |
| 6163 postalloc_expand( postalloc_expand_load_ptr_constant(dst, src, constanttablebase) ); | |
| 6164 %} | |
| 6165 | |
| 6166 // Expand node for constant pool load: small offset. | |
| 6167 instruct loadConF(regF dst, immF src, iRegLdst toc) %{ | |
| 6168 effect(DEF dst, USE src, USE toc); | |
| 6169 ins_cost(MEMORY_REF_COST); | |
| 6170 | |
| 6171 ins_num_consts(1); | |
| 6172 | |
| 6173 format %{ "LFS $dst, offset, $toc \t// load float $src from TOC" %} | |
| 6174 size(4); | |
| 6175 ins_encode %{ | |
| 6176 // TODO: PPC port $archOpcode(ppc64Opcode_lfs); | |
| 6177 address float_address = __ float_constant($src$$constant); | |
| 6178 __ lfs($dst$$FloatRegister, __ offset_to_method_toc(float_address), $toc$$Register); | |
| 6179 %} | |
| 6180 ins_pipe(pipe_class_memory); | |
| 6181 %} | |
| 6182 | |
| 6183 // Expand node for constant pool load: large offset. | |
| 6184 instruct loadConFComp(regF dst, immF src, iRegLdst toc) %{ | |
| 6185 effect(DEF dst, USE src, USE toc); | |
| 6186 ins_cost(MEMORY_REF_COST); | |
| 6187 | |
| 6188 ins_num_consts(1); | |
| 6189 | |
| 6190 format %{ "ADDIS $toc, $toc, offset_hi\n\t" | |
| 6191 "LFS $dst, offset_lo, $toc \t// load float $src from TOC (hi/lo)\n\t" | |
| 6192 "ADDIS $toc, $toc, -offset_hi"%} | |
| 6193 size(12); | |
| 6194 ins_encode %{ | |
| 6195 // TODO: PPC port $archOpcode(ppc64Opcode_compound); | |
| 6196 FloatRegister Rdst = $dst$$FloatRegister; | |
| 6197 Register Rtoc = $toc$$Register; | |
| 6198 address float_address = __ float_constant($src$$constant); | |
| 6199 int offset = __ offset_to_method_toc(float_address); | |
| 6200 int hi = (offset + (1<<15))>>16; | |
| 6201 int lo = offset - hi * (1<<16); | |
| 6202 | |
| 6203 __ addis(Rtoc, Rtoc, hi); | |
| 6204 __ lfs(Rdst, lo, Rtoc); | |
| 6205 __ addis(Rtoc, Rtoc, -hi); | |
| 6206 %} | |
| 6207 ins_pipe(pipe_class_memory); | |
| 6208 %} | |
| 6209 | |
| 6210 // Adlc adds toc node MachConstantTableBase. | |
| 6211 instruct loadConF_Ex(regF dst, immF src) %{ | |
| 6212 match(Set dst src); | |
| 6213 ins_cost(MEMORY_REF_COST); | |
| 6214 | |
| 6215 // See loadConP. | |
| 6216 ins_cannot_rematerialize(true); | |
| 6217 | |
| 6218 format %{ "LFS $dst, offset, $constanttablebase \t// load $src from table, postalloc expanded" %} | |
| 6219 postalloc_expand( postalloc_expand_load_float_constant(dst, src, constanttablebase) ); | |
| 6220 %} | |
| 6221 | |
| 6222 // Expand node for constant pool load: small offset. | |
| 6223 instruct loadConD(regD dst, immD src, iRegLdst toc) %{ | |
| 6224 effect(DEF dst, USE src, USE toc); | |
| 6225 ins_cost(MEMORY_REF_COST); | |
| 6226 | |
| 6227 ins_num_consts(1); | |
| 6228 | |
| 6229 format %{ "LFD $dst, offset, $toc \t// load double $src from TOC" %} | |
| 6230 size(4); | |
| 6231 ins_encode %{ | |
| 6232 // TODO: PPC port $archOpcode(ppc64Opcode_lfd); | |
| 6233 int offset = __ offset_to_method_toc(__ double_constant($src$$constant)); | |
| 6234 __ lfd($dst$$FloatRegister, offset, $toc$$Register); | |
| 6235 %} | |
| 6236 ins_pipe(pipe_class_memory); | |
| 6237 %} | |
| 6238 | |
| 6239 // Expand node for constant pool load: large offset. | |
| 6240 instruct loadConDComp(regD dst, immD src, iRegLdst toc) %{ | |
| 6241 effect(DEF dst, USE src, USE toc); | |
| 6242 ins_cost(MEMORY_REF_COST); | |
| 6243 | |
| 6244 ins_num_consts(1); | |
| 6245 | |
| 6246 format %{ "ADDIS $toc, $toc, offset_hi\n\t" | |
| 6247 "LFD $dst, offset_lo, $toc \t// load double $src from TOC (hi/lo)\n\t" | |
| 6248 "ADDIS $toc, $toc, -offset_hi" %} | |
| 6249 size(12); | |
| 6250 ins_encode %{ | |
| 6251 // TODO: PPC port $archOpcode(ppc64Opcode_compound); | |
| 6252 FloatRegister Rdst = $dst$$FloatRegister; | |
| 6253 Register Rtoc = $toc$$Register; | |
| 6254 address float_address = __ double_constant($src$$constant); | |
| 6255 int offset = __ offset_to_method_toc(float_address); | |
| 6256 int hi = (offset + (1<<15))>>16; | |
| 6257 int lo = offset - hi * (1<<16); | |
| 6258 | |
| 6259 __ addis(Rtoc, Rtoc, hi); | |
| 6260 __ lfd(Rdst, lo, Rtoc); | |
| 6261 __ addis(Rtoc, Rtoc, -hi); | |
| 6262 %} | |
| 6263 ins_pipe(pipe_class_memory); | |
| 6264 %} | |
| 6265 | |
| 6266 // Adlc adds toc node MachConstantTableBase. | |
| 6267 instruct loadConD_Ex(regD dst, immD src) %{ | |
| 6268 match(Set dst src); | |
| 6269 ins_cost(MEMORY_REF_COST); | |
| 6270 | |
| 6271 // See loadConP. | |
| 6272 ins_cannot_rematerialize(true); | |
| 6273 | |
| 6274 format %{ "ConD $dst, offset, $constanttablebase \t// load $src from table, postalloc expanded" %} | |
| 6275 postalloc_expand( postalloc_expand_load_double_constant(dst, src, constanttablebase) ); | |
| 6276 %} | |
| 6277 | |
| 6278 // Prefetch instructions. | |
| 6279 // Must be safe to execute with invalid address (cannot fault). | |
| 6280 | |
| 6281 instruct prefetchr(indirectMemory mem, iRegLsrc src) %{ | |
| 6282 match(PrefetchRead (AddP mem src)); | |
| 6283 ins_cost(MEMORY_REF_COST); | |
| 6284 | |
| 6285 format %{ "PREFETCH $mem, 0, $src \t// Prefetch read-many" %} | |
| 6286 size(4); | |
| 6287 ins_encode %{ | |
| 6288 // TODO: PPC port $archOpcode(ppc64Opcode_dcbt); | |
| 6289 __ dcbt($src$$Register, $mem$$base$$Register); | |
| 6290 %} | |
| 6291 ins_pipe(pipe_class_memory); | |
| 6292 %} | |
| 6293 | |
| 6294 instruct prefetchr_no_offset(indirectMemory mem) %{ | |
| 6295 match(PrefetchRead mem); | |
| 6296 ins_cost(MEMORY_REF_COST); | |
| 6297 | |
| 6298 format %{ "PREFETCH $mem" %} | |
| 6299 size(4); | |
| 6300 ins_encode %{ | |
| 6301 // TODO: PPC port $archOpcode(ppc64Opcode_dcbt); | |
| 6302 __ dcbt($mem$$base$$Register); | |
| 6303 %} | |
| 6304 ins_pipe(pipe_class_memory); | |
| 6305 %} | |
| 6306 | |
| 6307 instruct prefetchw(indirectMemory mem, iRegLsrc src) %{ | |
| 6308 match(PrefetchWrite (AddP mem src)); | |
| 6309 ins_cost(MEMORY_REF_COST); | |
| 6310 | |
| 6311 format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many (and read)" %} | |
| 6312 size(4); | |
| 6313 ins_encode %{ | |
| 6314 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst); | |
| 6315 __ dcbtst($src$$Register, $mem$$base$$Register); | |
| 6316 %} | |
| 6317 ins_pipe(pipe_class_memory); | |
| 6318 %} | |
| 6319 | |
| 6320 instruct prefetchw_no_offset(indirectMemory mem) %{ | |
| 6321 match(PrefetchWrite mem); | |
| 6322 ins_cost(MEMORY_REF_COST); | |
| 6323 | |
| 6324 format %{ "PREFETCH $mem" %} | |
| 6325 size(4); | |
| 6326 ins_encode %{ | |
| 6327 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst); | |
| 6328 __ dcbtst($mem$$base$$Register); | |
| 6329 %} | |
| 6330 ins_pipe(pipe_class_memory); | |
| 6331 %} | |
| 6332 | |
| 6333 // Special prefetch versions which use the dcbz instruction. | |
| 6334 instruct prefetch_alloc_zero(indirectMemory mem, iRegLsrc src) %{ | |
| 6335 match(PrefetchAllocation (AddP mem src)); | |
| 6336 predicate(AllocatePrefetchStyle == 3); | |
| 6337 ins_cost(MEMORY_REF_COST); | |
| 6338 | |
| 6339 format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many with zero" %} | |
| 6340 size(4); | |
| 6341 ins_encode %{ | |
| 6342 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst); | |
| 6343 __ dcbz($src$$Register, $mem$$base$$Register); | |
| 6344 %} | |
| 6345 ins_pipe(pipe_class_memory); | |
| 6346 %} | |
| 6347 | |
| 6348 instruct prefetch_alloc_zero_no_offset(indirectMemory mem) %{ | |
| 6349 match(PrefetchAllocation mem); | |
| 6350 predicate(AllocatePrefetchStyle == 3); | |
| 6351 ins_cost(MEMORY_REF_COST); | |
| 6352 | |
| 6353 format %{ "PREFETCH $mem, 2 \t// Prefetch write-many with zero" %} | |
| 6354 size(4); | |
| 6355 ins_encode %{ | |
| 6356 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst); | |
| 6357 __ dcbz($mem$$base$$Register); | |
| 6358 %} | |
| 6359 ins_pipe(pipe_class_memory); | |
| 6360 %} | |
| 6361 | |
| 6362 instruct prefetch_alloc(indirectMemory mem, iRegLsrc src) %{ | |
| 6363 match(PrefetchAllocation (AddP mem src)); | |
| 6364 predicate(AllocatePrefetchStyle != 3); | |
| 6365 ins_cost(MEMORY_REF_COST); | |
| 6366 | |
| 6367 format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many" %} | |
| 6368 size(4); | |
| 6369 ins_encode %{ | |
| 6370 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst); | |
| 6371 __ dcbtst($src$$Register, $mem$$base$$Register); | |
| 6372 %} | |
| 6373 ins_pipe(pipe_class_memory); | |
| 6374 %} | |
| 6375 | |
| 6376 instruct prefetch_alloc_no_offset(indirectMemory mem) %{ | |
| 6377 match(PrefetchAllocation mem); | |
| 6378 predicate(AllocatePrefetchStyle != 3); | |
| 6379 ins_cost(MEMORY_REF_COST); | |
| 6380 | |
| 6381 format %{ "PREFETCH $mem, 2 \t// Prefetch write-many" %} | |
| 6382 size(4); | |
| 6383 ins_encode %{ | |
| 6384 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst); | |
| 6385 __ dcbtst($mem$$base$$Register); | |
| 6386 %} | |
| 6387 ins_pipe(pipe_class_memory); | |
| 6388 %} | |
| 6389 | |
| 6390 //----------Store Instructions------------------------------------------------- | |
| 6391 | |
| 6392 // Store Byte | |
| 6393 instruct storeB(memory mem, iRegIsrc src) %{ | |
| 6394 match(Set mem (StoreB mem src)); | |
| 6395 ins_cost(MEMORY_REF_COST); | |
| 6396 | |
| 6397 format %{ "STB $src, $mem \t// byte" %} | |
| 6398 size(4); | |
| 6399 ins_encode %{ | |
| 6400 // TODO: PPC port $archOpcode(ppc64Opcode_stb); | |
| 6401 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); | |
| 6402 __ stb($src$$Register, Idisp, $mem$$base$$Register); | |
| 6403 %} | |
| 6404 ins_pipe(pipe_class_memory); | |
| 6405 %} | |
| 6406 | |
| 6407 // Store Char/Short | |
| 6408 instruct storeC(memory mem, iRegIsrc src) %{ | |
| 6409 match(Set mem (StoreC mem src)); | |
| 6410 ins_cost(MEMORY_REF_COST); | |
| 6411 | |
| 6412 format %{ "STH $src, $mem \t// short" %} | |
| 6413 size(4); | |
| 6414 ins_encode %{ | |
| 6415 // TODO: PPC port $archOpcode(ppc64Opcode_sth); | |
| 6416 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); | |
| 6417 __ sth($src$$Register, Idisp, $mem$$base$$Register); | |
| 6418 %} | |
| 6419 ins_pipe(pipe_class_memory); | |
| 6420 %} | |
| 6421 | |
| 6422 // Store Integer | |
| 6423 instruct storeI(memory mem, iRegIsrc src) %{ | |
| 6424 match(Set mem (StoreI mem src)); | |
| 6425 ins_cost(MEMORY_REF_COST); | |
| 6426 | |
| 6427 format %{ "STW $src, $mem" %} | |
| 6428 size(4); | |
| 6429 ins_encode( enc_stw(src, mem) ); | |
| 6430 ins_pipe(pipe_class_memory); | |
| 6431 %} | |
| 6432 | |
| 6433 // ConvL2I + StoreI. | |
| 6434 instruct storeI_convL2I(memory mem, iRegLsrc src) %{ | |
| 6435 match(Set mem (StoreI mem (ConvL2I src))); | |
| 6436 ins_cost(MEMORY_REF_COST); | |
| 6437 | |
| 6438 format %{ "STW l2i($src), $mem" %} | |
| 6439 size(4); | |
| 6440 ins_encode( enc_stw(src, mem) ); | |
| 6441 ins_pipe(pipe_class_memory); | |
| 6442 %} | |
| 6443 | |
| 6444 // Store Long | |
| 6445 instruct storeL(memoryAlg4 mem, iRegLsrc src) %{ | |
| 6446 match(Set mem (StoreL mem src)); | |
| 6447 ins_cost(MEMORY_REF_COST); | |
| 6448 | |
| 6449 format %{ "STD $src, $mem \t// long" %} | |
| 6450 size(4); | |
| 6451 ins_encode( enc_std(src, mem) ); | |
| 6452 ins_pipe(pipe_class_memory); | |
| 6453 %} | |
| 6454 | |
| 6455 // Store super word nodes. | |
| 6456 | |
| 6457 // Store Aligned Packed Byte long register to memory | |
| 6458 instruct storeA8B(memoryAlg4 mem, iRegLsrc src) %{ | |
| 6459 predicate(n->as_StoreVector()->memory_size() == 8); | |
| 6460 match(Set mem (StoreVector mem src)); | |
| 6461 ins_cost(MEMORY_REF_COST); | |
| 6462 | |
| 6463 format %{ "STD $mem, $src \t// packed8B" %} | |
| 6464 size(4); | |
| 6465 ins_encode( enc_std(src, mem) ); | |
| 6466 ins_pipe(pipe_class_memory); | |
| 6467 %} | |
| 6468 | |
| 6469 // Store Compressed Oop | |
| 6470 instruct storeN(memory dst, iRegN_P2N src) %{ | |
| 6471 match(Set dst (StoreN dst src)); | |
| 6472 ins_cost(MEMORY_REF_COST); | |
| 6473 | |
| 6474 format %{ "STW $src, $dst \t// compressed oop" %} | |
| 6475 size(4); | |
| 6476 ins_encode( enc_stw(src, dst) ); | |
| 6477 ins_pipe(pipe_class_memory); | |
| 6478 %} | |
| 6479 | |
| 6480 // Store Compressed KLass | |
| 6481 instruct storeNKlass(memory dst, iRegN_P2N src) %{ | |
| 6482 match(Set dst (StoreNKlass dst src)); | |
| 6483 ins_cost(MEMORY_REF_COST); | |
| 6484 | |
| 6485 format %{ "STW $src, $dst \t// compressed klass" %} | |
| 6486 size(4); | |
| 6487 ins_encode( enc_stw(src, dst) ); | |
| 6488 ins_pipe(pipe_class_memory); | |
| 6489 %} | |
| 6490 | |
| 6491 // Store Pointer | |
| 6492 instruct storeP(memoryAlg4 dst, iRegPsrc src) %{ | |
| 6493 match(Set dst (StoreP dst src)); | |
| 6494 ins_cost(MEMORY_REF_COST); | |
| 6495 | |
| 6496 format %{ "STD $src, $dst \t// ptr" %} | |
| 6497 size(4); | |
| 6498 ins_encode( enc_std(src, dst) ); | |
| 6499 ins_pipe(pipe_class_memory); | |
| 6500 %} | |
| 6501 | |
| 6502 // Store Float | |
| 6503 instruct storeF(memory mem, regF src) %{ | |
| 6504 match(Set mem (StoreF mem src)); | |
| 6505 ins_cost(MEMORY_REF_COST); | |
| 6506 | |
| 6507 format %{ "STFS $src, $mem" %} | |
| 6508 size(4); | |
| 6509 ins_encode( enc_stfs(src, mem) ); | |
| 6510 ins_pipe(pipe_class_memory); | |
| 6511 %} | |
| 6512 | |
| 6513 // Store Double | |
| 6514 instruct storeD(memory mem, regD src) %{ | |
| 6515 match(Set mem (StoreD mem src)); | |
| 6516 ins_cost(MEMORY_REF_COST); | |
| 6517 | |
| 6518 format %{ "STFD $src, $mem" %} | |
| 6519 size(4); | |
| 6520 ins_encode( enc_stfd(src, mem) ); | |
| 6521 ins_pipe(pipe_class_memory); | |
| 6522 %} | |
| 6523 | |
| 6524 //----------Store Instructions With Zeros-------------------------------------- | |
| 6525 | |
| 6526 // Card-mark for CMS garbage collection. | |
| 6527 // This cardmark does an optimization so that it must not always | |
| 6528 // do a releasing store. For this, it gets the address of | |
| 6529 // CMSCollectorCardTableModRefBSExt::_requires_release as input. | |
| 6530 // (Using releaseFieldAddr in the match rule is a hack.) | |
| 6531 instruct storeCM_CMS(memory mem, iRegLdst releaseFieldAddr) %{ | |
| 6532 match(Set mem (StoreCM mem releaseFieldAddr)); | |
| 6533 predicate(false); | |
| 6534 ins_cost(MEMORY_REF_COST); | |
| 6535 | |
| 6536 // See loadConP. | |
| 6537 ins_cannot_rematerialize(true); | |
| 6538 | |
| 6539 format %{ "STB #0, $mem \t// CMS card-mark byte (must be 0!), checking requires_release in [$releaseFieldAddr]" %} | |
| 6540 ins_encode( enc_cms_card_mark(mem, releaseFieldAddr) ); | |
| 6541 ins_pipe(pipe_class_memory); | |
| 6542 %} | |
| 6543 | |
| 6544 // Card-mark for CMS garbage collection. | |
| 6545 // This cardmark does an optimization so that it must not always | |
| 6546 // do a releasing store. For this, it needs the constant address of | |
| 6547 // CMSCollectorCardTableModRefBSExt::_requires_release. | |
| 6548 // This constant address is split off here by expand so we can use | |
| 6549 // adlc / matcher functionality to load it from the constant section. | |
| 6550 instruct storeCM_CMS_ExEx(memory mem, immI_0 zero) %{ | |
| 6551 match(Set mem (StoreCM mem zero)); | |
| 6552 predicate(UseConcMarkSweepGC); | |
| 6553 | |
| 6554 expand %{ | |
| 6555 immL baseImm %{ 0 /* TODO: PPC port (jlong)CMSCollectorCardTableModRefBSExt::requires_release_address() */ %} | |
| 6556 iRegLdst releaseFieldAddress; | |
| 6557 loadConL_Ex(releaseFieldAddress, baseImm); | |
| 6558 storeCM_CMS(mem, releaseFieldAddress); | |
| 6559 %} | |
| 6560 %} | |
| 6561 | |
| 6562 instruct storeCM_G1(memory mem, immI_0 zero) %{ | |
| 6563 match(Set mem (StoreCM mem zero)); | |
| 6564 predicate(UseG1GC); | |
| 6565 ins_cost(MEMORY_REF_COST); | |
| 6566 | |
| 6567 ins_cannot_rematerialize(true); | |
| 6568 | |
| 6569 format %{ "STB #0, $mem \t// CMS card-mark byte store (G1)" %} | |
| 6570 size(8); | |
| 6571 ins_encode %{ | |
| 6572 // TODO: PPC port $archOpcode(ppc64Opcode_compound); | |
| 6573 __ li(R0, 0); | |
| 6574 //__ release(); // G1: oops are allowed to get visible after dirty marking | |
| 6575 guarantee($mem$$base$$Register != R1_SP, "use frame_slots_bias"); | |
| 6576 __ stb(R0, $mem$$disp, $mem$$base$$Register); | |
| 6577 %} | |
| 6578 ins_pipe(pipe_class_memory); | |
| 6579 %} | |
| 6580 | |
| 6581 // Convert oop pointer into compressed form. | |
| 6582 | |
| 6583 // Nodes for postalloc expand. | |
| 6584 | |
| 6585 // Shift node for expand. | |
| 6586 instruct encodeP_shift(iRegNdst dst, iRegNsrc src) %{ | |
| 6587 // The match rule is needed to make it a 'MachTypeNode'! | |
| 6588 match(Set dst (EncodeP src)); | |
| 6589 predicate(false); | |
| 6590 | |
| 6591 format %{ "SRDI $dst, $src, 3 \t// encode" %} | |
| 6592 size(4); | |
| 6593 ins_encode %{ | |
| 6594 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); | |
| 6595 __ srdi($dst$$Register, $src$$Register, Universe::narrow_oop_shift() & 0x3f); | |
| 6596 %} | |
| 6597 ins_pipe(pipe_class_default); | |
| 6598 %} | |
| 6599 | |
| 6600 // Add node for expand. | |
| 6601 instruct encodeP_sub(iRegPdst dst, iRegPdst src) %{ | |
| 6602 // The match rule is needed to make it a 'MachTypeNode'! | |
| 6603 match(Set dst (EncodeP src)); | |
| 6604 predicate(false); | |
| 6605 | |
| 6606 format %{ "SUB $dst, $src, oop_base \t// encode" %} | |
| 6607 size(4); | |
| 6608 ins_encode %{ | |
| 6609 // TODO: PPC port $archOpcode(ppc64Opcode_subf); | |
| 6610 __ subf($dst$$Register, R30, $src$$Register); | |
| 6611 %} | |
| 6612 ins_pipe(pipe_class_default); | |
| 6613 %} | |
| 6614 | |
| 6615 // Conditional sub base. | |
| 6616 instruct cond_sub_base(iRegNdst dst, flagsReg crx, iRegPsrc src1) %{ | |
| 6617 // The match rule is needed to make it a 'MachTypeNode'! | |
| 6618 match(Set dst (EncodeP (Binary crx src1))); | |
| 6619 predicate(false); | |
| 6620 | |
| 6621 ins_variable_size_depending_on_alignment(true); | |
| 6622 | |
| 6623 format %{ "BEQ $crx, done\n\t" | |
| 6624 "SUB $dst, $src1, R30 \t// encode: subtract base if != NULL\n" | |
| 6625 "done:" %} | |
| 6626 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8); | |
| 6627 ins_encode %{ | |
| 6628 // TODO: PPC port $archOpcode(ppc64Opcode_cmove); | |
| 6629 Label done; | |
| 6630 __ beq($crx$$CondRegister, done); | |
| 6631 __ subf($dst$$Register, R30, $src1$$Register); | |
| 6632 // TODO PPC port __ endgroup_if_needed(_size == 12); | |
| 6633 __ bind(done); | |
| 6634 %} | |
| 6635 ins_pipe(pipe_class_default); | |
| 6636 %} | |
| 6637 | |
| 6638 // Power 7 can use isel instruction | |
| 6639 instruct cond_set_0_oop(iRegNdst dst, flagsReg crx, iRegPsrc src1) %{ | |
| 6640 // The match rule is needed to make it a 'MachTypeNode'! | |
| 6641 match(Set dst (EncodeP (Binary crx src1))); | |
| 6642 predicate(false); | |
| 6643 | |
| 6644 format %{ "CMOVE $dst, $crx eq, 0, $src1 \t// encode: preserve 0" %} | |
| 6645 size(4); | |
| 6646 ins_encode %{ | |
| 6647 // This is a Power7 instruction for which no machine description exists. | |
| 6648 // TODO: PPC port $archOpcode(ppc64Opcode_compound); | |
| 6649 __ isel_0($dst$$Register, $crx$$CondRegister, Assembler::equal, $src1$$Register); | |
| 6650 %} | |
| 6651 ins_pipe(pipe_class_default); | |
| 6652 %} | |
| 6653 | |
| 6654 // base != 0 | |
| 6655 // 32G aligned narrow oop base. | |
| 6656 instruct encodeP_32GAligned(iRegNdst dst, iRegPsrc src) %{ | |
| 6657 match(Set dst (EncodeP src)); | |
| 6658 predicate(false /* TODO: PPC port Universe::narrow_oop_base_disjoint()*/); | |
| 6659 | |
| 6660 format %{ "EXTRDI $dst, $src, #32, #3 \t// encode with 32G aligned base" %} | |
| 6661 size(4); | |
| 6662 ins_encode %{ | |
| 6663 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); | |
| 6664 __ rldicl($dst$$Register, $src$$Register, 64-Universe::narrow_oop_shift(), 32); | |
| 6665 %} | |
| 6666 ins_pipe(pipe_class_default); | |
| 6667 %} | |
| 6668 | |
| 6669 // shift != 0, base != 0 | |
| 6670 instruct encodeP_Ex(iRegNdst dst, flagsReg crx, iRegPsrc src) %{ | |
| 6671 match(Set dst (EncodeP src)); | |
| 6672 effect(TEMP crx); | |
| 6673 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull && | |
| 6674 Universe::narrow_oop_shift() != 0 && | |
| 6675 true /* TODO: PPC port Universe::narrow_oop_base_overlaps()*/); | |
| 6676 | |
| 6677 format %{ "EncodeP $dst, $crx, $src \t// postalloc expanded" %} | |
| 6678 postalloc_expand( postalloc_expand_encode_oop(dst, src, crx)); | |
| 6679 %} | |
| 6680 | |
| 6681 // shift != 0, base != 0 | |
| 6682 instruct encodeP_not_null_Ex(iRegNdst dst, iRegPsrc src) %{ | |
| 6683 match(Set dst (EncodeP src)); | |
| 6684 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull && | |
| 6685 Universe::narrow_oop_shift() != 0 && | |
| 6686 true /* TODO: PPC port Universe::narrow_oop_base_overlaps()*/); | |
| 6687 | |
| 6688 format %{ "EncodeP $dst, $src\t// $src != Null, postalloc expanded" %} | |
| 6689 postalloc_expand( postalloc_expand_encode_oop_not_null(dst, src) ); | |
| 6690 %} | |
| 6691 | |
| 6692 // shift != 0, base == 0 | |
| 6693 // TODO: This is the same as encodeP_shift. Merge! | |
| 6694 instruct encodeP_not_null_base_null(iRegNdst dst, iRegPsrc src) %{ | |
| 6695 match(Set dst (EncodeP src)); | |
| 6696 predicate(Universe::narrow_oop_shift() != 0 && | |
| 6697 Universe::narrow_oop_base() ==0); | |
| 6698 | |
| 6699 format %{ "SRDI $dst, $src, #3 \t// encodeP, $src != NULL" %} | |
| 6700 size(4); | |
| 6701 ins_encode %{ | |
| 6702 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); | |
| 6703 __ srdi($dst$$Register, $src$$Register, Universe::narrow_oop_shift() & 0x3f); | |
| 6704 %} | |
| 6705 ins_pipe(pipe_class_default); | |
| 6706 %} | |
| 6707 | |
| 6708 // Compressed OOPs with narrow_oop_shift == 0. | |
| 6709 // shift == 0, base == 0 | |
| 6710 instruct encodeP_narrow_oop_shift_0(iRegNdst dst, iRegPsrc src) %{ | |
| 6711 match(Set dst (EncodeP src)); | |
| 6712 predicate(Universe::narrow_oop_shift() == 0); | |
| 6713 | |
| 6714 format %{ "MR $dst, $src \t// Ptr->Narrow" %} | |
| 6715 // variable size, 0 or 4. | |
| 6716 ins_encode %{ | |
| 6717 // TODO: PPC port $archOpcode(ppc64Opcode_or); | |
| 6718 __ mr_if_needed($dst$$Register, $src$$Register); | |
| 6719 %} | |
| 6720 ins_pipe(pipe_class_default); | |
| 6721 %} | |
| 6722 | |
| 6723 // Decode nodes. | |
| 6724 | |
| 6725 // Shift node for expand. | |
| 6726 instruct decodeN_shift(iRegPdst dst, iRegPsrc src) %{ | |
| 6727 // The match rule is needed to make it a 'MachTypeNode'! | |
| 6728 match(Set dst (DecodeN src)); | |
| 6729 predicate(false); | |
| 6730 | |
| 6731 format %{ "SLDI $dst, $src, #3 \t// DecodeN" %} | |
| 6732 size(4); | |
| 6733 ins_encode %{ | |
| 6734 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr); | |
| 6735 __ sldi($dst$$Register, $src$$Register, Universe::narrow_oop_shift()); | |
| 6736 %} | |
| 6737 ins_pipe(pipe_class_default); | |
| 6738 %} | |
| 6739 | |
| 6740 // Add node for expand. | |
| 6741 instruct decodeN_add(iRegPdst dst, iRegPdst src) %{ | |
| 6742 // The match rule is needed to make it a 'MachTypeNode'! | |
| 6743 match(Set dst (DecodeN src)); | |
| 6744 predicate(false); | |
| 6745 | |
| 6746 format %{ "ADD $dst, $src, R30 \t// DecodeN, add oop base" %} | |
| 6747 size(4); | |
| 6748 ins_encode %{ | |
| 6749 // TODO: PPC port $archOpcode(ppc64Opcode_add); | |
| 6750 __ add($dst$$Register, $src$$Register, R30); | |
| 6751 %} | |
| 6752 ins_pipe(pipe_class_default); | |
| 6753 %} | |
| 6754 | |
| 6755 // conditianal add base for expand | |
| 6756 instruct cond_add_base(iRegPdst dst, flagsReg crx, iRegPsrc src1) %{ | |
| 6757 // The match rule is needed to make it a 'MachTypeNode'! | |
| 6758 // NOTICE that the rule is nonsense - we just have to make sure that: | |
| 6759 // - _matrule->_rChild->_opType == "DecodeN" (see InstructForm::captures_bottom_type() in formssel.cpp) | |
| 6760 // - we have to match 'crx' to avoid an "illegal USE of non-input: flagsReg crx" error in ADLC. | |
| 6761 match(Set dst (DecodeN (Binary crx src1))); | |
| 6762 predicate(false); | |
| 6763 | |
| 6764 ins_variable_size_depending_on_alignment(true); | |
| 6765 | |
| 6766 format %{ "BEQ $crx, done\n\t" | |
| 6767 "ADD $dst, $src1, R30 \t// DecodeN: add oop base if $src1 != NULL\n" | |
| 6768 "done:" %} | |
| 6769 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling()) */? 12 : 8); | |
| 6770 ins_encode %{ | |
| 6771 // TODO: PPC port $archOpcode(ppc64Opcode_cmove); | |
| 6772 Label done; | |
| 6773 __ beq($crx$$CondRegister, done); | |
| 6774 __ add($dst$$Register, $src1$$Register, R30); | |
|
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|
6775 // TODO PPC port __ endgroup_if_needed(_size == 12); |
| 14445 | 6776 __ bind(done); |
| 6777 %} | |
| 6778 ins_pipe(pipe_class_default); | |
| 6779 %} | |
| 6780 | |
| 6781 instruct cond_set_0_ptr(iRegPdst dst, flagsReg crx, iRegPsrc src1) %{ | |
| 6782 // The match rule is needed to make it a 'MachTypeNode'! | |
| 6783 // NOTICE that the rule is nonsense - we just have to make sure that: | |
| 6784 // - _matrule->_rChild->_opType == "DecodeN" (see InstructForm::captures_bottom_type() in formssel.cpp) | |
| 6785 // - we have to match 'crx' to avoid an "illegal USE of non-input: flagsReg crx" error in ADLC. | |
| 6786 match(Set dst (DecodeN (Binary crx src1))); | |
| 6787 predicate(false); | |
| 6788 | |
| 6789 format %{ "CMOVE $dst, $crx eq, 0, $src1 \t// decode: preserve 0" %} | |
| 6790 size(4); | |
| 6791 ins_encode %{ | |
| 6792 // This is a Power7 instruction for which no machine description exists. | |
| 6793 // TODO: PPC port $archOpcode(ppc64Opcode_compound); | |
| 6794 __ isel_0($dst$$Register, $crx$$CondRegister, Assembler::equal, $src1$$Register); | |
| 6795 %} | |
| 6796 ins_pipe(pipe_class_default); | |
| 6797 %} | |
| 6798 | |
| 6799 // shift != 0, base != 0 | |
| 6800 instruct decodeN_Ex(iRegPdst dst, iRegNsrc src, flagsReg crx) %{ | |
| 6801 match(Set dst (DecodeN src)); | |
| 6802 predicate((n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull && | |
| 6803 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant) && | |
| 6804 Universe::narrow_oop_shift() != 0 && | |
| 6805 Universe::narrow_oop_base() != 0); | |
| 6806 effect(TEMP crx); | |
| 6807 | |
| 6808 format %{ "DecodeN $dst, $src \t// Kills $crx, postalloc expanded" %} | |
| 6809 postalloc_expand( postalloc_expand_decode_oop(dst, src, crx) ); | |
| 6810 %} | |
| 6811 | |
| 6812 // shift != 0, base == 0 | |
| 6813 instruct decodeN_nullBase(iRegPdst dst, iRegNsrc src) %{ | |
| 6814 match(Set dst (DecodeN src)); | |
| 6815 predicate(Universe::narrow_oop_shift() != 0 && | |
| 6816 Universe::narrow_oop_base() == 0); | |
| 6817 | |
| 6818 format %{ "SLDI $dst, $src, #3 \t// DecodeN (zerobased)" %} | |
| 6819 size(4); | |
| 6820 ins_encode %{ | |
| 6821 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr); | |
| 6822 __ sldi($dst$$Register, $src$$Register, Universe::narrow_oop_shift()); | |
| 6823 %} | |
| 6824 ins_pipe(pipe_class_default); | |
| 6825 %} | |
| 6826 | |
| 6827 // src != 0, shift != 0, base != 0 | |
| 6828 instruct decodeN_notNull_addBase_Ex(iRegPdst dst, iRegNsrc src) %{ | |
| 6829 match(Set dst (DecodeN src)); | |
| 6830 predicate((n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull || | |
| 6831 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) && | |
| 6832 Universe::narrow_oop_shift() != 0 && | |
| 6833 Universe::narrow_oop_base() != 0); | |
| 6834 | |
| 6835 format %{ "DecodeN $dst, $src \t// $src != NULL, postalloc expanded" %} | |
| 6836 postalloc_expand( postalloc_expand_decode_oop_not_null(dst, src)); | |
| 6837 %} | |
| 6838 | |
| 6839 // Compressed OOPs with narrow_oop_shift == 0. | |
| 6840 instruct decodeN_unscaled(iRegPdst dst, iRegNsrc src) %{ | |
| 6841 match(Set dst (DecodeN src)); | |
| 6842 predicate(Universe::narrow_oop_shift() == 0); | |
| 6843 ins_cost(DEFAULT_COST); | |
| 6844 | |
| 6845 format %{ "MR $dst, $src \t// DecodeN (unscaled)" %} | |
| 6846 // variable size, 0 or 4. | |
| 6847 ins_encode %{ | |
| 6848 // TODO: PPC port $archOpcode(ppc64Opcode_or); | |
| 6849 __ mr_if_needed($dst$$Register, $src$$Register); | |
| 6850 %} | |
| 6851 ins_pipe(pipe_class_default); | |
| 6852 %} | |
| 6853 | |
| 6854 // Convert compressed oop into int for vectors alignment masking. | |
| 6855 instruct decodeN2I_unscaled(iRegIdst dst, iRegNsrc src) %{ | |
| 6856 match(Set dst (ConvL2I (CastP2X (DecodeN src)))); | |
| 6857 predicate(Universe::narrow_oop_shift() == 0); | |
| 6858 ins_cost(DEFAULT_COST); | |
| 6859 | |
| 6860 format %{ "MR $dst, $src \t// (int)DecodeN (unscaled)" %} | |
| 6861 // variable size, 0 or 4. | |
| 6862 ins_encode %{ | |
| 6863 // TODO: PPC port $archOpcode(ppc64Opcode_or); | |
| 6864 __ mr_if_needed($dst$$Register, $src$$Register); | |
| 6865 %} | |
| 6866 ins_pipe(pipe_class_default); | |
| 6867 %} | |
| 6868 | |
| 6869 // Convert klass pointer into compressed form. | |
| 6870 | |
| 6871 // Nodes for postalloc expand. | |
| 6872 | |
| 6873 // Shift node for expand. | |
| 6874 instruct encodePKlass_shift(iRegNdst dst, iRegNsrc src) %{ | |
| 6875 // The match rule is needed to make it a 'MachTypeNode'! | |
| 6876 match(Set dst (EncodePKlass src)); | |
| 6877 predicate(false); | |
| 6878 | |
| 6879 format %{ "SRDI $dst, $src, 3 \t// encode" %} | |
| 6880 size(4); | |
| 6881 ins_encode %{ | |
| 6882 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); | |
| 6883 __ srdi($dst$$Register, $src$$Register, Universe::narrow_klass_shift()); | |
| 6884 %} | |
| 6885 ins_pipe(pipe_class_default); | |
| 6886 %} | |
| 6887 | |
| 6888 // Add node for expand. | |
| 6889 instruct encodePKlass_sub_base(iRegPdst dst, iRegLsrc base, iRegPdst src) %{ | |
| 6890 // The match rule is needed to make it a 'MachTypeNode'! | |
| 6891 match(Set dst (EncodePKlass (Binary base src))); | |
| 6892 predicate(false); | |
| 6893 | |
| 6894 format %{ "SUB $dst, $base, $src \t// encode" %} | |
| 6895 size(4); | |
| 6896 ins_encode %{ | |
| 6897 // TODO: PPC port $archOpcode(ppc64Opcode_subf); | |
| 6898 __ subf($dst$$Register, $base$$Register, $src$$Register); | |
| 6899 %} | |
| 6900 ins_pipe(pipe_class_default); | |
| 6901 %} | |
| 6902 | |
| 6903 // base != 0 | |
| 6904 // 32G aligned narrow oop base. | |
| 6905 instruct encodePKlass_32GAligned(iRegNdst dst, iRegPsrc src) %{ | |
| 6906 match(Set dst (EncodePKlass src)); | |
| 6907 predicate(false /* TODO: PPC port Universe::narrow_klass_base_disjoint()*/); | |
| 6908 | |
| 6909 format %{ "EXTRDI $dst, $src, #32, #3 \t// encode with 32G aligned base" %} | |
| 6910 size(4); | |
| 6911 ins_encode %{ | |
| 6912 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); | |
| 6913 __ rldicl($dst$$Register, $src$$Register, 64-Universe::narrow_oop_shift(), 32); | |
| 6914 %} | |
| 6915 ins_pipe(pipe_class_default); | |
| 6916 %} | |
| 6917 | |
| 6918 // shift != 0, base != 0 | |
| 6919 instruct encodePKlass_not_null_Ex(iRegNdst dst, iRegLsrc base, iRegPsrc src) %{ | |
| 6920 match(Set dst (EncodePKlass (Binary base src))); | |
| 6921 predicate(false); | |
| 6922 | |
| 6923 format %{ "EncodePKlass $dst, $src\t// $src != Null, postalloc expanded" %} | |
| 6924 postalloc_expand %{ | |
| 6925 encodePKlass_sub_baseNode *n1 = new (C) encodePKlass_sub_baseNode(); | |
| 6926 n1->add_req(n_region, n_base, n_src); | |
| 6927 n1->_opnds[0] = op_dst; | |
| 6928 n1->_opnds[1] = op_base; | |
| 6929 n1->_opnds[2] = op_src; | |
| 6930 n1->_bottom_type = _bottom_type; | |
| 6931 | |
| 6932 encodePKlass_shiftNode *n2 = new (C) encodePKlass_shiftNode(); | |
| 6933 n2->add_req(n_region, n1); | |
| 6934 n2->_opnds[0] = op_dst; | |
| 6935 n2->_opnds[1] = op_dst; | |
| 6936 n2->_bottom_type = _bottom_type; | |
| 6937 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); | |
| 6938 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); | |
| 6939 | |
| 6940 nodes->push(n1); | |
| 6941 nodes->push(n2); | |
| 6942 %} | |
| 6943 %} | |
| 6944 | |
| 6945 // shift != 0, base != 0 | |
| 6946 instruct encodePKlass_not_null_ExEx(iRegNdst dst, iRegPsrc src) %{ | |
| 6947 match(Set dst (EncodePKlass src)); | |
| 6948 //predicate(Universe::narrow_klass_shift() != 0 && | |
| 6949 // true /* TODO: PPC port Universe::narrow_klass_base_overlaps()*/); | |
| 6950 | |
| 6951 //format %{ "EncodePKlass $dst, $src\t// $src != Null, postalloc expanded" %} | |
| 6952 ins_cost(DEFAULT_COST*2); // Don't count constant. | |
| 6953 expand %{ | |
| 6954 immL baseImm %{ (jlong)(intptr_t)Universe::narrow_klass_base() %} | |
| 6955 iRegLdst base; | |
| 6956 loadConL_Ex(base, baseImm); | |
| 6957 encodePKlass_not_null_Ex(dst, base, src); | |
| 6958 %} | |
| 6959 %} | |
| 6960 | |
| 6961 // Decode nodes. | |
| 6962 | |
| 6963 // Shift node for expand. | |
| 6964 instruct decodeNKlass_shift(iRegPdst dst, iRegPsrc src) %{ | |
| 6965 // The match rule is needed to make it a 'MachTypeNode'! | |
| 6966 match(Set dst (DecodeNKlass src)); | |
| 6967 predicate(false); | |
| 6968 | |
| 6969 format %{ "SLDI $dst, $src, #3 \t// DecodeNKlass" %} | |
| 6970 size(4); | |
| 6971 ins_encode %{ | |
| 6972 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr); | |
| 6973 __ sldi($dst$$Register, $src$$Register, Universe::narrow_klass_shift()); | |
| 6974 %} | |
| 6975 ins_pipe(pipe_class_default); | |
| 6976 %} | |
| 6977 | |
| 6978 // Add node for expand. | |
| 6979 | |
| 6980 instruct decodeNKlass_add_base(iRegPdst dst, iRegLsrc base, iRegPdst src) %{ | |
| 6981 // The match rule is needed to make it a 'MachTypeNode'! | |
| 6982 match(Set dst (DecodeNKlass (Binary base src))); | |
| 6983 predicate(false); | |
| 6984 | |
| 6985 format %{ "ADD $dst, $base, $src \t// DecodeNKlass, add klass base" %} | |
| 6986 size(4); | |
| 6987 ins_encode %{ | |
| 6988 // TODO: PPC port $archOpcode(ppc64Opcode_add); | |
| 6989 __ add($dst$$Register, $base$$Register, $src$$Register); | |
| 6990 %} | |
| 6991 ins_pipe(pipe_class_default); | |
| 6992 %} | |
| 6993 | |
| 6994 // src != 0, shift != 0, base != 0 | |
| 6995 instruct decodeNKlass_notNull_addBase_Ex(iRegPdst dst, iRegLsrc base, iRegNsrc src) %{ | |
| 6996 match(Set dst (DecodeNKlass (Binary base src))); | |
| 6997 //effect(kill src); // We need a register for the immediate result after shifting. | |
| 6998 predicate(false); | |
| 6999 | |
| 7000 format %{ "DecodeNKlass $dst = $base + ($src << 3) \t// $src != NULL, postalloc expanded" %} | |
| 7001 postalloc_expand %{ | |
| 7002 decodeNKlass_add_baseNode *n1 = new (C) decodeNKlass_add_baseNode(); | |
| 7003 n1->add_req(n_region, n_base, n_src); | |
| 7004 n1->_opnds[0] = op_dst; | |
| 7005 n1->_opnds[1] = op_base; | |
| 7006 n1->_opnds[2] = op_src; | |
| 7007 n1->_bottom_type = _bottom_type; | |
| 7008 | |
| 7009 decodeNKlass_shiftNode *n2 = new (C) decodeNKlass_shiftNode(); | |
| 7010 n2->add_req(n_region, n2); | |
| 7011 n2->_opnds[0] = op_dst; | |
| 7012 n2->_opnds[1] = op_dst; | |
| 7013 n2->_bottom_type = _bottom_type; | |
| 7014 | |
| 7015 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); | |
| 7016 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); | |
| 7017 | |
| 7018 nodes->push(n1); | |
| 7019 nodes->push(n2); | |
| 7020 %} | |
| 7021 %} | |
| 7022 | |
| 7023 // src != 0, shift != 0, base != 0 | |
| 7024 instruct decodeNKlass_notNull_addBase_ExEx(iRegPdst dst, iRegNsrc src) %{ | |
| 7025 match(Set dst (DecodeNKlass src)); | |
| 7026 // predicate(Universe::narrow_klass_shift() != 0 && | |
| 7027 // Universe::narrow_klass_base() != 0); | |
| 7028 | |
| 7029 //format %{ "DecodeNKlass $dst, $src \t// $src != NULL, expanded" %} | |
| 7030 | |
| 7031 ins_cost(DEFAULT_COST*2); // Don't count constant. | |
| 7032 expand %{ | |
| 7033 // We add first, then we shift. Like this, we can get along with one register less. | |
| 7034 // But we have to load the base pre-shifted. | |
| 7035 immL baseImm %{ (jlong)((intptr_t)Universe::narrow_klass_base() >> Universe::narrow_klass_shift()) %} | |
| 7036 iRegLdst base; | |
| 7037 loadConL_Ex(base, baseImm); | |
| 7038 decodeNKlass_notNull_addBase_Ex(dst, base, src); | |
| 7039 %} | |
| 7040 %} | |
| 7041 | |
| 7042 //----------MemBar Instructions----------------------------------------------- | |
| 7043 // Memory barrier flavors | |
| 7044 | |
| 7045 instruct membar_acquire() %{ | |
| 7046 match(LoadFence); | |
| 7047 ins_cost(4*MEMORY_REF_COST); | |
| 7048 | |
| 7049 format %{ "MEMBAR-acquire" %} | |
| 7050 size(4); | |
| 7051 ins_encode %{ | |
| 7052 // TODO: PPC port $archOpcode(ppc64Opcode_lwsync); | |
| 7053 __ acquire(); | |
| 7054 %} | |
| 7055 ins_pipe(pipe_class_default); | |
| 7056 %} | |
| 7057 | |
| 7058 instruct unnecessary_membar_acquire() %{ | |
| 7059 match(MemBarAcquire); | |
| 7060 ins_cost(0); | |
| 7061 | |
| 7062 format %{ " -- \t// redundant MEMBAR-acquire - empty" %} | |
| 7063 size(0); | |
| 7064 ins_encode( /*empty*/ ); | |
| 7065 ins_pipe(pipe_class_default); | |
| 7066 %} | |
| 7067 | |
| 7068 instruct membar_acquire_lock() %{ | |
| 7069 match(MemBarAcquireLock); | |
| 7070 ins_cost(0); | |
| 7071 | |
| 7072 format %{ " -- \t// redundant MEMBAR-acquire - empty (acquire as part of CAS in prior FastLock)" %} | |
| 7073 size(0); | |
| 7074 ins_encode( /*empty*/ ); | |
| 7075 ins_pipe(pipe_class_default); | |
| 7076 %} | |
| 7077 | |
| 7078 instruct membar_release() %{ | |
| 7079 match(MemBarRelease); | |
| 7080 match(StoreFence); | |
| 7081 ins_cost(4*MEMORY_REF_COST); | |
| 7082 | |
| 7083 format %{ "MEMBAR-release" %} | |
| 7084 size(4); | |
| 7085 ins_encode %{ | |
| 7086 // TODO: PPC port $archOpcode(ppc64Opcode_lwsync); | |
| 7087 __ release(); | |
| 7088 %} | |
| 7089 ins_pipe(pipe_class_default); | |
| 7090 %} | |
| 7091 | |
| 7092 instruct membar_storestore() %{ | |
| 7093 match(MemBarStoreStore); | |
| 7094 ins_cost(4*MEMORY_REF_COST); | |
| 7095 | |
| 7096 format %{ "MEMBAR-store-store" %} | |
| 7097 size(4); | |
| 7098 ins_encode %{ | |
| 7099 // TODO: PPC port $archOpcode(ppc64Opcode_lwsync); | |
| 7100 __ membar(Assembler::StoreStore); | |
| 7101 %} | |
| 7102 ins_pipe(pipe_class_default); | |
| 7103 %} | |
| 7104 | |
| 7105 instruct membar_release_lock() %{ | |
| 7106 match(MemBarReleaseLock); | |
| 7107 ins_cost(0); | |
| 7108 | |
| 7109 format %{ " -- \t// redundant MEMBAR-release - empty (release in FastUnlock)" %} | |
| 7110 size(0); | |
| 7111 ins_encode( /*empty*/ ); | |
| 7112 ins_pipe(pipe_class_default); | |
| 7113 %} | |
| 7114 | |
| 7115 instruct membar_volatile() %{ | |
| 7116 match(MemBarVolatile); | |
| 7117 ins_cost(4*MEMORY_REF_COST); | |
| 7118 | |
| 7119 format %{ "MEMBAR-volatile" %} | |
| 7120 size(4); | |
| 7121 ins_encode %{ | |
| 7122 // TODO: PPC port $archOpcode(ppc64Opcode_sync); | |
| 7123 __ fence(); | |
| 7124 %} | |
| 7125 ins_pipe(pipe_class_default); | |
| 7126 %} | |
| 7127 | |
| 7128 // This optimization is wrong on PPC. The following pattern is not supported: | |
| 7129 // MemBarVolatile | |
| 7130 // ^ ^ | |
| 7131 // | | | |
| 7132 // CtrlProj MemProj | |
| 7133 // ^ ^ | |
| 7134 // | | | |
| 7135 // | Load | |
| 7136 // | | |
| 7137 // MemBarVolatile | |
| 7138 // | |
| 7139 // The first MemBarVolatile could get optimized out! According to | |
| 7140 // Vladimir, this pattern can not occur on Oracle platforms. | |
| 7141 // However, it does occur on PPC64 (because of membars in | |
| 7142 // inline_unsafe_load_store). | |
| 7143 // | |
| 7144 // Add this node again if we found a good solution for inline_unsafe_load_store(). | |
| 7145 // Don't forget to look at the implementation of post_store_load_barrier again, | |
| 7146 // we did other fixes in that method. | |
| 7147 //instruct unnecessary_membar_volatile() %{ | |
| 7148 // match(MemBarVolatile); | |
| 7149 // predicate(Matcher::post_store_load_barrier(n)); | |
| 7150 // ins_cost(0); | |
| 7151 // | |
| 7152 // format %{ " -- \t// redundant MEMBAR-volatile - empty" %} | |
| 7153 // size(0); | |
| 7154 // ins_encode( /*empty*/ ); | |
| 7155 // ins_pipe(pipe_class_default); | |
| 7156 //%} | |
| 7157 | |
| 7158 instruct membar_CPUOrder() %{ | |
| 7159 match(MemBarCPUOrder); | |
| 7160 ins_cost(0); | |
| 7161 | |
| 7162 format %{ " -- \t// MEMBAR-CPUOrder - empty: PPC64 processors are self-consistent." %} | |
| 7163 size(0); | |
| 7164 ins_encode( /*empty*/ ); | |
| 7165 ins_pipe(pipe_class_default); | |
| 7166 %} | |
| 7167 | |
| 7168 //----------Conditional Move--------------------------------------------------- | |
| 7169 | |
| 7170 // Cmove using isel. | |
| 7171 instruct cmovI_reg_isel(cmpOp cmp, flagsReg crx, iRegIdst dst, iRegIsrc src) %{ | |
| 7172 match(Set dst (CMoveI (Binary cmp crx) (Binary dst src))); | |
| 7173 predicate(VM_Version::has_isel()); | |
| 7174 ins_cost(DEFAULT_COST); | |
| 7175 | |
| 7176 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} | |
| 7177 size(4); | |
| 7178 ins_encode %{ | |
| 7179 // This is a Power7 instruction for which no machine description | |
| 7180 // exists. Anyways, the scheduler should be off on Power7. | |
| 7181 // TODO: PPC port $archOpcode(ppc64Opcode_compound); | |
| 7182 int cc = $cmp$$cmpcode; | |
| 7183 __ isel($dst$$Register, $crx$$CondRegister, | |
| 7184 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register); | |
| 7185 %} | |
| 7186 ins_pipe(pipe_class_default); | |
| 7187 %} | |
| 7188 | |
| 7189 instruct cmovI_reg(cmpOp cmp, flagsReg crx, iRegIdst dst, iRegIsrc src) %{ | |
| 7190 match(Set dst (CMoveI (Binary cmp crx) (Binary dst src))); | |
| 7191 predicate(!VM_Version::has_isel()); | |
| 7192 ins_cost(DEFAULT_COST+BRANCH_COST); | |
| 7193 | |
| 7194 ins_variable_size_depending_on_alignment(true); | |
| 7195 | |
| 7196 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} | |
| 7197 // Worst case is branch + move + stop, no stop without scheduler | |
| 7198 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); | |
| 7199 ins_encode( enc_cmove_reg(dst, crx, src, cmp) ); | |
| 7200 ins_pipe(pipe_class_default); | |
| 7201 %} | |
| 7202 | |
| 7203 instruct cmovI_imm(cmpOp cmp, flagsReg crx, iRegIdst dst, immI16 src) %{ | |
| 7204 match(Set dst (CMoveI (Binary cmp crx) (Binary dst src))); | |
| 7205 ins_cost(DEFAULT_COST+BRANCH_COST); | |
| 7206 | |
| 7207 ins_variable_size_depending_on_alignment(true); | |
| 7208 | |
| 7209 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} | |
| 7210 // Worst case is branch + move + stop, no stop without scheduler | |
| 7211 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); | |
| 7212 ins_encode( enc_cmove_imm(dst, crx, src, cmp) ); | |
| 7213 ins_pipe(pipe_class_default); | |
| 7214 %} | |
| 7215 | |
| 7216 // Cmove using isel. | |
| 7217 instruct cmovL_reg_isel(cmpOp cmp, flagsReg crx, iRegLdst dst, iRegLsrc src) %{ | |
| 7218 match(Set dst (CMoveL (Binary cmp crx) (Binary dst src))); | |
| 7219 predicate(VM_Version::has_isel()); | |
| 7220 ins_cost(DEFAULT_COST); | |
| 7221 | |
| 7222 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} | |
| 7223 size(4); | |
| 7224 ins_encode %{ | |
| 7225 // This is a Power7 instruction for which no machine description | |
| 7226 // exists. Anyways, the scheduler should be off on Power7. | |
| 7227 // TODO: PPC port $archOpcode(ppc64Opcode_compound); | |
| 7228 int cc = $cmp$$cmpcode; | |
| 7229 __ isel($dst$$Register, $crx$$CondRegister, | |
| 7230 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register); | |
| 7231 %} | |
| 7232 ins_pipe(pipe_class_default); | |
| 7233 %} | |
| 7234 | |
| 7235 instruct cmovL_reg(cmpOp cmp, flagsReg crx, iRegLdst dst, iRegLsrc src) %{ | |
| 7236 match(Set dst (CMoveL (Binary cmp crx) (Binary dst src))); | |
| 7237 predicate(!VM_Version::has_isel()); | |
| 7238 ins_cost(DEFAULT_COST+BRANCH_COST); | |
| 7239 | |
| 7240 ins_variable_size_depending_on_alignment(true); | |
| 7241 | |
| 7242 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} | |
| 7243 // Worst case is branch + move + stop, no stop without scheduler. | |
| 7244 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); | |
| 7245 ins_encode( enc_cmove_reg(dst, crx, src, cmp) ); | |
| 7246 ins_pipe(pipe_class_default); | |
| 7247 %} | |
| 7248 | |
| 7249 instruct cmovL_imm(cmpOp cmp, flagsReg crx, iRegLdst dst, immL16 src) %{ | |
| 7250 match(Set dst (CMoveL (Binary cmp crx) (Binary dst src))); | |
| 7251 ins_cost(DEFAULT_COST+BRANCH_COST); | |
| 7252 | |
| 7253 ins_variable_size_depending_on_alignment(true); | |
| 7254 | |
| 7255 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} | |
| 7256 // Worst case is branch + move + stop, no stop without scheduler. | |
| 7257 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); | |
| 7258 ins_encode( enc_cmove_imm(dst, crx, src, cmp) ); | |
| 7259 ins_pipe(pipe_class_default); | |
| 7260 %} | |
| 7261 | |
| 7262 // Cmove using isel. | |
| 7263 instruct cmovN_reg_isel(cmpOp cmp, flagsReg crx, iRegNdst dst, iRegNsrc src) %{ | |
| 7264 match(Set dst (CMoveN (Binary cmp crx) (Binary dst src))); | |
| 7265 predicate(VM_Version::has_isel()); | |
| 7266 ins_cost(DEFAULT_COST); | |
| 7267 | |
| 7268 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} | |
| 7269 size(4); | |
| 7270 ins_encode %{ | |
| 7271 // This is a Power7 instruction for which no machine description | |
| 7272 // exists. Anyways, the scheduler should be off on Power7. | |
| 7273 // TODO: PPC port $archOpcode(ppc64Opcode_compound); | |
| 7274 int cc = $cmp$$cmpcode; | |
| 7275 __ isel($dst$$Register, $crx$$CondRegister, | |
| 7276 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register); | |
| 7277 %} | |
| 7278 ins_pipe(pipe_class_default); | |
| 7279 %} | |
| 7280 | |
| 7281 // Conditional move for RegN. Only cmov(reg, reg). | |
| 7282 instruct cmovN_reg(cmpOp cmp, flagsReg crx, iRegNdst dst, iRegNsrc src) %{ | |
| 7283 match(Set dst (CMoveN (Binary cmp crx) (Binary dst src))); | |
| 7284 predicate(!VM_Version::has_isel()); | |
| 7285 ins_cost(DEFAULT_COST+BRANCH_COST); | |
| 7286 | |
| 7287 ins_variable_size_depending_on_alignment(true); | |
| 7288 | |
| 7289 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} | |
| 7290 // Worst case is branch + move + stop, no stop without scheduler. | |
| 7291 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); | |
| 7292 ins_encode( enc_cmove_reg(dst, crx, src, cmp) ); | |
| 7293 ins_pipe(pipe_class_default); | |
| 7294 %} | |
| 7295 | |
| 7296 instruct cmovN_imm(cmpOp cmp, flagsReg crx, iRegNdst dst, immN_0 src) %{ | |
| 7297 match(Set dst (CMoveN (Binary cmp crx) (Binary dst src))); | |
| 7298 ins_cost(DEFAULT_COST+BRANCH_COST); | |
| 7299 | |
| 7300 ins_variable_size_depending_on_alignment(true); | |
| 7301 | |
| 7302 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} | |
| 7303 // Worst case is branch + move + stop, no stop without scheduler. | |
| 7304 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); | |
| 7305 ins_encode( enc_cmove_imm(dst, crx, src, cmp) ); | |
| 7306 ins_pipe(pipe_class_default); | |
| 7307 %} | |
| 7308 | |
| 7309 // Cmove using isel. | |
| 7310 instruct cmovP_reg_isel(cmpOp cmp, flagsReg crx, iRegPdst dst, iRegPsrc src) %{ | |
| 7311 match(Set dst (CMoveP (Binary cmp crx) (Binary dst src))); | |
| 7312 predicate(VM_Version::has_isel()); | |
| 7313 ins_cost(DEFAULT_COST); | |
| 7314 | |
| 7315 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} | |
| 7316 size(4); | |
| 7317 ins_encode %{ | |
| 7318 // This is a Power7 instruction for which no machine description | |
| 7319 // exists. Anyways, the scheduler should be off on Power7. | |
| 7320 // TODO: PPC port $archOpcode(ppc64Opcode_compound); | |
| 7321 int cc = $cmp$$cmpcode; | |
| 7322 __ isel($dst$$Register, $crx$$CondRegister, | |
| 7323 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register); | |
| 7324 %} | |
| 7325 ins_pipe(pipe_class_default); | |
| 7326 %} | |
| 7327 | |
| 7328 instruct cmovP_reg(cmpOp cmp, flagsReg crx, iRegPdst dst, iRegP_N2P src) %{ | |
| 7329 match(Set dst (CMoveP (Binary cmp crx) (Binary dst src))); | |
| 7330 predicate(!VM_Version::has_isel()); | |
| 7331 ins_cost(DEFAULT_COST+BRANCH_COST); | |
| 7332 | |
| 7333 ins_variable_size_depending_on_alignment(true); | |
| 7334 | |
| 7335 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} | |
| 7336 // Worst case is branch + move + stop, no stop without scheduler. | |
| 7337 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); | |
| 7338 ins_encode( enc_cmove_reg(dst, crx, src, cmp) ); | |
| 7339 ins_pipe(pipe_class_default); | |
| 7340 %} | |
| 7341 | |
| 7342 instruct cmovP_imm(cmpOp cmp, flagsReg crx, iRegPdst dst, immP_0 src) %{ | |
| 7343 match(Set dst (CMoveP (Binary cmp crx) (Binary dst src))); | |
| 7344 ins_cost(DEFAULT_COST+BRANCH_COST); | |
| 7345 | |
| 7346 ins_variable_size_depending_on_alignment(true); | |
| 7347 | |
| 7348 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} | |
| 7349 // Worst case is branch + move + stop, no stop without scheduler. | |
| 7350 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); | |
| 7351 ins_encode( enc_cmove_imm(dst, crx, src, cmp) ); | |
| 7352 ins_pipe(pipe_class_default); | |
| 7353 %} | |
| 7354 | |
| 7355 instruct cmovF_reg(cmpOp cmp, flagsReg crx, regF dst, regF src) %{ | |
| 7356 match(Set dst (CMoveF (Binary cmp crx) (Binary dst src))); | |
| 7357 ins_cost(DEFAULT_COST+BRANCH_COST); | |
| 7358 | |
| 7359 ins_variable_size_depending_on_alignment(true); | |
| 7360 | |
| 7361 format %{ "CMOVEF $cmp, $crx, $dst, $src\n\t" %} | |
| 7362 // Worst case is branch + move + stop, no stop without scheduler. | |
| 7363 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8); | |
| 7364 ins_encode %{ | |
| 7365 // TODO: PPC port $archOpcode(ppc64Opcode_cmovef); | |
| 7366 Label done; | |
| 7367 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding"); | |
| 7368 // Branch if not (cmp crx). | |
| 7369 __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done); | |
| 7370 __ fmr($dst$$FloatRegister, $src$$FloatRegister); | |
| 7371 // TODO PPC port __ endgroup_if_needed(_size == 12); | |
| 7372 __ bind(done); | |
| 7373 %} | |
| 7374 ins_pipe(pipe_class_default); | |
| 7375 %} | |
| 7376 | |
| 7377 instruct cmovD_reg(cmpOp cmp, flagsReg crx, regD dst, regD src) %{ | |
| 7378 match(Set dst (CMoveD (Binary cmp crx) (Binary dst src))); | |
| 7379 ins_cost(DEFAULT_COST+BRANCH_COST); | |
| 7380 | |
| 7381 ins_variable_size_depending_on_alignment(true); | |
| 7382 | |
| 7383 format %{ "CMOVEF $cmp, $crx, $dst, $src\n\t" %} | |
| 7384 // Worst case is branch + move + stop, no stop without scheduler. | |
| 7385 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8); | |
| 7386 ins_encode %{ | |
| 7387 // TODO: PPC port $archOpcode(ppc64Opcode_cmovef); | |
| 7388 Label done; | |
| 7389 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding"); | |
| 7390 // Branch if not (cmp crx). | |
| 7391 __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done); | |
| 7392 __ fmr($dst$$FloatRegister, $src$$FloatRegister); | |
| 7393 // TODO PPC port __ endgroup_if_needed(_size == 12); | |
| 7394 __ bind(done); | |
| 7395 %} | |
| 7396 ins_pipe(pipe_class_default); | |
| 7397 %} | |
| 7398 | |
| 7399 //----------Conditional_store-------------------------------------------------- | |
| 7400 // Conditional-store of the updated heap-top. | |
| 7401 // Used during allocation of the shared heap. | |
| 7402 // Sets flags (EQ) on success. Implemented with a CASA on Sparc. | |
| 7403 | |
| 7404 // As compareAndSwapL, but return flag register instead of boolean value in | |
| 7405 // int register. | |
| 7406 // Used by sun/misc/AtomicLongCSImpl.java. | |
| 7407 // Mem_ptr must be a memory operand, else this node does not get | |
| 7408 // Flag_needs_anti_dependence_check set by adlc. If this is not set this node | |
| 7409 // can be rematerialized which leads to errors. | |
| 7410 instruct storeLConditional_regP_regL_regL(flagsReg crx, indirect mem_ptr, iRegLsrc oldVal, iRegLsrc newVal) %{ | |
| 7411 match(Set crx (StoreLConditional mem_ptr (Binary oldVal newVal))); | |
| 7412 format %{ "CMPXCHGD if ($crx = ($oldVal == *$mem_ptr)) *mem_ptr = $newVal; as bool" %} | |
| 7413 ins_encode %{ | |
| 7414 // TODO: PPC port $archOpcode(ppc64Opcode_compound); | |
| 7415 __ cmpxchgd($crx$$CondRegister, R0, $oldVal$$Register, $newVal$$Register, $mem_ptr$$Register, | |
| 7416 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(), | |
| 7417 noreg, NULL, true); | |
| 7418 %} | |
| 7419 ins_pipe(pipe_class_default); | |
| 7420 %} | |
| 7421 | |
| 7422 // As compareAndSwapP, but return flag register instead of boolean value in | |
| 7423 // int register. | |
| 7424 // This instruction is matched if UseTLAB is off. | |
| 7425 // Mem_ptr must be a memory operand, else this node does not get | |
| 7426 // Flag_needs_anti_dependence_check set by adlc. If this is not set this node | |
| 7427 // can be rematerialized which leads to errors. | |
| 7428 instruct storePConditional_regP_regP_regP(flagsReg crx, indirect mem_ptr, iRegPsrc oldVal, iRegPsrc newVal) %{ | |
| 7429 match(Set crx (StorePConditional mem_ptr (Binary oldVal newVal))); | |
| 7430 format %{ "CMPXCHGD if ($crx = ($oldVal == *$mem_ptr)) *mem_ptr = $newVal; as bool" %} | |
| 7431 ins_encode %{ | |
| 7432 // TODO: PPC port $archOpcode(ppc64Opcode_compound); | |
| 7433 __ cmpxchgd($crx$$CondRegister, R0, $oldVal$$Register, $newVal$$Register, $mem_ptr$$Register, | |
| 7434 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(), | |
| 7435 noreg, NULL, true); | |
| 7436 %} | |
| 7437 ins_pipe(pipe_class_default); | |
| 7438 %} | |
| 7439 | |
| 7440 // Implement LoadPLocked. Must be ordered against changes of the memory location | |
| 7441 // by storePConditional. | |
| 7442 // Don't know whether this is ever used. | |
| 7443 instruct loadPLocked(iRegPdst dst, memory mem) %{ | |
| 7444 match(Set dst (LoadPLocked mem)); | |
| 7445 ins_cost(MEMORY_REF_COST); | |
| 7446 | |
| 7447 format %{ "LD $dst, $mem \t// loadPLocked\n\t" | |
| 7448 "TWI $dst\n\t" | |
| 7449 "ISYNC" %} | |
| 7450 size(12); | |
| 7451 ins_encode( enc_ld_ac(dst, mem) ); | |
| 7452 ins_pipe(pipe_class_memory); | |
| 7453 %} | |
| 7454 | |
| 7455 //----------Compare-And-Swap--------------------------------------------------- | |
| 7456 | |
| 7457 // CompareAndSwap{P,I,L} have more than one output, therefore "CmpI | |
| 7458 // (CompareAndSwap ...)" or "If (CmpI (CompareAndSwap ..))" cannot be | |
| 7459 // matched. | |
| 7460 | |
| 7461 instruct compareAndSwapI_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2) %{ | |
| 7462 match(Set res (CompareAndSwapI mem_ptr (Binary src1 src2))); | |
| 7463 format %{ "CMPXCHGW $res, $mem_ptr, $src1, $src2; as bool" %} | |
| 7464 // Variable size: instruction count smaller if regs are disjoint. | |
| 7465 ins_encode %{ | |
| 7466 // TODO: PPC port $archOpcode(ppc64Opcode_compound); | |
| 7467 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'. | |
| 7468 __ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, | |
| 7469 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(), | |
| 7470 $res$$Register, true); | |
| 7471 %} | |
| 7472 ins_pipe(pipe_class_default); | |
| 7473 %} | |
| 7474 | |
| 7475 instruct compareAndSwapN_regP_regN_regN(iRegIdst res, iRegPdst mem_ptr, iRegNsrc src1, iRegNsrc src2) %{ | |
| 7476 match(Set res (CompareAndSwapN mem_ptr (Binary src1 src2))); | |
| 7477 format %{ "CMPXCHGW $res, $mem_ptr, $src1, $src2; as bool" %} | |
| 7478 // Variable size: instruction count smaller if regs are disjoint. | |
| 7479 ins_encode %{ | |
| 7480 // TODO: PPC port $archOpcode(ppc64Opcode_compound); | |
| 7481 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'. | |
| 7482 __ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, | |
| 7483 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(), | |
| 7484 $res$$Register, true); | |
| 7485 %} | |
| 7486 ins_pipe(pipe_class_default); | |
| 7487 %} | |
| 7488 | |
| 7489 instruct compareAndSwapL_regP_regL_regL(iRegIdst res, iRegPdst mem_ptr, iRegLsrc src1, iRegLsrc src2) %{ | |
| 7490 match(Set res (CompareAndSwapL mem_ptr (Binary src1 src2))); | |
| 7491 format %{ "CMPXCHGD $res, $mem_ptr, $src1, $src2; as bool" %} | |
| 7492 // Variable size: instruction count smaller if regs are disjoint. | |
| 7493 ins_encode %{ | |
| 7494 // TODO: PPC port $archOpcode(ppc64Opcode_compound); | |
| 7495 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'. | |
| 7496 __ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, | |
| 7497 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(), | |
| 7498 $res$$Register, NULL, true); | |
| 7499 %} | |
| 7500 ins_pipe(pipe_class_default); | |
| 7501 %} | |
| 7502 | |
| 7503 instruct compareAndSwapP_regP_regP_regP(iRegIdst res, iRegPdst mem_ptr, iRegPsrc src1, iRegPsrc src2) %{ | |
| 7504 match(Set res (CompareAndSwapP mem_ptr (Binary src1 src2))); | |
| 7505 format %{ "CMPXCHGD $res, $mem_ptr, $src1, $src2; as bool; ptr" %} | |
| 7506 // Variable size: instruction count smaller if regs are disjoint. | |
| 7507 ins_encode %{ | |
| 7508 // TODO: PPC port $archOpcode(ppc64Opcode_compound); | |
| 7509 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'. | |
| 7510 __ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, | |
| 7511 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(), | |
| 7512 $res$$Register, NULL, true); | |
| 7513 %} | |
| 7514 ins_pipe(pipe_class_default); | |
| 7515 %} | |
| 7516 | |
| 7517 instruct getAndAddI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{ | |
| 7518 match(Set res (GetAndAddI mem_ptr src)); | |
| 7519 format %{ "GetAndAddI $res, $mem_ptr, $src" %} | |
| 7520 // Variable size: instruction count smaller if regs are disjoint. | |
| 7521 ins_encode( enc_GetAndAddI(res, mem_ptr, src) ); | |
| 7522 ins_pipe(pipe_class_default); | |
| 7523 %} | |
| 7524 | |
| 7525 instruct getAndAddL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{ | |
| 7526 match(Set res (GetAndAddL mem_ptr src)); | |
| 7527 format %{ "GetAndAddL $res, $mem_ptr, $src" %} | |
| 7528 // Variable size: instruction count smaller if regs are disjoint. | |
| 7529 ins_encode( enc_GetAndAddL(res, mem_ptr, src) ); | |
| 7530 ins_pipe(pipe_class_default); | |
| 7531 %} | |
| 7532 | |
| 7533 instruct getAndSetI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{ | |
| 7534 match(Set res (GetAndSetI mem_ptr src)); | |
| 7535 format %{ "GetAndSetI $res, $mem_ptr, $src" %} | |
| 7536 // Variable size: instruction count smaller if regs are disjoint. | |
| 7537 ins_encode( enc_GetAndSetI(res, mem_ptr, src) ); | |
| 7538 ins_pipe(pipe_class_default); | |
| 7539 %} | |
| 7540 | |
| 7541 instruct getAndSetL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{ | |
| 7542 match(Set res (GetAndSetL mem_ptr src)); | |
| 7543 format %{ "GetAndSetL $res, $mem_ptr, $src" %} | |
| 7544 // Variable size: instruction count smaller if regs are disjoint. | |
| 7545 ins_encode( enc_GetAndSetL(res, mem_ptr, src) ); | |
| 7546 ins_pipe(pipe_class_default); | |
| 7547 %} | |
| 7548 | |
| 7549 instruct getAndSetP(iRegPdst res, iRegPdst mem_ptr, iRegPsrc src) %{ | |
| 7550 match(Set res (GetAndSetP mem_ptr src)); | |
| 7551 format %{ "GetAndSetP $res, $mem_ptr, $src" %} | |
| 7552 // Variable size: instruction count smaller if regs are disjoint. | |
| 7553 ins_encode( enc_GetAndSetL(res, mem_ptr, src) ); | |
| 7554 ins_pipe(pipe_class_default); | |
| 7555 %} | |
| 7556 | |
| 7557 instruct getAndSetN(iRegNdst res, iRegPdst mem_ptr, iRegNsrc src) %{ | |
| 7558 match(Set res (GetAndSetN mem_ptr src)); | |
| 7559 format %{ "GetAndSetN $res, $mem_ptr, $src" %} | |
| 7560 // Variable size: instruction count smaller if regs are disjoint. | |
| 7561 ins_encode( enc_GetAndSetI(res, mem_ptr, src) ); | |
| 7562 ins_pipe(pipe_class_default); | |
| 7563 %} | |
| 7564 | |
| 7565 //----------Arithmetic Instructions-------------------------------------------- | |
| 7566 // Addition Instructions | |
| 7567 | |
| 7568 // PPC has no instruction setting overflow of 32-bit integer. | |
| 7569 //instruct addExactI_rReg(rarg4RegI dst, rRegI src, flagsReg cr) %{ | |
| 7570 // match(AddExactI dst src); | |
| 7571 // effect(DEF cr); | |
| 7572 // | |
| 7573 // format %{ "ADD $dst, $dst, $src \t// addExact int, sets $cr" %} | |
| 7574 // ins_encode( enc_add(dst, dst, src) ); | |
| 7575 // ins_pipe(pipe_class_default); | |
| 7576 //%} | |
| 7577 | |
| 7578 // Register Addition | |
| 7579 instruct addI_reg_reg(iRegIdst dst, iRegIsrc_iRegL2Isrc src1, iRegIsrc_iRegL2Isrc src2) %{ | |
| 7580 match(Set dst (AddI src1 src2)); | |
| 7581 format %{ "ADD $dst, $src1, $src2" %} | |
| 7582 size(4); | |
| 7583 ins_encode %{ | |
| 7584 // TODO: PPC port $archOpcode(ppc64Opcode_add); | |
| 7585 __ add($dst$$Register, $src1$$Register, $src2$$Register); | |
| 7586 %} | |
| 7587 ins_pipe(pipe_class_default); | |
| 7588 %} | |
| 7589 | |
| 7590 // Expand does not work with above instruct. (??) | |
| 7591 instruct addI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ | |
| 7592 // no match-rule | |
| 7593 effect(DEF dst, USE src1, USE src2); | |
| 7594 format %{ "ADD $dst, $src1, $src2" %} | |
| 7595 size(4); | |
| 7596 ins_encode %{ | |
| 7597 // TODO: PPC port $archOpcode(ppc64Opcode_add); | |
| 7598 __ add($dst$$Register, $src1$$Register, $src2$$Register); | |
| 7599 %} | |
| 7600 ins_pipe(pipe_class_default); | |
| 7601 %} | |
| 7602 | |
| 7603 instruct tree_addI_addI_addI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{ | |
| 7604 match(Set dst (AddI (AddI (AddI src1 src2) src3) src4)); | |
| 7605 ins_cost(DEFAULT_COST*3); | |
| 7606 | |
| 7607 expand %{ | |
| 7608 // FIXME: we should do this in the ideal world. | |
| 7609 iRegIdst tmp1; | |
| 7610 iRegIdst tmp2; | |
| 7611 addI_reg_reg(tmp1, src1, src2); | |
| 7612 addI_reg_reg_2(tmp2, src3, src4); // Adlc complains about addI_reg_reg. | |
| 7613 addI_reg_reg(dst, tmp1, tmp2); | |
| 7614 %} | |
| 7615 %} | |
| 7616 | |
| 7617 // Immediate Addition | |
| 7618 instruct addI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{ | |
| 7619 match(Set dst (AddI src1 src2)); | |
| 7620 format %{ "ADDI $dst, $src1, $src2" %} | |
| 7621 size(4); | |
| 7622 ins_encode %{ | |
| 7623 // TODO: PPC port $archOpcode(ppc64Opcode_addi); | |
| 7624 __ addi($dst$$Register, $src1$$Register, $src2$$constant); | |
| 7625 %} | |
| 7626 ins_pipe(pipe_class_default); | |
| 7627 %} | |
| 7628 | |
| 7629 // Immediate Addition with 16-bit shifted operand | |
| 7630 instruct addI_reg_immhi16(iRegIdst dst, iRegIsrc src1, immIhi16 src2) %{ | |
| 7631 match(Set dst (AddI src1 src2)); | |
| 7632 format %{ "ADDIS $dst, $src1, $src2" %} | |
| 7633 size(4); | |
| 7634 ins_encode %{ | |
| 7635 // TODO: PPC port $archOpcode(ppc64Opcode_addis); | |
| 7636 __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16); | |
| 7637 %} | |
| 7638 ins_pipe(pipe_class_default); | |
| 7639 %} | |
| 7640 | |
| 7641 // Long Addition | |
| 7642 instruct addL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ | |
| 7643 match(Set dst (AddL src1 src2)); | |
| 7644 format %{ "ADD $dst, $src1, $src2 \t// long" %} | |
| 7645 size(4); | |
| 7646 ins_encode %{ | |
| 7647 // TODO: PPC port $archOpcode(ppc64Opcode_add); | |
| 7648 __ add($dst$$Register, $src1$$Register, $src2$$Register); | |
| 7649 %} | |
| 7650 ins_pipe(pipe_class_default); | |
| 7651 %} | |
| 7652 | |
| 7653 // Expand does not work with above instruct. (??) | |
| 7654 instruct addL_reg_reg_2(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ | |
| 7655 // no match-rule | |
| 7656 effect(DEF dst, USE src1, USE src2); | |
| 7657 format %{ "ADD $dst, $src1, $src2 \t// long" %} | |
| 7658 size(4); | |
| 7659 ins_encode %{ | |
| 7660 // TODO: PPC port $archOpcode(ppc64Opcode_add); | |
| 7661 __ add($dst$$Register, $src1$$Register, $src2$$Register); | |
| 7662 %} | |
| 7663 ins_pipe(pipe_class_default); | |
| 7664 %} | |
| 7665 | |
| 7666 instruct tree_addL_addL_addL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2, iRegLsrc src3, iRegLsrc src4) %{ | |
| 7667 match(Set dst (AddL (AddL (AddL src1 src2) src3) src4)); | |
| 7668 ins_cost(DEFAULT_COST*3); | |
| 7669 | |
| 7670 expand %{ | |
| 7671 // FIXME: we should do this in the ideal world. | |
| 7672 iRegLdst tmp1; | |
| 7673 iRegLdst tmp2; | |
| 7674 addL_reg_reg(tmp1, src1, src2); | |
| 7675 addL_reg_reg_2(tmp2, src3, src4); // Adlc complains about orI_reg_reg. | |
| 7676 addL_reg_reg(dst, tmp1, tmp2); | |
| 7677 %} | |
| 7678 %} | |
| 7679 | |
| 7680 // AddL + ConvL2I. | |
| 7681 instruct addI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{ | |
| 7682 match(Set dst (ConvL2I (AddL src1 src2))); | |
| 7683 | |
| 7684 format %{ "ADD $dst, $src1, $src2 \t// long + l2i" %} | |
| 7685 size(4); | |
| 7686 ins_encode %{ | |
| 7687 // TODO: PPC port $archOpcode(ppc64Opcode_add); | |
| 7688 __ add($dst$$Register, $src1$$Register, $src2$$Register); | |
| 7689 %} | |
| 7690 ins_pipe(pipe_class_default); | |
| 7691 %} | |
| 7692 | |
| 7693 // No constant pool entries required. | |
| 7694 instruct addL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{ | |
| 7695 match(Set dst (AddL src1 src2)); | |
| 7696 | |
| 7697 format %{ "ADDI $dst, $src1, $src2" %} | |
| 7698 size(4); | |
| 7699 ins_encode %{ | |
| 7700 // TODO: PPC port $archOpcode(ppc64Opcode_addi); | |
| 7701 __ addi($dst$$Register, $src1$$Register, $src2$$constant); | |
| 7702 %} | |
| 7703 ins_pipe(pipe_class_default); | |
| 7704 %} | |
| 7705 | |
| 7706 // Long Immediate Addition with 16-bit shifted operand. | |
| 7707 // No constant pool entries required. | |
| 7708 instruct addL_reg_immhi16(iRegLdst dst, iRegLsrc src1, immL32hi16 src2) %{ | |
| 7709 match(Set dst (AddL src1 src2)); | |
| 7710 | |
| 7711 format %{ "ADDIS $dst, $src1, $src2" %} | |
| 7712 size(4); | |
| 7713 ins_encode %{ | |
| 7714 // TODO: PPC port $archOpcode(ppc64Opcode_addis); | |
| 7715 __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16); | |
| 7716 %} | |
| 7717 ins_pipe(pipe_class_default); | |
| 7718 %} | |
| 7719 | |
| 7720 // Pointer Register Addition | |
| 7721 instruct addP_reg_reg(iRegPdst dst, iRegP_N2P src1, iRegLsrc src2) %{ | |
| 7722 match(Set dst (AddP src1 src2)); | |
| 7723 format %{ "ADD $dst, $src1, $src2" %} | |
| 7724 size(4); | |
| 7725 ins_encode %{ | |
| 7726 // TODO: PPC port $archOpcode(ppc64Opcode_add); | |
| 7727 __ add($dst$$Register, $src1$$Register, $src2$$Register); | |
| 7728 %} | |
| 7729 ins_pipe(pipe_class_default); | |
| 7730 %} | |
| 7731 | |
| 7732 // Pointer Immediate Addition | |
| 7733 // No constant pool entries required. | |
| 7734 instruct addP_reg_imm16(iRegPdst dst, iRegP_N2P src1, immL16 src2) %{ | |
| 7735 match(Set dst (AddP src1 src2)); | |
| 7736 | |
| 7737 format %{ "ADDI $dst, $src1, $src2" %} | |
| 7738 size(4); | |
| 7739 ins_encode %{ | |
| 7740 // TODO: PPC port $archOpcode(ppc64Opcode_addi); | |
| 7741 __ addi($dst$$Register, $src1$$Register, $src2$$constant); | |
| 7742 %} | |
| 7743 ins_pipe(pipe_class_default); | |
| 7744 %} | |
| 7745 | |
| 7746 // Pointer Immediate Addition with 16-bit shifted operand. | |
| 7747 // No constant pool entries required. | |
| 7748 instruct addP_reg_immhi16(iRegPdst dst, iRegP_N2P src1, immL32hi16 src2) %{ | |
| 7749 match(Set dst (AddP src1 src2)); | |
| 7750 | |
| 7751 format %{ "ADDIS $dst, $src1, $src2" %} | |
| 7752 size(4); | |
| 7753 ins_encode %{ | |
| 7754 // TODO: PPC port $archOpcode(ppc64Opcode_addis); | |
| 7755 __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16); | |
| 7756 %} | |
| 7757 ins_pipe(pipe_class_default); | |
| 7758 %} | |
| 7759 | |
| 7760 //--------------------- | |
| 7761 // Subtraction Instructions | |
| 7762 | |
| 7763 // Register Subtraction | |
| 7764 instruct subI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ | |
| 7765 match(Set dst (SubI src1 src2)); | |
| 7766 format %{ "SUBF $dst, $src2, $src1" %} | |
| 7767 size(4); | |
| 7768 ins_encode %{ | |
| 7769 // TODO: PPC port $archOpcode(ppc64Opcode_subf); | |
| 7770 __ subf($dst$$Register, $src2$$Register, $src1$$Register); | |
| 7771 %} | |
| 7772 ins_pipe(pipe_class_default); | |
| 7773 %} | |
| 7774 | |
| 7775 // Immediate Subtraction | |
| 7776 // The compiler converts "x-c0" into "x+ -c0" (see SubINode::Ideal), | |
| 7777 // so this rule seems to be unused. | |
| 7778 instruct subI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{ | |
| 7779 match(Set dst (SubI src1 src2)); | |
| 7780 format %{ "SUBI $dst, $src1, $src2" %} | |
| 7781 size(4); | |
| 7782 ins_encode %{ | |
| 7783 // TODO: PPC port $archOpcode(ppc64Opcode_addi); | |
| 7784 __ addi($dst$$Register, $src1$$Register, ($src2$$constant) * (-1)); | |
| 7785 %} | |
| 7786 ins_pipe(pipe_class_default); | |
| 7787 %} | |
| 7788 | |
| 7789 // SubI from constant (using subfic). | |
| 7790 instruct subI_imm16_reg(iRegIdst dst, immI16 src1, iRegIsrc src2) %{ | |
| 7791 match(Set dst (SubI src1 src2)); | |
| 7792 format %{ "SUBI $dst, $src1, $src2" %} | |
| 7793 | |
| 7794 size(4); | |
| 7795 ins_encode %{ | |
| 7796 // TODO: PPC port $archOpcode(ppc64Opcode_subfic); | |
| 7797 __ subfic($dst$$Register, $src2$$Register, $src1$$constant); | |
| 7798 %} | |
| 7799 ins_pipe(pipe_class_default); | |
| 7800 %} | |
| 7801 | |
| 7802 // Turn the sign-bit of an integer into a 32-bit mask, 0x0...0 for | |
| 7803 // positive integers and 0xF...F for negative ones. | |
| 7804 instruct signmask32I_regI(iRegIdst dst, iRegIsrc src) %{ | |
| 7805 // no match-rule, false predicate | |
| 7806 effect(DEF dst, USE src); | |
| 7807 predicate(false); | |
| 7808 | |
| 7809 format %{ "SRAWI $dst, $src, #31" %} | |
| 7810 size(4); | |
| 7811 ins_encode %{ | |
| 7812 // TODO: PPC port $archOpcode(ppc64Opcode_srawi); | |
| 7813 __ srawi($dst$$Register, $src$$Register, 0x1f); | |
| 7814 %} | |
| 7815 ins_pipe(pipe_class_default); | |
| 7816 %} | |
| 7817 | |
| 7818 instruct absI_reg_Ex(iRegIdst dst, iRegIsrc src) %{ | |
| 7819 match(Set dst (AbsI src)); | |
| 7820 ins_cost(DEFAULT_COST*3); | |
| 7821 | |
| 7822 expand %{ | |
| 7823 iRegIdst tmp1; | |
| 7824 iRegIdst tmp2; | |
| 7825 signmask32I_regI(tmp1, src); | |
| 7826 xorI_reg_reg(tmp2, tmp1, src); | |
| 7827 subI_reg_reg(dst, tmp2, tmp1); | |
| 7828 %} | |
| 7829 %} | |
| 7830 | |
| 7831 instruct negI_regI(iRegIdst dst, immI_0 zero, iRegIsrc src2) %{ | |
| 7832 match(Set dst (SubI zero src2)); | |
| 7833 format %{ "NEG $dst, $src2" %} | |
| 7834 size(4); | |
| 7835 ins_encode %{ | |
| 7836 // TODO: PPC port $archOpcode(ppc64Opcode_neg); | |
| 7837 __ neg($dst$$Register, $src2$$Register); | |
| 7838 %} | |
| 7839 ins_pipe(pipe_class_default); | |
| 7840 %} | |
| 7841 | |
| 7842 // Long subtraction | |
| 7843 instruct subL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ | |
| 7844 match(Set dst (SubL src1 src2)); | |
| 7845 format %{ "SUBF $dst, $src2, $src1 \t// long" %} | |
| 7846 size(4); | |
| 7847 ins_encode %{ | |
| 7848 // TODO: PPC port $archOpcode(ppc64Opcode_subf); | |
| 7849 __ subf($dst$$Register, $src2$$Register, $src1$$Register); | |
| 7850 %} | |
| 7851 ins_pipe(pipe_class_default); | |
| 7852 %} | |
| 7853 | |
| 7854 // SubL + convL2I. | |
| 7855 instruct subI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{ | |
| 7856 match(Set dst (ConvL2I (SubL src1 src2))); | |
| 7857 | |
| 7858 format %{ "SUBF $dst, $src2, $src1 \t// long + l2i" %} | |
| 7859 size(4); | |
| 7860 ins_encode %{ | |
| 7861 // TODO: PPC port $archOpcode(ppc64Opcode_subf); | |
| 7862 __ subf($dst$$Register, $src2$$Register, $src1$$Register); | |
| 7863 %} | |
| 7864 ins_pipe(pipe_class_default); | |
| 7865 %} | |
| 7866 | |
| 7867 // Immediate Subtraction | |
| 7868 // The compiler converts "x-c0" into "x+ -c0" (see SubLNode::Ideal), | |
| 7869 // so this rule seems to be unused. | |
| 7870 // No constant pool entries required. | |
| 7871 instruct subL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{ | |
| 7872 match(Set dst (SubL src1 src2)); | |
| 7873 | |
| 7874 format %{ "SUBI $dst, $src1, $src2 \t// long" %} | |
| 7875 size(4); | |
| 7876 ins_encode %{ | |
| 7877 // TODO: PPC port $archOpcode(ppc64Opcode_addi); | |
| 7878 __ addi($dst$$Register, $src1$$Register, ($src2$$constant) * (-1)); | |
| 7879 %} | |
| 7880 ins_pipe(pipe_class_default); | |
| 7881 %} | |
| 7882 | |
| 7883 // Turn the sign-bit of a long into a 64-bit mask, 0x0...0 for | |
| 7884 // positive longs and 0xF...F for negative ones. | |
| 7885 instruct signmask64I_regI(iRegIdst dst, iRegIsrc src) %{ | |
| 7886 // no match-rule, false predicate | |
| 7887 effect(DEF dst, USE src); | |
| 7888 predicate(false); | |
| 7889 | |
| 7890 format %{ "SRADI $dst, $src, #63" %} | |
| 7891 size(4); | |
| 7892 ins_encode %{ | |
| 7893 // TODO: PPC port $archOpcode(ppc64Opcode_sradi); | |
| 7894 __ sradi($dst$$Register, $src$$Register, 0x3f); | |
| 7895 %} | |
| 7896 ins_pipe(pipe_class_default); | |
| 7897 %} | |
| 7898 | |
| 7899 // Long negation | |
| 7900 instruct negL_reg_reg(iRegLdst dst, immL_0 zero, iRegLsrc src2) %{ | |
| 7901 match(Set dst (SubL zero src2)); | |
| 7902 format %{ "NEG $dst, $src2 \t// long" %} | |
| 7903 size(4); | |
| 7904 ins_encode %{ | |
| 7905 // TODO: PPC port $archOpcode(ppc64Opcode_neg); | |
| 7906 __ neg($dst$$Register, $src2$$Register); | |
| 7907 %} | |
| 7908 ins_pipe(pipe_class_default); | |
| 7909 %} | |
| 7910 | |
| 7911 // NegL + ConvL2I. | |
| 7912 instruct negI_con0_regL(iRegIdst dst, immL_0 zero, iRegLsrc src2) %{ | |
| 7913 match(Set dst (ConvL2I (SubL zero src2))); | |
| 7914 | |
| 7915 format %{ "NEG $dst, $src2 \t// long + l2i" %} | |
| 7916 size(4); | |
| 7917 ins_encode %{ | |
| 7918 // TODO: PPC port $archOpcode(ppc64Opcode_neg); | |
| 7919 __ neg($dst$$Register, $src2$$Register); | |
| 7920 %} | |
| 7921 ins_pipe(pipe_class_default); | |
| 7922 %} | |
| 7923 | |
| 7924 // Multiplication Instructions | |
| 7925 // Integer Multiplication | |
| 7926 | |
| 7927 // Register Multiplication | |
| 7928 instruct mulI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ | |
| 7929 match(Set dst (MulI src1 src2)); | |
| 7930 ins_cost(DEFAULT_COST); | |
| 7931 | |
| 7932 format %{ "MULLW $dst, $src1, $src2" %} | |
| 7933 size(4); | |
| 7934 ins_encode %{ | |
| 7935 // TODO: PPC port $archOpcode(ppc64Opcode_mullw); | |
| 7936 __ mullw($dst$$Register, $src1$$Register, $src2$$Register); | |
| 7937 %} | |
| 7938 ins_pipe(pipe_class_default); | |
| 7939 %} | |
| 7940 | |
| 7941 // Immediate Multiplication | |
| 7942 instruct mulI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{ | |
| 7943 match(Set dst (MulI src1 src2)); | |
| 7944 ins_cost(DEFAULT_COST); | |
| 7945 | |
| 7946 format %{ "MULLI $dst, $src1, $src2" %} | |
| 7947 size(4); | |
| 7948 ins_encode %{ | |
| 7949 // TODO: PPC port $archOpcode(ppc64Opcode_mulli); | |
| 7950 __ mulli($dst$$Register, $src1$$Register, $src2$$constant); | |
| 7951 %} | |
| 7952 ins_pipe(pipe_class_default); | |
| 7953 %} | |
| 7954 | |
| 7955 instruct mulL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ | |
| 7956 match(Set dst (MulL src1 src2)); | |
| 7957 ins_cost(DEFAULT_COST); | |
| 7958 | |
| 7959 format %{ "MULLD $dst $src1, $src2 \t// long" %} | |
| 7960 size(4); | |
| 7961 ins_encode %{ | |
| 7962 // TODO: PPC port $archOpcode(ppc64Opcode_mulld); | |
| 7963 __ mulld($dst$$Register, $src1$$Register, $src2$$Register); | |
| 7964 %} | |
| 7965 ins_pipe(pipe_class_default); | |
| 7966 %} | |
| 7967 | |
| 7968 // Multiply high for optimized long division by constant. | |
| 7969 instruct mulHighL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ | |
| 7970 match(Set dst (MulHiL src1 src2)); | |
| 7971 ins_cost(DEFAULT_COST); | |
| 7972 | |
| 7973 format %{ "MULHD $dst $src1, $src2 \t// long" %} | |
| 7974 size(4); | |
| 7975 ins_encode %{ | |
| 7976 // TODO: PPC port $archOpcode(ppc64Opcode_mulhd); | |
| 7977 __ mulhd($dst$$Register, $src1$$Register, $src2$$Register); | |
| 7978 %} | |
| 7979 ins_pipe(pipe_class_default); | |
| 7980 %} | |
| 7981 | |
| 7982 // Immediate Multiplication | |
| 7983 instruct mulL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{ | |
| 7984 match(Set dst (MulL src1 src2)); | |
| 7985 ins_cost(DEFAULT_COST); | |
| 7986 | |
| 7987 format %{ "MULLI $dst, $src1, $src2" %} | |
| 7988 size(4); | |
| 7989 ins_encode %{ | |
| 7990 // TODO: PPC port $archOpcode(ppc64Opcode_mulli); | |
| 7991 __ mulli($dst$$Register, $src1$$Register, $src2$$constant); | |
| 7992 %} | |
| 7993 ins_pipe(pipe_class_default); | |
| 7994 %} | |
| 7995 | |
| 7996 // Integer Division with Immediate -1: Negate. | |
| 7997 instruct divI_reg_immIvalueMinus1(iRegIdst dst, iRegIsrc src1, immI_minus1 src2) %{ | |
| 7998 match(Set dst (DivI src1 src2)); | |
| 7999 ins_cost(DEFAULT_COST); | |
| 8000 | |
| 8001 format %{ "NEG $dst, $src1 \t// /-1" %} | |
| 8002 size(4); | |
| 8003 ins_encode %{ | |
| 8004 // TODO: PPC port $archOpcode(ppc64Opcode_neg); | |
| 8005 __ neg($dst$$Register, $src1$$Register); | |
| 8006 %} | |
| 8007 ins_pipe(pipe_class_default); | |
| 8008 %} | |
| 8009 | |
| 8010 // Integer Division with constant, but not -1. | |
| 8011 // We should be able to improve this by checking the type of src2. | |
| 8012 // It might well be that src2 is known to be positive. | |
| 8013 instruct divI_reg_regnotMinus1(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ | |
| 8014 match(Set dst (DivI src1 src2)); | |
| 8015 predicate(n->in(2)->find_int_con(-1) != -1); // src2 is a constant, but not -1 | |
| 8016 ins_cost(2*DEFAULT_COST); | |
| 8017 | |
| 8018 format %{ "DIVW $dst, $src1, $src2 \t// /not-1" %} | |
| 8019 size(4); | |
| 8020 ins_encode %{ | |
| 8021 // TODO: PPC port $archOpcode(ppc64Opcode_divw); | |
| 8022 __ divw($dst$$Register, $src1$$Register, $src2$$Register); | |
| 8023 %} | |
| 8024 ins_pipe(pipe_class_default); | |
| 8025 %} | |
| 8026 | |
| 8027 instruct cmovI_bne_negI_reg(iRegIdst dst, flagsReg crx, iRegIsrc src1) %{ | |
| 8028 effect(USE_DEF dst, USE src1, USE crx); | |
| 8029 predicate(false); | |
| 8030 | |
| 8031 ins_variable_size_depending_on_alignment(true); | |
| 8032 | |
| 8033 format %{ "CMOVE $dst, neg($src1), $crx" %} | |
| 8034 // Worst case is branch + move + stop, no stop without scheduler. | |
| 8035 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8); | |
| 8036 ins_encode %{ | |
| 8037 // TODO: PPC port $archOpcode(ppc64Opcode_cmove); | |
| 8038 Label done; | |
| 8039 __ bne($crx$$CondRegister, done); | |
| 8040 __ neg($dst$$Register, $src1$$Register); | |
| 8041 // TODO PPC port __ endgroup_if_needed(_size == 12); | |
| 8042 __ bind(done); | |
| 8043 %} | |
| 8044 ins_pipe(pipe_class_default); | |
| 8045 %} | |
| 8046 | |
| 8047 // Integer Division with Registers not containing constants. | |
| 8048 instruct divI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ | |
| 8049 match(Set dst (DivI src1 src2)); | |
| 8050 ins_cost(10*DEFAULT_COST); | |
| 8051 | |
| 8052 expand %{ | |
| 8053 immI16 imm %{ (int)-1 %} | |
| 8054 flagsReg tmp1; | |
| 8055 cmpI_reg_imm16(tmp1, src2, imm); // check src2 == -1 | |
| 8056 divI_reg_regnotMinus1(dst, src1, src2); // dst = src1 / src2 | |
| 8057 cmovI_bne_negI_reg(dst, tmp1, src1); // cmove dst = neg(src1) if src2 == -1 | |
| 8058 %} | |
| 8059 %} | |
| 8060 | |
| 8061 // Long Division with Immediate -1: Negate. | |
| 8062 instruct divL_reg_immLvalueMinus1(iRegLdst dst, iRegLsrc src1, immL_minus1 src2) %{ | |
| 8063 match(Set dst (DivL src1 src2)); | |
| 8064 ins_cost(DEFAULT_COST); | |
| 8065 | |
| 8066 format %{ "NEG $dst, $src1 \t// /-1, long" %} | |
| 8067 size(4); | |
| 8068 ins_encode %{ | |
| 8069 // TODO: PPC port $archOpcode(ppc64Opcode_neg); | |
| 8070 __ neg($dst$$Register, $src1$$Register); | |
| 8071 %} | |
| 8072 ins_pipe(pipe_class_default); | |
| 8073 %} | |
| 8074 | |
| 8075 // Long Division with constant, but not -1. | |
| 8076 instruct divL_reg_regnotMinus1(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ | |
| 8077 match(Set dst (DivL src1 src2)); | |
| 8078 predicate(n->in(2)->find_long_con(-1L) != -1L); // Src2 is a constant, but not -1. | |
| 8079 ins_cost(2*DEFAULT_COST); | |
| 8080 | |
| 8081 format %{ "DIVD $dst, $src1, $src2 \t// /not-1, long" %} | |
| 8082 size(4); | |
| 8083 ins_encode %{ | |
| 8084 // TODO: PPC port $archOpcode(ppc64Opcode_divd); | |
| 8085 __ divd($dst$$Register, $src1$$Register, $src2$$Register); | |
| 8086 %} | |
| 8087 ins_pipe(pipe_class_default); | |
| 8088 %} | |
| 8089 | |
| 8090 instruct cmovL_bne_negL_reg(iRegLdst dst, flagsReg crx, iRegLsrc src1) %{ | |
| 8091 effect(USE_DEF dst, USE src1, USE crx); | |
| 8092 predicate(false); | |
| 8093 | |
| 8094 ins_variable_size_depending_on_alignment(true); | |
| 8095 | |
| 8096 format %{ "CMOVE $dst, neg($src1), $crx" %} | |
| 8097 // Worst case is branch + move + stop, no stop without scheduler. | |
| 8098 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8); | |
| 8099 ins_encode %{ | |
| 8100 // TODO: PPC port $archOpcode(ppc64Opcode_cmove); | |
| 8101 Label done; | |
| 8102 __ bne($crx$$CondRegister, done); | |
| 8103 __ neg($dst$$Register, $src1$$Register); | |
| 8104 // TODO PPC port __ endgroup_if_needed(_size == 12); | |
| 8105 __ bind(done); | |
| 8106 %} | |
| 8107 ins_pipe(pipe_class_default); | |
| 8108 %} | |
| 8109 | |
| 8110 // Long Division with Registers not containing constants. | |
| 8111 instruct divL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ | |
| 8112 match(Set dst (DivL src1 src2)); | |
| 8113 ins_cost(10*DEFAULT_COST); | |
| 8114 | |
| 8115 expand %{ | |
| 8116 immL16 imm %{ (int)-1 %} | |
| 8117 flagsReg tmp1; | |
| 8118 cmpL_reg_imm16(tmp1, src2, imm); // check src2 == -1 | |
| 8119 divL_reg_regnotMinus1(dst, src1, src2); // dst = src1 / src2 | |
| 8120 cmovL_bne_negL_reg(dst, tmp1, src1); // cmove dst = neg(src1) if src2 == -1 | |
| 8121 %} | |
| 8122 %} | |
| 8123 | |
| 8124 // Integer Remainder with registers. | |
| 8125 instruct modI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ | |
| 8126 match(Set dst (ModI src1 src2)); | |
| 8127 ins_cost(10*DEFAULT_COST); | |
| 8128 | |
| 8129 expand %{ | |
| 8130 immI16 imm %{ (int)-1 %} | |
| 8131 flagsReg tmp1; | |
| 8132 iRegIdst tmp2; | |
| 8133 iRegIdst tmp3; | |
| 8134 cmpI_reg_imm16(tmp1, src2, imm); // check src2 == -1 | |
| 8135 divI_reg_regnotMinus1(tmp2, src1, src2); // tmp2 = src1 / src2 | |
| 8136 cmovI_bne_negI_reg(tmp2, tmp1, src1); // cmove tmp2 = neg(src1) if src2 == -1 | |
| 8137 mulI_reg_reg(tmp3, src2, tmp2); // tmp3 = src2 * tmp2 | |
| 8138 subI_reg_reg(dst, src1, tmp3); // dst = src1 - tmp3 | |
| 8139 %} | |
| 8140 %} | |
| 8141 | |
| 8142 // Long Remainder with registers | |
| 8143 instruct modL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2, flagsRegCR0 cr0) %{ | |
| 8144 match(Set dst (ModL src1 src2)); | |
| 8145 ins_cost(10*DEFAULT_COST); | |
| 8146 | |
| 8147 expand %{ | |
| 8148 immL16 imm %{ (int)-1 %} | |
| 8149 flagsReg tmp1; | |
| 8150 iRegLdst tmp2; | |
| 8151 iRegLdst tmp3; | |
| 8152 cmpL_reg_imm16(tmp1, src2, imm); // check src2 == -1 | |
| 8153 divL_reg_regnotMinus1(tmp2, src1, src2); // tmp2 = src1 / src2 | |
| 8154 cmovL_bne_negL_reg(tmp2, tmp1, src1); // cmove tmp2 = neg(src1) if src2 == -1 | |
| 8155 mulL_reg_reg(tmp3, src2, tmp2); // tmp3 = src2 * tmp2 | |
| 8156 subL_reg_reg(dst, src1, tmp3); // dst = src1 - tmp3 | |
| 8157 %} | |
| 8158 %} | |
| 8159 | |
| 8160 // Integer Shift Instructions | |
| 8161 | |
| 8162 // Register Shift Left | |
| 8163 | |
| 8164 // Clear all but the lowest #mask bits. | |
| 8165 // Used to normalize shift amounts in registers. | |
| 8166 instruct maskI_reg_imm(iRegIdst dst, iRegIsrc src, uimmI6 mask) %{ | |
| 8167 // no match-rule, false predicate | |
| 8168 effect(DEF dst, USE src, USE mask); | |
| 8169 predicate(false); | |
| 8170 | |
| 8171 format %{ "MASK $dst, $src, $mask \t// clear $mask upper bits" %} | |
| 8172 size(4); | |
| 8173 ins_encode %{ | |
| 8174 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); | |
| 8175 __ clrldi($dst$$Register, $src$$Register, $mask$$constant); | |
| 8176 %} | |
| 8177 ins_pipe(pipe_class_default); | |
| 8178 %} | |
| 8179 | |
| 8180 instruct lShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ | |
| 8181 // no match-rule, false predicate | |
| 8182 effect(DEF dst, USE src1, USE src2); | |
| 8183 predicate(false); | |
| 8184 | |
| 8185 format %{ "SLW $dst, $src1, $src2" %} | |
| 8186 size(4); | |
| 8187 ins_encode %{ | |
| 8188 // TODO: PPC port $archOpcode(ppc64Opcode_slw); | |
| 8189 __ slw($dst$$Register, $src1$$Register, $src2$$Register); | |
| 8190 %} | |
| 8191 ins_pipe(pipe_class_default); | |
| 8192 %} | |
| 8193 | |
| 8194 instruct lShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ | |
| 8195 match(Set dst (LShiftI src1 src2)); | |
| 8196 ins_cost(DEFAULT_COST*2); | |
| 8197 expand %{ | |
| 8198 uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %} | |
| 8199 iRegIdst tmpI; | |
| 8200 maskI_reg_imm(tmpI, src2, mask); | |
| 8201 lShiftI_reg_reg(dst, src1, tmpI); | |
| 8202 %} | |
| 8203 %} | |
| 8204 | |
| 8205 // Register Shift Left Immediate | |
| 8206 instruct lShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{ | |
| 8207 match(Set dst (LShiftI src1 src2)); | |
| 8208 | |
| 8209 format %{ "SLWI $dst, $src1, ($src2 & 0x1f)" %} | |
| 8210 size(4); | |
| 8211 ins_encode %{ | |
| 8212 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); | |
| 8213 __ slwi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f); | |
| 8214 %} | |
| 8215 ins_pipe(pipe_class_default); | |
| 8216 %} | |
| 8217 | |
| 8218 // AndI with negpow2-constant + LShiftI | |
| 8219 instruct lShiftI_andI_immInegpow2_imm5(iRegIdst dst, iRegIsrc src1, immInegpow2 src2, uimmI5 src3) %{ | |
| 8220 match(Set dst (LShiftI (AndI src1 src2) src3)); | |
| 8221 predicate(UseRotateAndMaskInstructionsPPC64); | |
| 8222 | |
| 8223 format %{ "RLWINM $dst, lShiftI(AndI($src1, $src2), $src3)" %} | |
| 8224 size(4); | |
| 8225 ins_encode %{ | |
| 8226 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); // FIXME: assert that rlwinm is equal to addi | |
| 8227 long src2 = $src2$$constant; | |
| 8228 long src3 = $src3$$constant; | |
| 8229 long maskbits = src3 + log2_long((jlong) (julong) (juint) -src2); | |
| 8230 if (maskbits >= 32) { | |
| 8231 __ li($dst$$Register, 0); // addi | |
| 8232 } else { | |
| 8233 __ rlwinm($dst$$Register, $src1$$Register, src3 & 0x1f, 0, (31-maskbits) & 0x1f); | |
| 8234 } | |
| 8235 %} | |
| 8236 ins_pipe(pipe_class_default); | |
| 8237 %} | |
| 8238 | |
| 8239 // RShiftI + AndI with negpow2-constant + LShiftI | |
| 8240 instruct lShiftI_andI_immInegpow2_rShiftI_imm5(iRegIdst dst, iRegIsrc src1, immInegpow2 src2, uimmI5 src3) %{ | |
| 8241 match(Set dst (LShiftI (AndI (RShiftI src1 src3) src2) src3)); | |
| 8242 predicate(UseRotateAndMaskInstructionsPPC64); | |
| 8243 | |
| 8244 format %{ "RLWINM $dst, lShiftI(AndI(RShiftI($src1, $src3), $src2), $src3)" %} | |
| 8245 size(4); | |
| 8246 ins_encode %{ | |
| 8247 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); // FIXME: assert that rlwinm is equal to addi | |
| 8248 long src2 = $src2$$constant; | |
| 8249 long src3 = $src3$$constant; | |
| 8250 long maskbits = src3 + log2_long((jlong) (julong) (juint) -src2); | |
| 8251 if (maskbits >= 32) { | |
| 8252 __ li($dst$$Register, 0); // addi | |
| 8253 } else { | |
| 8254 __ rlwinm($dst$$Register, $src1$$Register, 0, 0, (31-maskbits) & 0x1f); | |
| 8255 } | |
| 8256 %} | |
| 8257 ins_pipe(pipe_class_default); | |
| 8258 %} | |
| 8259 | |
| 8260 instruct lShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{ | |
| 8261 // no match-rule, false predicate | |
| 8262 effect(DEF dst, USE src1, USE src2); | |
| 8263 predicate(false); | |
| 8264 | |
| 8265 format %{ "SLD $dst, $src1, $src2" %} | |
| 8266 size(4); | |
| 8267 ins_encode %{ | |
| 8268 // TODO: PPC port $archOpcode(ppc64Opcode_sld); | |
| 8269 __ sld($dst$$Register, $src1$$Register, $src2$$Register); | |
| 8270 %} | |
| 8271 ins_pipe(pipe_class_default); | |
| 8272 %} | |
| 8273 | |
| 8274 // Register Shift Left | |
| 8275 instruct lShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{ | |
| 8276 match(Set dst (LShiftL src1 src2)); | |
| 8277 ins_cost(DEFAULT_COST*2); | |
| 8278 expand %{ | |
| 8279 uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %} | |
| 8280 iRegIdst tmpI; | |
| 8281 maskI_reg_imm(tmpI, src2, mask); | |
| 8282 lShiftL_regL_regI(dst, src1, tmpI); | |
| 8283 %} | |
| 8284 %} | |
| 8285 | |
| 8286 // Register Shift Left Immediate | |
| 8287 instruct lshiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{ | |
| 8288 match(Set dst (LShiftL src1 src2)); | |
| 8289 format %{ "SLDI $dst, $src1, ($src2 & 0x3f)" %} | |
| 8290 size(4); | |
| 8291 ins_encode %{ | |
| 8292 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr); | |
| 8293 __ sldi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f); | |
| 8294 %} | |
| 8295 ins_pipe(pipe_class_default); | |
| 8296 %} | |
| 8297 | |
| 8298 // If we shift more than 32 bits, we need not convert I2L. | |
| 8299 instruct lShiftL_regI_immGE32(iRegLdst dst, iRegIsrc src1, uimmI6_ge32 src2) %{ | |
| 8300 match(Set dst (LShiftL (ConvI2L src1) src2)); | |
| 8301 ins_cost(DEFAULT_COST); | |
| 8302 | |
| 8303 size(4); | |
| 8304 format %{ "SLDI $dst, i2l($src1), $src2" %} | |
| 8305 ins_encode %{ | |
| 8306 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr); | |
| 8307 __ sldi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f); | |
| 8308 %} | |
| 8309 ins_pipe(pipe_class_default); | |
| 8310 %} | |
| 8311 | |
| 8312 // Shift a postivie int to the left. | |
| 8313 // Clrlsldi clears the upper 32 bits and shifts. | |
| 8314 instruct scaledPositiveI2L_lShiftL_convI2L_reg_imm6(iRegLdst dst, iRegIsrc src1, uimmI6 src2) %{ | |
| 8315 match(Set dst (LShiftL (ConvI2L src1) src2)); | |
| 8316 predicate(((ConvI2LNode*)(_kids[0]->_leaf))->type()->is_long()->is_positive_int()); | |
| 8317 | |
| 8318 format %{ "SLDI $dst, i2l(positive_int($src1)), $src2" %} | |
| 8319 size(4); | |
| 8320 ins_encode %{ | |
| 8321 // TODO: PPC port $archOpcode(ppc64Opcode_rldic); | |
| 8322 __ clrlsldi($dst$$Register, $src1$$Register, 0x20, $src2$$constant); | |
| 8323 %} | |
| 8324 ins_pipe(pipe_class_default); | |
| 8325 %} | |
| 8326 | |
| 8327 instruct arShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ | |
| 8328 // no match-rule, false predicate | |
| 8329 effect(DEF dst, USE src1, USE src2); | |
| 8330 predicate(false); | |
| 8331 | |
| 8332 format %{ "SRAW $dst, $src1, $src2" %} | |
| 8333 size(4); | |
| 8334 ins_encode %{ | |
| 8335 // TODO: PPC port $archOpcode(ppc64Opcode_sraw); | |
| 8336 __ sraw($dst$$Register, $src1$$Register, $src2$$Register); | |
| 8337 %} | |
| 8338 ins_pipe(pipe_class_default); | |
| 8339 %} | |
| 8340 | |
| 8341 // Register Arithmetic Shift Right | |
| 8342 instruct arShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ | |
| 8343 match(Set dst (RShiftI src1 src2)); | |
| 8344 ins_cost(DEFAULT_COST*2); | |
| 8345 expand %{ | |
| 8346 uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %} | |
| 8347 iRegIdst tmpI; | |
| 8348 maskI_reg_imm(tmpI, src2, mask); | |
| 8349 arShiftI_reg_reg(dst, src1, tmpI); | |
| 8350 %} | |
| 8351 %} | |
| 8352 | |
| 8353 // Register Arithmetic Shift Right Immediate | |
| 8354 instruct arShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{ | |
| 8355 match(Set dst (RShiftI src1 src2)); | |
| 8356 | |
| 8357 format %{ "SRAWI $dst, $src1, ($src2 & 0x1f)" %} | |
| 8358 size(4); | |
| 8359 ins_encode %{ | |
| 8360 // TODO: PPC port $archOpcode(ppc64Opcode_srawi); | |
| 8361 __ srawi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f); | |
| 8362 %} | |
| 8363 ins_pipe(pipe_class_default); | |
| 8364 %} | |
| 8365 | |
| 8366 instruct arShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{ | |
| 8367 // no match-rule, false predicate | |
| 8368 effect(DEF dst, USE src1, USE src2); | |
| 8369 predicate(false); | |
| 8370 | |
| 8371 format %{ "SRAD $dst, $src1, $src2" %} | |
| 8372 size(4); | |
| 8373 ins_encode %{ | |
| 8374 // TODO: PPC port $archOpcode(ppc64Opcode_srad); | |
| 8375 __ srad($dst$$Register, $src1$$Register, $src2$$Register); | |
| 8376 %} | |
| 8377 ins_pipe(pipe_class_default); | |
| 8378 %} | |
| 8379 | |
| 8380 // Register Shift Right Arithmetic Long | |
| 8381 instruct arShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{ | |
| 8382 match(Set dst (RShiftL src1 src2)); | |
| 8383 ins_cost(DEFAULT_COST*2); | |
| 8384 | |
| 8385 expand %{ | |
| 8386 uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %} | |
| 8387 iRegIdst tmpI; | |
| 8388 maskI_reg_imm(tmpI, src2, mask); | |
| 8389 arShiftL_regL_regI(dst, src1, tmpI); | |
| 8390 %} | |
| 8391 %} | |
| 8392 | |
| 8393 // Register Shift Right Immediate | |
| 8394 instruct arShiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{ | |
| 8395 match(Set dst (RShiftL src1 src2)); | |
| 8396 | |
| 8397 format %{ "SRADI $dst, $src1, ($src2 & 0x3f)" %} | |
| 8398 size(4); | |
| 8399 ins_encode %{ | |
| 8400 // TODO: PPC port $archOpcode(ppc64Opcode_sradi); | |
| 8401 __ sradi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f); | |
| 8402 %} | |
| 8403 ins_pipe(pipe_class_default); | |
| 8404 %} | |
| 8405 | |
| 8406 // RShiftL + ConvL2I | |
| 8407 instruct convL2I_arShiftL_regL_immI(iRegIdst dst, iRegLsrc src1, immI src2) %{ | |
| 8408 match(Set dst (ConvL2I (RShiftL src1 src2))); | |
| 8409 | |
| 8410 format %{ "SRADI $dst, $src1, ($src2 & 0x3f) \t// long + l2i" %} | |
| 8411 size(4); | |
| 8412 ins_encode %{ | |
| 8413 // TODO: PPC port $archOpcode(ppc64Opcode_sradi); | |
| 8414 __ sradi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f); | |
| 8415 %} | |
| 8416 ins_pipe(pipe_class_default); | |
| 8417 %} | |
| 8418 | |
| 8419 instruct urShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ | |
| 8420 // no match-rule, false predicate | |
| 8421 effect(DEF dst, USE src1, USE src2); | |
| 8422 predicate(false); | |
| 8423 | |
| 8424 format %{ "SRW $dst, $src1, $src2" %} | |
| 8425 size(4); | |
| 8426 ins_encode %{ | |
| 8427 // TODO: PPC port $archOpcode(ppc64Opcode_srw); | |
| 8428 __ srw($dst$$Register, $src1$$Register, $src2$$Register); | |
| 8429 %} | |
| 8430 ins_pipe(pipe_class_default); | |
| 8431 %} | |
| 8432 | |
| 8433 // Register Shift Right | |
| 8434 instruct urShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ | |
| 8435 match(Set dst (URShiftI src1 src2)); | |
| 8436 ins_cost(DEFAULT_COST*2); | |
| 8437 | |
| 8438 expand %{ | |
| 8439 uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %} | |
| 8440 iRegIdst tmpI; | |
| 8441 maskI_reg_imm(tmpI, src2, mask); | |
| 8442 urShiftI_reg_reg(dst, src1, tmpI); | |
| 8443 %} | |
| 8444 %} | |
| 8445 | |
| 8446 // Register Shift Right Immediate | |
| 8447 instruct urShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{ | |
| 8448 match(Set dst (URShiftI src1 src2)); | |
| 8449 | |
| 8450 format %{ "SRWI $dst, $src1, ($src2 & 0x1f)" %} | |
| 8451 size(4); | |
| 8452 ins_encode %{ | |
| 8453 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); | |
| 8454 __ srwi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f); | |
| 8455 %} | |
| 8456 ins_pipe(pipe_class_default); | |
| 8457 %} | |
| 8458 | |
| 8459 instruct urShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{ | |
| 8460 // no match-rule, false predicate | |
| 8461 effect(DEF dst, USE src1, USE src2); | |
| 8462 predicate(false); | |
| 8463 | |
| 8464 format %{ "SRD $dst, $src1, $src2" %} | |
| 8465 size(4); | |
| 8466 ins_encode %{ | |
| 8467 // TODO: PPC port $archOpcode(ppc64Opcode_srd); | |
| 8468 __ srd($dst$$Register, $src1$$Register, $src2$$Register); | |
| 8469 %} | |
| 8470 ins_pipe(pipe_class_default); | |
| 8471 %} | |
| 8472 | |
| 8473 // Register Shift Right | |
| 8474 instruct urShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{ | |
| 8475 match(Set dst (URShiftL src1 src2)); | |
| 8476 ins_cost(DEFAULT_COST*2); | |
| 8477 | |
| 8478 expand %{ | |
| 8479 uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %} | |
| 8480 iRegIdst tmpI; | |
| 8481 maskI_reg_imm(tmpI, src2, mask); | |
| 8482 urShiftL_regL_regI(dst, src1, tmpI); | |
| 8483 %} | |
| 8484 %} | |
| 8485 | |
| 8486 // Register Shift Right Immediate | |
| 8487 instruct urShiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{ | |
| 8488 match(Set dst (URShiftL src1 src2)); | |
| 8489 | |
| 8490 format %{ "SRDI $dst, $src1, ($src2 & 0x3f)" %} | |
| 8491 size(4); | |
| 8492 ins_encode %{ | |
| 8493 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); | |
| 8494 __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f); | |
| 8495 %} | |
| 8496 ins_pipe(pipe_class_default); | |
| 8497 %} | |
| 8498 | |
| 8499 // URShiftL + ConvL2I. | |
| 8500 instruct convL2I_urShiftL_regL_immI(iRegIdst dst, iRegLsrc src1, immI src2) %{ | |
| 8501 match(Set dst (ConvL2I (URShiftL src1 src2))); | |
| 8502 | |
| 8503 format %{ "SRDI $dst, $src1, ($src2 & 0x3f) \t// long + l2i" %} | |
| 8504 size(4); | |
| 8505 ins_encode %{ | |
| 8506 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); | |
| 8507 __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f); | |
| 8508 %} | |
| 8509 ins_pipe(pipe_class_default); | |
| 8510 %} | |
| 8511 | |
| 8512 // Register Shift Right Immediate with a CastP2X | |
| 8513 instruct shrP_convP2X_reg_imm6(iRegLdst dst, iRegP_N2P src1, uimmI6 src2) %{ | |
| 8514 match(Set dst (URShiftL (CastP2X src1) src2)); | |
| 8515 | |
| 8516 format %{ "SRDI $dst, $src1, $src2 \t// Cast ptr $src1 to long and shift" %} | |
| 8517 size(4); | |
| 8518 ins_encode %{ | |
| 8519 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); | |
| 8520 __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f); | |
| 8521 %} | |
| 8522 ins_pipe(pipe_class_default); | |
| 8523 %} | |
| 8524 | |
| 8525 instruct sxtI_reg(iRegIdst dst, iRegIsrc src) %{ | |
| 8526 match(Set dst (ConvL2I (ConvI2L src))); | |
| 8527 | |
| 8528 format %{ "EXTSW $dst, $src \t// int->int" %} | |
| 8529 size(4); | |
| 8530 ins_encode %{ | |
| 8531 // TODO: PPC port $archOpcode(ppc64Opcode_extsw); | |
| 8532 __ extsw($dst$$Register, $src$$Register); | |
| 8533 %} | |
| 8534 ins_pipe(pipe_class_default); | |
| 8535 %} | |
| 8536 | |
| 8537 //----------Rotate Instructions------------------------------------------------ | |
| 8538 | |
| 8539 // Rotate Left by 8-bit immediate | |
| 8540 instruct rotlI_reg_immi8(iRegIdst dst, iRegIsrc src, immI8 lshift, immI8 rshift) %{ | |
| 8541 match(Set dst (OrI (LShiftI src lshift) (URShiftI src rshift))); | |
| 8542 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); | |
| 8543 | |
| 8544 format %{ "ROTLWI $dst, $src, $lshift" %} | |
| 8545 size(4); | |
| 8546 ins_encode %{ | |
| 8547 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); | |
| 8548 __ rotlwi($dst$$Register, $src$$Register, $lshift$$constant); | |
| 8549 %} | |
| 8550 ins_pipe(pipe_class_default); | |
| 8551 %} | |
| 8552 | |
| 8553 // Rotate Right by 8-bit immediate | |
| 8554 instruct rotrI_reg_immi8(iRegIdst dst, iRegIsrc src, immI8 rshift, immI8 lshift) %{ | |
| 8555 match(Set dst (OrI (URShiftI src rshift) (LShiftI src lshift))); | |
| 8556 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); | |
| 8557 | |
| 8558 format %{ "ROTRWI $dst, $rshift" %} | |
| 8559 size(4); | |
| 8560 ins_encode %{ | |
| 8561 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); | |
| 8562 __ rotrwi($dst$$Register, $src$$Register, $rshift$$constant); | |
| 8563 %} | |
| 8564 ins_pipe(pipe_class_default); | |
| 8565 %} | |
| 8566 | |
| 8567 //----------Floating Point Arithmetic Instructions----------------------------- | |
| 8568 | |
| 8569 // Add float single precision | |
| 8570 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{ | |
| 8571 match(Set dst (AddF src1 src2)); | |
| 8572 | |
| 8573 format %{ "FADDS $dst, $src1, $src2" %} | |
| 8574 size(4); | |
| 8575 ins_encode %{ | |
| 8576 // TODO: PPC port $archOpcode(ppc64Opcode_fadds); | |
| 8577 __ fadds($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); | |
| 8578 %} | |
| 8579 ins_pipe(pipe_class_default); | |
| 8580 %} | |
| 8581 | |
| 8582 // Add float double precision | |
| 8583 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{ | |
| 8584 match(Set dst (AddD src1 src2)); | |
| 8585 | |
| 8586 format %{ "FADD $dst, $src1, $src2" %} | |
| 8587 size(4); | |
| 8588 ins_encode %{ | |
| 8589 // TODO: PPC port $archOpcode(ppc64Opcode_fadd); | |
| 8590 __ fadd($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); | |
| 8591 %} | |
| 8592 ins_pipe(pipe_class_default); | |
| 8593 %} | |
| 8594 | |
| 8595 // Sub float single precision | |
| 8596 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{ | |
| 8597 match(Set dst (SubF src1 src2)); | |
| 8598 | |
| 8599 format %{ "FSUBS $dst, $src1, $src2" %} | |
| 8600 size(4); | |
| 8601 ins_encode %{ | |
| 8602 // TODO: PPC port $archOpcode(ppc64Opcode_fsubs); | |
| 8603 __ fsubs($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); | |
| 8604 %} | |
| 8605 ins_pipe(pipe_class_default); | |
| 8606 %} | |
| 8607 | |
| 8608 // Sub float double precision | |
| 8609 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{ | |
| 8610 match(Set dst (SubD src1 src2)); | |
| 8611 format %{ "FSUB $dst, $src1, $src2" %} | |
| 8612 size(4); | |
| 8613 ins_encode %{ | |
| 8614 // TODO: PPC port $archOpcode(ppc64Opcode_fsub); | |
| 8615 __ fsub($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); | |
| 8616 %} | |
| 8617 ins_pipe(pipe_class_default); | |
| 8618 %} | |
| 8619 | |
| 8620 // Mul float single precision | |
| 8621 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{ | |
| 8622 match(Set dst (MulF src1 src2)); | |
| 8623 format %{ "FMULS $dst, $src1, $src2" %} | |
| 8624 size(4); | |
| 8625 ins_encode %{ | |
| 8626 // TODO: PPC port $archOpcode(ppc64Opcode_fmuls); | |
| 8627 __ fmuls($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); | |
| 8628 %} | |
| 8629 ins_pipe(pipe_class_default); | |
| 8630 %} | |
| 8631 | |
| 8632 // Mul float double precision | |
| 8633 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{ | |
| 8634 match(Set dst (MulD src1 src2)); | |
| 8635 format %{ "FMUL $dst, $src1, $src2" %} | |
| 8636 size(4); | |
| 8637 ins_encode %{ | |
| 8638 // TODO: PPC port $archOpcode(ppc64Opcode_fmul); | |
| 8639 __ fmul($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); | |
| 8640 %} | |
| 8641 ins_pipe(pipe_class_default); | |
| 8642 %} | |
| 8643 | |
| 8644 // Div float single precision | |
| 8645 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{ | |
| 8646 match(Set dst (DivF src1 src2)); | |
| 8647 format %{ "FDIVS $dst, $src1, $src2" %} | |
| 8648 size(4); | |
| 8649 ins_encode %{ | |
| 8650 // TODO: PPC port $archOpcode(ppc64Opcode_fdivs); | |
| 8651 __ fdivs($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); | |
| 8652 %} | |
| 8653 ins_pipe(pipe_class_default); | |
| 8654 %} | |
| 8655 | |
| 8656 // Div float double precision | |
| 8657 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{ | |
| 8658 match(Set dst (DivD src1 src2)); | |
| 8659 format %{ "FDIV $dst, $src1, $src2" %} | |
| 8660 size(4); | |
| 8661 ins_encode %{ | |
| 8662 // TODO: PPC port $archOpcode(ppc64Opcode_fdiv); | |
| 8663 __ fdiv($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); | |
| 8664 %} | |
| 8665 ins_pipe(pipe_class_default); | |
| 8666 %} | |
| 8667 | |
| 8668 // Absolute float single precision | |
| 8669 instruct absF_reg(regF dst, regF src) %{ | |
| 8670 match(Set dst (AbsF src)); | |
| 8671 format %{ "FABS $dst, $src \t// float" %} | |
| 8672 size(4); | |
| 8673 ins_encode %{ | |
| 8674 // TODO: PPC port $archOpcode(ppc64Opcode_fabs); | |
| 8675 __ fabs($dst$$FloatRegister, $src$$FloatRegister); | |
| 8676 %} | |
| 8677 ins_pipe(pipe_class_default); | |
| 8678 %} | |
| 8679 | |
| 8680 // Absolute float double precision | |
| 8681 instruct absD_reg(regD dst, regD src) %{ | |
| 8682 match(Set dst (AbsD src)); | |
| 8683 format %{ "FABS $dst, $src \t// double" %} | |
| 8684 size(4); | |
| 8685 ins_encode %{ | |
| 8686 // TODO: PPC port $archOpcode(ppc64Opcode_fabs); | |
| 8687 __ fabs($dst$$FloatRegister, $src$$FloatRegister); | |
| 8688 %} | |
| 8689 ins_pipe(pipe_class_default); | |
| 8690 %} | |
| 8691 | |
| 8692 instruct negF_reg(regF dst, regF src) %{ | |
| 8693 match(Set dst (NegF src)); | |
| 8694 format %{ "FNEG $dst, $src \t// float" %} | |
| 8695 size(4); | |
| 8696 ins_encode %{ | |
| 8697 // TODO: PPC port $archOpcode(ppc64Opcode_fneg); | |
| 8698 __ fneg($dst$$FloatRegister, $src$$FloatRegister); | |
| 8699 %} | |
| 8700 ins_pipe(pipe_class_default); | |
| 8701 %} | |
| 8702 | |
| 8703 instruct negD_reg(regD dst, regD src) %{ | |
| 8704 match(Set dst (NegD src)); | |
| 8705 format %{ "FNEG $dst, $src \t// double" %} | |
| 8706 size(4); | |
| 8707 ins_encode %{ | |
| 8708 // TODO: PPC port $archOpcode(ppc64Opcode_fneg); | |
| 8709 __ fneg($dst$$FloatRegister, $src$$FloatRegister); | |
| 8710 %} | |
| 8711 ins_pipe(pipe_class_default); | |
| 8712 %} | |
| 8713 | |
| 8714 // AbsF + NegF. | |
| 8715 instruct negF_absF_reg(regF dst, regF src) %{ | |
| 8716 match(Set dst (NegF (AbsF src))); | |
| 8717 format %{ "FNABS $dst, $src \t// float" %} | |
| 8718 size(4); | |
| 8719 ins_encode %{ | |
| 8720 // TODO: PPC port $archOpcode(ppc64Opcode_fnabs); | |
| 8721 __ fnabs($dst$$FloatRegister, $src$$FloatRegister); | |
| 8722 %} | |
| 8723 ins_pipe(pipe_class_default); | |
| 8724 %} | |
| 8725 | |
| 8726 // AbsD + NegD. | |
| 8727 instruct negD_absD_reg(regD dst, regD src) %{ | |
| 8728 match(Set dst (NegD (AbsD src))); | |
| 8729 format %{ "FNABS $dst, $src \t// double" %} | |
| 8730 size(4); | |
| 8731 ins_encode %{ | |
| 8732 // TODO: PPC port $archOpcode(ppc64Opcode_fnabs); | |
| 8733 __ fnabs($dst$$FloatRegister, $src$$FloatRegister); | |
| 8734 %} | |
| 8735 ins_pipe(pipe_class_default); | |
| 8736 %} | |
| 8737 | |
| 8738 // VM_Version::has_sqrt() decides if this node will be used. | |
| 8739 // Sqrt float double precision | |
| 8740 instruct sqrtD_reg(regD dst, regD src) %{ | |
| 8741 match(Set dst (SqrtD src)); | |
| 8742 format %{ "FSQRT $dst, $src" %} | |
| 8743 size(4); | |
| 8744 ins_encode %{ | |
| 8745 // TODO: PPC port $archOpcode(ppc64Opcode_fsqrt); | |
| 8746 __ fsqrt($dst$$FloatRegister, $src$$FloatRegister); | |
| 8747 %} | |
| 8748 ins_pipe(pipe_class_default); | |
| 8749 %} | |
| 8750 | |
| 8751 // Single-precision sqrt. | |
| 8752 instruct sqrtF_reg(regF dst, regF src) %{ | |
| 8753 match(Set dst (ConvD2F (SqrtD (ConvF2D src)))); | |
| 8754 ins_cost(DEFAULT_COST); | |
| 8755 | |
| 8756 format %{ "FSQRTS $dst, $src" %} | |
| 8757 size(4); | |
| 8758 ins_encode %{ | |
| 8759 // TODO: PPC port $archOpcode(ppc64Opcode_fsqrts); | |
| 8760 __ fsqrts($dst$$FloatRegister, $src$$FloatRegister); | |
| 8761 %} | |
| 8762 ins_pipe(pipe_class_default); | |
| 8763 %} | |
| 8764 | |
| 8765 instruct roundDouble_nop(regD dst) %{ | |
| 8766 match(Set dst (RoundDouble dst)); | |
| 8767 ins_cost(0); | |
| 8768 | |
| 8769 format %{ " -- \t// RoundDouble not needed - empty" %} | |
| 8770 size(0); | |
| 8771 // PPC results are already "rounded" (i.e., normal-format IEEE). | |
| 8772 ins_encode( /*empty*/ ); | |
| 8773 ins_pipe(pipe_class_default); | |
| 8774 %} | |
| 8775 | |
| 8776 instruct roundFloat_nop(regF dst) %{ | |
| 8777 match(Set dst (RoundFloat dst)); | |
| 8778 ins_cost(0); | |
| 8779 | |
| 8780 format %{ " -- \t// RoundFloat not needed - empty" %} | |
| 8781 size(0); | |
| 8782 // PPC results are already "rounded" (i.e., normal-format IEEE). | |
| 8783 ins_encode( /*empty*/ ); | |
| 8784 ins_pipe(pipe_class_default); | |
| 8785 %} | |
| 8786 | |
| 8787 //----------Logical Instructions----------------------------------------------- | |
| 8788 | |
| 8789 // And Instructions | |
| 8790 | |
| 8791 // Register And | |
| 8792 instruct andI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ | |
| 8793 match(Set dst (AndI src1 src2)); | |
| 8794 format %{ "AND $dst, $src1, $src2" %} | |
| 8795 size(4); | |
| 8796 ins_encode %{ | |
| 8797 // TODO: PPC port $archOpcode(ppc64Opcode_and); | |
| 8798 __ andr($dst$$Register, $src1$$Register, $src2$$Register); | |
| 8799 %} | |
| 8800 ins_pipe(pipe_class_default); | |
| 8801 %} | |
| 8802 | |
| 8803 // Immediate And | |
| 8804 instruct andI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2, flagsRegCR0 cr0) %{ | |
| 8805 match(Set dst (AndI src1 src2)); | |
| 8806 effect(KILL cr0); | |
| 8807 | |
| 8808 format %{ "ANDI $dst, $src1, $src2" %} | |
| 8809 size(4); | |
| 8810 ins_encode %{ | |
| 8811 // TODO: PPC port $archOpcode(ppc64Opcode_andi_); | |
| 8812 // FIXME: avoid andi_ ? | |
| 8813 __ andi_($dst$$Register, $src1$$Register, $src2$$constant); | |
| 8814 %} | |
| 8815 ins_pipe(pipe_class_default); | |
| 8816 %} | |
| 8817 | |
| 8818 // Immediate And where the immediate is a negative power of 2. | |
| 8819 instruct andI_reg_immInegpow2(iRegIdst dst, iRegIsrc src1, immInegpow2 src2) %{ | |
| 8820 match(Set dst (AndI src1 src2)); | |
| 8821 format %{ "ANDWI $dst, $src1, $src2" %} | |
| 8822 size(4); | |
| 8823 ins_encode %{ | |
| 8824 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr); | |
| 8825 __ clrrdi($dst$$Register, $src1$$Register, log2_long((jlong)(julong)(juint)-($src2$$constant))); | |
| 8826 %} | |
| 8827 ins_pipe(pipe_class_default); | |
| 8828 %} | |
| 8829 | |
| 8830 instruct andI_reg_immIpow2minus1(iRegIdst dst, iRegIsrc src1, immIpow2minus1 src2) %{ | |
| 8831 match(Set dst (AndI src1 src2)); | |
| 8832 format %{ "ANDWI $dst, $src1, $src2" %} | |
| 8833 size(4); | |
| 8834 ins_encode %{ | |
| 8835 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); | |
| 8836 __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1))); | |
| 8837 %} | |
| 8838 ins_pipe(pipe_class_default); | |
| 8839 %} | |
| 8840 | |
| 8841 instruct andI_reg_immIpowerOf2(iRegIdst dst, iRegIsrc src1, immIpowerOf2 src2) %{ | |
| 8842 match(Set dst (AndI src1 src2)); | |
| 8843 predicate(UseRotateAndMaskInstructionsPPC64); | |
| 8844 format %{ "ANDWI $dst, $src1, $src2" %} | |
| 8845 size(4); | |
| 8846 ins_encode %{ | |
| 8847 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); | |
| 8848 __ rlwinm($dst$$Register, $src1$$Register, 0, | |
| 8849 (31-log2_long((jlong) $src2$$constant)) & 0x1f, (31-log2_long((jlong) $src2$$constant)) & 0x1f); | |
| 8850 %} | |
| 8851 ins_pipe(pipe_class_default); | |
| 8852 %} | |
| 8853 | |
| 8854 // Register And Long | |
| 8855 instruct andL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ | |
| 8856 match(Set dst (AndL src1 src2)); | |
| 8857 ins_cost(DEFAULT_COST); | |
| 8858 | |
| 8859 format %{ "AND $dst, $src1, $src2 \t// long" %} | |
| 8860 size(4); | |
| 8861 ins_encode %{ | |
| 8862 // TODO: PPC port $archOpcode(ppc64Opcode_and); | |
| 8863 __ andr($dst$$Register, $src1$$Register, $src2$$Register); | |
| 8864 %} | |
| 8865 ins_pipe(pipe_class_default); | |
| 8866 %} | |
| 8867 | |
| 8868 // Immediate And long | |
| 8869 instruct andL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 src2, flagsRegCR0 cr0) %{ | |
| 8870 match(Set dst (AndL src1 src2)); | |
| 8871 effect(KILL cr0); | |
| 8872 ins_cost(DEFAULT_COST); | |
| 8873 | |
| 8874 format %{ "ANDI $dst, $src1, $src2 \t// long" %} | |
| 8875 size(4); | |
| 8876 ins_encode %{ | |
| 8877 // TODO: PPC port $archOpcode(ppc64Opcode_andi_); | |
| 8878 // FIXME: avoid andi_ ? | |
| 8879 __ andi_($dst$$Register, $src1$$Register, $src2$$constant); | |
| 8880 %} | |
| 8881 ins_pipe(pipe_class_default); | |
| 8882 %} | |
| 8883 | |
| 8884 // Immediate And Long where the immediate is a negative power of 2. | |
| 8885 instruct andL_reg_immLnegpow2(iRegLdst dst, iRegLsrc src1, immLnegpow2 src2) %{ | |
| 8886 match(Set dst (AndL src1 src2)); | |
| 8887 format %{ "ANDDI $dst, $src1, $src2" %} | |
| 8888 size(4); | |
| 8889 ins_encode %{ | |
| 8890 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr); | |
| 8891 __ clrrdi($dst$$Register, $src1$$Register, log2_long((jlong)-$src2$$constant)); | |
| 8892 %} | |
| 8893 ins_pipe(pipe_class_default); | |
| 8894 %} | |
| 8895 | |
| 8896 instruct andL_reg_immLpow2minus1(iRegLdst dst, iRegLsrc src1, immLpow2minus1 src2) %{ | |
| 8897 match(Set dst (AndL src1 src2)); | |
| 8898 format %{ "ANDDI $dst, $src1, $src2" %} | |
| 8899 size(4); | |
| 8900 ins_encode %{ | |
| 8901 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); | |
| 8902 __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1))); | |
| 8903 %} | |
| 8904 ins_pipe(pipe_class_default); | |
| 8905 %} | |
| 8906 | |
| 8907 // AndL + ConvL2I. | |
| 8908 instruct convL2I_andL_reg_immLpow2minus1(iRegIdst dst, iRegLsrc src1, immLpow2minus1 src2) %{ | |
| 8909 match(Set dst (ConvL2I (AndL src1 src2))); | |
| 8910 ins_cost(DEFAULT_COST); | |
| 8911 | |
| 8912 format %{ "ANDDI $dst, $src1, $src2 \t// long + l2i" %} | |
| 8913 size(4); | |
| 8914 ins_encode %{ | |
| 8915 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); | |
| 8916 __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1))); | |
| 8917 %} | |
| 8918 ins_pipe(pipe_class_default); | |
| 8919 %} | |
| 8920 | |
| 8921 // Or Instructions | |
| 8922 | |
| 8923 // Register Or | |
| 8924 instruct orI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ | |
| 8925 match(Set dst (OrI src1 src2)); | |
| 8926 format %{ "OR $dst, $src1, $src2" %} | |
| 8927 size(4); | |
| 8928 ins_encode %{ | |
| 8929 // TODO: PPC port $archOpcode(ppc64Opcode_or); | |
| 8930 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register); | |
| 8931 %} | |
| 8932 ins_pipe(pipe_class_default); | |
| 8933 %} | |
| 8934 | |
| 8935 // Expand does not work with above instruct. (??) | |
| 8936 instruct orI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ | |
| 8937 // no match-rule | |
| 8938 effect(DEF dst, USE src1, USE src2); | |
| 8939 format %{ "OR $dst, $src1, $src2" %} | |
| 8940 size(4); | |
| 8941 ins_encode %{ | |
| 8942 // TODO: PPC port $archOpcode(ppc64Opcode_or); | |
| 8943 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register); | |
| 8944 %} | |
| 8945 ins_pipe(pipe_class_default); | |
| 8946 %} | |
| 8947 | |
| 8948 instruct tree_orI_orI_orI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{ | |
| 8949 match(Set dst (OrI (OrI (OrI src1 src2) src3) src4)); | |
| 8950 ins_cost(DEFAULT_COST*3); | |
| 8951 | |
| 8952 expand %{ | |
| 8953 // FIXME: we should do this in the ideal world. | |
| 8954 iRegIdst tmp1; | |
| 8955 iRegIdst tmp2; | |
| 8956 orI_reg_reg(tmp1, src1, src2); | |
| 8957 orI_reg_reg_2(tmp2, src3, src4); // Adlc complains about orI_reg_reg. | |
| 8958 orI_reg_reg(dst, tmp1, tmp2); | |
| 8959 %} | |
| 8960 %} | |
| 8961 | |
| 8962 // Immediate Or | |
| 8963 instruct orI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2) %{ | |
| 8964 match(Set dst (OrI src1 src2)); | |
| 8965 format %{ "ORI $dst, $src1, $src2" %} | |
| 8966 size(4); | |
| 8967 ins_encode %{ | |
| 8968 // TODO: PPC port $archOpcode(ppc64Opcode_ori); | |
| 8969 __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF); | |
| 8970 %} | |
| 8971 ins_pipe(pipe_class_default); | |
| 8972 %} | |
| 8973 | |
| 8974 // Register Or Long | |
| 8975 instruct orL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ | |
| 8976 match(Set dst (OrL src1 src2)); | |
| 8977 ins_cost(DEFAULT_COST); | |
| 8978 | |
| 8979 size(4); | |
| 8980 format %{ "OR $dst, $src1, $src2 \t// long" %} | |
| 8981 ins_encode %{ | |
| 8982 // TODO: PPC port $archOpcode(ppc64Opcode_or); | |
| 8983 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register); | |
| 8984 %} | |
| 8985 ins_pipe(pipe_class_default); | |
| 8986 %} | |
| 8987 | |
| 8988 // OrL + ConvL2I. | |
| 8989 instruct orI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{ | |
| 8990 match(Set dst (ConvL2I (OrL src1 src2))); | |
| 8991 ins_cost(DEFAULT_COST); | |
| 8992 | |
| 8993 format %{ "OR $dst, $src1, $src2 \t// long + l2i" %} | |
| 8994 size(4); | |
| 8995 ins_encode %{ | |
| 8996 // TODO: PPC port $archOpcode(ppc64Opcode_or); | |
| 8997 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register); | |
| 8998 %} | |
| 8999 ins_pipe(pipe_class_default); | |
| 9000 %} | |
| 9001 | |
| 9002 // Immediate Or long | |
| 9003 instruct orL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 con) %{ | |
| 9004 match(Set dst (OrL src1 con)); | |
| 9005 ins_cost(DEFAULT_COST); | |
| 9006 | |
| 9007 format %{ "ORI $dst, $src1, $con \t// long" %} | |
| 9008 size(4); | |
| 9009 ins_encode %{ | |
| 9010 // TODO: PPC port $archOpcode(ppc64Opcode_ori); | |
| 9011 __ ori($dst$$Register, $src1$$Register, ($con$$constant) & 0xFFFF); | |
| 9012 %} | |
| 9013 ins_pipe(pipe_class_default); | |
| 9014 %} | |
| 9015 | |
| 9016 // Xor Instructions | |
| 9017 | |
| 9018 // Register Xor | |
| 9019 instruct xorI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ | |
| 9020 match(Set dst (XorI src1 src2)); | |
| 9021 format %{ "XOR $dst, $src1, $src2" %} | |
| 9022 size(4); | |
| 9023 ins_encode %{ | |
| 9024 // TODO: PPC port $archOpcode(ppc64Opcode_xor); | |
| 9025 __ xorr($dst$$Register, $src1$$Register, $src2$$Register); | |
| 9026 %} | |
| 9027 ins_pipe(pipe_class_default); | |
| 9028 %} | |
| 9029 | |
| 9030 // Expand does not work with above instruct. (??) | |
| 9031 instruct xorI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ | |
| 9032 // no match-rule | |
| 9033 effect(DEF dst, USE src1, USE src2); | |
| 9034 format %{ "XOR $dst, $src1, $src2" %} | |
| 9035 size(4); | |
| 9036 ins_encode %{ | |
| 9037 // TODO: PPC port $archOpcode(ppc64Opcode_xor); | |
| 9038 __ xorr($dst$$Register, $src1$$Register, $src2$$Register); | |
| 9039 %} | |
| 9040 ins_pipe(pipe_class_default); | |
| 9041 %} | |
| 9042 | |
| 9043 instruct tree_xorI_xorI_xorI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{ | |
| 9044 match(Set dst (XorI (XorI (XorI src1 src2) src3) src4)); | |
| 9045 ins_cost(DEFAULT_COST*3); | |
| 9046 | |
| 9047 expand %{ | |
| 9048 // FIXME: we should do this in the ideal world. | |
| 9049 iRegIdst tmp1; | |
| 9050 iRegIdst tmp2; | |
| 9051 xorI_reg_reg(tmp1, src1, src2); | |
| 9052 xorI_reg_reg_2(tmp2, src3, src4); // Adlc complains about xorI_reg_reg. | |
| 9053 xorI_reg_reg(dst, tmp1, tmp2); | |
| 9054 %} | |
| 9055 %} | |
| 9056 | |
| 9057 // Immediate Xor | |
| 9058 instruct xorI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2) %{ | |
| 9059 match(Set dst (XorI src1 src2)); | |
| 9060 format %{ "XORI $dst, $src1, $src2" %} | |
| 9061 size(4); | |
| 9062 ins_encode %{ | |
| 9063 // TODO: PPC port $archOpcode(ppc64Opcode_xori); | |
| 9064 __ xori($dst$$Register, $src1$$Register, $src2$$constant); | |
| 9065 %} | |
| 9066 ins_pipe(pipe_class_default); | |
| 9067 %} | |
| 9068 | |
| 9069 // Register Xor Long | |
| 9070 instruct xorL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ | |
| 9071 match(Set dst (XorL src1 src2)); | |
| 9072 ins_cost(DEFAULT_COST); | |
| 9073 | |
| 9074 format %{ "XOR $dst, $src1, $src2 \t// long" %} | |
| 9075 size(4); | |
| 9076 ins_encode %{ | |
| 9077 // TODO: PPC port $archOpcode(ppc64Opcode_xor); | |
| 9078 __ xorr($dst$$Register, $src1$$Register, $src2$$Register); | |
| 9079 %} | |
| 9080 ins_pipe(pipe_class_default); | |
| 9081 %} | |
| 9082 | |
| 9083 // XorL + ConvL2I. | |
| 9084 instruct xorI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{ | |
| 9085 match(Set dst (ConvL2I (XorL src1 src2))); | |
| 9086 ins_cost(DEFAULT_COST); | |
| 9087 | |
| 9088 format %{ "XOR $dst, $src1, $src2 \t// long + l2i" %} | |
| 9089 size(4); | |
| 9090 ins_encode %{ | |
| 9091 // TODO: PPC port $archOpcode(ppc64Opcode_xor); | |
| 9092 __ xorr($dst$$Register, $src1$$Register, $src2$$Register); | |
| 9093 %} | |
| 9094 ins_pipe(pipe_class_default); | |
| 9095 %} | |
| 9096 | |
| 9097 // Immediate Xor Long | |
| 9098 instruct xorL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 src2) %{ | |
| 9099 match(Set dst (XorL src1 src2)); | |
| 9100 ins_cost(DEFAULT_COST); | |
| 9101 | |
| 9102 format %{ "XORI $dst, $src1, $src2 \t// long" %} | |
| 9103 size(4); | |
| 9104 ins_encode %{ | |
| 9105 // TODO: PPC port $archOpcode(ppc64Opcode_xori); | |
| 9106 __ xori($dst$$Register, $src1$$Register, $src2$$constant); | |
| 9107 %} | |
| 9108 ins_pipe(pipe_class_default); | |
| 9109 %} | |
| 9110 | |
| 9111 instruct notI_reg(iRegIdst dst, iRegIsrc src1, immI_minus1 src2) %{ | |
| 9112 match(Set dst (XorI src1 src2)); | |
| 9113 ins_cost(DEFAULT_COST); | |
| 9114 | |
| 9115 format %{ "NOT $dst, $src1 ($src2)" %} | |
| 9116 size(4); | |
| 9117 ins_encode %{ | |
| 9118 // TODO: PPC port $archOpcode(ppc64Opcode_nor); | |
| 9119 __ nor($dst$$Register, $src1$$Register, $src1$$Register); | |
| 9120 %} | |
| 9121 ins_pipe(pipe_class_default); | |
| 9122 %} | |
| 9123 | |
| 9124 instruct notL_reg(iRegLdst dst, iRegLsrc src1, immL_minus1 src2) %{ | |
| 9125 match(Set dst (XorL src1 src2)); | |
| 9126 ins_cost(DEFAULT_COST); | |
| 9127 | |
| 9128 format %{ "NOT $dst, $src1 ($src2) \t// long" %} | |
| 9129 size(4); | |
| 9130 ins_encode %{ | |
| 9131 // TODO: PPC port $archOpcode(ppc64Opcode_nor); | |
| 9132 __ nor($dst$$Register, $src1$$Register, $src1$$Register); | |
| 9133 %} | |
| 9134 ins_pipe(pipe_class_default); | |
| 9135 %} | |
| 9136 | |
| 9137 // And-complement | |
| 9138 instruct andcI_reg_reg(iRegIdst dst, iRegIsrc src1, immI_minus1 src2, iRegIsrc src3) %{ | |
| 9139 match(Set dst (AndI (XorI src1 src2) src3)); | |
| 9140 ins_cost(DEFAULT_COST); | |
| 9141 | |
| 9142 format %{ "ANDW $dst, xori($src1, $src2), $src3" %} | |
| 9143 size(4); | |
| 9144 ins_encode( enc_andc(dst, src3, src1) ); | |
| 9145 ins_pipe(pipe_class_default); | |
| 9146 %} | |
| 9147 | |
| 9148 // And-complement | |
| 9149 instruct andcL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ | |
| 9150 // no match-rule, false predicate | |
| 9151 effect(DEF dst, USE src1, USE src2); | |
| 9152 predicate(false); | |
| 9153 | |
| 9154 format %{ "ANDC $dst, $src1, $src2" %} | |
| 9155 size(4); | |
| 9156 ins_encode %{ | |
| 9157 // TODO: PPC port $archOpcode(ppc64Opcode_andc); | |
| 9158 __ andc($dst$$Register, $src1$$Register, $src2$$Register); | |
| 9159 %} | |
| 9160 ins_pipe(pipe_class_default); | |
| 9161 %} | |
| 9162 | |
| 9163 //----------Moves between int/long and float/double---------------------------- | |
| 9164 // | |
| 9165 // The following rules move values from int/long registers/stack-locations | |
| 9166 // to float/double registers/stack-locations and vice versa, without doing any | |
| 9167 // conversions. These rules are used to implement the bit-conversion methods | |
| 9168 // of java.lang.Float etc., e.g. | |
| 9169 // int floatToIntBits(float value) | |
| 9170 // float intBitsToFloat(int bits) | |
| 9171 // | |
| 9172 // Notes on the implementation on ppc64: | |
| 9173 // We only provide rules which move between a register and a stack-location, | |
| 9174 // because we always have to go through memory when moving between a float | |
| 9175 // register and an integer register. | |
| 9176 | |
| 9177 //---------- Chain stack slots between similar types -------- | |
| 9178 | |
| 9179 // These are needed so that the rules below can match. | |
| 9180 | |
| 9181 // Load integer from stack slot | |
| 9182 instruct stkI_to_regI(iRegIdst dst, stackSlotI src) %{ | |
| 9183 match(Set dst src); | |
| 9184 ins_cost(MEMORY_REF_COST); | |
| 9185 | |
| 9186 format %{ "LWZ $dst, $src" %} | |
| 9187 size(4); | |
| 9188 ins_encode( enc_lwz(dst, src) ); | |
| 9189 ins_pipe(pipe_class_memory); | |
| 9190 %} | |
| 9191 | |
| 9192 // Store integer to stack slot | |
| 9193 instruct regI_to_stkI(stackSlotI dst, iRegIsrc src) %{ | |
| 9194 match(Set dst src); | |
| 9195 ins_cost(MEMORY_REF_COST); | |
| 9196 | |
| 9197 format %{ "STW $src, $dst \t// stk" %} | |
| 9198 size(4); | |
| 9199 ins_encode( enc_stw(src, dst) ); // rs=rt | |
| 9200 ins_pipe(pipe_class_memory); | |
| 9201 %} | |
| 9202 | |
| 9203 // Load long from stack slot | |
| 9204 instruct stkL_to_regL(iRegLdst dst, stackSlotL src) %{ | |
| 9205 match(Set dst src); | |
| 9206 ins_cost(MEMORY_REF_COST); | |
| 9207 | |
| 9208 format %{ "LD $dst, $src \t// long" %} | |
| 9209 size(4); | |
| 9210 ins_encode( enc_ld(dst, src) ); | |
| 9211 ins_pipe(pipe_class_memory); | |
| 9212 %} | |
| 9213 | |
| 9214 // Store long to stack slot | |
| 9215 instruct regL_to_stkL(stackSlotL dst, iRegLsrc src) %{ | |
| 9216 match(Set dst src); | |
| 9217 ins_cost(MEMORY_REF_COST); | |
| 9218 | |
| 9219 format %{ "STD $src, $dst \t// long" %} | |
| 9220 size(4); | |
| 9221 ins_encode( enc_std(src, dst) ); // rs=rt | |
| 9222 ins_pipe(pipe_class_memory); | |
| 9223 %} | |
| 9224 | |
| 9225 //----------Moves between int and float | |
| 9226 | |
| 9227 // Move float value from float stack-location to integer register. | |
| 9228 instruct moveF2I_stack_reg(iRegIdst dst, stackSlotF src) %{ | |
| 9229 match(Set dst (MoveF2I src)); | |
| 9230 ins_cost(MEMORY_REF_COST); | |
| 9231 | |
| 9232 format %{ "LWZ $dst, $src \t// MoveF2I" %} | |
| 9233 size(4); | |
| 9234 ins_encode( enc_lwz(dst, src) ); | |
| 9235 ins_pipe(pipe_class_memory); | |
| 9236 %} | |
| 9237 | |
| 9238 // Move float value from float register to integer stack-location. | |
| 9239 instruct moveF2I_reg_stack(stackSlotI dst, regF src) %{ | |
| 9240 match(Set dst (MoveF2I src)); | |
| 9241 ins_cost(MEMORY_REF_COST); | |
| 9242 | |
| 9243 format %{ "STFS $src, $dst \t// MoveF2I" %} | |
| 9244 size(4); | |
| 9245 ins_encode( enc_stfs(src, dst) ); | |
| 9246 ins_pipe(pipe_class_memory); | |
| 9247 %} | |
| 9248 | |
| 9249 // Move integer value from integer stack-location to float register. | |
| 9250 instruct moveI2F_stack_reg(regF dst, stackSlotI src) %{ | |
| 9251 match(Set dst (MoveI2F src)); | |
| 9252 ins_cost(MEMORY_REF_COST); | |
| 9253 | |
| 9254 format %{ "LFS $dst, $src \t// MoveI2F" %} | |
| 9255 size(4); | |
| 9256 ins_encode %{ | |
| 9257 // TODO: PPC port $archOpcode(ppc64Opcode_lfs); | |
| 9258 int Idisp = $src$$disp + frame_slots_bias($src$$base, ra_); | |
| 9259 __ lfs($dst$$FloatRegister, Idisp, $src$$base$$Register); | |
| 9260 %} | |
| 9261 ins_pipe(pipe_class_memory); | |
| 9262 %} | |
| 9263 | |
| 9264 // Move integer value from integer register to float stack-location. | |
| 9265 instruct moveI2F_reg_stack(stackSlotF dst, iRegIsrc src) %{ | |
| 9266 match(Set dst (MoveI2F src)); | |
| 9267 ins_cost(MEMORY_REF_COST); | |
| 9268 | |
| 9269 format %{ "STW $src, $dst \t// MoveI2F" %} | |
| 9270 size(4); | |
| 9271 ins_encode( enc_stw(src, dst) ); | |
| 9272 ins_pipe(pipe_class_memory); | |
| 9273 %} | |
| 9274 | |
| 9275 //----------Moves between long and float | |
| 9276 | |
| 9277 instruct moveF2L_reg_stack(stackSlotL dst, regF src) %{ | |
| 9278 // no match-rule, false predicate | |
| 9279 effect(DEF dst, USE src); | |
| 9280 predicate(false); | |
| 9281 | |
| 9282 format %{ "storeD $src, $dst \t// STACK" %} | |
| 9283 size(4); | |
| 9284 ins_encode( enc_stfd(src, dst) ); | |
| 9285 ins_pipe(pipe_class_default); | |
| 9286 %} | |
| 9287 | |
| 9288 //----------Moves between long and double | |
| 9289 | |
| 9290 // Move double value from double stack-location to long register. | |
| 9291 instruct moveD2L_stack_reg(iRegLdst dst, stackSlotD src) %{ | |
| 9292 match(Set dst (MoveD2L src)); | |
| 9293 ins_cost(MEMORY_REF_COST); | |
| 9294 size(4); | |
| 9295 format %{ "LD $dst, $src \t// MoveD2L" %} | |
| 9296 ins_encode( enc_ld(dst, src) ); | |
| 9297 ins_pipe(pipe_class_memory); | |
| 9298 %} | |
| 9299 | |
| 9300 // Move double value from double register to long stack-location. | |
| 9301 instruct moveD2L_reg_stack(stackSlotL dst, regD src) %{ | |
| 9302 match(Set dst (MoveD2L src)); | |
| 9303 effect(DEF dst, USE src); | |
| 9304 ins_cost(MEMORY_REF_COST); | |
| 9305 | |
| 9306 format %{ "STFD $src, $dst \t// MoveD2L" %} | |
| 9307 size(4); | |
| 9308 ins_encode( enc_stfd(src, dst) ); | |
| 9309 ins_pipe(pipe_class_memory); | |
| 9310 %} | |
| 9311 | |
| 9312 // Move long value from long stack-location to double register. | |
| 9313 instruct moveL2D_stack_reg(regD dst, stackSlotL src) %{ | |
| 9314 match(Set dst (MoveL2D src)); | |
| 9315 ins_cost(MEMORY_REF_COST); | |
| 9316 | |
| 9317 format %{ "LFD $dst, $src \t// MoveL2D" %} | |
| 9318 size(4); | |
| 9319 ins_encode( enc_lfd(dst, src) ); | |
| 9320 ins_pipe(pipe_class_memory); | |
| 9321 %} | |
| 9322 | |
| 9323 // Move long value from long register to double stack-location. | |
| 9324 instruct moveL2D_reg_stack(stackSlotD dst, iRegLsrc src) %{ | |
| 9325 match(Set dst (MoveL2D src)); | |
| 9326 ins_cost(MEMORY_REF_COST); | |
| 9327 | |
| 9328 format %{ "STD $src, $dst \t// MoveL2D" %} | |
| 9329 size(4); | |
| 9330 ins_encode( enc_std(src, dst) ); | |
| 9331 ins_pipe(pipe_class_memory); | |
| 9332 %} | |
| 9333 | |
| 9334 //----------Register Move Instructions----------------------------------------- | |
| 9335 | |
| 9336 // Replicate for Superword | |
| 9337 | |
| 9338 instruct moveReg(iRegLdst dst, iRegIsrc src) %{ | |
| 9339 predicate(false); | |
| 9340 effect(DEF dst, USE src); | |
| 9341 | |
| 9342 format %{ "MR $dst, $src \t// replicate " %} | |
| 9343 // variable size, 0 or 4. | |
| 9344 ins_encode %{ | |
| 9345 // TODO: PPC port $archOpcode(ppc64Opcode_or); | |
| 9346 __ mr_if_needed($dst$$Register, $src$$Register); | |
| 9347 %} | |
| 9348 ins_pipe(pipe_class_default); | |
| 9349 %} | |
| 9350 | |
| 9351 //----------Cast instructions (Java-level type cast)--------------------------- | |
| 9352 | |
| 9353 // Cast Long to Pointer for unsafe natives. | |
| 9354 instruct castX2P(iRegPdst dst, iRegLsrc src) %{ | |
| 9355 match(Set dst (CastX2P src)); | |
| 9356 | |
| 9357 format %{ "MR $dst, $src \t// Long->Ptr" %} | |
| 9358 // variable size, 0 or 4. | |
| 9359 ins_encode %{ | |
| 9360 // TODO: PPC port $archOpcode(ppc64Opcode_or); | |
| 9361 __ mr_if_needed($dst$$Register, $src$$Register); | |
| 9362 %} | |
| 9363 ins_pipe(pipe_class_default); | |
| 9364 %} | |
| 9365 | |
| 9366 // Cast Pointer to Long for unsafe natives. | |
| 9367 instruct castP2X(iRegLdst dst, iRegP_N2P src) %{ | |
| 9368 match(Set dst (CastP2X src)); | |
| 9369 | |
| 9370 format %{ "MR $dst, $src \t// Ptr->Long" %} | |
| 9371 // variable size, 0 or 4. | |
| 9372 ins_encode %{ | |
| 9373 // TODO: PPC port $archOpcode(ppc64Opcode_or); | |
| 9374 __ mr_if_needed($dst$$Register, $src$$Register); | |
| 9375 %} | |
| 9376 ins_pipe(pipe_class_default); | |
| 9377 %} | |
| 9378 | |
| 9379 instruct castPP(iRegPdst dst) %{ | |
| 9380 match(Set dst (CastPP dst)); | |
| 9381 format %{ " -- \t// castPP of $dst" %} | |
| 9382 size(0); | |
| 9383 ins_encode( /*empty*/ ); | |
| 9384 ins_pipe(pipe_class_default); | |
| 9385 %} | |
| 9386 | |
| 9387 instruct castII(iRegIdst dst) %{ | |
| 9388 match(Set dst (CastII dst)); | |
| 9389 format %{ " -- \t// castII of $dst" %} | |
| 9390 size(0); | |
| 9391 ins_encode( /*empty*/ ); | |
| 9392 ins_pipe(pipe_class_default); | |
| 9393 %} | |
| 9394 | |
| 9395 instruct checkCastPP(iRegPdst dst) %{ | |
| 9396 match(Set dst (CheckCastPP dst)); | |
| 9397 format %{ " -- \t// checkcastPP of $dst" %} | |
| 9398 size(0); | |
| 9399 ins_encode( /*empty*/ ); | |
| 9400 ins_pipe(pipe_class_default); | |
| 9401 %} | |
| 9402 | |
| 9403 //----------Convert instructions----------------------------------------------- | |
| 9404 | |
| 9405 // Convert to boolean. | |
| 9406 | |
| 9407 // int_to_bool(src) : { 1 if src != 0 | |
| 9408 // { 0 else | |
| 9409 // | |
| 9410 // strategy: | |
| 9411 // 1) Count leading zeros of 32 bit-value src, | |
| 9412 // this returns 32 (0b10.0000) iff src == 0 and <32 otherwise. | |
| 9413 // 2) Shift 5 bits to the right, result is 0b1 iff src == 0, 0b0 otherwise. | |
| 9414 // 3) Xori the result to get 0b1 if src != 0 and 0b0 if src == 0. | |
| 9415 | |
| 9416 // convI2Bool | |
| 9417 instruct convI2Bool_reg__cntlz_Ex(iRegIdst dst, iRegIsrc src) %{ | |
| 9418 match(Set dst (Conv2B src)); | |
| 9419 predicate(UseCountLeadingZerosInstructionsPPC64); | |
| 9420 ins_cost(DEFAULT_COST); | |
| 9421 | |
| 9422 expand %{ | |
| 9423 immI shiftAmount %{ 0x5 %} | |
| 9424 uimmI16 mask %{ 0x1 %} | |
| 9425 iRegIdst tmp1; | |
| 9426 iRegIdst tmp2; | |
| 9427 countLeadingZerosI(tmp1, src); | |
| 9428 urShiftI_reg_imm(tmp2, tmp1, shiftAmount); | |
| 9429 xorI_reg_uimm16(dst, tmp2, mask); | |
| 9430 %} | |
| 9431 %} | |
| 9432 | |
| 9433 instruct convI2Bool_reg__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx) %{ | |
| 9434 match(Set dst (Conv2B src)); | |
| 9435 effect(TEMP crx); | |
| 9436 predicate(!UseCountLeadingZerosInstructionsPPC64); | |
| 9437 ins_cost(DEFAULT_COST); | |
| 9438 | |
| 9439 format %{ "CMPWI $crx, $src, #0 \t// convI2B" | |
| 9440 "LI $dst, #0\n\t" | |
| 9441 "BEQ $crx, done\n\t" | |
| 9442 "LI $dst, #1\n" | |
| 9443 "done:" %} | |
| 9444 size(16); | |
| 9445 ins_encode( enc_convI2B_regI__cmove(dst, src, crx, 0x0, 0x1) ); | |
| 9446 ins_pipe(pipe_class_compare); | |
| 9447 %} | |
| 9448 | |
| 9449 // ConvI2B + XorI | |
| 9450 instruct xorI_convI2Bool_reg_immIvalue1__cntlz_Ex(iRegIdst dst, iRegIsrc src, immI_1 mask) %{ | |
| 9451 match(Set dst (XorI (Conv2B src) mask)); | |
| 9452 predicate(UseCountLeadingZerosInstructionsPPC64); | |
| 9453 ins_cost(DEFAULT_COST); | |
| 9454 | |
| 9455 expand %{ | |
| 9456 immI shiftAmount %{ 0x5 %} | |
| 9457 iRegIdst tmp1; | |
| 9458 countLeadingZerosI(tmp1, src); | |
| 9459 urShiftI_reg_imm(dst, tmp1, shiftAmount); | |
| 9460 %} | |
| 9461 %} | |
| 9462 | |
| 9463 instruct xorI_convI2Bool_reg_immIvalue1__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx, immI_1 mask) %{ | |
| 9464 match(Set dst (XorI (Conv2B src) mask)); | |
| 9465 effect(TEMP crx); | |
| 9466 predicate(!UseCountLeadingZerosInstructionsPPC64); | |
| 9467 ins_cost(DEFAULT_COST); | |
| 9468 | |
| 9469 format %{ "CMPWI $crx, $src, #0 \t// Xor(convI2B($src), $mask)" | |
| 9470 "LI $dst, #1\n\t" | |
| 9471 "BEQ $crx, done\n\t" | |
| 9472 "LI $dst, #0\n" | |
| 9473 "done:" %} | |
| 9474 size(16); | |
| 9475 ins_encode( enc_convI2B_regI__cmove(dst, src, crx, 0x1, 0x0) ); | |
| 9476 ins_pipe(pipe_class_compare); | |
| 9477 %} | |
| 9478 | |
| 9479 // AndI 0b0..010..0 + ConvI2B | |
| 9480 instruct convI2Bool_andI_reg_immIpowerOf2(iRegIdst dst, iRegIsrc src, immIpowerOf2 mask) %{ | |
| 9481 match(Set dst (Conv2B (AndI src mask))); | |
| 9482 predicate(UseRotateAndMaskInstructionsPPC64); | |
| 9483 ins_cost(DEFAULT_COST); | |
| 9484 | |
| 9485 format %{ "RLWINM $dst, $src, $mask \t// convI2B(AndI($src, $mask))" %} | |
| 9486 size(4); | |
| 9487 ins_encode %{ | |
| 9488 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); | |
| 9489 __ rlwinm($dst$$Register, $src$$Register, (32-log2_long((jlong)$mask$$constant)) & 0x1f, 31, 31); | |
| 9490 %} | |
| 9491 ins_pipe(pipe_class_default); | |
| 9492 %} | |
| 9493 | |
| 9494 // Convert pointer to boolean. | |
| 9495 // | |
| 9496 // ptr_to_bool(src) : { 1 if src != 0 | |
| 9497 // { 0 else | |
| 9498 // | |
| 9499 // strategy: | |
| 9500 // 1) Count leading zeros of 64 bit-value src, | |
| 9501 // this returns 64 (0b100.0000) iff src == 0 and <64 otherwise. | |
| 9502 // 2) Shift 6 bits to the right, result is 0b1 iff src == 0, 0b0 otherwise. | |
| 9503 // 3) Xori the result to get 0b1 if src != 0 and 0b0 if src == 0. | |
| 9504 | |
| 9505 // ConvP2B | |
| 9506 instruct convP2Bool_reg__cntlz_Ex(iRegIdst dst, iRegP_N2P src) %{ | |
| 9507 match(Set dst (Conv2B src)); | |
| 9508 predicate(UseCountLeadingZerosInstructionsPPC64); | |
| 9509 ins_cost(DEFAULT_COST); | |
| 9510 | |
| 9511 expand %{ | |
| 9512 immI shiftAmount %{ 0x6 %} | |
| 9513 uimmI16 mask %{ 0x1 %} | |
| 9514 iRegIdst tmp1; | |
| 9515 iRegIdst tmp2; | |
| 9516 countLeadingZerosP(tmp1, src); | |
| 9517 urShiftI_reg_imm(tmp2, tmp1, shiftAmount); | |
| 9518 xorI_reg_uimm16(dst, tmp2, mask); | |
| 9519 %} | |
| 9520 %} | |
| 9521 | |
| 9522 instruct convP2Bool_reg__cmove(iRegIdst dst, iRegP_N2P src, flagsReg crx) %{ | |
| 9523 match(Set dst (Conv2B src)); | |
| 9524 effect(TEMP crx); | |
| 9525 predicate(!UseCountLeadingZerosInstructionsPPC64); | |
| 9526 ins_cost(DEFAULT_COST); | |
| 9527 | |
| 9528 format %{ "CMPDI $crx, $src, #0 \t// convP2B" | |
| 9529 "LI $dst, #0\n\t" | |
| 9530 "BEQ $crx, done\n\t" | |
| 9531 "LI $dst, #1\n" | |
| 9532 "done:" %} | |
| 9533 size(16); | |
| 9534 ins_encode( enc_convP2B_regP__cmove(dst, src, crx, 0x0, 0x1) ); | |
| 9535 ins_pipe(pipe_class_compare); | |
| 9536 %} | |
| 9537 | |
| 9538 // ConvP2B + XorI | |
| 9539 instruct xorI_convP2Bool_reg__cntlz_Ex(iRegIdst dst, iRegP_N2P src, immI_1 mask) %{ | |
| 9540 match(Set dst (XorI (Conv2B src) mask)); | |
| 9541 predicate(UseCountLeadingZerosInstructionsPPC64); | |
| 9542 ins_cost(DEFAULT_COST); | |
| 9543 | |
| 9544 expand %{ | |
| 9545 immI shiftAmount %{ 0x6 %} | |
| 9546 iRegIdst tmp1; | |
| 9547 countLeadingZerosP(tmp1, src); | |
| 9548 urShiftI_reg_imm(dst, tmp1, shiftAmount); | |
| 9549 %} | |
| 9550 %} | |
| 9551 | |
| 9552 instruct xorI_convP2Bool_reg_immIvalue1__cmove(iRegIdst dst, iRegP_N2P src, flagsReg crx, immI_1 mask) %{ | |
| 9553 match(Set dst (XorI (Conv2B src) mask)); | |
| 9554 effect(TEMP crx); | |
| 9555 predicate(!UseCountLeadingZerosInstructionsPPC64); | |
| 9556 ins_cost(DEFAULT_COST); | |
| 9557 | |
| 9558 format %{ "CMPDI $crx, $src, #0 \t// XorI(convP2B($src), $mask)" | |
| 9559 "LI $dst, #1\n\t" | |
| 9560 "BEQ $crx, done\n\t" | |
| 9561 "LI $dst, #0\n" | |
| 9562 "done:" %} | |
| 9563 size(16); | |
| 9564 ins_encode( enc_convP2B_regP__cmove(dst, src, crx, 0x1, 0x0) ); | |
| 9565 ins_pipe(pipe_class_compare); | |
| 9566 %} | |
| 9567 | |
| 9568 // if src1 < src2, return -1 else return 0 | |
| 9569 instruct cmpLTMask_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ | |
| 9570 match(Set dst (CmpLTMask src1 src2)); | |
| 9571 ins_cost(DEFAULT_COST*4); | |
| 9572 | |
| 9573 expand %{ | |
| 9574 iRegIdst src1s; | |
| 9575 iRegIdst src2s; | |
| 9576 iRegIdst diff; | |
| 9577 sxtI_reg(src1s, src1); // ensure proper sign extention | |
| 9578 sxtI_reg(src2s, src2); // ensure proper sign extention | |
| 9579 subI_reg_reg(diff, src1s, src2s); | |
| 9580 // Need to consider >=33 bit result, therefore we need signmaskL. | |
| 9581 signmask64I_regI(dst, diff); | |
| 9582 %} | |
| 9583 %} | |
| 9584 | |
| 9585 instruct cmpLTMask_reg_immI0(iRegIdst dst, iRegIsrc src1, immI_0 src2) %{ | |
| 9586 match(Set dst (CmpLTMask src1 src2)); // if src1 < src2, return -1 else return 0 | |
| 9587 format %{ "SRAWI $dst, $src1, $src2 \t// CmpLTMask" %} | |
| 9588 size(4); | |
| 9589 ins_encode %{ | |
| 9590 // TODO: PPC port $archOpcode(ppc64Opcode_srawi); | |
| 9591 __ srawi($dst$$Register, $src1$$Register, 0x1f); | |
| 9592 %} | |
| 9593 ins_pipe(pipe_class_default); | |
| 9594 %} | |
| 9595 | |
| 9596 //----------Arithmetic Conversion Instructions--------------------------------- | |
| 9597 | |
| 9598 // Convert to Byte -- nop | |
| 9599 // Convert to Short -- nop | |
| 9600 | |
| 9601 // Convert to Int | |
| 9602 | |
| 9603 instruct convB2I_reg(iRegIdst dst, iRegIsrc src, immI_24 amount) %{ | |
| 9604 match(Set dst (RShiftI (LShiftI src amount) amount)); | |
| 9605 format %{ "EXTSB $dst, $src \t// byte->int" %} | |
| 9606 size(4); | |
| 9607 ins_encode %{ | |
| 9608 // TODO: PPC port $archOpcode(ppc64Opcode_extsb); | |
| 9609 __ extsb($dst$$Register, $src$$Register); | |
| 9610 %} | |
| 9611 ins_pipe(pipe_class_default); | |
| 9612 %} | |
| 9613 | |
| 9614 // LShiftI 16 + RShiftI 16 converts short to int. | |
| 9615 instruct convS2I_reg(iRegIdst dst, iRegIsrc src, immI_16 amount) %{ | |
| 9616 match(Set dst (RShiftI (LShiftI src amount) amount)); | |
| 9617 format %{ "EXTSH $dst, $src \t// short->int" %} | |
| 9618 size(4); | |
| 9619 ins_encode %{ | |
| 9620 // TODO: PPC port $archOpcode(ppc64Opcode_extsh); | |
| 9621 __ extsh($dst$$Register, $src$$Register); | |
| 9622 %} | |
| 9623 ins_pipe(pipe_class_default); | |
| 9624 %} | |
| 9625 | |
| 9626 // ConvL2I + ConvI2L: Sign extend int in long register. | |
| 9627 instruct sxtI_L2L_reg(iRegLdst dst, iRegLsrc src) %{ | |
| 9628 match(Set dst (ConvI2L (ConvL2I src))); | |
| 9629 | |
| 9630 format %{ "EXTSW $dst, $src \t// long->long" %} | |
| 9631 size(4); | |
| 9632 ins_encode %{ | |
| 9633 // TODO: PPC port $archOpcode(ppc64Opcode_extsw); | |
| 9634 __ extsw($dst$$Register, $src$$Register); | |
| 9635 %} | |
| 9636 ins_pipe(pipe_class_default); | |
| 9637 %} | |
| 9638 | |
| 9639 instruct convL2I_reg(iRegIdst dst, iRegLsrc src) %{ | |
| 9640 match(Set dst (ConvL2I src)); | |
| 9641 format %{ "MR $dst, $src \t// long->int" %} | |
| 9642 // variable size, 0 or 4 | |
| 9643 ins_encode %{ | |
| 9644 // TODO: PPC port $archOpcode(ppc64Opcode_or); | |
| 9645 __ mr_if_needed($dst$$Register, $src$$Register); | |
| 9646 %} | |
| 9647 ins_pipe(pipe_class_default); | |
| 9648 %} | |
| 9649 | |
| 9650 instruct convD2IRaw_regD(regD dst, regD src) %{ | |
| 9651 // no match-rule, false predicate | |
| 9652 effect(DEF dst, USE src); | |
| 9653 predicate(false); | |
| 9654 | |
| 9655 format %{ "FCTIWZ $dst, $src \t// convD2I, $src != NaN" %} | |
| 9656 size(4); | |
| 9657 ins_encode %{ | |
| 9658 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);; | |
| 9659 __ fctiwz($dst$$FloatRegister, $src$$FloatRegister); | |
| 9660 %} | |
| 9661 ins_pipe(pipe_class_default); | |
| 9662 %} | |
| 9663 | |
| 9664 instruct cmovI_bso_stackSlotL(iRegIdst dst, flagsReg crx, stackSlotL src) %{ | |
| 9665 // no match-rule, false predicate | |
| 9666 effect(DEF dst, USE crx, USE src); | |
| 9667 predicate(false); | |
| 9668 | |
| 9669 ins_variable_size_depending_on_alignment(true); | |
| 9670 | |
| 9671 format %{ "cmovI $crx, $dst, $src" %} | |
| 9672 // Worst case is branch + move + stop, no stop without scheduler. | |
| 9673 size(false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8); | |
| 9674 ins_encode( enc_cmove_bso_stackSlotL(dst, crx, src) ); | |
| 9675 ins_pipe(pipe_class_default); | |
| 9676 %} | |
| 9677 | |
| 9678 instruct cmovI_bso_stackSlotL_conLvalue0_Ex(iRegIdst dst, flagsReg crx, stackSlotL mem) %{ | |
| 9679 // no match-rule, false predicate | |
| 9680 effect(DEF dst, USE crx, USE mem); | |
| 9681 predicate(false); | |
| 9682 | |
| 9683 format %{ "CmovI $dst, $crx, $mem \t// postalloc expanded" %} | |
| 9684 postalloc_expand %{ | |
| 9685 // | |
| 9686 // replaces | |
| 9687 // | |
| 9688 // region dst crx mem | |
| 9689 // \ | | / | |
| 9690 // dst=cmovI_bso_stackSlotL_conLvalue0 | |
| 9691 // | |
| 9692 // with | |
| 9693 // | |
| 9694 // region dst | |
| 9695 // \ / | |
| 9696 // dst=loadConI16(0) | |
| 9697 // | | |
| 9698 // ^ region dst crx mem | |
| 9699 // | \ | | / | |
| 9700 // dst=cmovI_bso_stackSlotL | |
| 9701 // | |
| 9702 | |
| 9703 // Create new nodes. | |
| 9704 MachNode *m1 = new (C) loadConI16Node(); | |
| 9705 MachNode *m2 = new (C) cmovI_bso_stackSlotLNode(); | |
| 9706 | |
| 9707 // inputs for new nodes | |
| 9708 m1->add_req(n_region); | |
| 9709 m2->add_req(n_region, n_crx, n_mem); | |
| 9710 | |
| 9711 // precedences for new nodes | |
| 9712 m2->add_prec(m1); | |
| 9713 | |
| 9714 // operands for new nodes | |
| 9715 m1->_opnds[0] = op_dst; | |
| 9716 m1->_opnds[1] = new (C) immI16Oper(0); | |
| 9717 | |
| 9718 m2->_opnds[0] = op_dst; | |
| 9719 m2->_opnds[1] = op_crx; | |
| 9720 m2->_opnds[2] = op_mem; | |
| 9721 | |
| 9722 // registers for new nodes | |
| 9723 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst | |
| 9724 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst | |
| 9725 | |
| 9726 // Insert new nodes. | |
| 9727 nodes->push(m1); | |
| 9728 nodes->push(m2); | |
| 9729 %} | |
| 9730 %} | |
| 9731 | |
| 9732 // Double to Int conversion, NaN is mapped to 0. | |
| 9733 instruct convD2I_reg_ExEx(iRegIdst dst, regD src) %{ | |
| 9734 match(Set dst (ConvD2I src)); | |
| 9735 ins_cost(DEFAULT_COST); | |
| 9736 | |
| 9737 expand %{ | |
| 9738 regD tmpD; | |
| 9739 stackSlotL tmpS; | |
| 9740 flagsReg crx; | |
| 9741 cmpDUnordered_reg_reg(crx, src, src); // Check whether src is NaN. | |
| 9742 convD2IRaw_regD(tmpD, src); // Convert float to int (speculated). | |
| 9743 moveD2L_reg_stack(tmpS, tmpD); // Store float to stack (speculated). | |
| 9744 cmovI_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check. | |
| 9745 %} | |
| 9746 %} | |
| 9747 | |
| 9748 instruct convF2IRaw_regF(regF dst, regF src) %{ | |
| 9749 // no match-rule, false predicate | |
| 9750 effect(DEF dst, USE src); | |
| 9751 predicate(false); | |
| 9752 | |
| 9753 format %{ "FCTIWZ $dst, $src \t// convF2I, $src != NaN" %} | |
| 9754 size(4); | |
| 9755 ins_encode %{ | |
| 9756 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz); | |
| 9757 __ fctiwz($dst$$FloatRegister, $src$$FloatRegister); | |
| 9758 %} | |
| 9759 ins_pipe(pipe_class_default); | |
| 9760 %} | |
| 9761 | |
| 9762 // Float to Int conversion, NaN is mapped to 0. | |
| 9763 instruct convF2I_regF_ExEx(iRegIdst dst, regF src) %{ | |
| 9764 match(Set dst (ConvF2I src)); | |
| 9765 ins_cost(DEFAULT_COST); | |
| 9766 | |
| 9767 expand %{ | |
| 9768 regF tmpF; | |
| 9769 stackSlotL tmpS; | |
| 9770 flagsReg crx; | |
| 9771 cmpFUnordered_reg_reg(crx, src, src); // Check whether src is NaN. | |
| 9772 convF2IRaw_regF(tmpF, src); // Convert float to int (speculated). | |
| 9773 moveF2L_reg_stack(tmpS, tmpF); // Store float to stack (speculated). | |
| 9774 cmovI_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check. | |
| 9775 %} | |
| 9776 %} | |
| 9777 | |
| 9778 // Convert to Long | |
| 9779 | |
| 9780 instruct convI2L_reg(iRegLdst dst, iRegIsrc src) %{ | |
| 9781 match(Set dst (ConvI2L src)); | |
| 9782 format %{ "EXTSW $dst, $src \t// int->long" %} | |
| 9783 size(4); | |
| 9784 ins_encode %{ | |
| 9785 // TODO: PPC port $archOpcode(ppc64Opcode_extsw); | |
| 9786 __ extsw($dst$$Register, $src$$Register); | |
| 9787 %} | |
| 9788 ins_pipe(pipe_class_default); | |
| 9789 %} | |
| 9790 | |
| 9791 // Zero-extend: convert unsigned int to long (convUI2L). | |
| 9792 instruct zeroExtendL_regI(iRegLdst dst, iRegIsrc src, immL_32bits mask) %{ | |
| 9793 match(Set dst (AndL (ConvI2L src) mask)); | |
| 9794 ins_cost(DEFAULT_COST); | |
| 9795 | |
| 9796 format %{ "CLRLDI $dst, $src, #32 \t// zero-extend int to long" %} | |
| 9797 size(4); | |
| 9798 ins_encode %{ | |
| 9799 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); | |
| 9800 __ clrldi($dst$$Register, $src$$Register, 32); | |
| 9801 %} | |
| 9802 ins_pipe(pipe_class_default); | |
| 9803 %} | |
| 9804 | |
| 9805 // Zero-extend: convert unsigned int to long in long register. | |
| 9806 instruct zeroExtendL_regL(iRegLdst dst, iRegLsrc src, immL_32bits mask) %{ | |
| 9807 match(Set dst (AndL src mask)); | |
| 9808 ins_cost(DEFAULT_COST); | |
| 9809 | |
| 9810 format %{ "CLRLDI $dst, $src, #32 \t// zero-extend int to long" %} | |
| 9811 size(4); | |
| 9812 ins_encode %{ | |
| 9813 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); | |
| 9814 __ clrldi($dst$$Register, $src$$Register, 32); | |
| 9815 %} | |
| 9816 ins_pipe(pipe_class_default); | |
| 9817 %} | |
| 9818 | |
| 9819 instruct convF2LRaw_regF(regF dst, regF src) %{ | |
| 9820 // no match-rule, false predicate | |
| 9821 effect(DEF dst, USE src); | |
| 9822 predicate(false); | |
| 9823 | |
| 9824 format %{ "FCTIDZ $dst, $src \t// convF2L, $src != NaN" %} | |
| 9825 size(4); | |
| 9826 ins_encode %{ | |
| 9827 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz); | |
| 9828 __ fctidz($dst$$FloatRegister, $src$$FloatRegister); | |
| 9829 %} | |
| 9830 ins_pipe(pipe_class_default); | |
| 9831 %} | |
| 9832 | |
| 9833 instruct cmovL_bso_stackSlotL(iRegLdst dst, flagsReg crx, stackSlotL src) %{ | |
| 9834 // no match-rule, false predicate | |
| 9835 effect(DEF dst, USE crx, USE src); | |
| 9836 predicate(false); | |
| 9837 | |
| 9838 ins_variable_size_depending_on_alignment(true); | |
| 9839 | |
| 9840 format %{ "cmovL $crx, $dst, $src" %} | |
| 9841 // Worst case is branch + move + stop, no stop without scheduler. | |
| 9842 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); | |
| 9843 ins_encode( enc_cmove_bso_stackSlotL(dst, crx, src) ); | |
| 9844 ins_pipe(pipe_class_default); | |
| 9845 %} | |
| 9846 | |
| 9847 instruct cmovL_bso_stackSlotL_conLvalue0_Ex(iRegLdst dst, flagsReg crx, stackSlotL mem) %{ | |
| 9848 // no match-rule, false predicate | |
| 9849 effect(DEF dst, USE crx, USE mem); | |
| 9850 predicate(false); | |
| 9851 | |
| 9852 format %{ "CmovL $dst, $crx, $mem \t// postalloc expanded" %} | |
| 9853 postalloc_expand %{ | |
| 9854 // | |
| 9855 // replaces | |
| 9856 // | |
| 9857 // region dst crx mem | |
| 9858 // \ | | / | |
| 9859 // dst=cmovL_bso_stackSlotL_conLvalue0 | |
| 9860 // | |
| 9861 // with | |
| 9862 // | |
| 9863 // region dst | |
| 9864 // \ / | |
| 9865 // dst=loadConL16(0) | |
| 9866 // | | |
| 9867 // ^ region dst crx mem | |
| 9868 // | \ | | / | |
| 9869 // dst=cmovL_bso_stackSlotL | |
| 9870 // | |
| 9871 | |
| 9872 // Create new nodes. | |
| 9873 MachNode *m1 = new (C) loadConL16Node(); | |
| 9874 MachNode *m2 = new (C) cmovL_bso_stackSlotLNode(); | |
| 9875 | |
| 9876 // inputs for new nodes | |
| 9877 m1->add_req(n_region); | |
| 9878 m2->add_req(n_region, n_crx, n_mem); | |
| 9879 m2->add_prec(m1); | |
| 9880 | |
| 9881 // operands for new nodes | |
| 9882 m1->_opnds[0] = op_dst; | |
| 9883 m1->_opnds[1] = new (C) immL16Oper(0); | |
| 9884 m2->_opnds[0] = op_dst; | |
| 9885 m2->_opnds[1] = op_crx; | |
| 9886 m2->_opnds[2] = op_mem; | |
| 9887 | |
| 9888 // registers for new nodes | |
| 9889 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst | |
| 9890 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst | |
| 9891 | |
| 9892 // Insert new nodes. | |
| 9893 nodes->push(m1); | |
| 9894 nodes->push(m2); | |
| 9895 %} | |
| 9896 %} | |
| 9897 | |
| 9898 // Float to Long conversion, NaN is mapped to 0. | |
| 9899 instruct convF2L_reg_ExEx(iRegLdst dst, regF src) %{ | |
| 9900 match(Set dst (ConvF2L src)); | |
| 9901 ins_cost(DEFAULT_COST); | |
| 9902 | |
| 9903 expand %{ | |
| 9904 regF tmpF; | |
| 9905 stackSlotL tmpS; | |
| 9906 flagsReg crx; | |
| 9907 cmpFUnordered_reg_reg(crx, src, src); // Check whether src is NaN. | |
| 9908 convF2LRaw_regF(tmpF, src); // Convert float to long (speculated). | |
| 9909 moveF2L_reg_stack(tmpS, tmpF); // Store float to stack (speculated). | |
| 9910 cmovL_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check. | |
| 9911 %} | |
| 9912 %} | |
| 9913 | |
| 9914 instruct convD2LRaw_regD(regD dst, regD src) %{ | |
| 9915 // no match-rule, false predicate | |
| 9916 effect(DEF dst, USE src); | |
| 9917 predicate(false); | |
| 9918 | |
| 9919 format %{ "FCTIDZ $dst, $src \t// convD2L $src != NaN" %} | |
| 9920 size(4); | |
| 9921 ins_encode %{ | |
| 9922 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz); | |
| 9923 __ fctidz($dst$$FloatRegister, $src$$FloatRegister); | |
| 9924 %} | |
| 9925 ins_pipe(pipe_class_default); | |
| 9926 %} | |
| 9927 | |
| 9928 // Double to Long conversion, NaN is mapped to 0. | |
| 9929 instruct convD2L_reg_ExEx(iRegLdst dst, regD src) %{ | |
| 9930 match(Set dst (ConvD2L src)); | |
| 9931 ins_cost(DEFAULT_COST); | |
| 9932 | |
| 9933 expand %{ | |
| 9934 regD tmpD; | |
| 9935 stackSlotL tmpS; | |
| 9936 flagsReg crx; | |
| 9937 cmpDUnordered_reg_reg(crx, src, src); // Check whether src is NaN. | |
| 9938 convD2LRaw_regD(tmpD, src); // Convert float to long (speculated). | |
| 9939 moveD2L_reg_stack(tmpS, tmpD); // Store float to stack (speculated). | |
| 9940 cmovL_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check. | |
| 9941 %} | |
| 9942 %} | |
| 9943 | |
| 9944 // Convert to Float | |
| 9945 | |
| 9946 // Placed here as needed in expand. | |
| 9947 instruct convL2DRaw_regD(regD dst, regD src) %{ | |
| 9948 // no match-rule, false predicate | |
| 9949 effect(DEF dst, USE src); | |
| 9950 predicate(false); | |
| 9951 | |
| 9952 format %{ "FCFID $dst, $src \t// convL2D" %} | |
| 9953 size(4); | |
| 9954 ins_encode %{ | |
| 9955 // TODO: PPC port $archOpcode(ppc64Opcode_fcfid); | |
| 9956 __ fcfid($dst$$FloatRegister, $src$$FloatRegister); | |
| 9957 %} | |
| 9958 ins_pipe(pipe_class_default); | |
| 9959 %} | |
| 9960 | |
| 9961 // Placed here as needed in expand. | |
| 9962 instruct convD2F_reg(regF dst, regD src) %{ | |
| 9963 match(Set dst (ConvD2F src)); | |
| 9964 format %{ "FRSP $dst, $src \t// convD2F" %} | |
| 9965 size(4); | |
| 9966 ins_encode %{ | |
| 9967 // TODO: PPC port $archOpcode(ppc64Opcode_frsp); | |
| 9968 __ frsp($dst$$FloatRegister, $src$$FloatRegister); | |
| 9969 %} | |
| 9970 ins_pipe(pipe_class_default); | |
| 9971 %} | |
| 9972 | |
| 9973 // Integer to Float conversion. | |
| 9974 instruct convI2F_ireg_Ex(regF dst, iRegIsrc src) %{ | |
| 9975 match(Set dst (ConvI2F src)); | |
| 9976 predicate(!VM_Version::has_fcfids()); | |
| 9977 ins_cost(DEFAULT_COST); | |
| 9978 | |
| 9979 expand %{ | |
| 9980 iRegLdst tmpL; | |
| 9981 stackSlotL tmpS; | |
| 9982 regD tmpD; | |
| 9983 regD tmpD2; | |
| 9984 convI2L_reg(tmpL, src); // Sign-extension int to long. | |
| 9985 regL_to_stkL(tmpS, tmpL); // Store long to stack. | |
| 9986 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register. | |
| 9987 convL2DRaw_regD(tmpD2, tmpD); // Convert to double. | |
| 9988 convD2F_reg(dst, tmpD2); // Convert double to float. | |
| 9989 %} | |
| 9990 %} | |
| 9991 | |
| 9992 instruct convL2FRaw_regF(regF dst, regD src) %{ | |
| 9993 // no match-rule, false predicate | |
| 9994 effect(DEF dst, USE src); | |
| 9995 predicate(false); | |
| 9996 | |
| 9997 format %{ "FCFIDS $dst, $src \t// convL2F" %} | |
| 9998 size(4); | |
| 9999 ins_encode %{ | |
| 10000 // TODO: PPC port $archOpcode(ppc64Opcode_fcfid); | |
| 10001 __ fcfids($dst$$FloatRegister, $src$$FloatRegister); | |
| 10002 %} | |
| 10003 ins_pipe(pipe_class_default); | |
| 10004 %} | |
| 10005 | |
| 10006 // Integer to Float conversion. Special version for Power7. | |
| 10007 instruct convI2F_ireg_fcfids_Ex(regF dst, iRegIsrc src) %{ | |
| 10008 match(Set dst (ConvI2F src)); | |
| 10009 predicate(VM_Version::has_fcfids()); | |
| 10010 ins_cost(DEFAULT_COST); | |
| 10011 | |
| 10012 expand %{ | |
| 10013 iRegLdst tmpL; | |
| 10014 stackSlotL tmpS; | |
| 10015 regD tmpD; | |
| 10016 convI2L_reg(tmpL, src); // Sign-extension int to long. | |
| 10017 regL_to_stkL(tmpS, tmpL); // Store long to stack. | |
| 10018 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register. | |
| 10019 convL2FRaw_regF(dst, tmpD); // Convert to float. | |
| 10020 %} | |
| 10021 %} | |
| 10022 | |
| 10023 // L2F to avoid runtime call. | |
| 10024 instruct convL2F_ireg_fcfids_Ex(regF dst, iRegLsrc src) %{ | |
| 10025 match(Set dst (ConvL2F src)); | |
| 10026 predicate(VM_Version::has_fcfids()); | |
| 10027 ins_cost(DEFAULT_COST); | |
| 10028 | |
| 10029 expand %{ | |
| 10030 stackSlotL tmpS; | |
| 10031 regD tmpD; | |
| 10032 regL_to_stkL(tmpS, src); // Store long to stack. | |
| 10033 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register. | |
| 10034 convL2FRaw_regF(dst, tmpD); // Convert to float. | |
| 10035 %} | |
| 10036 %} | |
| 10037 | |
| 10038 // Moved up as used in expand. | |
| 10039 //instruct convD2F_reg(regF dst, regD src) %{%} | |
| 10040 | |
| 10041 // Convert to Double | |
| 10042 | |
| 10043 // Integer to Double conversion. | |
| 10044 instruct convI2D_reg_Ex(regD dst, iRegIsrc src) %{ | |
| 10045 match(Set dst (ConvI2D src)); | |
| 10046 ins_cost(DEFAULT_COST); | |
| 10047 | |
| 10048 expand %{ | |
| 10049 iRegLdst tmpL; | |
| 10050 stackSlotL tmpS; | |
| 10051 regD tmpD; | |
| 10052 convI2L_reg(tmpL, src); // Sign-extension int to long. | |
| 10053 regL_to_stkL(tmpS, tmpL); // Store long to stack. | |
| 10054 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register. | |
| 10055 convL2DRaw_regD(dst, tmpD); // Convert to double. | |
| 10056 %} | |
| 10057 %} | |
| 10058 | |
| 10059 // Long to Double conversion | |
| 10060 instruct convL2D_reg_Ex(regD dst, stackSlotL src) %{ | |
| 10061 match(Set dst (ConvL2D src)); | |
| 10062 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
| 10063 | |
| 10064 expand %{ | |
| 10065 regD tmpD; | |
| 10066 moveL2D_stack_reg(tmpD, src); | |
| 10067 convL2DRaw_regD(dst, tmpD); | |
| 10068 %} | |
| 10069 %} | |
| 10070 | |
| 10071 instruct convF2D_reg(regD dst, regF src) %{ | |
| 10072 match(Set dst (ConvF2D src)); | |
| 10073 format %{ "FMR $dst, $src \t// float->double" %} | |
| 10074 // variable size, 0 or 4 | |
| 10075 ins_encode %{ | |
| 10076 // TODO: PPC port $archOpcode(ppc64Opcode_fmr); | |
| 10077 __ fmr_if_needed($dst$$FloatRegister, $src$$FloatRegister); | |
| 10078 %} | |
| 10079 ins_pipe(pipe_class_default); | |
| 10080 %} | |
| 10081 | |
| 10082 //----------Control Flow Instructions------------------------------------------ | |
| 10083 // Compare Instructions | |
| 10084 | |
| 10085 // Compare Integers | |
| 10086 instruct cmpI_reg_reg(flagsReg crx, iRegIsrc src1, iRegIsrc src2) %{ | |
| 10087 match(Set crx (CmpI src1 src2)); | |
| 10088 size(4); | |
| 10089 format %{ "CMPW $crx, $src1, $src2" %} | |
| 10090 ins_encode %{ | |
| 10091 // TODO: PPC port $archOpcode(ppc64Opcode_cmp); | |
| 10092 __ cmpw($crx$$CondRegister, $src1$$Register, $src2$$Register); | |
| 10093 %} | |
| 10094 ins_pipe(pipe_class_compare); | |
| 10095 %} | |
| 10096 | |
| 10097 instruct cmpI_reg_imm16(flagsReg crx, iRegIsrc src1, immI16 src2) %{ | |
| 10098 match(Set crx (CmpI src1 src2)); | |
| 10099 format %{ "CMPWI $crx, $src1, $src2" %} | |
| 10100 size(4); | |
| 10101 ins_encode %{ | |
| 10102 // TODO: PPC port $archOpcode(ppc64Opcode_cmpi); | |
| 10103 __ cmpwi($crx$$CondRegister, $src1$$Register, $src2$$constant); | |
| 10104 %} | |
| 10105 ins_pipe(pipe_class_compare); | |
| 10106 %} | |
| 10107 | |
| 10108 // (src1 & src2) == 0? | |
| 10109 instruct testI_reg_imm(flagsRegCR0 cr0, iRegIsrc src1, uimmI16 src2, immI_0 zero) %{ | |
| 10110 match(Set cr0 (CmpI (AndI src1 src2) zero)); | |
| 10111 // r0 is killed | |
| 10112 format %{ "ANDI R0, $src1, $src2 \t// BTST int" %} | |
| 10113 size(4); | |
| 10114 ins_encode %{ | |
| 10115 // TODO: PPC port $archOpcode(ppc64Opcode_andi_); | |
| 10116 // FIXME: avoid andi_ ? | |
| 10117 __ andi_(R0, $src1$$Register, $src2$$constant); | |
| 10118 %} | |
| 10119 ins_pipe(pipe_class_compare); | |
| 10120 %} | |
| 10121 | |
| 10122 instruct cmpL_reg_reg(flagsReg crx, iRegLsrc src1, iRegLsrc src2) %{ | |
| 10123 match(Set crx (CmpL src1 src2)); | |
| 10124 format %{ "CMPD $crx, $src1, $src2" %} | |
| 10125 size(4); | |
| 10126 ins_encode %{ | |
| 10127 // TODO: PPC port $archOpcode(ppc64Opcode_cmp); | |
| 10128 __ cmpd($crx$$CondRegister, $src1$$Register, $src2$$Register); | |
| 10129 %} | |
| 10130 ins_pipe(pipe_class_compare); | |
| 10131 %} | |
| 10132 | |
| 10133 instruct cmpL_reg_imm16(flagsReg crx, iRegLsrc src1, immL16 src2) %{ | |
| 10134 match(Set crx (CmpL src1 src2)); | |
| 10135 format %{ "CMPDI $crx, $src1, $src2" %} | |
| 10136 size(4); | |
| 10137 ins_encode %{ | |
| 10138 // TODO: PPC port $archOpcode(ppc64Opcode_cmpi); | |
| 10139 __ cmpdi($crx$$CondRegister, $src1$$Register, $src2$$constant); | |
| 10140 %} | |
| 10141 ins_pipe(pipe_class_compare); | |
| 10142 %} | |
| 10143 | |
| 10144 instruct testL_reg_reg(flagsRegCR0 cr0, iRegLsrc src1, iRegLsrc src2, immL_0 zero) %{ | |
| 10145 match(Set cr0 (CmpL (AndL src1 src2) zero)); | |
| 10146 // r0 is killed | |
| 10147 format %{ "AND R0, $src1, $src2 \t// BTST long" %} | |
| 10148 size(4); | |
| 10149 ins_encode %{ | |
| 10150 // TODO: PPC port $archOpcode(ppc64Opcode_and_); | |
| 10151 __ and_(R0, $src1$$Register, $src2$$Register); | |
| 10152 %} | |
| 10153 ins_pipe(pipe_class_compare); | |
| 10154 %} | |
| 10155 | |
| 10156 instruct testL_reg_imm(flagsRegCR0 cr0, iRegLsrc src1, uimmL16 src2, immL_0 zero) %{ | |
| 10157 match(Set cr0 (CmpL (AndL src1 src2) zero)); | |
| 10158 // r0 is killed | |
| 10159 format %{ "ANDI R0, $src1, $src2 \t// BTST long" %} | |
| 10160 size(4); | |
| 10161 ins_encode %{ | |
| 10162 // TODO: PPC port $archOpcode(ppc64Opcode_andi_); | |
| 10163 // FIXME: avoid andi_ ? | |
| 10164 __ andi_(R0, $src1$$Register, $src2$$constant); | |
| 10165 %} | |
| 10166 ins_pipe(pipe_class_compare); | |
| 10167 %} | |
| 10168 | |
| 10169 instruct cmovI_conIvalueMinus1_conIvalue1(iRegIdst dst, flagsReg crx) %{ | |
| 10170 // no match-rule, false predicate | |
| 10171 effect(DEF dst, USE crx); | |
| 10172 predicate(false); | |
| 10173 | |
| 10174 ins_variable_size_depending_on_alignment(true); | |
| 10175 | |
| 10176 format %{ "cmovI $crx, $dst, -1, 0, +1" %} | |
| 10177 // Worst case is branch + move + branch + move + stop, no stop without scheduler. | |
| 10178 size(false /* TODO: PPC PORTInsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 20 : 16); | |
| 10179 ins_encode %{ | |
| 10180 // TODO: PPC port $archOpcode(ppc64Opcode_cmove); | |
| 10181 Label done; | |
| 10182 // li(Rdst, 0); // equal -> 0 | |
| 10183 __ beq($crx$$CondRegister, done); | |
| 10184 __ li($dst$$Register, 1); // greater -> +1 | |
| 10185 __ bgt($crx$$CondRegister, done); | |
| 10186 __ li($dst$$Register, -1); // unordered or less -> -1 | |
| 10187 // TODO: PPC port__ endgroup_if_needed(_size == 20); | |
| 10188 __ bind(done); | |
| 10189 %} | |
| 10190 ins_pipe(pipe_class_compare); | |
| 10191 %} | |
| 10192 | |
| 10193 instruct cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(iRegIdst dst, flagsReg crx) %{ | |
| 10194 // no match-rule, false predicate | |
| 10195 effect(DEF dst, USE crx); | |
| 10196 predicate(false); | |
| 10197 | |
| 10198 format %{ "CmovI $crx, $dst, -1, 0, +1 \t// postalloc expanded" %} | |
| 10199 postalloc_expand %{ | |
| 10200 // | |
| 10201 // replaces | |
| 10202 // | |
| 10203 // region crx | |
| 10204 // \ | | |
| 10205 // dst=cmovI_conIvalueMinus1_conIvalue0_conIvalue1 | |
| 10206 // | |
| 10207 // with | |
| 10208 // | |
| 10209 // region | |
| 10210 // \ | |
| 10211 // dst=loadConI16(0) | |
| 10212 // | | |
| 10213 // ^ region crx | |
| 10214 // | \ | | |
| 10215 // dst=cmovI_conIvalueMinus1_conIvalue1 | |
| 10216 // | |
| 10217 | |
| 10218 // Create new nodes. | |
| 10219 MachNode *m1 = new (C) loadConI16Node(); | |
| 10220 MachNode *m2 = new (C) cmovI_conIvalueMinus1_conIvalue1Node(); | |
| 10221 | |
| 10222 // inputs for new nodes | |
| 10223 m1->add_req(n_region); | |
| 10224 m2->add_req(n_region, n_crx); | |
| 10225 m2->add_prec(m1); | |
| 10226 | |
| 10227 // operands for new nodes | |
| 10228 m1->_opnds[0] = op_dst; | |
| 10229 m1->_opnds[1] = new (C) immI16Oper(0); | |
| 10230 m2->_opnds[0] = op_dst; | |
| 10231 m2->_opnds[1] = op_crx; | |
| 10232 | |
| 10233 // registers for new nodes | |
| 10234 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst | |
| 10235 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst | |
| 10236 | |
| 10237 // Insert new nodes. | |
| 10238 nodes->push(m1); | |
| 10239 nodes->push(m2); | |
| 10240 %} | |
| 10241 %} | |
| 10242 | |
| 10243 // Manifest a CmpL3 result in an integer register. Very painful. | |
| 10244 // This is the test to avoid. | |
| 10245 // (src1 < src2) ? -1 : ((src1 > src2) ? 1 : 0) | |
| 10246 instruct cmpL3_reg_reg_ExEx(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{ | |
| 10247 match(Set dst (CmpL3 src1 src2)); | |
| 10248 ins_cost(DEFAULT_COST*5+BRANCH_COST); | |
| 10249 | |
| 10250 expand %{ | |
| 10251 flagsReg tmp1; | |
| 10252 cmpL_reg_reg(tmp1, src1, src2); | |
| 10253 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1); | |
| 10254 %} | |
| 10255 %} | |
| 10256 | |
| 10257 // Implicit range checks. | |
| 10258 // A range check in the ideal world has one of the following shapes: | |
| 10259 // - (If le (CmpU length index)), (IfTrue throw exception) | |
| 10260 // - (If lt (CmpU index length)), (IfFalse throw exception) | |
| 10261 // | |
| 10262 // Match range check 'If le (CmpU length index)'. | |
| 10263 instruct rangeCheck_iReg_uimm15(cmpOp cmp, iRegIsrc src_length, uimmI15 index, label labl) %{ | |
| 10264 match(If cmp (CmpU src_length index)); | |
| 10265 effect(USE labl); | |
| 10266 predicate(TrapBasedRangeChecks && | |
| 10267 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le && | |
| 10268 PROB_UNLIKELY(_leaf->as_If()->_prob) >= PROB_ALWAYS && | |
| 10269 (Matcher::branches_to_uncommon_trap(_leaf))); | |
| 10270 | |
| 10271 ins_is_TrapBasedCheckNode(true); | |
| 10272 | |
| 10273 format %{ "TWI $index $cmp $src_length \t// RangeCheck => trap $labl" %} | |
| 10274 size(4); | |
| 10275 ins_encode %{ | |
| 10276 // TODO: PPC port $archOpcode(ppc64Opcode_twi); | |
| 10277 if ($cmp$$cmpcode == 0x1 /* less_equal */) { | |
| 10278 __ trap_range_check_le($src_length$$Register, $index$$constant); | |
| 10279 } else { | |
| 10280 // Both successors are uncommon traps, probability is 0. | |
| 10281 // Node got flipped during fixup flow. | |
| 10282 assert($cmp$$cmpcode == 0x9, "must be greater"); | |
| 10283 __ trap_range_check_g($src_length$$Register, $index$$constant); | |
| 10284 } | |
| 10285 %} | |
| 10286 ins_pipe(pipe_class_trap); | |
| 10287 %} | |
| 10288 | |
| 10289 // Match range check 'If lt (CmpU index length)'. | |
| 10290 instruct rangeCheck_iReg_iReg(cmpOp cmp, iRegIsrc src_index, iRegIsrc src_length, label labl) %{ | |
| 10291 match(If cmp (CmpU src_index src_length)); | |
| 10292 effect(USE labl); | |
| 10293 predicate(TrapBasedRangeChecks && | |
| 10294 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt && | |
| 10295 _leaf->as_If()->_prob >= PROB_ALWAYS && | |
| 10296 (Matcher::branches_to_uncommon_trap(_leaf))); | |
| 10297 | |
| 10298 ins_is_TrapBasedCheckNode(true); | |
| 10299 | |
| 10300 format %{ "TW $src_index $cmp $src_length \t// RangeCheck => trap $labl" %} | |
| 10301 size(4); | |
| 10302 ins_encode %{ | |
| 10303 // TODO: PPC port $archOpcode(ppc64Opcode_tw); | |
| 10304 if ($cmp$$cmpcode == 0x0 /* greater_equal */) { | |
| 10305 __ trap_range_check_ge($src_index$$Register, $src_length$$Register); | |
| 10306 } else { | |
| 10307 // Both successors are uncommon traps, probability is 0. | |
| 10308 // Node got flipped during fixup flow. | |
| 10309 assert($cmp$$cmpcode == 0x8, "must be less"); | |
| 10310 __ trap_range_check_l($src_index$$Register, $src_length$$Register); | |
| 10311 } | |
| 10312 %} | |
| 10313 ins_pipe(pipe_class_trap); | |
| 10314 %} | |
| 10315 | |
| 10316 // Match range check 'If lt (CmpU index length)'. | |
| 10317 instruct rangeCheck_uimm15_iReg(cmpOp cmp, iRegIsrc src_index, uimmI15 length, label labl) %{ | |
| 10318 match(If cmp (CmpU src_index length)); | |
| 10319 effect(USE labl); | |
| 10320 predicate(TrapBasedRangeChecks && | |
| 10321 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt && | |
| 10322 _leaf->as_If()->_prob >= PROB_ALWAYS && | |
| 10323 (Matcher::branches_to_uncommon_trap(_leaf))); | |
| 10324 | |
| 10325 ins_is_TrapBasedCheckNode(true); | |
| 10326 | |
| 10327 format %{ "TWI $src_index $cmp $length \t// RangeCheck => trap $labl" %} | |
| 10328 size(4); | |
| 10329 ins_encode %{ | |
| 10330 // TODO: PPC port $archOpcode(ppc64Opcode_twi); | |
| 10331 if ($cmp$$cmpcode == 0x0 /* greater_equal */) { | |
| 10332 __ trap_range_check_ge($src_index$$Register, $length$$constant); | |
| 10333 } else { | |
| 10334 // Both successors are uncommon traps, probability is 0. | |
| 10335 // Node got flipped during fixup flow. | |
| 10336 assert($cmp$$cmpcode == 0x8, "must be less"); | |
| 10337 __ trap_range_check_l($src_index$$Register, $length$$constant); | |
| 10338 } | |
| 10339 %} | |
| 10340 ins_pipe(pipe_class_trap); | |
| 10341 %} | |
| 10342 | |
| 10343 instruct compU_reg_reg(flagsReg crx, iRegIsrc src1, iRegIsrc src2) %{ | |
| 10344 match(Set crx (CmpU src1 src2)); | |
| 10345 format %{ "CMPLW $crx, $src1, $src2 \t// unsigned" %} | |
| 10346 size(4); | |
| 10347 ins_encode %{ | |
| 10348 // TODO: PPC port $archOpcode(ppc64Opcode_cmpl); | |
| 10349 __ cmplw($crx$$CondRegister, $src1$$Register, $src2$$Register); | |
| 10350 %} | |
| 10351 ins_pipe(pipe_class_compare); | |
| 10352 %} | |
| 10353 | |
| 10354 instruct compU_reg_uimm16(flagsReg crx, iRegIsrc src1, uimmI16 src2) %{ | |
| 10355 match(Set crx (CmpU src1 src2)); | |
| 10356 size(4); | |
| 10357 format %{ "CMPLWI $crx, $src1, $src2" %} | |
| 10358 ins_encode %{ | |
| 10359 // TODO: PPC port $archOpcode(ppc64Opcode_cmpli); | |
| 10360 __ cmplwi($crx$$CondRegister, $src1$$Register, $src2$$constant); | |
| 10361 %} | |
| 10362 ins_pipe(pipe_class_compare); | |
| 10363 %} | |
| 10364 | |
| 10365 // Implicit zero checks (more implicit null checks). | |
| 10366 // No constant pool entries required. | |
| 10367 instruct zeroCheckN_iReg_imm0(cmpOp cmp, iRegNsrc value, immN_0 zero, label labl) %{ | |
| 10368 match(If cmp (CmpN value zero)); | |
| 10369 effect(USE labl); | |
| 10370 predicate(TrapBasedNullChecks && | |
| 10371 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne && | |
| 10372 _leaf->as_If()->_prob >= PROB_LIKELY_MAG(4) && | |
| 10373 Matcher::branches_to_uncommon_trap(_leaf)); | |
| 10374 ins_cost(1); | |
| 10375 | |
| 10376 ins_is_TrapBasedCheckNode(true); | |
| 10377 | |
| 10378 format %{ "TDI $value $cmp $zero \t// ZeroCheckN => trap $labl" %} | |
| 10379 size(4); | |
| 10380 ins_encode %{ | |
| 10381 // TODO: PPC port $archOpcode(ppc64Opcode_tdi); | |
| 10382 if ($cmp$$cmpcode == 0xA) { | |
| 10383 __ trap_null_check($value$$Register); | |
| 10384 } else { | |
| 10385 // Both successors are uncommon traps, probability is 0. | |
| 10386 // Node got flipped during fixup flow. | |
| 10387 assert($cmp$$cmpcode == 0x2 , "must be equal(0xA) or notEqual(0x2)"); | |
| 10388 __ trap_null_check($value$$Register, Assembler::traptoGreaterThanUnsigned); | |
| 10389 } | |
| 10390 %} | |
| 10391 ins_pipe(pipe_class_trap); | |
| 10392 %} | |
| 10393 | |
| 10394 // Compare narrow oops. | |
| 10395 instruct cmpN_reg_reg(flagsReg crx, iRegNsrc src1, iRegNsrc src2) %{ | |
| 10396 match(Set crx (CmpN src1 src2)); | |
| 10397 | |
| 10398 size(4); | |
| 10399 ins_cost(DEFAULT_COST); | |
| 10400 format %{ "CMPLW $crx, $src1, $src2 \t// compressed ptr" %} | |
| 10401 ins_encode %{ | |
| 10402 // TODO: PPC port $archOpcode(ppc64Opcode_cmpl); | |
| 10403 __ cmplw($crx$$CondRegister, $src1$$Register, $src2$$Register); | |
| 10404 %} | |
| 10405 ins_pipe(pipe_class_compare); | |
| 10406 %} | |
| 10407 | |
| 10408 instruct cmpN_reg_imm0(flagsReg crx, iRegNsrc src1, immN_0 src2) %{ | |
| 10409 match(Set crx (CmpN src1 src2)); | |
| 10410 // Make this more expensive than zeroCheckN_iReg_imm0. | |
| 10411 ins_cost(DEFAULT_COST); | |
| 10412 | |
| 10413 format %{ "CMPLWI $crx, $src1, $src2 \t// compressed ptr" %} | |
| 10414 size(4); | |
| 10415 ins_encode %{ | |
| 10416 // TODO: PPC port $archOpcode(ppc64Opcode_cmpli); | |
| 10417 __ cmplwi($crx$$CondRegister, $src1$$Register, $src2$$constant); | |
| 10418 %} | |
| 10419 ins_pipe(pipe_class_compare); | |
| 10420 %} | |
| 10421 | |
| 10422 // Implicit zero checks (more implicit null checks). | |
| 10423 // No constant pool entries required. | |
| 10424 instruct zeroCheckP_reg_imm0(cmpOp cmp, iRegP_N2P value, immP_0 zero, label labl) %{ | |
| 10425 match(If cmp (CmpP value zero)); | |
| 10426 effect(USE labl); | |
| 10427 predicate(TrapBasedNullChecks && | |
| 10428 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne && | |
| 10429 _leaf->as_If()->_prob >= PROB_LIKELY_MAG(4) && | |
| 10430 Matcher::branches_to_uncommon_trap(_leaf)); | |
| 10431 | |
| 10432 ins_is_TrapBasedCheckNode(true); | |
| 10433 | |
| 10434 format %{ "TDI $value $cmp $zero \t// ZeroCheckP => trap $labl" %} | |
| 10435 size(4); | |
| 10436 ins_encode %{ | |
| 10437 // TODO: PPC port $archOpcode(ppc64Opcode_tdi); | |
| 10438 if ($cmp$$cmpcode == 0xA) { | |
| 10439 __ trap_null_check($value$$Register); | |
| 10440 } else { | |
| 10441 // Both successors are uncommon traps, probability is 0. | |
| 10442 // Node got flipped during fixup flow. | |
| 10443 assert($cmp$$cmpcode == 0x2 , "must be equal(0xA) or notEqual(0x2)"); | |
| 10444 __ trap_null_check($value$$Register, Assembler::traptoGreaterThanUnsigned); | |
| 10445 } | |
| 10446 %} | |
| 10447 ins_pipe(pipe_class_trap); | |
| 10448 %} | |
| 10449 | |
| 10450 // Compare Pointers | |
| 10451 instruct cmpP_reg_reg(flagsReg crx, iRegP_N2P src1, iRegP_N2P src2) %{ | |
| 10452 match(Set crx (CmpP src1 src2)); | |
| 10453 format %{ "CMPLD $crx, $src1, $src2 \t// ptr" %} | |
| 10454 size(4); | |
| 10455 ins_encode %{ | |
| 10456 // TODO: PPC port $archOpcode(ppc64Opcode_cmpl); | |
| 10457 __ cmpld($crx$$CondRegister, $src1$$Register, $src2$$Register); | |
| 10458 %} | |
| 10459 ins_pipe(pipe_class_compare); | |
| 10460 %} | |
| 10461 | |
| 10462 // Used in postalloc expand. | |
| 10463 instruct cmpP_reg_imm16(flagsReg crx, iRegPsrc src1, immL16 src2) %{ | |
| 10464 // This match rule prevents reordering of node before a safepoint. | |
| 10465 // This only makes sense if this instructions is used exclusively | |
| 10466 // for the expansion of EncodeP! | |
| 10467 match(Set crx (CmpP src1 src2)); | |
| 10468 predicate(false); | |
| 10469 | |
| 10470 format %{ "CMPDI $crx, $src1, $src2" %} | |
| 10471 size(4); | |
| 10472 ins_encode %{ | |
| 10473 // TODO: PPC port $archOpcode(ppc64Opcode_cmpi); | |
| 10474 __ cmpdi($crx$$CondRegister, $src1$$Register, $src2$$constant); | |
| 10475 %} | |
| 10476 ins_pipe(pipe_class_compare); | |
| 10477 %} | |
| 10478 | |
| 10479 //----------Float Compares---------------------------------------------------- | |
| 10480 | |
| 10481 instruct cmpFUnordered_reg_reg(flagsReg crx, regF src1, regF src2) %{ | |
| 10482 // no match-rule, false predicate | |
| 10483 effect(DEF crx, USE src1, USE src2); | |
| 10484 predicate(false); | |
| 10485 | |
| 10486 format %{ "cmpFUrd $crx, $src1, $src2" %} | |
| 10487 size(4); | |
| 10488 ins_encode %{ | |
| 10489 // TODO: PPC port $archOpcode(ppc64Opcode_fcmpu); | |
| 10490 __ fcmpu($crx$$CondRegister, $src1$$FloatRegister, $src2$$FloatRegister); | |
| 10491 %} | |
| 10492 ins_pipe(pipe_class_default); | |
| 10493 %} | |
| 10494 | |
| 10495 instruct cmov_bns_less(flagsReg crx) %{ | |
| 10496 // no match-rule, false predicate | |
| 10497 effect(DEF crx); | |
| 10498 predicate(false); | |
| 10499 | |
| 10500 ins_variable_size_depending_on_alignment(true); | |
| 10501 | |
| 10502 format %{ "cmov $crx" %} | |
| 10503 // Worst case is branch + move + stop, no stop without scheduler. | |
| 10504 size(false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 16 : 12); | |
| 10505 ins_encode %{ | |
| 10506 // TODO: PPC port $archOpcode(ppc64Opcode_cmovecr); | |
| 10507 Label done; | |
| 10508 __ bns($crx$$CondRegister, done); // not unordered -> keep crx | |
| 10509 __ li(R0, 0); | |
| 10510 __ cmpwi($crx$$CondRegister, R0, 1); // unordered -> set crx to 'less' | |
| 10511 // TODO PPC port __ endgroup_if_needed(_size == 16); | |
| 10512 __ bind(done); | |
| 10513 %} | |
| 10514 ins_pipe(pipe_class_default); | |
| 10515 %} | |
| 10516 | |
| 10517 // Compare floating, generate condition code. | |
| 10518 instruct cmpF_reg_reg_Ex(flagsReg crx, regF src1, regF src2) %{ | |
| 10519 // FIXME: should we match 'If cmp (CmpF src1 src2))' ?? | |
| 10520 // | |
| 10521 // The following code sequence occurs a lot in mpegaudio: | |
| 10522 // | |
| 10523 // block BXX: | |
| 10524 // 0: instruct cmpFUnordered_reg_reg (cmpF_reg_reg-0): | |
| 10525 // cmpFUrd CCR6, F11, F9 | |
| 10526 // 4: instruct cmov_bns_less (cmpF_reg_reg-1): | |
| 10527 // cmov CCR6 | |
| 10528 // 8: instruct branchConSched: | |
| 10529 // B_FARle CCR6, B56 P=0.500000 C=-1.000000 | |
| 10530 match(Set crx (CmpF src1 src2)); | |
| 10531 ins_cost(DEFAULT_COST+BRANCH_COST); | |
| 10532 | |
| 10533 format %{ "CmpF $crx, $src1, $src2 \t// postalloc expanded" %} | |
| 10534 postalloc_expand %{ | |
| 10535 // | |
| 10536 // replaces | |
| 10537 // | |
| 10538 // region src1 src2 | |
| 10539 // \ | | | |
| 10540 // crx=cmpF_reg_reg | |
| 10541 // | |
| 10542 // with | |
| 10543 // | |
| 10544 // region src1 src2 | |
| 10545 // \ | | | |
| 10546 // crx=cmpFUnordered_reg_reg | |
| 10547 // | | |
| 10548 // ^ region | |
| 10549 // | \ | |
| 10550 // crx=cmov_bns_less | |
| 10551 // | |
| 10552 | |
| 10553 // Create new nodes. | |
| 10554 MachNode *m1 = new (C) cmpFUnordered_reg_regNode(); | |
| 10555 MachNode *m2 = new (C) cmov_bns_lessNode(); | |
| 10556 | |
| 10557 // inputs for new nodes | |
| 10558 m1->add_req(n_region, n_src1, n_src2); | |
| 10559 m2->add_req(n_region); | |
| 10560 m2->add_prec(m1); | |
| 10561 | |
| 10562 // operands for new nodes | |
| 10563 m1->_opnds[0] = op_crx; | |
| 10564 m1->_opnds[1] = op_src1; | |
| 10565 m1->_opnds[2] = op_src2; | |
| 10566 m2->_opnds[0] = op_crx; | |
| 10567 | |
| 10568 // registers for new nodes | |
| 10569 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx | |
| 10570 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx | |
| 10571 | |
| 10572 // Insert new nodes. | |
| 10573 nodes->push(m1); | |
| 10574 nodes->push(m2); | |
| 10575 %} | |
| 10576 %} | |
| 10577 | |
| 10578 // Compare float, generate -1,0,1 | |
| 10579 instruct cmpF3_reg_reg_ExEx(iRegIdst dst, regF src1, regF src2) %{ | |
| 10580 match(Set dst (CmpF3 src1 src2)); | |
| 10581 ins_cost(DEFAULT_COST*5+BRANCH_COST); | |
| 10582 | |
| 10583 expand %{ | |
| 10584 flagsReg tmp1; | |
| 10585 cmpFUnordered_reg_reg(tmp1, src1, src2); | |
| 10586 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1); | |
| 10587 %} | |
| 10588 %} | |
| 10589 | |
| 10590 instruct cmpDUnordered_reg_reg(flagsReg crx, regD src1, regD src2) %{ | |
| 10591 // no match-rule, false predicate | |
| 10592 effect(DEF crx, USE src1, USE src2); | |
| 10593 predicate(false); | |
| 10594 | |
| 10595 format %{ "cmpFUrd $crx, $src1, $src2" %} | |
| 10596 size(4); | |
| 10597 ins_encode %{ | |
| 10598 // TODO: PPC port $archOpcode(ppc64Opcode_fcmpu); | |
| 10599 __ fcmpu($crx$$CondRegister, $src1$$FloatRegister, $src2$$FloatRegister); | |
| 10600 %} | |
| 10601 ins_pipe(pipe_class_default); | |
| 10602 %} | |
| 10603 | |
| 10604 instruct cmpD_reg_reg_Ex(flagsReg crx, regD src1, regD src2) %{ | |
| 10605 match(Set crx (CmpD src1 src2)); | |
| 10606 ins_cost(DEFAULT_COST+BRANCH_COST); | |
| 10607 | |
| 10608 format %{ "CmpD $crx, $src1, $src2 \t// postalloc expanded" %} | |
| 10609 postalloc_expand %{ | |
| 10610 // | |
| 10611 // replaces | |
| 10612 // | |
| 10613 // region src1 src2 | |
| 10614 // \ | | | |
| 10615 // crx=cmpD_reg_reg | |
| 10616 // | |
| 10617 // with | |
| 10618 // | |
| 10619 // region src1 src2 | |
| 10620 // \ | | | |
| 10621 // crx=cmpDUnordered_reg_reg | |
| 10622 // | | |
| 10623 // ^ region | |
| 10624 // | \ | |
| 10625 // crx=cmov_bns_less | |
| 10626 // | |
| 10627 | |
| 10628 // create new nodes | |
| 10629 MachNode *m1 = new (C) cmpDUnordered_reg_regNode(); | |
| 10630 MachNode *m2 = new (C) cmov_bns_lessNode(); | |
| 10631 | |
| 10632 // inputs for new nodes | |
| 10633 m1->add_req(n_region, n_src1, n_src2); | |
| 10634 m2->add_req(n_region); | |
| 10635 m2->add_prec(m1); | |
| 10636 | |
| 10637 // operands for new nodes | |
| 10638 m1->_opnds[0] = op_crx; | |
| 10639 m1->_opnds[1] = op_src1; | |
| 10640 m1->_opnds[2] = op_src2; | |
| 10641 m2->_opnds[0] = op_crx; | |
| 10642 | |
| 10643 // registers for new nodes | |
| 10644 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx | |
| 10645 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx | |
| 10646 | |
| 10647 // Insert new nodes. | |
| 10648 nodes->push(m1); | |
| 10649 nodes->push(m2); | |
| 10650 %} | |
| 10651 %} | |
| 10652 | |
| 10653 // Compare double, generate -1,0,1 | |
| 10654 instruct cmpD3_reg_reg_ExEx(iRegIdst dst, regD src1, regD src2) %{ | |
| 10655 match(Set dst (CmpD3 src1 src2)); | |
| 10656 ins_cost(DEFAULT_COST*5+BRANCH_COST); | |
| 10657 | |
| 10658 expand %{ | |
| 10659 flagsReg tmp1; | |
| 10660 cmpDUnordered_reg_reg(tmp1, src1, src2); | |
| 10661 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1); | |
| 10662 %} | |
| 10663 %} | |
| 10664 | |
| 10665 //----------Branches--------------------------------------------------------- | |
| 10666 // Jump | |
| 10667 | |
| 10668 // Direct Branch. | |
| 10669 instruct branch(label labl) %{ | |
| 10670 match(Goto); | |
| 10671 effect(USE labl); | |
| 10672 ins_cost(BRANCH_COST); | |
| 10673 | |
| 10674 format %{ "B $labl" %} | |
| 10675 size(4); | |
| 10676 ins_encode %{ | |
| 10677 // TODO: PPC port $archOpcode(ppc64Opcode_b); | |
| 10678 Label d; // dummy | |
| 10679 __ bind(d); | |
| 10680 Label* p = $labl$$label; | |
| 10681 // `p' is `NULL' when this encoding class is used only to | |
| 10682 // determine the size of the encoded instruction. | |
| 10683 Label& l = (NULL == p)? d : *(p); | |
| 10684 __ b(l); | |
| 10685 %} | |
| 10686 ins_pipe(pipe_class_default); | |
| 10687 %} | |
| 10688 | |
| 10689 // Conditional Near Branch | |
| 10690 instruct branchCon(cmpOp cmp, flagsReg crx, label lbl) %{ | |
| 10691 // Same match rule as `branchConFar'. | |
| 10692 match(If cmp crx); | |
| 10693 effect(USE lbl); | |
| 10694 ins_cost(BRANCH_COST); | |
| 10695 | |
| 10696 // If set to 1 this indicates that the current instruction is a | |
| 10697 // short variant of a long branch. This avoids using this | |
| 10698 // instruction in first-pass matching. It will then only be used in | |
| 10699 // the `Shorten_branches' pass. | |
| 10700 ins_short_branch(1); | |
| 10701 | |
| 10702 format %{ "B$cmp $crx, $lbl" %} | |
| 10703 size(4); | |
| 10704 ins_encode( enc_bc(crx, cmp, lbl) ); | |
| 10705 ins_pipe(pipe_class_default); | |
| 10706 %} | |
| 10707 | |
| 10708 // This is for cases when the ppc64 `bc' instruction does not | |
| 10709 // reach far enough. So we emit a far branch here, which is more | |
| 10710 // expensive. | |
| 10711 // | |
| 10712 // Conditional Far Branch | |
| 10713 instruct branchConFar(cmpOp cmp, flagsReg crx, label lbl) %{ | |
| 10714 // Same match rule as `branchCon'. | |
| 10715 match(If cmp crx); | |
| 10716 effect(USE crx, USE lbl); | |
| 10717 predicate(!false /* TODO: PPC port HB_Schedule*/); | |
| 10718 // Higher cost than `branchCon'. | |
| 10719 ins_cost(5*BRANCH_COST); | |
| 10720 | |
| 10721 // This is not a short variant of a branch, but the long variant. | |
| 10722 ins_short_branch(0); | |
| 10723 | |
| 10724 format %{ "B_FAR$cmp $crx, $lbl" %} | |
| 10725 size(8); | |
| 10726 ins_encode( enc_bc_far(crx, cmp, lbl) ); | |
| 10727 ins_pipe(pipe_class_default); | |
| 10728 %} | |
| 10729 | |
| 10730 // Conditional Branch used with Power6 scheduler (can be far or short). | |
| 10731 instruct branchConSched(cmpOp cmp, flagsReg crx, label lbl) %{ | |
| 10732 // Same match rule as `branchCon'. | |
| 10733 match(If cmp crx); | |
| 10734 effect(USE crx, USE lbl); | |
| 10735 predicate(false /* TODO: PPC port HB_Schedule*/); | |
| 10736 // Higher cost than `branchCon'. | |
| 10737 ins_cost(5*BRANCH_COST); | |
| 10738 | |
| 10739 // Actually size doesn't depend on alignment but on shortening. | |
| 10740 ins_variable_size_depending_on_alignment(true); | |
| 10741 // long variant. | |
| 10742 ins_short_branch(0); | |
| 10743 | |
| 10744 format %{ "B_FAR$cmp $crx, $lbl" %} | |
| 10745 size(8); // worst case | |
| 10746 ins_encode( enc_bc_short_far(crx, cmp, lbl) ); | |
| 10747 ins_pipe(pipe_class_default); | |
| 10748 %} | |
| 10749 | |
| 10750 instruct branchLoopEnd(cmpOp cmp, flagsReg crx, label labl) %{ | |
| 10751 match(CountedLoopEnd cmp crx); | |
| 10752 effect(USE labl); | |
| 10753 ins_cost(BRANCH_COST); | |
| 10754 | |
| 10755 // short variant. | |
| 10756 ins_short_branch(1); | |
| 10757 | |
| 10758 format %{ "B$cmp $crx, $labl \t// counted loop end" %} | |
| 10759 size(4); | |
| 10760 ins_encode( enc_bc(crx, cmp, labl) ); | |
| 10761 ins_pipe(pipe_class_default); | |
| 10762 %} | |
| 10763 | |
| 10764 instruct branchLoopEndFar(cmpOp cmp, flagsReg crx, label labl) %{ | |
| 10765 match(CountedLoopEnd cmp crx); | |
| 10766 effect(USE labl); | |
| 10767 predicate(!false /* TODO: PPC port HB_Schedule */); | |
| 10768 ins_cost(BRANCH_COST); | |
| 10769 | |
| 10770 // Long variant. | |
| 10771 ins_short_branch(0); | |
| 10772 | |
| 10773 format %{ "B_FAR$cmp $crx, $labl \t// counted loop end" %} | |
| 10774 size(8); | |
| 10775 ins_encode( enc_bc_far(crx, cmp, labl) ); | |
| 10776 ins_pipe(pipe_class_default); | |
| 10777 %} | |
| 10778 | |
| 10779 // Conditional Branch used with Power6 scheduler (can be far or short). | |
| 10780 instruct branchLoopEndSched(cmpOp cmp, flagsReg crx, label labl) %{ | |
| 10781 match(CountedLoopEnd cmp crx); | |
| 10782 effect(USE labl); | |
| 10783 predicate(false /* TODO: PPC port HB_Schedule */); | |
| 10784 // Higher cost than `branchCon'. | |
| 10785 ins_cost(5*BRANCH_COST); | |
| 10786 | |
| 10787 // Actually size doesn't depend on alignment but on shortening. | |
| 10788 ins_variable_size_depending_on_alignment(true); | |
| 10789 // Long variant. | |
| 10790 ins_short_branch(0); | |
| 10791 | |
| 10792 format %{ "B_FAR$cmp $crx, $labl \t// counted loop end" %} | |
| 10793 size(8); // worst case | |
| 10794 ins_encode( enc_bc_short_far(crx, cmp, labl) ); | |
| 10795 ins_pipe(pipe_class_default); | |
| 10796 %} | |
| 10797 | |
| 10798 // ============================================================================ | |
| 10799 // Java runtime operations, intrinsics and other complex operations. | |
| 10800 | |
| 10801 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass | |
| 10802 // array for an instance of the superklass. Set a hidden internal cache on a | |
| 10803 // hit (cache is checked with exposed code in gen_subtype_check()). Return | |
| 10804 // not zero for a miss or zero for a hit. The encoding ALSO sets flags. | |
| 10805 // | |
| 10806 // GL TODO: Improve this. | |
| 10807 // - result should not be a TEMP | |
| 10808 // - Add match rule as on sparc avoiding additional Cmp. | |
| 10809 instruct partialSubtypeCheck(iRegPdst result, iRegP_N2P subklass, iRegP_N2P superklass, | |
| 10810 iRegPdst tmp_klass, iRegPdst tmp_arrayptr) %{ | |
| 10811 match(Set result (PartialSubtypeCheck subklass superklass)); | |
| 10812 effect(TEMP result, TEMP tmp_klass, TEMP tmp_arrayptr); | |
| 10813 ins_cost(DEFAULT_COST*10); | |
| 10814 | |
| 10815 format %{ "PartialSubtypeCheck $result = ($subklass instanceOf $superklass) tmp: $tmp_klass, $tmp_arrayptr" %} | |
| 10816 ins_encode %{ | |
| 10817 // TODO: PPC port $archOpcode(ppc64Opcode_compound); | |
| 10818 __ check_klass_subtype_slow_path($subklass$$Register, $superklass$$Register, $tmp_arrayptr$$Register, | |
| 10819 $tmp_klass$$Register, NULL, $result$$Register); | |
| 10820 %} | |
| 10821 ins_pipe(pipe_class_default); | |
| 10822 %} | |
| 10823 | |
| 10824 // inlined locking and unlocking | |
| 10825 | |
| 10826 instruct cmpFastLock(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{ | |
| 10827 match(Set crx (FastLock oop box)); | |
| 10828 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3); | |
| 10829 // TODO PPC port predicate(!UseNewFastLockPPC64 || UseBiasedLocking); | |
| 10830 | |
| 10831 format %{ "FASTLOCK $oop, $box, $tmp1, $tmp2, $tmp3" %} | |
| 10832 ins_encode %{ | |
| 10833 // TODO: PPC port $archOpcode(ppc64Opcode_compound); | |
| 10834 __ compiler_fast_lock_object($crx$$CondRegister, $oop$$Register, $box$$Register, | |
| 10835 $tmp3$$Register, $tmp1$$Register, $tmp2$$Register); | |
| 10836 // If locking was successfull, crx should indicate 'EQ'. | |
| 10837 // The compiler generates a branch to the runtime call to | |
| 10838 // _complete_monitor_locking_Java for the case where crx is 'NE'. | |
| 10839 %} | |
| 10840 ins_pipe(pipe_class_compare); | |
| 10841 %} | |
| 10842 | |
| 10843 instruct cmpFastUnlock(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{ | |
| 10844 match(Set crx (FastUnlock oop box)); | |
| 10845 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3); | |
| 10846 | |
| 10847 format %{ "FASTUNLOCK $oop, $box, $tmp1, $tmp2" %} | |
| 10848 ins_encode %{ | |
| 10849 // TODO: PPC port $archOpcode(ppc64Opcode_compound); | |
| 10850 __ compiler_fast_unlock_object($crx$$CondRegister, $oop$$Register, $box$$Register, | |
| 10851 $tmp3$$Register, $tmp1$$Register, $tmp2$$Register); | |
| 10852 // If unlocking was successfull, crx should indicate 'EQ'. | |
| 10853 // The compiler generates a branch to the runtime call to | |
| 10854 // _complete_monitor_unlocking_Java for the case where crx is 'NE'. | |
| 10855 %} | |
| 10856 ins_pipe(pipe_class_compare); | |
| 10857 %} | |
| 10858 | |
| 10859 // Align address. | |
| 10860 instruct align_addr(iRegPdst dst, iRegPsrc src, immLnegpow2 mask) %{ | |
| 10861 match(Set dst (CastX2P (AndL (CastP2X src) mask))); | |
| 10862 | |
| 10863 format %{ "ANDDI $dst, $src, $mask \t// next aligned address" %} | |
| 10864 size(4); | |
| 10865 ins_encode %{ | |
| 10866 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr); | |
| 10867 __ clrrdi($dst$$Register, $src$$Register, log2_long((jlong)-$mask$$constant)); | |
| 10868 %} | |
| 10869 ins_pipe(pipe_class_default); | |
| 10870 %} | |
| 10871 | |
| 10872 // Array size computation. | |
| 10873 instruct array_size(iRegLdst dst, iRegPsrc end, iRegPsrc start) %{ | |
| 10874 match(Set dst (SubL (CastP2X end) (CastP2X start))); | |
| 10875 | |
| 10876 format %{ "SUB $dst, $end, $start \t// array size in bytes" %} | |
| 10877 size(4); | |
| 10878 ins_encode %{ | |
| 10879 // TODO: PPC port $archOpcode(ppc64Opcode_subf); | |
| 10880 __ subf($dst$$Register, $start$$Register, $end$$Register); | |
| 10881 %} | |
| 10882 ins_pipe(pipe_class_default); | |
| 10883 %} | |
| 10884 | |
| 10885 // Clear-array with dynamic array-size. | |
| 10886 instruct inlineCallClearArray(rarg1RegL cnt, rarg2RegP base, Universe dummy, regCTR ctr) %{ | |
| 10887 match(Set dummy (ClearArray cnt base)); | |
| 10888 effect(USE_KILL cnt, USE_KILL base, KILL ctr); | |
| 10889 ins_cost(MEMORY_REF_COST); | |
| 10890 | |
| 10891 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted. | |
| 10892 | |
| 10893 format %{ "ClearArray $cnt, $base" %} | |
| 10894 ins_encode %{ | |
| 10895 // TODO: PPC port $archOpcode(ppc64Opcode_compound); | |
| 10896 __ clear_memory_doubleword($base$$Register, $cnt$$Register); // kills cnt, base, R0 | |
| 10897 %} | |
| 10898 ins_pipe(pipe_class_default); | |
| 10899 %} | |
| 10900 | |
| 10901 // String_IndexOf for needle of length 1. | |
| 10902 // | |
| 10903 // Match needle into immediate operands: no loadConP node needed. Saves one | |
| 10904 // register and two instructions over string_indexOf_imm1Node. | |
| 10905 // | |
| 10906 // Assumes register result differs from all input registers. | |
| 10907 // | |
| 10908 // Preserves registers haystack, haycnt | |
| 10909 // Kills registers tmp1, tmp2 | |
| 10910 // Defines registers result | |
| 10911 // | |
| 10912 // Use dst register classes if register gets killed, as it is the case for tmp registers! | |
| 10913 // | |
| 10914 // Unfortunately this does not match too often. In many situations the AddP is used | |
| 10915 // by several nodes, even several StrIndexOf nodes, breaking the match tree. | |
| 10916 instruct string_indexOf_imm1_char(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt, | |
| 10917 immP needleImm, immL offsetImm, immI_1 needlecntImm, | |
| 10918 iRegIdst tmp1, iRegIdst tmp2, | |
| 10919 flagsRegCR0 cr0, flagsRegCR1 cr1) %{ | |
| 10920 predicate(SpecialStringIndexOf); // type check implicit by parameter type, See Matcher::match_rule_supported | |
| 10921 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary (AddP needleImm offsetImm) needlecntImm))); | |
| 10922 | |
| 10923 effect(TEMP result, TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1); | |
| 10924 | |
| 10925 ins_cost(150); | |
| 10926 format %{ "String IndexOf CSCL1 $haystack[0..$haycnt], $needleImm+$offsetImm[0..$needlecntImm]" | |
| 10927 "-> $result \t// KILL $haycnt, $tmp1, $tmp2, $cr0, $cr1" %} | |
| 10928 | |
| 10929 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted | |
| 10930 ins_encode %{ | |
| 10931 // TODO: PPC port $archOpcode(ppc64Opcode_compound); | |
| 10932 immPOper *needleOper = (immPOper *)$needleImm; | |
| 10933 const TypeOopPtr *t = needleOper->type()->isa_oopptr(); | |
| 10934 ciTypeArray* needle_values = t->const_oop()->as_type_array(); // Pointer to live char * | |
| 10935 | |
| 10936 __ string_indexof_1($result$$Register, | |
| 10937 $haystack$$Register, $haycnt$$Register, | |
| 10938 R0, needle_values->char_at(0), | |
| 10939 $tmp1$$Register, $tmp2$$Register); | |
| 10940 %} | |
| 10941 ins_pipe(pipe_class_compare); | |
| 10942 %} | |
| 10943 | |
| 10944 // String_IndexOf for needle of length 1. | |
| 10945 // | |
| 10946 // Special case requires less registers and emits less instructions. | |
| 10947 // | |
| 10948 // Assumes register result differs from all input registers. | |
| 10949 // | |
| 10950 // Preserves registers haystack, haycnt | |
| 10951 // Kills registers tmp1, tmp2, needle | |
| 10952 // Defines registers result | |
| 10953 // | |
| 10954 // Use dst register classes if register gets killed, as it is the case for tmp registers! | |
| 10955 instruct string_indexOf_imm1(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt, | |
| 10956 rscratch2RegP needle, immI_1 needlecntImm, | |
| 10957 iRegIdst tmp1, iRegIdst tmp2, | |
| 10958 flagsRegCR0 cr0, flagsRegCR1 cr1) %{ | |
| 10959 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm))); | |
| 10960 effect(USE_KILL needle, /* TDEF needle, */ TEMP result, | |
| 10961 TEMP tmp1, TEMP tmp2); | |
| 10962 // Required for EA: check if it is still a type_array. | |
| 10963 predicate(SpecialStringIndexOf && n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() && | |
| 10964 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array()); | |
| 10965 ins_cost(180); | |
| 10966 | |
| 10967 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted. | |
| 10968 | |
| 10969 format %{ "String IndexOf SCL1 $haystack[0..$haycnt], $needle[0..$needlecntImm]" | |
| 10970 " -> $result \t// KILL $haycnt, $needle, $tmp1, $tmp2, $cr0, $cr1" %} | |
| 10971 ins_encode %{ | |
| 10972 // TODO: PPC port $archOpcode(ppc64Opcode_compound); | |
| 10973 Node *ndl = in(operand_index($needle)); // The node that defines needle. | |
| 10974 ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array(); | |
| 10975 guarantee(needle_values, "sanity"); | |
| 10976 if (needle_values != NULL) { | |
| 10977 __ string_indexof_1($result$$Register, | |
| 10978 $haystack$$Register, $haycnt$$Register, | |
| 10979 R0, needle_values->char_at(0), | |
| 10980 $tmp1$$Register, $tmp2$$Register); | |
| 10981 } else { | |
| 10982 __ string_indexof_1($result$$Register, | |
| 10983 $haystack$$Register, $haycnt$$Register, | |
| 10984 $needle$$Register, 0, | |
| 10985 $tmp1$$Register, $tmp2$$Register); | |
| 10986 } | |
| 10987 %} | |
| 10988 ins_pipe(pipe_class_compare); | |
| 10989 %} | |
| 10990 | |
| 10991 // String_IndexOf. | |
| 10992 // | |
| 10993 // Length of needle as immediate. This saves instruction loading constant needle | |
| 10994 // length. | |
| 10995 // @@@ TODO Specify rules for length < 8 or so, and roll out comparison of needle | |
| 10996 // completely or do it in vector instruction. This should save registers for | |
| 10997 // needlecnt and needle. | |
| 10998 // | |
| 10999 // Assumes register result differs from all input registers. | |
| 11000 // Overwrites haycnt, needlecnt. | |
| 11001 // Use dst register classes if register gets killed, as it is the case for tmp registers! | |
| 11002 instruct string_indexOf_imm(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt, | |
| 11003 iRegPsrc needle, uimmI15 needlecntImm, | |
| 11004 iRegIdst tmp1, iRegIdst tmp2, iRegIdst tmp3, iRegIdst tmp4, iRegIdst tmp5, | |
| 11005 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6) %{ | |
| 11006 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm))); | |
| 11007 effect(USE_KILL haycnt, /* better: TDEF haycnt, */ TEMP result, | |
| 11008 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, KILL cr0, KILL cr1, KILL cr6); | |
| 11009 // Required for EA: check if it is still a type_array. | |
| 11010 predicate(SpecialStringIndexOf && n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() && | |
| 11011 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array()); | |
| 11012 ins_cost(250); | |
| 11013 | |
| 11014 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted. | |
| 11015 | |
| 11016 format %{ "String IndexOf SCL $haystack[0..$haycnt], $needle[0..$needlecntImm]" | |
| 11017 " -> $result \t// KILL $haycnt, $tmp1, $tmp2, $tmp3, $tmp4, $tmp5, $cr0, $cr1" %} | |
| 11018 ins_encode %{ | |
| 11019 // TODO: PPC port $archOpcode(ppc64Opcode_compound); | |
| 11020 Node *ndl = in(operand_index($needle)); // The node that defines needle. | |
| 11021 ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array(); | |
| 11022 | |
| 11023 __ string_indexof($result$$Register, | |
| 11024 $haystack$$Register, $haycnt$$Register, | |
| 11025 $needle$$Register, needle_values, $tmp5$$Register, $needlecntImm$$constant, | |
| 11026 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register); | |
| 11027 %} | |
| 11028 ins_pipe(pipe_class_compare); | |
| 11029 %} | |
| 11030 | |
| 11031 // StrIndexOf node. | |
| 11032 // | |
| 11033 // Assumes register result differs from all input registers. | |
| 11034 // Overwrites haycnt, needlecnt. | |
| 11035 // Use dst register classes if register gets killed, as it is the case for tmp registers! | |
| 11036 instruct string_indexOf(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt, iRegPsrc needle, rscratch2RegI needlecnt, | |
| 11037 iRegLdst tmp1, iRegLdst tmp2, iRegLdst tmp3, iRegLdst tmp4, | |
| 11038 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6) %{ | |
| 11039 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt))); | |
| 11040 effect(USE_KILL haycnt, USE_KILL needlecnt, /*better: TDEF haycnt, TDEF needlecnt,*/ | |
| 11041 TEMP result, | |
| 11042 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr0, KILL cr1, KILL cr6); | |
| 11043 predicate(SpecialStringIndexOf); // See Matcher::match_rule_supported. | |
| 11044 ins_cost(300); | |
| 11045 | |
| 11046 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted. | |
| 11047 | |
| 11048 format %{ "String IndexOf $haystack[0..$haycnt], $needle[0..$needlecnt]" | |
| 11049 " -> $result \t// KILL $haycnt, $needlecnt, $tmp1, $tmp2, $tmp3, $tmp4, $cr0, $cr1" %} | |
| 11050 ins_encode %{ | |
| 11051 // TODO: PPC port $archOpcode(ppc64Opcode_compound); | |
| 11052 __ string_indexof($result$$Register, | |
| 11053 $haystack$$Register, $haycnt$$Register, | |
| 11054 $needle$$Register, NULL, $needlecnt$$Register, 0, // needlecnt not constant. | |
| 11055 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register); | |
| 11056 %} | |
| 11057 ins_pipe(pipe_class_compare); | |
| 11058 %} | |
| 11059 | |
| 11060 // String equals with immediate. | |
| 11061 instruct string_equals_imm(iRegPsrc str1, iRegPsrc str2, uimmI15 cntImm, iRegIdst result, | |
| 11062 iRegPdst tmp1, iRegPdst tmp2, | |
| 11063 flagsRegCR0 cr0, flagsRegCR6 cr6, regCTR ctr) %{ | |
| 11064 match(Set result (StrEquals (Binary str1 str2) cntImm)); | |
| 11065 effect(TEMP result, TEMP tmp1, TEMP tmp2, | |
| 11066 KILL cr0, KILL cr6, KILL ctr); | |
| 11067 predicate(SpecialStringEquals); // See Matcher::match_rule_supported. | |
| 11068 ins_cost(250); | |
| 11069 | |
| 11070 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted. | |
| 11071 | |
| 11072 format %{ "String Equals SCL [0..$cntImm]($str1),[0..$cntImm]($str2)" | |
| 11073 " -> $result \t// KILL $cr0, $cr6, $ctr, TEMP $result, $tmp1, $tmp2" %} | |
| 11074 ins_encode %{ | |
| 11075 // TODO: PPC port $archOpcode(ppc64Opcode_compound); | |
| 11076 __ char_arrays_equalsImm($str1$$Register, $str2$$Register, $cntImm$$constant, | |
| 11077 $result$$Register, $tmp1$$Register, $tmp2$$Register); | |
| 11078 %} | |
| 11079 ins_pipe(pipe_class_compare); | |
| 11080 %} | |
| 11081 | |
| 11082 // String equals. | |
| 11083 // Use dst register classes if register gets killed, as it is the case for TEMP operands! | |
| 11084 instruct string_equals(iRegPsrc str1, iRegPsrc str2, iRegIsrc cnt, iRegIdst result, | |
| 11085 iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3, iRegPdst tmp4, iRegPdst tmp5, | |
| 11086 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6, regCTR ctr) %{ | |
| 11087 match(Set result (StrEquals (Binary str1 str2) cnt)); | |
| 11088 effect(TEMP result, TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, | |
| 11089 KILL cr0, KILL cr1, KILL cr6, KILL ctr); | |
| 11090 predicate(SpecialStringEquals); // See Matcher::match_rule_supported. | |
| 11091 ins_cost(300); | |
| 11092 | |
| 11093 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted. | |
| 11094 | |
| 11095 format %{ "String Equals [0..$cnt]($str1),[0..$cnt]($str2) -> $result" | |
| 11096 " \t// KILL $cr0, $cr1, $cr6, $ctr, TEMP $result, $tmp1, $tmp2, $tmp3, $tmp4, $tmp5" %} | |
| 11097 ins_encode %{ | |
| 11098 // TODO: PPC port $archOpcode(ppc64Opcode_compound); | |
| 11099 __ char_arrays_equals($str1$$Register, $str2$$Register, $cnt$$Register, $result$$Register, | |
| 11100 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, $tmp5$$Register); | |
| 11101 %} | |
| 11102 ins_pipe(pipe_class_compare); | |
| 11103 %} | |
| 11104 | |
| 11105 // String compare. | |
| 11106 // Char[] pointers are passed in. | |
| 11107 // Use dst register classes if register gets killed, as it is the case for TEMP operands! | |
| 11108 instruct string_compare(rarg1RegP str1, rarg2RegP str2, rarg3RegI cnt1, rarg4RegI cnt2, iRegIdst result, | |
| 11109 iRegPdst tmp, flagsRegCR0 cr0, regCTR ctr) %{ | |
| 11110 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); | |
| 11111 effect(USE_KILL cnt1, USE_KILL cnt2, USE_KILL str1, USE_KILL str2, TEMP result, TEMP tmp, KILL cr0, KILL ctr); | |
| 11112 ins_cost(300); | |
| 11113 | |
| 11114 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted. | |
| 11115 | |
| 11116 format %{ "String Compare $str1[0..$cnt1], $str2[0..$cnt2] -> $result" | |
| 11117 " \t// TEMP $tmp, $result KILLs $str1, $cnt1, $str2, $cnt2, $cr0, $ctr" %} | |
| 11118 ins_encode %{ | |
| 11119 // TODO: PPC port $archOpcode(ppc64Opcode_compound); | |
| 11120 __ string_compare($str1$$Register, $str2$$Register, $cnt1$$Register, $cnt2$$Register, | |
| 11121 $result$$Register, $tmp$$Register); | |
| 11122 %} | |
| 11123 ins_pipe(pipe_class_compare); | |
| 11124 %} | |
| 11125 | |
| 11126 //---------- Min/Max Instructions --------------------------------------------- | |
| 11127 | |
| 11128 instruct minI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ | |
| 11129 match(Set dst (MinI src1 src2)); | |
| 11130 ins_cost(DEFAULT_COST*6); | |
| 11131 | |
| 11132 expand %{ | |
| 11133 iRegIdst src1s; | |
| 11134 iRegIdst src2s; | |
| 11135 iRegIdst diff; | |
| 11136 iRegIdst sm; | |
| 11137 iRegIdst doz; // difference or zero | |
| 11138 sxtI_reg(src1s, src1); // Ensure proper sign extention. | |
| 11139 sxtI_reg(src2s, src2); // Ensure proper sign extention. | |
| 11140 subI_reg_reg(diff, src2s, src1s); | |
| 11141 // Need to consider >=33 bit result, therefore we need signmaskL. | |
| 11142 signmask64I_regI(sm, diff); | |
| 11143 andI_reg_reg(doz, diff, sm); // <=0 | |
| 11144 addI_reg_reg(dst, doz, src1s); | |
| 11145 %} | |
| 11146 %} | |
| 11147 | |
| 11148 instruct maxI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ | |
| 11149 match(Set dst (MaxI src1 src2)); | |
| 11150 ins_cost(DEFAULT_COST*6); | |
| 11151 | |
| 11152 expand %{ | |
| 11153 immI_minus1 m1 %{ -1 %} | |
| 11154 iRegIdst src1s; | |
| 11155 iRegIdst src2s; | |
| 11156 iRegIdst diff; | |
| 11157 iRegIdst sm; | |
| 11158 iRegIdst doz; // difference or zero | |
| 11159 sxtI_reg(src1s, src1); // Ensure proper sign extention. | |
| 11160 sxtI_reg(src2s, src2); // Ensure proper sign extention. | |
| 11161 subI_reg_reg(diff, src2s, src1s); | |
| 11162 // Need to consider >=33 bit result, therefore we need signmaskL. | |
| 11163 signmask64I_regI(sm, diff); | |
| 11164 andcI_reg_reg(doz, sm, m1, diff); // >=0 | |
| 11165 addI_reg_reg(dst, doz, src1s); | |
| 11166 %} | |
| 11167 %} | |
| 11168 | |
| 11169 //---------- Population Count Instructions ------------------------------------ | |
| 11170 | |
| 11171 // Popcnt for Power7. | |
| 11172 instruct popCountI(iRegIdst dst, iRegIsrc src) %{ | |
| 11173 match(Set dst (PopCountI src)); | |
| 11174 predicate(UsePopCountInstruction && VM_Version::has_popcntw()); | |
| 11175 ins_cost(DEFAULT_COST); | |
| 11176 | |
| 11177 format %{ "POPCNTW $dst, $src" %} | |
| 11178 size(4); | |
| 11179 ins_encode %{ | |
| 11180 // TODO: PPC port $archOpcode(ppc64Opcode_popcntb); | |
| 11181 __ popcntw($dst$$Register, $src$$Register); | |
| 11182 %} | |
| 11183 ins_pipe(pipe_class_default); | |
| 11184 %} | |
| 11185 | |
| 11186 // Popcnt for Power7. | |
| 11187 instruct popCountL(iRegIdst dst, iRegLsrc src) %{ | |
| 11188 predicate(UsePopCountInstruction && VM_Version::has_popcntw()); | |
| 11189 match(Set dst (PopCountL src)); | |
| 11190 ins_cost(DEFAULT_COST); | |
| 11191 | |
| 11192 format %{ "POPCNTD $dst, $src" %} | |
| 11193 size(4); | |
| 11194 ins_encode %{ | |
| 11195 // TODO: PPC port $archOpcode(ppc64Opcode_popcntb); | |
| 11196 __ popcntd($dst$$Register, $src$$Register); | |
| 11197 %} | |
| 11198 ins_pipe(pipe_class_default); | |
| 11199 %} | |
| 11200 | |
| 11201 instruct countLeadingZerosI(iRegIdst dst, iRegIsrc src) %{ | |
| 11202 match(Set dst (CountLeadingZerosI src)); | |
| 11203 predicate(UseCountLeadingZerosInstructionsPPC64); // See Matcher::match_rule_supported. | |
| 11204 ins_cost(DEFAULT_COST); | |
| 11205 | |
| 11206 format %{ "CNTLZW $dst, $src" %} | |
| 11207 size(4); | |
| 11208 ins_encode %{ | |
| 11209 // TODO: PPC port $archOpcode(ppc64Opcode_cntlzw); | |
| 11210 __ cntlzw($dst$$Register, $src$$Register); | |
| 11211 %} | |
| 11212 ins_pipe(pipe_class_default); | |
| 11213 %} | |
| 11214 | |
| 11215 instruct countLeadingZerosL(iRegIdst dst, iRegLsrc src) %{ | |
| 11216 match(Set dst (CountLeadingZerosL src)); | |
| 11217 predicate(UseCountLeadingZerosInstructionsPPC64); // See Matcher::match_rule_supported. | |
| 11218 ins_cost(DEFAULT_COST); | |
| 11219 | |
| 11220 format %{ "CNTLZD $dst, $src" %} | |
| 11221 size(4); | |
| 11222 ins_encode %{ | |
| 11223 // TODO: PPC port $archOpcode(ppc64Opcode_cntlzd); | |
| 11224 __ cntlzd($dst$$Register, $src$$Register); | |
| 11225 %} | |
| 11226 ins_pipe(pipe_class_default); | |
| 11227 %} | |
| 11228 | |
| 11229 instruct countLeadingZerosP(iRegIdst dst, iRegPsrc src) %{ | |
| 11230 // no match-rule, false predicate | |
| 11231 effect(DEF dst, USE src); | |
| 11232 predicate(false); | |
| 11233 | |
| 11234 format %{ "CNTLZD $dst, $src" %} | |
| 11235 size(4); | |
| 11236 ins_encode %{ | |
| 11237 // TODO: PPC port $archOpcode(ppc64Opcode_cntlzd); | |
| 11238 __ cntlzd($dst$$Register, $src$$Register); | |
| 11239 %} | |
| 11240 ins_pipe(pipe_class_default); | |
| 11241 %} | |
| 11242 | |
| 11243 instruct countTrailingZerosI_Ex(iRegIdst dst, iRegIsrc src) %{ | |
| 11244 match(Set dst (CountTrailingZerosI src)); | |
| 11245 predicate(UseCountLeadingZerosInstructionsPPC64); | |
| 11246 ins_cost(DEFAULT_COST); | |
| 11247 | |
| 11248 expand %{ | |
| 11249 immI16 imm1 %{ (int)-1 %} | |
| 11250 immI16 imm2 %{ (int)32 %} | |
| 11251 immI_minus1 m1 %{ -1 %} | |
| 11252 iRegIdst tmpI1; | |
| 11253 iRegIdst tmpI2; | |
| 11254 iRegIdst tmpI3; | |
| 11255 addI_reg_imm16(tmpI1, src, imm1); | |
| 11256 andcI_reg_reg(tmpI2, src, m1, tmpI1); | |
| 11257 countLeadingZerosI(tmpI3, tmpI2); | |
| 11258 subI_imm16_reg(dst, imm2, tmpI3); | |
| 11259 %} | |
| 11260 %} | |
| 11261 | |
| 11262 instruct countTrailingZerosL_Ex(iRegIdst dst, iRegLsrc src) %{ | |
| 11263 match(Set dst (CountTrailingZerosL src)); | |
| 11264 predicate(UseCountLeadingZerosInstructionsPPC64); | |
| 11265 ins_cost(DEFAULT_COST); | |
| 11266 | |
| 11267 expand %{ | |
| 11268 immL16 imm1 %{ (long)-1 %} | |
| 11269 immI16 imm2 %{ (int)64 %} | |
| 11270 iRegLdst tmpL1; | |
| 11271 iRegLdst tmpL2; | |
| 11272 iRegIdst tmpL3; | |
| 11273 addL_reg_imm16(tmpL1, src, imm1); | |
| 11274 andcL_reg_reg(tmpL2, tmpL1, src); | |
| 11275 countLeadingZerosL(tmpL3, tmpL2); | |
| 11276 subI_imm16_reg(dst, imm2, tmpL3); | |
| 11277 %} | |
| 11278 %} | |
| 11279 | |
| 11280 // Expand nodes for byte_reverse_int. | |
| 11281 instruct insrwi_a(iRegIdst dst, iRegIsrc src, immI16 pos, immI16 shift) %{ | |
| 11282 effect(DEF dst, USE src, USE pos, USE shift); | |
| 11283 predicate(false); | |
| 11284 | |
| 11285 format %{ "INSRWI $dst, $src, $pos, $shift" %} | |
| 11286 size(4); | |
| 11287 ins_encode %{ | |
| 11288 // TODO: PPC port $archOpcode(ppc64Opcode_rlwimi); | |
| 11289 __ insrwi($dst$$Register, $src$$Register, $shift$$constant, $pos$$constant); | |
| 11290 %} | |
| 11291 ins_pipe(pipe_class_default); | |
| 11292 %} | |
| 11293 | |
| 11294 // As insrwi_a, but with USE_DEF. | |
| 11295 instruct insrwi(iRegIdst dst, iRegIsrc src, immI16 pos, immI16 shift) %{ | |
| 11296 effect(USE_DEF dst, USE src, USE pos, USE shift); | |
| 11297 predicate(false); | |
| 11298 | |
| 11299 format %{ "INSRWI $dst, $src, $pos, $shift" %} | |
| 11300 size(4); | |
| 11301 ins_encode %{ | |
| 11302 // TODO: PPC port $archOpcode(ppc64Opcode_rlwimi); | |
| 11303 __ insrwi($dst$$Register, $src$$Register, $shift$$constant, $pos$$constant); | |
| 11304 %} | |
| 11305 ins_pipe(pipe_class_default); | |
| 11306 %} | |
| 11307 | |
| 11308 // Just slightly faster than java implementation. | |
| 11309 instruct bytes_reverse_int_Ex(iRegIdst dst, iRegIsrc src) %{ | |
| 11310 match(Set dst (ReverseBytesI src)); | |
| 11311 predicate(UseCountLeadingZerosInstructionsPPC64); | |
| 11312 ins_cost(DEFAULT_COST); | |
| 11313 | |
| 11314 expand %{ | |
| 11315 immI16 imm24 %{ (int) 24 %} | |
| 11316 immI16 imm16 %{ (int) 16 %} | |
| 11317 immI16 imm8 %{ (int) 8 %} | |
| 11318 immI16 imm4 %{ (int) 4 %} | |
| 11319 immI16 imm0 %{ (int) 0 %} | |
| 11320 iRegLdst tmpI1; | |
| 11321 iRegLdst tmpI2; | |
| 11322 iRegLdst tmpI3; | |
| 11323 | |
| 11324 urShiftI_reg_imm(tmpI1, src, imm24); | |
| 11325 insrwi_a(dst, tmpI1, imm24, imm8); | |
| 11326 urShiftI_reg_imm(tmpI2, src, imm16); | |
| 11327 insrwi(dst, tmpI2, imm8, imm16); | |
| 11328 urShiftI_reg_imm(tmpI3, src, imm8); | |
| 11329 insrwi(dst, tmpI3, imm8, imm8); | |
| 11330 insrwi(dst, src, imm0, imm8); | |
| 11331 %} | |
| 11332 %} | |
| 11333 | |
| 11334 //---------- Replicate Vector Instructions ------------------------------------ | |
| 11335 | |
| 11336 // Insrdi does replicate if src == dst. | |
| 11337 instruct repl32(iRegLdst dst) %{ | |
| 11338 predicate(false); | |
| 11339 effect(USE_DEF dst); | |
| 11340 | |
| 11341 format %{ "INSRDI $dst, #0, $dst, #32 \t// replicate" %} | |
| 11342 size(4); | |
| 11343 ins_encode %{ | |
| 11344 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi); | |
| 11345 __ insrdi($dst$$Register, $dst$$Register, 32, 0); | |
| 11346 %} | |
| 11347 ins_pipe(pipe_class_default); | |
| 11348 %} | |
| 11349 | |
| 11350 // Insrdi does replicate if src == dst. | |
| 11351 instruct repl48(iRegLdst dst) %{ | |
| 11352 predicate(false); | |
| 11353 effect(USE_DEF dst); | |
| 11354 | |
| 11355 format %{ "INSRDI $dst, #0, $dst, #48 \t// replicate" %} | |
| 11356 size(4); | |
| 11357 ins_encode %{ | |
| 11358 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi); | |
| 11359 __ insrdi($dst$$Register, $dst$$Register, 48, 0); | |
| 11360 %} | |
| 11361 ins_pipe(pipe_class_default); | |
| 11362 %} | |
| 11363 | |
| 11364 // Insrdi does replicate if src == dst. | |
| 11365 instruct repl56(iRegLdst dst) %{ | |
| 11366 predicate(false); | |
| 11367 effect(USE_DEF dst); | |
| 11368 | |
| 11369 format %{ "INSRDI $dst, #0, $dst, #56 \t// replicate" %} | |
| 11370 size(4); | |
| 11371 ins_encode %{ | |
| 11372 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi); | |
| 11373 __ insrdi($dst$$Register, $dst$$Register, 56, 0); | |
| 11374 %} | |
| 11375 ins_pipe(pipe_class_default); | |
| 11376 %} | |
| 11377 | |
| 11378 instruct repl8B_reg_Ex(iRegLdst dst, iRegIsrc src) %{ | |
| 11379 match(Set dst (ReplicateB src)); | |
| 11380 predicate(n->as_Vector()->length() == 8); | |
| 11381 expand %{ | |
| 11382 moveReg(dst, src); | |
| 11383 repl56(dst); | |
| 11384 repl48(dst); | |
| 11385 repl32(dst); | |
| 11386 %} | |
| 11387 %} | |
| 11388 | |
| 11389 instruct repl8B_immI0(iRegLdst dst, immI_0 zero) %{ | |
| 11390 match(Set dst (ReplicateB zero)); | |
| 11391 predicate(n->as_Vector()->length() == 8); | |
| 11392 format %{ "LI $dst, #0 \t// replicate8B" %} | |
| 11393 size(4); | |
| 11394 ins_encode %{ | |
| 11395 // TODO: PPC port $archOpcode(ppc64Opcode_addi); | |
| 11396 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF))); | |
| 11397 %} | |
| 11398 ins_pipe(pipe_class_default); | |
| 11399 %} | |
| 11400 | |
| 11401 instruct repl8B_immIminus1(iRegLdst dst, immI_minus1 src) %{ | |
| 11402 match(Set dst (ReplicateB src)); | |
| 11403 predicate(n->as_Vector()->length() == 8); | |
| 11404 format %{ "LI $dst, #-1 \t// replicate8B" %} | |
| 11405 size(4); | |
| 11406 ins_encode %{ | |
| 11407 // TODO: PPC port $archOpcode(ppc64Opcode_addi); | |
| 11408 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF))); | |
| 11409 %} | |
| 11410 ins_pipe(pipe_class_default); | |
| 11411 %} | |
| 11412 | |
| 11413 instruct repl4S_reg_Ex(iRegLdst dst, iRegIsrc src) %{ | |
| 11414 match(Set dst (ReplicateS src)); | |
| 11415 predicate(n->as_Vector()->length() == 4); | |
| 11416 expand %{ | |
| 11417 moveReg(dst, src); | |
| 11418 repl48(dst); | |
| 11419 repl32(dst); | |
| 11420 %} | |
| 11421 %} | |
| 11422 | |
| 11423 instruct repl4S_immI0(iRegLdst dst, immI_0 zero) %{ | |
| 11424 match(Set dst (ReplicateS zero)); | |
| 11425 predicate(n->as_Vector()->length() == 4); | |
| 11426 format %{ "LI $dst, #0 \t// replicate4C" %} | |
| 11427 size(4); | |
| 11428 ins_encode %{ | |
| 11429 // TODO: PPC port $archOpcode(ppc64Opcode_addi); | |
| 11430 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF))); | |
| 11431 %} | |
| 11432 ins_pipe(pipe_class_default); | |
| 11433 %} | |
| 11434 | |
| 11435 instruct repl4S_immIminus1(iRegLdst dst, immI_minus1 src) %{ | |
| 11436 match(Set dst (ReplicateS src)); | |
| 11437 predicate(n->as_Vector()->length() == 4); | |
| 11438 format %{ "LI $dst, -1 \t// replicate4C" %} | |
| 11439 size(4); | |
| 11440 ins_encode %{ | |
| 11441 // TODO: PPC port $archOpcode(ppc64Opcode_addi); | |
| 11442 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF))); | |
| 11443 %} | |
| 11444 ins_pipe(pipe_class_default); | |
| 11445 %} | |
| 11446 | |
| 11447 instruct repl2I_reg_Ex(iRegLdst dst, iRegIsrc src) %{ | |
| 11448 match(Set dst (ReplicateI src)); | |
| 11449 predicate(n->as_Vector()->length() == 2); | |
| 11450 ins_cost(2 * DEFAULT_COST); | |
| 11451 expand %{ | |
| 11452 moveReg(dst, src); | |
| 11453 repl32(dst); | |
| 11454 %} | |
| 11455 %} | |
| 11456 | |
| 11457 instruct repl2I_immI0(iRegLdst dst, immI_0 zero) %{ | |
| 11458 match(Set dst (ReplicateI zero)); | |
| 11459 predicate(n->as_Vector()->length() == 2); | |
| 11460 format %{ "LI $dst, #0 \t// replicate4C" %} | |
| 11461 size(4); | |
| 11462 ins_encode %{ | |
| 11463 // TODO: PPC port $archOpcode(ppc64Opcode_addi); | |
| 11464 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF))); | |
| 11465 %} | |
| 11466 ins_pipe(pipe_class_default); | |
| 11467 %} | |
| 11468 | |
| 11469 instruct repl2I_immIminus1(iRegLdst dst, immI_minus1 src) %{ | |
| 11470 match(Set dst (ReplicateI src)); | |
| 11471 predicate(n->as_Vector()->length() == 2); | |
| 11472 format %{ "LI $dst, -1 \t// replicate4C" %} | |
| 11473 size(4); | |
| 11474 ins_encode %{ | |
| 11475 // TODO: PPC port $archOpcode(ppc64Opcode_addi); | |
| 11476 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF))); | |
| 11477 %} | |
| 11478 ins_pipe(pipe_class_default); | |
| 11479 %} | |
| 11480 | |
| 11481 // Move float to int register via stack, replicate. | |
| 11482 instruct repl2F_reg_Ex(iRegLdst dst, regF src) %{ | |
| 11483 match(Set dst (ReplicateF src)); | |
| 11484 predicate(n->as_Vector()->length() == 2); | |
| 11485 ins_cost(2 * MEMORY_REF_COST + DEFAULT_COST); | |
| 11486 expand %{ | |
| 11487 stackSlotL tmpS; | |
| 11488 iRegIdst tmpI; | |
| 11489 moveF2I_reg_stack(tmpS, src); // Move float to stack. | |
| 11490 moveF2I_stack_reg(tmpI, tmpS); // Move stack to int reg. | |
| 11491 moveReg(dst, tmpI); // Move int to long reg. | |
| 11492 repl32(dst); // Replicate bitpattern. | |
| 11493 %} | |
| 11494 %} | |
| 11495 | |
| 11496 // Replicate scalar constant to packed float values in Double register | |
| 11497 instruct repl2F_immF_Ex(iRegLdst dst, immF src) %{ | |
| 11498 match(Set dst (ReplicateF src)); | |
| 11499 predicate(n->as_Vector()->length() == 2); | |
| 11500 ins_cost(5 * DEFAULT_COST); | |
| 11501 | |
| 11502 format %{ "LD $dst, offset, $constanttablebase\t// load replicated float $src $src from table, postalloc expanded" %} | |
| 11503 postalloc_expand( postalloc_expand_load_replF_constant(dst, src, constanttablebase) ); | |
| 11504 %} | |
| 11505 | |
| 11506 // Replicate scalar zero constant to packed float values in Double register | |
| 11507 instruct repl2F_immF0(iRegLdst dst, immF_0 zero) %{ | |
| 11508 match(Set dst (ReplicateF zero)); | |
| 11509 predicate(n->as_Vector()->length() == 2); | |
| 11510 | |
| 11511 format %{ "LI $dst, #0 \t// replicate2F" %} | |
| 11512 ins_encode %{ | |
| 11513 // TODO: PPC port $archOpcode(ppc64Opcode_addi); | |
| 11514 __ li($dst$$Register, 0x0); | |
| 11515 %} | |
| 11516 ins_pipe(pipe_class_default); | |
| 11517 %} | |
| 11518 | |
| 11519 // ============================================================================ | |
| 11520 // Safepoint Instruction | |
| 11521 | |
| 11522 instruct safePoint_poll(iRegPdst poll) %{ | |
| 11523 match(SafePoint poll); | |
| 11524 predicate(LoadPollAddressFromThread); | |
| 11525 | |
| 11526 // It caused problems to add the effect that r0 is killed, but this | |
| 11527 // effect no longer needs to be mentioned, since r0 is not contained | |
| 11528 // in a reg_class. | |
| 11529 | |
| 11530 format %{ "LD R0, #0, $poll \t// Safepoint poll for GC" %} | |
| 11531 size(4); | |
| 11532 ins_encode( enc_poll(0x0, poll) ); | |
| 11533 ins_pipe(pipe_class_default); | |
| 11534 %} | |
| 11535 | |
| 11536 // Safepoint without per-thread support. Load address of page to poll | |
| 11537 // as constant. | |
| 11538 // Rscratch2RegP is R12. | |
| 11539 // LoadConPollAddr node is added in pd_post_matching_hook(). It must be | |
| 11540 // a seperate node so that the oop map is at the right location. | |
| 11541 instruct safePoint_poll_conPollAddr(rscratch2RegP poll) %{ | |
| 11542 match(SafePoint poll); | |
| 11543 predicate(!LoadPollAddressFromThread); | |
| 11544 | |
| 11545 // It caused problems to add the effect that r0 is killed, but this | |
| 11546 // effect no longer needs to be mentioned, since r0 is not contained | |
| 11547 // in a reg_class. | |
| 11548 | |
| 11549 format %{ "LD R12, addr of polling page\n\t" | |
| 11550 "LD R0, #0, R12 \t// Safepoint poll for GC" %} | |
| 11551 ins_encode( enc_poll(0x0, poll) ); | |
| 11552 ins_pipe(pipe_class_default); | |
| 11553 %} | |
| 11554 | |
| 11555 // ============================================================================ | |
| 11556 // Call Instructions | |
| 11557 | |
| 11558 // Call Java Static Instruction | |
| 11559 | |
| 11560 // Schedulable version of call static node. | |
| 11561 instruct CallStaticJavaDirect(method meth) %{ | |
| 11562 match(CallStaticJava); | |
| 11563 effect(USE meth); | |
| 11564 predicate(!((CallStaticJavaNode*)n)->is_method_handle_invoke()); | |
| 11565 ins_cost(CALL_COST); | |
| 11566 | |
| 11567 ins_num_consts(3 /* up to 3 patchable constants: inline cache, 2 call targets. */); | |
| 11568 | |
| 11569 format %{ "CALL,static $meth \t// ==> " %} | |
| 11570 size(4); | |
| 11571 ins_encode( enc_java_static_call(meth) ); | |
| 11572 ins_pipe(pipe_class_call); | |
| 11573 %} | |
| 11574 | |
| 11575 // Schedulable version of call static node. | |
| 11576 instruct CallStaticJavaDirectHandle(method meth) %{ | |
| 11577 match(CallStaticJava); | |
| 11578 effect(USE meth); | |
| 11579 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke()); | |
| 11580 ins_cost(CALL_COST); | |
| 11581 | |
| 11582 ins_num_consts(3 /* up to 3 patchable constants: inline cache, 2 call targets. */); | |
| 11583 | |
| 11584 format %{ "CALL,static $meth \t// ==> " %} | |
| 11585 ins_encode( enc_java_handle_call(meth) ); | |
| 11586 ins_pipe(pipe_class_call); | |
| 11587 %} | |
| 11588 | |
| 11589 // Call Java Dynamic Instruction | |
| 11590 | |
| 11591 // Used by postalloc expand of CallDynamicJavaDirectSchedEx (actual call). | |
| 11592 // Loading of IC was postalloc expanded. The nodes loading the IC are reachable | |
| 11593 // via fields ins_field_load_ic_hi_node and ins_field_load_ic_node. | |
| 11594 // The call destination must still be placed in the constant pool. | |
| 11595 instruct CallDynamicJavaDirectSched(method meth) %{ | |
| 11596 match(CallDynamicJava); // To get all the data fields we need ... | |
| 11597 effect(USE meth); | |
| 11598 predicate(false); // ... but never match. | |
| 11599 | |
| 11600 ins_field_load_ic_hi_node(loadConL_hiNode*); | |
| 11601 ins_field_load_ic_node(loadConLNode*); | |
| 11602 ins_num_consts(1 /* 1 patchable constant: call destination */); | |
| 11603 | |
| 11604 format %{ "BL \t// dynamic $meth ==> " %} | |
| 11605 size(4); | |
| 11606 ins_encode( enc_java_dynamic_call_sched(meth) ); | |
| 11607 ins_pipe(pipe_class_call); | |
| 11608 %} | |
| 11609 | |
| 11610 // Schedulable (i.e. postalloc expanded) version of call dynamic java. | |
| 11611 // We use postalloc expanded calls if we use inline caches | |
| 11612 // and do not update method data. | |
| 11613 // | |
| 11614 // This instruction has two constants: inline cache (IC) and call destination. | |
| 11615 // Loading the inline cache will be postalloc expanded, thus leaving a call with | |
| 11616 // one constant. | |
| 11617 instruct CallDynamicJavaDirectSched_Ex(method meth) %{ | |
| 11618 match(CallDynamicJava); | |
| 11619 effect(USE meth); | |
| 11620 predicate(UseInlineCaches); | |
| 11621 ins_cost(CALL_COST); | |
| 11622 | |
| 11623 ins_num_consts(2 /* 2 patchable constants: inline cache, call destination. */); | |
| 11624 | |
| 11625 format %{ "CALL,dynamic $meth \t// postalloc expanded" %} | |
| 11626 postalloc_expand( postalloc_expand_java_dynamic_call_sched(meth, constanttablebase) ); | |
| 11627 %} | |
| 11628 | |
| 11629 // Compound version of call dynamic java | |
| 11630 // We use postalloc expanded calls if we use inline caches | |
| 11631 // and do not update method data. | |
| 11632 instruct CallDynamicJavaDirect(method meth) %{ | |
| 11633 match(CallDynamicJava); | |
| 11634 effect(USE meth); | |
| 11635 predicate(!UseInlineCaches); | |
| 11636 ins_cost(CALL_COST); | |
| 11637 | |
| 11638 // Enc_java_to_runtime_call needs up to 4 constants (method data oop). | |
| 11639 ins_num_consts(4); | |
| 11640 | |
| 11641 format %{ "CALL,dynamic $meth \t// ==> " %} | |
| 11642 ins_encode( enc_java_dynamic_call(meth, constanttablebase) ); | |
| 11643 ins_pipe(pipe_class_call); | |
| 11644 %} | |
| 11645 | |
| 11646 // Call Runtime Instruction | |
| 11647 | |
| 11648 instruct CallRuntimeDirect(method meth) %{ | |
| 11649 match(CallRuntime); | |
| 11650 effect(USE meth); | |
| 11651 ins_cost(CALL_COST); | |
| 11652 | |
| 11653 // Enc_java_to_runtime_call needs up to 3 constants: call target, | |
| 11654 // env for callee, C-toc. | |
| 11655 ins_num_consts(3); | |
| 11656 | |
| 11657 format %{ "CALL,runtime" %} | |
| 11658 ins_encode( enc_java_to_runtime_call(meth) ); | |
| 11659 ins_pipe(pipe_class_call); | |
| 11660 %} | |
| 11661 | |
| 11662 // Call Leaf | |
| 11663 | |
| 11664 // Used by postalloc expand of CallLeafDirect_Ex (mtctr). | |
| 11665 instruct CallLeafDirect_mtctr(iRegLdst dst, iRegLsrc src) %{ | |
| 11666 effect(DEF dst, USE src); | |
| 11667 | |
| 11668 ins_num_consts(1); | |
| 11669 | |
| 11670 format %{ "MTCTR $src" %} | |
| 11671 size(4); | |
| 11672 ins_encode( enc_leaf_call_mtctr(src) ); | |
| 11673 ins_pipe(pipe_class_default); | |
| 11674 %} | |
| 11675 | |
| 11676 // Used by postalloc expand of CallLeafDirect_Ex (actual call). | |
| 11677 instruct CallLeafDirect(method meth) %{ | |
| 11678 match(CallLeaf); // To get the data all the data fields we need ... | |
| 11679 effect(USE meth); | |
| 11680 predicate(false); // but never match. | |
| 11681 | |
| 11682 format %{ "BCTRL \t// leaf call $meth ==> " %} | |
| 11683 size(4); | |
| 11684 ins_encode %{ | |
| 11685 // TODO: PPC port $archOpcode(ppc64Opcode_bctrl); | |
| 11686 __ bctrl(); | |
| 11687 %} | |
| 11688 ins_pipe(pipe_class_call); | |
| 11689 %} | |
| 11690 | |
| 11691 // postalloc expand of CallLeafDirect. | |
| 11692 // Load adress to call from TOC, then bl to it. | |
| 11693 instruct CallLeafDirect_Ex(method meth) %{ | |
| 11694 match(CallLeaf); | |
| 11695 effect(USE meth); | |
| 11696 ins_cost(CALL_COST); | |
| 11697 | |
| 11698 // Postalloc_expand_java_to_runtime_call needs up to 3 constants: call target, | |
| 11699 // env for callee, C-toc. | |
| 11700 ins_num_consts(3); | |
| 11701 | |
| 11702 format %{ "CALL,runtime leaf $meth \t// postalloc expanded" %} | |
| 11703 postalloc_expand( postalloc_expand_java_to_runtime_call(meth, constanttablebase) ); | |
| 11704 %} | |
| 11705 | |
| 11706 // Call runtime without safepoint - same as CallLeaf. | |
| 11707 // postalloc expand of CallLeafNoFPDirect. | |
| 11708 // Load adress to call from TOC, then bl to it. | |
| 11709 instruct CallLeafNoFPDirect_Ex(method meth) %{ | |
| 11710 match(CallLeafNoFP); | |
| 11711 effect(USE meth); | |
| 11712 ins_cost(CALL_COST); | |
| 11713 | |
| 11714 // Enc_java_to_runtime_call needs up to 3 constants: call target, | |
| 11715 // env for callee, C-toc. | |
| 11716 ins_num_consts(3); | |
| 11717 | |
| 11718 format %{ "CALL,runtime leaf nofp $meth \t// postalloc expanded" %} | |
| 11719 postalloc_expand( postalloc_expand_java_to_runtime_call(meth, constanttablebase) ); | |
| 11720 %} | |
| 11721 | |
| 11722 // Tail Call; Jump from runtime stub to Java code. | |
| 11723 // Also known as an 'interprocedural jump'. | |
| 11724 // Target of jump will eventually return to caller. | |
| 11725 // TailJump below removes the return address. | |
| 11726 instruct TailCalljmpInd(iRegPdstNoScratch jump_target, inline_cache_regP method_oop) %{ | |
| 11727 match(TailCall jump_target method_oop); | |
| 11728 ins_cost(CALL_COST); | |
| 11729 | |
| 11730 format %{ "MTCTR $jump_target \t// $method_oop holds method oop\n\t" | |
| 11731 "BCTR \t// tail call" %} | |
| 11732 size(8); | |
| 11733 ins_encode %{ | |
| 11734 // TODO: PPC port $archOpcode(ppc64Opcode_compound); | |
| 11735 __ mtctr($jump_target$$Register); | |
| 11736 __ bctr(); | |
| 11737 %} | |
| 11738 ins_pipe(pipe_class_call); | |
| 11739 %} | |
| 11740 | |
| 11741 // Return Instruction | |
| 11742 instruct Ret() %{ | |
| 11743 match(Return); | |
| 11744 format %{ "BLR \t// branch to link register" %} | |
| 11745 size(4); | |
| 11746 ins_encode %{ | |
| 11747 // TODO: PPC port $archOpcode(ppc64Opcode_blr); | |
| 11748 // LR is restored in MachEpilogNode. Just do the RET here. | |
| 11749 __ blr(); | |
| 11750 %} | |
| 11751 ins_pipe(pipe_class_default); | |
| 11752 %} | |
| 11753 | |
| 11754 // Tail Jump; remove the return address; jump to target. | |
| 11755 // TailCall above leaves the return address around. | |
| 11756 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2). | |
| 11757 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a | |
| 11758 // "restore" before this instruction (in Epilogue), we need to materialize it | |
| 11759 // in %i0. | |
| 11760 instruct tailjmpInd(iRegPdstNoScratch jump_target, rarg1RegP ex_oop) %{ | |
| 11761 match(TailJump jump_target ex_oop); | |
| 11762 ins_cost(CALL_COST); | |
| 11763 | |
| 11764 format %{ "LD R4_ARG2 = LR\n\t" | |
| 11765 "MTCTR $jump_target\n\t" | |
| 11766 "BCTR \t// TailJump, exception oop: $ex_oop" %} | |
| 11767 size(12); | |
| 11768 ins_encode %{ | |
| 11769 // TODO: PPC port $archOpcode(ppc64Opcode_compound); | |
| 11770 __ ld(R4_ARG2/* issuing pc */, _abi(lr), R1_SP); | |
| 11771 __ mtctr($jump_target$$Register); | |
| 11772 __ bctr(); | |
| 11773 %} | |
| 11774 ins_pipe(pipe_class_call); | |
| 11775 %} | |
| 11776 | |
| 11777 // Create exception oop: created by stack-crawling runtime code. | |
| 11778 // Created exception is now available to this handler, and is setup | |
| 11779 // just prior to jumping to this handler. No code emitted. | |
| 11780 instruct CreateException(rarg1RegP ex_oop) %{ | |
| 11781 match(Set ex_oop (CreateEx)); | |
| 11782 ins_cost(0); | |
| 11783 | |
| 11784 format %{ " -- \t// exception oop; no code emitted" %} | |
| 11785 size(0); | |
| 11786 ins_encode( /*empty*/ ); | |
| 11787 ins_pipe(pipe_class_default); | |
| 11788 %} | |
| 11789 | |
| 11790 // Rethrow exception: The exception oop will come in the first | |
| 11791 // argument position. Then JUMP (not call) to the rethrow stub code. | |
| 11792 instruct RethrowException() %{ | |
| 11793 match(Rethrow); | |
| 11794 ins_cost(CALL_COST); | |
| 11795 | |
| 11796 format %{ "Jmp rethrow_stub" %} | |
| 11797 ins_encode %{ | |
| 11798 // TODO: PPC port $archOpcode(ppc64Opcode_compound); | |
| 11799 cbuf.set_insts_mark(); | |
| 11800 __ b64_patchable((address)OptoRuntime::rethrow_stub(), relocInfo::runtime_call_type); | |
| 11801 %} | |
| 11802 ins_pipe(pipe_class_call); | |
| 11803 %} | |
| 11804 | |
| 11805 // Die now. | |
| 11806 instruct ShouldNotReachHere() %{ | |
| 11807 match(Halt); | |
| 11808 ins_cost(CALL_COST); | |
| 11809 | |
| 11810 format %{ "ShouldNotReachHere" %} | |
| 11811 size(4); | |
| 11812 ins_encode %{ | |
| 11813 // TODO: PPC port $archOpcode(ppc64Opcode_tdi); | |
| 11814 __ trap_should_not_reach_here(); | |
| 11815 %} | |
| 11816 ins_pipe(pipe_class_default); | |
| 11817 %} | |
| 11818 | |
| 11819 // This name is KNOWN by the ADLC and cannot be changed. The ADLC | |
| 11820 // forces a 'TypeRawPtr::BOTTOM' output type for this guy. | |
| 11821 // Get a DEF on threadRegP, no costs, no encoding, use | |
| 11822 // 'ins_should_rematerialize(true)' to avoid spilling. | |
| 11823 instruct tlsLoadP(threadRegP dst) %{ | |
| 11824 match(Set dst (ThreadLocal)); | |
| 11825 ins_cost(0); | |
| 11826 | |
| 11827 ins_should_rematerialize(true); | |
| 11828 | |
| 11829 format %{ " -- \t// $dst=Thread::current(), empty" %} | |
| 11830 size(0); | |
| 11831 ins_encode( /*empty*/ ); | |
| 11832 ins_pipe(pipe_class_empty); | |
| 11833 %} | |
| 11834 | |
| 11835 //---Some PPC specific nodes--------------------------------------------------- | |
| 11836 | |
| 11837 // Stop a group. | |
| 11838 instruct endGroup() %{ | |
| 11839 ins_cost(0); | |
| 11840 | |
| 11841 ins_is_nop(true); | |
| 11842 | |
| 11843 format %{ "End Bundle (ori r1, r1, 0)" %} | |
| 11844 size(4); | |
| 11845 ins_encode %{ | |
| 11846 // TODO: PPC port $archOpcode(ppc64Opcode_endgroup); | |
| 11847 __ endgroup(); | |
| 11848 %} | |
| 11849 ins_pipe(pipe_class_default); | |
| 11850 %} | |
| 11851 | |
| 11852 // Nop instructions | |
| 11853 | |
| 11854 instruct fxNop() %{ | |
| 11855 ins_cost(0); | |
| 11856 | |
| 11857 ins_is_nop(true); | |
| 11858 | |
| 11859 format %{ "fxNop" %} | |
| 11860 size(4); | |
| 11861 ins_encode %{ | |
| 11862 // TODO: PPC port $archOpcode(ppc64Opcode_fmr); | |
| 11863 __ nop(); | |
| 11864 %} | |
| 11865 ins_pipe(pipe_class_default); | |
| 11866 %} | |
| 11867 | |
| 11868 instruct fpNop0() %{ | |
| 11869 ins_cost(0); | |
| 11870 | |
| 11871 ins_is_nop(true); | |
| 11872 | |
| 11873 format %{ "fpNop0" %} | |
| 11874 size(4); | |
| 11875 ins_encode %{ | |
| 11876 // TODO: PPC port $archOpcode(ppc64Opcode_fmr); | |
| 11877 __ fpnop0(); | |
| 11878 %} | |
| 11879 ins_pipe(pipe_class_default); | |
| 11880 %} | |
| 11881 | |
| 11882 instruct fpNop1() %{ | |
| 11883 ins_cost(0); | |
| 11884 | |
| 11885 ins_is_nop(true); | |
| 11886 | |
| 11887 format %{ "fpNop1" %} | |
| 11888 size(4); | |
| 11889 ins_encode %{ | |
| 11890 // TODO: PPC port $archOpcode(ppc64Opcode_fmr); | |
| 11891 __ fpnop1(); | |
| 11892 %} | |
| 11893 ins_pipe(pipe_class_default); | |
| 11894 %} | |
| 11895 | |
| 11896 instruct brNop0() %{ | |
| 11897 ins_cost(0); | |
| 11898 size(4); | |
| 11899 format %{ "brNop0" %} | |
| 11900 ins_encode %{ | |
| 11901 // TODO: PPC port $archOpcode(ppc64Opcode_mcrf); | |
| 11902 __ brnop0(); | |
| 11903 %} | |
| 11904 ins_is_nop(true); | |
| 11905 ins_pipe(pipe_class_default); | |
| 11906 %} | |
| 11907 | |
| 11908 instruct brNop1() %{ | |
| 11909 ins_cost(0); | |
| 11910 | |
| 11911 ins_is_nop(true); | |
| 11912 | |
| 11913 format %{ "brNop1" %} | |
| 11914 size(4); | |
| 11915 ins_encode %{ | |
| 11916 // TODO: PPC port $archOpcode(ppc64Opcode_mcrf); | |
| 11917 __ brnop1(); | |
| 11918 %} | |
| 11919 ins_pipe(pipe_class_default); | |
| 11920 %} | |
| 11921 | |
| 11922 instruct brNop2() %{ | |
| 11923 ins_cost(0); | |
| 11924 | |
| 11925 ins_is_nop(true); | |
| 11926 | |
| 11927 format %{ "brNop2" %} | |
| 11928 size(4); | |
| 11929 ins_encode %{ | |
| 11930 // TODO: PPC port $archOpcode(ppc64Opcode_mcrf); | |
| 11931 __ brnop2(); | |
| 11932 %} | |
| 11933 ins_pipe(pipe_class_default); | |
| 11934 %} | |
| 11935 | |
| 11936 //----------PEEPHOLE RULES----------------------------------------------------- | |
| 11937 // These must follow all instruction definitions as they use the names | |
| 11938 // defined in the instructions definitions. | |
| 11939 // | |
| 11940 // peepmatch ( root_instr_name [preceeding_instruction]* ); | |
| 11941 // | |
| 11942 // peepconstraint %{ | |
| 11943 // (instruction_number.operand_name relational_op instruction_number.operand_name | |
| 11944 // [, ...] ); | |
| 11945 // // instruction numbers are zero-based using left to right order in peepmatch | |
| 11946 // | |
| 11947 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) ); | |
| 11948 // // provide an instruction_number.operand_name for each operand that appears | |
| 11949 // // in the replacement instruction's match rule | |
| 11950 // | |
| 11951 // ---------VM FLAGS--------------------------------------------------------- | |
| 11952 // | |
| 11953 // All peephole optimizations can be turned off using -XX:-OptoPeephole | |
| 11954 // | |
| 11955 // Each peephole rule is given an identifying number starting with zero and | |
| 11956 // increasing by one in the order seen by the parser. An individual peephole | |
| 11957 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=# | |
| 11958 // on the command-line. | |
| 11959 // | |
| 11960 // ---------CURRENT LIMITATIONS---------------------------------------------- | |
| 11961 // | |
| 11962 // Only match adjacent instructions in same basic block | |
| 11963 // Only equality constraints | |
| 11964 // Only constraints between operands, not (0.dest_reg == EAX_enc) | |
| 11965 // Only one replacement instruction | |
| 11966 // | |
| 11967 // ---------EXAMPLE---------------------------------------------------------- | |
| 11968 // | |
| 11969 // // pertinent parts of existing instructions in architecture description | |
| 11970 // instruct movI(eRegI dst, eRegI src) %{ | |
| 11971 // match(Set dst (CopyI src)); | |
| 11972 // %} | |
| 11973 // | |
| 11974 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{ | |
| 11975 // match(Set dst (AddI dst src)); | |
| 11976 // effect(KILL cr); | |
| 11977 // %} | |
| 11978 // | |
| 11979 // // Change (inc mov) to lea | |
| 11980 // peephole %{ | |
| 11981 // // increment preceeded by register-register move | |
| 11982 // peepmatch ( incI_eReg movI ); | |
| 11983 // // require that the destination register of the increment | |
| 11984 // // match the destination register of the move | |
| 11985 // peepconstraint ( 0.dst == 1.dst ); | |
| 11986 // // construct a replacement instruction that sets | |
| 11987 // // the destination to ( move's source register + one ) | |
| 11988 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); | |
| 11989 // %} | |
| 11990 // | |
| 11991 // Implementation no longer uses movX instructions since | |
| 11992 // machine-independent system no longer uses CopyX nodes. | |
| 11993 // | |
| 11994 // peephole %{ | |
| 11995 // peepmatch ( incI_eReg movI ); | |
| 11996 // peepconstraint ( 0.dst == 1.dst ); | |
| 11997 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); | |
| 11998 // %} | |
| 11999 // | |
| 12000 // peephole %{ | |
| 12001 // peepmatch ( decI_eReg movI ); | |
| 12002 // peepconstraint ( 0.dst == 1.dst ); | |
| 12003 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); | |
| 12004 // %} | |
| 12005 // | |
| 12006 // peephole %{ | |
| 12007 // peepmatch ( addI_eReg_imm movI ); | |
| 12008 // peepconstraint ( 0.dst == 1.dst ); | |
| 12009 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); | |
| 12010 // %} | |
| 12011 // | |
| 12012 // peephole %{ | |
| 12013 // peepmatch ( addP_eReg_imm movP ); | |
| 12014 // peepconstraint ( 0.dst == 1.dst ); | |
| 12015 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) ); | |
| 12016 // %} | |
| 12017 | |
| 12018 // // Change load of spilled value to only a spill | |
| 12019 // instruct storeI(memory mem, eRegI src) %{ | |
| 12020 // match(Set mem (StoreI mem src)); | |
| 12021 // %} | |
| 12022 // | |
| 12023 // instruct loadI(eRegI dst, memory mem) %{ | |
| 12024 // match(Set dst (LoadI mem)); | |
| 12025 // %} | |
| 12026 // | |
| 12027 peephole %{ | |
| 12028 peepmatch ( loadI storeI ); | |
| 12029 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem ); | |
| 12030 peepreplace ( storeI( 1.mem 1.mem 1.src ) ); | |
| 12031 %} | |
| 12032 | |
| 12033 peephole %{ | |
| 12034 peepmatch ( loadL storeL ); | |
| 12035 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem ); | |
| 12036 peepreplace ( storeL( 1.mem 1.mem 1.src ) ); | |
| 12037 %} | |
| 12038 | |
| 12039 peephole %{ | |
| 12040 peepmatch ( loadP storeP ); | |
| 12041 peepconstraint ( 1.src == 0.dst, 1.dst == 0.mem ); | |
| 12042 peepreplace ( storeP( 1.dst 1.dst 1.src ) ); | |
| 12043 %} | |
| 12044 | |
| 12045 //----------SMARTSPILL RULES--------------------------------------------------- | |
| 12046 // These must follow all instruction definitions as they use the names | |
| 12047 // defined in the instructions definitions. |