Mercurial > hg > truffle
annotate src/share/vm/opto/matcher.hpp @ 17716:cdb71841f4bc
6498581: ThreadInterruptTest3 produces wrong output on Windows
Summary: There is race condition between os::interrupt and os::is_interrupted on Windows. In JVM_Sleep(Thread.sleep), check if thread gets interrupted, it may see interrupted but not really interrupted so cause spurious waking up (early return from sleep). Fix by checking if interrupt event really gets set thus prevent false return. For intrinsic of _isInterrupted, on Windows, go fastpath only on bit not set.
Reviewed-by: acorn, kvn
Contributed-by: david.holmes@oracle.com, yumin.qi@oracle.com
| author | minqi |
|---|---|
| date | Wed, 26 Feb 2014 15:20:41 -0800 |
| parents | 04d32e7fad07 |
| children | abec000618bf 085b304a1cc5 752ba2e5f6d0 |
| rev | line source |
|---|---|
| 0 | 1 /* |
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2 * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. |
| 0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 4 * | |
| 5 * This code is free software; you can redistribute it and/or modify it | |
| 6 * under the terms of the GNU General Public License version 2 only, as | |
| 7 * published by the Free Software Foundation. | |
| 8 * | |
| 9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 * version 2 for more details (a copy is included in the LICENSE file that | |
| 13 * accompanied this code). | |
| 14 * | |
| 15 * You should have received a copy of the GNU General Public License version | |
| 16 * 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 * | |
|
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
| 0 | 22 * |
| 23 */ | |
| 24 | |
| 1972 | 25 #ifndef SHARE_VM_OPTO_MATCHER_HPP |
| 26 #define SHARE_VM_OPTO_MATCHER_HPP | |
| 27 | |
| 28 #include "libadt/vectset.hpp" | |
| 29 #include "memory/resourceArea.hpp" | |
| 30 #include "opto/node.hpp" | |
| 31 #include "opto/phaseX.hpp" | |
| 32 #include "opto/regmask.hpp" | |
| 33 | |
| 0 | 34 class Compile; |
| 35 class Node; | |
| 36 class MachNode; | |
| 37 class MachTypeNode; | |
| 38 class MachOper; | |
| 39 | |
| 40 //---------------------------Matcher------------------------------------------- | |
| 41 class Matcher : public PhaseTransform { | |
| 42 friend class VMStructs; | |
| 43 // Private arena of State objects | |
| 44 ResourceArea _states_arena; | |
| 45 | |
| 46 VectorSet _visited; // Visit bits | |
| 47 | |
| 48 // Used to control the Label pass | |
| 49 VectorSet _shared; // Shared Ideal Node | |
| 50 VectorSet _dontcare; // Nothing the matcher cares about | |
| 51 | |
| 52 // Private methods which perform the actual matching and reduction | |
| 53 // Walks the label tree, generating machine nodes | |
| 54 MachNode *ReduceInst( State *s, int rule, Node *&mem); | |
| 55 void ReduceInst_Chain_Rule( State *s, int rule, Node *&mem, MachNode *mach); | |
| 56 uint ReduceInst_Interior(State *s, int rule, Node *&mem, MachNode *mach, uint num_opnds); | |
| 57 void ReduceOper( State *s, int newrule, Node *&mem, MachNode *mach ); | |
| 58 | |
| 59 // If this node already matched using "rule", return the MachNode for it. | |
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60 MachNode* find_shared_node(Node* n, uint rule); |
| 0 | 61 |
| 62 // Convert a dense opcode number to an expanded rule number | |
| 63 const int *_reduceOp; | |
| 64 const int *_leftOp; | |
| 65 const int *_rightOp; | |
| 66 | |
| 67 // Map dense opcode number to info on when rule is swallowed constant. | |
| 68 const bool *_swallowed; | |
| 69 | |
| 70 // Map dense rule number to determine if this is an instruction chain rule | |
| 71 const uint _begin_inst_chain_rule; | |
| 72 const uint _end_inst_chain_rule; | |
| 73 | |
| 74 // We want to clone constants and possible CmpI-variants. | |
| 75 // If we do not clone CmpI, then we can have many instances of | |
| 76 // condition codes alive at once. This is OK on some chips and | |
| 77 // bad on others. Hence the machine-dependent table lookup. | |
| 78 const char *_must_clone; | |
| 79 | |
| 80 // Find shared Nodes, or Nodes that otherwise are Matcher roots | |
| 81 void find_shared( Node *n ); | |
| 82 | |
| 83 // Debug and profile information for nodes in old space: | |
| 84 GrowableArray<Node_Notes*>* _old_node_note_array; | |
| 85 | |
| 86 // Node labeling iterator for instruction selection | |
| 87 Node *Label_Root( const Node *n, State *svec, Node *control, const Node *mem ); | |
| 88 | |
| 89 Node *transform( Node *dummy ); | |
| 90 | |
| 12071 | 91 Node_List _projection_list; // For Machine nodes killing many values |
| 0 | 92 |
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93 Node_Array _shared_nodes; |
| 0 | 94 |
| 95 debug_only(Node_Array _old2new_map;) // Map roots of ideal-trees to machine-roots | |
| 222 | 96 debug_only(Node_Array _new2old_map;) // Maps machine nodes back to ideal |
| 0 | 97 |
| 98 // Accessors for the inherited field PhaseTransform::_nodes: | |
| 99 void grow_new_node_array(uint idx_limit) { | |
| 100 _nodes.map(idx_limit-1, NULL); | |
| 101 } | |
| 102 bool has_new_node(const Node* n) const { | |
| 103 return _nodes.at(n->_idx) != NULL; | |
| 104 } | |
| 105 Node* new_node(const Node* n) const { | |
| 106 assert(has_new_node(n), "set before get"); | |
| 107 return _nodes.at(n->_idx); | |
| 108 } | |
| 109 void set_new_node(const Node* n, Node *nn) { | |
| 110 assert(!has_new_node(n), "set only once"); | |
| 111 _nodes.map(n->_idx, nn); | |
| 112 } | |
| 113 | |
| 114 #ifdef ASSERT | |
| 115 // Make sure only new nodes are reachable from this node | |
| 116 void verify_new_nodes_only(Node* root); | |
|
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117 |
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118 Node* _mem_node; // Ideal memory node consumed by mach node |
| 0 | 119 #endif |
| 120 | |
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121 // Mach node for ConP #NULL |
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122 MachNode* _mach_null; |
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123 |
| 0 | 124 public: |
| 125 int LabelRootDepth; | |
| 126 // Convert ideal machine register to a register mask for spill-loads | |
| 127 static const RegMask *idealreg2regmask[]; | |
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128 RegMask *idealreg2spillmask [_last_machine_leaf]; |
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129 RegMask *idealreg2debugmask [_last_machine_leaf]; |
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130 RegMask *idealreg2mhdebugmask[_last_machine_leaf]; |
| 0 | 131 void init_spill_mask( Node *ret ); |
| 132 // Convert machine register number to register mask | |
| 133 static uint mreg2regmask_max; | |
| 134 static RegMask mreg2regmask[]; | |
| 135 static RegMask STACK_ONLY_mask; | |
| 136 | |
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137 MachNode* mach_null() const { return _mach_null; } |
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138 |
| 0 | 139 bool is_shared( Node *n ) { return _shared.test(n->_idx) != 0; } |
| 140 void set_shared( Node *n ) { _shared.set(n->_idx); } | |
| 141 bool is_visited( Node *n ) { return _visited.test(n->_idx) != 0; } | |
| 142 void set_visited( Node *n ) { _visited.set(n->_idx); } | |
| 143 bool is_dontcare( Node *n ) { return _dontcare.test(n->_idx) != 0; } | |
| 144 void set_dontcare( Node *n ) { _dontcare.set(n->_idx); } | |
| 145 | |
| 146 // Mode bit to tell DFA and expand rules whether we are running after | |
| 147 // (or during) register selection. Usually, the matcher runs before, | |
| 148 // but it will also get called to generate post-allocation spill code. | |
| 149 // In this situation, it is a deadly error to attempt to allocate more | |
| 150 // temporary registers. | |
| 151 bool _allocation_started; | |
| 152 | |
| 153 // Machine register names | |
| 154 static const char *regName[]; | |
| 155 // Machine register encodings | |
| 156 static const unsigned char _regEncode[]; | |
| 157 // Machine Node names | |
| 158 const char **_ruleName; | |
| 159 // Rules that are cheaper to rematerialize than to spill | |
| 160 static const uint _begin_rematerialize; | |
| 161 static const uint _end_rematerialize; | |
| 162 | |
| 163 // An array of chars, from 0 to _last_Mach_Reg. | |
| 164 // No Save = 'N' (for register windows) | |
| 165 // Save on Entry = 'E' | |
| 166 // Save on Call = 'C' | |
| 167 // Always Save = 'A' (same as SOE + SOC) | |
| 168 const char *_register_save_policy; | |
| 169 const char *_c_reg_save_policy; | |
| 170 // Convert a machine register to a machine register type, so-as to | |
| 171 // properly match spill code. | |
| 172 const int *_register_save_type; | |
| 173 // Maps from machine register to boolean; true if machine register can | |
| 174 // be holding a call argument in some signature. | |
| 175 static bool can_be_java_arg( int reg ); | |
| 176 // Maps from machine register to boolean; true if machine register holds | |
| 177 // a spillable argument. | |
| 178 static bool is_spillable_arg( int reg ); | |
| 179 | |
| 180 // List of IfFalse or IfTrue Nodes that indicate a taken null test. | |
| 181 // List is valid in the post-matching space. | |
| 182 Node_List _null_check_tests; | |
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183 void collect_null_checks( Node *proj, Node *orig_proj ); |
| 0 | 184 void validate_null_checks( ); |
| 185 | |
| 12071 | 186 Matcher(); |
| 187 | |
| 188 // Get a projection node at position pos | |
| 189 Node* get_projection(uint pos) { | |
| 190 return _projection_list[pos]; | |
| 191 } | |
| 192 | |
| 193 // Push a projection node onto the projection list | |
| 194 void push_projection(Node* node) { | |
| 195 _projection_list.push(node); | |
| 196 } | |
| 197 | |
| 198 Node* pop_projection() { | |
| 199 return _projection_list.pop(); | |
| 200 } | |
| 201 | |
| 202 // Number of nodes in the projection list | |
| 203 uint number_of_projections() const { | |
| 204 return _projection_list.size(); | |
| 205 } | |
| 0 | 206 |
| 207 // Select instructions for entire method | |
| 12071 | 208 void match(); |
| 209 | |
| 0 | 210 // Helper for match |
| 211 OptoReg::Name warp_incoming_stk_arg( VMReg reg ); | |
| 212 | |
| 213 // Transform, then walk. Does implicit DCE while walking. | |
| 214 // Name changed from "transform" to avoid it being virtual. | |
| 215 Node *xform( Node *old_space_node, int Nodes ); | |
| 216 | |
| 217 // Match a single Ideal Node - turn it into a 1-Node tree; Label & Reduce. | |
| 218 MachNode *match_tree( const Node *n ); | |
| 219 MachNode *match_sfpt( SafePointNode *sfpt ); | |
| 220 // Helper for match_sfpt | |
| 221 OptoReg::Name warp_outgoing_stk_arg( VMReg reg, OptoReg::Name begin_out_arg_area, OptoReg::Name &out_arg_limit_per_call ); | |
| 222 | |
| 223 // Initialize first stack mask and related masks. | |
| 224 void init_first_stack_mask(); | |
| 225 | |
| 226 // If we should save-on-entry this register | |
| 227 bool is_save_on_entry( int reg ); | |
| 228 | |
| 229 // Fixup the save-on-entry registers | |
| 230 void Fixup_Save_On_Entry( ); | |
| 231 | |
| 232 // --- Frame handling --- | |
| 233 | |
| 234 // Register number of the stack slot corresponding to the incoming SP. | |
| 235 // Per the Big Picture in the AD file, it is: | |
| 236 // SharedInfo::stack0 + locks + in_preserve_stack_slots + pad2. | |
| 237 OptoReg::Name _old_SP; | |
| 238 | |
| 239 // Register number of the stack slot corresponding to the highest incoming | |
| 240 // argument on the stack. Per the Big Picture in the AD file, it is: | |
| 241 // _old_SP + out_preserve_stack_slots + incoming argument size. | |
| 242 OptoReg::Name _in_arg_limit; | |
| 243 | |
| 244 // Register number of the stack slot corresponding to the new SP. | |
| 245 // Per the Big Picture in the AD file, it is: | |
| 246 // _in_arg_limit + pad0 | |
| 247 OptoReg::Name _new_SP; | |
| 248 | |
| 249 // Register number of the stack slot corresponding to the highest outgoing | |
| 250 // argument on the stack. Per the Big Picture in the AD file, it is: | |
| 251 // _new_SP + max outgoing arguments of all calls | |
| 252 OptoReg::Name _out_arg_limit; | |
| 253 | |
| 254 OptoRegPair *_parm_regs; // Array of machine registers per argument | |
| 255 RegMask *_calling_convention_mask; // Array of RegMasks per argument | |
| 256 | |
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257 // Does matcher have a match rule for this ideal node? |
| 0 | 258 static const bool has_match_rule(int opcode); |
| 259 static const bool _hasMatchRule[_last_opcode]; | |
| 260 | |
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261 // Does matcher have a match rule for this ideal node and is the |
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262 // predicate (if there is one) true? |
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263 // NOTE: If this function is used more commonly in the future, ADLC |
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264 // should generate this one. |
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265 static const bool match_rule_supported(int opcode); |
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266 |
| 0 | 267 // Used to determine if we have fast l2f conversion |
| 268 // USII has it, USIII doesn't | |
| 269 static const bool convL2FSupported(void); | |
| 270 | |
| 271 // Vector width in bytes | |
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272 static const int vector_width_in_bytes(BasicType bt); |
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273 |
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274 // Limits on vector size (number of elements). |
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275 static const int max_vector_size(const BasicType bt); |
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276 static const int min_vector_size(const BasicType bt); |
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277 static const bool vector_size_supported(const BasicType bt, int size) { |
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278 return (Matcher::max_vector_size(bt) >= size && |
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279 Matcher::min_vector_size(bt) <= size); |
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280 } |
| 0 | 281 |
| 282 // Vector ideal reg | |
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283 static const int vector_ideal_reg(int len); |
| 6823 | 284 static const int vector_shift_count_ideal_reg(int len); |
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285 |
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286 // CPU supports misaligned vectors store/load. |
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287 static const bool misaligned_vectors_ok(); |
| 0 | 288 |
| 17670 | 289 // Should original key array reference be passed to AES stubs |
| 290 static const bool pass_original_key_for_aes(); | |
| 291 | |
| 0 | 292 // Used to determine a "low complexity" 64-bit constant. (Zero is simple.) |
| 293 // The standard of comparison is one (StoreL ConL) vs. two (StoreI ConI). | |
| 294 // Depends on the details of 64-bit constant generation on the CPU. | |
| 295 static const bool isSimpleConstant64(jlong con); | |
| 296 | |
| 297 // These calls are all generated by the ADLC | |
| 298 | |
| 299 // TRUE - grows up, FALSE - grows down (Intel) | |
| 300 virtual bool stack_direction() const; | |
| 301 | |
| 302 // Java-Java calling convention | |
| 303 // (what you use when Java calls Java) | |
| 304 | |
| 305 // Alignment of stack in bytes, standard Intel word alignment is 4. | |
| 306 // Sparc probably wants at least double-word (8). | |
| 307 static uint stack_alignment_in_bytes(); | |
| 308 // Alignment of stack, measured in stack slots. | |
| 309 // The size of stack slots is defined by VMRegImpl::stack_slot_size. | |
| 310 static uint stack_alignment_in_slots() { | |
| 311 return stack_alignment_in_bytes() / (VMRegImpl::stack_slot_size); | |
| 312 } | |
| 313 | |
| 314 // Array mapping arguments to registers. Argument 0 is usually the 'this' | |
| 315 // pointer. Registers can include stack-slots and regular registers. | |
| 316 static void calling_convention( BasicType *, VMRegPair *, uint len, bool is_outgoing ); | |
| 317 | |
| 318 // Convert a sig into a calling convention register layout | |
| 319 // and find interesting things about it. | |
| 320 static OptoReg::Name find_receiver( bool is_outgoing ); | |
| 321 // Return address register. On Intel it is a stack-slot. On PowerPC | |
| 322 // it is the Link register. On Sparc it is r31? | |
| 323 virtual OptoReg::Name return_addr() const; | |
| 324 RegMask _return_addr_mask; | |
| 325 // Return value register. On Intel it is EAX. On Sparc i0/o0. | |
| 326 static OptoRegPair return_value(int ideal_reg, bool is_outgoing); | |
| 327 static OptoRegPair c_return_value(int ideal_reg, bool is_outgoing); | |
| 328 RegMask _return_value_mask; | |
| 329 // Inline Cache Register | |
| 330 static OptoReg::Name inline_cache_reg(); | |
| 331 static int inline_cache_reg_encode(); | |
| 332 | |
| 333 // Register for DIVI projection of divmodI | |
| 334 static RegMask divI_proj_mask(); | |
| 335 // Register for MODI projection of divmodI | |
| 336 static RegMask modI_proj_mask(); | |
| 337 | |
| 338 // Register for DIVL projection of divmodL | |
| 339 static RegMask divL_proj_mask(); | |
| 340 // Register for MODL projection of divmodL | |
| 341 static RegMask modL_proj_mask(); | |
| 342 | |
| 12323 | 343 static const RegMask mathExactI_result_proj_mask(); |
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344 static const RegMask mathExactL_result_proj_mask(); |
| 12323 | 345 static const RegMask mathExactI_flags_proj_mask(); |
| 346 | |
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347 // Use hardware DIV instruction when it is faster than |
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348 // a code which use multiply for division by constant. |
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349 static bool use_asm_for_ldiv_by_con( jlong divisor ); |
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350 |
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351 static const RegMask method_handle_invoke_SP_save_mask(); |
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352 |
| 0 | 353 // Java-Interpreter calling convention |
| 354 // (what you use when calling between compiled-Java and Interpreted-Java | |
| 355 | |
| 356 // Number of callee-save + always-save registers | |
| 357 // Ignores frame pointer and "special" registers | |
| 358 static int number_of_saved_registers(); | |
| 359 | |
| 360 // The Method-klass-holder may be passed in the inline_cache_reg | |
| 361 // and then expanded into the inline_cache_reg and a method_oop register | |
| 362 | |
| 363 static OptoReg::Name interpreter_method_oop_reg(); | |
| 364 static int interpreter_method_oop_reg_encode(); | |
| 365 | |
| 366 static OptoReg::Name compiler_method_oop_reg(); | |
| 367 static const RegMask &compiler_method_oop_reg_mask(); | |
| 368 static int compiler_method_oop_reg_encode(); | |
| 369 | |
| 370 // Interpreter's Frame Pointer Register | |
| 371 static OptoReg::Name interpreter_frame_pointer_reg(); | |
| 372 | |
| 373 // Java-Native calling convention | |
| 374 // (what you use when intercalling between Java and C++ code) | |
| 375 | |
| 376 // Array mapping arguments to registers. Argument 0 is usually the 'this' | |
| 377 // pointer. Registers can include stack-slots and regular registers. | |
| 378 static void c_calling_convention( BasicType*, VMRegPair *, uint ); | |
| 379 // Frame pointer. The frame pointer is kept at the base of the stack | |
| 380 // and so is probably the stack pointer for most machines. On Intel | |
| 381 // it is ESP. On the PowerPC it is R1. On Sparc it is SP. | |
| 382 OptoReg::Name c_frame_pointer() const; | |
| 383 static RegMask c_frame_ptr_mask; | |
| 384 | |
| 385 // !!!!! Special stuff for building ScopeDescs | |
| 386 virtual int regnum_to_fpu_offset(int regnum); | |
| 387 | |
| 388 // Is this branch offset small enough to be addressed by a short branch? | |
| 3851 | 389 bool is_short_branch_offset(int rule, int br_size, int offset); |
| 0 | 390 |
| 391 // Optional scaling for the parameter to the ClearArray/CopyArray node. | |
| 392 static const bool init_array_count_is_in_bytes; | |
| 393 | |
| 394 // Threshold small size (in bytes) for a ClearArray/CopyArray node. | |
| 395 // Anything this size or smaller may get converted to discrete scalar stores. | |
| 396 static const int init_array_short_size; | |
| 397 | |
| 4047 | 398 // Some hardware needs 2 CMOV's for longs. |
| 399 static const int long_cmove_cost(); | |
| 400 | |
| 401 // Some hardware have expensive CMOV for float and double. | |
| 402 static const int float_cmove_cost(); | |
| 403 | |
| 0 | 404 // Should the Matcher clone shifts on addressing modes, expecting them to |
| 405 // be subsumed into complex addressing expressions or compute them into | |
| 406 // registers? True for Intel but false for most RISCs | |
| 407 static const bool clone_shift_expressions; | |
| 408 | |
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409 static bool narrow_oop_use_complex_address(); |
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410 static bool narrow_klass_use_complex_address(); |
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411 |
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412 // Generate implicit null check for narrow oops if it can fold |
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413 // into address expression (x64). |
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414 // |
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415 // [R12 + narrow_oop_reg<<3 + offset] // fold into address expression |
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416 // NullCheck narrow_oop_reg |
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417 // |
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418 // When narrow oops can't fold into address expression (Sparc) and |
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419 // base is not null use decode_not_null and normal implicit null check. |
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420 // Note, decode_not_null node can be used here since it is referenced |
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421 // only on non null path but it requires special handling, see |
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422 // collect_null_checks(): |
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423 // |
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424 // decode_not_null narrow_oop_reg, oop_reg // 'shift' and 'add base' |
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425 // [oop_reg + offset] |
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426 // NullCheck oop_reg |
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427 // |
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428 // With Zero base and when narrow oops can not fold into address |
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429 // expression use normal implicit null check since only shift |
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430 // is needed to decode narrow oop. |
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431 // |
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432 // decode narrow_oop_reg, oop_reg // only 'shift' |
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433 // [oop_reg + offset] |
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434 // NullCheck oop_reg |
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435 // |
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436 inline static bool gen_narrow_oop_implicit_null_checks() { |
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437 return Universe::narrow_oop_use_implicit_null_checks() && |
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438 (narrow_oop_use_complex_address() || |
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439 Universe::narrow_oop_base() != NULL); |
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440 } |
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441 |
| 0 | 442 // Is it better to copy float constants, or load them directly from memory? |
| 443 // Intel can load a float constant from a direct address, requiring no | |
| 444 // extra registers. Most RISCs will have to materialize an address into a | |
| 445 // register first, so they may as well materialize the constant immediately. | |
| 446 static const bool rematerialize_float_constants; | |
| 447 | |
| 448 // If CPU can load and store mis-aligned doubles directly then no fixup is | |
| 449 // needed. Else we split the double into 2 integer pieces and move it | |
| 450 // piece-by-piece. Only happens when passing doubles into C code or when | |
| 451 // calling i2c adapters as the Java calling convention forces doubles to be | |
| 452 // aligned. | |
| 453 static const bool misaligned_doubles_ok; | |
| 454 | |
| 455 // Perform a platform dependent implicit null fixup. This is needed | |
| 456 // on windows95 to take care of some unusual register constraints. | |
| 457 void pd_implicit_null_fixup(MachNode *load, uint idx); | |
| 458 | |
| 459 // Advertise here if the CPU requires explicit rounding operations | |
| 460 // to implement the UseStrictFP mode. | |
| 461 static const bool strict_fp_requires_explicit_rounding; | |
| 462 | |
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463 // Are floats conerted to double when stored to stack during deoptimization? |
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464 static bool float_in_double(); |
| 0 | 465 // Do ints take an entire long register or just half? |
| 466 static const bool int_in_long; | |
| 467 | |
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468 // Do the processor's shift instructions only use the low 5/6 bits |
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469 // of the count for 32/64 bit ints? If not we need to do the masking |
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470 // ourselves. |
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471 static const bool need_masked_shift_count; |
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472 |
| 0 | 473 // This routine is run whenever a graph fails to match. |
| 474 // If it returns, the compiler should bailout to interpreter without error. | |
| 475 // In non-product mode, SoftMatchFailure is false to detect non-canonical | |
| 476 // graphs. Print a message and exit. | |
| 477 static void soft_match_failure() { | |
| 478 if( SoftMatchFailure ) return; | |
| 479 else { fatal("SoftMatchFailure is not allowed except in product"); } | |
| 480 } | |
| 481 | |
| 482 // Check for a following volatile memory barrier without an | |
| 483 // intervening load and thus we don't need a barrier here. We | |
| 484 // retain the Node to act as a compiler ordering barrier. | |
| 485 static bool post_store_load_barrier(const Node* mb); | |
| 486 | |
| 487 | |
| 488 #ifdef ASSERT | |
| 489 void dump_old2new_map(); // machine-independent to machine-dependent | |
| 222 | 490 |
| 491 Node* find_old_node(Node* new_node) { | |
| 492 return _new2old_map[new_node->_idx]; | |
| 493 } | |
| 0 | 494 #endif |
| 495 }; | |
| 1972 | 496 |
| 497 #endif // SHARE_VM_OPTO_MATCHER_HPP |