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0
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1 /*
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196
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2 * Copyright 1997-2008 Sun Microsystems, Inc. All Rights Reserved.
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0
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3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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4 *
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5 * This code is free software; you can redistribute it and/or modify it
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6 * under the terms of the GNU General Public License version 2 only, as
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7 * published by the Free Software Foundation.
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8 *
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9 * This code is distributed in the hope that it will be useful, but WITHOUT
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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12 * version 2 for more details (a copy is included in the LICENSE file that
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13 * accompanied this code).
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14 *
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15 * You should have received a copy of the GNU General Public License version
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16 * 2 along with this work; if not, write to the Free Software Foundation,
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17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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18 *
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19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
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20 * CA 95054 USA or visit www.sun.com if you need additional information or
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21 * have any questions.
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22 *
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23 */
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24
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25 # include "incls/_precompiled.incl"
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26 # include "incls/_vm_version_x86_32.cpp.incl"
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27
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28
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29 int VM_Version::_cpu;
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30 int VM_Version::_model;
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31 int VM_Version::_stepping;
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32 int VM_Version::_cpuFeatures;
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33 const char* VM_Version::_features_str = "";
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34 VM_Version::CpuidInfo VM_Version::_cpuid_info = { 0, };
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35
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36 static BufferBlob* stub_blob;
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37 static const int stub_size = 300;
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38
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39 extern "C" {
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40 typedef void (*getPsrInfo_stub_t)(void*);
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41 }
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42 static getPsrInfo_stub_t getPsrInfo_stub = NULL;
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43
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44
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45 class VM_Version_StubGenerator: public StubCodeGenerator {
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46 public:
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47
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48 VM_Version_StubGenerator(CodeBuffer *c) : StubCodeGenerator(c) {}
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49
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50 address generate_getPsrInfo() {
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51 // Flags to test CPU type.
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52 const uint32_t EFL_AC = 0x40000;
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53 const uint32_t EFL_ID = 0x200000;
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54 // Values for when we don't have a CPUID instruction.
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55 const int CPU_FAMILY_SHIFT = 8;
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56 const uint32_t CPU_FAMILY_386 = (3 << CPU_FAMILY_SHIFT);
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57 const uint32_t CPU_FAMILY_486 = (4 << CPU_FAMILY_SHIFT);
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58
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59 Label detect_486, cpu486, detect_586, std_cpuid1;
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60 Label ext_cpuid1, ext_cpuid5, done;
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61
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62 StubCodeMark mark(this, "VM_Version", "getPsrInfo_stub");
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63 # define __ _masm->
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64
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65 address start = __ pc();
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66
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67 //
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68 // void getPsrInfo(VM_Version::CpuidInfo* cpuid_info);
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69 //
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70 __ pushl(rbp);
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71 __ movl(rbp, Address(rsp, 8)); // cpuid_info address
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72 __ pushl(rbx);
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73 __ pushl(rsi);
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74 __ pushfd(); // preserve rbx, and flags
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75 __ popl(rax);
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76 __ pushl(rax);
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77 __ movl(rcx, rax);
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78 //
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79 // if we are unable to change the AC flag, we have a 386
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80 //
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81 __ xorl(rax, EFL_AC);
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82 __ pushl(rax);
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83 __ popfd();
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84 __ pushfd();
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85 __ popl(rax);
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86 __ cmpl(rax, rcx);
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87 __ jccb(Assembler::notEqual, detect_486);
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88
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89 __ movl(rax, CPU_FAMILY_386);
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90 __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax);
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91 __ jmp(done);
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92
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93 //
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94 // If we are unable to change the ID flag, we have a 486 which does
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95 // not support the "cpuid" instruction.
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96 //
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97 __ bind(detect_486);
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98 __ movl(rax, rcx);
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99 __ xorl(rax, EFL_ID);
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100 __ pushl(rax);
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101 __ popfd();
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102 __ pushfd();
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103 __ popl(rax);
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104 __ cmpl(rcx, rax);
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105 __ jccb(Assembler::notEqual, detect_586);
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106
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107 __ bind(cpu486);
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108 __ movl(rax, CPU_FAMILY_486);
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109 __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax);
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110 __ jmp(done);
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111
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112 //
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113 // at this point, we have a chip which supports the "cpuid" instruction
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114 //
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115 __ bind(detect_586);
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116 __ xorl(rax, rax);
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117 __ cpuid();
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118 __ orl(rax, rax);
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119 __ jcc(Assembler::equal, cpu486); // if cpuid doesn't support an input
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120 // value of at least 1, we give up and
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121 // assume a 486
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122 __ leal(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset())));
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123 __ movl(Address(rsi, 0), rax);
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124 __ movl(Address(rsi, 4), rbx);
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125 __ movl(Address(rsi, 8), rcx);
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126 __ movl(Address(rsi,12), rdx);
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127
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128 __ cmpl(rax, 3); // Is cpuid(0x4) supported?
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129 __ jccb(Assembler::belowEqual, std_cpuid1);
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130
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131 //
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132 // cpuid(0x4) Deterministic cache params
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133 //
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134 __ movl(rax, 4); // and rcx already set to 0x0
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135 __ xorl(rcx, rcx);
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136 __ cpuid();
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137 __ pushl(rax);
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138 __ andl(rax, 0x1f); // Determine if valid cache parameters used
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139 __ orl(rax, rax); // rax,[4:0] == 0 indicates invalid cache
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140 __ popl(rax);
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141 __ jccb(Assembler::equal, std_cpuid1);
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142
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143 __ leal(rsi, Address(rbp, in_bytes(VM_Version::dcp_cpuid4_offset())));
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144 __ movl(Address(rsi, 0), rax);
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145 __ movl(Address(rsi, 4), rbx);
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146 __ movl(Address(rsi, 8), rcx);
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147 __ movl(Address(rsi,12), rdx);
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148
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149 //
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150 // Standard cpuid(0x1)
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151 //
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152 __ bind(std_cpuid1);
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153 __ movl(rax, 1);
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154 __ cpuid();
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155 __ leal(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
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156 __ movl(Address(rsi, 0), rax);
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157 __ movl(Address(rsi, 4), rbx);
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158 __ movl(Address(rsi, 8), rcx);
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159 __ movl(Address(rsi,12), rdx);
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160
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161 __ movl(rax, 0x80000000);
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162 __ cpuid();
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163 __ cmpl(rax, 0x80000000); // Is cpuid(0x80000001) supported?
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164 __ jcc(Assembler::belowEqual, done);
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165 __ cmpl(rax, 0x80000004); // Is cpuid(0x80000005) supported?
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166 __ jccb(Assembler::belowEqual, ext_cpuid1);
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167 __ cmpl(rax, 0x80000007); // Is cpuid(0x80000008) supported?
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168 __ jccb(Assembler::belowEqual, ext_cpuid5);
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169 //
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170 // Extended cpuid(0x80000008)
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171 //
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172 __ movl(rax, 0x80000008);
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173 __ cpuid();
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174 __ leal(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid8_offset())));
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175 __ movl(Address(rsi, 0), rax);
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176 __ movl(Address(rsi, 4), rbx);
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177 __ movl(Address(rsi, 8), rcx);
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178 __ movl(Address(rsi,12), rdx);
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179
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180 //
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181 // Extended cpuid(0x80000005)
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182 //
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183 __ bind(ext_cpuid5);
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184 __ movl(rax, 0x80000005);
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185 __ cpuid();
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186 __ leal(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid5_offset())));
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187 __ movl(Address(rsi, 0), rax);
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188 __ movl(Address(rsi, 4), rbx);
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189 __ movl(Address(rsi, 8), rcx);
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190 __ movl(Address(rsi,12), rdx);
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191
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192 //
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193 // Extended cpuid(0x80000001)
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194 //
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195 __ bind(ext_cpuid1);
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196 __ movl(rax, 0x80000001);
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197 __ cpuid();
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198 __ leal(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid1_offset())));
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199 __ movl(Address(rsi, 0), rax);
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200 __ movl(Address(rsi, 4), rbx);
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201 __ movl(Address(rsi, 8), rcx);
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202 __ movl(Address(rsi,12), rdx);
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203
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204 //
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205 // return
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206 //
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207 __ bind(done);
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208 __ popfd();
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209 __ popl(rsi);
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210 __ popl(rbx);
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211 __ popl(rbp);
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212 __ ret(0);
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213
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214 # undef __
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215
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216 return start;
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217 };
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218 };
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219
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220
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221 void VM_Version::get_processor_features() {
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222
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223 _cpu = 4; // 486 by default
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224 _model = 0;
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225 _stepping = 0;
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226 _cpuFeatures = 0;
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227 _logical_processors_per_package = 1;
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228 if (!Use486InstrsOnly) {
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229 // Get raw processor info
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230 getPsrInfo_stub(&_cpuid_info);
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231 assert_is_initialized();
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232 _cpu = extended_cpu_family();
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233 _model = extended_cpu_model();
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234 _stepping = cpu_stepping();
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235 if (cpu_family() > 4) { // it supports CPUID
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236 _cpuFeatures = feature_flags();
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237 // Logical processors are only available on P4s and above,
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238 // and only if hyperthreading is available.
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239 _logical_processors_per_package = logical_processor_count();
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240 }
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241 }
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242 _supports_cx8 = supports_cmpxchg8();
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243 // if the OS doesn't support SSE, we can't use this feature even if the HW does
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244 if( !os::supports_sse())
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245 _cpuFeatures &= ~(CPU_SSE|CPU_SSE2|CPU_SSE3|CPU_SSSE3|CPU_SSE4|CPU_SSE4A);
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246 if (UseSSE < 4)
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247 _cpuFeatures &= ~CPU_SSE4;
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248 if (UseSSE < 3) {
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249 _cpuFeatures &= ~CPU_SSE3;
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250 _cpuFeatures &= ~CPU_SSSE3;
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251 _cpuFeatures &= ~CPU_SSE4A;
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252 }
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253 if (UseSSE < 2)
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254 _cpuFeatures &= ~CPU_SSE2;
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255 if (UseSSE < 1)
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256 _cpuFeatures &= ~CPU_SSE;
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257
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258 if (logical_processors_per_package() == 1) {
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259 // HT processor could be installed on a system which doesn't support HT.
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260 _cpuFeatures &= ~CPU_HT;
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261 }
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262
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263 char buf[256];
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264 jio_snprintf(buf, sizeof(buf), "(%u cores per cpu, %u threads per core) family %d model %d stepping %d%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
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265 cores_per_cpu(), threads_per_core(),
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266 cpu_family(), _model, _stepping,
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267 (supports_cmov() ? ", cmov" : ""),
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268 (supports_cmpxchg8() ? ", cx8" : ""),
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269 (supports_fxsr() ? ", fxsr" : ""),
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270 (supports_mmx() ? ", mmx" : ""),
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271 (supports_sse() ? ", sse" : ""),
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272 (supports_sse2() ? ", sse2" : ""),
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273 (supports_sse3() ? ", sse3" : ""),
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274 (supports_ssse3()? ", ssse3": ""),
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275 (supports_sse4() ? ", sse4" : ""),
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276 (supports_mmx_ext() ? ", mmxext" : ""),
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277 (supports_3dnow() ? ", 3dnow" : ""),
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278 (supports_3dnow2() ? ", 3dnowext" : ""),
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279 (supports_sse4a() ? ", sse4a": ""),
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280 (supports_ht() ? ", ht": ""));
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281 _features_str = strdup(buf);
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282
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283 // UseSSE is set to the smaller of what hardware supports and what
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284 // the command line requires. I.e., you cannot set UseSSE to 2 on
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285 // older Pentiums which do not support it.
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286 if( UseSSE > 4 ) UseSSE=4;
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287 if( UseSSE < 0 ) UseSSE=0;
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288 if( !supports_sse4() ) // Drop to 3 if no SSE4 support
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289 UseSSE = MIN2((intx)3,UseSSE);
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290 if( !supports_sse3() ) // Drop to 2 if no SSE3 support
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291 UseSSE = MIN2((intx)2,UseSSE);
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292 if( !supports_sse2() ) // Drop to 1 if no SSE2 support
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293 UseSSE = MIN2((intx)1,UseSSE);
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294 if( !supports_sse () ) // Drop to 0 if no SSE support
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295 UseSSE = 0;
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296
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297 // On new cpus instructions which update whole XMM register should be used
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298 // to prevent partial register stall due to dependencies on high half.
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299 //
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300 // UseXmmLoadAndClearUpper == true --> movsd(xmm, mem)
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301 // UseXmmLoadAndClearUpper == false --> movlpd(xmm, mem)
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302 // UseXmmRegToRegMoveAll == true --> movaps(xmm, xmm), movapd(xmm, xmm).
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303 // UseXmmRegToRegMoveAll == false --> movss(xmm, xmm), movsd(xmm, xmm).
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304
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305 if( is_amd() ) { // AMD cpus specific settings
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306 if( supports_sse2() && FLAG_IS_DEFAULT(UseAddressNop) ) {
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307 // Use it on new AMD cpus starting from Opteron.
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308 UseAddressNop = true;
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309 }
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310 if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) {
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311 if( supports_sse4a() ) {
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312 UseXmmLoadAndClearUpper = true; // use movsd only on '10h' Opteron
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313 } else {
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314 UseXmmLoadAndClearUpper = false;
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315 }
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316 }
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317 if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) {
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318 if( supports_sse4a() ) {
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319 UseXmmRegToRegMoveAll = true; // use movaps, movapd only on '10h'
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320 } else {
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321 UseXmmRegToRegMoveAll = false;
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322 }
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323 }
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71
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324 if( FLAG_IS_DEFAULT(UseXmmI2F) ) {
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325 if( supports_sse4a() ) {
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326 UseXmmI2F = true;
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327 } else {
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328 UseXmmI2F = false;
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329 }
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330 }
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331 if( FLAG_IS_DEFAULT(UseXmmI2D) ) {
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332 if( supports_sse4a() ) {
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333 UseXmmI2D = true;
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334 } else {
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335 UseXmmI2D = false;
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336 }
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337 }
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0
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338 }
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339
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340 if( is_intel() ) { // Intel cpus specific settings
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341 if( FLAG_IS_DEFAULT(UseStoreImmI16) ) {
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342 UseStoreImmI16 = false; // don't use it on Intel cpus
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343 }
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344 if( cpu_family() == 6 || cpu_family() == 15 ) {
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345 if( FLAG_IS_DEFAULT(UseAddressNop) ) {
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346 // Use it on all Intel cpus starting from PentiumPro
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347 UseAddressNop = true;
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348 }
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349 }
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350 if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) {
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351 UseXmmLoadAndClearUpper = true; // use movsd on all Intel cpus
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352 }
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353 if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) {
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354 if( supports_sse3() ) {
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355 UseXmmRegToRegMoveAll = true; // use movaps, movapd on new Intel cpus
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356 } else {
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357 UseXmmRegToRegMoveAll = false;
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358 }
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359 }
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360 if( cpu_family() == 6 && supports_sse3() ) { // New Intel cpus
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361 #ifdef COMPILER2
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362 if( FLAG_IS_DEFAULT(MaxLoopPad) ) {
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363 // For new Intel cpus do the next optimization:
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364 // don't align the beginning of a loop if there are enough instructions
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365 // left (NumberOfLoopInstrToAlign defined in c2_globals.hpp)
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366 // in current fetch line (OptoLoopAlignment) or the padding
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367 // is big (> MaxLoopPad).
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368 // Set MaxLoopPad to 11 for new Intel cpus to reduce number of
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369 // generated NOP instructions. 11 is the largest size of one
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370 // address NOP instruction '0F 1F' (see Assembler::nop(i)).
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371 MaxLoopPad = 11;
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372 }
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373 #endif // COMPILER2
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374 }
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375 }
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376
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377 assert(0 <= ReadPrefetchInstr && ReadPrefetchInstr <= 3, "invalid value");
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378 assert(0 <= AllocatePrefetchInstr && AllocatePrefetchInstr <= 3, "invalid value");
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379
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380 // set valid Prefetch instruction
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381 if( ReadPrefetchInstr < 0 ) ReadPrefetchInstr = 0;
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382 if( ReadPrefetchInstr > 3 ) ReadPrefetchInstr = 3;
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383 if( ReadPrefetchInstr == 3 && !supports_3dnow() ) ReadPrefetchInstr = 0;
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384 if( !supports_sse() && supports_3dnow() ) ReadPrefetchInstr = 3;
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385
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386 if( AllocatePrefetchInstr < 0 ) AllocatePrefetchInstr = 0;
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387 if( AllocatePrefetchInstr > 3 ) AllocatePrefetchInstr = 3;
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388 if( AllocatePrefetchInstr == 3 && !supports_3dnow() ) AllocatePrefetchInstr=0;
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389 if( !supports_sse() && supports_3dnow() ) AllocatePrefetchInstr = 3;
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390
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391 // Allocation prefetch settings
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392 intx cache_line_size = L1_data_cache_line_size();
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393 if( cache_line_size > AllocatePrefetchStepSize )
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394 AllocatePrefetchStepSize = cache_line_size;
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395 if( FLAG_IS_DEFAULT(AllocatePrefetchLines) )
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396 AllocatePrefetchLines = 3; // Optimistic value
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397 assert(AllocatePrefetchLines > 0, "invalid value");
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398 if( AllocatePrefetchLines < 1 ) // set valid value in product VM
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399 AllocatePrefetchLines = 1; // Conservative value
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400
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401 AllocatePrefetchDistance = allocate_prefetch_distance();
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402 AllocatePrefetchStyle = allocate_prefetch_style();
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403
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404 if( AllocatePrefetchStyle == 2 && is_intel() &&
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405 cpu_family() == 6 && supports_sse3() ) { // watermark prefetching on Core
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406 AllocatePrefetchDistance = 320;
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407 }
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408 assert(AllocatePrefetchDistance % AllocatePrefetchStepSize == 0, "invalid value");
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409
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410 #ifndef PRODUCT
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411 if (PrintMiscellaneous && Verbose) {
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412 tty->print_cr("Logical CPUs per package: %u",
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413 logical_processors_per_package());
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414 tty->print_cr("UseSSE=%d",UseSSE);
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415 tty->print("Allocation: ");
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416 if (AllocatePrefetchStyle <= 0 || UseSSE == 0 && !supports_3dnow()) {
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417 tty->print_cr("no prefetching");
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418 } else {
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419 if (UseSSE == 0 && supports_3dnow()) {
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420 tty->print("PREFETCHW");
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421 } else if (UseSSE >= 1) {
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422 if (AllocatePrefetchInstr == 0) {
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423 tty->print("PREFETCHNTA");
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424 } else if (AllocatePrefetchInstr == 1) {
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425 tty->print("PREFETCHT0");
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426 } else if (AllocatePrefetchInstr == 2) {
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427 tty->print("PREFETCHT2");
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428 } else if (AllocatePrefetchInstr == 3) {
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429 tty->print("PREFETCHW");
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430 }
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431 }
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432 if (AllocatePrefetchLines > 1) {
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433 tty->print_cr(" %d, %d lines with step %d bytes", AllocatePrefetchDistance, AllocatePrefetchLines, AllocatePrefetchStepSize);
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434 } else {
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435 tty->print_cr(" %d, one line", AllocatePrefetchDistance);
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436 }
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437 }
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438 }
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439 #endif // !PRODUCT
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440 }
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441
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442 void VM_Version::initialize() {
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443 ResourceMark rm;
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444 // Making this stub must be FIRST use of assembler
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445
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446 stub_blob = BufferBlob::create("getPsrInfo_stub", stub_size);
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447 if (stub_blob == NULL) {
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448 vm_exit_during_initialization("Unable to allocate getPsrInfo_stub");
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449 }
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450 CodeBuffer c(stub_blob->instructions_begin(),
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451 stub_blob->instructions_size());
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452 VM_Version_StubGenerator g(&c);
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453 getPsrInfo_stub = CAST_TO_FN_PTR(getPsrInfo_stub_t,
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454 g.generate_getPsrInfo());
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455
|
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456 get_processor_features();
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457 }
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