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1 /*
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196
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2 * Copyright 2003-2008 Sun Microsystems, Inc. All Rights Reserved.
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0
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3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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4 *
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5 * This code is free software; you can redistribute it and/or modify it
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6 * under the terms of the GNU General Public License version 2 only, as
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7 * published by the Free Software Foundation.
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8 *
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9 * This code is distributed in the hope that it will be useful, but WITHOUT
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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12 * version 2 for more details (a copy is included in the LICENSE file that
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13 * accompanied this code).
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14 *
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15 * You should have received a copy of the GNU General Public License version
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16 * 2 along with this work; if not, write to the Free Software Foundation,
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17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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18 *
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19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
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20 * CA 95054 USA or visit www.sun.com if you need additional information or
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21 * have any questions.
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22 *
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23 */
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24
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25 # include "incls/_precompiled.incl"
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26 # include "incls/_vm_version_x86_64.cpp.incl"
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27
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28 int VM_Version::_cpu;
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29 int VM_Version::_model;
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30 int VM_Version::_stepping;
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31 int VM_Version::_cpuFeatures;
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32 const char* VM_Version::_features_str = "";
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33 VM_Version::CpuidInfo VM_Version::_cpuid_info = { 0, };
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34
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35 static BufferBlob* stub_blob;
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36 static const int stub_size = 300;
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37
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38 extern "C" {
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39 typedef void (*getPsrInfo_stub_t)(void*);
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40 }
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41 static getPsrInfo_stub_t getPsrInfo_stub = NULL;
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42
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43
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44 class VM_Version_StubGenerator: public StubCodeGenerator {
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45 public:
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46
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47 VM_Version_StubGenerator(CodeBuffer *c) : StubCodeGenerator(c) {}
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48
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49 address generate_getPsrInfo() {
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50
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51 Label std_cpuid1, ext_cpuid1, ext_cpuid5, done;
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52
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53 StubCodeMark mark(this, "VM_Version", "getPsrInfo_stub");
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54 # define __ _masm->
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55
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56 address start = __ pc();
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57
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58 //
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59 // void getPsrInfo(VM_Version::CpuidInfo* cpuid_info);
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60 //
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61 // rcx and rdx are first and second argument registers on windows
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62
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63 __ pushq(rbp);
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64 __ movq(rbp, c_rarg0); // cpuid_info address
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65 __ pushq(rbx);
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66 __ pushq(rsi);
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67
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68 //
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69 // we have a chip which supports the "cpuid" instruction
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70 //
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71 __ xorl(rax, rax);
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72 __ cpuid();
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73 __ leaq(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset())));
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74 __ movl(Address(rsi, 0), rax);
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75 __ movl(Address(rsi, 4), rbx);
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76 __ movl(Address(rsi, 8), rcx);
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77 __ movl(Address(rsi,12), rdx);
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78
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79 __ cmpl(rax, 3); // Is cpuid(0x4) supported?
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80 __ jccb(Assembler::belowEqual, std_cpuid1);
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81
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82 //
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83 // cpuid(0x4) Deterministic cache params
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84 //
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85 __ movl(rax, 4);
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86 __ xorl(rcx, rcx); // L1 cache
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87 __ cpuid();
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88 __ pushq(rax);
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89 __ andl(rax, 0x1f); // Determine if valid cache parameters used
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90 __ orl(rax, rax); // eax[4:0] == 0 indicates invalid cache
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91 __ popq(rax);
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92 __ jccb(Assembler::equal, std_cpuid1);
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93
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94 __ leaq(rsi, Address(rbp, in_bytes(VM_Version::dcp_cpuid4_offset())));
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95 __ movl(Address(rsi, 0), rax);
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96 __ movl(Address(rsi, 4), rbx);
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97 __ movl(Address(rsi, 8), rcx);
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98 __ movl(Address(rsi,12), rdx);
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99
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100 //
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101 // Standard cpuid(0x1)
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102 //
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103 __ bind(std_cpuid1);
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104 __ movl(rax, 1);
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105 __ cpuid();
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106 __ leaq(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
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107 __ movl(Address(rsi, 0), rax);
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108 __ movl(Address(rsi, 4), rbx);
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109 __ movl(Address(rsi, 8), rcx);
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110 __ movl(Address(rsi,12), rdx);
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111
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112 __ movl(rax, 0x80000000);
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113 __ cpuid();
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114 __ cmpl(rax, 0x80000000); // Is cpuid(0x80000001) supported?
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115 __ jcc(Assembler::belowEqual, done);
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116 __ cmpl(rax, 0x80000004); // Is cpuid(0x80000005) supported?
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117 __ jccb(Assembler::belowEqual, ext_cpuid1);
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118 __ cmpl(rax, 0x80000007); // Is cpuid(0x80000008) supported?
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119 __ jccb(Assembler::belowEqual, ext_cpuid5);
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120 //
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121 // Extended cpuid(0x80000008)
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122 //
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123 __ movl(rax, 0x80000008);
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124 __ cpuid();
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125 __ leaq(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid8_offset())));
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126 __ movl(Address(rsi, 0), rax);
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127 __ movl(Address(rsi, 4), rbx);
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128 __ movl(Address(rsi, 8), rcx);
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129 __ movl(Address(rsi,12), rdx);
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130
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131 //
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132 // Extended cpuid(0x80000005)
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133 //
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134 __ bind(ext_cpuid5);
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135 __ movl(rax, 0x80000005);
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136 __ cpuid();
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137 __ leaq(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid5_offset())));
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138 __ movl(Address(rsi, 0), rax);
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139 __ movl(Address(rsi, 4), rbx);
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140 __ movl(Address(rsi, 8), rcx);
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141 __ movl(Address(rsi,12), rdx);
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142
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143 //
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144 // Extended cpuid(0x80000001)
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145 //
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146 __ bind(ext_cpuid1);
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147 __ movl(rax, 0x80000001);
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148 __ cpuid();
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149 __ leaq(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid1_offset())));
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150 __ movl(Address(rsi, 0), rax);
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151 __ movl(Address(rsi, 4), rbx);
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152 __ movl(Address(rsi, 8), rcx);
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153 __ movl(Address(rsi,12), rdx);
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154
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155 //
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156 // return
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157 //
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158 __ bind(done);
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159 __ popq(rsi);
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160 __ popq(rbx);
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161 __ popq(rbp);
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162 __ ret(0);
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163
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164 # undef __
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165
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166 return start;
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167 };
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168 };
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169
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170
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171 void VM_Version::get_processor_features() {
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172
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173 _logical_processors_per_package = 1;
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174 // Get raw processor info
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175 getPsrInfo_stub(&_cpuid_info);
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176 assert_is_initialized();
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177 _cpu = extended_cpu_family();
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178 _model = extended_cpu_model();
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179 _stepping = cpu_stepping();
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180 _cpuFeatures = feature_flags();
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181 // Logical processors are only available on P4s and above,
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182 // and only if hyperthreading is available.
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183 _logical_processors_per_package = logical_processor_count();
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184 _supports_cx8 = supports_cmpxchg8();
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185 // OS should support SSE for x64 and hardware should support at least SSE2.
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186 if (!VM_Version::supports_sse2()) {
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187 vm_exit_during_initialization("Unknown x64 processor: SSE2 not supported");
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188 }
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189 if (UseSSE < 4)
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190 _cpuFeatures &= ~CPU_SSE4;
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191 if (UseSSE < 3) {
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192 _cpuFeatures &= ~CPU_SSE3;
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193 _cpuFeatures &= ~CPU_SSSE3;
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194 _cpuFeatures &= ~CPU_SSE4A;
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195 }
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196 if (UseSSE < 2)
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197 _cpuFeatures &= ~CPU_SSE2;
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198 if (UseSSE < 1)
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199 _cpuFeatures &= ~CPU_SSE;
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200
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201 if (logical_processors_per_package() == 1) {
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202 // HT processor could be installed on a system which doesn't support HT.
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203 _cpuFeatures &= ~CPU_HT;
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204 }
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205
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206 char buf[256];
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207 jio_snprintf(buf, sizeof(buf), "(%u cores per cpu, %u threads per core) family %d model %d stepping %d%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
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208 cores_per_cpu(), threads_per_core(),
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209 cpu_family(), _model, _stepping,
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210 (supports_cmov() ? ", cmov" : ""),
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211 (supports_cmpxchg8() ? ", cx8" : ""),
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212 (supports_fxsr() ? ", fxsr" : ""),
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213 (supports_mmx() ? ", mmx" : ""),
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214 (supports_sse() ? ", sse" : ""),
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215 (supports_sse2() ? ", sse2" : ""),
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216 (supports_sse3() ? ", sse3" : ""),
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217 (supports_ssse3()? ", ssse3": ""),
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218 (supports_sse4() ? ", sse4" : ""),
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219 (supports_mmx_ext() ? ", mmxext" : ""),
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220 (supports_3dnow() ? ", 3dnow" : ""),
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221 (supports_3dnow2() ? ", 3dnowext" : ""),
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222 (supports_sse4a() ? ", sse4a": ""),
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223 (supports_ht() ? ", ht": ""));
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224 _features_str = strdup(buf);
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225
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226 // UseSSE is set to the smaller of what hardware supports and what
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227 // the command line requires. I.e., you cannot set UseSSE to 2 on
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228 // older Pentiums which do not support it.
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229 if( UseSSE > 4 ) UseSSE=4;
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230 if( UseSSE < 0 ) UseSSE=0;
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231 if( !supports_sse4() ) // Drop to 3 if no SSE4 support
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232 UseSSE = MIN2((intx)3,UseSSE);
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233 if( !supports_sse3() ) // Drop to 2 if no SSE3 support
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234 UseSSE = MIN2((intx)2,UseSSE);
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235 if( !supports_sse2() ) // Drop to 1 if no SSE2 support
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236 UseSSE = MIN2((intx)1,UseSSE);
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237 if( !supports_sse () ) // Drop to 0 if no SSE support
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238 UseSSE = 0;
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239
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240 // On new cpus instructions which update whole XMM register should be used
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241 // to prevent partial register stall due to dependencies on high half.
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242 //
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243 // UseXmmLoadAndClearUpper == true --> movsd(xmm, mem)
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244 // UseXmmLoadAndClearUpper == false --> movlpd(xmm, mem)
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245 // UseXmmRegToRegMoveAll == true --> movaps(xmm, xmm), movapd(xmm, xmm).
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246 // UseXmmRegToRegMoveAll == false --> movss(xmm, xmm), movsd(xmm, xmm).
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247
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248 if( is_amd() ) { // AMD cpus specific settings
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249 if( FLAG_IS_DEFAULT(UseAddressNop) ) {
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250 // Use it on all AMD cpus starting from Opteron (don't need
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251 // a cpu check since only Opteron and new cpus support 64-bits mode).
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252 UseAddressNop = true;
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253 }
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254 if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) {
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255 if( supports_sse4a() ) {
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256 UseXmmLoadAndClearUpper = true; // use movsd only on '10h' Opteron
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257 } else {
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258 UseXmmLoadAndClearUpper = false;
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259 }
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260 }
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261 if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) {
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262 if( supports_sse4a() ) {
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263 UseXmmRegToRegMoveAll = true; // use movaps, movapd only on '10h'
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264 } else {
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265 UseXmmRegToRegMoveAll = false;
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266 }
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267 }
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71
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268 if( FLAG_IS_DEFAULT(UseXmmI2F) ) {
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269 if( supports_sse4a() ) {
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270 UseXmmI2F = true;
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271 } else {
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272 UseXmmI2F = false;
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273 }
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274 }
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275 if( FLAG_IS_DEFAULT(UseXmmI2D) ) {
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276 if( supports_sse4a() ) {
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277 UseXmmI2D = true;
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278 } else {
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279 UseXmmI2D = false;
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280 }
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281 }
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0
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282 }
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283
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284 if( is_intel() ) { // Intel cpus specific settings
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285 if( FLAG_IS_DEFAULT(UseStoreImmI16) ) {
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286 UseStoreImmI16 = false; // don't use it on Intel cpus
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287 }
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288 if( FLAG_IS_DEFAULT(UseAddressNop) ) {
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289 // Use it on all Intel cpus starting from PentiumPro
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290 // (don't need a cpu check since only new cpus support 64-bits mode).
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291 UseAddressNop = true;
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292 }
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293 if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) {
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294 UseXmmLoadAndClearUpper = true; // use movsd on all Intel cpus
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295 }
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296 if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) {
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297 if( supports_sse3() ) {
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298 UseXmmRegToRegMoveAll = true; // use movaps, movapd on new Intel cpus
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299 } else {
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300 UseXmmRegToRegMoveAll = false;
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301 }
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302 }
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303 if( cpu_family() == 6 && supports_sse3() ) { // New Intel cpus
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304 #ifdef COMPILER2
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305 if( FLAG_IS_DEFAULT(MaxLoopPad) ) {
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306 // For new Intel cpus do the next optimization:
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307 // don't align the beginning of a loop if there are enough instructions
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308 // left (NumberOfLoopInstrToAlign defined in c2_globals.hpp)
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309 // in current fetch line (OptoLoopAlignment) or the padding
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310 // is big (> MaxLoopPad).
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311 // Set MaxLoopPad to 11 for new Intel cpus to reduce number of
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312 // generated NOP instructions. 11 is the largest size of one
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313 // address NOP instruction '0F 1F' (see Assembler::nop(i)).
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314 MaxLoopPad = 11;
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315 }
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316 #endif // COMPILER2
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317 }
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318 }
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319
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320 assert(0 <= ReadPrefetchInstr && ReadPrefetchInstr <= 3, "invalid value");
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321 assert(0 <= AllocatePrefetchInstr && AllocatePrefetchInstr <= 3, "invalid value");
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322
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323 // set valid Prefetch instruction
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324 if( ReadPrefetchInstr < 0 ) ReadPrefetchInstr = 0;
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325 if( ReadPrefetchInstr > 3 ) ReadPrefetchInstr = 3;
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326 if( ReadPrefetchInstr == 3 && !supports_3dnow() ) ReadPrefetchInstr = 0;
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327
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328 if( AllocatePrefetchInstr < 0 ) AllocatePrefetchInstr = 0;
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329 if( AllocatePrefetchInstr > 3 ) AllocatePrefetchInstr = 3;
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330 if( AllocatePrefetchInstr == 3 && !supports_3dnow() ) AllocatePrefetchInstr=0;
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331
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332 // Allocation prefetch settings
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333 intx cache_line_size = L1_data_cache_line_size();
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334 if( cache_line_size > AllocatePrefetchStepSize )
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335 AllocatePrefetchStepSize = cache_line_size;
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336 if( FLAG_IS_DEFAULT(AllocatePrefetchLines) )
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337 AllocatePrefetchLines = 3; // Optimistic value
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338 assert(AllocatePrefetchLines > 0, "invalid value");
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339 if( AllocatePrefetchLines < 1 ) // set valid value in product VM
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340 AllocatePrefetchLines = 1; // Conservative value
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341
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342 AllocatePrefetchDistance = allocate_prefetch_distance();
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343 AllocatePrefetchStyle = allocate_prefetch_style();
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344
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345 if( AllocatePrefetchStyle == 2 && is_intel() &&
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346 cpu_family() == 6 && supports_sse3() ) { // watermark prefetching on Core
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347 AllocatePrefetchDistance = 384;
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348 }
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349 assert(AllocatePrefetchDistance % AllocatePrefetchStepSize == 0, "invalid value");
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350
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351 // Prefetch settings
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352 PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes();
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353 PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes();
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354 PrefetchFieldsAhead = prefetch_fields_ahead();
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355
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356 #ifndef PRODUCT
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357 if (PrintMiscellaneous && Verbose) {
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358 tty->print_cr("Logical CPUs per package: %u",
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359 logical_processors_per_package());
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360 tty->print_cr("UseSSE=%d",UseSSE);
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361 tty->print("Allocation: ");
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362 if (AllocatePrefetchStyle <= 0) {
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363 tty->print_cr("no prefetching");
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364 } else {
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365 if (AllocatePrefetchInstr == 0) {
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366 tty->print("PREFETCHNTA");
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367 } else if (AllocatePrefetchInstr == 1) {
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368 tty->print("PREFETCHT0");
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369 } else if (AllocatePrefetchInstr == 2) {
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370 tty->print("PREFETCHT2");
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371 } else if (AllocatePrefetchInstr == 3) {
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372 tty->print("PREFETCHW");
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373 }
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374 if (AllocatePrefetchLines > 1) {
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375 tty->print_cr(" %d, %d lines with step %d bytes", AllocatePrefetchDistance, AllocatePrefetchLines, AllocatePrefetchStepSize);
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376 } else {
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377 tty->print_cr(" %d, one line", AllocatePrefetchDistance);
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378 }
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379 }
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380 if (PrefetchCopyIntervalInBytes > 0) {
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381 tty->print_cr("PrefetchCopyIntervalInBytes %d", PrefetchCopyIntervalInBytes);
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382 }
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383 if (PrefetchScanIntervalInBytes > 0) {
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384 tty->print_cr("PrefetchScanIntervalInBytes %d", PrefetchScanIntervalInBytes);
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385 }
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386 if (PrefetchFieldsAhead > 0) {
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387 tty->print_cr("PrefetchFieldsAhead %d", PrefetchFieldsAhead);
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388 }
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389 }
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390 #endif // !PRODUCT
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391 }
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392
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393 void VM_Version::initialize() {
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394 ResourceMark rm;
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395 // Making this stub must be FIRST use of assembler
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396
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397 stub_blob = BufferBlob::create("getPsrInfo_stub", stub_size);
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398 if (stub_blob == NULL) {
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399 vm_exit_during_initialization("Unable to allocate getPsrInfo_stub");
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400 }
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401 CodeBuffer c(stub_blob->instructions_begin(),
|
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402 stub_blob->instructions_size());
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403 VM_Version_StubGenerator g(&c);
|
|
|
404 getPsrInfo_stub = CAST_TO_FN_PTR(getPsrInfo_stub_t,
|
|
|
405 g.generate_getPsrInfo());
|
|
|
406
|
|
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407 get_processor_features();
|
|
|
408 }
|
